ixgbe: Use the instance of net_device_stats from net_device.
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/vmalloc.h>
36 #include <linux/uaccess.h>
37
38 #include "ixgbe.h"
39
40
41 #define IXGBE_ALL_RAR_ENTRIES 16
42
43 struct ixgbe_stats {
44         char stat_string[ETH_GSTRING_LEN];
45         int sizeof_stat;
46         int stat_offset;
47 };
48
49 #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
50                              offsetof(struct ixgbe_adapter, m)
51 #define IXGBE_NETDEV_STAT(m) sizeof(((struct net_device *)0)->m), \
52                              offsetof(struct net_device, m)
53 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
54         {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
55         {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
56         {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
57         {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
58         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
59         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
60         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
61         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
62         {"lsc_int", IXGBE_STAT(lsc_int)},
63         {"tx_busy", IXGBE_STAT(tx_busy)},
64         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
65         {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
66         {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
67         {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
68         {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
69         {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
70         {"broadcast", IXGBE_STAT(stats.bprc)},
71         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
72         {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
73         {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
74         {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
75         {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
76         {"hw_rsc_count", IXGBE_STAT(rsc_count)},
77         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
78         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
79         {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
80         {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
81         {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
82         {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
83         {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
84         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
85         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
86         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
87         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
88         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
89         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
90         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
91         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
92         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
93         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
94         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
95         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
96         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
97         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
98         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
99         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
100         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
101         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
102 #ifdef IXGBE_FCOE
103         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
104         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
105         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
106         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
107         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
108         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
109 #endif /* IXGBE_FCOE */
110 };
111
112 #define IXGBE_QUEUE_STATS_LEN \
113         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
114         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
115         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
116 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
117 #define IXGBE_PB_STATS_LEN ( \
118                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
119                  IXGBE_FLAG_DCB_ENABLED) ? \
120                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
121                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
122                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
123                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
124                   / sizeof(u64) : 0)
125 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
126                          IXGBE_PB_STATS_LEN + \
127                          IXGBE_QUEUE_STATS_LEN)
128
129 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
130         "Register test  (offline)", "Eeprom test    (offline)",
131         "Interrupt test (offline)", "Loopback test  (offline)",
132         "Link test   (on/offline)"
133 };
134 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
135
136 static int ixgbe_get_settings(struct net_device *netdev,
137                               struct ethtool_cmd *ecmd)
138 {
139         struct ixgbe_adapter *adapter = netdev_priv(netdev);
140         struct ixgbe_hw *hw = &adapter->hw;
141         u32 link_speed = 0;
142         bool link_up;
143
144         ecmd->supported = SUPPORTED_10000baseT_Full;
145         ecmd->autoneg = AUTONEG_ENABLE;
146         ecmd->transceiver = XCVR_EXTERNAL;
147         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
148             (hw->phy.multispeed_fiber)) {
149                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
150                                     SUPPORTED_Autoneg);
151
152                 ecmd->advertising = ADVERTISED_Autoneg;
153                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
154                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
155                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
156                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
157                 /*
158                  * It's possible that phy.autoneg_advertised may not be
159                  * set yet.  If so display what the default would be -
160                  * both 1G and 10G supported.
161                  */
162                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
163                                            ADVERTISED_10000baseT_Full)))
164                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
165                                               ADVERTISED_1000baseT_Full);
166
167                 if (hw->phy.media_type == ixgbe_media_type_copper) {
168                         ecmd->supported |= SUPPORTED_TP;
169                         ecmd->advertising |= ADVERTISED_TP;
170                         ecmd->port = PORT_TP;
171                 } else {
172                         ecmd->supported |= SUPPORTED_FIBRE;
173                         ecmd->advertising |= ADVERTISED_FIBRE;
174                         ecmd->port = PORT_FIBRE;
175                 }
176         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
177                 /* Set as FIBRE until SERDES defined in kernel */
178                 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
179                         ecmd->supported = (SUPPORTED_1000baseT_Full |
180                                            SUPPORTED_FIBRE);
181                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
182                                              ADVERTISED_FIBRE);
183                         ecmd->port = PORT_FIBRE;
184                         ecmd->autoneg = AUTONEG_DISABLE;
185                 } else {
186                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
187                                             SUPPORTED_FIBRE);
188                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
189                                              ADVERTISED_1000baseT_Full |
190                                              ADVERTISED_FIBRE);
191                         ecmd->port = PORT_FIBRE;
192                 }
193         } else {
194                 ecmd->supported |= SUPPORTED_FIBRE;
195                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
196                                      ADVERTISED_FIBRE);
197                 ecmd->port = PORT_FIBRE;
198                 ecmd->autoneg = AUTONEG_DISABLE;
199         }
200
201         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
202         if (link_up) {
203                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
204                                SPEED_10000 : SPEED_1000;
205                 ecmd->duplex = DUPLEX_FULL;
206         } else {
207                 ecmd->speed = -1;
208                 ecmd->duplex = -1;
209         }
210
211         return 0;
212 }
213
214 static int ixgbe_set_settings(struct net_device *netdev,
215                               struct ethtool_cmd *ecmd)
216 {
217         struct ixgbe_adapter *adapter = netdev_priv(netdev);
218         struct ixgbe_hw *hw = &adapter->hw;
219         u32 advertised, old;
220         s32 err = 0;
221
222         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
223             (hw->phy.multispeed_fiber)) {
224                 /* 10000/copper and 1000/copper must autoneg
225                  * this function does not support any duplex forcing, but can
226                  * limit the advertising of the adapter to only 10000 or 1000 */
227                 if (ecmd->autoneg == AUTONEG_DISABLE)
228                         return -EINVAL;
229
230                 old = hw->phy.autoneg_advertised;
231                 advertised = 0;
232                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
233                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
234
235                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
236                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
237
238                 if (old == advertised)
239                         return err;
240                 /* this sets the link speed and restarts auto-neg */
241                 hw->mac.autotry_restart = true;
242                 err = hw->mac.ops.setup_link(hw, advertised, true, true);
243                 if (err) {
244                         DPRINTK(PROBE, INFO,
245                                 "setup link failed with code %d\n", err);
246                         hw->mac.ops.setup_link(hw, old, true, true);
247                 }
248         } else {
249                 /* in this case we currently only support 10Gb/FULL */
250                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
251                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
252                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
253                         return -EINVAL;
254         }
255
256         return err;
257 }
258
259 static void ixgbe_get_pauseparam(struct net_device *netdev,
260                                  struct ethtool_pauseparam *pause)
261 {
262         struct ixgbe_adapter *adapter = netdev_priv(netdev);
263         struct ixgbe_hw *hw = &adapter->hw;
264
265         /*
266          * Flow Control Autoneg isn't on if
267          *  - we didn't ask for it OR
268          *  - it failed, we know this by tx & rx being off
269          */
270         if (hw->fc.disable_fc_autoneg ||
271             (hw->fc.current_mode == ixgbe_fc_none))
272                 pause->autoneg = 0;
273         else
274                 pause->autoneg = 1;
275
276 #ifdef CONFIG_DCB
277         if (hw->fc.current_mode == ixgbe_fc_pfc) {
278                 pause->rx_pause = 0;
279                 pause->tx_pause = 0;
280         }
281
282 #endif
283         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
284                 pause->rx_pause = 1;
285         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
286                 pause->tx_pause = 1;
287         } else if (hw->fc.current_mode == ixgbe_fc_full) {
288                 pause->rx_pause = 1;
289                 pause->tx_pause = 1;
290         }
291 }
292
293 static int ixgbe_set_pauseparam(struct net_device *netdev,
294                                 struct ethtool_pauseparam *pause)
295 {
296         struct ixgbe_adapter *adapter = netdev_priv(netdev);
297         struct ixgbe_hw *hw = &adapter->hw;
298         struct ixgbe_fc_info fc;
299
300 #ifdef CONFIG_DCB
301         if (adapter->dcb_cfg.pfc_mode_enable ||
302                 ((hw->mac.type == ixgbe_mac_82598EB) &&
303                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
304                 return -EINVAL;
305
306 #endif
307
308         fc = hw->fc;
309
310         if (pause->autoneg != AUTONEG_ENABLE)
311                 fc.disable_fc_autoneg = true;
312         else
313                 fc.disable_fc_autoneg = false;
314
315         if (pause->rx_pause && pause->tx_pause)
316                 fc.requested_mode = ixgbe_fc_full;
317         else if (pause->rx_pause && !pause->tx_pause)
318                 fc.requested_mode = ixgbe_fc_rx_pause;
319         else if (!pause->rx_pause && pause->tx_pause)
320                 fc.requested_mode = ixgbe_fc_tx_pause;
321         else if (!pause->rx_pause && !pause->tx_pause)
322                 fc.requested_mode = ixgbe_fc_none;
323         else
324                 return -EINVAL;
325
326 #ifdef CONFIG_DCB
327         adapter->last_lfc_mode = fc.requested_mode;
328 #endif
329
330         /* if the thing changed then we'll update and use new autoneg */
331         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
332                 hw->fc = fc;
333                 if (netif_running(netdev))
334                         ixgbe_reinit_locked(adapter);
335                 else
336                         ixgbe_reset(adapter);
337         }
338
339         return 0;
340 }
341
342 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
343 {
344         struct ixgbe_adapter *adapter = netdev_priv(netdev);
345         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
346 }
347
348 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
349 {
350         struct ixgbe_adapter *adapter = netdev_priv(netdev);
351         if (data)
352                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
353         else
354                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
355
356         if (netif_running(netdev))
357                 ixgbe_reinit_locked(adapter);
358         else
359                 ixgbe_reset(adapter);
360
361         return 0;
362 }
363
364 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
365 {
366         return (netdev->features & NETIF_F_IP_CSUM) != 0;
367 }
368
369 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
370 {
371         struct ixgbe_adapter *adapter = netdev_priv(netdev);
372
373         if (data) {
374                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
375                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
376                         netdev->features |= NETIF_F_SCTP_CSUM;
377         } else {
378                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
379                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
380                         netdev->features &= ~NETIF_F_SCTP_CSUM;
381         }
382
383         return 0;
384 }
385
386 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
387 {
388         if (data) {
389                 netdev->features |= NETIF_F_TSO;
390                 netdev->features |= NETIF_F_TSO6;
391         } else {
392                 netif_tx_stop_all_queues(netdev);
393                 netdev->features &= ~NETIF_F_TSO;
394                 netdev->features &= ~NETIF_F_TSO6;
395                 netif_tx_start_all_queues(netdev);
396         }
397         return 0;
398 }
399
400 static u32 ixgbe_get_msglevel(struct net_device *netdev)
401 {
402         struct ixgbe_adapter *adapter = netdev_priv(netdev);
403         return adapter->msg_enable;
404 }
405
406 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
407 {
408         struct ixgbe_adapter *adapter = netdev_priv(netdev);
409         adapter->msg_enable = data;
410 }
411
412 static int ixgbe_get_regs_len(struct net_device *netdev)
413 {
414 #define IXGBE_REGS_LEN  1128
415         return IXGBE_REGS_LEN * sizeof(u32);
416 }
417
418 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
419
420 static void ixgbe_get_regs(struct net_device *netdev,
421                            struct ethtool_regs *regs, void *p)
422 {
423         struct ixgbe_adapter *adapter = netdev_priv(netdev);
424         struct ixgbe_hw *hw = &adapter->hw;
425         u32 *regs_buff = p;
426         u8 i;
427
428         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
429
430         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
431
432         /* General Registers */
433         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
434         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
435         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
436         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
437         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
438         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
439         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
440         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
441
442         /* NVM Register */
443         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
444         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
445         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
446         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
447         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
448         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
449         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
450         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
451         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
452         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
453
454         /* Interrupt */
455         /* don't read EICR because it can clear interrupt causes, instead
456          * read EICS which is a shadow but doesn't clear EICR */
457         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
458         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
459         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
460         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
461         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
462         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
463         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
464         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
465         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
466         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
467         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
468         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
469
470         /* Flow Control */
471         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
472         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
473         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
474         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
475         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
476         for (i = 0; i < 8; i++)
477                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
478         for (i = 0; i < 8; i++)
479                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
480         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
481         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
482
483         /* Receive DMA */
484         for (i = 0; i < 64; i++)
485                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
486         for (i = 0; i < 64; i++)
487                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488         for (i = 0; i < 64; i++)
489                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
490         for (i = 0; i < 64; i++)
491                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
492         for (i = 0; i < 64; i++)
493                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
494         for (i = 0; i < 64; i++)
495                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
496         for (i = 0; i < 16; i++)
497                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
498         for (i = 0; i < 16; i++)
499                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
500         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
501         for (i = 0; i < 8; i++)
502                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
503         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
504         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
505
506         /* Receive */
507         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
508         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
509         for (i = 0; i < 16; i++)
510                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
511         for (i = 0; i < 16; i++)
512                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
513         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
514         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
515         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
516         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
517         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
518         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
519         for (i = 0; i < 8; i++)
520                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
521         for (i = 0; i < 8; i++)
522                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
523         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
524
525         /* Transmit */
526         for (i = 0; i < 32; i++)
527                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
528         for (i = 0; i < 32; i++)
529                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
530         for (i = 0; i < 32; i++)
531                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
532         for (i = 0; i < 32; i++)
533                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
534         for (i = 0; i < 32; i++)
535                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
536         for (i = 0; i < 32; i++)
537                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
538         for (i = 0; i < 32; i++)
539                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
540         for (i = 0; i < 32; i++)
541                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
542         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
543         for (i = 0; i < 16; i++)
544                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
545         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
546         for (i = 0; i < 8; i++)
547                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
548         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
549
550         /* Wake Up */
551         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
552         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
553         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
554         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
555         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
556         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
557         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
558         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
559         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
560
561         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
562         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
563         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
564         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
565         for (i = 0; i < 8; i++)
566                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
567         for (i = 0; i < 8; i++)
568                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
569         for (i = 0; i < 8; i++)
570                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
571         for (i = 0; i < 8; i++)
572                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
573         for (i = 0; i < 8; i++)
574                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
575         for (i = 0; i < 8; i++)
576                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
577
578         /* Statistics */
579         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
580         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
581         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
582         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
583         for (i = 0; i < 8; i++)
584                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
585         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
586         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
587         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
588         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
589         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
590         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
591         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
592         for (i = 0; i < 8; i++)
593                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
594         for (i = 0; i < 8; i++)
595                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
596         for (i = 0; i < 8; i++)
597                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
598         for (i = 0; i < 8; i++)
599                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
600         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
601         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
602         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
603         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
604         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
605         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
606         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
607         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
608         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
609         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
610         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
611         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
612         for (i = 0; i < 8; i++)
613                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
614         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
615         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
616         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
617         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
618         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
619         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
620         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
621         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
622         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
623         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
624         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
625         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
626         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
627         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
628         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
629         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
630         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
631         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
632         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
633         for (i = 0; i < 16; i++)
634                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
635         for (i = 0; i < 16; i++)
636                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
637         for (i = 0; i < 16; i++)
638                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
639         for (i = 0; i < 16; i++)
640                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
641
642         /* MAC */
643         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
644         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
645         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
646         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
647         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
648         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
649         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
650         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
651         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
652         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
653         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
654         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
655         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
656         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
657         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
658         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
659         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
660         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
661         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
662         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
663         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
664         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
665         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
666         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
667         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
668         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
669         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
670         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
671         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
672         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
673         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
674         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
675         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
676
677         /* Diagnostic */
678         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
679         for (i = 0; i < 8; i++)
680                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
681         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
682         for (i = 0; i < 4; i++)
683                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
684         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
685         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
686         for (i = 0; i < 8; i++)
687                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
688         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
689         for (i = 0; i < 4; i++)
690                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
691         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
692         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
693         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
694         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
695         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
696         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
697         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
698         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
699         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
700         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
701         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
702         for (i = 0; i < 8; i++)
703                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
704         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
705         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
706         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
707         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
708         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
709         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
710         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
711         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
712         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
713 }
714
715 static int ixgbe_get_eeprom_len(struct net_device *netdev)
716 {
717         struct ixgbe_adapter *adapter = netdev_priv(netdev);
718         return adapter->hw.eeprom.word_size * 2;
719 }
720
721 static int ixgbe_get_eeprom(struct net_device *netdev,
722                             struct ethtool_eeprom *eeprom, u8 *bytes)
723 {
724         struct ixgbe_adapter *adapter = netdev_priv(netdev);
725         struct ixgbe_hw *hw = &adapter->hw;
726         u16 *eeprom_buff;
727         int first_word, last_word, eeprom_len;
728         int ret_val = 0;
729         u16 i;
730
731         if (eeprom->len == 0)
732                 return -EINVAL;
733
734         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
735
736         first_word = eeprom->offset >> 1;
737         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
738         eeprom_len = last_word - first_word + 1;
739
740         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
741         if (!eeprom_buff)
742                 return -ENOMEM;
743
744         for (i = 0; i < eeprom_len; i++) {
745                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
746                     &eeprom_buff[i])))
747                         break;
748         }
749
750         /* Device's eeprom is always little-endian, word addressable */
751         for (i = 0; i < eeprom_len; i++)
752                 le16_to_cpus(&eeprom_buff[i]);
753
754         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
755         kfree(eeprom_buff);
756
757         return ret_val;
758 }
759
760 static void ixgbe_get_drvinfo(struct net_device *netdev,
761                               struct ethtool_drvinfo *drvinfo)
762 {
763         struct ixgbe_adapter *adapter = netdev_priv(netdev);
764         char firmware_version[32];
765
766         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
767         strncpy(drvinfo->version, ixgbe_driver_version, 32);
768
769         sprintf(firmware_version, "%d.%d-%d",
770                 (adapter->eeprom_version & 0xF000) >> 12,
771                 (adapter->eeprom_version & 0x0FF0) >> 4,
772                 adapter->eeprom_version & 0x000F);
773
774         strncpy(drvinfo->fw_version, firmware_version, 32);
775         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
776         drvinfo->n_stats = IXGBE_STATS_LEN;
777         drvinfo->testinfo_len = IXGBE_TEST_LEN;
778         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
779 }
780
781 static void ixgbe_get_ringparam(struct net_device *netdev,
782                                 struct ethtool_ringparam *ring)
783 {
784         struct ixgbe_adapter *adapter = netdev_priv(netdev);
785         struct ixgbe_ring *tx_ring = adapter->tx_ring;
786         struct ixgbe_ring *rx_ring = adapter->rx_ring;
787
788         ring->rx_max_pending = IXGBE_MAX_RXD;
789         ring->tx_max_pending = IXGBE_MAX_TXD;
790         ring->rx_mini_max_pending = 0;
791         ring->rx_jumbo_max_pending = 0;
792         ring->rx_pending = rx_ring->count;
793         ring->tx_pending = tx_ring->count;
794         ring->rx_mini_pending = 0;
795         ring->rx_jumbo_pending = 0;
796 }
797
798 static int ixgbe_set_ringparam(struct net_device *netdev,
799                                struct ethtool_ringparam *ring)
800 {
801         struct ixgbe_adapter *adapter = netdev_priv(netdev);
802         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
803         int i, err;
804         u32 new_rx_count, new_tx_count;
805         bool need_update = false;
806
807         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
808                 return -EINVAL;
809
810         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
811         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
812         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
813
814         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
815         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
816         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
817
818         if ((new_tx_count == adapter->tx_ring->count) &&
819             (new_rx_count == adapter->rx_ring->count)) {
820                 /* nothing to do */
821                 return 0;
822         }
823
824         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
825                 msleep(1);
826
827         temp_tx_ring = kcalloc(adapter->num_tx_queues,
828                                sizeof(struct ixgbe_ring), GFP_KERNEL);
829         if (!temp_tx_ring) {
830                 err = -ENOMEM;
831                 goto err_setup;
832         }
833
834         if (new_tx_count != adapter->tx_ring_count) {
835                 memcpy(temp_tx_ring, adapter->tx_ring,
836                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
837                 for (i = 0; i < adapter->num_tx_queues; i++) {
838                         temp_tx_ring[i].count = new_tx_count;
839                         err = ixgbe_setup_tx_resources(adapter,
840                                                        &temp_tx_ring[i]);
841                         if (err) {
842                                 while (i) {
843                                         i--;
844                                         ixgbe_free_tx_resources(adapter,
845                                                                 &temp_tx_ring[i]);
846                                 }
847                                 goto err_setup;
848                         }
849                 }
850                 need_update = true;
851         }
852
853         temp_rx_ring = kcalloc(adapter->num_rx_queues,
854                                sizeof(struct ixgbe_ring), GFP_KERNEL);
855         if ((!temp_rx_ring) && (need_update)) {
856                 for (i = 0; i < adapter->num_tx_queues; i++)
857                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
858                 kfree(temp_tx_ring);
859                 err = -ENOMEM;
860                 goto err_setup;
861         }
862
863         if (new_rx_count != adapter->rx_ring_count) {
864                 memcpy(temp_rx_ring, adapter->rx_ring,
865                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
866                 for (i = 0; i < adapter->num_rx_queues; i++) {
867                         temp_rx_ring[i].count = new_rx_count;
868                         err = ixgbe_setup_rx_resources(adapter,
869                                                        &temp_rx_ring[i]);
870                         if (err) {
871                                 while (i) {
872                                         i--;
873                                         ixgbe_free_rx_resources(adapter,
874                                                               &temp_rx_ring[i]);
875                                 }
876                                 goto err_setup;
877                         }
878                 }
879                 need_update = true;
880         }
881
882         /* if rings need to be updated, here's the place to do it in one shot */
883         if (need_update) {
884                 if (netif_running(netdev))
885                         ixgbe_down(adapter);
886
887                 /* tx */
888                 if (new_tx_count != adapter->tx_ring_count) {
889                         kfree(adapter->tx_ring);
890                         adapter->tx_ring = temp_tx_ring;
891                         temp_tx_ring = NULL;
892                         adapter->tx_ring_count = new_tx_count;
893                 }
894
895                 /* rx */
896                 if (new_rx_count != adapter->rx_ring_count) {
897                         kfree(adapter->rx_ring);
898                         adapter->rx_ring = temp_rx_ring;
899                         temp_rx_ring = NULL;
900                         adapter->rx_ring_count = new_rx_count;
901                 }
902         }
903
904         /* success! */
905         err = 0;
906         if (netif_running(netdev))
907                 ixgbe_up(adapter);
908
909 err_setup:
910         clear_bit(__IXGBE_RESETTING, &adapter->state);
911         return err;
912 }
913
914 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
915 {
916         switch (sset) {
917         case ETH_SS_TEST:
918                 return IXGBE_TEST_LEN;
919         case ETH_SS_STATS:
920                 return IXGBE_STATS_LEN;
921         default:
922                 return -EOPNOTSUPP;
923         }
924 }
925
926 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
927                                     struct ethtool_stats *stats, u64 *data)
928 {
929         struct ixgbe_adapter *adapter = netdev_priv(netdev);
930         u64 *queue_stat;
931         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
932         int j, k;
933         int i;
934
935         ixgbe_update_stats(adapter);
936         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
937                 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
938                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
939                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
940         }
941         for (j = 0; j < adapter->num_tx_queues; j++) {
942                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
943                 for (k = 0; k < stat_count; k++)
944                         data[i + k] = queue_stat[k];
945                 i += k;
946         }
947         for (j = 0; j < adapter->num_rx_queues; j++) {
948                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
949                 for (k = 0; k < stat_count; k++)
950                         data[i + k] = queue_stat[k];
951                 i += k;
952         }
953         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
954                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
955                         data[i++] = adapter->stats.pxontxc[j];
956                         data[i++] = adapter->stats.pxofftxc[j];
957                 }
958                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
959                         data[i++] = adapter->stats.pxonrxc[j];
960                         data[i++] = adapter->stats.pxoffrxc[j];
961                 }
962         }
963 }
964
965 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
966                               u8 *data)
967 {
968         struct ixgbe_adapter *adapter = netdev_priv(netdev);
969         char *p = (char *)data;
970         int i;
971
972         switch (stringset) {
973         case ETH_SS_TEST:
974                 memcpy(data, *ixgbe_gstrings_test,
975                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
976                 break;
977         case ETH_SS_STATS:
978                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
979                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
980                                ETH_GSTRING_LEN);
981                         p += ETH_GSTRING_LEN;
982                 }
983                 for (i = 0; i < adapter->num_tx_queues; i++) {
984                         sprintf(p, "tx_queue_%u_packets", i);
985                         p += ETH_GSTRING_LEN;
986                         sprintf(p, "tx_queue_%u_bytes", i);
987                         p += ETH_GSTRING_LEN;
988                 }
989                 for (i = 0; i < adapter->num_rx_queues; i++) {
990                         sprintf(p, "rx_queue_%u_packets", i);
991                         p += ETH_GSTRING_LEN;
992                         sprintf(p, "rx_queue_%u_bytes", i);
993                         p += ETH_GSTRING_LEN;
994                 }
995                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
996                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
997                                 sprintf(p, "tx_pb_%u_pxon", i);
998                                 p += ETH_GSTRING_LEN;
999                                 sprintf(p, "tx_pb_%u_pxoff", i);
1000                                 p += ETH_GSTRING_LEN;
1001                         }
1002                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1003                                 sprintf(p, "rx_pb_%u_pxon", i);
1004                                 p += ETH_GSTRING_LEN;
1005                                 sprintf(p, "rx_pb_%u_pxoff", i);
1006                                 p += ETH_GSTRING_LEN;
1007                         }
1008                 }
1009                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1010                 break;
1011         }
1012 }
1013
1014 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1015 {
1016         struct ixgbe_hw *hw = &adapter->hw;
1017         bool link_up;
1018         u32 link_speed = 0;
1019         *data = 0;
1020
1021         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1022         if (link_up)
1023                 return *data;
1024         else
1025                 *data = 1;
1026         return *data;
1027 }
1028
1029 /* ethtool register test data */
1030 struct ixgbe_reg_test {
1031         u16 reg;
1032         u8  array_len;
1033         u8  test_type;
1034         u32 mask;
1035         u32 write;
1036 };
1037
1038 /* In the hardware, registers are laid out either singly, in arrays
1039  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1040  * most tests take place on arrays or single registers (handled
1041  * as a single-element array) and special-case the tables.
1042  * Table tests are always pattern tests.
1043  *
1044  * We also make provision for some required setup steps by specifying
1045  * registers to be written without any read-back testing.
1046  */
1047
1048 #define PATTERN_TEST    1
1049 #define SET_READ_TEST   2
1050 #define WRITE_NO_TEST   3
1051 #define TABLE32_TEST    4
1052 #define TABLE64_TEST_LO 5
1053 #define TABLE64_TEST_HI 6
1054
1055 /* default 82599 register test */
1056 static struct ixgbe_reg_test reg_test_82599[] = {
1057         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1058         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1059         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1060         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1061         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1062         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1063         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1064         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1065         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1066         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1067         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1068         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1069         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1070         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1071         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1072         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1073         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1074         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1075         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1076         { 0, 0, 0, 0 }
1077 };
1078
1079 /* default 82598 register test */
1080 static struct ixgbe_reg_test reg_test_82598[] = {
1081         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1082         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1083         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1084         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1085         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1086         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1087         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1088         /* Enable all four RX queues before testing. */
1089         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1090         /* RDH is read-only for 82598, only test RDT. */
1091         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1092         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1093         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1094         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1095         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1096         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1097         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1099         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1100         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1101         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1102         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1103         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1104         { 0, 0, 0, 0 }
1105 };
1106
1107 #define REG_PATTERN_TEST(R, M, W)                                             \
1108 {                                                                             \
1109         u32 pat, val, before;                                                 \
1110         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1111         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1112                 before = readl(adapter->hw.hw_addr + R);                      \
1113                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1114                 val = readl(adapter->hw.hw_addr + R);                         \
1115                 if (val != (_test[pat] & W & M)) {                            \
1116                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1117                                           "0x%08X expected 0x%08X\n",         \
1118                                 R, val, (_test[pat] & W & M));                \
1119                         *data = R;                                            \
1120                         writel(before, adapter->hw.hw_addr + R);              \
1121                         return 1;                                             \
1122                 }                                                             \
1123                 writel(before, adapter->hw.hw_addr + R);                      \
1124         }                                                                     \
1125 }
1126
1127 #define REG_SET_AND_CHECK(R, M, W)                                            \
1128 {                                                                             \
1129         u32 val, before;                                                      \
1130         before = readl(adapter->hw.hw_addr + R);                              \
1131         writel((W & M), (adapter->hw.hw_addr + R));                           \
1132         val = readl(adapter->hw.hw_addr + R);                                 \
1133         if ((W & M) != (val & M)) {                                           \
1134                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1135                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1136                 *data = R;                                                    \
1137                 writel(before, (adapter->hw.hw_addr + R));                    \
1138                 return 1;                                                     \
1139         }                                                                     \
1140         writel(before, (adapter->hw.hw_addr + R));                            \
1141 }
1142
1143 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1144 {
1145         struct ixgbe_reg_test *test;
1146         u32 value, before, after;
1147         u32 i, toggle;
1148
1149         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1150                 toggle = 0x7FFFF30F;
1151                 test = reg_test_82599;
1152         } else {
1153                 toggle = 0x7FFFF3FF;
1154                 test = reg_test_82598;
1155         }
1156
1157         /*
1158          * Because the status register is such a special case,
1159          * we handle it separately from the rest of the register
1160          * tests.  Some bits are read-only, some toggle, and some
1161          * are writeable on newer MACs.
1162          */
1163         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1164         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1165         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1166         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1167         if (value != after) {
1168                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1169                         "0x%08X expected: 0x%08X\n", after, value);
1170                 *data = 1;
1171                 return 1;
1172         }
1173         /* restore previous status */
1174         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1175
1176         /*
1177          * Perform the remainder of the register test, looping through
1178          * the test table until we either fail or reach the null entry.
1179          */
1180         while (test->reg) {
1181                 for (i = 0; i < test->array_len; i++) {
1182                         switch (test->test_type) {
1183                         case PATTERN_TEST:
1184                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1185                                                 test->mask,
1186                                                 test->write);
1187                                 break;
1188                         case SET_READ_TEST:
1189                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1190                                                 test->mask,
1191                                                 test->write);
1192                                 break;
1193                         case WRITE_NO_TEST:
1194                                 writel(test->write,
1195                                        (adapter->hw.hw_addr + test->reg)
1196                                        + (i * 0x40));
1197                                 break;
1198                         case TABLE32_TEST:
1199                                 REG_PATTERN_TEST(test->reg + (i * 4),
1200                                                 test->mask,
1201                                                 test->write);
1202                                 break;
1203                         case TABLE64_TEST_LO:
1204                                 REG_PATTERN_TEST(test->reg + (i * 8),
1205                                                 test->mask,
1206                                                 test->write);
1207                                 break;
1208                         case TABLE64_TEST_HI:
1209                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1210                                                 test->mask,
1211                                                 test->write);
1212                                 break;
1213                         }
1214                 }
1215                 test++;
1216         }
1217
1218         *data = 0;
1219         return 0;
1220 }
1221
1222 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1223 {
1224         struct ixgbe_hw *hw = &adapter->hw;
1225         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1226                 *data = 1;
1227         else
1228                 *data = 0;
1229         return *data;
1230 }
1231
1232 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1233 {
1234         struct net_device *netdev = (struct net_device *) data;
1235         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1236
1237         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1238
1239         return IRQ_HANDLED;
1240 }
1241
1242 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1243 {
1244         struct net_device *netdev = adapter->netdev;
1245         u32 mask, i = 0, shared_int = true;
1246         u32 irq = adapter->pdev->irq;
1247
1248         *data = 0;
1249
1250         /* Hook up test interrupt handler just for this test */
1251         if (adapter->msix_entries) {
1252                 /* NOTE: we don't test MSI-X interrupts here, yet */
1253                 return 0;
1254         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1255                 shared_int = false;
1256                 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1257                                 netdev)) {
1258                         *data = 1;
1259                         return -1;
1260                 }
1261         } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1262                                 netdev->name, netdev)) {
1263                 shared_int = false;
1264         } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1265                                netdev->name, netdev)) {
1266                 *data = 1;
1267                 return -1;
1268         }
1269         DPRINTK(HW, INFO, "testing %s interrupt\n",
1270                 (shared_int ? "shared" : "unshared"));
1271
1272         /* Disable all the interrupts */
1273         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1274         msleep(10);
1275
1276         /* Test each interrupt */
1277         for (; i < 10; i++) {
1278                 /* Interrupt to test */
1279                 mask = 1 << i;
1280
1281                 if (!shared_int) {
1282                         /*
1283                          * Disable the interrupts to be reported in
1284                          * the cause register and then force the same
1285                          * interrupt and see if one gets posted.  If
1286                          * an interrupt was posted to the bus, the
1287                          * test failed.
1288                          */
1289                         adapter->test_icr = 0;
1290                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1291                                         ~mask & 0x00007FFF);
1292                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1293                                         ~mask & 0x00007FFF);
1294                         msleep(10);
1295
1296                         if (adapter->test_icr & mask) {
1297                                 *data = 3;
1298                                 break;
1299                         }
1300                 }
1301
1302                 /*
1303                  * Enable the interrupt to be reported in the cause
1304                  * register and then force the same interrupt and see
1305                  * if one gets posted.  If an interrupt was not posted
1306                  * to the bus, the test failed.
1307                  */
1308                 adapter->test_icr = 0;
1309                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1310                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1311                 msleep(10);
1312
1313                 if (!(adapter->test_icr &mask)) {
1314                         *data = 4;
1315                         break;
1316                 }
1317
1318                 if (!shared_int) {
1319                         /*
1320                          * Disable the other interrupts to be reported in
1321                          * the cause register and then force the other
1322                          * interrupts and see if any get posted.  If
1323                          * an interrupt was posted to the bus, the
1324                          * test failed.
1325                          */
1326                         adapter->test_icr = 0;
1327                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1328                                         ~mask & 0x00007FFF);
1329                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1330                                         ~mask & 0x00007FFF);
1331                         msleep(10);
1332
1333                         if (adapter->test_icr) {
1334                                 *data = 5;
1335                                 break;
1336                         }
1337                 }
1338         }
1339
1340         /* Disable all the interrupts */
1341         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1342         msleep(10);
1343
1344         /* Unhook test interrupt handler */
1345         free_irq(irq, netdev);
1346
1347         return *data;
1348 }
1349
1350 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1351 {
1352         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1353         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1354         struct ixgbe_hw *hw = &adapter->hw;
1355         struct pci_dev *pdev = adapter->pdev;
1356         u32 reg_ctl;
1357         int i;
1358
1359         /* shut down the DMA engines now so they can be reinitialized later */
1360
1361         /* first Rx */
1362         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1363         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1364         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1365         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1366         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1367         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1368
1369         /* now Tx */
1370         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1371         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1372         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1373         if (hw->mac.type == ixgbe_mac_82599EB) {
1374                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1375                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1376                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1377         }
1378
1379         ixgbe_reset(adapter);
1380
1381         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1382                 for (i = 0; i < tx_ring->count; i++) {
1383                         struct ixgbe_tx_buffer *buf =
1384                                         &(tx_ring->tx_buffer_info[i]);
1385                         if (buf->dma)
1386                                 pci_unmap_single(pdev, buf->dma, buf->length,
1387                                                  PCI_DMA_TODEVICE);
1388                         if (buf->skb)
1389                                 dev_kfree_skb(buf->skb);
1390                 }
1391         }
1392
1393         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1394                 for (i = 0; i < rx_ring->count; i++) {
1395                         struct ixgbe_rx_buffer *buf =
1396                                         &(rx_ring->rx_buffer_info[i]);
1397                         if (buf->dma)
1398                                 pci_unmap_single(pdev, buf->dma,
1399                                                  IXGBE_RXBUFFER_2048,
1400                                                  PCI_DMA_FROMDEVICE);
1401                         if (buf->skb)
1402                                 dev_kfree_skb(buf->skb);
1403                 }
1404         }
1405
1406         if (tx_ring->desc) {
1407                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1408                                     tx_ring->dma);
1409                 tx_ring->desc = NULL;
1410         }
1411         if (rx_ring->desc) {
1412                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1413                                     rx_ring->dma);
1414                 rx_ring->desc = NULL;
1415         }
1416
1417         kfree(tx_ring->tx_buffer_info);
1418         tx_ring->tx_buffer_info = NULL;
1419         kfree(rx_ring->rx_buffer_info);
1420         rx_ring->rx_buffer_info = NULL;
1421
1422         return;
1423 }
1424
1425 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1426 {
1427         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1428         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1429         struct pci_dev *pdev = adapter->pdev;
1430         u32 rctl, reg_data;
1431         int i, ret_val;
1432
1433         /* Setup Tx descriptor ring and Tx buffers */
1434
1435         if (!tx_ring->count)
1436                 tx_ring->count = IXGBE_DEFAULT_TXD;
1437
1438         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1439                                           sizeof(struct ixgbe_tx_buffer),
1440                                           GFP_KERNEL);
1441         if (!(tx_ring->tx_buffer_info)) {
1442                 ret_val = 1;
1443                 goto err_nomem;
1444         }
1445
1446         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1447         tx_ring->size = ALIGN(tx_ring->size, 4096);
1448         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1449                                                    &tx_ring->dma))) {
1450                 ret_val = 2;
1451                 goto err_nomem;
1452         }
1453         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1454
1455         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1456                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1457         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1458                         ((u64) tx_ring->dma >> 32));
1459         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1460                         tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1461         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1462         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1463
1464         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1465         reg_data |= IXGBE_HLREG0_TXPADEN;
1466         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1467
1468         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1469                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1470                 reg_data |= IXGBE_DMATXCTL_TE;
1471                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1472         }
1473         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1474         reg_data |= IXGBE_TXDCTL_ENABLE;
1475         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1476
1477         for (i = 0; i < tx_ring->count; i++) {
1478                 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1479                 struct sk_buff *skb;
1480                 unsigned int size = 1024;
1481
1482                 skb = alloc_skb(size, GFP_KERNEL);
1483                 if (!skb) {
1484                         ret_val = 3;
1485                         goto err_nomem;
1486                 }
1487                 skb_put(skb, size);
1488                 tx_ring->tx_buffer_info[i].skb = skb;
1489                 tx_ring->tx_buffer_info[i].length = skb->len;
1490                 tx_ring->tx_buffer_info[i].dma =
1491                         pci_map_single(pdev, skb->data, skb->len,
1492                                        PCI_DMA_TODEVICE);
1493                 desc->read.buffer_addr =
1494                                     cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1495                 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1496                 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1497                                                        IXGBE_TXD_CMD_IFCS |
1498                                                        IXGBE_TXD_CMD_RS);
1499                 desc->read.olinfo_status = 0;
1500                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1501                         desc->read.olinfo_status |=
1502                                         (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1503
1504         }
1505
1506         /* Setup Rx Descriptor ring and Rx buffers */
1507
1508         if (!rx_ring->count)
1509                 rx_ring->count = IXGBE_DEFAULT_RXD;
1510
1511         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1512                                           sizeof(struct ixgbe_rx_buffer),
1513                                           GFP_KERNEL);
1514         if (!(rx_ring->rx_buffer_info)) {
1515                 ret_val = 4;
1516                 goto err_nomem;
1517         }
1518
1519         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1520         rx_ring->size = ALIGN(rx_ring->size, 4096);
1521         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1522                                                    &rx_ring->dma))) {
1523                 ret_val = 5;
1524                 goto err_nomem;
1525         }
1526         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1527
1528         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1529         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1530         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1531                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1532         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1533                         ((u64) rx_ring->dma >> 32));
1534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1536         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1537
1538         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1539         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1540         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1541
1542         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1543         reg_data &= ~IXGBE_HLREG0_LPBK;
1544         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1545
1546         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1547 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1548                                                   Threshold Size mask */
1549         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1550         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1551
1552         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1553 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1554         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1555         reg_data |= adapter->hw.mac.mc_filter_type;
1556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1557
1558         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1559         reg_data |= IXGBE_RXDCTL_ENABLE;
1560         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1561         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1562                 int j = adapter->rx_ring[0].reg_idx;
1563                 u32 k;
1564                 for (k = 0; k < 10; k++) {
1565                         if (IXGBE_READ_REG(&adapter->hw,
1566                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1567                                 break;
1568                         else
1569                                 msleep(1);
1570                 }
1571         }
1572
1573         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1574         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1575
1576         for (i = 0; i < rx_ring->count; i++) {
1577                 union ixgbe_adv_rx_desc *rx_desc =
1578                                                  IXGBE_RX_DESC_ADV(*rx_ring, i);
1579                 struct sk_buff *skb;
1580
1581                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1582                 if (!skb) {
1583                         ret_val = 6;
1584                         goto err_nomem;
1585                 }
1586                 skb_reserve(skb, NET_IP_ALIGN);
1587                 rx_ring->rx_buffer_info[i].skb = skb;
1588                 rx_ring->rx_buffer_info[i].dma =
1589                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1590                                        PCI_DMA_FROMDEVICE);
1591                 rx_desc->read.pkt_addr =
1592                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1593                 memset(skb->data, 0x00, skb->len);
1594         }
1595
1596         return 0;
1597
1598 err_nomem:
1599         ixgbe_free_desc_rings(adapter);
1600         return ret_val;
1601 }
1602
1603 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1604 {
1605         struct ixgbe_hw *hw = &adapter->hw;
1606         u32 reg_data;
1607
1608         /* right now we only support MAC loopback in the driver */
1609
1610         /* Setup MAC loopback */
1611         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1612         reg_data |= IXGBE_HLREG0_LPBK;
1613         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1614
1615         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1616         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1617         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1618         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1619
1620         /* Disable Atlas Tx lanes; re-enabled in reset path */
1621         if (hw->mac.type == ixgbe_mac_82598EB) {
1622                 u8 atlas;
1623
1624                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1625                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1626                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1627
1628                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1629                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1630                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1631
1632                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1633                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1634                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1635
1636                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1637                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1638                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1639         }
1640
1641         return 0;
1642 }
1643
1644 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1645 {
1646         u32 reg_data;
1647
1648         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1649         reg_data &= ~IXGBE_HLREG0_LPBK;
1650         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1651 }
1652
1653 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1654                                       unsigned int frame_size)
1655 {
1656         memset(skb->data, 0xFF, frame_size);
1657         frame_size &= ~1;
1658         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1659         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1660         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1661 }
1662
1663 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1664                                     unsigned int frame_size)
1665 {
1666         frame_size &= ~1;
1667         if (*(skb->data + 3) == 0xFF) {
1668                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1669                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1670                         return 0;
1671                 }
1672         }
1673         return 13;
1674 }
1675
1676 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1677 {
1678         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1679         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1680         struct pci_dev *pdev = adapter->pdev;
1681         int i, j, k, l, lc, good_cnt, ret_val = 0;
1682         unsigned long time;
1683
1684         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1685
1686         /*
1687          * Calculate the loop count based on the largest descriptor ring
1688          * The idea is to wrap the largest ring a number of times using 64
1689          * send/receive pairs during each loop
1690          */
1691
1692         if (rx_ring->count <= tx_ring->count)
1693                 lc = ((tx_ring->count / 64) * 2) + 1;
1694         else
1695                 lc = ((rx_ring->count / 64) * 2) + 1;
1696
1697         k = l = 0;
1698         for (j = 0; j <= lc; j++) {
1699                 for (i = 0; i < 64; i++) {
1700                         ixgbe_create_lbtest_frame(
1701                                         tx_ring->tx_buffer_info[k].skb,
1702                                         1024);
1703                         pci_dma_sync_single_for_device(pdev,
1704                                 tx_ring->tx_buffer_info[k].dma,
1705                                 tx_ring->tx_buffer_info[k].length,
1706                                 PCI_DMA_TODEVICE);
1707                         if (unlikely(++k == tx_ring->count))
1708                                 k = 0;
1709                 }
1710                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1711                 msleep(200);
1712                 /* set the start time for the receive */
1713                 time = jiffies;
1714                 good_cnt = 0;
1715                 do {
1716                         /* receive the sent packets */
1717                         pci_dma_sync_single_for_cpu(pdev,
1718                                         rx_ring->rx_buffer_info[l].dma,
1719                                         IXGBE_RXBUFFER_2048,
1720                                         PCI_DMA_FROMDEVICE);
1721                         ret_val = ixgbe_check_lbtest_frame(
1722                                         rx_ring->rx_buffer_info[l].skb, 1024);
1723                         if (!ret_val)
1724                                 good_cnt++;
1725                         if (++l == rx_ring->count)
1726                                 l = 0;
1727                         /*
1728                          * time + 20 msecs (200 msecs on 2.4) is more than
1729                          * enough time to complete the receives, if it's
1730                          * exceeded, break and error off
1731                          */
1732                 } while (good_cnt < 64 && jiffies < (time + 20));
1733                 if (good_cnt != 64) {
1734                         /* ret_val is the same as mis-compare */
1735                         ret_val = 13;
1736                         break;
1737                 }
1738                 if (jiffies >= (time + 20)) {
1739                         /* Error code for time out error */
1740                         ret_val = 14;
1741                         break;
1742                 }
1743         }
1744
1745         return ret_val;
1746 }
1747
1748 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1749 {
1750         *data = ixgbe_setup_desc_rings(adapter);
1751         if (*data)
1752                 goto out;
1753         *data = ixgbe_setup_loopback_test(adapter);
1754         if (*data)
1755                 goto err_loopback;
1756         *data = ixgbe_run_loopback_test(adapter);
1757         ixgbe_loopback_cleanup(adapter);
1758
1759 err_loopback:
1760         ixgbe_free_desc_rings(adapter);
1761 out:
1762         return *data;
1763 }
1764
1765 static void ixgbe_diag_test(struct net_device *netdev,
1766                             struct ethtool_test *eth_test, u64 *data)
1767 {
1768         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1769         bool if_running = netif_running(netdev);
1770
1771         set_bit(__IXGBE_TESTING, &adapter->state);
1772         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1773                 /* Offline tests */
1774
1775                 DPRINTK(HW, INFO, "offline testing starting\n");
1776
1777                 /* Link test performed before hardware reset so autoneg doesn't
1778                  * interfere with test result */
1779                 if (ixgbe_link_test(adapter, &data[4]))
1780                         eth_test->flags |= ETH_TEST_FL_FAILED;
1781
1782                 if (if_running)
1783                         /* indicate we're in test mode */
1784                         dev_close(netdev);
1785                 else
1786                         ixgbe_reset(adapter);
1787
1788                 DPRINTK(HW, INFO, "register testing starting\n");
1789                 if (ixgbe_reg_test(adapter, &data[0]))
1790                         eth_test->flags |= ETH_TEST_FL_FAILED;
1791
1792                 ixgbe_reset(adapter);
1793                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1794                 if (ixgbe_eeprom_test(adapter, &data[1]))
1795                         eth_test->flags |= ETH_TEST_FL_FAILED;
1796
1797                 ixgbe_reset(adapter);
1798                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1799                 if (ixgbe_intr_test(adapter, &data[2]))
1800                         eth_test->flags |= ETH_TEST_FL_FAILED;
1801
1802                 ixgbe_reset(adapter);
1803                 DPRINTK(HW, INFO, "loopback testing starting\n");
1804                 if (ixgbe_loopback_test(adapter, &data[3]))
1805                         eth_test->flags |= ETH_TEST_FL_FAILED;
1806
1807                 ixgbe_reset(adapter);
1808
1809                 clear_bit(__IXGBE_TESTING, &adapter->state);
1810                 if (if_running)
1811                         dev_open(netdev);
1812         } else {
1813                 DPRINTK(HW, INFO, "online testing starting\n");
1814                 /* Online tests */
1815                 if (ixgbe_link_test(adapter, &data[4]))
1816                         eth_test->flags |= ETH_TEST_FL_FAILED;
1817
1818                 /* Online tests aren't run; pass by default */
1819                 data[0] = 0;
1820                 data[1] = 0;
1821                 data[2] = 0;
1822                 data[3] = 0;
1823
1824                 clear_bit(__IXGBE_TESTING, &adapter->state);
1825         }
1826         msleep_interruptible(4 * 1000);
1827 }
1828
1829 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1830                                struct ethtool_wolinfo *wol)
1831 {
1832         struct ixgbe_hw *hw = &adapter->hw;
1833         int retval = 1;
1834
1835         switch(hw->device_id) {
1836         case IXGBE_DEV_ID_82599_KX4:
1837                 retval = 0;
1838                 break;
1839         default:
1840                 wol->supported = 0;
1841         }
1842
1843         return retval;
1844 }
1845
1846 static void ixgbe_get_wol(struct net_device *netdev,
1847                           struct ethtool_wolinfo *wol)
1848 {
1849         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1850
1851         wol->supported = WAKE_UCAST | WAKE_MCAST |
1852                          WAKE_BCAST | WAKE_MAGIC;
1853         wol->wolopts = 0;
1854
1855         if (ixgbe_wol_exclusion(adapter, wol) ||
1856             !device_can_wakeup(&adapter->pdev->dev))
1857                 return;
1858
1859         if (adapter->wol & IXGBE_WUFC_EX)
1860                 wol->wolopts |= WAKE_UCAST;
1861         if (adapter->wol & IXGBE_WUFC_MC)
1862                 wol->wolopts |= WAKE_MCAST;
1863         if (adapter->wol & IXGBE_WUFC_BC)
1864                 wol->wolopts |= WAKE_BCAST;
1865         if (adapter->wol & IXGBE_WUFC_MAG)
1866                 wol->wolopts |= WAKE_MAGIC;
1867
1868         return;
1869 }
1870
1871 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1872 {
1873         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1874
1875         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1876                 return -EOPNOTSUPP;
1877
1878         if (ixgbe_wol_exclusion(adapter, wol))
1879                 return wol->wolopts ? -EOPNOTSUPP : 0;
1880
1881         adapter->wol = 0;
1882
1883         if (wol->wolopts & WAKE_UCAST)
1884                 adapter->wol |= IXGBE_WUFC_EX;
1885         if (wol->wolopts & WAKE_MCAST)
1886                 adapter->wol |= IXGBE_WUFC_MC;
1887         if (wol->wolopts & WAKE_BCAST)
1888                 adapter->wol |= IXGBE_WUFC_BC;
1889         if (wol->wolopts & WAKE_MAGIC)
1890                 adapter->wol |= IXGBE_WUFC_MAG;
1891
1892         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1893
1894         return 0;
1895 }
1896
1897 static int ixgbe_nway_reset(struct net_device *netdev)
1898 {
1899         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1900
1901         if (netif_running(netdev))
1902                 ixgbe_reinit_locked(adapter);
1903
1904         return 0;
1905 }
1906
1907 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1908 {
1909         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1910         struct ixgbe_hw *hw = &adapter->hw;
1911         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1912         u32 i;
1913
1914         if (!data || data > 300)
1915                 data = 300;
1916
1917         for (i = 0; i < (data * 1000); i += 400) {
1918                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1919                 msleep_interruptible(200);
1920                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1921                 msleep_interruptible(200);
1922         }
1923
1924         /* Restore LED settings */
1925         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1926
1927         return 0;
1928 }
1929
1930 static int ixgbe_get_coalesce(struct net_device *netdev,
1931                               struct ethtool_coalesce *ec)
1932 {
1933         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1934
1935         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1936
1937         /* only valid if in constant ITR mode */
1938         switch (adapter->rx_itr_setting) {
1939         case 0:
1940                 /* throttling disabled */
1941                 ec->rx_coalesce_usecs = 0;
1942                 break;
1943         case 1:
1944                 /* dynamic ITR mode */
1945                 ec->rx_coalesce_usecs = 1;
1946                 break;
1947         default:
1948                 /* fixed interrupt rate mode */
1949                 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
1950                 break;
1951         }
1952
1953         /* only valid if in constant ITR mode */
1954         switch (adapter->tx_itr_setting) {
1955         case 0:
1956                 /* throttling disabled */
1957                 ec->tx_coalesce_usecs = 0;
1958                 break;
1959         case 1:
1960                 /* dynamic ITR mode */
1961                 ec->tx_coalesce_usecs = 1;
1962                 break;
1963         default:
1964                 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1965                 break;
1966         }
1967
1968         return 0;
1969 }
1970
1971 static int ixgbe_set_coalesce(struct net_device *netdev,
1972                               struct ethtool_coalesce *ec)
1973 {
1974         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1975         struct ixgbe_q_vector *q_vector;
1976         int i;
1977
1978         /*
1979          * don't accept tx specific changes if we've got mixed RxTx vectors
1980          * test and jump out here if needed before changing the rx numbers
1981          */
1982         if ((1000000/ec->tx_coalesce_usecs) != adapter->tx_eitr_param &&
1983             adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
1984                 return -EINVAL;
1985
1986         if (ec->tx_max_coalesced_frames_irq)
1987                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1988
1989         if (ec->rx_coalesce_usecs > 1) {
1990                 /* check the limits */
1991                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1992                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1993                         return -EINVAL;
1994
1995                 /* store the value in ints/second */
1996                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
1997
1998                 /* static value of interrupt rate */
1999                 adapter->rx_itr_setting = adapter->rx_eitr_param;
2000                 /* clear the lower bit as its used for dynamic state */
2001                 adapter->rx_itr_setting &= ~1;
2002         } else if (ec->rx_coalesce_usecs == 1) {
2003                 /* 1 means dynamic mode */
2004                 adapter->rx_eitr_param = 20000;
2005                 adapter->rx_itr_setting = 1;
2006         } else {
2007                 /*
2008                  * any other value means disable eitr, which is best
2009                  * served by setting the interrupt rate very high
2010                  */
2011                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2012                         adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
2013                 else
2014                         adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2015                 adapter->rx_itr_setting = 0;
2016         }
2017
2018         if (ec->tx_coalesce_usecs > 1) {
2019                 /* check the limits */
2020                 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2021                     (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2022                         return -EINVAL;
2023
2024                 /* store the value in ints/second */
2025                 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2026
2027                 /* static value of interrupt rate */
2028                 adapter->tx_itr_setting = adapter->tx_eitr_param;
2029
2030                 /* clear the lower bit as its used for dynamic state */
2031                 adapter->tx_itr_setting &= ~1;
2032         } else if (ec->tx_coalesce_usecs == 1) {
2033                 /* 1 means dynamic mode */
2034                 adapter->tx_eitr_param = 10000;
2035                 adapter->tx_itr_setting = 1;
2036         } else {
2037                 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2038                 adapter->tx_itr_setting = 0;
2039         }
2040
2041         /* MSI/MSIx Interrupt Mode */
2042         if (adapter->flags &
2043             (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2044                 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2045                 for (i = 0; i < num_vectors; i++) {
2046                         q_vector = adapter->q_vector[i];
2047                         if (q_vector->txr_count && !q_vector->rxr_count)
2048                                 /* tx only */
2049                                 q_vector->eitr = adapter->tx_eitr_param;
2050                         else
2051                                 /* rx only or mixed */
2052                                 q_vector->eitr = adapter->rx_eitr_param;
2053                         ixgbe_write_eitr(q_vector);
2054                 }
2055         /* Legacy Interrupt Mode */
2056         } else {
2057                 q_vector = adapter->q_vector[0];
2058                 q_vector->eitr = adapter->rx_eitr_param;
2059                 ixgbe_write_eitr(q_vector);
2060         }
2061
2062         return 0;
2063 }
2064
2065 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2066 {
2067         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2068
2069         ethtool_op_set_flags(netdev, data);
2070
2071         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2072                 return 0;
2073
2074         /* if state changes we need to update adapter->flags and reset */
2075         if ((!!(data & ETH_FLAG_LRO)) != 
2076             (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2077                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2078                 if (netif_running(netdev))
2079                         ixgbe_reinit_locked(adapter);
2080                 else
2081                         ixgbe_reset(adapter);
2082         }
2083         return 0;
2084
2085 }
2086
2087 static const struct ethtool_ops ixgbe_ethtool_ops = {
2088         .get_settings           = ixgbe_get_settings,
2089         .set_settings           = ixgbe_set_settings,
2090         .get_drvinfo            = ixgbe_get_drvinfo,
2091         .get_regs_len           = ixgbe_get_regs_len,
2092         .get_regs               = ixgbe_get_regs,
2093         .get_wol                = ixgbe_get_wol,
2094         .set_wol                = ixgbe_set_wol,
2095         .nway_reset             = ixgbe_nway_reset,
2096         .get_link               = ethtool_op_get_link,
2097         .get_eeprom_len         = ixgbe_get_eeprom_len,
2098         .get_eeprom             = ixgbe_get_eeprom,
2099         .get_ringparam          = ixgbe_get_ringparam,
2100         .set_ringparam          = ixgbe_set_ringparam,
2101         .get_pauseparam         = ixgbe_get_pauseparam,
2102         .set_pauseparam         = ixgbe_set_pauseparam,
2103         .get_rx_csum            = ixgbe_get_rx_csum,
2104         .set_rx_csum            = ixgbe_set_rx_csum,
2105         .get_tx_csum            = ixgbe_get_tx_csum,
2106         .set_tx_csum            = ixgbe_set_tx_csum,
2107         .get_sg                 = ethtool_op_get_sg,
2108         .set_sg                 = ethtool_op_set_sg,
2109         .get_msglevel           = ixgbe_get_msglevel,
2110         .set_msglevel           = ixgbe_set_msglevel,
2111         .get_tso                = ethtool_op_get_tso,
2112         .set_tso                = ixgbe_set_tso,
2113         .self_test              = ixgbe_diag_test,
2114         .get_strings            = ixgbe_get_strings,
2115         .phys_id                = ixgbe_phys_id,
2116         .get_sset_count         = ixgbe_get_sset_count,
2117         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2118         .get_coalesce           = ixgbe_get_coalesce,
2119         .set_coalesce           = ixgbe_set_coalesce,
2120         .get_flags              = ethtool_op_get_flags,
2121         .set_flags              = ixgbe_set_flags,
2122 };
2123
2124 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2125 {
2126         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2127 }