ed265a7a898faea70408ae635c92328ae54003a7
[linux-2.6.git] / drivers / net / ixgbe / ixgbe_82598.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES   16
38 #define IXGBE_82598_MC_TBL_SIZE  128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42                                              ixgbe_link_speed *speed,
43                                              bool *autoneg);
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46                                                ixgbe_link_speed speed,
47                                                bool autoneg,
48                                                bool autoneg_wait_to_complete);
49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50                                        u8 *eeprom_data);
51
52 /**
53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
54  *  @hw: pointer to hardware structure
55  *
56  *  Read PCIe configuration space, and get the MSI-X vector count from
57  *  the capabilities table.
58  **/
59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
60 {
61         struct ixgbe_adapter *adapter = hw->back;
62         u16 msix_count;
63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
64                              &msix_count);
65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
66
67         /* MSI-X count is zero-based in HW, so increment to give proper value */
68         msix_count++;
69
70         return msix_count;
71 }
72
73 /**
74  */
75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
76 {
77         struct ixgbe_mac_info *mac = &hw->mac;
78         struct ixgbe_phy_info *phy = &hw->phy;
79         s32 ret_val = 0;
80         u16 list_offset, data_offset;
81
82         /* Set the bus information prior to PHY identification */
83         mac->ops.get_bus_info(hw);
84
85         /* Call PHY identify routine to get the phy type */
86         ixgbe_identify_phy_generic(hw);
87
88         /* PHY Init */
89         switch (phy->type) {
90         case ixgbe_phy_tn:
91                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
92                 phy->ops.get_firmware_version =
93                              &ixgbe_get_phy_firmware_version_tnx;
94                 break;
95         case ixgbe_phy_nl:
96                 phy->ops.reset = &ixgbe_reset_phy_nl;
97
98                 /* Call SFP+ identify routine to get the SFP+ module type */
99                 ret_val = phy->ops.identify_sfp(hw);
100                 if (ret_val != 0)
101                         goto out;
102                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
103                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
104                         goto out;
105                 }
106
107                 /* Check to see if SFP+ module is supported */
108                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
109                                                               &list_offset,
110                                                               &data_offset);
111                 if (ret_val != 0) {
112                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
113                         goto out;
114                 }
115                 break;
116         default:
117                 break;
118         }
119
120         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
121                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
122                 mac->ops.setup_link_speed =
123                                      &ixgbe_setup_copper_link_speed_82598;
124                 mac->ops.get_link_capabilities =
125                                      &ixgbe_get_copper_link_capabilities_82598;
126         }
127
128         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
129         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
130         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
131         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
132         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
133         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
134
135 out:
136         return ret_val;
137 }
138
139 /**
140  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
141  *  @hw: pointer to hardware structure
142  *  @speed: pointer to link speed
143  *  @autoneg: boolean auto-negotiation value
144  *
145  *  Determines the link capabilities by reading the AUTOC register.
146  **/
147 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
148                                              ixgbe_link_speed *speed,
149                                              bool *autoneg)
150 {
151         s32 status = 0;
152
153         /*
154          * Determine link capabilities based on the stored value of AUTOC,
155          * which represents EEPROM defaults.
156          */
157         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
158         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
159                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
160                 *autoneg = false;
161                 break;
162
163         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
164                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
165                 *autoneg = false;
166                 break;
167
168         case IXGBE_AUTOC_LMS_1G_AN:
169                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
170                 *autoneg = true;
171                 break;
172
173         case IXGBE_AUTOC_LMS_KX4_AN:
174         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
175                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
176                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
177                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
178                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
179                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
180                 *autoneg = true;
181                 break;
182
183         default:
184                 status = IXGBE_ERR_LINK_SETUP;
185                 break;
186         }
187
188         return status;
189 }
190
191 /**
192  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
193  *  @hw: pointer to hardware structure
194  *  @speed: pointer to link speed
195  *  @autoneg: boolean auto-negotiation value
196  *
197  *  Determines the link capabilities by reading the AUTOC register.
198  **/
199 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
200                                                     ixgbe_link_speed *speed,
201                                                     bool *autoneg)
202 {
203         s32 status = IXGBE_ERR_LINK_SETUP;
204         u16 speed_ability;
205
206         *speed = 0;
207         *autoneg = true;
208
209         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
210                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
211                                       &speed_ability);
212
213         if (status == 0) {
214                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
215                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
216                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
217                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
218         }
219
220         return status;
221 }
222
223 /**
224  *  ixgbe_get_media_type_82598 - Determines media type
225  *  @hw: pointer to hardware structure
226  *
227  *  Returns the media type (fiber, copper, backplane)
228  **/
229 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
230 {
231         enum ixgbe_media_type media_type;
232
233         /* Media type for I82598 is based on device ID */
234         switch (hw->device_id) {
235         case IXGBE_DEV_ID_82598:
236         case IXGBE_DEV_ID_82598_BX:
237                 media_type = ixgbe_media_type_backplane;
238                 break;
239         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
240         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
241         case IXGBE_DEV_ID_82598EB_CX4:
242         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
243         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
244         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
245         case IXGBE_DEV_ID_82598EB_XF_LR:
246         case IXGBE_DEV_ID_82598EB_SFP_LOM:
247                 media_type = ixgbe_media_type_fiber;
248                 break;
249         case IXGBE_DEV_ID_82598AT:
250                 media_type = ixgbe_media_type_copper;
251                 break;
252         default:
253                 media_type = ixgbe_media_type_unknown;
254                 break;
255         }
256
257         return media_type;
258 }
259
260 /**
261  *  ixgbe_fc_enable_82598 - Enable flow control
262  *  @hw: pointer to hardware structure
263  *  @packetbuf_num: packet buffer number (0-7)
264  *
265  *  Enable flow control according to the current settings.
266  **/
267 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
268 {
269         s32 ret_val = 0;
270         u32 fctrl_reg;
271         u32 rmcs_reg;
272         u32 reg;
273
274         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
275         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
276
277         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
278         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
279
280         /*
281          * The possible values of fc.current_mode are:
282          * 0: Flow control is completely disabled
283          * 1: Rx flow control is enabled (we can receive pause frames,
284          *    but not send pause frames).
285          * 2:  Tx flow control is enabled (we can send pause frames but
286          *     we do not support receiving pause frames).
287          * 3: Both Rx and Tx flow control (symmetric) are enabled.
288          * other: Invalid.
289          */
290         switch (hw->fc.current_mode) {
291         case ixgbe_fc_none:
292                 /* Flow control completely disabled by software override. */
293                 break;
294         case ixgbe_fc_rx_pause:
295                 /*
296                  * Rx Flow control is enabled and Tx Flow control is
297                  * disabled by software override. Since there really
298                  * isn't a way to advertise that we are capable of RX
299                  * Pause ONLY, we will advertise that we support both
300                  * symmetric and asymmetric Rx PAUSE.  Later, we will
301                  * disable the adapter's ability to send PAUSE frames.
302                  */
303                 fctrl_reg |= IXGBE_FCTRL_RFCE;
304                 break;
305         case ixgbe_fc_tx_pause:
306                 /*
307                  * Tx Flow control is enabled, and Rx Flow control is
308                  * disabled by software override.
309                  */
310                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
311                 break;
312         case ixgbe_fc_full:
313                 /* Flow control (both Rx and Tx) is enabled by SW override. */
314                 fctrl_reg |= IXGBE_FCTRL_RFCE;
315                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
316                 break;
317         default:
318                 hw_dbg(hw, "Flow control param set incorrectly\n");
319                 ret_val = -IXGBE_ERR_CONFIG;
320                 goto out;
321                 break;
322         }
323
324         /* Enable 802.3x based flow control settings. */
325         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
326         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
327
328         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
329         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
330                 if (hw->fc.send_xon) {
331                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
332                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
333                 } else {
334                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
335                                         hw->fc.low_water);
336                 }
337
338                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
339                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
340         }
341
342         /* Configure pause time (2 TCs per register) */
343         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
344         if ((packetbuf_num & 1) == 0)
345                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
346         else
347                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
348         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
349
350         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
351
352 out:
353         return ret_val;
354 }
355
356 /**
357  *  ixgbe_setup_fc_82598 - Configure flow control settings
358  *  @hw: pointer to hardware structure
359  *  @packetbuf_num: packet buffer number (0-7)
360  *
361  *  Configures the flow control settings based on SW configuration.  This
362  *  function is used for 802.3x flow control configuration only.
363  **/
364 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
365 {
366         s32 ret_val = 0;
367         ixgbe_link_speed speed;
368         bool link_up;
369
370         /* Validate the packetbuf configuration */
371         if (packetbuf_num < 0 || packetbuf_num > 7) {
372                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
373                           " 0-7\n", packetbuf_num);
374                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
375                 goto out;
376         }
377
378         /*
379          * Validate the water mark configuration.  Zero water marks are invalid
380          * because it causes the controller to just blast out fc packets.
381          */
382         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
383                 hw_dbg(hw, "Invalid water mark configuration\n");
384                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
385                 goto out;
386         }
387
388         /*
389          * Validate the requested mode.  Strict IEEE mode does not allow
390          * ixgbe_fc_rx_pause because it will cause testing anomalies.
391          */
392         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
393                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
394                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
395                 goto out;
396         }
397
398         /*
399          * 10gig parts do not have a word in the EEPROM to determine the
400          * default flow control setting, so we explicitly set it to full.
401          */
402         if (hw->fc.requested_mode == ixgbe_fc_default)
403                 hw->fc.requested_mode = ixgbe_fc_full;
404
405         /*
406          * Save off the requested flow control mode for use later.  Depending
407          * on the link partner's capabilities, we may or may not use this mode.
408          */
409
410         hw->fc.current_mode = hw->fc.requested_mode;
411
412         /* Decide whether to use autoneg or not. */
413         hw->mac.ops.check_link(hw, &speed, &link_up, false);
414         if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL))
415                 ret_val = ixgbe_fc_autoneg(hw);
416
417         if (ret_val)
418                 goto out;
419
420         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
421
422 out:
423         return ret_val;
424 }
425
426 /**
427  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
428  *  @hw: pointer to hardware structure
429  *
430  *  Configures link settings based on values in the ixgbe_hw struct.
431  *  Restarts the link.  Performs autonegotiation if needed.
432  **/
433 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
434 {
435         u32 autoc_reg;
436         u32 links_reg;
437         u32 i;
438         s32 status = 0;
439
440         /* Restart link */
441         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
442         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
443         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
444
445         /* Only poll for autoneg to complete if specified to do so */
446         if (hw->phy.autoneg_wait_to_complete) {
447                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
448                      IXGBE_AUTOC_LMS_KX4_AN ||
449                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
450                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
451                         links_reg = 0; /* Just in case Autoneg time = 0 */
452                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
453                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
454                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
455                                         break;
456                                 msleep(100);
457                         }
458                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
459                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
460                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
461                         }
462                 }
463         }
464
465         /*
466          * We want to save off the original Flow Control configuration just in
467          * case we get disconnected and then reconnected into a different hub
468          * or switch with different Flow Control capabilities.
469          */
470         ixgbe_setup_fc_82598(hw, 0);
471
472         /* Add delay to filter out noises during initial link setup */
473         msleep(50);
474
475         return status;
476 }
477
478 /**
479  *  ixgbe_check_mac_link_82598 - Get link/speed status
480  *  @hw: pointer to hardware structure
481  *  @speed: pointer to link speed
482  *  @link_up: true is link is up, false otherwise
483  *  @link_up_wait_to_complete: bool used to wait for link up or not
484  *
485  *  Reads the links register to determine if link is up and the current speed
486  **/
487 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
488                                       ixgbe_link_speed *speed, bool *link_up,
489                                       bool link_up_wait_to_complete)
490 {
491         u32 links_reg;
492         u32 i;
493         u16 link_reg, adapt_comp_reg;
494
495         /*
496          * SERDES PHY requires us to read link status from register 0xC79F.
497          * Bit 0 set indicates link is up/ready; clear indicates link down.
498          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
499          * clear indicates active; set indicates inactive.
500          */
501         if (hw->phy.type == ixgbe_phy_nl) {
502                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
503                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
504                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
505                                      &adapt_comp_reg);
506                 if (link_up_wait_to_complete) {
507                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
508                                 if ((link_reg & 1) &&
509                                     ((adapt_comp_reg & 1) == 0)) {
510                                         *link_up = true;
511                                         break;
512                                 } else {
513                                         *link_up = false;
514                                 }
515                                 msleep(100);
516                                 hw->phy.ops.read_reg(hw, 0xC79F,
517                                                      IXGBE_TWINAX_DEV,
518                                                      &link_reg);
519                                 hw->phy.ops.read_reg(hw, 0xC00C,
520                                                      IXGBE_TWINAX_DEV,
521                                                      &adapt_comp_reg);
522                         }
523                 } else {
524                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
525                                 *link_up = true;
526                         else
527                                 *link_up = false;
528                 }
529
530                 if (*link_up == false)
531                         goto out;
532         }
533
534         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
535         if (link_up_wait_to_complete) {
536                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
537                         if (links_reg & IXGBE_LINKS_UP) {
538                                 *link_up = true;
539                                 break;
540                         } else {
541                                 *link_up = false;
542                         }
543                         msleep(100);
544                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
545                 }
546         } else {
547                 if (links_reg & IXGBE_LINKS_UP)
548                         *link_up = true;
549                 else
550                         *link_up = false;
551         }
552
553         if (links_reg & IXGBE_LINKS_SPEED)
554                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
555         else
556                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
557
558 out:
559         return 0;
560 }
561
562
563 /**
564  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
565  *  @hw: pointer to hardware structure
566  *  @speed: new link speed
567  *  @autoneg: true if auto-negotiation enabled
568  *  @autoneg_wait_to_complete: true if waiting is needed to complete
569  *
570  *  Set the link speed in the AUTOC register and restarts link.
571  **/
572 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
573                                            ixgbe_link_speed speed, bool autoneg,
574                                            bool autoneg_wait_to_complete)
575 {
576         s32              status            = 0;
577         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
578         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
579         u32              autoc             = curr_autoc;
580         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
581
582         /* Check to see if speed passed in is supported. */
583         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
584         speed &= link_capabilities;
585
586         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
587                 status = IXGBE_ERR_LINK_SETUP;
588
589         /* Set KX4/KX support according to speed requested */
590         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
591                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
592                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
593                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
594                         autoc |= IXGBE_AUTOC_KX4_SUPP;
595                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
596                         autoc |= IXGBE_AUTOC_KX_SUPP;
597                 if (autoc != curr_autoc)
598                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
599         }
600
601         if (status == 0) {
602                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
603
604                 /*
605                  * Setup and restart the link based on the new values in
606                  * ixgbe_hw This will write the AUTOC register based on the new
607                  * stored values
608                  */
609                 status = ixgbe_setup_mac_link_82598(hw);
610         }
611
612         return status;
613 }
614
615
616 /**
617  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
618  *  @hw: pointer to hardware structure
619  *
620  *  Configures link settings based on values in the ixgbe_hw struct.
621  *  Restarts the link.  Performs autonegotiation if needed.  Restart
622  *  phy and wait for autonegotiate to finish.  Then synchronize the
623  *  MAC and PHY.
624  **/
625 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
626 {
627         s32 status;
628
629         /* Restart autonegotiation on PHY */
630         status = hw->phy.ops.setup_link(hw);
631
632         /* Set up MAC */
633         ixgbe_setup_mac_link_82598(hw);
634
635         return status;
636 }
637
638 /**
639  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
640  *  @hw: pointer to hardware structure
641  *  @speed: new link speed
642  *  @autoneg: true if autonegotiation enabled
643  *  @autoneg_wait_to_complete: true if waiting is needed to complete
644  *
645  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
646  **/
647 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
648                                                ixgbe_link_speed speed,
649                                                bool autoneg,
650                                                bool autoneg_wait_to_complete)
651 {
652         s32 status;
653
654         /* Setup the PHY according to input speed */
655         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
656                                               autoneg_wait_to_complete);
657
658         /* Set up MAC */
659         ixgbe_setup_mac_link_82598(hw);
660
661         return status;
662 }
663
664 /**
665  *  ixgbe_reset_hw_82598 - Performs hardware reset
666  *  @hw: pointer to hardware structure
667  *
668  *  Resets the hardware by resetting the transmit and receive units, masks and
669  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
670  *  reset.
671  **/
672 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
673 {
674         s32 status = 0;
675         u32 ctrl;
676         u32 gheccr;
677         u32 i;
678         u32 autoc;
679         u8  analog_val;
680
681         /* Call adapter stop to disable tx/rx and clear interrupts */
682         hw->mac.ops.stop_adapter(hw);
683
684         /*
685          * Power up the Atlas Tx lanes if they are currently powered down.
686          * Atlas Tx lanes are powered down for MAC loopback tests, but
687          * they are not automatically restored on reset.
688          */
689         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
690         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
691                 /* Enable Tx Atlas so packets can be transmitted again */
692                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
693                                              &analog_val);
694                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
695                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
696                                               analog_val);
697
698                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
699                                              &analog_val);
700                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
701                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
702                                               analog_val);
703
704                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
705                                              &analog_val);
706                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
707                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
708                                               analog_val);
709
710                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
711                                              &analog_val);
712                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
713                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
714                                               analog_val);
715         }
716
717         /* Reset PHY */
718         if (hw->phy.reset_disable == false)
719                 hw->phy.ops.reset(hw);
720
721         /*
722          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
723          * access and verify no pending requests before reset
724          */
725         if (ixgbe_disable_pcie_master(hw) != 0) {
726                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
727                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
728         }
729
730         /*
731          * Issue global reset to the MAC.  This needs to be a SW reset.
732          * If link reset is used, it might reset the MAC when mng is using it
733          */
734         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
735         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
736         IXGBE_WRITE_FLUSH(hw);
737
738         /* Poll for reset bit to self-clear indicating reset is complete */
739         for (i = 0; i < 10; i++) {
740                 udelay(1);
741                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
742                 if (!(ctrl & IXGBE_CTRL_RST))
743                         break;
744         }
745         if (ctrl & IXGBE_CTRL_RST) {
746                 status = IXGBE_ERR_RESET_FAILED;
747                 hw_dbg(hw, "Reset polling failed to complete.\n");
748         }
749
750         msleep(50);
751
752         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
753         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
754         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
755
756         /*
757          * Store the original AUTOC value if it has not been
758          * stored off yet.  Otherwise restore the stored original
759          * AUTOC value since the reset operation sets back to deaults.
760          */
761         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
762         if (hw->mac.orig_link_settings_stored == false) {
763                 hw->mac.orig_autoc = autoc;
764                 hw->mac.orig_link_settings_stored = true;
765         } else if (autoc != hw->mac.orig_autoc) {
766                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
767         }
768
769         /* Store the permanent mac address */
770         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
771
772         return status;
773 }
774
775 /**
776  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
777  *  @hw: pointer to hardware struct
778  *  @rar: receive address register index to associate with a VMDq index
779  *  @vmdq: VMDq set index
780  **/
781 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
782 {
783         u32 rar_high;
784
785         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
786         rar_high &= ~IXGBE_RAH_VIND_MASK;
787         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
788         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
789         return 0;
790 }
791
792 /**
793  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
794  *  @hw: pointer to hardware struct
795  *  @rar: receive address register index to associate with a VMDq index
796  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
797  **/
798 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
799 {
800         u32 rar_high;
801         u32 rar_entries = hw->mac.num_rar_entries;
802
803         if (rar < rar_entries) {
804                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
805                 if (rar_high & IXGBE_RAH_VIND_MASK) {
806                         rar_high &= ~IXGBE_RAH_VIND_MASK;
807                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
808                 }
809         } else {
810                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
811         }
812
813         return 0;
814 }
815
816 /**
817  *  ixgbe_set_vfta_82598 - Set VLAN filter table
818  *  @hw: pointer to hardware structure
819  *  @vlan: VLAN id to write to VLAN filter
820  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
821  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
822  *
823  *  Turn on/off specified VLAN in the VLAN filter table.
824  **/
825 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
826                                 bool vlan_on)
827 {
828         u32 regindex;
829         u32 bitindex;
830         u32 bits;
831         u32 vftabyte;
832
833         if (vlan > 4095)
834                 return IXGBE_ERR_PARAM;
835
836         /* Determine 32-bit word position in array */
837         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
838
839         /* Determine the location of the (VMD) queue index */
840         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
841         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
842
843         /* Set the nibble for VMD queue index */
844         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
845         bits &= (~(0x0F << bitindex));
846         bits |= (vind << bitindex);
847         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
848
849         /* Determine the location of the bit for this VLAN id */
850         bitindex = vlan & 0x1F;   /* lower five bits */
851
852         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
853         if (vlan_on)
854                 /* Turn on this VLAN id */
855                 bits |= (1 << bitindex);
856         else
857                 /* Turn off this VLAN id */
858                 bits &= ~(1 << bitindex);
859         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
860
861         return 0;
862 }
863
864 /**
865  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
866  *  @hw: pointer to hardware structure
867  *
868  *  Clears the VLAN filer table, and the VMDq index associated with the filter
869  **/
870 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
871 {
872         u32 offset;
873         u32 vlanbyte;
874
875         for (offset = 0; offset < hw->mac.vft_size; offset++)
876                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
877
878         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
879                 for (offset = 0; offset < hw->mac.vft_size; offset++)
880                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
881                                         0);
882
883         return 0;
884 }
885
886 /**
887  *  ixgbe_blink_led_start_82598 - Blink LED based on index.
888  *  @hw: pointer to hardware structure
889  *  @index: led number to blink
890  **/
891 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
892 {
893         ixgbe_link_speed speed = 0;
894         bool link_up = 0;
895         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
896         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
897
898         /*
899          * Link must be up to auto-blink the LEDs on the 82598EB MAC;
900          * force it if link is down.
901          */
902         hw->mac.ops.check_link(hw, &speed, &link_up, false);
903
904         if (!link_up) {
905                 autoc_reg |= IXGBE_AUTOC_FLU;
906                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
907                 msleep(10);
908         }
909
910         led_reg &= ~IXGBE_LED_MODE_MASK(index);
911         led_reg |= IXGBE_LED_BLINK(index);
912         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
913         IXGBE_WRITE_FLUSH(hw);
914
915         return 0;
916 }
917
918 /**
919  *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
920  *  @hw: pointer to hardware structure
921  *  @index: led number to stop blinking
922  **/
923 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
924 {
925         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
926         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
927
928         autoc_reg &= ~IXGBE_AUTOC_FLU;
929         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
930         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
931
932         led_reg &= ~IXGBE_LED_MODE_MASK(index);
933         led_reg &= ~IXGBE_LED_BLINK(index);
934         led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
935         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
936         IXGBE_WRITE_FLUSH(hw);
937
938         return 0;
939 }
940
941 /**
942  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
943  *  @hw: pointer to hardware structure
944  *  @reg: analog register to read
945  *  @val: read value
946  *
947  *  Performs read operation to Atlas analog register specified.
948  **/
949 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
950 {
951         u32  atlas_ctl;
952
953         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
954                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
955         IXGBE_WRITE_FLUSH(hw);
956         udelay(10);
957         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
958         *val = (u8)atlas_ctl;
959
960         return 0;
961 }
962
963 /**
964  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
965  *  @hw: pointer to hardware structure
966  *  @reg: atlas register to write
967  *  @val: value to write
968  *
969  *  Performs write operation to Atlas analog register specified.
970  **/
971 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
972 {
973         u32  atlas_ctl;
974
975         atlas_ctl = (reg << 8) | val;
976         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
977         IXGBE_WRITE_FLUSH(hw);
978         udelay(10);
979
980         return 0;
981 }
982
983 /**
984  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
985  *  over I2C interface through an intermediate phy.
986  *  @hw: pointer to hardware structure
987  *  @byte_offset: EEPROM byte offset to read
988  *  @eeprom_data: value read
989  *
990  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
991  **/
992 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
993                                        u8 *eeprom_data)
994 {
995         s32 status = 0;
996         u16 sfp_addr = 0;
997         u16 sfp_data = 0;
998         u16 sfp_stat = 0;
999         u32 i;
1000
1001         if (hw->phy.type == ixgbe_phy_nl) {
1002                 /*
1003                  * phy SDA/SCL registers are at addresses 0xC30A to
1004                  * 0xC30D.  These registers are used to talk to the SFP+
1005                  * module's EEPROM through the SDA/SCL (I2C) interface.
1006                  */
1007                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1008                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1009                 hw->phy.ops.write_reg(hw,
1010                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1011                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1012                                       sfp_addr);
1013
1014                 /* Poll status */
1015                 for (i = 0; i < 100; i++) {
1016                         hw->phy.ops.read_reg(hw,
1017                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1018                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1019                                              &sfp_stat);
1020                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1021                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1022                                 break;
1023                         msleep(10);
1024                 }
1025
1026                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1027                         hw_dbg(hw, "EEPROM read did not pass.\n");
1028                         status = IXGBE_ERR_SFP_NOT_PRESENT;
1029                         goto out;
1030                 }
1031
1032                 /* Read data */
1033                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1034                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1035
1036                 *eeprom_data = (u8)(sfp_data >> 8);
1037         } else {
1038                 status = IXGBE_ERR_PHY;
1039                 goto out;
1040         }
1041
1042 out:
1043         return status;
1044 }
1045
1046 /**
1047  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1048  *  @hw: pointer to hardware structure
1049  *
1050  *  Determines physical layer capabilities of the current configuration.
1051  **/
1052 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1053 {
1054         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1055
1056         switch (hw->device_id) {
1057         case IXGBE_DEV_ID_82598:
1058                 /* Default device ID is mezzanine card KX/KX4 */
1059                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1060                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1061                 break;
1062         case IXGBE_DEV_ID_82598_BX:
1063                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1064         case IXGBE_DEV_ID_82598EB_CX4:
1065         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1066                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1067                 break;
1068         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1069                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1070                 break;
1071         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1072         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1073         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1074                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1075                 break;
1076         case IXGBE_DEV_ID_82598EB_XF_LR:
1077                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1078                 break;
1079         case IXGBE_DEV_ID_82598AT:
1080                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1081                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1082                 break;
1083         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1084                 hw->phy.ops.identify_sfp(hw);
1085
1086                 switch (hw->phy.sfp_type) {
1087                 case ixgbe_sfp_type_da_cu:
1088                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1089                         break;
1090                 case ixgbe_sfp_type_sr:
1091                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1092                         break;
1093                 case ixgbe_sfp_type_lr:
1094                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1095                         break;
1096                 default:
1097                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1098                         break;
1099                 }
1100                 break;
1101
1102         default:
1103                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1104                 break;
1105         }
1106
1107         return physical_layer;
1108 }
1109
1110 static struct ixgbe_mac_operations mac_ops_82598 = {
1111         .init_hw                = &ixgbe_init_hw_generic,
1112         .reset_hw               = &ixgbe_reset_hw_82598,
1113         .start_hw               = &ixgbe_start_hw_generic,
1114         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1115         .get_media_type         = &ixgbe_get_media_type_82598,
1116         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1117         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1118         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1119         .stop_adapter           = &ixgbe_stop_adapter_generic,
1120         .get_bus_info           = &ixgbe_get_bus_info_generic,
1121         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1122         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1123         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1124         .setup_link             = &ixgbe_setup_mac_link_82598,
1125         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1126         .check_link             = &ixgbe_check_mac_link_82598,
1127         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1128         .led_on                 = &ixgbe_led_on_generic,
1129         .led_off                = &ixgbe_led_off_generic,
1130         .blink_led_start        = &ixgbe_blink_led_start_82598,
1131         .blink_led_stop         = &ixgbe_blink_led_stop_82598,
1132         .set_rar                = &ixgbe_set_rar_generic,
1133         .clear_rar              = &ixgbe_clear_rar_generic,
1134         .set_vmdq               = &ixgbe_set_vmdq_82598,
1135         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1136         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1137         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1138         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1139         .enable_mc              = &ixgbe_enable_mc_generic,
1140         .disable_mc             = &ixgbe_disable_mc_generic,
1141         .clear_vfta             = &ixgbe_clear_vfta_82598,
1142         .set_vfta               = &ixgbe_set_vfta_82598,
1143         .setup_fc               = &ixgbe_setup_fc_82598,
1144 };
1145
1146 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1147         .init_params            = &ixgbe_init_eeprom_params_generic,
1148         .read                   = &ixgbe_read_eeprom_generic,
1149         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1150         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1151 };
1152
1153 static struct ixgbe_phy_operations phy_ops_82598 = {
1154         .identify               = &ixgbe_identify_phy_generic,
1155         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1156         .reset                  = &ixgbe_reset_phy_generic,
1157         .read_reg               = &ixgbe_read_phy_reg_generic,
1158         .write_reg              = &ixgbe_write_phy_reg_generic,
1159         .setup_link             = &ixgbe_setup_phy_link_generic,
1160         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1161         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1162 };
1163
1164 struct ixgbe_info ixgbe_82598_info = {
1165         .mac                    = ixgbe_mac_82598EB,
1166         .get_invariants         = &ixgbe_get_invariants_82598,
1167         .mac_ops                = &mac_ops_82598,
1168         .eeprom_ops             = &eeprom_ops_82598,
1169         .phy_ops                = &phy_ops_82598,
1170 };
1171