ipg: add __devexit annotation
[linux-2.6.git] / drivers / net / ipg.c
1 /*
2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3  *
4  * Copyright (C) 2003, 2007  IC Plus Corp
5  *
6  * Original Author:
7  *
8  *   Craig Rich
9  *   Sundance Technology, Inc.
10  *   www.sundanceti.com
11  *   craig_rich@sundanceti.com
12  *
13  * Current Maintainer:
14  *
15  *   Sorbica Shieh.
16  *   http://www.icplus.com.tw
17  *   sorbica@icplus.com.tw
18  *
19  *   Jesse Huang
20  *   http://www.icplus.com.tw
21  *   jesse@icplus.com.tw
22  */
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/mutex.h>
27
28 #include <asm/div64.h>
29
30 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32 #define IPG_RESET_MASK \
33         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35          IPG_AC_AUTO_INIT)
36
37 #define ipg_w32(val32, reg)     iowrite32((val32), ioaddr + (reg))
38 #define ipg_w16(val16, reg)     iowrite16((val16), ioaddr + (reg))
39 #define ipg_w8(val8, reg)       iowrite8((val8), ioaddr + (reg))
40
41 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
42 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
43 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
44
45 #define JUMBO_FRAME_4k_ONLY
46 enum {
47         netdev_io_size = 128
48 };
49
50 #include "ipg.h"
51 #define DRV_NAME        "ipg"
52
53 MODULE_AUTHOR("IC Plus Corp. 2003");
54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
55 MODULE_LICENSE("GPL");
56
57 /*
58  * Variable record -- index by leading revision/length
59  * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
60  */
61 static unsigned short DefaultPhyParam[] = {
62         /* 11/12/03 IP1000A v1-3 rev=0x40 */
63         /*--------------------------------------------------------------------------
64         (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
65                                  27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
66                                  31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7,  9, 0x0700,
67           --------------------------------------------------------------------------*/
68         /* 12/17/03 IP1000A v1-4 rev=0x40 */
69         (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
70             0x0000,
71         30, 0x005e, 9, 0x0700,
72         /* 01/09/04 IP1000A v1-5 rev=0x41 */
73         (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
74             0x0000,
75         30, 0x005e, 9, 0x0700,
76         0x0000
77 };
78
79 static const char *ipg_brand_name[] = {
80         "IC PLUS IP1000 1000/100/10 based NIC",
81         "Sundance Technology ST2021 based NIC",
82         "Tamarack Microelectronics TC9020/9021 based NIC",
83         "Tamarack Microelectronics TC9020/9021 based NIC",
84         "D-Link NIC",
85         "D-Link NIC IP1000A"
86 };
87
88 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
89         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
90         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
91         { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
92         { PCI_VDEVICE(DLINK,    0x9021), 3 },
93         { PCI_VDEVICE(DLINK,    0x4000), 4 },
94         { PCI_VDEVICE(DLINK,    0x4020), 5 },
95         { 0, }
96 };
97
98 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
99
100 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
101 {
102         struct ipg_nic_private *sp = netdev_priv(dev);
103         return sp->ioaddr;
104 }
105
106 #ifdef IPG_DEBUG
107 static void ipg_dump_rfdlist(struct net_device *dev)
108 {
109         struct ipg_nic_private *sp = netdev_priv(dev);
110         void __iomem *ioaddr = sp->ioaddr;
111         unsigned int i;
112         u32 offset;
113
114         IPG_DEBUG_MSG("_dump_rfdlist\n");
115
116         printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
117         printk(KERN_INFO "rx_dirty   = %2.2x\n", sp->rx_dirty);
118         printk(KERN_INFO "RFDList start address = %16.16lx\n",
119                (unsigned long) sp->rxd_map);
120         printk(KERN_INFO "RFDListPtr register   = %8.8x%8.8x\n",
121                ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
122
123         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
124                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
125                 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
126                        offset, (unsigned long) sp->rxd[i].next_desc);
127                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
128                 printk(KERN_INFO "%2.2x %4.4x RFS        = %16.16lx\n", i,
129                        offset, (unsigned long) sp->rxd[i].rfs);
130                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
131                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
132                        offset, (unsigned long) sp->rxd[i].frag_info);
133         }
134 }
135
136 static void ipg_dump_tfdlist(struct net_device *dev)
137 {
138         struct ipg_nic_private *sp = netdev_priv(dev);
139         void __iomem *ioaddr = sp->ioaddr;
140         unsigned int i;
141         u32 offset;
142
143         IPG_DEBUG_MSG("_dump_tfdlist\n");
144
145         printk(KERN_INFO "tx_current         = %2.2x\n", sp->tx_current);
146         printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
147         printk(KERN_INFO "TFDList start address = %16.16lx\n",
148                (unsigned long) sp->txd_map);
149         printk(KERN_INFO "TFDListPtr register   = %8.8x%8.8x\n",
150                ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
151
152         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
153                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
154                 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
155                        offset, (unsigned long) sp->txd[i].next_desc);
156
157                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
158                 printk(KERN_INFO "%2.2x %4.4x TFC        = %16.16lx\n", i,
159                        offset, (unsigned long) sp->txd[i].tfc);
160                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
161                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
162                        offset, (unsigned long) sp->txd[i].frag_info);
163         }
164 }
165 #endif
166
167 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
168 {
169         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
170         ndelay(IPG_PC_PHYCTRLWAIT_NS);
171 }
172
173 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
174 {
175         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
176         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
177 }
178
179 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
180 {
181         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
182
183         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
184 }
185
186 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
187 {
188         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
189                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
190 }
191
192 static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
193 {
194         u16 bit_data;
195
196         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
197
198         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
199
200         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
201
202         return bit_data;
203 }
204
205 /*
206  * Read a register from the Physical Layer device located
207  * on the IPG NIC, using the IPG PHYCTRL register.
208  */
209 static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
210 {
211         void __iomem *ioaddr = ipg_ioaddr(dev);
212         /*
213          * The GMII mangement frame structure for a read is as follows:
214          *
215          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
216          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
217          *
218          * <32 1s> = 32 consecutive logic 1 values
219          * A = bit of Physical Layer device address (MSB first)
220          * R = bit of register address (MSB first)
221          * z = High impedance state
222          * D = bit of read data (MSB first)
223          *
224          * Transmission order is 'Preamble' field first, bits transmitted
225          * left to right (first to last).
226          */
227         struct {
228                 u32 field;
229                 unsigned int len;
230         } p[] = {
231                 { GMII_PREAMBLE,        32 },   /* Preamble */
232                 { GMII_ST,              2  },   /* ST */
233                 { GMII_READ,            2  },   /* OP */
234                 { phy_id,               5  },   /* PHYAD */
235                 { phy_reg,              5  },   /* REGAD */
236                 { 0x0000,               2  },   /* TA */
237                 { 0x0000,               16 },   /* DATA */
238                 { 0x0000,               1  }    /* IDLE */
239         };
240         unsigned int i, j;
241         u8 polarity, data;
242
243         polarity  = ipg_r8(PHY_CTRL);
244         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
245
246         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
247         for (j = 0; j < 5; j++) {
248                 for (i = 0; i < p[j].len; i++) {
249                         /* For each variable length field, the MSB must be
250                          * transmitted first. Rotate through the field bits,
251                          * starting with the MSB, and move each bit into the
252                          * the 1st (2^1) bit position (this is the bit position
253                          * corresponding to the MgmtData bit of the PhyCtrl
254                          * register for the IPG).
255                          *
256                          * Example: ST = 01;
257                          *
258                          *          First write a '0' to bit 1 of the PhyCtrl
259                          *          register, then write a '1' to bit 1 of the
260                          *          PhyCtrl register.
261                          *
262                          * To do this, right shift the MSB of ST by the value:
263                          * [field length - 1 - #ST bits already written]
264                          * then left shift this result by 1.
265                          */
266                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
267                         data &= IPG_PC_MGMTDATA;
268                         data |= polarity | IPG_PC_MGMTDIR;
269
270                         ipg_drive_phy_ctl_low_high(ioaddr, data);
271                 }
272         }
273
274         send_three_state(ioaddr, polarity);
275
276         read_phy_bit(ioaddr, polarity);
277
278         /*
279          * For a read cycle, the bits for the next two fields (TA and
280          * DATA) are driven by the PHY (the IPG reads these bits).
281          */
282         for (i = 0; i < p[6].len; i++) {
283                 p[6].field |=
284                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
285         }
286
287         send_three_state(ioaddr, polarity);
288         send_three_state(ioaddr, polarity);
289         send_three_state(ioaddr, polarity);
290         send_end(ioaddr, polarity);
291
292         /* Return the value of the DATA field. */
293         return p[6].field;
294 }
295
296 /*
297  * Write to a register from the Physical Layer device located
298  * on the IPG NIC, using the IPG PHYCTRL register.
299  */
300 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
301 {
302         void __iomem *ioaddr = ipg_ioaddr(dev);
303         /*
304          * The GMII mangement frame structure for a read is as follows:
305          *
306          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
307          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
308          *
309          * <32 1s> = 32 consecutive logic 1 values
310          * A = bit of Physical Layer device address (MSB first)
311          * R = bit of register address (MSB first)
312          * z = High impedance state
313          * D = bit of write data (MSB first)
314          *
315          * Transmission order is 'Preamble' field first, bits transmitted
316          * left to right (first to last).
317          */
318         struct {
319                 u32 field;
320                 unsigned int len;
321         } p[] = {
322                 { GMII_PREAMBLE,        32 },   /* Preamble */
323                 { GMII_ST,              2  },   /* ST */
324                 { GMII_WRITE,           2  },   /* OP */
325                 { phy_id,               5  },   /* PHYAD */
326                 { phy_reg,              5  },   /* REGAD */
327                 { 0x0002,               2  },   /* TA */
328                 { val & 0xffff,         16 },   /* DATA */
329                 { 0x0000,               1  }    /* IDLE */
330         };
331         unsigned int i, j;
332         u8 polarity, data;
333
334         polarity  = ipg_r8(PHY_CTRL);
335         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
336
337         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
338         for (j = 0; j < 7; j++) {
339                 for (i = 0; i < p[j].len; i++) {
340                         /* For each variable length field, the MSB must be
341                          * transmitted first. Rotate through the field bits,
342                          * starting with the MSB, and move each bit into the
343                          * the 1st (2^1) bit position (this is the bit position
344                          * corresponding to the MgmtData bit of the PhyCtrl
345                          * register for the IPG).
346                          *
347                          * Example: ST = 01;
348                          *
349                          *          First write a '0' to bit 1 of the PhyCtrl
350                          *          register, then write a '1' to bit 1 of the
351                          *          PhyCtrl register.
352                          *
353                          * To do this, right shift the MSB of ST by the value:
354                          * [field length - 1 - #ST bits already written]
355                          * then left shift this result by 1.
356                          */
357                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
358                         data &= IPG_PC_MGMTDATA;
359                         data |= polarity | IPG_PC_MGMTDIR;
360
361                         ipg_drive_phy_ctl_low_high(ioaddr, data);
362                 }
363         }
364
365         /* The last cycle is a tri-state, so read from the PHY. */
366         for (j = 7; j < 8; j++) {
367                 for (i = 0; i < p[j].len; i++) {
368                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
369
370                         p[j].field |= ((ipg_r8(PHY_CTRL) &
371                                 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
372
373                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
374                 }
375         }
376 }
377
378 static void ipg_set_led_mode(struct net_device *dev)
379 {
380         struct ipg_nic_private *sp = netdev_priv(dev);
381         void __iomem *ioaddr = sp->ioaddr;
382         u32 mode;
383
384         mode = ipg_r32(ASIC_CTRL);
385         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
386
387         if ((sp->led_mode & 0x03) > 1)
388                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
389
390         if ((sp->led_mode & 0x01) == 1)
391                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
392
393         if ((sp->led_mode & 0x08) == 8)
394                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
395
396         ipg_w32(mode, ASIC_CTRL);
397 }
398
399 static void ipg_set_phy_set(struct net_device *dev)
400 {
401         struct ipg_nic_private *sp = netdev_priv(dev);
402         void __iomem *ioaddr = sp->ioaddr;
403         int physet;
404
405         physet = ipg_r8(PHY_SET);
406         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
407         physet |= ((sp->led_mode & 0x70) >> 4);
408         ipg_w8(physet, PHY_SET);
409 }
410
411 static int ipg_reset(struct net_device *dev, u32 resetflags)
412 {
413         /* Assert functional resets via the IPG AsicCtrl
414          * register as specified by the 'resetflags' input
415          * parameter.
416          */
417         void __iomem *ioaddr = ipg_ioaddr(dev);
418         unsigned int timeout_count = 0;
419
420         IPG_DEBUG_MSG("_reset\n");
421
422         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
423
424         /* Delay added to account for problem with 10Mbps reset. */
425         mdelay(IPG_AC_RESETWAIT);
426
427         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
428                 mdelay(IPG_AC_RESETWAIT);
429                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
430                         return -ETIME;
431         }
432         /* Set LED Mode in Asic Control */
433         ipg_set_led_mode(dev);
434
435         /* Set PHYSet Register Value */
436         ipg_set_phy_set(dev);
437         return 0;
438 }
439
440 /* Find the GMII PHY address. */
441 static int ipg_find_phyaddr(struct net_device *dev)
442 {
443         unsigned int phyaddr, i;
444
445         for (i = 0; i < 32; i++) {
446                 u32 status;
447
448                 /* Search for the correct PHY address among 32 possible. */
449                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
450
451                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
452                    GMII_PHY_ID1
453                  */
454
455                 status = mdio_read(dev, phyaddr, MII_BMSR);
456
457                 if ((status != 0xFFFF) && (status != 0))
458                         return phyaddr;
459         }
460
461         return 0x1f;
462 }
463
464 /*
465  * Configure IPG based on result of IEEE 802.3 PHY
466  * auto-negotiation.
467  */
468 static int ipg_config_autoneg(struct net_device *dev)
469 {
470         struct ipg_nic_private *sp = netdev_priv(dev);
471         void __iomem *ioaddr = sp->ioaddr;
472         unsigned int txflowcontrol;
473         unsigned int rxflowcontrol;
474         unsigned int fullduplex;
475         unsigned int gig;
476         u32 mac_ctrl_val;
477         u32 asicctrl;
478         u8 phyctrl;
479
480         IPG_DEBUG_MSG("_config_autoneg\n");
481
482         asicctrl = ipg_r32(ASIC_CTRL);
483         phyctrl = ipg_r8(PHY_CTRL);
484         mac_ctrl_val = ipg_r32(MAC_CTRL);
485
486         /* Set flags for use in resolving auto-negotation, assuming
487          * non-1000Mbps, half duplex, no flow control.
488          */
489         fullduplex = 0;
490         txflowcontrol = 0;
491         rxflowcontrol = 0;
492         gig = 0;
493
494         /* To accomodate a problem in 10Mbps operation,
495          * set a global flag if PHY running in 10Mbps mode.
496          */
497         sp->tenmbpsmode = 0;
498
499         printk(KERN_INFO "%s: Link speed = ", dev->name);
500
501         /* Determine actual speed of operation. */
502         switch (phyctrl & IPG_PC_LINK_SPEED) {
503         case IPG_PC_LINK_SPEED_10MBPS:
504                 printk("10Mbps.\n");
505                 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
506                        dev->name);
507                 sp->tenmbpsmode = 1;
508                 break;
509         case IPG_PC_LINK_SPEED_100MBPS:
510                 printk("100Mbps.\n");
511                 break;
512         case IPG_PC_LINK_SPEED_1000MBPS:
513                 printk("1000Mbps.\n");
514                 gig = 1;
515                 break;
516         default:
517                 printk("undefined!\n");
518                 return 0;
519         }
520
521         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
522                 fullduplex = 1;
523                 txflowcontrol = 1;
524                 rxflowcontrol = 1;
525         }
526
527         /* Configure full duplex, and flow control. */
528         if (fullduplex == 1) {
529                 /* Configure IPG for full duplex operation. */
530                 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
531
532                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
533
534                 if (txflowcontrol == 1) {
535                         printk("TX flow control");
536                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
537                 } else {
538                         printk("no TX flow control");
539                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
540                 }
541
542                 if (rxflowcontrol == 1) {
543                         printk(", RX flow control.");
544                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
545                 } else {
546                         printk(", no RX flow control.");
547                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
548                 }
549
550                 printk("\n");
551         } else {
552                 /* Configure IPG for half duplex operation. */
553                 printk(KERN_INFO "%s: setting half duplex, "
554                        "no TX flow control, no RX flow control.\n", dev->name);
555
556                 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
557                         ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
558                         ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
559         }
560         ipg_w32(mac_ctrl_val, MAC_CTRL);
561         return 0;
562 }
563
564 /* Determine and configure multicast operation and set
565  * receive mode for IPG.
566  */
567 static void ipg_nic_set_multicast_list(struct net_device *dev)
568 {
569         void __iomem *ioaddr = ipg_ioaddr(dev);
570         struct dev_mc_list *mc_list_ptr;
571         unsigned int hashindex;
572         u32 hashtable[2];
573         u8 receivemode;
574
575         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
576
577         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
578
579         if (dev->flags & IFF_PROMISC) {
580                 /* NIC to be configured in promiscuous mode. */
581                 receivemode = IPG_RM_RECEIVEALLFRAMES;
582         } else if ((dev->flags & IFF_ALLMULTI) ||
583                    (dev->flags & IFF_MULTICAST &
584                     (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
585                 /* NIC to be configured to receive all multicast
586                  * frames. */
587                 receivemode |= IPG_RM_RECEIVEMULTICAST;
588         } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
589                 /* NIC to be configured to receive selected
590                  * multicast addresses. */
591                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
592         }
593
594         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
595          * The IPG applies a cyclic-redundancy-check (the same CRC
596          * used to calculate the frame data FCS) to the destination
597          * address all incoming multicast frames whose destination
598          * address has the multicast bit set. The least significant
599          * 6 bits of the CRC result are used as an addressing index
600          * into the hash table. If the value of the bit addressed by
601          * this index is a 1, the frame is passed to the host system.
602          */
603
604         /* Clear hashtable. */
605         hashtable[0] = 0x00000000;
606         hashtable[1] = 0x00000000;
607
608         /* Cycle through all multicast addresses to filter. */
609         for (mc_list_ptr = dev->mc_list;
610              mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
611                 /* Calculate CRC result for each multicast address. */
612                 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
613                                      ETH_ALEN);
614
615                 /* Use only the least significant 6 bits. */
616                 hashindex = hashindex & 0x3F;
617
618                 /* Within "hashtable", set bit number "hashindex"
619                  * to a logic 1.
620                  */
621                 set_bit(hashindex, (void *)hashtable);
622         }
623
624         /* Write the value of the hashtable, to the 4, 16 bit
625          * HASHTABLE IPG registers.
626          */
627         ipg_w32(hashtable[0], HASHTABLE_0);
628         ipg_w32(hashtable[1], HASHTABLE_1);
629
630         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
631
632         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
633 }
634
635 static int ipg_io_config(struct net_device *dev)
636 {
637         void __iomem *ioaddr = ipg_ioaddr(dev);
638         u32 origmacctrl;
639         u32 restoremacctrl;
640
641         IPG_DEBUG_MSG("_io_config\n");
642
643         origmacctrl = ipg_r32(MAC_CTRL);
644
645         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
646
647         /* Based on compilation option, determine if FCS is to be
648          * stripped on receive frames by IPG.
649          */
650         if (!IPG_STRIP_FCS_ON_RX)
651                 restoremacctrl |= IPG_MC_RCV_FCS;
652
653         /* Determine if transmitter and/or receiver are
654          * enabled so we may restore MACCTRL correctly.
655          */
656         if (origmacctrl & IPG_MC_TX_ENABLED)
657                 restoremacctrl |= IPG_MC_TX_ENABLE;
658
659         if (origmacctrl & IPG_MC_RX_ENABLED)
660                 restoremacctrl |= IPG_MC_RX_ENABLE;
661
662         /* Transmitter and receiver must be disabled before setting
663          * IFSSelect.
664          */
665         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
666                 IPG_MC_RSVD_MASK, MAC_CTRL);
667
668         /* Now that transmitter and receiver are disabled, write
669          * to IFSSelect.
670          */
671         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
672
673         /* Set RECEIVEMODE register. */
674         ipg_nic_set_multicast_list(dev);
675
676         ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
677
678         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
679         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
680         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
681         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
682         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
683         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
684         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
685                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
686                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
687                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
688         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
689         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
690
691         /* IPG multi-frag frame bug workaround.
692          * Per silicon revision B3 eratta.
693          */
694         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
695
696         /* IPG TX poll now bug workaround.
697          * Per silicon revision B3 eratta.
698          */
699         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
700
701         /* IPG RX poll now bug workaround.
702          * Per silicon revision B3 eratta.
703          */
704         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
705
706         /* Now restore MACCTRL to original setting. */
707         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
708
709         /* Disable unused RMON statistics. */
710         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
711
712         /* Disable unused MIB statistics. */
713         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
714                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
715                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
716                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
717                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
718                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
719
720         return 0;
721 }
722
723 /*
724  * Create a receive buffer within system memory and update
725  * NIC private structure appropriately.
726  */
727 static int ipg_get_rxbuff(struct net_device *dev, int entry)
728 {
729         struct ipg_nic_private *sp = netdev_priv(dev);
730         struct ipg_rx *rxfd = sp->rxd + entry;
731         struct sk_buff *skb;
732         u64 rxfragsize;
733
734         IPG_DEBUG_MSG("_get_rxbuff\n");
735
736         skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
737         if (!skb) {
738                 sp->rx_buff[entry] = NULL;
739                 return -ENOMEM;
740         }
741
742         /* Adjust the data start location within the buffer to
743          * align IP address field to a 16 byte boundary.
744          */
745         skb_reserve(skb, NET_IP_ALIGN);
746
747         /* Associate the receive buffer with the IPG NIC. */
748         skb->dev = dev;
749
750         /* Save the address of the sk_buff structure. */
751         sp->rx_buff[entry] = skb;
752
753         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
754                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
755
756         /* Set the RFD fragment length. */
757         rxfragsize = IPG_RXFRAG_SIZE;
758         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
759
760         return 0;
761 }
762
763 static int init_rfdlist(struct net_device *dev)
764 {
765         struct ipg_nic_private *sp = netdev_priv(dev);
766         void __iomem *ioaddr = sp->ioaddr;
767         unsigned int i;
768
769         IPG_DEBUG_MSG("_init_rfdlist\n");
770
771         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
772                 struct ipg_rx *rxfd = sp->rxd + i;
773
774                 if (sp->rx_buff[i]) {
775                         pci_unmap_single(sp->pdev,
776                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
777                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
778                         dev_kfree_skb_irq(sp->rx_buff[i]);
779                         sp->rx_buff[i] = NULL;
780                 }
781
782                 /* Clear out the RFS field. */
783                 rxfd->rfs = 0x0000000000000000;
784
785                 if (ipg_get_rxbuff(dev, i) < 0) {
786                         /*
787                          * A receive buffer was not ready, break the
788                          * RFD list here.
789                          */
790                         IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
791
792                         /* Just in case we cannot allocate a single RFD.
793                          * Should not occur.
794                          */
795                         if (i == 0) {
796                                 printk(KERN_ERR "%s: No memory available"
797                                         " for RFD list.\n", dev->name);
798                                 return -ENOMEM;
799                         }
800                 }
801
802                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
803                         sizeof(struct ipg_rx)*(i + 1));
804         }
805         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
806
807         sp->rx_current = 0;
808         sp->rx_dirty = 0;
809
810         /* Write the location of the RFDList to the IPG. */
811         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
812         ipg_w32(0x00000000, RFD_LIST_PTR_1);
813
814         return 0;
815 }
816
817 static void init_tfdlist(struct net_device *dev)
818 {
819         struct ipg_nic_private *sp = netdev_priv(dev);
820         void __iomem *ioaddr = sp->ioaddr;
821         unsigned int i;
822
823         IPG_DEBUG_MSG("_init_tfdlist\n");
824
825         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
826                 struct ipg_tx *txfd = sp->txd + i;
827
828                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
829
830                 if (sp->tx_buff[i]) {
831                         dev_kfree_skb_irq(sp->tx_buff[i]);
832                         sp->tx_buff[i] = NULL;
833                 }
834
835                 txfd->next_desc = cpu_to_le64(sp->txd_map +
836                         sizeof(struct ipg_tx)*(i + 1));
837         }
838         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
839
840         sp->tx_current = 0;
841         sp->tx_dirty = 0;
842
843         /* Write the location of the TFDList to the IPG. */
844         IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
845                        (u32) sp->txd_map);
846         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
847         ipg_w32(0x00000000, TFD_LIST_PTR_1);
848
849         sp->reset_current_tfd = 1;
850 }
851
852 /*
853  * Free all transmit buffers which have already been transfered
854  * via DMA to the IPG.
855  */
856 static void ipg_nic_txfree(struct net_device *dev)
857 {
858         struct ipg_nic_private *sp = netdev_priv(dev);
859         unsigned int released, pending, dirty;
860
861         IPG_DEBUG_MSG("_nic_txfree\n");
862
863         pending = sp->tx_current - sp->tx_dirty;
864         dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
865
866         for (released = 0; released < pending; released++) {
867                 struct sk_buff *skb = sp->tx_buff[dirty];
868                 struct ipg_tx *txfd = sp->txd + dirty;
869
870                 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
871
872                 /* Look at each TFD's TFC field beginning
873                  * at the last freed TFD up to the current TFD.
874                  * If the TFDDone bit is set, free the associated
875                  * buffer.
876                  */
877                 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
878                         break;
879
880                 /* Free the transmit buffer. */
881                 if (skb) {
882                         pci_unmap_single(sp->pdev,
883                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
884                                 skb->len, PCI_DMA_TODEVICE);
885
886                         dev_kfree_skb_irq(skb);
887
888                         sp->tx_buff[dirty] = NULL;
889                 }
890                 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
891         }
892
893         sp->tx_dirty += released;
894
895         if (netif_queue_stopped(dev) &&
896             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
897                 netif_wake_queue(dev);
898         }
899 }
900
901 static void ipg_tx_timeout(struct net_device *dev)
902 {
903         struct ipg_nic_private *sp = netdev_priv(dev);
904         void __iomem *ioaddr = sp->ioaddr;
905
906         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
907                   IPG_AC_FIFO);
908
909         spin_lock_irq(&sp->lock);
910
911         /* Re-configure after DMA reset. */
912         if (ipg_io_config(dev) < 0) {
913                 printk(KERN_INFO "%s: Error during re-configuration.\n",
914                        dev->name);
915         }
916
917         init_tfdlist(dev);
918
919         spin_unlock_irq(&sp->lock);
920
921         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
922                 MAC_CTRL);
923 }
924
925 /*
926  * For TxComplete interrupts, free all transmit
927  * buffers which have already been transfered via DMA
928  * to the IPG.
929  */
930 static void ipg_nic_txcleanup(struct net_device *dev)
931 {
932         struct ipg_nic_private *sp = netdev_priv(dev);
933         void __iomem *ioaddr = sp->ioaddr;
934         unsigned int i;
935
936         IPG_DEBUG_MSG("_nic_txcleanup\n");
937
938         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
939                 /* Reading the TXSTATUS register clears the
940                  * TX_COMPLETE interrupt.
941                  */
942                 u32 txstatusdword = ipg_r32(TX_STATUS);
943
944                 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
945
946                 /* Check for Transmit errors. Error bits only valid if
947                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
948                  */
949                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
950                         break;
951
952                 /* If in 10Mbps mode, indicate transmit is ready. */
953                 if (sp->tenmbpsmode) {
954                         netif_wake_queue(dev);
955                 }
956
957                 /* Transmit error, increment stat counters. */
958                 if (txstatusdword & IPG_TS_TX_ERROR) {
959                         IPG_DEBUG_MSG("Transmit error.\n");
960                         sp->stats.tx_errors++;
961                 }
962
963                 /* Late collision, re-enable transmitter. */
964                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
965                         IPG_DEBUG_MSG("Late collision on transmit.\n");
966                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
967                                 IPG_MC_RSVD_MASK, MAC_CTRL);
968                 }
969
970                 /* Maximum collisions, re-enable transmitter. */
971                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
972                         IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
973                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
974                                 IPG_MC_RSVD_MASK, MAC_CTRL);
975                 }
976
977                 /* Transmit underrun, reset and re-enable
978                  * transmitter.
979                  */
980                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
981                         IPG_DEBUG_MSG("Transmitter underrun.\n");
982                         sp->stats.tx_fifo_errors++;
983                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
984                                   IPG_AC_NETWORK | IPG_AC_FIFO);
985
986                         /* Re-configure after DMA reset. */
987                         if (ipg_io_config(dev) < 0) {
988                                 printk(KERN_INFO
989                                        "%s: Error during re-configuration.\n",
990                                        dev->name);
991                         }
992                         init_tfdlist(dev);
993
994                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
995                                 IPG_MC_RSVD_MASK, MAC_CTRL);
996                 }
997         }
998
999         ipg_nic_txfree(dev);
1000 }
1001
1002 /* Provides statistical information about the IPG NIC. */
1003 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1004 {
1005         struct ipg_nic_private *sp = netdev_priv(dev);
1006         void __iomem *ioaddr = sp->ioaddr;
1007         u16 temp1;
1008         u16 temp2;
1009
1010         IPG_DEBUG_MSG("_nic_get_stats\n");
1011
1012         /* Check to see if the NIC has been initialized via nic_open,
1013          * before trying to read statistic registers.
1014          */
1015         if (!test_bit(__LINK_STATE_START, &dev->state))
1016                 return &sp->stats;
1017
1018         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1019         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1020         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1021         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1022         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1023         sp->stats.rx_errors += temp1;
1024         sp->stats.rx_missed_errors += temp1;
1025         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1026                 ipg_r32(IPG_LATECOLLISIONS);
1027         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1028         sp->stats.collisions += temp1;
1029         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1030         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1031                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1032         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1033
1034         /* detailed tx_errors */
1035         sp->stats.tx_carrier_errors += temp2;
1036
1037         /* detailed rx_errors */
1038         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1039                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1040         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1041
1042         /* Unutilized IPG statistic registers. */
1043         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1044
1045         return &sp->stats;
1046 }
1047
1048 /* Restore used receive buffers. */
1049 static int ipg_nic_rxrestore(struct net_device *dev)
1050 {
1051         struct ipg_nic_private *sp = netdev_priv(dev);
1052         const unsigned int curr = sp->rx_current;
1053         unsigned int dirty = sp->rx_dirty;
1054
1055         IPG_DEBUG_MSG("_nic_rxrestore\n");
1056
1057         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1058                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1059
1060                 /* rx_copybreak may poke hole here and there. */
1061                 if (sp->rx_buff[entry])
1062                         continue;
1063
1064                 /* Generate a new receive buffer to replace the
1065                  * current buffer (which will be released by the
1066                  * Linux system).
1067                  */
1068                 if (ipg_get_rxbuff(dev, entry) < 0) {
1069                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1070
1071                         break;
1072                 }
1073
1074                 /* Reset the RFS field. */
1075                 sp->rxd[entry].rfs = 0x0000000000000000;
1076         }
1077         sp->rx_dirty = dirty;
1078
1079         return 0;
1080 }
1081
1082 #ifdef JUMBO_FRAME
1083
1084 /* use jumboindex and jumbosize to control jumbo frame status
1085  * initial status is jumboindex=-1 and jumbosize=0
1086  * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1087  * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1088  * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1089  *               previous receiving and need to continue dumping the current one
1090  */
1091 enum {
1092         NORMAL_PACKET,
1093         ERROR_PACKET
1094 };
1095
1096 enum {
1097         FRAME_NO_START_NO_END   = 0,
1098         FRAME_WITH_START                = 1,
1099         FRAME_WITH_END          = 10,
1100         FRAME_WITH_START_WITH_END = 11
1101 };
1102
1103 inline void ipg_nic_rx_free_skb(struct net_device *dev)
1104 {
1105         struct ipg_nic_private *sp = netdev_priv(dev);
1106         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1107
1108         if (sp->rx_buff[entry]) {
1109                 struct ipg_rx *rxfd = sp->rxd + entry;
1110
1111                 pci_unmap_single(sp->pdev,
1112                         le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1113                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1114                 dev_kfree_skb_irq(sp->rx_buff[entry]);
1115                 sp->rx_buff[entry] = NULL;
1116         }
1117 }
1118
1119 inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1120 {
1121         struct ipg_nic_private *sp = netdev_priv(dev);
1122         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1123         int type = FRAME_NO_START_NO_END;
1124
1125         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1126                 type += FRAME_WITH_START;
1127         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1128                 type += FRAME_WITH_END;
1129         return type;
1130 }
1131
1132 inline int ipg_nic_rx_check_error(struct net_device *dev)
1133 {
1134         struct ipg_nic_private *sp = netdev_priv(dev);
1135         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1136         struct ipg_rx *rxfd = sp->rxd + entry;
1137
1138         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1139              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1140               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1141               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1142                 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1143                               (unsigned long) rxfd->rfs);
1144
1145                 /* Increment general receive error statistic. */
1146                 sp->stats.rx_errors++;
1147
1148                 /* Increment detailed receive error statistics. */
1149                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1150                         IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1151
1152                         sp->stats.rx_fifo_errors++;
1153                 }
1154
1155                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1156                         IPG_DEBUG_MSG("RX runt occured.\n");
1157                         sp->stats.rx_length_errors++;
1158                 }
1159
1160                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1161                  * error count handled by a IPG statistic register.
1162                  */
1163
1164                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1165                         IPG_DEBUG_MSG("RX alignment error occured.\n");
1166                         sp->stats.rx_frame_errors++;
1167                 }
1168
1169                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1170                  * handled by a IPG statistic register.
1171                  */
1172
1173                 /* Free the memory associated with the RX
1174                  * buffer since it is erroneous and we will
1175                  * not pass it to higher layer processes.
1176                  */
1177                 if (sp->rx_buff[entry]) {
1178                         pci_unmap_single(sp->pdev,
1179                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1180                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1181
1182                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1183                         sp->rx_buff[entry] = NULL;
1184                 }
1185                 return ERROR_PACKET;
1186         }
1187         return NORMAL_PACKET;
1188 }
1189
1190 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1191                                           struct ipg_nic_private *sp,
1192                                           struct ipg_rx *rxfd, unsigned entry)
1193 {
1194         struct ipg_jumbo *jumbo = &sp->jumbo;
1195         struct sk_buff *skb;
1196         int framelen;
1197
1198         if (jumbo->found_start) {
1199                 dev_kfree_skb_irq(jumbo->skb);
1200                 jumbo->found_start = 0;
1201                 jumbo->current_size = 0;
1202                 jumbo->skb = NULL;
1203         }
1204
1205         /* 1: found error, 0 no error */
1206         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1207                 return;
1208
1209         skb = sp->rx_buff[entry];
1210         if (!skb)
1211                 return;
1212
1213         /* accept this frame and send to upper layer */
1214         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1215         if (framelen > IPG_RXFRAG_SIZE)
1216                 framelen = IPG_RXFRAG_SIZE;
1217
1218         skb_put(skb, framelen);
1219         skb->protocol = eth_type_trans(skb, dev);
1220         skb->ip_summed = CHECKSUM_NONE;
1221         netif_rx(skb);
1222         dev->last_rx = jiffies;
1223         sp->rx_buff[entry] = NULL;
1224 }
1225
1226 static void ipg_nic_rx_with_start(struct net_device *dev,
1227                                   struct ipg_nic_private *sp,
1228                                   struct ipg_rx *rxfd, unsigned entry)
1229 {
1230         struct ipg_jumbo *jumbo = &sp->jumbo;
1231         struct pci_dev *pdev = sp->pdev;
1232         struct sk_buff *skb;
1233
1234         /* 1: found error, 0 no error */
1235         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1236                 return;
1237
1238         /* accept this frame and send to upper layer */
1239         skb = sp->rx_buff[entry];
1240         if (!skb)
1241                 return;
1242
1243         if (jumbo->found_start)
1244                 dev_kfree_skb_irq(jumbo->skb);
1245
1246         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1247                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1248
1249         skb_put(skb, IPG_RXFRAG_SIZE);
1250
1251         jumbo->found_start = 1;
1252         jumbo->current_size = IPG_RXFRAG_SIZE;
1253         jumbo->skb = skb;
1254
1255         sp->rx_buff[entry] = NULL;
1256         dev->last_rx = jiffies;
1257 }
1258
1259 static void ipg_nic_rx_with_end(struct net_device *dev,
1260                                 struct ipg_nic_private *sp,
1261                                 struct ipg_rx *rxfd, unsigned entry)
1262 {
1263         struct ipg_jumbo *jumbo = &sp->jumbo;
1264
1265         /* 1: found error, 0 no error */
1266         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1267                 struct sk_buff *skb = sp->rx_buff[entry];
1268
1269                 if (!skb)
1270                         return;
1271
1272                 if (jumbo->found_start) {
1273                         int framelen, endframelen;
1274
1275                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1276
1277                         endframeLen = framelen - jumbo->current_size;
1278                         /*
1279                         if (framelen > IPG_RXFRAG_SIZE)
1280                                 framelen=IPG_RXFRAG_SIZE;
1281                          */
1282                         if (framelen > IPG_RXSUPPORT_SIZE)
1283                                 dev_kfree_skb_irq(jumbo->skb);
1284                         else {
1285                                 memcpy(skb_put(jumbo->skb, endframeLen),
1286                                        skb->data, endframeLen);
1287
1288                                 jumbo->skb->protocol =
1289                                     eth_type_trans(jumbo->skb, dev);
1290
1291                                 jumbo->skb->ip_summed = CHECKSUM_NONE;
1292                                 netif_rx(jumbo->skb);
1293                         }
1294                 }
1295
1296                 dev->last_rx = jiffies;
1297                 jumbo->found_start = 0;
1298                 jumbo->current_size = 0;
1299                 jumbo->skb = NULL;
1300
1301                 ipg_nic_rx_free_skb(dev);
1302         } else {
1303                 dev_kfree_skb_irq(jumbo->skb);
1304                 jumbo->found_start = 0;
1305                 jumbo->current_size = 0;
1306                 jumbo->skb = NULL;
1307         }
1308 }
1309
1310 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1311                                        struct ipg_nic_private *sp,
1312                                        struct ipg_rx *rxfd, unsigned entry)
1313 {
1314         struct ipg_jumbo *jumbo = &sp->jumbo;
1315
1316         /* 1: found error, 0 no error */
1317         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1318                 struct sk_buff *skb = sp->rx_buff[entry];
1319
1320                 if (skb) {
1321                         if (jumbo->found_start) {
1322                                 jumbo->current_size += IPG_RXFRAG_SIZE;
1323                                 if (jumbo->current_size <= IPG_RXSUPPORT_SIZE) {
1324                                         memcpy(skb_put(jumbo->skb,
1325                                                        IPG_RXFRAG_SIZE),
1326                                                skb->data, IPG_RXFRAG_SIZE);
1327                                 }
1328                         }
1329                         dev->last_rx = jiffies;
1330                         ipg_nic_rx_free_skb(dev);
1331                 }
1332         } else {
1333                 dev_kfree_skb_irq(jumbo->skb);
1334                 jumbo->found_start = 0;
1335                 jumbo->current_size = 0;
1336                 jumbo->skb = NULL;
1337         }
1338 }
1339
1340 static int ipg_nic_rx(struct net_device *dev)
1341 {
1342         struct ipg_nic_private *sp = netdev_priv(dev);
1343         unsigned int curr = sp->rx_current;
1344         void __iomem *ioaddr = sp->ioaddr;
1345         unsigned int i;
1346
1347         IPG_DEBUG_MSG("_nic_rx\n");
1348
1349         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1350                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1351                 struct ipg_rx *rxfd = sp->rxd + entry;
1352
1353                 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1354                         break;
1355
1356                 switch (ipg_nic_rx_check_frame_type(dev)) {
1357                 case FRAME_WITH_START_WITH_END:
1358                         ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1359                         break;
1360                 case FRAME_WITH_START:
1361                         ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1362                         break;
1363                 case FRAME_WITH_END:
1364                         ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1365                         break;
1366                 case FRAME_NO_START_NO_END:
1367                         ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1368                         break;
1369                 }
1370         }
1371
1372         sp->rx_current = curr;
1373
1374         if (i == IPG_MAXRFDPROCESS_COUNT) {
1375                 /* There are more RFDs to process, however the
1376                  * allocated amount of RFD processing time has
1377                  * expired. Assert Interrupt Requested to make
1378                  * sure we come back to process the remaining RFDs.
1379                  */
1380                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1381         }
1382
1383         ipg_nic_rxrestore(dev);
1384
1385         return 0;
1386 }
1387
1388 #else
1389 static int ipg_nic_rx(struct net_device *dev)
1390 {
1391         /* Transfer received Ethernet frames to higher network layers. */
1392         struct ipg_nic_private *sp = netdev_priv(dev);
1393         unsigned int curr = sp->rx_current;
1394         void __iomem *ioaddr = sp->ioaddr;
1395         struct ipg_rx *rxfd;
1396         unsigned int i;
1397
1398         IPG_DEBUG_MSG("_nic_rx\n");
1399
1400 #define __RFS_MASK \
1401         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1402
1403         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1404                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1405                 struct sk_buff *skb = sp->rx_buff[entry];
1406                 unsigned int framelen;
1407
1408                 rxfd = sp->rxd + entry;
1409
1410                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1411                         break;
1412
1413                 /* Get received frame length. */
1414                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1415
1416                 /* Check for jumbo frame arrival with too small
1417                  * RXFRAG_SIZE.
1418                  */
1419                 if (framelen > IPG_RXFRAG_SIZE) {
1420                         IPG_DEBUG_MSG
1421                             ("RFS FrameLen > allocated fragment size.\n");
1422
1423                         framelen = IPG_RXFRAG_SIZE;
1424                 }
1425
1426                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1427                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1428                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1429                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1430
1431                         IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1432                                       (unsigned long int) rxfd->rfs);
1433
1434                         /* Increment general receive error statistic. */
1435                         sp->stats.rx_errors++;
1436
1437                         /* Increment detailed receive error statistics. */
1438                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1439                                 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1440                                 sp->stats.rx_fifo_errors++;
1441                         }
1442
1443                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1444                                 IPG_DEBUG_MSG("RX runt occured.\n");
1445                                 sp->stats.rx_length_errors++;
1446                         }
1447
1448                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1449                         /* Do nothing, error count handled by a IPG
1450                          * statistic register.
1451                          */
1452
1453                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1454                                 IPG_DEBUG_MSG("RX alignment error occured.\n");
1455                                 sp->stats.rx_frame_errors++;
1456                         }
1457
1458                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1459                         /* Do nothing, error count handled by a IPG
1460                          * statistic register.
1461                          */
1462
1463                         /* Free the memory associated with the RX
1464                          * buffer since it is erroneous and we will
1465                          * not pass it to higher layer processes.
1466                          */
1467                         if (skb) {
1468                                 __le64 info = rxfd->frag_info;
1469
1470                                 pci_unmap_single(sp->pdev,
1471                                         le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1472                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1473
1474                                 dev_kfree_skb_irq(skb);
1475                         }
1476                 } else {
1477
1478                         /* Adjust the new buffer length to accomodate the size
1479                          * of the received frame.
1480                          */
1481                         skb_put(skb, framelen);
1482
1483                         /* Set the buffer's protocol field to Ethernet. */
1484                         skb->protocol = eth_type_trans(skb, dev);
1485
1486                         /* The IPG encountered an error with (or
1487                          * there were no) IP/TCP/UDP checksums.
1488                          * This may or may not indicate an invalid
1489                          * IP/TCP/UDP frame was received. Let the
1490                          * upper layer decide.
1491                          */
1492                         skb->ip_summed = CHECKSUM_NONE;
1493
1494                         /* Hand off frame for higher layer processing.
1495                          * The function netif_rx() releases the sk_buff
1496                          * when processing completes.
1497                          */
1498                         netif_rx(skb);
1499
1500                         /* Record frame receive time (jiffies = Linux
1501                          * kernel current time stamp).
1502                          */
1503                         dev->last_rx = jiffies;
1504                 }
1505
1506                 /* Assure RX buffer is not reused by IPG. */
1507                 sp->rx_buff[entry] = NULL;
1508         }
1509
1510         /*
1511          * If there are more RFDs to proces and the allocated amount of RFD
1512          * processing time has expired, assert Interrupt Requested to make
1513          * sure we come back to process the remaining RFDs.
1514          */
1515         if (i == IPG_MAXRFDPROCESS_COUNT)
1516                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1517
1518 #ifdef IPG_DEBUG
1519         /* Check if the RFD list contained no receive frame data. */
1520         if (!i)
1521                 sp->EmptyRFDListCount++;
1522 #endif
1523         while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1524                !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1525                  (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1526                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1527
1528                 rxfd = sp->rxd + entry;
1529
1530                 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1531
1532                 /* An unexpected event, additional code needed to handle
1533                  * properly. So for the time being, just disregard the
1534                  * frame.
1535                  */
1536
1537                 /* Free the memory associated with the RX
1538                  * buffer since it is erroneous and we will
1539                  * not pass it to higher layer processes.
1540                  */
1541                 if (sp->rx_buff[entry]) {
1542                         pci_unmap_single(sp->pdev,
1543                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1544                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1545                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1546                 }
1547
1548                 /* Assure RX buffer is not reused by IPG. */
1549                 sp->rx_buff[entry] = NULL;
1550         }
1551
1552         sp->rx_current = curr;
1553
1554         /* Check to see if there are a minimum number of used
1555          * RFDs before restoring any (should improve performance.)
1556          */
1557         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1558                 ipg_nic_rxrestore(dev);
1559
1560         return 0;
1561 }
1562 #endif
1563
1564 static void ipg_reset_after_host_error(struct work_struct *work)
1565 {
1566         struct ipg_nic_private *sp =
1567                 container_of(work, struct ipg_nic_private, task.work);
1568         struct net_device *dev = sp->dev;
1569
1570         IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1571
1572         /*
1573          * Acknowledge HostError interrupt by resetting
1574          * IPG DMA and HOST.
1575          */
1576         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1577
1578         init_rfdlist(dev);
1579         init_tfdlist(dev);
1580
1581         if (ipg_io_config(dev) < 0) {
1582                 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1583                        dev->name);
1584                 schedule_delayed_work(&sp->task, HZ);
1585         }
1586 }
1587
1588 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1589 {
1590         struct net_device *dev = dev_inst;
1591         struct ipg_nic_private *sp = netdev_priv(dev);
1592         void __iomem *ioaddr = sp->ioaddr;
1593         unsigned int handled = 0;
1594         u16 status;
1595
1596         IPG_DEBUG_MSG("_interrupt_handler\n");
1597
1598 #ifdef JUMBO_FRAME
1599         ipg_nic_rxrestore(dev);
1600 #endif
1601         spin_lock(&sp->lock);
1602
1603         /* Get interrupt source information, and acknowledge
1604          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1605          * IntRequested, MacControlFrame, LinkEvent) interrupts
1606          * if issued. Also, all IPG interrupts are disabled by
1607          * reading IntStatusAck.
1608          */
1609         status = ipg_r16(INT_STATUS_ACK);
1610
1611         IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1612
1613         /* Shared IRQ of remove event. */
1614         if (!(status & IPG_IS_RSVD_MASK))
1615                 goto out_enable;
1616
1617         handled = 1;
1618
1619         if (unlikely(!netif_running(dev)))
1620                 goto out_unlock;
1621
1622         /* If RFDListEnd interrupt, restore all used RFDs. */
1623         if (status & IPG_IS_RFD_LIST_END) {
1624                 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1625
1626                 /* The RFD list end indicates an RFD was encountered
1627                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1628                  * (indicating the RFD is not read for use by the
1629                  * IPG.) Try to restore all RFDs.
1630                  */
1631                 ipg_nic_rxrestore(dev);
1632
1633 #ifdef IPG_DEBUG
1634                 /* Increment the RFDlistendCount counter. */
1635                 sp->RFDlistendCount++;
1636 #endif
1637         }
1638
1639         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1640          * IntRequested interrupt, process received frames. */
1641         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1642             (status & IPG_IS_RFD_LIST_END) ||
1643             (status & IPG_IS_RX_DMA_COMPLETE) ||
1644             (status & IPG_IS_INT_REQUESTED)) {
1645 #ifdef IPG_DEBUG
1646                 /* Increment the RFD list checked counter if interrupted
1647                  * only to check the RFD list. */
1648                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1649                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1650                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1651                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1652                                 IPG_IS_UPDATE_STATS)))
1653                         sp->RFDListCheckedCount++;
1654 #endif
1655
1656                 ipg_nic_rx(dev);
1657         }
1658
1659         /* If TxDMAComplete interrupt, free used TFDs. */
1660         if (status & IPG_IS_TX_DMA_COMPLETE)
1661                 ipg_nic_txfree(dev);
1662
1663         /* TxComplete interrupts indicate one of numerous actions.
1664          * Determine what action to take based on TXSTATUS register.
1665          */
1666         if (status & IPG_IS_TX_COMPLETE)
1667                 ipg_nic_txcleanup(dev);
1668
1669         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1670         if (status & IPG_IS_UPDATE_STATS)
1671                 ipg_nic_get_stats(dev);
1672
1673         /* If HostError interrupt, reset IPG. */
1674         if (status & IPG_IS_HOST_ERROR) {
1675                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1676
1677                 schedule_delayed_work(&sp->task, 0);
1678         }
1679
1680         /* If LinkEvent interrupt, resolve autonegotiation. */
1681         if (status & IPG_IS_LINK_EVENT) {
1682                 if (ipg_config_autoneg(dev) < 0)
1683                         printk(KERN_INFO "%s: Auto-negotiation error.\n",
1684                                dev->name);
1685         }
1686
1687         /* If MACCtrlFrame interrupt, do nothing. */
1688         if (status & IPG_IS_MAC_CTRL_FRAME)
1689                 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1690
1691         /* If RxComplete interrupt, do nothing. */
1692         if (status & IPG_IS_RX_COMPLETE)
1693                 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1694
1695         /* If RxEarly interrupt, do nothing. */
1696         if (status & IPG_IS_RX_EARLY)
1697                 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1698
1699 out_enable:
1700         /* Re-enable IPG interrupts. */
1701         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1702                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1703                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1704 out_unlock:
1705         spin_unlock(&sp->lock);
1706
1707         return IRQ_RETVAL(handled);
1708 }
1709
1710 static void ipg_rx_clear(struct ipg_nic_private *sp)
1711 {
1712         unsigned int i;
1713
1714         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1715                 if (sp->rx_buff[i]) {
1716                         struct ipg_rx *rxfd = sp->rxd + i;
1717
1718                         dev_kfree_skb_irq(sp->rx_buff[i]);
1719                         sp->rx_buff[i] = NULL;
1720                         pci_unmap_single(sp->pdev,
1721                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1722                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1723                 }
1724         }
1725 }
1726
1727 static void ipg_tx_clear(struct ipg_nic_private *sp)
1728 {
1729         unsigned int i;
1730
1731         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1732                 if (sp->tx_buff[i]) {
1733                         struct ipg_tx *txfd = sp->txd + i;
1734
1735                         pci_unmap_single(sp->pdev,
1736                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1737                                 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
1738
1739                         dev_kfree_skb_irq(sp->tx_buff[i]);
1740
1741                         sp->tx_buff[i] = NULL;
1742                 }
1743         }
1744 }
1745
1746 static int ipg_nic_open(struct net_device *dev)
1747 {
1748         struct ipg_nic_private *sp = netdev_priv(dev);
1749         void __iomem *ioaddr = sp->ioaddr;
1750         struct pci_dev *pdev = sp->pdev;
1751         int rc;
1752
1753         IPG_DEBUG_MSG("_nic_open\n");
1754
1755         sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1756
1757         /* Check for interrupt line conflicts, and request interrupt
1758          * line for IPG.
1759          *
1760          * IMPORTANT: Disable IPG interrupts prior to registering
1761          *            IRQ.
1762          */
1763         ipg_w16(0x0000, INT_ENABLE);
1764
1765         /* Register the interrupt line to be used by the IPG within
1766          * the Linux system.
1767          */
1768         rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1769                          dev->name, dev);
1770         if (rc < 0) {
1771                 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1772                        dev->name);
1773                 goto out;
1774         }
1775
1776         dev->irq = pdev->irq;
1777
1778         rc = -ENOMEM;
1779
1780         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1781                                      &sp->rxd_map, GFP_KERNEL);
1782         if (!sp->rxd)
1783                 goto err_free_irq_0;
1784
1785         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1786                                      &sp->txd_map, GFP_KERNEL);
1787         if (!sp->txd)
1788                 goto err_free_rx_1;
1789
1790         rc = init_rfdlist(dev);
1791         if (rc < 0) {
1792                 printk(KERN_INFO "%s: Error during configuration.\n",
1793                        dev->name);
1794                 goto err_free_tx_2;
1795         }
1796
1797         init_tfdlist(dev);
1798
1799         rc = ipg_io_config(dev);
1800         if (rc < 0) {
1801                 printk(KERN_INFO "%s: Error during configuration.\n",
1802                        dev->name);
1803                 goto err_release_tfdlist_3;
1804         }
1805
1806         /* Resolve autonegotiation. */
1807         if (ipg_config_autoneg(dev) < 0)
1808                 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1809
1810 #ifdef JUMBO_FRAME
1811         /* initialize JUMBO Frame control variable */
1812         sp->jumbo.found_start = 0;
1813         sp->jumbo.current_size = 0;
1814         sp->jumbo.skb = 0;
1815         dev->mtu = IPG_TXFRAG_SIZE;
1816 #endif
1817
1818         /* Enable transmit and receive operation of the IPG. */
1819         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1820                  IPG_MC_RSVD_MASK, MAC_CTRL);
1821
1822         netif_start_queue(dev);
1823 out:
1824         return rc;
1825
1826 err_release_tfdlist_3:
1827         ipg_tx_clear(sp);
1828         ipg_rx_clear(sp);
1829 err_free_tx_2:
1830         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1831 err_free_rx_1:
1832         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1833 err_free_irq_0:
1834         free_irq(pdev->irq, dev);
1835         goto out;
1836 }
1837
1838 static int ipg_nic_stop(struct net_device *dev)
1839 {
1840         struct ipg_nic_private *sp = netdev_priv(dev);
1841         void __iomem *ioaddr = sp->ioaddr;
1842         struct pci_dev *pdev = sp->pdev;
1843
1844         IPG_DEBUG_MSG("_nic_stop\n");
1845
1846         netif_stop_queue(dev);
1847
1848         IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1849         IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1850         IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1851         IPG_DUMPTFDLIST(dev);
1852
1853         do {
1854                 (void) ipg_r16(INT_STATUS_ACK);
1855
1856                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1857
1858                 synchronize_irq(pdev->irq);
1859         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1860
1861         ipg_rx_clear(sp);
1862
1863         ipg_tx_clear(sp);
1864
1865         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1866         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1867
1868         free_irq(pdev->irq, dev);
1869
1870         return 0;
1871 }
1872
1873 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1874 {
1875         struct ipg_nic_private *sp = netdev_priv(dev);
1876         void __iomem *ioaddr = sp->ioaddr;
1877         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1878         unsigned long flags;
1879         struct ipg_tx *txfd;
1880
1881         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1882
1883         /* If in 10Mbps mode, stop the transmit queue so
1884          * no more transmit frames are accepted.
1885          */
1886         if (sp->tenmbpsmode)
1887                 netif_stop_queue(dev);
1888
1889         if (sp->reset_current_tfd) {
1890                 sp->reset_current_tfd = 0;
1891                 entry = 0;
1892         }
1893
1894         txfd = sp->txd + entry;
1895
1896         sp->tx_buff[entry] = skb;
1897
1898         /* Clear all TFC fields, except TFDDONE. */
1899         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1900
1901         /* Specify the TFC field within the TFD. */
1902         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1903                 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1904                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1905
1906         /* Request TxComplete interrupts at an interval defined
1907          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1908          * Request TxComplete interrupt for every frame
1909          * if in 10Mbps mode to accomodate problem with 10Mbps
1910          * processing.
1911          */
1912         if (sp->tenmbpsmode)
1913                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1914         txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1915         /* Based on compilation option, determine if FCS is to be
1916          * appended to transmit frame by IPG.
1917          */
1918         if (!(IPG_APPEND_FCS_ON_TX))
1919                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1920
1921         /* Based on compilation option, determine if IP, TCP and/or
1922          * UDP checksums are to be added to transmit frame by IPG.
1923          */
1924         if (IPG_ADD_IPCHECKSUM_ON_TX)
1925                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1926
1927         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1928                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1929
1930         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1931                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1932
1933         /* Based on compilation option, determine if VLAN tag info is to be
1934          * inserted into transmit frame by IPG.
1935          */
1936         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1937                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1938                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1939                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1940                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1941         }
1942
1943         /* The fragment start location within system memory is defined
1944          * by the sk_buff structure's data field. The physical address
1945          * of this location within the system's virtual memory space
1946          * is determined using the IPG_HOST2BUS_MAP function.
1947          */
1948         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1949                 skb->len, PCI_DMA_TODEVICE));
1950
1951         /* The length of the fragment within system memory is defined by
1952          * the sk_buff structure's len field.
1953          */
1954         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1955                 ((u64) (skb->len & 0xffff) << 48));
1956
1957         /* Clear the TFDDone bit last to indicate the TFD is ready
1958          * for transfer to the IPG.
1959          */
1960         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1961
1962         spin_lock_irqsave(&sp->lock, flags);
1963
1964         sp->tx_current++;
1965
1966         mmiowb();
1967
1968         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1969
1970         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1971                 netif_stop_queue(dev);
1972
1973         spin_unlock_irqrestore(&sp->lock, flags);
1974
1975         return NETDEV_TX_OK;
1976 }
1977
1978 static void ipg_set_phy_default_param(unsigned char rev,
1979                                       struct net_device *dev, int phy_address)
1980 {
1981         unsigned short length;
1982         unsigned char revision;
1983         unsigned short *phy_param;
1984         unsigned short address, value;
1985
1986         phy_param = &DefaultPhyParam[0];
1987         length = *phy_param & 0x00FF;
1988         revision = (unsigned char)((*phy_param) >> 8);
1989         phy_param++;
1990         while (length != 0) {
1991                 if (rev == revision) {
1992                         while (length > 1) {
1993                                 address = *phy_param;
1994                                 value = *(phy_param + 1);
1995                                 phy_param += 2;
1996                                 mdio_write(dev, phy_address, address, value);
1997                                 length -= 4;
1998                         }
1999                         break;
2000                 } else {
2001                         phy_param += length / 2;
2002                         length = *phy_param & 0x00FF;
2003                         revision = (unsigned char)((*phy_param) >> 8);
2004                         phy_param++;
2005                 }
2006         }
2007 }
2008
2009 static int read_eeprom(struct net_device *dev, int eep_addr)
2010 {
2011         void __iomem *ioaddr = ipg_ioaddr(dev);
2012         unsigned int i;
2013         int ret = 0;
2014         u16 value;
2015
2016         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2017         ipg_w16(value, EEPROM_CTRL);
2018
2019         for (i = 0; i < 1000; i++) {
2020                 u16 data;
2021
2022                 mdelay(10);
2023                 data = ipg_r16(EEPROM_CTRL);
2024                 if (!(data & IPG_EC_EEPROM_BUSY)) {
2025                         ret = ipg_r16(EEPROM_DATA);
2026                         break;
2027                 }
2028         }
2029         return ret;
2030 }
2031
2032 static void ipg_init_mii(struct net_device *dev)
2033 {
2034         struct ipg_nic_private *sp = netdev_priv(dev);
2035         struct mii_if_info *mii_if = &sp->mii_if;
2036         int phyaddr;
2037
2038         mii_if->dev          = dev;
2039         mii_if->mdio_read    = mdio_read;
2040         mii_if->mdio_write   = mdio_write;
2041         mii_if->phy_id_mask  = 0x1f;
2042         mii_if->reg_num_mask = 0x1f;
2043
2044         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2045
2046         if (phyaddr != 0x1f) {
2047                 u16 mii_phyctrl, mii_1000cr;
2048                 u8 revisionid = 0;
2049
2050                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2051                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2052                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2053                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2054
2055                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2056
2057                 /* Set default phyparam */
2058                 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2059                 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2060
2061                 /* Reset PHY */
2062                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2063                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2064
2065         }
2066 }
2067
2068 static int ipg_hw_init(struct net_device *dev)
2069 {
2070         struct ipg_nic_private *sp = netdev_priv(dev);
2071         void __iomem *ioaddr = sp->ioaddr;
2072         unsigned int i;
2073         int rc;
2074
2075         /* Read/Write and Reset EEPROM Value */
2076         /* Read LED Mode Configuration from EEPROM */
2077         sp->led_mode = read_eeprom(dev, 6);
2078
2079         /* Reset all functions within the IPG. Do not assert
2080          * RST_OUT as not compatible with some PHYs.
2081          */
2082         rc = ipg_reset(dev, IPG_RESET_MASK);
2083         if (rc < 0)
2084                 goto out;
2085
2086         ipg_init_mii(dev);
2087
2088         /* Read MAC Address from EEPROM */
2089         for (i = 0; i < 3; i++)
2090                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2091
2092         for (i = 0; i < 3; i++)
2093                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2094
2095         /* Set station address in ethernet_device structure. */
2096         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2097         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2098         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2099         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2100         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2101         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2102 out:
2103         return rc;
2104 }
2105
2106 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2107 {
2108         struct ipg_nic_private *sp = netdev_priv(dev);
2109         int rc;
2110
2111         mutex_lock(&sp->mii_mutex);
2112         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2113         mutex_unlock(&sp->mii_mutex);
2114
2115         return rc;
2116 }
2117
2118 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2119 {
2120         /* Function to accomodate changes to Maximum Transfer Unit
2121          * (or MTU) of IPG NIC. Cannot use default function since
2122          * the default will not allow for MTU > 1500 bytes.
2123          */
2124
2125         IPG_DEBUG_MSG("_nic_change_mtu\n");
2126
2127         /* Check that the new MTU value is between 68 (14 byte header, 46
2128          * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2129          * corresponds to the MAXFRAMESIZE register in the IPG.
2130          */
2131         if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2132                 return -EINVAL;
2133
2134         dev->mtu = new_mtu;
2135
2136         return 0;
2137 }
2138
2139 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2140 {
2141         struct ipg_nic_private *sp = netdev_priv(dev);
2142         int rc;
2143
2144         mutex_lock(&sp->mii_mutex);
2145         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2146         mutex_unlock(&sp->mii_mutex);
2147
2148         return rc;
2149 }
2150
2151 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2152 {
2153         struct ipg_nic_private *sp = netdev_priv(dev);
2154         int rc;
2155
2156         mutex_lock(&sp->mii_mutex);
2157         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2158         mutex_unlock(&sp->mii_mutex);
2159
2160         return rc;
2161 }
2162
2163 static int ipg_nway_reset(struct net_device *dev)
2164 {
2165         struct ipg_nic_private *sp = netdev_priv(dev);
2166         int rc;
2167
2168         mutex_lock(&sp->mii_mutex);
2169         rc = mii_nway_restart(&sp->mii_if);
2170         mutex_unlock(&sp->mii_mutex);
2171
2172         return rc;
2173 }
2174
2175 static struct ethtool_ops ipg_ethtool_ops = {
2176         .get_settings = ipg_get_settings,
2177         .set_settings = ipg_set_settings,
2178         .nway_reset   = ipg_nway_reset,
2179 };
2180
2181 static void __devexit ipg_remove(struct pci_dev *pdev)
2182 {
2183         struct net_device *dev = pci_get_drvdata(pdev);
2184         struct ipg_nic_private *sp = netdev_priv(dev);
2185
2186         IPG_DEBUG_MSG("_remove\n");
2187
2188         /* Un-register Ethernet device. */
2189         unregister_netdev(dev);
2190
2191         pci_iounmap(pdev, sp->ioaddr);
2192
2193         pci_release_regions(pdev);
2194
2195         free_netdev(dev);
2196         pci_disable_device(pdev);
2197         pci_set_drvdata(pdev, NULL);
2198 }
2199
2200 static int __devinit ipg_probe(struct pci_dev *pdev,
2201                                const struct pci_device_id *id)
2202 {
2203         unsigned int i = id->driver_data;
2204         struct ipg_nic_private *sp;
2205         struct net_device *dev;
2206         void __iomem *ioaddr;
2207         int rc;
2208
2209         rc = pci_enable_device(pdev);
2210         if (rc < 0)
2211                 goto out;
2212
2213         printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2214
2215         pci_set_master(pdev);
2216
2217         rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2218         if (rc < 0) {
2219                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2220                 if (rc < 0) {
2221                         printk(KERN_ERR "%s: DMA config failed.\n",
2222                                pci_name(pdev));
2223                         goto err_disable_0;
2224                 }
2225         }
2226
2227         /*
2228          * Initialize net device.
2229          */
2230         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2231         if (!dev) {
2232                 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2233                 rc = -ENOMEM;
2234                 goto err_disable_0;
2235         }
2236
2237         sp = netdev_priv(dev);
2238         spin_lock_init(&sp->lock);
2239         mutex_init(&sp->mii_mutex);
2240
2241         /* Declare IPG NIC functions for Ethernet device methods.
2242          */
2243         dev->open = &ipg_nic_open;
2244         dev->stop = &ipg_nic_stop;
2245         dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2246         dev->get_stats = &ipg_nic_get_stats;
2247         dev->set_multicast_list = &ipg_nic_set_multicast_list;
2248         dev->do_ioctl = ipg_ioctl;
2249         dev->tx_timeout = ipg_tx_timeout;
2250         dev->change_mtu = &ipg_nic_change_mtu;
2251
2252         SET_NETDEV_DEV(dev, &pdev->dev);
2253         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2254
2255         rc = pci_request_regions(pdev, DRV_NAME);
2256         if (rc)
2257                 goto err_free_dev_1;
2258
2259         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2260         if (!ioaddr) {
2261                 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2262                 rc = -EIO;
2263                 goto err_release_regions_2;
2264         }
2265
2266         /* Save the pointer to the PCI device information. */
2267         sp->ioaddr = ioaddr;
2268         sp->pdev = pdev;
2269         sp->dev = dev;
2270
2271         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2272
2273         pci_set_drvdata(pdev, dev);
2274
2275         rc = ipg_hw_init(dev);
2276         if (rc < 0)
2277                 goto err_unmap_3;
2278
2279         rc = register_netdev(dev);
2280         if (rc < 0)
2281                 goto err_unmap_3;
2282
2283         printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2284 out:
2285         return rc;
2286
2287 err_unmap_3:
2288         pci_iounmap(pdev, ioaddr);
2289 err_release_regions_2:
2290         pci_release_regions(pdev);
2291 err_free_dev_1:
2292         free_netdev(dev);
2293 err_disable_0:
2294         pci_disable_device(pdev);
2295         goto out;
2296 }
2297
2298 static struct pci_driver ipg_pci_driver = {
2299         .name           = IPG_DRIVER_NAME,
2300         .id_table       = ipg_pci_tbl,
2301         .probe          = ipg_probe,
2302         .remove         = __devexit_p(ipg_remove),
2303 };
2304
2305 static int __init ipg_init_module(void)
2306 {
2307         return pci_register_driver(&ipg_pci_driver);
2308 }
2309
2310 static void __exit ipg_exit_module(void)
2311 {
2312         pci_unregister_driver(&ipg_pci_driver);
2313 }
2314
2315 module_init(ipg_init_module);
2316 module_exit(ipg_exit_module);