ipg: balance locking in irq handler
[linux-2.6.git] / drivers / net / ipg.c
1 /*
2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3  *
4  * Copyright (C) 2003, 2007  IC Plus Corp
5  *
6  * Original Author:
7  *
8  *   Craig Rich
9  *   Sundance Technology, Inc.
10  *   www.sundanceti.com
11  *   craig_rich@sundanceti.com
12  *
13  * Current Maintainer:
14  *
15  *   Sorbica Shieh.
16  *   http://www.icplus.com.tw
17  *   sorbica@icplus.com.tw
18  *
19  *   Jesse Huang
20  *   http://www.icplus.com.tw
21  *   jesse@icplus.com.tw
22  */
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/mutex.h>
27
28 #include <asm/div64.h>
29
30 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32 #define IPG_RESET_MASK \
33         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35          IPG_AC_AUTO_INIT)
36
37 #define ipg_w32(val32,reg)      iowrite32((val32), ioaddr + (reg))
38 #define ipg_w16(val16,reg)      iowrite16((val16), ioaddr + (reg))
39 #define ipg_w8(val8,reg)        iowrite8((val8), ioaddr + (reg))
40
41 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
42 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
43 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
44
45 #define JUMBO_FRAME_4k_ONLY
46 enum {
47         netdev_io_size = 128
48 };
49
50 #include "ipg.h"
51 #define DRV_NAME        "ipg"
52
53 MODULE_AUTHOR("IC Plus Corp. 2003");
54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver "
55                    DrvVer);
56 MODULE_LICENSE("GPL");
57
58 //variable record -- index by leading revision/length
59 //Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
60 static unsigned short DefaultPhyParam[] = {
61         // 11/12/03 IP1000A v1-3 rev=0x40
62         /*--------------------------------------------------------------------------
63         (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
64                                  27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
65                                  31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7,  9, 0x0700,
66           --------------------------------------------------------------------------*/
67         // 12/17/03 IP1000A v1-4 rev=0x40
68         (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
69             0x0000,
70         30, 0x005e, 9, 0x0700,
71         // 01/09/04 IP1000A v1-5 rev=0x41
72         (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
73             0x0000,
74         30, 0x005e, 9, 0x0700,
75         0x0000
76 };
77
78 static const char *ipg_brand_name[] = {
79         "IC PLUS IP1000 1000/100/10 based NIC",
80         "Sundance Technology ST2021 based NIC",
81         "Tamarack Microelectronics TC9020/9021 based NIC",
82         "Tamarack Microelectronics TC9020/9021 based NIC",
83         "D-Link NIC",
84         "D-Link NIC IP1000A"
85 };
86
87 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
88         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
89         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
90         { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
91         { PCI_VDEVICE(DLINK,    0x9021), 3 },
92         { PCI_VDEVICE(DLINK,    0x4000), 4 },
93         { PCI_VDEVICE(DLINK,    0x4020), 5 },
94         { 0, }
95 };
96
97 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
98
99 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
100 {
101         struct ipg_nic_private *sp = netdev_priv(dev);
102         return sp->ioaddr;
103 }
104
105 #ifdef IPG_DEBUG
106 static void ipg_dump_rfdlist(struct net_device *dev)
107 {
108         struct ipg_nic_private *sp = netdev_priv(dev);
109         void __iomem *ioaddr = sp->ioaddr;
110         unsigned int i;
111         u32 offset;
112
113         IPG_DEBUG_MSG("_dump_rfdlist\n");
114
115         printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
116         printk(KERN_INFO "rx_dirty   = %2.2x\n", sp->rx_dirty);
117         printk(KERN_INFO "RFDList start address = %16.16lx\n",
118                (unsigned long) sp->rxd_map);
119         printk(KERN_INFO "RFDListPtr register   = %8.8x%8.8x\n",
120                ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
121
122         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
123                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
124                 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
125                        offset, (unsigned long) sp->rxd[i].next_desc);
126                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
127                 printk(KERN_INFO "%2.2x %4.4x RFS        = %16.16lx\n", i,
128                        offset, (unsigned long) sp->rxd[i].rfs);
129                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
130                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
131                        offset, (unsigned long) sp->rxd[i].frag_info);
132         }
133 }
134
135 static void ipg_dump_tfdlist(struct net_device *dev)
136 {
137         struct ipg_nic_private *sp = netdev_priv(dev);
138         void __iomem *ioaddr = sp->ioaddr;
139         unsigned int i;
140         u32 offset;
141
142         IPG_DEBUG_MSG("_dump_tfdlist\n");
143
144         printk(KERN_INFO "tx_current         = %2.2x\n", sp->tx_current);
145         printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
146         printk(KERN_INFO "TFDList start address = %16.16lx\n",
147                (unsigned long) sp->txd_map);
148         printk(KERN_INFO "TFDListPtr register   = %8.8x%8.8x\n",
149                ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
150
151         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
152                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
153                 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
154                        offset, (unsigned long) sp->txd[i].next_desc);
155
156                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
157                 printk(KERN_INFO "%2.2x %4.4x TFC        = %16.16lx\n", i,
158                        offset, (unsigned long) sp->txd[i].tfc);
159                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
160                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
161                        offset, (unsigned long) sp->txd[i].frag_info);
162         }
163 }
164 #endif
165
166 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
167 {
168         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
169         ndelay(IPG_PC_PHYCTRLWAIT_NS);
170 }
171
172 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
173 {
174         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
175         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
176 }
177
178 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
179 {
180         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
181
182         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
183 }
184
185 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
186 {
187         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
188                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
189 }
190
191 static u16 read_phy_bit(void __iomem * ioaddr, u8 phyctrlpolarity)
192 {
193         u16 bit_data;
194
195         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
196
197         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
198
199         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
200
201         return bit_data;
202 }
203
204 /*
205  * Read a register from the Physical Layer device located
206  * on the IPG NIC, using the IPG PHYCTRL register.
207  */
208 static int mdio_read(struct net_device * dev, int phy_id, int phy_reg)
209 {
210         void __iomem *ioaddr = ipg_ioaddr(dev);
211         /*
212          * The GMII mangement frame structure for a read is as follows:
213          *
214          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
215          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
216          *
217          * <32 1s> = 32 consecutive logic 1 values
218          * A = bit of Physical Layer device address (MSB first)
219          * R = bit of register address (MSB first)
220          * z = High impedance state
221          * D = bit of read data (MSB first)
222          *
223          * Transmission order is 'Preamble' field first, bits transmitted
224          * left to right (first to last).
225          */
226         struct {
227                 u32 field;
228                 unsigned int len;
229         } p[] = {
230                 { GMII_PREAMBLE,        32 },   /* Preamble */
231                 { GMII_ST,              2  },   /* ST */
232                 { GMII_READ,            2  },   /* OP */
233                 { phy_id,               5  },   /* PHYAD */
234                 { phy_reg,              5  },   /* REGAD */
235                 { 0x0000,               2  },   /* TA */
236                 { 0x0000,               16 },   /* DATA */
237                 { 0x0000,               1  }    /* IDLE */
238         };
239         unsigned int i, j;
240         u8 polarity, data;
241
242         polarity  = ipg_r8(PHY_CTRL);
243         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
244
245         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
246         for (j = 0; j < 5; j++) {
247                 for (i = 0; i < p[j].len; i++) {
248                         /* For each variable length field, the MSB must be
249                          * transmitted first. Rotate through the field bits,
250                          * starting with the MSB, and move each bit into the
251                          * the 1st (2^1) bit position (this is the bit position
252                          * corresponding to the MgmtData bit of the PhyCtrl
253                          * register for the IPG).
254                          *
255                          * Example: ST = 01;
256                          *
257                          *          First write a '0' to bit 1 of the PhyCtrl
258                          *          register, then write a '1' to bit 1 of the
259                          *          PhyCtrl register.
260                          *
261                          * To do this, right shift the MSB of ST by the value:
262                          * [field length - 1 - #ST bits already written]
263                          * then left shift this result by 1.
264                          */
265                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
266                         data &= IPG_PC_MGMTDATA;
267                         data |= polarity | IPG_PC_MGMTDIR;
268
269                         ipg_drive_phy_ctl_low_high(ioaddr, data);
270                 }
271         }
272
273         send_three_state(ioaddr, polarity);
274
275         read_phy_bit(ioaddr, polarity);
276
277         /*
278          * For a read cycle, the bits for the next two fields (TA and
279          * DATA) are driven by the PHY (the IPG reads these bits).
280          */
281         for (i = 0; i < p[6].len; i++) {
282                 p[6].field |=
283                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
284         }
285
286         send_three_state(ioaddr, polarity);
287         send_three_state(ioaddr, polarity);
288         send_three_state(ioaddr, polarity);
289         send_end(ioaddr, polarity);
290
291         /* Return the value of the DATA field. */
292         return p[6].field;
293 }
294
295 /*
296  * Write to a register from the Physical Layer device located
297  * on the IPG NIC, using the IPG PHYCTRL register.
298  */
299 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
300 {
301         void __iomem *ioaddr = ipg_ioaddr(dev);
302         /*
303          * The GMII mangement frame structure for a read is as follows:
304          *
305          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
306          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
307          *
308          * <32 1s> = 32 consecutive logic 1 values
309          * A = bit of Physical Layer device address (MSB first)
310          * R = bit of register address (MSB first)
311          * z = High impedance state
312          * D = bit of write data (MSB first)
313          *
314          * Transmission order is 'Preamble' field first, bits transmitted
315          * left to right (first to last).
316          */
317         struct {
318                 u32 field;
319                 unsigned int len;
320         } p[] = {
321                 { GMII_PREAMBLE,        32 },   /* Preamble */
322                 { GMII_ST,              2  },   /* ST */
323                 { GMII_WRITE,           2  },   /* OP */
324                 { phy_id,               5  },   /* PHYAD */
325                 { phy_reg,              5  },   /* REGAD */
326                 { 0x0002,               2  },   /* TA */
327                 { val & 0xffff,         16 },   /* DATA */
328                 { 0x0000,               1  }    /* IDLE */
329         };
330         unsigned int i, j;
331         u8 polarity, data;
332
333         polarity  = ipg_r8(PHY_CTRL);
334         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
335
336         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
337         for (j = 0; j < 7; j++) {
338                 for (i = 0; i < p[j].len; i++) {
339                         /* For each variable length field, the MSB must be
340                          * transmitted first. Rotate through the field bits,
341                          * starting with the MSB, and move each bit into the
342                          * the 1st (2^1) bit position (this is the bit position
343                          * corresponding to the MgmtData bit of the PhyCtrl
344                          * register for the IPG).
345                          *
346                          * Example: ST = 01;
347                          *
348                          *          First write a '0' to bit 1 of the PhyCtrl
349                          *          register, then write a '1' to bit 1 of the
350                          *          PhyCtrl register.
351                          *
352                          * To do this, right shift the MSB of ST by the value:
353                          * [field length - 1 - #ST bits already written]
354                          * then left shift this result by 1.
355                          */
356                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
357                         data &= IPG_PC_MGMTDATA;
358                         data |= polarity | IPG_PC_MGMTDIR;
359
360                         ipg_drive_phy_ctl_low_high(ioaddr, data);
361                 }
362         }
363
364         /* The last cycle is a tri-state, so read from the PHY. */
365         for (j = 7; j < 8; j++) {
366                 for (i = 0; i < p[j].len; i++) {
367                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
368
369                         p[j].field |= ((ipg_r8(PHY_CTRL) &
370                                 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
371
372                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
373                 }
374         }
375 }
376
377 /* Set LED_Mode JES20040127EEPROM */
378 static void ipg_set_led_mode(struct net_device *dev)
379 {
380         struct ipg_nic_private *sp = netdev_priv(dev);
381         void __iomem *ioaddr = sp->ioaddr;
382         u32 mode;
383
384         mode = ipg_r32(ASIC_CTRL);
385         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
386
387         if ((sp->LED_Mode & 0x03) > 1)
388                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
389
390         if ((sp->LED_Mode & 0x01) == 1)
391                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
392
393         if ((sp->LED_Mode & 0x08) == 8)
394                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
395
396         ipg_w32(mode, ASIC_CTRL);
397 }
398
399 /* Set PHYSet JES20040127EEPROM */
400 static void ipg_set_phy_set(struct net_device *dev)
401 {
402         struct ipg_nic_private *sp = netdev_priv(dev);
403         void __iomem *ioaddr = sp->ioaddr;
404         int physet;
405
406         physet = ipg_r8(PHY_SET);
407         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
408         physet |= ((sp->LED_Mode & 0x70) >> 4);
409         ipg_w8(physet, PHY_SET);
410 }
411
412 static int ipg_reset(struct net_device *dev, u32 resetflags)
413 {
414         /* Assert functional resets via the IPG AsicCtrl
415          * register as specified by the 'resetflags' input
416          * parameter.
417          */
418         void __iomem *ioaddr = ipg_ioaddr(dev); //JES20040127EEPROM:
419         unsigned int timeout_count = 0;
420
421         IPG_DEBUG_MSG("_reset\n");
422
423         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
424
425         /* Delay added to account for problem with 10Mbps reset. */
426         mdelay(IPG_AC_RESETWAIT);
427
428         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
429                 mdelay(IPG_AC_RESETWAIT);
430                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
431                         return -ETIME;
432         }
433         /* Set LED Mode in Asic Control JES20040127EEPROM */
434         ipg_set_led_mode(dev);
435
436         /* Set PHYSet Register Value JES20040127EEPROM */
437         ipg_set_phy_set(dev);
438         return 0;
439 }
440
441 /* Find the GMII PHY address. */
442 static int ipg_find_phyaddr(struct net_device *dev)
443 {
444         unsigned int phyaddr, i;
445
446         for (i = 0; i < 32; i++) {
447                 u32 status;
448
449                 /* Search for the correct PHY address among 32 possible. */
450                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
451
452                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
453                    GMII_PHY_ID1
454                  */
455
456                 status = mdio_read(dev, phyaddr, MII_BMSR);
457
458                 if ((status != 0xFFFF) && (status != 0))
459                         return phyaddr;
460         }
461
462         return 0x1f;
463 }
464
465 /*
466  * Configure IPG based on result of IEEE 802.3 PHY
467  * auto-negotiation.
468  */
469 static int ipg_config_autoneg(struct net_device *dev)
470 {
471         struct ipg_nic_private *sp = netdev_priv(dev);
472         void __iomem *ioaddr = sp->ioaddr;
473         unsigned int txflowcontrol;
474         unsigned int rxflowcontrol;
475         unsigned int fullduplex;
476         unsigned int gig;
477         u32 mac_ctrl_val;
478         u32 asicctrl;
479         u8 phyctrl;
480
481         IPG_DEBUG_MSG("_config_autoneg\n");
482
483         asicctrl = ipg_r32(ASIC_CTRL);
484         phyctrl = ipg_r8(PHY_CTRL);
485         mac_ctrl_val = ipg_r32(MAC_CTRL);
486
487         /* Set flags for use in resolving auto-negotation, assuming
488          * non-1000Mbps, half duplex, no flow control.
489          */
490         fullduplex = 0;
491         txflowcontrol = 0;
492         rxflowcontrol = 0;
493         gig = 0;
494
495         /* To accomodate a problem in 10Mbps operation,
496          * set a global flag if PHY running in 10Mbps mode.
497          */
498         sp->tenmbpsmode = 0;
499
500         printk(KERN_INFO "%s: Link speed = ", dev->name);
501
502         /* Determine actual speed of operation. */
503         switch (phyctrl & IPG_PC_LINK_SPEED) {
504         case IPG_PC_LINK_SPEED_10MBPS:
505                 printk("10Mbps.\n");
506                 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
507                        dev->name);
508                 sp->tenmbpsmode = 1;
509                 break;
510         case IPG_PC_LINK_SPEED_100MBPS:
511                 printk("100Mbps.\n");
512                 break;
513         case IPG_PC_LINK_SPEED_1000MBPS:
514                 printk("1000Mbps.\n");
515                 gig = 1;
516                 break;
517         default:
518                 printk("undefined!\n");
519                 return 0;
520         }
521
522         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
523                 fullduplex = 1;
524                 txflowcontrol = 1;
525                 rxflowcontrol = 1;
526         }
527
528         /* Configure full duplex, and flow control. */
529         if (fullduplex == 1) {
530                 /* Configure IPG for full duplex operation. */
531                 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
532
533                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
534
535                 if (txflowcontrol == 1) {
536                         printk("TX flow control");
537                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
538                 } else {
539                         printk("no TX flow control");
540                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
541                 }
542
543                 if (rxflowcontrol == 1) {
544                         printk(", RX flow control.");
545                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
546                 } else {
547                         printk(", no RX flow control.");
548                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
549                 }
550
551                 printk("\n");
552         } else {
553                 /* Configure IPG for half duplex operation. */
554                 printk(KERN_INFO "%s: setting half duplex, "
555                        "no TX flow control, no RX flow control.\n", dev->name);
556
557                 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
558                         ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
559                         ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
560         }
561         ipg_w32(mac_ctrl_val, MAC_CTRL);
562         return 0;
563 }
564
565 /* Determine and configure multicast operation and set
566  * receive mode for IPG.
567  */
568 static void ipg_nic_set_multicast_list(struct net_device *dev)
569 {
570         void __iomem *ioaddr = ipg_ioaddr(dev);
571         struct dev_mc_list *mc_list_ptr;
572         unsigned int hashindex;
573         u32 hashtable[2];
574         u8 receivemode;
575
576         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
577
578         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
579
580         if (dev->flags & IFF_PROMISC) {
581                 /* NIC to be configured in promiscuous mode. */
582                 receivemode = IPG_RM_RECEIVEALLFRAMES;
583         } else if ((dev->flags & IFF_ALLMULTI) ||
584                    (dev->flags & IFF_MULTICAST &
585                     (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
586                 /* NIC to be configured to receive all multicast
587                  * frames. */
588                 receivemode |= IPG_RM_RECEIVEMULTICAST;
589         } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
590                 /* NIC to be configured to receive selected
591                  * multicast addresses. */
592                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
593         }
594
595         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
596          * The IPG applies a cyclic-redundancy-check (the same CRC
597          * used to calculate the frame data FCS) to the destination
598          * address all incoming multicast frames whose destination
599          * address has the multicast bit set. The least significant
600          * 6 bits of the CRC result are used as an addressing index
601          * into the hash table. If the value of the bit addressed by
602          * this index is a 1, the frame is passed to the host system.
603          */
604
605         /* Clear hashtable. */
606         hashtable[0] = 0x00000000;
607         hashtable[1] = 0x00000000;
608
609         /* Cycle through all multicast addresses to filter. */
610         for (mc_list_ptr = dev->mc_list;
611              mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
612                 /* Calculate CRC result for each multicast address. */
613                 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
614                                      ETH_ALEN);
615
616                 /* Use only the least significant 6 bits. */
617                 hashindex = hashindex & 0x3F;
618
619                 /* Within "hashtable", set bit number "hashindex"
620                  * to a logic 1.
621                  */
622                 set_bit(hashindex, (void *)hashtable);
623         }
624
625         /* Write the value of the hashtable, to the 4, 16 bit
626          * HASHTABLE IPG registers.
627          */
628         ipg_w32(hashtable[0], HASHTABLE_0);
629         ipg_w32(hashtable[1], HASHTABLE_1);
630
631         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
632
633         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
634 }
635
636 static int ipg_io_config(struct net_device *dev)
637 {
638         void __iomem *ioaddr = ipg_ioaddr(dev);
639         u32 origmacctrl;
640         u32 restoremacctrl;
641
642         IPG_DEBUG_MSG("_io_config\n");
643
644         origmacctrl = ipg_r32(MAC_CTRL);
645
646         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
647
648         /* Based on compilation option, determine if FCS is to be
649          * stripped on receive frames by IPG.
650          */
651         if (!IPG_STRIP_FCS_ON_RX)
652                 restoremacctrl |= IPG_MC_RCV_FCS;
653
654         /* Determine if transmitter and/or receiver are
655          * enabled so we may restore MACCTRL correctly.
656          */
657         if (origmacctrl & IPG_MC_TX_ENABLED)
658                 restoremacctrl |= IPG_MC_TX_ENABLE;
659
660         if (origmacctrl & IPG_MC_RX_ENABLED)
661                 restoremacctrl |= IPG_MC_RX_ENABLE;
662
663         /* Transmitter and receiver must be disabled before setting
664          * IFSSelect.
665          */
666         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
667                 IPG_MC_RSVD_MASK, MAC_CTRL);
668
669         /* Now that transmitter and receiver are disabled, write
670          * to IFSSelect.
671          */
672         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
673
674         /* Set RECEIVEMODE register. */
675         ipg_nic_set_multicast_list(dev);
676
677         ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
678
679         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
680         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
681         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
682         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
683         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
684         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
685         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
686                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
687                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
688                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
689         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
690         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
691
692         /* IPG multi-frag frame bug workaround.
693          * Per silicon revision B3 eratta.
694          */
695         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
696
697         /* IPG TX poll now bug workaround.
698          * Per silicon revision B3 eratta.
699          */
700         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
701
702         /* IPG RX poll now bug workaround.
703          * Per silicon revision B3 eratta.
704          */
705         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
706
707         /* Now restore MACCTRL to original setting. */
708         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
709
710         /* Disable unused RMON statistics. */
711         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
712
713         /* Disable unused MIB statistics. */
714         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
715                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
716                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
717                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
718                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
719                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
720
721         return 0;
722 }
723
724 /*
725  * Create a receive buffer within system memory and update
726  * NIC private structure appropriately.
727  */
728 static int ipg_get_rxbuff(struct net_device *dev, int entry)
729 {
730         struct ipg_nic_private *sp = netdev_priv(dev);
731         struct ipg_rx *rxfd = sp->rxd + entry;
732         struct sk_buff *skb;
733         u64 rxfragsize;
734
735         IPG_DEBUG_MSG("_get_rxbuff\n");
736
737         skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
738         if (!skb) {
739                 sp->RxBuff[entry] = NULL;
740                 return -ENOMEM;
741         }
742
743         /* Adjust the data start location within the buffer to
744          * align IP address field to a 16 byte boundary.
745          */
746         skb_reserve(skb, NET_IP_ALIGN);
747
748         /* Associate the receive buffer with the IPG NIC. */
749         skb->dev = dev;
750
751         /* Save the address of the sk_buff structure. */
752         sp->RxBuff[entry] = skb;
753
754         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
755                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
756
757         /* Set the RFD fragment length. */
758         rxfragsize = IPG_RXFRAG_SIZE;
759         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
760
761         return 0;
762 }
763
764 static int init_rfdlist(struct net_device *dev)
765 {
766         struct ipg_nic_private *sp = netdev_priv(dev);
767         void __iomem *ioaddr = sp->ioaddr;
768         unsigned int i;
769
770         IPG_DEBUG_MSG("_init_rfdlist\n");
771
772         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
773                 struct ipg_rx *rxfd = sp->rxd + i;
774
775                 if (sp->RxBuff[i]) {
776                         pci_unmap_single(sp->pdev,
777                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
778                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
779                         IPG_DEV_KFREE_SKB(sp->RxBuff[i]);
780                         sp->RxBuff[i] = NULL;
781                 }
782
783                 /* Clear out the RFS field. */
784                 rxfd->rfs = 0x0000000000000000;
785
786                 if (ipg_get_rxbuff(dev, i) < 0) {
787                         /*
788                          * A receive buffer was not ready, break the
789                          * RFD list here.
790                          */
791                         IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
792
793                         /* Just in case we cannot allocate a single RFD.
794                          * Should not occur.
795                          */
796                         if (i == 0) {
797                                 printk(KERN_ERR "%s: No memory available"
798                                         " for RFD list.\n", dev->name);
799                                 return -ENOMEM;
800                         }
801                 }
802
803                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
804                         sizeof(struct ipg_rx)*(i + 1));
805         }
806         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
807
808         sp->rx_current = 0;
809         sp->rx_dirty = 0;
810
811         /* Write the location of the RFDList to the IPG. */
812         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
813         ipg_w32(0x00000000, RFD_LIST_PTR_1);
814
815         return 0;
816 }
817
818 static void init_tfdlist(struct net_device *dev)
819 {
820         struct ipg_nic_private *sp = netdev_priv(dev);
821         void __iomem *ioaddr = sp->ioaddr;
822         unsigned int i;
823
824         IPG_DEBUG_MSG("_init_tfdlist\n");
825
826         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
827                 struct ipg_tx *txfd = sp->txd + i;
828
829                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
830
831                 if (sp->TxBuff[i]) {
832                         IPG_DEV_KFREE_SKB(sp->TxBuff[i]);
833                         sp->TxBuff[i] = NULL;
834                 }
835
836                 txfd->next_desc = cpu_to_le64(sp->txd_map +
837                         sizeof(struct ipg_tx)*(i + 1));
838         }
839         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
840
841         sp->tx_current = 0;
842         sp->tx_dirty = 0;
843
844         /* Write the location of the TFDList to the IPG. */
845         IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
846                        (u32) sp->txd_map);
847         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
848         ipg_w32(0x00000000, TFD_LIST_PTR_1);
849
850         sp->ResetCurrentTFD = 1;
851 }
852
853 /*
854  * Free all transmit buffers which have already been transfered
855  * via DMA to the IPG.
856  */
857 static void ipg_nic_txfree(struct net_device *dev)
858 {
859         struct ipg_nic_private *sp = netdev_priv(dev);
860         void __iomem *ioaddr = sp->ioaddr;
861         unsigned int curr;
862         u64 txd_map;
863         unsigned int released, pending;
864
865         txd_map = (u64)sp->txd_map;
866         curr = ipg_r32(TFD_LIST_PTR_0) -
867                 do_div(txd_map, sizeof(struct ipg_tx)) - 1;
868
869         IPG_DEBUG_MSG("_nic_txfree\n");
870
871         pending = sp->tx_current - sp->tx_dirty;
872
873         for (released = 0; released < pending; released++) {
874                 unsigned int dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
875                 struct sk_buff *skb = sp->TxBuff[dirty];
876                 struct ipg_tx *txfd = sp->txd + dirty;
877
878                 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
879
880                 /* Look at each TFD's TFC field beginning
881                  * at the last freed TFD up to the current TFD.
882                  * If the TFDDone bit is set, free the associated
883                  * buffer.
884                  */
885                 if (dirty == curr)
886                         break;
887
888                 /* Setup TFDDONE for compatible issue. */
889                 txfd->tfc |= cpu_to_le64(IPG_TFC_TFDDONE);
890
891                 /* Free the transmit buffer. */
892                 if (skb) {
893                         pci_unmap_single(sp->pdev,
894                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
895                                 skb->len, PCI_DMA_TODEVICE);
896
897                         IPG_DEV_KFREE_SKB(skb);
898
899                         sp->TxBuff[dirty] = NULL;
900                 }
901         }
902
903         sp->tx_dirty += released;
904
905         if (netif_queue_stopped(dev) &&
906             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
907                 netif_wake_queue(dev);
908         }
909 }
910
911 static void ipg_tx_timeout(struct net_device *dev)
912 {
913         struct ipg_nic_private *sp = netdev_priv(dev);
914         void __iomem *ioaddr = sp->ioaddr;
915
916         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
917                   IPG_AC_FIFO);
918
919         spin_lock_irq(&sp->lock);
920
921         /* Re-configure after DMA reset. */
922         if (ipg_io_config(dev) < 0) {
923                 printk(KERN_INFO "%s: Error during re-configuration.\n",
924                        dev->name);
925         }
926
927         init_tfdlist(dev);
928
929         spin_unlock_irq(&sp->lock);
930
931         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
932                 MAC_CTRL);
933 }
934
935 /*
936  * For TxComplete interrupts, free all transmit
937  * buffers which have already been transfered via DMA
938  * to the IPG.
939  */
940 static void ipg_nic_txcleanup(struct net_device *dev)
941 {
942         struct ipg_nic_private *sp = netdev_priv(dev);
943         void __iomem *ioaddr = sp->ioaddr;
944         unsigned int i;
945
946         IPG_DEBUG_MSG("_nic_txcleanup\n");
947
948         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
949                 /* Reading the TXSTATUS register clears the
950                  * TX_COMPLETE interrupt.
951                  */
952                 u32 txstatusdword = ipg_r32(TX_STATUS);
953
954                 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
955
956                 /* Check for Transmit errors. Error bits only valid if
957                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
958                  */
959                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
960                         break;
961
962                 /* If in 10Mbps mode, indicate transmit is ready. */
963                 if (sp->tenmbpsmode) {
964                         netif_wake_queue(dev);
965                 }
966
967                 /* Transmit error, increment stat counters. */
968                 if (txstatusdword & IPG_TS_TX_ERROR) {
969                         IPG_DEBUG_MSG("Transmit error.\n");
970                         sp->stats.tx_errors++;
971                 }
972
973                 /* Late collision, re-enable transmitter. */
974                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
975                         IPG_DEBUG_MSG("Late collision on transmit.\n");
976                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
977                                 IPG_MC_RSVD_MASK, MAC_CTRL);
978                 }
979
980                 /* Maximum collisions, re-enable transmitter. */
981                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
982                         IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
983                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
984                                 IPG_MC_RSVD_MASK, MAC_CTRL);
985                 }
986
987                 /* Transmit underrun, reset and re-enable
988                  * transmitter.
989                  */
990                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
991                         IPG_DEBUG_MSG("Transmitter underrun.\n");
992                         sp->stats.tx_fifo_errors++;
993                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
994                                   IPG_AC_NETWORK | IPG_AC_FIFO);
995
996                         /* Re-configure after DMA reset. */
997                         if (ipg_io_config(dev) < 0) {
998                                 printk(KERN_INFO
999                                        "%s: Error during re-configuration.\n",
1000                                        dev->name);
1001                         }
1002                         init_tfdlist(dev);
1003
1004                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
1005                                 IPG_MC_RSVD_MASK, MAC_CTRL);
1006                 }
1007         }
1008
1009         ipg_nic_txfree(dev);
1010 }
1011
1012 /* Provides statistical information about the IPG NIC. */
1013 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1014 {
1015         struct ipg_nic_private *sp = netdev_priv(dev);
1016         void __iomem *ioaddr = sp->ioaddr;
1017         u16 temp1;
1018         u16 temp2;
1019
1020         IPG_DEBUG_MSG("_nic_get_stats\n");
1021
1022         /* Check to see if the NIC has been initialized via nic_open,
1023          * before trying to read statistic registers.
1024          */
1025         if (!test_bit(__LINK_STATE_START, &dev->state))
1026                 return &sp->stats;
1027
1028         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1029         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1030         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1031         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1032         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1033         sp->stats.rx_errors += temp1;
1034         sp->stats.rx_missed_errors += temp1;
1035         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1036                 ipg_r32(IPG_LATECOLLISIONS);
1037         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1038         sp->stats.collisions += temp1;
1039         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1040         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1041                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1042         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1043
1044         /* detailed tx_errors */
1045         sp->stats.tx_carrier_errors += temp2;
1046
1047         /* detailed rx_errors */
1048         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1049                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1050         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1051
1052         /* Unutilized IPG statistic registers. */
1053         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1054
1055         return &sp->stats;
1056 }
1057
1058 /* Restore used receive buffers. */
1059 static int ipg_nic_rxrestore(struct net_device *dev)
1060 {
1061         struct ipg_nic_private *sp = netdev_priv(dev);
1062         const unsigned int curr = sp->rx_current;
1063         unsigned int dirty = sp->rx_dirty;
1064
1065         IPG_DEBUG_MSG("_nic_rxrestore\n");
1066
1067         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1068                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1069
1070                 /* rx_copybreak may poke hole here and there. */
1071                 if (sp->RxBuff[entry])
1072                         continue;
1073
1074                 /* Generate a new receive buffer to replace the
1075                  * current buffer (which will be released by the
1076                  * Linux system).
1077                  */
1078                 if (ipg_get_rxbuff(dev, entry) < 0) {
1079                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1080
1081                         break;
1082                 }
1083
1084                 /* Reset the RFS field. */
1085                 sp->rxd[entry].rfs = 0x0000000000000000;
1086         }
1087         sp->rx_dirty = dirty;
1088
1089         return 0;
1090 }
1091
1092 #ifdef JUMBO_FRAME
1093
1094 /* use jumboindex and jumbosize to control jumbo frame status
1095    initial status is jumboindex=-1 and jumbosize=0
1096    1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1097    2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1098    3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1099                 previous receiving and need to continue dumping the current one
1100 */
1101 enum {
1102         NormalPacket,
1103         ErrorPacket
1104 };
1105
1106 enum {
1107         Frame_NoStart_NoEnd     = 0,
1108         Frame_WithStart         = 1,
1109         Frame_WithEnd           = 10,
1110         Frame_WithStart_WithEnd = 11
1111 };
1112
1113 inline void ipg_nic_rx_free_skb(struct net_device *dev)
1114 {
1115         struct ipg_nic_private *sp = netdev_priv(dev);
1116         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1117
1118         if (sp->RxBuff[entry]) {
1119                 struct ipg_rx *rxfd = sp->rxd + entry;
1120
1121                 pci_unmap_single(sp->pdev,
1122                         le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1123                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1124                 IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1125                 sp->RxBuff[entry] = NULL;
1126         }
1127 }
1128
1129 inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1130 {
1131         struct ipg_nic_private *sp = netdev_priv(dev);
1132         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1133         int type = Frame_NoStart_NoEnd;
1134
1135         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1136                 type += Frame_WithStart;
1137         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1138                 type += Frame_WithEnd;
1139         return type;
1140 }
1141
1142 inline int ipg_nic_rx_check_error(struct net_device *dev)
1143 {
1144         struct ipg_nic_private *sp = netdev_priv(dev);
1145         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1146         struct ipg_rx *rxfd = sp->rxd + entry;
1147
1148         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1149              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1150               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1151               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1152                 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1153                               (unsigned long) rxfd->rfs);
1154
1155                 /* Increment general receive error statistic. */
1156                 sp->stats.rx_errors++;
1157
1158                 /* Increment detailed receive error statistics. */
1159                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1160                         IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1161
1162                         sp->stats.rx_fifo_errors++;
1163                 }
1164
1165                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1166                         IPG_DEBUG_MSG("RX runt occured.\n");
1167                         sp->stats.rx_length_errors++;
1168                 }
1169
1170                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1171                  * error count handled by a IPG statistic register.
1172                  */
1173
1174                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1175                         IPG_DEBUG_MSG("RX alignment error occured.\n");
1176                         sp->stats.rx_frame_errors++;
1177                 }
1178
1179                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1180                  * handled by a IPG statistic register.
1181                  */
1182
1183                 /* Free the memory associated with the RX
1184                  * buffer since it is erroneous and we will
1185                  * not pass it to higher layer processes.
1186                  */
1187                 if (sp->RxBuff[entry]) {
1188                         pci_unmap_single(sp->pdev,
1189                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1190                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1191
1192                         IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1193                         sp->RxBuff[entry] = NULL;
1194                 }
1195                 return ErrorPacket;
1196         }
1197         return NormalPacket;
1198 }
1199
1200 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1201                                           struct ipg_nic_private *sp,
1202                                           struct ipg_rx *rxfd, unsigned entry)
1203 {
1204         struct SJumbo *jumbo = &sp->Jumbo;
1205         struct sk_buff *skb;
1206         int framelen;
1207
1208         if (jumbo->FoundStart) {
1209                 IPG_DEV_KFREE_SKB(jumbo->skb);
1210                 jumbo->FoundStart = 0;
1211                 jumbo->CurrentSize = 0;
1212                 jumbo->skb = NULL;
1213         }
1214
1215         // 1: found error, 0 no error
1216         if (ipg_nic_rx_check_error(dev) != NormalPacket)
1217                 return;
1218
1219         skb = sp->RxBuff[entry];
1220         if (!skb)
1221                 return;
1222
1223         // accept this frame and send to upper layer
1224         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1225         if (framelen > IPG_RXFRAG_SIZE)
1226                 framelen = IPG_RXFRAG_SIZE;
1227
1228         skb_put(skb, framelen);
1229         skb->protocol = eth_type_trans(skb, dev);
1230         skb->ip_summed = CHECKSUM_NONE;
1231         netif_rx(skb);
1232         dev->last_rx = jiffies;
1233         sp->RxBuff[entry] = NULL;
1234 }
1235
1236 static void ipg_nic_rx_with_start(struct net_device *dev,
1237                                   struct ipg_nic_private *sp,
1238                                   struct ipg_rx *rxfd, unsigned entry)
1239 {
1240         struct SJumbo *jumbo = &sp->Jumbo;
1241         struct pci_dev *pdev = sp->pdev;
1242         struct sk_buff *skb;
1243
1244         // 1: found error, 0 no error
1245         if (ipg_nic_rx_check_error(dev) != NormalPacket)
1246                 return;
1247
1248         // accept this frame and send to upper layer
1249         skb = sp->RxBuff[entry];
1250         if (!skb)
1251                 return;
1252
1253         if (jumbo->FoundStart)
1254                 IPG_DEV_KFREE_SKB(jumbo->skb);
1255
1256         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1257                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1258
1259         skb_put(skb, IPG_RXFRAG_SIZE);
1260
1261         jumbo->FoundStart = 1;
1262         jumbo->CurrentSize = IPG_RXFRAG_SIZE;
1263         jumbo->skb = skb;
1264
1265         sp->RxBuff[entry] = NULL;
1266         dev->last_rx = jiffies;
1267 }
1268
1269 static void ipg_nic_rx_with_end(struct net_device *dev,
1270                                 struct ipg_nic_private *sp,
1271                                 struct ipg_rx *rxfd, unsigned entry)
1272 {
1273         struct SJumbo *jumbo = &sp->Jumbo;
1274
1275         //1: found error, 0 no error
1276         if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1277                 struct sk_buff *skb = sp->RxBuff[entry];
1278
1279                 if (!skb)
1280                         return;
1281
1282                 if (jumbo->FoundStart) {
1283                         int framelen, endframelen;
1284
1285                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1286
1287                         endframeLen = framelen - jumbo->CurrentSize;
1288                         /*
1289                         if (framelen > IPG_RXFRAG_SIZE)
1290                                 framelen=IPG_RXFRAG_SIZE;
1291                          */
1292                         if (framelen > IPG_RXSUPPORT_SIZE)
1293                                 IPG_DEV_KFREE_SKB(jumbo->skb);
1294                         else {
1295                                 memcpy(skb_put(jumbo->skb, endframeLen),
1296                                        skb->data, endframeLen);
1297
1298                                 jumbo->skb->protocol =
1299                                     eth_type_trans(jumbo->skb, dev);
1300
1301                                 jumbo->skb->ip_summed = CHECKSUM_NONE;
1302                                 netif_rx(jumbo->skb);
1303                         }
1304                 }
1305
1306                 dev->last_rx = jiffies;
1307                 jumbo->FoundStart = 0;
1308                 jumbo->CurrentSize = 0;
1309                 jumbo->skb = NULL;
1310
1311                 ipg_nic_rx_free_skb(dev);
1312         } else {
1313                 IPG_DEV_KFREE_SKB(jumbo->skb);
1314                 jumbo->FoundStart = 0;
1315                 jumbo->CurrentSize = 0;
1316                 jumbo->skb = NULL;
1317         }
1318 }
1319
1320 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1321                                        struct ipg_nic_private *sp,
1322                                        struct ipg_rx *rxfd, unsigned entry)
1323 {
1324         struct SJumbo *jumbo = &sp->Jumbo;
1325
1326         //1: found error, 0 no error
1327         if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1328                 struct sk_buff *skb = sp->RxBuff[entry];
1329
1330                 if (skb) {
1331                         if (jumbo->FoundStart) {
1332                                 jumbo->CurrentSize += IPG_RXFRAG_SIZE;
1333                                 if (jumbo->CurrentSize <= IPG_RXSUPPORT_SIZE) {
1334                                         memcpy(skb_put(jumbo->skb,
1335                                                        IPG_RXFRAG_SIZE),
1336                                                skb->data, IPG_RXFRAG_SIZE);
1337                                 }
1338                         }
1339                         dev->last_rx = jiffies;
1340                         ipg_nic_rx_free_skb(dev);
1341                 }
1342         } else {
1343                 IPG_DEV_KFREE_SKB(jumbo->skb);
1344                 jumbo->FoundStart = 0;
1345                 jumbo->CurrentSize = 0;
1346                 jumbo->skb = NULL;
1347         }
1348 }
1349
1350 static int ipg_nic_rx(struct net_device *dev)
1351 {
1352         struct ipg_nic_private *sp = netdev_priv(dev);
1353         unsigned int curr = sp->rx_current;
1354         void __iomem *ioaddr = sp->ioaddr;
1355         unsigned int i;
1356
1357         IPG_DEBUG_MSG("_nic_rx\n");
1358
1359         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1360                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1361                 struct ipg_rx *rxfd = sp->rxd + entry;
1362
1363                 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1364                         break;
1365
1366                 switch (ipg_nic_rx_check_frame_type(dev)) {
1367                 case Frame_WithStart_WithEnd:
1368                         ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1369                         break;
1370                 case Frame_WithStart:
1371                         ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1372                         break;
1373                 case Frame_WithEnd:
1374                         ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1375                         break;
1376                 case Frame_NoStart_NoEnd:
1377                         ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1378                         break;
1379                 }
1380         }
1381
1382         sp->rx_current = curr;
1383
1384         if (i == IPG_MAXRFDPROCESS_COUNT) {
1385                 /* There are more RFDs to process, however the
1386                  * allocated amount of RFD processing time has
1387                  * expired. Assert Interrupt Requested to make
1388                  * sure we come back to process the remaining RFDs.
1389                  */
1390                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1391         }
1392
1393         ipg_nic_rxrestore(dev);
1394
1395         return 0;
1396 }
1397
1398 #else
1399 static int ipg_nic_rx(struct net_device *dev)
1400 {
1401         /* Transfer received Ethernet frames to higher network layers. */
1402         struct ipg_nic_private *sp = netdev_priv(dev);
1403         unsigned int curr = sp->rx_current;
1404         void __iomem *ioaddr = sp->ioaddr;
1405         struct ipg_rx *rxfd;
1406         unsigned int i;
1407
1408         IPG_DEBUG_MSG("_nic_rx\n");
1409
1410 #define __RFS_MASK \
1411         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1412
1413         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1414                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1415                 struct sk_buff *skb = sp->RxBuff[entry];
1416                 unsigned int framelen;
1417
1418                 rxfd = sp->rxd + entry;
1419
1420                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1421                         break;
1422
1423                 /* Get received frame length. */
1424                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1425
1426                 /* Check for jumbo frame arrival with too small
1427                  * RXFRAG_SIZE.
1428                  */
1429                 if (framelen > IPG_RXFRAG_SIZE) {
1430                         IPG_DEBUG_MSG
1431                             ("RFS FrameLen > allocated fragment size.\n");
1432
1433                         framelen = IPG_RXFRAG_SIZE;
1434                 }
1435
1436                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1437                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1438                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1439                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1440
1441                         IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1442                                       (unsigned long int) rxfd->rfs);
1443
1444                         /* Increment general receive error statistic. */
1445                         sp->stats.rx_errors++;
1446
1447                         /* Increment detailed receive error statistics. */
1448                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1449                                 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1450                                 sp->stats.rx_fifo_errors++;
1451                         }
1452
1453                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1454                                 IPG_DEBUG_MSG("RX runt occured.\n");
1455                                 sp->stats.rx_length_errors++;
1456                         }
1457
1458                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1459                         /* Do nothing, error count handled by a IPG
1460                          * statistic register.
1461                          */
1462
1463                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1464                                 IPG_DEBUG_MSG("RX alignment error occured.\n");
1465                                 sp->stats.rx_frame_errors++;
1466                         }
1467
1468                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1469                         /* Do nothing, error count handled by a IPG
1470                          * statistic register.
1471                          */
1472
1473                         /* Free the memory associated with the RX
1474                          * buffer since it is erroneous and we will
1475                          * not pass it to higher layer processes.
1476                          */
1477                         if (skb) {
1478                                 __le64 info = rxfd->frag_info;
1479
1480                                 pci_unmap_single(sp->pdev,
1481                                         le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1482                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1483
1484                                 IPG_DEV_KFREE_SKB(skb);
1485                         }
1486                 } else {
1487
1488                         /* Adjust the new buffer length to accomodate the size
1489                          * of the received frame.
1490                          */
1491                         skb_put(skb, framelen);
1492
1493                         /* Set the buffer's protocol field to Ethernet. */
1494                         skb->protocol = eth_type_trans(skb, dev);
1495
1496                         /* If the frame contains an IP/TCP/UDP frame,
1497                          * determine if upper layer must check IP/TCP/UDP
1498                          * checksums.
1499                          *
1500                          * NOTE: DO NOT RELY ON THE TCP/UDP CHECKSUM
1501                          *       VERIFICATION FOR SILICON REVISIONS B3
1502                          *       AND EARLIER!
1503                          *
1504                          if ((le64_to_cpu(rxfd->rfs &
1505                              (IPG_RFS_TCPDETECTED | IPG_RFS_UDPDETECTED |
1506                               IPG_RFS_IPDETECTED))) &&
1507                             !(le64_to_cpu(rxfd->rfs &
1508                               (IPG_RFS_TCPERROR | IPG_RFS_UDPERROR |
1509                                IPG_RFS_IPERROR)))) {
1510                                  * Indicate IP checksums were performed
1511                                  * by the IPG.
1512                                  *
1513                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1514                          } else
1515                          */
1516                          {
1517                                 /* The IPG encountered an error with (or
1518                                  * there were no) IP/TCP/UDP checksums.
1519                                  * This may or may not indicate an invalid
1520                                  * IP/TCP/UDP frame was received. Let the
1521                                  * upper layer decide.
1522                                  */
1523                                 skb->ip_summed = CHECKSUM_NONE;
1524                         }
1525
1526                         /* Hand off frame for higher layer processing.
1527                          * The function netif_rx() releases the sk_buff
1528                          * when processing completes.
1529                          */
1530                         netif_rx(skb);
1531
1532                         /* Record frame receive time (jiffies = Linux
1533                          * kernel current time stamp).
1534                          */
1535                         dev->last_rx = jiffies;
1536                 }
1537
1538                 /* Assure RX buffer is not reused by IPG. */
1539                 sp->RxBuff[entry] = NULL;
1540         }
1541
1542         /*
1543          * If there are more RFDs to proces and the allocated amount of RFD
1544          * processing time has expired, assert Interrupt Requested to make
1545          * sure we come back to process the remaining RFDs.
1546          */
1547         if (i == IPG_MAXRFDPROCESS_COUNT)
1548                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1549
1550 #ifdef IPG_DEBUG
1551         /* Check if the RFD list contained no receive frame data. */
1552         if (!i)
1553                 sp->EmptyRFDListCount++;
1554 #endif
1555         while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1556                !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1557                  (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1558                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1559
1560                 rxfd = sp->rxd + entry;
1561
1562                 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1563
1564                 /* An unexpected event, additional code needed to handle
1565                  * properly. So for the time being, just disregard the
1566                  * frame.
1567                  */
1568
1569                 /* Free the memory associated with the RX
1570                  * buffer since it is erroneous and we will
1571                  * not pass it to higher layer processes.
1572                  */
1573                 if (sp->RxBuff[entry]) {
1574                         pci_unmap_single(sp->pdev,
1575                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1576                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1577                         IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1578                 }
1579
1580                 /* Assure RX buffer is not reused by IPG. */
1581                 sp->RxBuff[entry] = NULL;
1582         }
1583
1584         sp->rx_current = curr;
1585
1586         /* Check to see if there are a minimum number of used
1587          * RFDs before restoring any (should improve performance.)
1588          */
1589         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1590                 ipg_nic_rxrestore(dev);
1591
1592         return 0;
1593 }
1594 #endif
1595
1596 static void ipg_reset_after_host_error(struct work_struct *work)
1597 {
1598         struct ipg_nic_private *sp =
1599                 container_of(work, struct ipg_nic_private, task.work);
1600         struct net_device *dev = sp->dev;
1601
1602         IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1603
1604         /*
1605          * Acknowledge HostError interrupt by resetting
1606          * IPG DMA and HOST.
1607          */
1608         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1609
1610         init_rfdlist(dev);
1611         init_tfdlist(dev);
1612
1613         if (ipg_io_config(dev) < 0) {
1614                 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1615                        dev->name);
1616                 schedule_delayed_work(&sp->task, HZ);
1617         }
1618 }
1619
1620 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1621 {
1622         struct net_device *dev = dev_inst;
1623         struct ipg_nic_private *sp = netdev_priv(dev);
1624         void __iomem *ioaddr = sp->ioaddr;
1625         unsigned int handled = 0;
1626         u16 status;
1627
1628         IPG_DEBUG_MSG("_interrupt_handler\n");
1629
1630 #ifdef JUMBO_FRAME
1631         ipg_nic_rxrestore(dev);
1632 #endif
1633         spin_lock(&sp->lock);
1634
1635         /* Get interrupt source information, and acknowledge
1636          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1637          * IntRequested, MacControlFrame, LinkEvent) interrupts
1638          * if issued. Also, all IPG interrupts are disabled by
1639          * reading IntStatusAck.
1640          */
1641         status = ipg_r16(INT_STATUS_ACK);
1642
1643         IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1644
1645         /* Shared IRQ of remove event. */
1646         if (!(status & IPG_IS_RSVD_MASK))
1647                 goto out_enable;
1648
1649         handled = 1;
1650
1651         if (unlikely(!netif_running(dev)))
1652                 goto out_unlock;
1653
1654         /* If RFDListEnd interrupt, restore all used RFDs. */
1655         if (status & IPG_IS_RFD_LIST_END) {
1656                 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1657
1658                 /* The RFD list end indicates an RFD was encountered
1659                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1660                  * (indicating the RFD is not read for use by the
1661                  * IPG.) Try to restore all RFDs.
1662                  */
1663                 ipg_nic_rxrestore(dev);
1664
1665 #ifdef IPG_DEBUG
1666                 /* Increment the RFDlistendCount counter. */
1667                 sp->RFDlistendCount++;
1668 #endif
1669         }
1670
1671         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1672          * IntRequested interrupt, process received frames. */
1673         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1674             (status & IPG_IS_RFD_LIST_END) ||
1675             (status & IPG_IS_RX_DMA_COMPLETE) ||
1676             (status & IPG_IS_INT_REQUESTED)) {
1677 #ifdef IPG_DEBUG
1678                 /* Increment the RFD list checked counter if interrupted
1679                  * only to check the RFD list. */
1680                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1681                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1682                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1683                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1684                                 IPG_IS_UPDATE_STATS)))
1685                         sp->RFDListCheckedCount++;
1686 #endif
1687
1688                 ipg_nic_rx(dev);
1689         }
1690
1691         /* If TxDMAComplete interrupt, free used TFDs. */
1692         if (status & IPG_IS_TX_DMA_COMPLETE)
1693                 ipg_nic_txfree(dev);
1694
1695         /* TxComplete interrupts indicate one of numerous actions.
1696          * Determine what action to take based on TXSTATUS register.
1697          */
1698         if (status & IPG_IS_TX_COMPLETE)
1699                 ipg_nic_txcleanup(dev);
1700
1701         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1702         if (status & IPG_IS_UPDATE_STATS)
1703                 ipg_nic_get_stats(dev);
1704
1705         /* If HostError interrupt, reset IPG. */
1706         if (status & IPG_IS_HOST_ERROR) {
1707                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1708
1709                 schedule_delayed_work(&sp->task, 0);
1710         }
1711
1712         /* If LinkEvent interrupt, resolve autonegotiation. */
1713         if (status & IPG_IS_LINK_EVENT) {
1714                 if (ipg_config_autoneg(dev) < 0)
1715                         printk(KERN_INFO "%s: Auto-negotiation error.\n",
1716                                dev->name);
1717         }
1718
1719         /* If MACCtrlFrame interrupt, do nothing. */
1720         if (status & IPG_IS_MAC_CTRL_FRAME)
1721                 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1722
1723         /* If RxComplete interrupt, do nothing. */
1724         if (status & IPG_IS_RX_COMPLETE)
1725                 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1726
1727         /* If RxEarly interrupt, do nothing. */
1728         if (status & IPG_IS_RX_EARLY)
1729                 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1730
1731 out_enable:
1732         /* Re-enable IPG interrupts. */
1733         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1734                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1735                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1736 out_unlock:
1737         spin_unlock(&sp->lock);
1738
1739         return IRQ_RETVAL(handled);
1740 }
1741
1742 static void ipg_rx_clear(struct ipg_nic_private *sp)
1743 {
1744         unsigned int i;
1745
1746         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1747                 if (sp->RxBuff[i]) {
1748                         struct ipg_rx *rxfd = sp->rxd + i;
1749
1750                         IPG_DEV_KFREE_SKB(sp->RxBuff[i]);
1751                         sp->RxBuff[i] = NULL;
1752                         pci_unmap_single(sp->pdev,
1753                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1754                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1755                 }
1756         }
1757 }
1758
1759 static void ipg_tx_clear(struct ipg_nic_private *sp)
1760 {
1761         unsigned int i;
1762
1763         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1764                 if (sp->TxBuff[i]) {
1765                         struct ipg_tx *txfd = sp->txd + i;
1766
1767                         pci_unmap_single(sp->pdev,
1768                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1769                                 sp->TxBuff[i]->len, PCI_DMA_TODEVICE);
1770
1771                         IPG_DEV_KFREE_SKB(sp->TxBuff[i]);
1772
1773                         sp->TxBuff[i] = NULL;
1774                 }
1775         }
1776 }
1777
1778 static int ipg_nic_open(struct net_device *dev)
1779 {
1780         struct ipg_nic_private *sp = netdev_priv(dev);
1781         void __iomem *ioaddr = sp->ioaddr;
1782         struct pci_dev *pdev = sp->pdev;
1783         int rc;
1784
1785         IPG_DEBUG_MSG("_nic_open\n");
1786
1787         sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1788
1789         /* Check for interrupt line conflicts, and request interrupt
1790          * line for IPG.
1791          *
1792          * IMPORTANT: Disable IPG interrupts prior to registering
1793          *            IRQ.
1794          */
1795         ipg_w16(0x0000, INT_ENABLE);
1796
1797         /* Register the interrupt line to be used by the IPG within
1798          * the Linux system.
1799          */
1800         rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1801                          dev->name, dev);
1802         if (rc < 0) {
1803                 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1804                        dev->name);
1805                 goto out;
1806         }
1807
1808         dev->irq = pdev->irq;
1809
1810         rc = -ENOMEM;
1811
1812         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1813                                      &sp->rxd_map, GFP_KERNEL);
1814         if (!sp->rxd)
1815                 goto err_free_irq_0;
1816
1817         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1818                                      &sp->txd_map, GFP_KERNEL);
1819         if (!sp->txd)
1820                 goto err_free_rx_1;
1821
1822         rc = init_rfdlist(dev);
1823         if (rc < 0) {
1824                 printk(KERN_INFO "%s: Error during configuration.\n",
1825                        dev->name);
1826                 goto err_free_tx_2;
1827         }
1828
1829         init_tfdlist(dev);
1830
1831         rc = ipg_io_config(dev);
1832         if (rc < 0) {
1833                 printk(KERN_INFO "%s: Error during configuration.\n",
1834                        dev->name);
1835                 goto err_release_tfdlist_3;
1836         }
1837
1838         /* Resolve autonegotiation. */
1839         if (ipg_config_autoneg(dev) < 0)
1840                 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1841
1842 #ifdef JUMBO_FRAME
1843         /* initialize JUMBO Frame control variable */
1844         sp->Jumbo.FoundStart = 0;
1845         sp->Jumbo.CurrentSize = 0;
1846         sp->Jumbo.skb = 0;
1847         dev->mtu = IPG_TXFRAG_SIZE;
1848 #endif
1849
1850         /* Enable transmit and receive operation of the IPG. */
1851         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1852                  IPG_MC_RSVD_MASK, MAC_CTRL);
1853
1854         netif_start_queue(dev);
1855 out:
1856         return rc;
1857
1858 err_release_tfdlist_3:
1859         ipg_tx_clear(sp);
1860         ipg_rx_clear(sp);
1861 err_free_tx_2:
1862         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1863 err_free_rx_1:
1864         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1865 err_free_irq_0:
1866         free_irq(pdev->irq, dev);
1867         goto out;
1868 }
1869
1870 static int ipg_nic_stop(struct net_device *dev)
1871 {
1872         struct ipg_nic_private *sp = netdev_priv(dev);
1873         void __iomem *ioaddr = sp->ioaddr;
1874         struct pci_dev *pdev = sp->pdev;
1875
1876         IPG_DEBUG_MSG("_nic_stop\n");
1877
1878         netif_stop_queue(dev);
1879
1880         IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1881         IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1882         IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1883         IPG_DUMPTFDLIST(dev);
1884
1885         do {
1886                 (void) ipg_r16(INT_STATUS_ACK);
1887
1888                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1889
1890                 synchronize_irq(pdev->irq);
1891         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1892
1893         ipg_rx_clear(sp);
1894
1895         ipg_tx_clear(sp);
1896
1897         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1898         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1899
1900         free_irq(pdev->irq, dev);
1901
1902         return 0;
1903 }
1904
1905 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1906 {
1907         struct ipg_nic_private *sp = netdev_priv(dev);
1908         void __iomem *ioaddr = sp->ioaddr;
1909         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1910         unsigned long flags;
1911         struct ipg_tx *txfd;
1912
1913         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1914
1915         /* If in 10Mbps mode, stop the transmit queue so
1916          * no more transmit frames are accepted.
1917          */
1918         if (sp->tenmbpsmode)
1919                 netif_stop_queue(dev);
1920
1921         if (sp->ResetCurrentTFD) {
1922                 sp->ResetCurrentTFD = 0;
1923                 entry = 0;
1924         }
1925
1926         txfd = sp->txd + entry;
1927
1928         sp->TxBuff[entry] = skb;
1929
1930         /* Clear all TFC fields, except TFDDONE. */
1931         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1932
1933         /* Specify the TFC field within the TFD. */
1934         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1935                 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1936                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1937
1938         /* Request TxComplete interrupts at an interval defined
1939          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1940          * Request TxComplete interrupt for every frame
1941          * if in 10Mbps mode to accomodate problem with 10Mbps
1942          * processing.
1943          */
1944         if (sp->tenmbpsmode)
1945                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1946         else if (!((sp->tx_current - sp->tx_dirty + 1) >
1947             IPG_FRAMESBETWEENTXDMACOMPLETES)) {
1948                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1949         }
1950         /* Based on compilation option, determine if FCS is to be
1951          * appended to transmit frame by IPG.
1952          */
1953         if (!(IPG_APPEND_FCS_ON_TX))
1954                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1955
1956         /* Based on compilation option, determine if IP, TCP and/or
1957          * UDP checksums are to be added to transmit frame by IPG.
1958          */
1959         if (IPG_ADD_IPCHECKSUM_ON_TX)
1960                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1961
1962         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1963                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1964
1965         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1966                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1967
1968         /* Based on compilation option, determine if VLAN tag info is to be
1969          * inserted into transmit frame by IPG.
1970          */
1971         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1972                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1973                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1974                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1975                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1976         }
1977
1978         /* The fragment start location within system memory is defined
1979          * by the sk_buff structure's data field. The physical address
1980          * of this location within the system's virtual memory space
1981          * is determined using the IPG_HOST2BUS_MAP function.
1982          */
1983         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1984                 skb->len, PCI_DMA_TODEVICE));
1985
1986         /* The length of the fragment within system memory is defined by
1987          * the sk_buff structure's len field.
1988          */
1989         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1990                 ((u64) (skb->len & 0xffff) << 48));
1991
1992         /* Clear the TFDDone bit last to indicate the TFD is ready
1993          * for transfer to the IPG.
1994          */
1995         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1996
1997         spin_lock_irqsave(&sp->lock, flags);
1998
1999         sp->tx_current++;
2000
2001         mmiowb();
2002
2003         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
2004
2005         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
2006                 netif_wake_queue(dev);
2007
2008         spin_unlock_irqrestore(&sp->lock, flags);
2009
2010         return NETDEV_TX_OK;
2011 }
2012
2013 static void ipg_set_phy_default_param(unsigned char rev,
2014                                       struct net_device *dev, int phy_address)
2015 {
2016         unsigned short length;
2017         unsigned char revision;
2018         unsigned short *phy_param;
2019         unsigned short address, value;
2020
2021         phy_param = &DefaultPhyParam[0];
2022         length = *phy_param & 0x00FF;
2023         revision = (unsigned char)((*phy_param) >> 8);
2024         phy_param++;
2025         while (length != 0) {
2026                 if (rev == revision) {
2027                         while (length > 1) {
2028                                 address = *phy_param;
2029                                 value = *(phy_param + 1);
2030                                 phy_param += 2;
2031                                 mdio_write(dev, phy_address, address, value);
2032                                 length -= 4;
2033                         }
2034                         break;
2035                 } else {
2036                         phy_param += length / 2;
2037                         length = *phy_param & 0x00FF;
2038                         revision = (unsigned char)((*phy_param) >> 8);
2039                         phy_param++;
2040                 }
2041         }
2042 }
2043
2044 /* JES20040127EEPROM */
2045 static int read_eeprom(struct net_device *dev, int eep_addr)
2046 {
2047         void __iomem *ioaddr = ipg_ioaddr(dev);
2048         unsigned int i;
2049         int ret = 0;
2050         u16 value;
2051
2052         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2053         ipg_w16(value, EEPROM_CTRL);
2054
2055         for (i = 0; i < 1000; i++) {
2056                 u16 data;
2057
2058                 mdelay(10);
2059                 data = ipg_r16(EEPROM_CTRL);
2060                 if (!(data & IPG_EC_EEPROM_BUSY)) {
2061                         ret = ipg_r16(EEPROM_DATA);
2062                         break;
2063                 }
2064         }
2065         return ret;
2066 }
2067
2068 static void ipg_init_mii(struct net_device *dev)
2069 {
2070         struct ipg_nic_private *sp = netdev_priv(dev);
2071         struct mii_if_info *mii_if = &sp->mii_if;
2072         int phyaddr;
2073
2074         mii_if->dev          = dev;
2075         mii_if->mdio_read    = mdio_read;
2076         mii_if->mdio_write   = mdio_write;
2077         mii_if->phy_id_mask  = 0x1f;
2078         mii_if->reg_num_mask = 0x1f;
2079
2080         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2081
2082         if (phyaddr != 0x1f) {
2083                 u16 mii_phyctrl, mii_1000cr;
2084                 u8 revisionid = 0;
2085
2086                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2087                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2088                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2089                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2090
2091                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2092
2093                 /* Set default phyparam */
2094                 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2095                 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2096
2097                 /* Reset PHY */
2098                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2099                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2100
2101         }
2102 }
2103
2104 static int ipg_hw_init(struct net_device *dev)
2105 {
2106         struct ipg_nic_private *sp = netdev_priv(dev);
2107         void __iomem *ioaddr = sp->ioaddr;
2108         unsigned int i;
2109         int rc;
2110
2111         /* Read/Write and Reset EEPROM Value Jesse20040128EEPROM_VALUE */
2112         /* Read LED Mode Configuration from EEPROM */
2113         sp->LED_Mode = read_eeprom(dev, 6);
2114
2115         /* Reset all functions within the IPG. Do not assert
2116          * RST_OUT as not compatible with some PHYs.
2117          */
2118         rc = ipg_reset(dev, IPG_RESET_MASK);
2119         if (rc < 0)
2120                 goto out;
2121
2122         ipg_init_mii(dev);
2123
2124         /* Read MAC Address from EEPROM */
2125         for (i = 0; i < 3; i++)
2126                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2127
2128         for (i = 0; i < 3; i++)
2129                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2130
2131         /* Set station address in ethernet_device structure. */
2132         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2133         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2134         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2135         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2136         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2137         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2138 out:
2139         return rc;
2140 }
2141
2142 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2143 {
2144         struct ipg_nic_private *sp = netdev_priv(dev);
2145         int rc;
2146
2147         mutex_lock(&sp->mii_mutex);
2148         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2149         mutex_unlock(&sp->mii_mutex);
2150
2151         return rc;
2152 }
2153
2154 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2155 {
2156         /* Function to accomodate changes to Maximum Transfer Unit
2157          * (or MTU) of IPG NIC. Cannot use default function since
2158          * the default will not allow for MTU > 1500 bytes.
2159          */
2160
2161         IPG_DEBUG_MSG("_nic_change_mtu\n");
2162
2163         /* Check that the new MTU value is between 68 (14 byte header, 46
2164          * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2165          * corresponds to the MAXFRAMESIZE register in the IPG.
2166          */
2167         if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2168                 return -EINVAL;
2169
2170         dev->mtu = new_mtu;
2171
2172         return 0;
2173 }
2174
2175 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2176 {
2177         struct ipg_nic_private *sp = netdev_priv(dev);
2178         int rc;
2179
2180         mutex_lock(&sp->mii_mutex);
2181         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2182         mutex_unlock(&sp->mii_mutex);
2183
2184         return rc;
2185 }
2186
2187 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2188 {
2189         struct ipg_nic_private *sp = netdev_priv(dev);
2190         int rc;
2191
2192         mutex_lock(&sp->mii_mutex);
2193         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2194         mutex_unlock(&sp->mii_mutex);
2195
2196         return rc;
2197 }
2198
2199 static int ipg_nway_reset(struct net_device *dev)
2200 {
2201         struct ipg_nic_private *sp = netdev_priv(dev);
2202         int rc;
2203
2204         mutex_lock(&sp->mii_mutex);
2205         rc = mii_nway_restart(&sp->mii_if);
2206         mutex_unlock(&sp->mii_mutex);
2207
2208         return rc;
2209 }
2210
2211 static struct ethtool_ops ipg_ethtool_ops = {
2212         .get_settings = ipg_get_settings,
2213         .set_settings = ipg_set_settings,
2214         .nway_reset   = ipg_nway_reset,
2215 };
2216
2217 static void ipg_remove(struct pci_dev *pdev)
2218 {
2219         struct net_device *dev = pci_get_drvdata(pdev);
2220         struct ipg_nic_private *sp = netdev_priv(dev);
2221
2222         IPG_DEBUG_MSG("_remove\n");
2223
2224         /* Un-register Ethernet device. */
2225         unregister_netdev(dev);
2226
2227         pci_iounmap(pdev, sp->ioaddr);
2228
2229         pci_release_regions(pdev);
2230
2231         free_netdev(dev);
2232         pci_disable_device(pdev);
2233         pci_set_drvdata(pdev, NULL);
2234 }
2235
2236 static int __devinit ipg_probe(struct pci_dev *pdev,
2237                                const struct pci_device_id *id)
2238 {
2239         unsigned int i = id->driver_data;
2240         struct ipg_nic_private *sp;
2241         struct net_device *dev;
2242         void __iomem *ioaddr;
2243         int rc;
2244
2245         rc = pci_enable_device(pdev);
2246         if (rc < 0)
2247                 goto out;
2248
2249         printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2250
2251         pci_set_master(pdev);
2252
2253         rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2254         if (rc < 0) {
2255                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2256                 if (rc < 0) {
2257                         printk(KERN_ERR "%s: DMA config failed.\n",
2258                                pci_name(pdev));
2259                         goto err_disable_0;
2260                 }
2261         }
2262
2263         /*
2264          * Initialize net device.
2265          */
2266         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2267         if (!dev) {
2268                 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2269                 rc = -ENOMEM;
2270                 goto err_disable_0;
2271         }
2272
2273         sp = netdev_priv(dev);
2274         spin_lock_init(&sp->lock);
2275         mutex_init(&sp->mii_mutex);
2276
2277         /* Declare IPG NIC functions for Ethernet device methods.
2278          */
2279         dev->open = &ipg_nic_open;
2280         dev->stop = &ipg_nic_stop;
2281         dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2282         dev->get_stats = &ipg_nic_get_stats;
2283         dev->set_multicast_list = &ipg_nic_set_multicast_list;
2284         dev->do_ioctl = ipg_ioctl;
2285         dev->tx_timeout = ipg_tx_timeout;
2286         dev->change_mtu = &ipg_nic_change_mtu;
2287
2288         SET_NETDEV_DEV(dev, &pdev->dev);
2289         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2290
2291         rc = pci_request_regions(pdev, DRV_NAME);
2292         if (rc)
2293                 goto err_free_dev_1;
2294
2295         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2296         if (!ioaddr) {
2297                 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2298                 rc = -EIO;
2299                 goto err_release_regions_2;
2300         }
2301
2302         /* Save the pointer to the PCI device information. */
2303         sp->ioaddr = ioaddr;
2304         sp->pdev = pdev;
2305         sp->dev = dev;
2306
2307         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2308
2309         pci_set_drvdata(pdev, dev);
2310
2311         rc = ipg_hw_init(dev);
2312         if (rc < 0)
2313                 goto err_unmap_3;
2314
2315         rc = register_netdev(dev);
2316         if (rc < 0)
2317                 goto err_unmap_3;
2318
2319         printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2320 out:
2321         return rc;
2322
2323 err_unmap_3:
2324         pci_iounmap(pdev, ioaddr);
2325 err_release_regions_2:
2326         pci_release_regions(pdev);
2327 err_free_dev_1:
2328         free_netdev(dev);
2329 err_disable_0:
2330         pci_disable_device(pdev);
2331         goto out;
2332 }
2333
2334 static struct pci_driver ipg_pci_driver = {
2335         .name           = IPG_DRIVER_NAME,
2336         .id_table       = ipg_pci_tbl,
2337         .probe          = ipg_probe,
2338         .remove         = __devexit_p(ipg_remove),
2339 };
2340
2341 static int __init ipg_init_module(void)
2342 {
2343         return pci_register_driver(&ipg_pci_driver);
2344 }
2345
2346 static void __exit ipg_exit_module(void)
2347 {
2348         pci_unregister_driver(&ipg_pci_driver);
2349 }
2350
2351 module_init(ipg_init_module);
2352 module_exit(ipg_exit_module);