igb: remove 82576 quad adapter
[linux-2.6.git] / drivers / net / igb / e1000_hw.h
1 /*******************************************************************************
2
3   Intel(R) Gigabit Ethernet Linux driver
4   Copyright(c) 2007 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _E1000_HW_H_
29 #define _E1000_HW_H_
30
31 #include <linux/types.h>
32 #include <linux/delay.h>
33 #include <linux/io.h>
34
35 #include "e1000_mac.h"
36 #include "e1000_regs.h"
37 #include "e1000_defines.h"
38
39 struct e1000_hw;
40
41 #define E1000_DEV_ID_82576                    0x10C9
42 #define E1000_DEV_ID_82576_FIBER              0x10E6
43 #define E1000_DEV_ID_82576_SERDES             0x10E7
44 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
45 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
46 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
47
48 #define E1000_REVISION_2 2
49 #define E1000_REVISION_4 4
50
51 #define E1000_FUNC_1     1
52
53 enum e1000_mac_type {
54         e1000_undefined = 0,
55         e1000_82575,
56         e1000_82576,
57         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
58 };
59
60 enum e1000_media_type {
61         e1000_media_type_unknown = 0,
62         e1000_media_type_copper = 1,
63         e1000_media_type_fiber = 2,
64         e1000_media_type_internal_serdes = 3,
65         e1000_num_media_types
66 };
67
68 enum e1000_nvm_type {
69         e1000_nvm_unknown = 0,
70         e1000_nvm_none,
71         e1000_nvm_eeprom_spi,
72         e1000_nvm_eeprom_microwire,
73         e1000_nvm_flash_hw,
74         e1000_nvm_flash_sw
75 };
76
77 enum e1000_nvm_override {
78         e1000_nvm_override_none = 0,
79         e1000_nvm_override_spi_small,
80         e1000_nvm_override_spi_large,
81         e1000_nvm_override_microwire_small,
82         e1000_nvm_override_microwire_large
83 };
84
85 enum e1000_phy_type {
86         e1000_phy_unknown = 0,
87         e1000_phy_none,
88         e1000_phy_m88,
89         e1000_phy_igp,
90         e1000_phy_igp_2,
91         e1000_phy_gg82563,
92         e1000_phy_igp_3,
93         e1000_phy_ife,
94 };
95
96 enum e1000_bus_type {
97         e1000_bus_type_unknown = 0,
98         e1000_bus_type_pci,
99         e1000_bus_type_pcix,
100         e1000_bus_type_pci_express,
101         e1000_bus_type_reserved
102 };
103
104 enum e1000_bus_speed {
105         e1000_bus_speed_unknown = 0,
106         e1000_bus_speed_33,
107         e1000_bus_speed_66,
108         e1000_bus_speed_100,
109         e1000_bus_speed_120,
110         e1000_bus_speed_133,
111         e1000_bus_speed_2500,
112         e1000_bus_speed_5000,
113         e1000_bus_speed_reserved
114 };
115
116 enum e1000_bus_width {
117         e1000_bus_width_unknown = 0,
118         e1000_bus_width_pcie_x1,
119         e1000_bus_width_pcie_x2,
120         e1000_bus_width_pcie_x4 = 4,
121         e1000_bus_width_pcie_x8 = 8,
122         e1000_bus_width_32,
123         e1000_bus_width_64,
124         e1000_bus_width_reserved
125 };
126
127 enum e1000_1000t_rx_status {
128         e1000_1000t_rx_status_not_ok = 0,
129         e1000_1000t_rx_status_ok,
130         e1000_1000t_rx_status_undefined = 0xFF
131 };
132
133 enum e1000_rev_polarity {
134         e1000_rev_polarity_normal = 0,
135         e1000_rev_polarity_reversed,
136         e1000_rev_polarity_undefined = 0xFF
137 };
138
139 enum e1000_fc_type {
140         e1000_fc_none = 0,
141         e1000_fc_rx_pause,
142         e1000_fc_tx_pause,
143         e1000_fc_full,
144         e1000_fc_default = 0xFF
145 };
146
147
148 /* Receive Descriptor */
149 struct e1000_rx_desc {
150         __le64 buffer_addr; /* Address of the descriptor's data buffer */
151         __le16 length;      /* Length of data DMAed into data buffer */
152         __le16 csum;        /* Packet checksum */
153         u8  status;      /* Descriptor status */
154         u8  errors;      /* Descriptor Errors */
155         __le16 special;
156 };
157
158 /* Receive Descriptor - Extended */
159 union e1000_rx_desc_extended {
160         struct {
161                 __le64 buffer_addr;
162                 __le64 reserved;
163         } read;
164         struct {
165                 struct {
166                         __le32 mrq;              /* Multiple Rx Queues */
167                         union {
168                                 __le32 rss;            /* RSS Hash */
169                                 struct {
170                                         __le16 ip_id;  /* IP id */
171                                         __le16 csum;   /* Packet Checksum */
172                                 } csum_ip;
173                         } hi_dword;
174                 } lower;
175                 struct {
176                         __le32 status_error;     /* ext status/error */
177                         __le16 length;
178                         __le16 vlan;             /* VLAN tag */
179                 } upper;
180         } wb;  /* writeback */
181 };
182
183 #define MAX_PS_BUFFERS 4
184 /* Receive Descriptor - Packet Split */
185 union e1000_rx_desc_packet_split {
186         struct {
187                 /* one buffer for protocol header(s), three data buffers */
188                 __le64 buffer_addr[MAX_PS_BUFFERS];
189         } read;
190         struct {
191                 struct {
192                         __le32 mrq;              /* Multiple Rx Queues */
193                         union {
194                                 __le32 rss;              /* RSS Hash */
195                                 struct {
196                                         __le16 ip_id;    /* IP id */
197                                         __le16 csum;     /* Packet Checksum */
198                                 } csum_ip;
199                         } hi_dword;
200                 } lower;
201                 struct {
202                         __le32 status_error;     /* ext status/error */
203                         __le16 length0;          /* length of buffer 0 */
204                         __le16 vlan;             /* VLAN tag */
205                 } middle;
206                 struct {
207                         __le16 header_status;
208                         __le16 length[3];        /* length of buffers 1-3 */
209                 } upper;
210                 __le64 reserved;
211         } wb; /* writeback */
212 };
213
214 /* Transmit Descriptor */
215 struct e1000_tx_desc {
216         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
217         union {
218                 __le32 data;
219                 struct {
220                         __le16 length;    /* Data buffer length */
221                         u8 cso;        /* Checksum offset */
222                         u8 cmd;        /* Descriptor control */
223                 } flags;
224         } lower;
225         union {
226                 __le32 data;
227                 struct {
228                         u8 status;     /* Descriptor status */
229                         u8 css;        /* Checksum start */
230                         __le16 special;
231                 } fields;
232         } upper;
233 };
234
235 /* Offload Context Descriptor */
236 struct e1000_context_desc {
237         union {
238                 __le32 ip_config;
239                 struct {
240                         u8 ipcss;      /* IP checksum start */
241                         u8 ipcso;      /* IP checksum offset */
242                         __le16 ipcse;     /* IP checksum end */
243                 } ip_fields;
244         } lower_setup;
245         union {
246                 __le32 tcp_config;
247                 struct {
248                         u8 tucss;      /* TCP checksum start */
249                         u8 tucso;      /* TCP checksum offset */
250                         __le16 tucse;     /* TCP checksum end */
251                 } tcp_fields;
252         } upper_setup;
253         __le32 cmd_and_length;
254         union {
255                 __le32 data;
256                 struct {
257                         u8 status;     /* Descriptor status */
258                         u8 hdr_len;    /* Header length */
259                         __le16 mss;       /* Maximum segment size */
260                 } fields;
261         } tcp_seg_setup;
262 };
263
264 /* Offload data descriptor */
265 struct e1000_data_desc {
266         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
267         union {
268                 __le32 data;
269                 struct {
270                         __le16 length;    /* Data buffer length */
271                         u8 typ_len_ext;
272                         u8 cmd;
273                 } flags;
274         } lower;
275         union {
276                 __le32 data;
277                 struct {
278                         u8 status;     /* Descriptor status */
279                         u8 popts;      /* Packet Options */
280                         __le16 special;
281                 } fields;
282         } upper;
283 };
284
285 /* Statistics counters collected by the MAC */
286 struct e1000_hw_stats {
287         u64 crcerrs;
288         u64 algnerrc;
289         u64 symerrs;
290         u64 rxerrc;
291         u64 mpc;
292         u64 scc;
293         u64 ecol;
294         u64 mcc;
295         u64 latecol;
296         u64 colc;
297         u64 dc;
298         u64 tncrs;
299         u64 sec;
300         u64 cexterr;
301         u64 rlec;
302         u64 xonrxc;
303         u64 xontxc;
304         u64 xoffrxc;
305         u64 xofftxc;
306         u64 fcruc;
307         u64 prc64;
308         u64 prc127;
309         u64 prc255;
310         u64 prc511;
311         u64 prc1023;
312         u64 prc1522;
313         u64 gprc;
314         u64 bprc;
315         u64 mprc;
316         u64 gptc;
317         u64 gorc;
318         u64 gotc;
319         u64 rnbc;
320         u64 ruc;
321         u64 rfc;
322         u64 roc;
323         u64 rjc;
324         u64 mgprc;
325         u64 mgpdc;
326         u64 mgptc;
327         u64 tor;
328         u64 tot;
329         u64 tpr;
330         u64 tpt;
331         u64 ptc64;
332         u64 ptc127;
333         u64 ptc255;
334         u64 ptc511;
335         u64 ptc1023;
336         u64 ptc1522;
337         u64 mptc;
338         u64 bptc;
339         u64 tsctc;
340         u64 tsctfc;
341         u64 iac;
342         u64 icrxptc;
343         u64 icrxatc;
344         u64 ictxptc;
345         u64 ictxatc;
346         u64 ictxqec;
347         u64 ictxqmtc;
348         u64 icrxdmtc;
349         u64 icrxoc;
350         u64 cbtmpc;
351         u64 htdpmc;
352         u64 cbrdpc;
353         u64 cbrmpc;
354         u64 rpthc;
355         u64 hgptc;
356         u64 htcbdpc;
357         u64 hgorc;
358         u64 hgotc;
359         u64 lenerrs;
360         u64 scvpc;
361         u64 hrmpc;
362 };
363
364 struct e1000_phy_stats {
365         u32 idle_errors;
366         u32 receive_errors;
367 };
368
369 struct e1000_host_mng_dhcp_cookie {
370         u32 signature;
371         u8  status;
372         u8  reserved0;
373         u16 vlan_id;
374         u32 reserved1;
375         u16 reserved2;
376         u8  reserved3;
377         u8  checksum;
378 };
379
380 /* Host Interface "Rev 1" */
381 struct e1000_host_command_header {
382         u8 command_id;
383         u8 command_length;
384         u8 command_options;
385         u8 checksum;
386 };
387
388 #define E1000_HI_MAX_DATA_LENGTH     252
389 struct e1000_host_command_info {
390         struct e1000_host_command_header command_header;
391         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
392 };
393
394 /* Host Interface "Rev 2" */
395 struct e1000_host_mng_command_header {
396         u8  command_id;
397         u8  checksum;
398         u16 reserved1;
399         u16 reserved2;
400         u16 command_length;
401 };
402
403 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
404 struct e1000_host_mng_command_info {
405         struct e1000_host_mng_command_header command_header;
406         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
407 };
408
409 #include "e1000_mac.h"
410 #include "e1000_phy.h"
411 #include "e1000_nvm.h"
412
413 struct e1000_mac_operations {
414         s32  (*check_for_link)(struct e1000_hw *);
415         s32  (*reset_hw)(struct e1000_hw *);
416         s32  (*init_hw)(struct e1000_hw *);
417         bool (*check_mng_mode)(struct e1000_hw *);
418         s32  (*setup_physical_interface)(struct e1000_hw *);
419         void (*rar_set)(struct e1000_hw *, u8 *, u32);
420         s32  (*read_mac_addr)(struct e1000_hw *);
421         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
422 };
423
424 struct e1000_phy_operations {
425         s32  (*acquire_phy)(struct e1000_hw *);
426         s32  (*check_reset_block)(struct e1000_hw *);
427         s32  (*force_speed_duplex)(struct e1000_hw *);
428         s32  (*get_cfg_done)(struct e1000_hw *hw);
429         s32  (*get_cable_length)(struct e1000_hw *);
430         s32  (*get_phy_info)(struct e1000_hw *);
431         s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
432         void (*release_phy)(struct e1000_hw *);
433         s32  (*reset_phy)(struct e1000_hw *);
434         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
435         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
436         s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
437 };
438
439 struct e1000_nvm_operations {
440         s32  (*acquire_nvm)(struct e1000_hw *);
441         s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
442         void (*release_nvm)(struct e1000_hw *);
443         s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
444 };
445
446 struct e1000_info {
447         s32 (*get_invariants)(struct e1000_hw *);
448         struct e1000_mac_operations *mac_ops;
449         struct e1000_phy_operations *phy_ops;
450         struct e1000_nvm_operations *nvm_ops;
451 };
452
453 extern const struct e1000_info e1000_82575_info;
454
455 struct e1000_mac_info {
456         struct e1000_mac_operations ops;
457
458         u8 addr[6];
459         u8 perm_addr[6];
460
461         enum e1000_mac_type type;
462
463         u32 collision_delta;
464         u32 ledctl_default;
465         u32 ledctl_mode1;
466         u32 ledctl_mode2;
467         u32 mc_filter_type;
468         u32 tx_packet_delta;
469         u32 txcw;
470
471         u16 current_ifs_val;
472         u16 ifs_max_val;
473         u16 ifs_min_val;
474         u16 ifs_ratio;
475         u16 ifs_step_size;
476         u16 mta_reg_count;
477         u16 rar_entry_count;
478
479         u8  forced_speed_duplex;
480
481         bool adaptive_ifs;
482         bool arc_subsystem_valid;
483         bool asf_firmware_present;
484         bool autoneg;
485         bool autoneg_failed;
486         bool disable_av;
487         bool disable_hw_init_bits;
488         bool get_link_status;
489         bool ifs_params_forced;
490         bool in_ifs_mode;
491         bool report_tx_early;
492         bool serdes_has_link;
493         bool tx_pkt_filtering;
494 };
495
496 struct e1000_phy_info {
497         struct e1000_phy_operations ops;
498
499         enum e1000_phy_type type;
500
501         enum e1000_1000t_rx_status local_rx;
502         enum e1000_1000t_rx_status remote_rx;
503         enum e1000_ms_type ms_type;
504         enum e1000_ms_type original_ms_type;
505         enum e1000_rev_polarity cable_polarity;
506         enum e1000_smart_speed smart_speed;
507
508         u32 addr;
509         u32 id;
510         u32 reset_delay_us; /* in usec */
511         u32 revision;
512
513         enum e1000_media_type media_type;
514
515         u16 autoneg_advertised;
516         u16 autoneg_mask;
517         u16 cable_length;
518         u16 max_cable_length;
519         u16 min_cable_length;
520
521         u8 mdix;
522
523         bool disable_polarity_correction;
524         bool is_mdix;
525         bool polarity_correction;
526         bool reset_disable;
527         bool speed_downgraded;
528         bool autoneg_wait_to_complete;
529 };
530
531 struct e1000_nvm_info {
532         struct e1000_nvm_operations ops;
533
534         enum e1000_nvm_type type;
535         enum e1000_nvm_override override;
536
537         u32 flash_bank_size;
538         u32 flash_base_addr;
539
540         u16 word_size;
541         u16 delay_usec;
542         u16 address_bits;
543         u16 opcode_bits;
544         u16 page_size;
545 };
546
547 struct e1000_bus_info {
548         enum e1000_bus_type type;
549         enum e1000_bus_speed speed;
550         enum e1000_bus_width width;
551
552         u32 snoop;
553
554         u16 func;
555         u16 pci_cmd_word;
556 };
557
558 struct e1000_fc_info {
559         u32 high_water;     /* Flow control high-water mark */
560         u32 low_water;      /* Flow control low-water mark */
561         u16 pause_time;     /* Flow control pause timer */
562         bool send_xon;      /* Flow control send XON */
563         bool strict_ieee;   /* Strict IEEE mode */
564         enum e1000_fc_type type; /* Type of flow control */
565         enum e1000_fc_type original_type;
566 };
567
568 struct e1000_hw {
569         void *back;
570         void *dev_spec;
571
572         u8 __iomem *hw_addr;
573         u8 __iomem *flash_address;
574         unsigned long io_base;
575
576         struct e1000_mac_info  mac;
577         struct e1000_fc_info   fc;
578         struct e1000_phy_info  phy;
579         struct e1000_nvm_info  nvm;
580         struct e1000_bus_info  bus;
581         struct e1000_host_mng_dhcp_cookie mng_cookie;
582
583         u32 dev_spec_size;
584
585         u16 device_id;
586         u16 subsystem_vendor_id;
587         u16 subsystem_device_id;
588         u16 vendor_id;
589
590         u8  revision_id;
591 };
592
593 #ifdef DEBUG
594 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
595 #define hw_dbg(format, arg...) \
596         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
597 #else
598 #define hw_dbg(format, arg...)
599 #endif
600
601 #endif