Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...
[linux-2.6.git] / drivers / net / igb / e1000_hw.h
1 /*******************************************************************************
2
3   Intel(R) Gigabit Ethernet Linux driver
4   Copyright(c) 2007-2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _E1000_HW_H_
29 #define _E1000_HW_H_
30
31 #include <linux/types.h>
32 #include <linux/delay.h>
33 #include <linux/io.h>
34
35 #include "e1000_regs.h"
36 #include "e1000_defines.h"
37
38 struct e1000_hw;
39
40 #define E1000_DEV_ID_82576                    0x10C9
41 #define E1000_DEV_ID_82576_FIBER              0x10E6
42 #define E1000_DEV_ID_82576_SERDES             0x10E7
43 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
44 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
45 #define E1000_DEV_ID_82576_NS                 0x150A
46 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
47 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
48 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
49 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
50 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
51 #define E1000_DEV_ID_82580_COPPER             0x150E
52 #define E1000_DEV_ID_82580_FIBER              0x150F
53 #define E1000_DEV_ID_82580_SERDES             0x1510
54 #define E1000_DEV_ID_82580_SGMII              0x1511
55 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
56
57 #define E1000_REVISION_2 2
58 #define E1000_REVISION_4 4
59
60 #define E1000_FUNC_0     0
61 #define E1000_FUNC_1     1
62 #define E1000_FUNC_2     2
63 #define E1000_FUNC_3     3
64
65 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
66 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
67 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
68 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
69
70 enum e1000_mac_type {
71         e1000_undefined = 0,
72         e1000_82575,
73         e1000_82576,
74         e1000_82580,
75         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
76 };
77
78 enum e1000_media_type {
79         e1000_media_type_unknown = 0,
80         e1000_media_type_copper = 1,
81         e1000_media_type_internal_serdes = 2,
82         e1000_num_media_types
83 };
84
85 enum e1000_nvm_type {
86         e1000_nvm_unknown = 0,
87         e1000_nvm_none,
88         e1000_nvm_eeprom_spi,
89         e1000_nvm_flash_hw,
90         e1000_nvm_flash_sw
91 };
92
93 enum e1000_nvm_override {
94         e1000_nvm_override_none = 0,
95         e1000_nvm_override_spi_small,
96         e1000_nvm_override_spi_large,
97 };
98
99 enum e1000_phy_type {
100         e1000_phy_unknown = 0,
101         e1000_phy_none,
102         e1000_phy_m88,
103         e1000_phy_igp,
104         e1000_phy_igp_2,
105         e1000_phy_gg82563,
106         e1000_phy_igp_3,
107         e1000_phy_ife,
108         e1000_phy_82580,
109 };
110
111 enum e1000_bus_type {
112         e1000_bus_type_unknown = 0,
113         e1000_bus_type_pci,
114         e1000_bus_type_pcix,
115         e1000_bus_type_pci_express,
116         e1000_bus_type_reserved
117 };
118
119 enum e1000_bus_speed {
120         e1000_bus_speed_unknown = 0,
121         e1000_bus_speed_33,
122         e1000_bus_speed_66,
123         e1000_bus_speed_100,
124         e1000_bus_speed_120,
125         e1000_bus_speed_133,
126         e1000_bus_speed_2500,
127         e1000_bus_speed_5000,
128         e1000_bus_speed_reserved
129 };
130
131 enum e1000_bus_width {
132         e1000_bus_width_unknown = 0,
133         e1000_bus_width_pcie_x1,
134         e1000_bus_width_pcie_x2,
135         e1000_bus_width_pcie_x4 = 4,
136         e1000_bus_width_pcie_x8 = 8,
137         e1000_bus_width_32,
138         e1000_bus_width_64,
139         e1000_bus_width_reserved
140 };
141
142 enum e1000_1000t_rx_status {
143         e1000_1000t_rx_status_not_ok = 0,
144         e1000_1000t_rx_status_ok,
145         e1000_1000t_rx_status_undefined = 0xFF
146 };
147
148 enum e1000_rev_polarity {
149         e1000_rev_polarity_normal = 0,
150         e1000_rev_polarity_reversed,
151         e1000_rev_polarity_undefined = 0xFF
152 };
153
154 enum e1000_fc_mode {
155         e1000_fc_none = 0,
156         e1000_fc_rx_pause,
157         e1000_fc_tx_pause,
158         e1000_fc_full,
159         e1000_fc_default = 0xFF
160 };
161
162 /* Statistics counters collected by the MAC */
163 struct e1000_hw_stats {
164         u64 crcerrs;
165         u64 algnerrc;
166         u64 symerrs;
167         u64 rxerrc;
168         u64 mpc;
169         u64 scc;
170         u64 ecol;
171         u64 mcc;
172         u64 latecol;
173         u64 colc;
174         u64 dc;
175         u64 tncrs;
176         u64 sec;
177         u64 cexterr;
178         u64 rlec;
179         u64 xonrxc;
180         u64 xontxc;
181         u64 xoffrxc;
182         u64 xofftxc;
183         u64 fcruc;
184         u64 prc64;
185         u64 prc127;
186         u64 prc255;
187         u64 prc511;
188         u64 prc1023;
189         u64 prc1522;
190         u64 gprc;
191         u64 bprc;
192         u64 mprc;
193         u64 gptc;
194         u64 gorc;
195         u64 gotc;
196         u64 rnbc;
197         u64 ruc;
198         u64 rfc;
199         u64 roc;
200         u64 rjc;
201         u64 mgprc;
202         u64 mgpdc;
203         u64 mgptc;
204         u64 tor;
205         u64 tot;
206         u64 tpr;
207         u64 tpt;
208         u64 ptc64;
209         u64 ptc127;
210         u64 ptc255;
211         u64 ptc511;
212         u64 ptc1023;
213         u64 ptc1522;
214         u64 mptc;
215         u64 bptc;
216         u64 tsctc;
217         u64 tsctfc;
218         u64 iac;
219         u64 icrxptc;
220         u64 icrxatc;
221         u64 ictxptc;
222         u64 ictxatc;
223         u64 ictxqec;
224         u64 ictxqmtc;
225         u64 icrxdmtc;
226         u64 icrxoc;
227         u64 cbtmpc;
228         u64 htdpmc;
229         u64 cbrdpc;
230         u64 cbrmpc;
231         u64 rpthc;
232         u64 hgptc;
233         u64 htcbdpc;
234         u64 hgorc;
235         u64 hgotc;
236         u64 lenerrs;
237         u64 scvpc;
238         u64 hrmpc;
239         u64 doosync;
240 };
241
242 struct e1000_phy_stats {
243         u32 idle_errors;
244         u32 receive_errors;
245 };
246
247 struct e1000_host_mng_dhcp_cookie {
248         u32 signature;
249         u8  status;
250         u8  reserved0;
251         u16 vlan_id;
252         u32 reserved1;
253         u16 reserved2;
254         u8  reserved3;
255         u8  checksum;
256 };
257
258 /* Host Interface "Rev 1" */
259 struct e1000_host_command_header {
260         u8 command_id;
261         u8 command_length;
262         u8 command_options;
263         u8 checksum;
264 };
265
266 #define E1000_HI_MAX_DATA_LENGTH     252
267 struct e1000_host_command_info {
268         struct e1000_host_command_header command_header;
269         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
270 };
271
272 /* Host Interface "Rev 2" */
273 struct e1000_host_mng_command_header {
274         u8  command_id;
275         u8  checksum;
276         u16 reserved1;
277         u16 reserved2;
278         u16 command_length;
279 };
280
281 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
282 struct e1000_host_mng_command_info {
283         struct e1000_host_mng_command_header command_header;
284         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
285 };
286
287 #include "e1000_mac.h"
288 #include "e1000_phy.h"
289 #include "e1000_nvm.h"
290 #include "e1000_mbx.h"
291
292 struct e1000_mac_operations {
293         s32  (*check_for_link)(struct e1000_hw *);
294         s32  (*reset_hw)(struct e1000_hw *);
295         s32  (*init_hw)(struct e1000_hw *);
296         bool (*check_mng_mode)(struct e1000_hw *);
297         s32  (*setup_physical_interface)(struct e1000_hw *);
298         void (*rar_set)(struct e1000_hw *, u8 *, u32);
299         s32  (*read_mac_addr)(struct e1000_hw *);
300         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
301 };
302
303 struct e1000_phy_operations {
304         s32  (*acquire)(struct e1000_hw *);
305         s32  (*check_polarity)(struct e1000_hw *);
306         s32  (*check_reset_block)(struct e1000_hw *);
307         s32  (*force_speed_duplex)(struct e1000_hw *);
308         s32  (*get_cfg_done)(struct e1000_hw *hw);
309         s32  (*get_cable_length)(struct e1000_hw *);
310         s32  (*get_phy_info)(struct e1000_hw *);
311         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
312         void (*release)(struct e1000_hw *);
313         s32  (*reset)(struct e1000_hw *);
314         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
315         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
316         s32  (*write_reg)(struct e1000_hw *, u32, u16);
317 };
318
319 struct e1000_nvm_operations {
320         s32  (*acquire)(struct e1000_hw *);
321         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
322         void (*release)(struct e1000_hw *);
323         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
324 };
325
326 struct e1000_info {
327         s32 (*get_invariants)(struct e1000_hw *);
328         struct e1000_mac_operations *mac_ops;
329         struct e1000_phy_operations *phy_ops;
330         struct e1000_nvm_operations *nvm_ops;
331 };
332
333 extern const struct e1000_info e1000_82575_info;
334
335 struct e1000_mac_info {
336         struct e1000_mac_operations ops;
337
338         u8 addr[6];
339         u8 perm_addr[6];
340
341         enum e1000_mac_type type;
342
343         u32 ledctl_default;
344         u32 ledctl_mode1;
345         u32 ledctl_mode2;
346         u32 mc_filter_type;
347         u32 txcw;
348
349         u16 mta_reg_count;
350         u16 uta_reg_count;
351
352         /* Maximum size of the MTA register table in all supported adapters */
353         #define MAX_MTA_REG 128
354         u32 mta_shadow[MAX_MTA_REG];
355         u16 rar_entry_count;
356
357         u8  forced_speed_duplex;
358
359         bool adaptive_ifs;
360         bool arc_subsystem_valid;
361         bool asf_firmware_present;
362         bool autoneg;
363         bool autoneg_failed;
364         bool disable_hw_init_bits;
365         bool get_link_status;
366         bool ifs_params_forced;
367         bool in_ifs_mode;
368         bool report_tx_early;
369         bool serdes_has_link;
370         bool tx_pkt_filtering;
371 };
372
373 struct e1000_phy_info {
374         struct e1000_phy_operations ops;
375
376         enum e1000_phy_type type;
377
378         enum e1000_1000t_rx_status local_rx;
379         enum e1000_1000t_rx_status remote_rx;
380         enum e1000_ms_type ms_type;
381         enum e1000_ms_type original_ms_type;
382         enum e1000_rev_polarity cable_polarity;
383         enum e1000_smart_speed smart_speed;
384
385         u32 addr;
386         u32 id;
387         u32 reset_delay_us; /* in usec */
388         u32 revision;
389
390         enum e1000_media_type media_type;
391
392         u16 autoneg_advertised;
393         u16 autoneg_mask;
394         u16 cable_length;
395         u16 max_cable_length;
396         u16 min_cable_length;
397
398         u8 mdix;
399
400         bool disable_polarity_correction;
401         bool is_mdix;
402         bool polarity_correction;
403         bool reset_disable;
404         bool speed_downgraded;
405         bool autoneg_wait_to_complete;
406 };
407
408 struct e1000_nvm_info {
409         struct e1000_nvm_operations ops;
410
411         enum e1000_nvm_type type;
412         enum e1000_nvm_override override;
413
414         u32 flash_bank_size;
415         u32 flash_base_addr;
416
417         u16 word_size;
418         u16 delay_usec;
419         u16 address_bits;
420         u16 opcode_bits;
421         u16 page_size;
422 };
423
424 struct e1000_bus_info {
425         enum e1000_bus_type type;
426         enum e1000_bus_speed speed;
427         enum e1000_bus_width width;
428
429         u32 snoop;
430
431         u16 func;
432         u16 pci_cmd_word;
433 };
434
435 struct e1000_fc_info {
436         u32 high_water;     /* Flow control high-water mark */
437         u32 low_water;      /* Flow control low-water mark */
438         u16 pause_time;     /* Flow control pause timer */
439         bool send_xon;      /* Flow control send XON */
440         bool strict_ieee;   /* Strict IEEE mode */
441         enum e1000_fc_mode current_mode; /* Type of flow control */
442         enum e1000_fc_mode requested_mode;
443 };
444
445 struct e1000_mbx_operations {
446         s32 (*init_params)(struct e1000_hw *hw);
447         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
448         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
449         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
450         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
451         s32 (*check_for_msg)(struct e1000_hw *, u16);
452         s32 (*check_for_ack)(struct e1000_hw *, u16);
453         s32 (*check_for_rst)(struct e1000_hw *, u16);
454 };
455
456 struct e1000_mbx_stats {
457         u32 msgs_tx;
458         u32 msgs_rx;
459
460         u32 acks;
461         u32 reqs;
462         u32 rsts;
463 };
464
465 struct e1000_mbx_info {
466         struct e1000_mbx_operations ops;
467         struct e1000_mbx_stats stats;
468         u32 timeout;
469         u32 usec_delay;
470         u16 size;
471 };
472
473 struct e1000_dev_spec_82575 {
474         bool sgmii_active;
475         bool global_device_reset;
476 };
477
478 struct e1000_hw {
479         void *back;
480
481         u8 __iomem *hw_addr;
482         u8 __iomem *flash_address;
483         unsigned long io_base;
484
485         struct e1000_mac_info  mac;
486         struct e1000_fc_info   fc;
487         struct e1000_phy_info  phy;
488         struct e1000_nvm_info  nvm;
489         struct e1000_bus_info  bus;
490         struct e1000_mbx_info mbx;
491         struct e1000_host_mng_dhcp_cookie mng_cookie;
492
493         union {
494                 struct e1000_dev_spec_82575     _82575;
495         } dev_spec;
496
497         u16 device_id;
498         u16 subsystem_vendor_id;
499         u16 subsystem_device_id;
500         u16 vendor_id;
501
502         u8  revision_id;
503 };
504
505 #ifdef DEBUG
506 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
507 #define hw_dbg(format, arg...) \
508         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
509 #else
510 #define hw_dbg(format, arg...)
511 #endif
512 #endif
513 /* These functions must be implemented by drivers */
514 s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
515 s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);