trivial: remove unnecessary semicolons
[linux-2.6.git] / drivers / net / ibm_newemac / core.c
1 /*
2  * drivers/net/ibm_newemac/core.c
3  *
4  * Driver for PowerPC 4xx on-chip ethernet controller.
5  *
6  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7  *                <benh@kernel.crashing.org>
8  *
9  * Based on the arch/ppc version of the driver:
10  *
11  * Copyright (c) 2004, 2005 Zultys Technologies.
12  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13  *
14  * Based on original work by
15  *      Matt Porter <mporter@kernel.crashing.org>
16  *      (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
17  *      Armin Kuster <akuster@mvista.com>
18  *      Johnnie Peters <jpeters@mvista.com>
19  *
20  * This program is free software; you can redistribute  it and/or modify it
21  * under  the terms of  the GNU General  Public License as published by the
22  * Free Software Foundation;  either version 2 of the  License, or (at your
23  * option) any later version.
24  *
25  */
26
27 #include <linux/sched.h>
28 #include <linux/string.h>
29 #include <linux/errno.h>
30 #include <linux/delay.h>
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/crc32.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/bitops.h>
39 #include <linux/workqueue.h>
40 #include <linux/of.h>
41
42 #include <asm/processor.h>
43 #include <asm/io.h>
44 #include <asm/dma.h>
45 #include <asm/uaccess.h>
46 #include <asm/dcr.h>
47 #include <asm/dcr-regs.h>
48
49 #include "core.h"
50
51 /*
52  * Lack of dma_unmap_???? calls is intentional.
53  *
54  * API-correct usage requires additional support state information to be
55  * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
56  * EMAC design (e.g. TX buffer passed from network stack can be split into
57  * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
58  * maintaining such information will add additional overhead.
59  * Current DMA API implementation for 4xx processors only ensures cache coherency
60  * and dma_unmap_???? routines are empty and are likely to stay this way.
61  * I decided to omit dma_unmap_??? calls because I don't want to add additional
62  * complexity just for the sake of following some abstract API, when it doesn't
63  * add any real benefit to the driver. I understand that this decision maybe
64  * controversial, but I really tried to make code API-correct and efficient
65  * at the same time and didn't come up with code I liked :(.                --ebs
66  */
67
68 #define DRV_NAME        "emac"
69 #define DRV_VERSION     "3.54"
70 #define DRV_DESC        "PPC 4xx OCP EMAC driver"
71
72 MODULE_DESCRIPTION(DRV_DESC);
73 MODULE_AUTHOR
74     ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
75 MODULE_LICENSE("GPL");
76
77 /*
78  * PPC64 doesn't (yet) have a cacheable_memcpy
79  */
80 #ifdef CONFIG_PPC64
81 #define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
82 #endif
83
84 /* minimum number of free TX descriptors required to wake up TX process */
85 #define EMAC_TX_WAKEUP_THRESH           (NUM_TX_BUFF / 4)
86
87 /* If packet size is less than this number, we allocate small skb and copy packet
88  * contents into it instead of just sending original big skb up
89  */
90 #define EMAC_RX_COPY_THRESH             CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD
91
92 /* Since multiple EMACs share MDIO lines in various ways, we need
93  * to avoid re-using the same PHY ID in cases where the arch didn't
94  * setup precise phy_map entries
95  *
96  * XXX This is something that needs to be reworked as we can have multiple
97  * EMAC "sets" (multiple ASICs containing several EMACs) though we can
98  * probably require in that case to have explicit PHY IDs in the device-tree
99  */
100 static u32 busy_phy_map;
101 static DEFINE_MUTEX(emac_phy_map_lock);
102
103 /* This is the wait queue used to wait on any event related to probe, that
104  * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
105  */
106 static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
107
108 /* Having stable interface names is a doomed idea. However, it would be nice
109  * if we didn't have completely random interface names at boot too :-) It's
110  * just a matter of making everybody's life easier. Since we are doing
111  * threaded probing, it's a bit harder though. The base idea here is that
112  * we make up a list of all emacs in the device-tree before we register the
113  * driver. Every emac will then wait for the previous one in the list to
114  * initialize before itself. We should also keep that list ordered by
115  * cell_index.
116  * That list is only 4 entries long, meaning that additional EMACs don't
117  * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
118  */
119
120 #define EMAC_BOOT_LIST_SIZE     4
121 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
122
123 /* How long should I wait for dependent devices ? */
124 #define EMAC_PROBE_DEP_TIMEOUT  (HZ * 5)
125
126 /* I don't want to litter system log with timeout errors
127  * when we have brain-damaged PHY.
128  */
129 static inline void emac_report_timeout_error(struct emac_instance *dev,
130                                              const char *error)
131 {
132         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
133                                   EMAC_FTR_460EX_PHY_CLK_FIX |
134                                   EMAC_FTR_440EP_PHY_CLK_FIX))
135                 DBG(dev, "%s" NL, error);
136         else if (net_ratelimit())
137                 printk(KERN_ERR "%s: %s\n", dev->ofdev->node->full_name, error);
138 }
139
140 /* EMAC PHY clock workaround:
141  * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
142  * which allows controlling each EMAC clock
143  */
144 static inline void emac_rx_clk_tx(struct emac_instance *dev)
145 {
146 #ifdef CONFIG_PPC_DCR_NATIVE
147         if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
148                 dcri_clrset(SDR0, SDR0_MFR,
149                             0, SDR0_MFR_ECS >> dev->cell_index);
150 #endif
151 }
152
153 static inline void emac_rx_clk_default(struct emac_instance *dev)
154 {
155 #ifdef CONFIG_PPC_DCR_NATIVE
156         if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
157                 dcri_clrset(SDR0, SDR0_MFR,
158                             SDR0_MFR_ECS >> dev->cell_index, 0);
159 #endif
160 }
161
162 /* PHY polling intervals */
163 #define PHY_POLL_LINK_ON        HZ
164 #define PHY_POLL_LINK_OFF       (HZ / 5)
165
166 /* Graceful stop timeouts in us.
167  * We should allow up to 1 frame time (full-duplex, ignoring collisions)
168  */
169 #define STOP_TIMEOUT_10         1230
170 #define STOP_TIMEOUT_100        124
171 #define STOP_TIMEOUT_1000       13
172 #define STOP_TIMEOUT_1000_JUMBO 73
173
174 static unsigned char default_mcast_addr[] = {
175         0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
176 };
177
178 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
179 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
180         "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
181         "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
182         "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
183         "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
184         "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
185         "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
186         "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
187         "rx_bad_packet", "rx_runt_packet", "rx_short_event",
188         "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
189         "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
190         "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
191         "tx_bd_excessive_collisions", "tx_bd_late_collision",
192         "tx_bd_multple_collisions", "tx_bd_single_collision",
193         "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
194         "tx_errors"
195 };
196
197 static irqreturn_t emac_irq(int irq, void *dev_instance);
198 static void emac_clean_tx_ring(struct emac_instance *dev);
199 static void __emac_set_multicast_list(struct emac_instance *dev);
200
201 static inline int emac_phy_supports_gige(int phy_mode)
202 {
203         return  phy_mode == PHY_MODE_GMII ||
204                 phy_mode == PHY_MODE_RGMII ||
205                 phy_mode == PHY_MODE_SGMII ||
206                 phy_mode == PHY_MODE_TBI ||
207                 phy_mode == PHY_MODE_RTBI;
208 }
209
210 static inline int emac_phy_gpcs(int phy_mode)
211 {
212         return  phy_mode == PHY_MODE_SGMII ||
213                 phy_mode == PHY_MODE_TBI ||
214                 phy_mode == PHY_MODE_RTBI;
215 }
216
217 static inline void emac_tx_enable(struct emac_instance *dev)
218 {
219         struct emac_regs __iomem *p = dev->emacp;
220         u32 r;
221
222         DBG(dev, "tx_enable" NL);
223
224         r = in_be32(&p->mr0);
225         if (!(r & EMAC_MR0_TXE))
226                 out_be32(&p->mr0, r | EMAC_MR0_TXE);
227 }
228
229 static void emac_tx_disable(struct emac_instance *dev)
230 {
231         struct emac_regs __iomem *p = dev->emacp;
232         u32 r;
233
234         DBG(dev, "tx_disable" NL);
235
236         r = in_be32(&p->mr0);
237         if (r & EMAC_MR0_TXE) {
238                 int n = dev->stop_timeout;
239                 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
240                 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
241                         udelay(1);
242                         --n;
243                 }
244                 if (unlikely(!n))
245                         emac_report_timeout_error(dev, "TX disable timeout");
246         }
247 }
248
249 static void emac_rx_enable(struct emac_instance *dev)
250 {
251         struct emac_regs __iomem *p = dev->emacp;
252         u32 r;
253
254         if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
255                 goto out;
256
257         DBG(dev, "rx_enable" NL);
258
259         r = in_be32(&p->mr0);
260         if (!(r & EMAC_MR0_RXE)) {
261                 if (unlikely(!(r & EMAC_MR0_RXI))) {
262                         /* Wait if previous async disable is still in progress */
263                         int n = dev->stop_timeout;
264                         while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
265                                 udelay(1);
266                                 --n;
267                         }
268                         if (unlikely(!n))
269                                 emac_report_timeout_error(dev,
270                                                           "RX disable timeout");
271                 }
272                 out_be32(&p->mr0, r | EMAC_MR0_RXE);
273         }
274  out:
275         ;
276 }
277
278 static void emac_rx_disable(struct emac_instance *dev)
279 {
280         struct emac_regs __iomem *p = dev->emacp;
281         u32 r;
282
283         DBG(dev, "rx_disable" NL);
284
285         r = in_be32(&p->mr0);
286         if (r & EMAC_MR0_RXE) {
287                 int n = dev->stop_timeout;
288                 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
289                 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
290                         udelay(1);
291                         --n;
292                 }
293                 if (unlikely(!n))
294                         emac_report_timeout_error(dev, "RX disable timeout");
295         }
296 }
297
298 static inline void emac_netif_stop(struct emac_instance *dev)
299 {
300         netif_tx_lock_bh(dev->ndev);
301         netif_addr_lock(dev->ndev);
302         dev->no_mcast = 1;
303         netif_addr_unlock(dev->ndev);
304         netif_tx_unlock_bh(dev->ndev);
305         dev->ndev->trans_start = jiffies;       /* prevent tx timeout */
306         mal_poll_disable(dev->mal, &dev->commac);
307         netif_tx_disable(dev->ndev);
308 }
309
310 static inline void emac_netif_start(struct emac_instance *dev)
311 {
312         netif_tx_lock_bh(dev->ndev);
313         netif_addr_lock(dev->ndev);
314         dev->no_mcast = 0;
315         if (dev->mcast_pending && netif_running(dev->ndev))
316                 __emac_set_multicast_list(dev);
317         netif_addr_unlock(dev->ndev);
318         netif_tx_unlock_bh(dev->ndev);
319
320         netif_wake_queue(dev->ndev);
321
322         /* NOTE: unconditional netif_wake_queue is only appropriate
323          * so long as all callers are assured to have free tx slots
324          * (taken from tg3... though the case where that is wrong is
325          *  not terribly harmful)
326          */
327         mal_poll_enable(dev->mal, &dev->commac);
328 }
329
330 static inline void emac_rx_disable_async(struct emac_instance *dev)
331 {
332         struct emac_regs __iomem *p = dev->emacp;
333         u32 r;
334
335         DBG(dev, "rx_disable_async" NL);
336
337         r = in_be32(&p->mr0);
338         if (r & EMAC_MR0_RXE)
339                 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
340 }
341
342 static int emac_reset(struct emac_instance *dev)
343 {
344         struct emac_regs __iomem *p = dev->emacp;
345         int n = 20;
346
347         DBG(dev, "reset" NL);
348
349         if (!dev->reset_failed) {
350                 /* 40x erratum suggests stopping RX channel before reset,
351                  * we stop TX as well
352                  */
353                 emac_rx_disable(dev);
354                 emac_tx_disable(dev);
355         }
356
357 #ifdef CONFIG_PPC_DCR_NATIVE
358         /* Enable internal clock source */
359         if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
360                 dcri_clrset(SDR0, SDR0_ETH_CFG,
361                             0, SDR0_ETH_CFG_ECS << dev->cell_index);
362 #endif
363
364         out_be32(&p->mr0, EMAC_MR0_SRST);
365         while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
366                 --n;
367
368 #ifdef CONFIG_PPC_DCR_NATIVE
369          /* Enable external clock source */
370         if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
371                 dcri_clrset(SDR0, SDR0_ETH_CFG,
372                             SDR0_ETH_CFG_ECS << dev->cell_index, 0);
373 #endif
374
375         if (n) {
376                 dev->reset_failed = 0;
377                 return 0;
378         } else {
379                 emac_report_timeout_error(dev, "reset timeout");
380                 dev->reset_failed = 1;
381                 return -ETIMEDOUT;
382         }
383 }
384
385 static void emac_hash_mc(struct emac_instance *dev)
386 {
387         const int regs = EMAC_XAHT_REGS(dev);
388         u32 *gaht_base = emac_gaht_base(dev);
389         u32 gaht_temp[regs];
390         struct dev_mc_list *dmi;
391         int i;
392
393         DBG(dev, "hash_mc %d" NL, dev->ndev->mc_count);
394
395         memset(gaht_temp, 0, sizeof (gaht_temp));
396
397         for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
398                 int slot, reg, mask;
399                 DBG2(dev, "mc %pM" NL, dmi->dmi_addr);
400
401                 slot = EMAC_XAHT_CRC_TO_SLOT(dev, ether_crc(ETH_ALEN, dmi->dmi_addr));
402                 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
403                 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
404
405                 gaht_temp[reg] |= mask;
406         }
407
408         for (i = 0; i < regs; i++)
409                 out_be32(gaht_base + i, gaht_temp[i]);
410 }
411
412 static inline u32 emac_iff2rmr(struct net_device *ndev)
413 {
414         struct emac_instance *dev = netdev_priv(ndev);
415         u32 r;
416
417         r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
418
419         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
420             r |= EMAC4_RMR_BASE;
421         else
422             r |= EMAC_RMR_BASE;
423
424         if (ndev->flags & IFF_PROMISC)
425                 r |= EMAC_RMR_PME;
426         else if (ndev->flags & IFF_ALLMULTI ||
427                          (ndev->mc_count > EMAC_XAHT_SLOTS(dev)))
428                 r |= EMAC_RMR_PMME;
429         else if (ndev->mc_count > 0)
430                 r |= EMAC_RMR_MAE;
431
432         return r;
433 }
434
435 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
436 {
437         u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
438
439         DBG2(dev, "__emac_calc_base_mr1" NL);
440
441         switch(tx_size) {
442         case 2048:
443                 ret |= EMAC_MR1_TFS_2K;
444                 break;
445         default:
446                 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
447                        dev->ndev->name, tx_size);
448         }
449
450         switch(rx_size) {
451         case 16384:
452                 ret |= EMAC_MR1_RFS_16K;
453                 break;
454         case 4096:
455                 ret |= EMAC_MR1_RFS_4K;
456                 break;
457         default:
458                 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
459                        dev->ndev->name, rx_size);
460         }
461
462         return ret;
463 }
464
465 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
466 {
467         u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
468                 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
469
470         DBG2(dev, "__emac4_calc_base_mr1" NL);
471
472         switch(tx_size) {
473         case 4096:
474                 ret |= EMAC4_MR1_TFS_4K;
475                 break;
476         case 2048:
477                 ret |= EMAC4_MR1_TFS_2K;
478                 break;
479         default:
480                 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
481                        dev->ndev->name, tx_size);
482         }
483
484         switch(rx_size) {
485         case 16384:
486                 ret |= EMAC4_MR1_RFS_16K;
487                 break;
488         case 4096:
489                 ret |= EMAC4_MR1_RFS_4K;
490                 break;
491         case 2048:
492                 ret |= EMAC4_MR1_RFS_2K;
493                 break;
494         default:
495                 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
496                        dev->ndev->name, rx_size);
497         }
498
499         return ret;
500 }
501
502 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
503 {
504         return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
505                 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
506                 __emac_calc_base_mr1(dev, tx_size, rx_size);
507 }
508
509 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
510 {
511         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
512                 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
513         else
514                 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
515 }
516
517 static inline u32 emac_calc_rwmr(struct emac_instance *dev,
518                                  unsigned int low, unsigned int high)
519 {
520         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
521                 return (low << 22) | ( (high & 0x3ff) << 6);
522         else
523                 return (low << 23) | ( (high & 0x1ff) << 7);
524 }
525
526 static int emac_configure(struct emac_instance *dev)
527 {
528         struct emac_regs __iomem *p = dev->emacp;
529         struct net_device *ndev = dev->ndev;
530         int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
531         u32 r, mr1 = 0;
532
533         DBG(dev, "configure" NL);
534
535         if (!link) {
536                 out_be32(&p->mr1, in_be32(&p->mr1)
537                          | EMAC_MR1_FDE | EMAC_MR1_ILE);
538                 udelay(100);
539         } else if (emac_reset(dev) < 0)
540                 return -ETIMEDOUT;
541
542         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
543                 tah_reset(dev->tah_dev);
544
545         DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
546             link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
547
548         /* Default fifo sizes */
549         tx_size = dev->tx_fifo_size;
550         rx_size = dev->rx_fifo_size;
551
552         /* No link, force loopback */
553         if (!link)
554                 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
555
556         /* Check for full duplex */
557         else if (dev->phy.duplex == DUPLEX_FULL)
558                 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
559
560         /* Adjust fifo sizes, mr1 and timeouts based on link speed */
561         dev->stop_timeout = STOP_TIMEOUT_10;
562         switch (dev->phy.speed) {
563         case SPEED_1000:
564                 if (emac_phy_gpcs(dev->phy.mode)) {
565                         mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
566                                 (dev->phy.gpcs_address != 0xffffffff) ?
567                                  dev->phy.gpcs_address : dev->phy.address);
568
569                         /* Put some arbitrary OUI, Manuf & Rev IDs so we can
570                          * identify this GPCS PHY later.
571                          */
572                         out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
573                 } else
574                         mr1 |= EMAC_MR1_MF_1000;
575
576                 /* Extended fifo sizes */
577                 tx_size = dev->tx_fifo_size_gige;
578                 rx_size = dev->rx_fifo_size_gige;
579
580                 if (dev->ndev->mtu > ETH_DATA_LEN) {
581                         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
582                                 mr1 |= EMAC4_MR1_JPSM;
583                         else
584                                 mr1 |= EMAC_MR1_JPSM;
585                         dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
586                 } else
587                         dev->stop_timeout = STOP_TIMEOUT_1000;
588                 break;
589         case SPEED_100:
590                 mr1 |= EMAC_MR1_MF_100;
591                 dev->stop_timeout = STOP_TIMEOUT_100;
592                 break;
593         default: /* make gcc happy */
594                 break;
595         }
596
597         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
598                 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
599                                 dev->phy.speed);
600         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
601                 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
602
603         /* on 40x erratum forces us to NOT use integrated flow control,
604          * let's hope it works on 44x ;)
605          */
606         if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
607             dev->phy.duplex == DUPLEX_FULL) {
608                 if (dev->phy.pause)
609                         mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
610                 else if (dev->phy.asym_pause)
611                         mr1 |= EMAC_MR1_APP;
612         }
613
614         /* Add base settings & fifo sizes & program MR1 */
615         mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
616         out_be32(&p->mr1, mr1);
617
618         /* Set individual MAC address */
619         out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
620         out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
621                  (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
622                  ndev->dev_addr[5]);
623
624         /* VLAN Tag Protocol ID */
625         out_be32(&p->vtpid, 0x8100);
626
627         /* Receive mode register */
628         r = emac_iff2rmr(ndev);
629         if (r & EMAC_RMR_MAE)
630                 emac_hash_mc(dev);
631         out_be32(&p->rmr, r);
632
633         /* FIFOs thresholds */
634         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
635                 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
636                                tx_size / 2 / dev->fifo_entry_size);
637         else
638                 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
639                               tx_size / 2 / dev->fifo_entry_size);
640         out_be32(&p->tmr1, r);
641         out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
642
643         /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
644            there should be still enough space in FIFO to allow the our link
645            partner time to process this frame and also time to send PAUSE
646            frame itself.
647
648            Here is the worst case scenario for the RX FIFO "headroom"
649            (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
650
651            1) One maximum-length frame on TX                    1522 bytes
652            2) One PAUSE frame time                                64 bytes
653            3) PAUSE frame decode time allowance                   64 bytes
654            4) One maximum-length frame on RX                    1522 bytes
655            5) Round-trip propagation delay of the link (100Mb)    15 bytes
656            ----------
657            3187 bytes
658
659            I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
660            low-water mark  to RX_FIFO_SIZE / 8 (512 bytes)
661          */
662         r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
663                            rx_size / 4 / dev->fifo_entry_size);
664         out_be32(&p->rwmr, r);
665
666         /* Set PAUSE timer to the maximum */
667         out_be32(&p->ptr, 0xffff);
668
669         /* IRQ sources */
670         r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
671                 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
672                 EMAC_ISR_IRE | EMAC_ISR_TE;
673         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
674             r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
675                                                   EMAC4_ISR_RXOE | */;
676         out_be32(&p->iser,  r);
677
678         /* We need to take GPCS PHY out of isolate mode after EMAC reset */
679         if (emac_phy_gpcs(dev->phy.mode)) {
680                 if (dev->phy.gpcs_address != 0xffffffff)
681                         emac_mii_reset_gpcs(&dev->phy);
682                 else
683                         emac_mii_reset_phy(&dev->phy);
684         }
685
686         return 0;
687 }
688
689 static void emac_reinitialize(struct emac_instance *dev)
690 {
691         DBG(dev, "reinitialize" NL);
692
693         emac_netif_stop(dev);
694         if (!emac_configure(dev)) {
695                 emac_tx_enable(dev);
696                 emac_rx_enable(dev);
697         }
698         emac_netif_start(dev);
699 }
700
701 static void emac_full_tx_reset(struct emac_instance *dev)
702 {
703         DBG(dev, "full_tx_reset" NL);
704
705         emac_tx_disable(dev);
706         mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
707         emac_clean_tx_ring(dev);
708         dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
709
710         emac_configure(dev);
711
712         mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
713         emac_tx_enable(dev);
714         emac_rx_enable(dev);
715 }
716
717 static void emac_reset_work(struct work_struct *work)
718 {
719         struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
720
721         DBG(dev, "reset_work" NL);
722
723         mutex_lock(&dev->link_lock);
724         if (dev->opened) {
725                 emac_netif_stop(dev);
726                 emac_full_tx_reset(dev);
727                 emac_netif_start(dev);
728         }
729         mutex_unlock(&dev->link_lock);
730 }
731
732 static void emac_tx_timeout(struct net_device *ndev)
733 {
734         struct emac_instance *dev = netdev_priv(ndev);
735
736         DBG(dev, "tx_timeout" NL);
737
738         schedule_work(&dev->reset_work);
739 }
740
741
742 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
743 {
744         int done = !!(stacr & EMAC_STACR_OC);
745
746         if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
747                 done = !done;
748
749         return done;
750 };
751
752 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
753 {
754         struct emac_regs __iomem *p = dev->emacp;
755         u32 r = 0;
756         int n, err = -ETIMEDOUT;
757
758         mutex_lock(&dev->mdio_lock);
759
760         DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
761
762         /* Enable proper MDIO port */
763         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
764                 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
765         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
766                 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
767
768         /* Wait for management interface to become idle */
769         n = 20;
770         while (!emac_phy_done(dev, in_be32(&p->stacr))) {
771                 udelay(1);
772                 if (!--n) {
773                         DBG2(dev, " -> timeout wait idle\n");
774                         goto bail;
775                 }
776         }
777
778         /* Issue read command */
779         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
780                 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
781         else
782                 r = EMAC_STACR_BASE(dev->opb_bus_freq);
783         if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
784                 r |= EMAC_STACR_OC;
785         if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
786                 r |= EMACX_STACR_STAC_READ;
787         else
788                 r |= EMAC_STACR_STAC_READ;
789         r |= (reg & EMAC_STACR_PRA_MASK)
790                 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
791         out_be32(&p->stacr, r);
792
793         /* Wait for read to complete */
794         n = 200;
795         while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
796                 udelay(1);
797                 if (!--n) {
798                         DBG2(dev, " -> timeout wait complete\n");
799                         goto bail;
800                 }
801         }
802
803         if (unlikely(r & EMAC_STACR_PHYE)) {
804                 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
805                 err = -EREMOTEIO;
806                 goto bail;
807         }
808
809         r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
810
811         DBG2(dev, "mdio_read -> %04x" NL, r);
812         err = 0;
813  bail:
814         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
815                 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
816         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
817                 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
818         mutex_unlock(&dev->mdio_lock);
819
820         return err == 0 ? r : err;
821 }
822
823 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
824                               u16 val)
825 {
826         struct emac_regs __iomem *p = dev->emacp;
827         u32 r = 0;
828         int n, err = -ETIMEDOUT;
829
830         mutex_lock(&dev->mdio_lock);
831
832         DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
833
834         /* Enable proper MDIO port */
835         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
836                 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
837         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
838                 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
839
840         /* Wait for management interface to be idle */
841         n = 20;
842         while (!emac_phy_done(dev, in_be32(&p->stacr))) {
843                 udelay(1);
844                 if (!--n) {
845                         DBG2(dev, " -> timeout wait idle\n");
846                         goto bail;
847                 }
848         }
849
850         /* Issue write command */
851         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
852                 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
853         else
854                 r = EMAC_STACR_BASE(dev->opb_bus_freq);
855         if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
856                 r |= EMAC_STACR_OC;
857         if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
858                 r |= EMACX_STACR_STAC_WRITE;
859         else
860                 r |= EMAC_STACR_STAC_WRITE;
861         r |= (reg & EMAC_STACR_PRA_MASK) |
862                 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
863                 (val << EMAC_STACR_PHYD_SHIFT);
864         out_be32(&p->stacr, r);
865
866         /* Wait for write to complete */
867         n = 200;
868         while (!emac_phy_done(dev, in_be32(&p->stacr))) {
869                 udelay(1);
870                 if (!--n) {
871                         DBG2(dev, " -> timeout wait complete\n");
872                         goto bail;
873                 }
874         }
875         err = 0;
876  bail:
877         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
878                 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
879         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
880                 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
881         mutex_unlock(&dev->mdio_lock);
882 }
883
884 static int emac_mdio_read(struct net_device *ndev, int id, int reg)
885 {
886         struct emac_instance *dev = netdev_priv(ndev);
887         int res;
888
889         res = __emac_mdio_read((dev->mdio_instance &&
890                                 dev->phy.gpcs_address != id) ?
891                                 dev->mdio_instance : dev,
892                                (u8) id, (u8) reg);
893         return res;
894 }
895
896 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
897 {
898         struct emac_instance *dev = netdev_priv(ndev);
899
900         __emac_mdio_write((dev->mdio_instance &&
901                            dev->phy.gpcs_address != id) ?
902                            dev->mdio_instance : dev,
903                           (u8) id, (u8) reg, (u16) val);
904 }
905
906 /* Tx lock BH */
907 static void __emac_set_multicast_list(struct emac_instance *dev)
908 {
909         struct emac_regs __iomem *p = dev->emacp;
910         u32 rmr = emac_iff2rmr(dev->ndev);
911
912         DBG(dev, "__multicast %08x" NL, rmr);
913
914         /* I decided to relax register access rules here to avoid
915          * full EMAC reset.
916          *
917          * There is a real problem with EMAC4 core if we use MWSW_001 bit
918          * in MR1 register and do a full EMAC reset.
919          * One TX BD status update is delayed and, after EMAC reset, it
920          * never happens, resulting in TX hung (it'll be recovered by TX
921          * timeout handler eventually, but this is just gross).
922          * So we either have to do full TX reset or try to cheat here :)
923          *
924          * The only required change is to RX mode register, so I *think* all
925          * we need is just to stop RX channel. This seems to work on all
926          * tested SoCs.                                                --ebs
927          *
928          * If we need the full reset, we might just trigger the workqueue
929          * and do it async... a bit nasty but should work --BenH
930          */
931         dev->mcast_pending = 0;
932         emac_rx_disable(dev);
933         if (rmr & EMAC_RMR_MAE)
934                 emac_hash_mc(dev);
935         out_be32(&p->rmr, rmr);
936         emac_rx_enable(dev);
937 }
938
939 /* Tx lock BH */
940 static void emac_set_multicast_list(struct net_device *ndev)
941 {
942         struct emac_instance *dev = netdev_priv(ndev);
943
944         DBG(dev, "multicast" NL);
945
946         BUG_ON(!netif_running(dev->ndev));
947
948         if (dev->no_mcast) {
949                 dev->mcast_pending = 1;
950                 return;
951         }
952         __emac_set_multicast_list(dev);
953 }
954
955 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
956 {
957         int rx_sync_size = emac_rx_sync_size(new_mtu);
958         int rx_skb_size = emac_rx_skb_size(new_mtu);
959         int i, ret = 0;
960
961         mutex_lock(&dev->link_lock);
962         emac_netif_stop(dev);
963         emac_rx_disable(dev);
964         mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
965
966         if (dev->rx_sg_skb) {
967                 ++dev->estats.rx_dropped_resize;
968                 dev_kfree_skb(dev->rx_sg_skb);
969                 dev->rx_sg_skb = NULL;
970         }
971
972         /* Make a first pass over RX ring and mark BDs ready, dropping
973          * non-processed packets on the way. We need this as a separate pass
974          * to simplify error recovery in the case of allocation failure later.
975          */
976         for (i = 0; i < NUM_RX_BUFF; ++i) {
977                 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
978                         ++dev->estats.rx_dropped_resize;
979
980                 dev->rx_desc[i].data_len = 0;
981                 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
982                     (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
983         }
984
985         /* Reallocate RX ring only if bigger skb buffers are required */
986         if (rx_skb_size <= dev->rx_skb_size)
987                 goto skip;
988
989         /* Second pass, allocate new skbs */
990         for (i = 0; i < NUM_RX_BUFF; ++i) {
991                 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
992                 if (!skb) {
993                         ret = -ENOMEM;
994                         goto oom;
995                 }
996
997                 BUG_ON(!dev->rx_skb[i]);
998                 dev_kfree_skb(dev->rx_skb[i]);
999
1000                 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1001                 dev->rx_desc[i].data_ptr =
1002                     dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1003                                    DMA_FROM_DEVICE) + 2;
1004                 dev->rx_skb[i] = skb;
1005         }
1006  skip:
1007         /* Check if we need to change "Jumbo" bit in MR1 */
1008         if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
1009                 /* This is to prevent starting RX channel in emac_rx_enable() */
1010                 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1011
1012                 dev->ndev->mtu = new_mtu;
1013                 emac_full_tx_reset(dev);
1014         }
1015
1016         mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1017  oom:
1018         /* Restart RX */
1019         clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1020         dev->rx_slot = 0;
1021         mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1022         emac_rx_enable(dev);
1023         emac_netif_start(dev);
1024         mutex_unlock(&dev->link_lock);
1025
1026         return ret;
1027 }
1028
1029 /* Process ctx, rtnl_lock semaphore */
1030 static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1031 {
1032         struct emac_instance *dev = netdev_priv(ndev);
1033         int ret = 0;
1034
1035         if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
1036                 return -EINVAL;
1037
1038         DBG(dev, "change_mtu(%d)" NL, new_mtu);
1039
1040         if (netif_running(ndev)) {
1041                 /* Check if we really need to reinitalize RX ring */
1042                 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1043                         ret = emac_resize_rx_ring(dev, new_mtu);
1044         }
1045
1046         if (!ret) {
1047                 ndev->mtu = new_mtu;
1048                 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1049                 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1050         }
1051
1052         return ret;
1053 }
1054
1055 static void emac_clean_tx_ring(struct emac_instance *dev)
1056 {
1057         int i;
1058
1059         for (i = 0; i < NUM_TX_BUFF; ++i) {
1060                 if (dev->tx_skb[i]) {
1061                         dev_kfree_skb(dev->tx_skb[i]);
1062                         dev->tx_skb[i] = NULL;
1063                         if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1064                                 ++dev->estats.tx_dropped;
1065                 }
1066                 dev->tx_desc[i].ctrl = 0;
1067                 dev->tx_desc[i].data_ptr = 0;
1068         }
1069 }
1070
1071 static void emac_clean_rx_ring(struct emac_instance *dev)
1072 {
1073         int i;
1074
1075         for (i = 0; i < NUM_RX_BUFF; ++i)
1076                 if (dev->rx_skb[i]) {
1077                         dev->rx_desc[i].ctrl = 0;
1078                         dev_kfree_skb(dev->rx_skb[i]);
1079                         dev->rx_skb[i] = NULL;
1080                         dev->rx_desc[i].data_ptr = 0;
1081                 }
1082
1083         if (dev->rx_sg_skb) {
1084                 dev_kfree_skb(dev->rx_sg_skb);
1085                 dev->rx_sg_skb = NULL;
1086         }
1087 }
1088
1089 static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1090                                     gfp_t flags)
1091 {
1092         struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1093         if (unlikely(!skb))
1094                 return -ENOMEM;
1095
1096         dev->rx_skb[slot] = skb;
1097         dev->rx_desc[slot].data_len = 0;
1098
1099         skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1100         dev->rx_desc[slot].data_ptr =
1101             dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1102                            DMA_FROM_DEVICE) + 2;
1103         wmb();
1104         dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1105             (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1106
1107         return 0;
1108 }
1109
1110 static void emac_print_link_status(struct emac_instance *dev)
1111 {
1112         if (netif_carrier_ok(dev->ndev))
1113                 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1114                        dev->ndev->name, dev->phy.speed,
1115                        dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1116                        dev->phy.pause ? ", pause enabled" :
1117                        dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1118         else
1119                 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1120 }
1121
1122 /* Process ctx, rtnl_lock semaphore */
1123 static int emac_open(struct net_device *ndev)
1124 {
1125         struct emac_instance *dev = netdev_priv(ndev);
1126         int err, i;
1127
1128         DBG(dev, "open" NL);
1129
1130         /* Setup error IRQ handler */
1131         err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1132         if (err) {
1133                 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1134                        ndev->name, dev->emac_irq);
1135                 return err;
1136         }
1137
1138         /* Allocate RX ring */
1139         for (i = 0; i < NUM_RX_BUFF; ++i)
1140                 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1141                         printk(KERN_ERR "%s: failed to allocate RX ring\n",
1142                                ndev->name);
1143                         goto oom;
1144                 }
1145
1146         dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1147         clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1148         dev->rx_sg_skb = NULL;
1149
1150         mutex_lock(&dev->link_lock);
1151         dev->opened = 1;
1152
1153         /* Start PHY polling now.
1154          */
1155         if (dev->phy.address >= 0) {
1156                 int link_poll_interval;
1157                 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1158                         dev->phy.def->ops->read_link(&dev->phy);
1159                         emac_rx_clk_default(dev);
1160                         netif_carrier_on(dev->ndev);
1161                         link_poll_interval = PHY_POLL_LINK_ON;
1162                 } else {
1163                         emac_rx_clk_tx(dev);
1164                         netif_carrier_off(dev->ndev);
1165                         link_poll_interval = PHY_POLL_LINK_OFF;
1166                 }
1167                 dev->link_polling = 1;
1168                 wmb();
1169                 schedule_delayed_work(&dev->link_work, link_poll_interval);
1170                 emac_print_link_status(dev);
1171         } else
1172                 netif_carrier_on(dev->ndev);
1173
1174         /* Required for Pause packet support in EMAC */
1175         dev_mc_add(ndev, default_mcast_addr, sizeof(default_mcast_addr), 1);
1176
1177         emac_configure(dev);
1178         mal_poll_add(dev->mal, &dev->commac);
1179         mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1180         mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1181         mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1182         emac_tx_enable(dev);
1183         emac_rx_enable(dev);
1184         emac_netif_start(dev);
1185
1186         mutex_unlock(&dev->link_lock);
1187
1188         return 0;
1189  oom:
1190         emac_clean_rx_ring(dev);
1191         free_irq(dev->emac_irq, dev);
1192
1193         return -ENOMEM;
1194 }
1195
1196 /* BHs disabled */
1197 #if 0
1198 static int emac_link_differs(struct emac_instance *dev)
1199 {
1200         u32 r = in_be32(&dev->emacp->mr1);
1201
1202         int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1203         int speed, pause, asym_pause;
1204
1205         if (r & EMAC_MR1_MF_1000)
1206                 speed = SPEED_1000;
1207         else if (r & EMAC_MR1_MF_100)
1208                 speed = SPEED_100;
1209         else
1210                 speed = SPEED_10;
1211
1212         switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1213         case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1214                 pause = 1;
1215                 asym_pause = 0;
1216                 break;
1217         case EMAC_MR1_APP:
1218                 pause = 0;
1219                 asym_pause = 1;
1220                 break;
1221         default:
1222                 pause = asym_pause = 0;
1223         }
1224         return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1225             pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1226 }
1227 #endif
1228
1229 static void emac_link_timer(struct work_struct *work)
1230 {
1231         struct emac_instance *dev =
1232                 container_of(to_delayed_work(work),
1233                              struct emac_instance, link_work);
1234         int link_poll_interval;
1235
1236         mutex_lock(&dev->link_lock);
1237         DBG2(dev, "link timer" NL);
1238
1239         if (!dev->opened)
1240                 goto bail;
1241
1242         if (dev->phy.def->ops->poll_link(&dev->phy)) {
1243                 if (!netif_carrier_ok(dev->ndev)) {
1244                         emac_rx_clk_default(dev);
1245                         /* Get new link parameters */
1246                         dev->phy.def->ops->read_link(&dev->phy);
1247
1248                         netif_carrier_on(dev->ndev);
1249                         emac_netif_stop(dev);
1250                         emac_full_tx_reset(dev);
1251                         emac_netif_start(dev);
1252                         emac_print_link_status(dev);
1253                 }
1254                 link_poll_interval = PHY_POLL_LINK_ON;
1255         } else {
1256                 if (netif_carrier_ok(dev->ndev)) {
1257                         emac_rx_clk_tx(dev);
1258                         netif_carrier_off(dev->ndev);
1259                         netif_tx_disable(dev->ndev);
1260                         emac_reinitialize(dev);
1261                         emac_print_link_status(dev);
1262                 }
1263                 link_poll_interval = PHY_POLL_LINK_OFF;
1264         }
1265         schedule_delayed_work(&dev->link_work, link_poll_interval);
1266  bail:
1267         mutex_unlock(&dev->link_lock);
1268 }
1269
1270 static void emac_force_link_update(struct emac_instance *dev)
1271 {
1272         netif_carrier_off(dev->ndev);
1273         smp_rmb();
1274         if (dev->link_polling) {
1275                 cancel_rearming_delayed_work(&dev->link_work);
1276                 if (dev->link_polling)
1277                         schedule_delayed_work(&dev->link_work,  PHY_POLL_LINK_OFF);
1278         }
1279 }
1280
1281 /* Process ctx, rtnl_lock semaphore */
1282 static int emac_close(struct net_device *ndev)
1283 {
1284         struct emac_instance *dev = netdev_priv(ndev);
1285
1286         DBG(dev, "close" NL);
1287
1288         if (dev->phy.address >= 0) {
1289                 dev->link_polling = 0;
1290                 cancel_rearming_delayed_work(&dev->link_work);
1291         }
1292         mutex_lock(&dev->link_lock);
1293         emac_netif_stop(dev);
1294         dev->opened = 0;
1295         mutex_unlock(&dev->link_lock);
1296
1297         emac_rx_disable(dev);
1298         emac_tx_disable(dev);
1299         mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1300         mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1301         mal_poll_del(dev->mal, &dev->commac);
1302
1303         emac_clean_tx_ring(dev);
1304         emac_clean_rx_ring(dev);
1305
1306         free_irq(dev->emac_irq, dev);
1307
1308         netif_carrier_off(ndev);
1309
1310         return 0;
1311 }
1312
1313 static inline u16 emac_tx_csum(struct emac_instance *dev,
1314                                struct sk_buff *skb)
1315 {
1316         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1317                 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1318                 ++dev->stats.tx_packets_csum;
1319                 return EMAC_TX_CTRL_TAH_CSUM;
1320         }
1321         return 0;
1322 }
1323
1324 static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1325 {
1326         struct emac_regs __iomem *p = dev->emacp;
1327         struct net_device *ndev = dev->ndev;
1328
1329         /* Send the packet out. If the if makes a significant perf
1330          * difference, then we can store the TMR0 value in "dev"
1331          * instead
1332          */
1333         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1334                 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1335         else
1336                 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1337
1338         if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1339                 netif_stop_queue(ndev);
1340                 DBG2(dev, "stopped TX queue" NL);
1341         }
1342
1343         ndev->trans_start = jiffies;
1344         ++dev->stats.tx_packets;
1345         dev->stats.tx_bytes += len;
1346
1347         return NETDEV_TX_OK;
1348 }
1349
1350 /* Tx lock BH */
1351 static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1352 {
1353         struct emac_instance *dev = netdev_priv(ndev);
1354         unsigned int len = skb->len;
1355         int slot;
1356
1357         u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1358             MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1359
1360         slot = dev->tx_slot++;
1361         if (dev->tx_slot == NUM_TX_BUFF) {
1362                 dev->tx_slot = 0;
1363                 ctrl |= MAL_TX_CTRL_WRAP;
1364         }
1365
1366         DBG2(dev, "xmit(%u) %d" NL, len, slot);
1367
1368         dev->tx_skb[slot] = skb;
1369         dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1370                                                      skb->data, len,
1371                                                      DMA_TO_DEVICE);
1372         dev->tx_desc[slot].data_len = (u16) len;
1373         wmb();
1374         dev->tx_desc[slot].ctrl = ctrl;
1375
1376         return emac_xmit_finish(dev, len);
1377 }
1378
1379 static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1380                                   u32 pd, int len, int last, u16 base_ctrl)
1381 {
1382         while (1) {
1383                 u16 ctrl = base_ctrl;
1384                 int chunk = min(len, MAL_MAX_TX_SIZE);
1385                 len -= chunk;
1386
1387                 slot = (slot + 1) % NUM_TX_BUFF;
1388
1389                 if (last && !len)
1390                         ctrl |= MAL_TX_CTRL_LAST;
1391                 if (slot == NUM_TX_BUFF - 1)
1392                         ctrl |= MAL_TX_CTRL_WRAP;
1393
1394                 dev->tx_skb[slot] = NULL;
1395                 dev->tx_desc[slot].data_ptr = pd;
1396                 dev->tx_desc[slot].data_len = (u16) chunk;
1397                 dev->tx_desc[slot].ctrl = ctrl;
1398                 ++dev->tx_cnt;
1399
1400                 if (!len)
1401                         break;
1402
1403                 pd += chunk;
1404         }
1405         return slot;
1406 }
1407
1408 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1409 static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1410 {
1411         struct emac_instance *dev = netdev_priv(ndev);
1412         int nr_frags = skb_shinfo(skb)->nr_frags;
1413         int len = skb->len, chunk;
1414         int slot, i;
1415         u16 ctrl;
1416         u32 pd;
1417
1418         /* This is common "fast" path */
1419         if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1420                 return emac_start_xmit(skb, ndev);
1421
1422         len -= skb->data_len;
1423
1424         /* Note, this is only an *estimation*, we can still run out of empty
1425          * slots because of the additional fragmentation into
1426          * MAL_MAX_TX_SIZE-sized chunks
1427          */
1428         if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1429                 goto stop_queue;
1430
1431         ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1432             emac_tx_csum(dev, skb);
1433         slot = dev->tx_slot;
1434
1435         /* skb data */
1436         dev->tx_skb[slot] = NULL;
1437         chunk = min(len, MAL_MAX_TX_SIZE);
1438         dev->tx_desc[slot].data_ptr = pd =
1439             dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1440         dev->tx_desc[slot].data_len = (u16) chunk;
1441         len -= chunk;
1442         if (unlikely(len))
1443                 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1444                                        ctrl);
1445         /* skb fragments */
1446         for (i = 0; i < nr_frags; ++i) {
1447                 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1448                 len = frag->size;
1449
1450                 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1451                         goto undo_frame;
1452
1453                 pd = dma_map_page(&dev->ofdev->dev, frag->page, frag->page_offset, len,
1454                                   DMA_TO_DEVICE);
1455
1456                 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1457                                        ctrl);
1458         }
1459
1460         DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1461
1462         /* Attach skb to the last slot so we don't release it too early */
1463         dev->tx_skb[slot] = skb;
1464
1465         /* Send the packet out */
1466         if (dev->tx_slot == NUM_TX_BUFF - 1)
1467                 ctrl |= MAL_TX_CTRL_WRAP;
1468         wmb();
1469         dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1470         dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1471
1472         return emac_xmit_finish(dev, skb->len);
1473
1474  undo_frame:
1475         /* Well, too bad. Our previous estimation was overly optimistic.
1476          * Undo everything.
1477          */
1478         while (slot != dev->tx_slot) {
1479                 dev->tx_desc[slot].ctrl = 0;
1480                 --dev->tx_cnt;
1481                 if (--slot < 0)
1482                         slot = NUM_TX_BUFF - 1;
1483         }
1484         ++dev->estats.tx_undo;
1485
1486  stop_queue:
1487         netif_stop_queue(ndev);
1488         DBG2(dev, "stopped TX queue" NL);
1489         return NETDEV_TX_BUSY;
1490 }
1491
1492 /* Tx lock BHs */
1493 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1494 {
1495         struct emac_error_stats *st = &dev->estats;
1496
1497         DBG(dev, "BD TX error %04x" NL, ctrl);
1498
1499         ++st->tx_bd_errors;
1500         if (ctrl & EMAC_TX_ST_BFCS)
1501                 ++st->tx_bd_bad_fcs;
1502         if (ctrl & EMAC_TX_ST_LCS)
1503                 ++st->tx_bd_carrier_loss;
1504         if (ctrl & EMAC_TX_ST_ED)
1505                 ++st->tx_bd_excessive_deferral;
1506         if (ctrl & EMAC_TX_ST_EC)
1507                 ++st->tx_bd_excessive_collisions;
1508         if (ctrl & EMAC_TX_ST_LC)
1509                 ++st->tx_bd_late_collision;
1510         if (ctrl & EMAC_TX_ST_MC)
1511                 ++st->tx_bd_multple_collisions;
1512         if (ctrl & EMAC_TX_ST_SC)
1513                 ++st->tx_bd_single_collision;
1514         if (ctrl & EMAC_TX_ST_UR)
1515                 ++st->tx_bd_underrun;
1516         if (ctrl & EMAC_TX_ST_SQE)
1517                 ++st->tx_bd_sqe;
1518 }
1519
1520 static void emac_poll_tx(void *param)
1521 {
1522         struct emac_instance *dev = param;
1523         u32 bad_mask;
1524
1525         DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1526
1527         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1528                 bad_mask = EMAC_IS_BAD_TX_TAH;
1529         else
1530                 bad_mask = EMAC_IS_BAD_TX;
1531
1532         netif_tx_lock_bh(dev->ndev);
1533         if (dev->tx_cnt) {
1534                 u16 ctrl;
1535                 int slot = dev->ack_slot, n = 0;
1536         again:
1537                 ctrl = dev->tx_desc[slot].ctrl;
1538                 if (!(ctrl & MAL_TX_CTRL_READY)) {
1539                         struct sk_buff *skb = dev->tx_skb[slot];
1540                         ++n;
1541
1542                         if (skb) {
1543                                 dev_kfree_skb(skb);
1544                                 dev->tx_skb[slot] = NULL;
1545                         }
1546                         slot = (slot + 1) % NUM_TX_BUFF;
1547
1548                         if (unlikely(ctrl & bad_mask))
1549                                 emac_parse_tx_error(dev, ctrl);
1550
1551                         if (--dev->tx_cnt)
1552                                 goto again;
1553                 }
1554                 if (n) {
1555                         dev->ack_slot = slot;
1556                         if (netif_queue_stopped(dev->ndev) &&
1557                             dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1558                                 netif_wake_queue(dev->ndev);
1559
1560                         DBG2(dev, "tx %d pkts" NL, n);
1561                 }
1562         }
1563         netif_tx_unlock_bh(dev->ndev);
1564 }
1565
1566 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1567                                        int len)
1568 {
1569         struct sk_buff *skb = dev->rx_skb[slot];
1570
1571         DBG2(dev, "recycle %d %d" NL, slot, len);
1572
1573         if (len)
1574                 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1575                                EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1576
1577         dev->rx_desc[slot].data_len = 0;
1578         wmb();
1579         dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1580             (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1581 }
1582
1583 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1584 {
1585         struct emac_error_stats *st = &dev->estats;
1586
1587         DBG(dev, "BD RX error %04x" NL, ctrl);
1588
1589         ++st->rx_bd_errors;
1590         if (ctrl & EMAC_RX_ST_OE)
1591                 ++st->rx_bd_overrun;
1592         if (ctrl & EMAC_RX_ST_BP)
1593                 ++st->rx_bd_bad_packet;
1594         if (ctrl & EMAC_RX_ST_RP)
1595                 ++st->rx_bd_runt_packet;
1596         if (ctrl & EMAC_RX_ST_SE)
1597                 ++st->rx_bd_short_event;
1598         if (ctrl & EMAC_RX_ST_AE)
1599                 ++st->rx_bd_alignment_error;
1600         if (ctrl & EMAC_RX_ST_BFCS)
1601                 ++st->rx_bd_bad_fcs;
1602         if (ctrl & EMAC_RX_ST_PTL)
1603                 ++st->rx_bd_packet_too_long;
1604         if (ctrl & EMAC_RX_ST_ORE)
1605                 ++st->rx_bd_out_of_range;
1606         if (ctrl & EMAC_RX_ST_IRE)
1607                 ++st->rx_bd_in_range;
1608 }
1609
1610 static inline void emac_rx_csum(struct emac_instance *dev,
1611                                 struct sk_buff *skb, u16 ctrl)
1612 {
1613 #ifdef CONFIG_IBM_NEW_EMAC_TAH
1614         if (!ctrl && dev->tah_dev) {
1615                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1616                 ++dev->stats.rx_packets_csum;
1617         }
1618 #endif
1619 }
1620
1621 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1622 {
1623         if (likely(dev->rx_sg_skb != NULL)) {
1624                 int len = dev->rx_desc[slot].data_len;
1625                 int tot_len = dev->rx_sg_skb->len + len;
1626
1627                 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1628                         ++dev->estats.rx_dropped_mtu;
1629                         dev_kfree_skb(dev->rx_sg_skb);
1630                         dev->rx_sg_skb = NULL;
1631                 } else {
1632                         cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1633                                          dev->rx_skb[slot]->data, len);
1634                         skb_put(dev->rx_sg_skb, len);
1635                         emac_recycle_rx_skb(dev, slot, len);
1636                         return 0;
1637                 }
1638         }
1639         emac_recycle_rx_skb(dev, slot, 0);
1640         return -1;
1641 }
1642
1643 /* NAPI poll context */
1644 static int emac_poll_rx(void *param, int budget)
1645 {
1646         struct emac_instance *dev = param;
1647         int slot = dev->rx_slot, received = 0;
1648
1649         DBG2(dev, "poll_rx(%d)" NL, budget);
1650
1651  again:
1652         while (budget > 0) {
1653                 int len;
1654                 struct sk_buff *skb;
1655                 u16 ctrl = dev->rx_desc[slot].ctrl;
1656
1657                 if (ctrl & MAL_RX_CTRL_EMPTY)
1658                         break;
1659
1660                 skb = dev->rx_skb[slot];
1661                 mb();
1662                 len = dev->rx_desc[slot].data_len;
1663
1664                 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1665                         goto sg;
1666
1667                 ctrl &= EMAC_BAD_RX_MASK;
1668                 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1669                         emac_parse_rx_error(dev, ctrl);
1670                         ++dev->estats.rx_dropped_error;
1671                         emac_recycle_rx_skb(dev, slot, 0);
1672                         len = 0;
1673                         goto next;
1674                 }
1675
1676                 if (len < ETH_HLEN) {
1677                         ++dev->estats.rx_dropped_stack;
1678                         emac_recycle_rx_skb(dev, slot, len);
1679                         goto next;
1680                 }
1681
1682                 if (len && len < EMAC_RX_COPY_THRESH) {
1683                         struct sk_buff *copy_skb =
1684                             alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1685                         if (unlikely(!copy_skb))
1686                                 goto oom;
1687
1688                         skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1689                         cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1690                                          len + 2);
1691                         emac_recycle_rx_skb(dev, slot, len);
1692                         skb = copy_skb;
1693                 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1694                         goto oom;
1695
1696                 skb_put(skb, len);
1697         push_packet:
1698                 skb->dev = dev->ndev;
1699                 skb->protocol = eth_type_trans(skb, dev->ndev);
1700                 emac_rx_csum(dev, skb, ctrl);
1701
1702                 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1703                         ++dev->estats.rx_dropped_stack;
1704         next:
1705                 ++dev->stats.rx_packets;
1706         skip:
1707                 dev->stats.rx_bytes += len;
1708                 slot = (slot + 1) % NUM_RX_BUFF;
1709                 --budget;
1710                 ++received;
1711                 continue;
1712         sg:
1713                 if (ctrl & MAL_RX_CTRL_FIRST) {
1714                         BUG_ON(dev->rx_sg_skb);
1715                         if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1716                                 DBG(dev, "rx OOM %d" NL, slot);
1717                                 ++dev->estats.rx_dropped_oom;
1718                                 emac_recycle_rx_skb(dev, slot, 0);
1719                         } else {
1720                                 dev->rx_sg_skb = skb;
1721                                 skb_put(skb, len);
1722                         }
1723                 } else if (!emac_rx_sg_append(dev, slot) &&
1724                            (ctrl & MAL_RX_CTRL_LAST)) {
1725
1726                         skb = dev->rx_sg_skb;
1727                         dev->rx_sg_skb = NULL;
1728
1729                         ctrl &= EMAC_BAD_RX_MASK;
1730                         if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1731                                 emac_parse_rx_error(dev, ctrl);
1732                                 ++dev->estats.rx_dropped_error;
1733                                 dev_kfree_skb(skb);
1734                                 len = 0;
1735                         } else
1736                                 goto push_packet;
1737                 }
1738                 goto skip;
1739         oom:
1740                 DBG(dev, "rx OOM %d" NL, slot);
1741                 /* Drop the packet and recycle skb */
1742                 ++dev->estats.rx_dropped_oom;
1743                 emac_recycle_rx_skb(dev, slot, 0);
1744                 goto next;
1745         }
1746
1747         if (received) {
1748                 DBG2(dev, "rx %d BDs" NL, received);
1749                 dev->rx_slot = slot;
1750         }
1751
1752         if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1753                 mb();
1754                 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1755                         DBG2(dev, "rx restart" NL);
1756                         received = 0;
1757                         goto again;
1758                 }
1759
1760                 if (dev->rx_sg_skb) {
1761                         DBG2(dev, "dropping partial rx packet" NL);
1762                         ++dev->estats.rx_dropped_error;
1763                         dev_kfree_skb(dev->rx_sg_skb);
1764                         dev->rx_sg_skb = NULL;
1765                 }
1766
1767                 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1768                 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1769                 emac_rx_enable(dev);
1770                 dev->rx_slot = 0;
1771         }
1772         return received;
1773 }
1774
1775 /* NAPI poll context */
1776 static int emac_peek_rx(void *param)
1777 {
1778         struct emac_instance *dev = param;
1779
1780         return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1781 }
1782
1783 /* NAPI poll context */
1784 static int emac_peek_rx_sg(void *param)
1785 {
1786         struct emac_instance *dev = param;
1787
1788         int slot = dev->rx_slot;
1789         while (1) {
1790                 u16 ctrl = dev->rx_desc[slot].ctrl;
1791                 if (ctrl & MAL_RX_CTRL_EMPTY)
1792                         return 0;
1793                 else if (ctrl & MAL_RX_CTRL_LAST)
1794                         return 1;
1795
1796                 slot = (slot + 1) % NUM_RX_BUFF;
1797
1798                 /* I'm just being paranoid here :) */
1799                 if (unlikely(slot == dev->rx_slot))
1800                         return 0;
1801         }
1802 }
1803
1804 /* Hard IRQ */
1805 static void emac_rxde(void *param)
1806 {
1807         struct emac_instance *dev = param;
1808
1809         ++dev->estats.rx_stopped;
1810         emac_rx_disable_async(dev);
1811 }
1812
1813 /* Hard IRQ */
1814 static irqreturn_t emac_irq(int irq, void *dev_instance)
1815 {
1816         struct emac_instance *dev = dev_instance;
1817         struct emac_regs __iomem *p = dev->emacp;
1818         struct emac_error_stats *st = &dev->estats;
1819         u32 isr;
1820
1821         spin_lock(&dev->lock);
1822
1823         isr = in_be32(&p->isr);
1824         out_be32(&p->isr, isr);
1825
1826         DBG(dev, "isr = %08x" NL, isr);
1827
1828         if (isr & EMAC4_ISR_TXPE)
1829                 ++st->tx_parity;
1830         if (isr & EMAC4_ISR_RXPE)
1831                 ++st->rx_parity;
1832         if (isr & EMAC4_ISR_TXUE)
1833                 ++st->tx_underrun;
1834         if (isr & EMAC4_ISR_RXOE)
1835                 ++st->rx_fifo_overrun;
1836         if (isr & EMAC_ISR_OVR)
1837                 ++st->rx_overrun;
1838         if (isr & EMAC_ISR_BP)
1839                 ++st->rx_bad_packet;
1840         if (isr & EMAC_ISR_RP)
1841                 ++st->rx_runt_packet;
1842         if (isr & EMAC_ISR_SE)
1843                 ++st->rx_short_event;
1844         if (isr & EMAC_ISR_ALE)
1845                 ++st->rx_alignment_error;
1846         if (isr & EMAC_ISR_BFCS)
1847                 ++st->rx_bad_fcs;
1848         if (isr & EMAC_ISR_PTLE)
1849                 ++st->rx_packet_too_long;
1850         if (isr & EMAC_ISR_ORE)
1851                 ++st->rx_out_of_range;
1852         if (isr & EMAC_ISR_IRE)
1853                 ++st->rx_in_range;
1854         if (isr & EMAC_ISR_SQE)
1855                 ++st->tx_sqe;
1856         if (isr & EMAC_ISR_TE)
1857                 ++st->tx_errors;
1858
1859         spin_unlock(&dev->lock);
1860
1861         return IRQ_HANDLED;
1862 }
1863
1864 static struct net_device_stats *emac_stats(struct net_device *ndev)
1865 {
1866         struct emac_instance *dev = netdev_priv(ndev);
1867         struct emac_stats *st = &dev->stats;
1868         struct emac_error_stats *est = &dev->estats;
1869         struct net_device_stats *nst = &dev->nstats;
1870         unsigned long flags;
1871
1872         DBG2(dev, "stats" NL);
1873
1874         /* Compute "legacy" statistics */
1875         spin_lock_irqsave(&dev->lock, flags);
1876         nst->rx_packets = (unsigned long)st->rx_packets;
1877         nst->rx_bytes = (unsigned long)st->rx_bytes;
1878         nst->tx_packets = (unsigned long)st->tx_packets;
1879         nst->tx_bytes = (unsigned long)st->tx_bytes;
1880         nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1881                                           est->rx_dropped_error +
1882                                           est->rx_dropped_resize +
1883                                           est->rx_dropped_mtu);
1884         nst->tx_dropped = (unsigned long)est->tx_dropped;
1885
1886         nst->rx_errors = (unsigned long)est->rx_bd_errors;
1887         nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1888                                               est->rx_fifo_overrun +
1889                                               est->rx_overrun);
1890         nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1891                                                est->rx_alignment_error);
1892         nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1893                                              est->rx_bad_fcs);
1894         nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1895                                                 est->rx_bd_short_event +
1896                                                 est->rx_bd_packet_too_long +
1897                                                 est->rx_bd_out_of_range +
1898                                                 est->rx_bd_in_range +
1899                                                 est->rx_runt_packet +
1900                                                 est->rx_short_event +
1901                                                 est->rx_packet_too_long +
1902                                                 est->rx_out_of_range +
1903                                                 est->rx_in_range);
1904
1905         nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1906         nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1907                                               est->tx_underrun);
1908         nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1909         nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1910                                           est->tx_bd_excessive_collisions +
1911                                           est->tx_bd_late_collision +
1912                                           est->tx_bd_multple_collisions);
1913         spin_unlock_irqrestore(&dev->lock, flags);
1914         return nst;
1915 }
1916
1917 static struct mal_commac_ops emac_commac_ops = {
1918         .poll_tx = &emac_poll_tx,
1919         .poll_rx = &emac_poll_rx,
1920         .peek_rx = &emac_peek_rx,
1921         .rxde = &emac_rxde,
1922 };
1923
1924 static struct mal_commac_ops emac_commac_sg_ops = {
1925         .poll_tx = &emac_poll_tx,
1926         .poll_rx = &emac_poll_rx,
1927         .peek_rx = &emac_peek_rx_sg,
1928         .rxde = &emac_rxde,
1929 };
1930
1931 /* Ethtool support */
1932 static int emac_ethtool_get_settings(struct net_device *ndev,
1933                                      struct ethtool_cmd *cmd)
1934 {
1935         struct emac_instance *dev = netdev_priv(ndev);
1936
1937         cmd->supported = dev->phy.features;
1938         cmd->port = PORT_MII;
1939         cmd->phy_address = dev->phy.address;
1940         cmd->transceiver =
1941             dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1942
1943         mutex_lock(&dev->link_lock);
1944         cmd->advertising = dev->phy.advertising;
1945         cmd->autoneg = dev->phy.autoneg;
1946         cmd->speed = dev->phy.speed;
1947         cmd->duplex = dev->phy.duplex;
1948         mutex_unlock(&dev->link_lock);
1949
1950         return 0;
1951 }
1952
1953 static int emac_ethtool_set_settings(struct net_device *ndev,
1954                                      struct ethtool_cmd *cmd)
1955 {
1956         struct emac_instance *dev = netdev_priv(ndev);
1957         u32 f = dev->phy.features;
1958
1959         DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
1960             cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1961
1962         /* Basic sanity checks */
1963         if (dev->phy.address < 0)
1964                 return -EOPNOTSUPP;
1965         if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1966                 return -EINVAL;
1967         if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1968                 return -EINVAL;
1969         if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1970                 return -EINVAL;
1971
1972         if (cmd->autoneg == AUTONEG_DISABLE) {
1973                 switch (cmd->speed) {
1974                 case SPEED_10:
1975                         if (cmd->duplex == DUPLEX_HALF
1976                             && !(f & SUPPORTED_10baseT_Half))
1977                                 return -EINVAL;
1978                         if (cmd->duplex == DUPLEX_FULL
1979                             && !(f & SUPPORTED_10baseT_Full))
1980                                 return -EINVAL;
1981                         break;
1982                 case SPEED_100:
1983                         if (cmd->duplex == DUPLEX_HALF
1984                             && !(f & SUPPORTED_100baseT_Half))
1985                                 return -EINVAL;
1986                         if (cmd->duplex == DUPLEX_FULL
1987                             && !(f & SUPPORTED_100baseT_Full))
1988                                 return -EINVAL;
1989                         break;
1990                 case SPEED_1000:
1991                         if (cmd->duplex == DUPLEX_HALF
1992                             && !(f & SUPPORTED_1000baseT_Half))
1993                                 return -EINVAL;
1994                         if (cmd->duplex == DUPLEX_FULL
1995                             && !(f & SUPPORTED_1000baseT_Full))
1996                                 return -EINVAL;
1997                         break;
1998                 default:
1999                         return -EINVAL;
2000                 }
2001
2002                 mutex_lock(&dev->link_lock);
2003                 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
2004                                                 cmd->duplex);
2005                 mutex_unlock(&dev->link_lock);
2006
2007         } else {
2008                 if (!(f & SUPPORTED_Autoneg))
2009                         return -EINVAL;
2010
2011                 mutex_lock(&dev->link_lock);
2012                 dev->phy.def->ops->setup_aneg(&dev->phy,
2013                                               (cmd->advertising & f) |
2014                                               (dev->phy.advertising &
2015                                                (ADVERTISED_Pause |
2016                                                 ADVERTISED_Asym_Pause)));
2017                 mutex_unlock(&dev->link_lock);
2018         }
2019         emac_force_link_update(dev);
2020
2021         return 0;
2022 }
2023
2024 static void emac_ethtool_get_ringparam(struct net_device *ndev,
2025                                        struct ethtool_ringparam *rp)
2026 {
2027         rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2028         rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2029 }
2030
2031 static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2032                                         struct ethtool_pauseparam *pp)
2033 {
2034         struct emac_instance *dev = netdev_priv(ndev);
2035
2036         mutex_lock(&dev->link_lock);
2037         if ((dev->phy.features & SUPPORTED_Autoneg) &&
2038             (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2039                 pp->autoneg = 1;
2040
2041         if (dev->phy.duplex == DUPLEX_FULL) {
2042                 if (dev->phy.pause)
2043                         pp->rx_pause = pp->tx_pause = 1;
2044                 else if (dev->phy.asym_pause)
2045                         pp->tx_pause = 1;
2046         }
2047         mutex_unlock(&dev->link_lock);
2048 }
2049
2050 static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
2051 {
2052         struct emac_instance *dev = netdev_priv(ndev);
2053
2054         return dev->tah_dev != NULL;
2055 }
2056
2057 static int emac_get_regs_len(struct emac_instance *dev)
2058 {
2059         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
2060                 return sizeof(struct emac_ethtool_regs_subhdr) +
2061                         EMAC4_ETHTOOL_REGS_SIZE(dev);
2062         else
2063                 return sizeof(struct emac_ethtool_regs_subhdr) +
2064                         EMAC_ETHTOOL_REGS_SIZE(dev);
2065 }
2066
2067 static int emac_ethtool_get_regs_len(struct net_device *ndev)
2068 {
2069         struct emac_instance *dev = netdev_priv(ndev);
2070         int size;
2071
2072         size = sizeof(struct emac_ethtool_regs_hdr) +
2073                 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2074         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2075                 size += zmii_get_regs_len(dev->zmii_dev);
2076         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2077                 size += rgmii_get_regs_len(dev->rgmii_dev);
2078         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2079                 size += tah_get_regs_len(dev->tah_dev);
2080
2081         return size;
2082 }
2083
2084 static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2085 {
2086         struct emac_ethtool_regs_subhdr *hdr = buf;
2087
2088         hdr->index = dev->cell_index;
2089         if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2090                 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2091                 memcpy_fromio(hdr + 1, dev->emacp, EMAC4_ETHTOOL_REGS_SIZE(dev));
2092                 return ((void *)(hdr + 1) + EMAC4_ETHTOOL_REGS_SIZE(dev));
2093         } else {
2094                 hdr->version = EMAC_ETHTOOL_REGS_VER;
2095                 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE(dev));
2096                 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE(dev));
2097         }
2098 }
2099
2100 static void emac_ethtool_get_regs(struct net_device *ndev,
2101                                   struct ethtool_regs *regs, void *buf)
2102 {
2103         struct emac_instance *dev = netdev_priv(ndev);
2104         struct emac_ethtool_regs_hdr *hdr = buf;
2105
2106         hdr->components = 0;
2107         buf = hdr + 1;
2108
2109         buf = mal_dump_regs(dev->mal, buf);
2110         buf = emac_dump_regs(dev, buf);
2111         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2112                 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2113                 buf = zmii_dump_regs(dev->zmii_dev, buf);
2114         }
2115         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2116                 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2117                 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2118         }
2119         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2120                 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2121                 buf = tah_dump_regs(dev->tah_dev, buf);
2122         }
2123 }
2124
2125 static int emac_ethtool_nway_reset(struct net_device *ndev)
2126 {
2127         struct emac_instance *dev = netdev_priv(ndev);
2128         int res = 0;
2129
2130         DBG(dev, "nway_reset" NL);
2131
2132         if (dev->phy.address < 0)
2133                 return -EOPNOTSUPP;
2134
2135         mutex_lock(&dev->link_lock);
2136         if (!dev->phy.autoneg) {
2137                 res = -EINVAL;
2138                 goto out;
2139         }
2140
2141         dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2142  out:
2143         mutex_unlock(&dev->link_lock);
2144         emac_force_link_update(dev);
2145         return res;
2146 }
2147
2148 static int emac_ethtool_get_stats_count(struct net_device *ndev)
2149 {
2150         return EMAC_ETHTOOL_STATS_COUNT;
2151 }
2152
2153 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2154                                      u8 * buf)
2155 {
2156         if (stringset == ETH_SS_STATS)
2157                 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2158 }
2159
2160 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2161                                            struct ethtool_stats *estats,
2162                                            u64 * tmp_stats)
2163 {
2164         struct emac_instance *dev = netdev_priv(ndev);
2165
2166         memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2167         tmp_stats += sizeof(dev->stats) / sizeof(u64);
2168         memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2169 }
2170
2171 static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2172                                      struct ethtool_drvinfo *info)
2173 {
2174         struct emac_instance *dev = netdev_priv(ndev);
2175
2176         strcpy(info->driver, "ibm_emac");
2177         strcpy(info->version, DRV_VERSION);
2178         info->fw_version[0] = '\0';
2179         sprintf(info->bus_info, "PPC 4xx EMAC-%d %s",
2180                 dev->cell_index, dev->ofdev->node->full_name);
2181         info->n_stats = emac_ethtool_get_stats_count(ndev);
2182         info->regdump_len = emac_ethtool_get_regs_len(ndev);
2183 }
2184
2185 static const struct ethtool_ops emac_ethtool_ops = {
2186         .get_settings = emac_ethtool_get_settings,
2187         .set_settings = emac_ethtool_set_settings,
2188         .get_drvinfo = emac_ethtool_get_drvinfo,
2189
2190         .get_regs_len = emac_ethtool_get_regs_len,
2191         .get_regs = emac_ethtool_get_regs,
2192
2193         .nway_reset = emac_ethtool_nway_reset,
2194
2195         .get_ringparam = emac_ethtool_get_ringparam,
2196         .get_pauseparam = emac_ethtool_get_pauseparam,
2197
2198         .get_rx_csum = emac_ethtool_get_rx_csum,
2199
2200         .get_strings = emac_ethtool_get_strings,
2201         .get_stats_count = emac_ethtool_get_stats_count,
2202         .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2203
2204         .get_link = ethtool_op_get_link,
2205         .get_tx_csum = ethtool_op_get_tx_csum,
2206         .get_sg = ethtool_op_get_sg,
2207 };
2208
2209 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2210 {
2211         struct emac_instance *dev = netdev_priv(ndev);
2212         struct mii_ioctl_data *data = if_mii(rq);
2213
2214         DBG(dev, "ioctl %08x" NL, cmd);
2215
2216         if (dev->phy.address < 0)
2217                 return -EOPNOTSUPP;
2218
2219         switch (cmd) {
2220         case SIOCGMIIPHY:
2221                 data->phy_id = dev->phy.address;
2222                 /* Fall through */
2223         case SIOCGMIIREG:
2224                 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2225                                                data->reg_num);
2226                 return 0;
2227
2228         case SIOCSMIIREG:
2229                 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2230                                 data->val_in);
2231                 return 0;
2232         default:
2233                 return -EOPNOTSUPP;
2234         }
2235 }
2236
2237 struct emac_depentry {
2238         u32                     phandle;
2239         struct device_node      *node;
2240         struct of_device        *ofdev;
2241         void                    *drvdata;
2242 };
2243
2244 #define EMAC_DEP_MAL_IDX        0
2245 #define EMAC_DEP_ZMII_IDX       1
2246 #define EMAC_DEP_RGMII_IDX      2
2247 #define EMAC_DEP_TAH_IDX        3
2248 #define EMAC_DEP_MDIO_IDX       4
2249 #define EMAC_DEP_PREV_IDX       5
2250 #define EMAC_DEP_COUNT          6
2251
2252 static int __devinit emac_check_deps(struct emac_instance *dev,
2253                                      struct emac_depentry *deps)
2254 {
2255         int i, there = 0;
2256         struct device_node *np;
2257
2258         for (i = 0; i < EMAC_DEP_COUNT; i++) {
2259                 /* no dependency on that item, allright */
2260                 if (deps[i].phandle == 0) {
2261                         there++;
2262                         continue;
2263                 }
2264                 /* special case for blist as the dependency might go away */
2265                 if (i == EMAC_DEP_PREV_IDX) {
2266                         np = *(dev->blist - 1);
2267                         if (np == NULL) {
2268                                 deps[i].phandle = 0;
2269                                 there++;
2270                                 continue;
2271                         }
2272                         if (deps[i].node == NULL)
2273                                 deps[i].node = of_node_get(np);
2274                 }
2275                 if (deps[i].node == NULL)
2276                         deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2277                 if (deps[i].node == NULL)
2278                         continue;
2279                 if (deps[i].ofdev == NULL)
2280                         deps[i].ofdev = of_find_device_by_node(deps[i].node);
2281                 if (deps[i].ofdev == NULL)
2282                         continue;
2283                 if (deps[i].drvdata == NULL)
2284                         deps[i].drvdata = dev_get_drvdata(&deps[i].ofdev->dev);
2285                 if (deps[i].drvdata != NULL)
2286                         there++;
2287         }
2288         return (there == EMAC_DEP_COUNT);
2289 }
2290
2291 static void emac_put_deps(struct emac_instance *dev)
2292 {
2293         if (dev->mal_dev)
2294                 of_dev_put(dev->mal_dev);
2295         if (dev->zmii_dev)
2296                 of_dev_put(dev->zmii_dev);
2297         if (dev->rgmii_dev)
2298                 of_dev_put(dev->rgmii_dev);
2299         if (dev->mdio_dev)
2300                 of_dev_put(dev->mdio_dev);
2301         if (dev->tah_dev)
2302                 of_dev_put(dev->tah_dev);
2303 }
2304
2305 static int __devinit emac_of_bus_notify(struct notifier_block *nb,
2306                                         unsigned long action, void *data)
2307 {
2308         /* We are only intereted in device addition */
2309         if (action == BUS_NOTIFY_BOUND_DRIVER)
2310                 wake_up_all(&emac_probe_wait);
2311         return 0;
2312 }
2313
2314 static struct notifier_block emac_of_bus_notifier __devinitdata = {
2315         .notifier_call = emac_of_bus_notify
2316 };
2317
2318 static int __devinit emac_wait_deps(struct emac_instance *dev)
2319 {
2320         struct emac_depentry deps[EMAC_DEP_COUNT];
2321         int i, err;
2322
2323         memset(&deps, 0, sizeof(deps));
2324
2325         deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2326         deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2327         deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2328         if (dev->tah_ph)
2329                 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2330         if (dev->mdio_ph)
2331                 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2332         if (dev->blist && dev->blist > emac_boot_list)
2333                 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2334         bus_register_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2335         wait_event_timeout(emac_probe_wait,
2336                            emac_check_deps(dev, deps),
2337                            EMAC_PROBE_DEP_TIMEOUT);
2338         bus_unregister_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2339         err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2340         for (i = 0; i < EMAC_DEP_COUNT; i++) {
2341                 if (deps[i].node)
2342                         of_node_put(deps[i].node);
2343                 if (err && deps[i].ofdev)
2344                         of_dev_put(deps[i].ofdev);
2345         }
2346         if (err == 0) {
2347                 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2348                 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2349                 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2350                 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2351                 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2352         }
2353         if (deps[EMAC_DEP_PREV_IDX].ofdev)
2354                 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2355         return err;
2356 }
2357
2358 static int __devinit emac_read_uint_prop(struct device_node *np, const char *name,
2359                                          u32 *val, int fatal)
2360 {
2361         int len;
2362         const u32 *prop = of_get_property(np, name, &len);
2363         if (prop == NULL || len < sizeof(u32)) {
2364                 if (fatal)
2365                         printk(KERN_ERR "%s: missing %s property\n",
2366                                np->full_name, name);
2367                 return -ENODEV;
2368         }
2369         *val = *prop;
2370         return 0;
2371 }
2372
2373 static int __devinit emac_init_phy(struct emac_instance *dev)
2374 {
2375         struct device_node *np = dev->ofdev->node;
2376         struct net_device *ndev = dev->ndev;
2377         u32 phy_map, adv;
2378         int i;
2379
2380         dev->phy.dev = ndev;
2381         dev->phy.mode = dev->phy_mode;
2382
2383         /* PHY-less configuration.
2384          * XXX I probably should move these settings to the dev tree
2385          */
2386         if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2387                 emac_reset(dev);
2388
2389                 /* PHY-less configuration.
2390                  * XXX I probably should move these settings to the dev tree
2391                  */
2392                 dev->phy.address = -1;
2393                 dev->phy.features = SUPPORTED_MII;
2394                 if (emac_phy_supports_gige(dev->phy_mode))
2395                         dev->phy.features |= SUPPORTED_1000baseT_Full;
2396                 else
2397                         dev->phy.features |= SUPPORTED_100baseT_Full;
2398                 dev->phy.pause = 1;
2399
2400                 return 0;
2401         }
2402
2403         mutex_lock(&emac_phy_map_lock);
2404         phy_map = dev->phy_map | busy_phy_map;
2405
2406         DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2407
2408         dev->phy.mdio_read = emac_mdio_read;
2409         dev->phy.mdio_write = emac_mdio_write;
2410
2411         /* Enable internal clock source */
2412 #ifdef CONFIG_PPC_DCR_NATIVE
2413         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2414                 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2415 #endif
2416         /* PHY clock workaround */
2417         emac_rx_clk_tx(dev);
2418
2419         /* Enable internal clock source on 440GX*/
2420 #ifdef CONFIG_PPC_DCR_NATIVE
2421         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2422                 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2423 #endif
2424         /* Configure EMAC with defaults so we can at least use MDIO
2425          * This is needed mostly for 440GX
2426          */
2427         if (emac_phy_gpcs(dev->phy.mode)) {
2428                 /* XXX
2429                  * Make GPCS PHY address equal to EMAC index.
2430                  * We probably should take into account busy_phy_map
2431                  * and/or phy_map here.
2432                  *
2433                  * Note that the busy_phy_map is currently global
2434                  * while it should probably be per-ASIC...
2435                  */
2436                 dev->phy.gpcs_address = dev->gpcs_address;
2437                 if (dev->phy.gpcs_address == 0xffffffff)
2438                         dev->phy.address = dev->cell_index;
2439         }
2440
2441         emac_configure(dev);
2442
2443         if (dev->phy_address != 0xffffffff)
2444                 phy_map = ~(1 << dev->phy_address);
2445
2446         for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2447                 if (!(phy_map & 1)) {
2448                         int r;
2449                         busy_phy_map |= 1 << i;
2450
2451                         /* Quick check if there is a PHY at the address */
2452                         r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2453                         if (r == 0xffff || r < 0)
2454                                 continue;
2455                         if (!emac_mii_phy_probe(&dev->phy, i))
2456                                 break;
2457                 }
2458
2459         /* Enable external clock source */
2460 #ifdef CONFIG_PPC_DCR_NATIVE
2461         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2462                 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2463 #endif
2464         mutex_unlock(&emac_phy_map_lock);
2465         if (i == 0x20) {
2466                 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2467                 return -ENXIO;
2468         }
2469
2470         /* Init PHY */
2471         if (dev->phy.def->ops->init)
2472                 dev->phy.def->ops->init(&dev->phy);
2473
2474         /* Disable any PHY features not supported by the platform */
2475         dev->phy.def->features &= ~dev->phy_feat_exc;
2476
2477         /* Setup initial link parameters */
2478         if (dev->phy.features & SUPPORTED_Autoneg) {
2479                 adv = dev->phy.features;
2480                 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2481                         adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2482                 /* Restart autonegotiation */
2483                 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2484         } else {
2485                 u32 f = dev->phy.def->features;
2486                 int speed = SPEED_10, fd = DUPLEX_HALF;
2487
2488                 /* Select highest supported speed/duplex */
2489                 if (f & SUPPORTED_1000baseT_Full) {
2490                         speed = SPEED_1000;
2491                         fd = DUPLEX_FULL;
2492                 } else if (f & SUPPORTED_1000baseT_Half)
2493                         speed = SPEED_1000;
2494                 else if (f & SUPPORTED_100baseT_Full) {
2495                         speed = SPEED_100;
2496                         fd = DUPLEX_FULL;
2497                 } else if (f & SUPPORTED_100baseT_Half)
2498                         speed = SPEED_100;
2499                 else if (f & SUPPORTED_10baseT_Full)
2500                         fd = DUPLEX_FULL;
2501
2502                 /* Force link parameters */
2503                 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2504         }
2505         return 0;
2506 }
2507
2508 static int __devinit emac_init_config(struct emac_instance *dev)
2509 {
2510         struct device_node *np = dev->ofdev->node;
2511         const void *p;
2512         unsigned int plen;
2513         const char *pm, *phy_modes[] = {
2514                 [PHY_MODE_NA] = "",
2515                 [PHY_MODE_MII] = "mii",
2516                 [PHY_MODE_RMII] = "rmii",
2517                 [PHY_MODE_SMII] = "smii",
2518                 [PHY_MODE_RGMII] = "rgmii",
2519                 [PHY_MODE_TBI] = "tbi",
2520                 [PHY_MODE_GMII] = "gmii",
2521                 [PHY_MODE_RTBI] = "rtbi",
2522                 [PHY_MODE_SGMII] = "sgmii",
2523         };
2524
2525         /* Read config from device-tree */
2526         if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2527                 return -ENXIO;
2528         if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2529                 return -ENXIO;
2530         if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2531                 return -ENXIO;
2532         if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2533                 return -ENXIO;
2534         if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2535                 dev->max_mtu = 1500;
2536         if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2537                 dev->rx_fifo_size = 2048;
2538         if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2539                 dev->tx_fifo_size = 2048;
2540         if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2541                 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2542         if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2543                 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2544         if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2545                 dev->phy_address = 0xffffffff;
2546         if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2547                 dev->phy_map = 0xffffffff;
2548         if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2549                 dev->gpcs_address = 0xffffffff;
2550         if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2551                 return -ENXIO;
2552         if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2553                 dev->tah_ph = 0;
2554         if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2555                 dev->tah_port = 0;
2556         if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2557                 dev->mdio_ph = 0;
2558         if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2559                 dev->zmii_ph = 0;
2560         if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2561                 dev->zmii_port = 0xffffffff;
2562         if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2563                 dev->rgmii_ph = 0;
2564         if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2565                 dev->rgmii_port = 0xffffffff;
2566         if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2567                 dev->fifo_entry_size = 16;
2568         if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2569                 dev->mal_burst_size = 256;
2570
2571         /* PHY mode needs some decoding */
2572         dev->phy_mode = PHY_MODE_NA;
2573         pm = of_get_property(np, "phy-mode", &plen);
2574         if (pm != NULL) {
2575                 int i;
2576                 for (i = 0; i < ARRAY_SIZE(phy_modes); i++)
2577                         if (!strcasecmp(pm, phy_modes[i])) {
2578                                 dev->phy_mode = i;
2579                                 break;
2580                         }
2581         }
2582
2583         /* Backward compat with non-final DT */
2584         if (dev->phy_mode == PHY_MODE_NA && pm != NULL && plen == 4) {
2585                 u32 nmode = *(const u32 *)pm;
2586                 if (nmode > PHY_MODE_NA && nmode <= PHY_MODE_SGMII)
2587                         dev->phy_mode = nmode;
2588         }
2589
2590         /* Check EMAC version */
2591         if (of_device_is_compatible(np, "ibm,emac4sync")) {
2592                 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2593                 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2594                     of_device_is_compatible(np, "ibm,emac-460gt"))
2595                         dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2596                 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2597                     of_device_is_compatible(np, "ibm,emac-405exr"))
2598                         dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2599         } else if (of_device_is_compatible(np, "ibm,emac4")) {
2600                 dev->features |= EMAC_FTR_EMAC4;
2601                 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2602                         dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2603         } else {
2604                 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2605                     of_device_is_compatible(np, "ibm,emac-440gr"))
2606                         dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2607                 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2608 #ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL
2609                         dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2610 #else
2611                         printk(KERN_ERR "%s: Flow control not disabled!\n",
2612                                         np->full_name);
2613                         return -ENXIO;
2614 #endif
2615                 }
2616
2617         }
2618
2619         /* Fixup some feature bits based on the device tree */
2620         if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2621                 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2622         if (of_get_property(np, "has-new-stacr-staopc", NULL))
2623                 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2624
2625         /* CAB lacks the appropriate properties */
2626         if (of_device_is_compatible(np, "ibm,emac-axon"))
2627                 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2628                         EMAC_FTR_STACR_OC_INVERT;
2629
2630         /* Enable TAH/ZMII/RGMII features as found */
2631         if (dev->tah_ph != 0) {
2632 #ifdef CONFIG_IBM_NEW_EMAC_TAH
2633                 dev->features |= EMAC_FTR_HAS_TAH;
2634 #else
2635                 printk(KERN_ERR "%s: TAH support not enabled !\n",
2636                        np->full_name);
2637                 return -ENXIO;
2638 #endif
2639         }
2640
2641         if (dev->zmii_ph != 0) {
2642 #ifdef CONFIG_IBM_NEW_EMAC_ZMII
2643                 dev->features |= EMAC_FTR_HAS_ZMII;
2644 #else
2645                 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2646                        np->full_name);
2647                 return -ENXIO;
2648 #endif
2649         }
2650
2651         if (dev->rgmii_ph != 0) {
2652 #ifdef CONFIG_IBM_NEW_EMAC_RGMII
2653                 dev->features |= EMAC_FTR_HAS_RGMII;
2654 #else
2655                 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2656                        np->full_name);
2657                 return -ENXIO;
2658 #endif
2659         }
2660
2661         /* Read MAC-address */
2662         p = of_get_property(np, "local-mac-address", NULL);
2663         if (p == NULL) {
2664                 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2665                        np->full_name);
2666                 return -ENXIO;
2667         }
2668         memcpy(dev->ndev->dev_addr, p, 6);
2669
2670         /* IAHT and GAHT filter parameterization */
2671         if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2672                 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2673                 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2674         } else {
2675                 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2676                 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2677         }
2678
2679         DBG(dev, "features     : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2680         DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2681         DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2682         DBG(dev, "max_mtu      : %d\n", dev->max_mtu);
2683         DBG(dev, "OPB freq     : %d\n", dev->opb_bus_freq);
2684
2685         return 0;
2686 }
2687
2688 static const struct net_device_ops emac_netdev_ops = {
2689         .ndo_open               = emac_open,
2690         .ndo_stop               = emac_close,
2691         .ndo_get_stats          = emac_stats,
2692         .ndo_set_multicast_list = emac_set_multicast_list,
2693         .ndo_do_ioctl           = emac_ioctl,
2694         .ndo_tx_timeout         = emac_tx_timeout,
2695         .ndo_validate_addr      = eth_validate_addr,
2696         .ndo_set_mac_address    = eth_mac_addr,
2697         .ndo_start_xmit         = emac_start_xmit,
2698         .ndo_change_mtu         = eth_change_mtu,
2699 };
2700
2701 static const struct net_device_ops emac_gige_netdev_ops = {
2702         .ndo_open               = emac_open,
2703         .ndo_stop               = emac_close,
2704         .ndo_get_stats          = emac_stats,
2705         .ndo_set_multicast_list = emac_set_multicast_list,
2706         .ndo_do_ioctl           = emac_ioctl,
2707         .ndo_tx_timeout         = emac_tx_timeout,
2708         .ndo_validate_addr      = eth_validate_addr,
2709         .ndo_set_mac_address    = eth_mac_addr,
2710         .ndo_start_xmit         = emac_start_xmit_sg,
2711         .ndo_change_mtu         = emac_change_mtu,
2712 };
2713
2714 static int __devinit emac_probe(struct of_device *ofdev,
2715                                 const struct of_device_id *match)
2716 {
2717         struct net_device *ndev;
2718         struct emac_instance *dev;
2719         struct device_node *np = ofdev->node;
2720         struct device_node **blist = NULL;
2721         int err, i;
2722
2723         /* Skip unused/unwired EMACS.  We leave the check for an unused
2724          * property here for now, but new flat device trees should set a
2725          * status property to "disabled" instead.
2726          */
2727         if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
2728                 return -ENODEV;
2729
2730         /* Find ourselves in the bootlist if we are there */
2731         for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2732                 if (emac_boot_list[i] == np)
2733                         blist = &emac_boot_list[i];
2734
2735         /* Allocate our net_device structure */
2736         err = -ENOMEM;
2737         ndev = alloc_etherdev(sizeof(struct emac_instance));
2738         if (!ndev) {
2739                 printk(KERN_ERR "%s: could not allocate ethernet device!\n",
2740                        np->full_name);
2741                 goto err_gone;
2742         }
2743         dev = netdev_priv(ndev);
2744         dev->ndev = ndev;
2745         dev->ofdev = ofdev;
2746         dev->blist = blist;
2747         SET_NETDEV_DEV(ndev, &ofdev->dev);
2748
2749         /* Initialize some embedded data structures */
2750         mutex_init(&dev->mdio_lock);
2751         mutex_init(&dev->link_lock);
2752         spin_lock_init(&dev->lock);
2753         INIT_WORK(&dev->reset_work, emac_reset_work);
2754
2755         /* Init various config data based on device-tree */
2756         err = emac_init_config(dev);
2757         if (err != 0)
2758                 goto err_free;
2759
2760         /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2761         dev->emac_irq = irq_of_parse_and_map(np, 0);
2762         dev->wol_irq = irq_of_parse_and_map(np, 1);
2763         if (dev->emac_irq == NO_IRQ) {
2764                 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2765                 goto err_free;
2766         }
2767         ndev->irq = dev->emac_irq;
2768
2769         /* Map EMAC regs */
2770         if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2771                 printk(KERN_ERR "%s: Can't get registers address\n",
2772                        np->full_name);
2773                 goto err_irq_unmap;
2774         }
2775         // TODO : request_mem_region
2776         dev->emacp = ioremap(dev->rsrc_regs.start,
2777                              dev->rsrc_regs.end - dev->rsrc_regs.start + 1);
2778         if (dev->emacp == NULL) {
2779                 printk(KERN_ERR "%s: Can't map device registers!\n",
2780                        np->full_name);
2781                 err = -ENOMEM;
2782                 goto err_irq_unmap;
2783         }
2784
2785         /* Wait for dependent devices */
2786         err = emac_wait_deps(dev);
2787         if (err) {
2788                 printk(KERN_ERR
2789                        "%s: Timeout waiting for dependent devices\n",
2790                        np->full_name);
2791                 /*  display more info about what's missing ? */
2792                 goto err_reg_unmap;
2793         }
2794         dev->mal = dev_get_drvdata(&dev->mal_dev->dev);
2795         if (dev->mdio_dev != NULL)
2796                 dev->mdio_instance = dev_get_drvdata(&dev->mdio_dev->dev);
2797
2798         /* Register with MAL */
2799         dev->commac.ops = &emac_commac_ops;
2800         dev->commac.dev = dev;
2801         dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2802         dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2803         err = mal_register_commac(dev->mal, &dev->commac);
2804         if (err) {
2805                 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2806                        np->full_name, dev->mal_dev->node->full_name);
2807                 goto err_rel_deps;
2808         }
2809         dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2810         dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2811
2812         /* Get pointers to BD rings */
2813         dev->tx_desc =
2814             dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2815         dev->rx_desc =
2816             dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2817
2818         DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2819         DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2820
2821         /* Clean rings */
2822         memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2823         memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2824         memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
2825         memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
2826
2827         /* Attach to ZMII, if needed */
2828         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2829             (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2830                 goto err_unreg_commac;
2831
2832         /* Attach to RGMII, if needed */
2833         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2834             (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2835                 goto err_detach_zmii;
2836
2837         /* Attach to TAH, if needed */
2838         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2839             (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2840                 goto err_detach_rgmii;
2841
2842         /* Set some link defaults before we can find out real parameters */
2843         dev->phy.speed = SPEED_100;
2844         dev->phy.duplex = DUPLEX_FULL;
2845         dev->phy.autoneg = AUTONEG_DISABLE;
2846         dev->phy.pause = dev->phy.asym_pause = 0;
2847         dev->stop_timeout = STOP_TIMEOUT_100;
2848         INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2849
2850         /* Find PHY if any */
2851         err = emac_init_phy(dev);
2852         if (err != 0)
2853                 goto err_detach_tah;
2854
2855         if (dev->tah_dev)
2856                 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2857         ndev->watchdog_timeo = 5 * HZ;
2858         if (emac_phy_supports_gige(dev->phy_mode)) {
2859                 ndev->netdev_ops = &emac_gige_netdev_ops;
2860                 dev->commac.ops = &emac_commac_sg_ops;
2861         } else
2862                 ndev->netdev_ops = &emac_netdev_ops;
2863         SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2864
2865         netif_carrier_off(ndev);
2866         netif_stop_queue(ndev);
2867
2868         err = register_netdev(ndev);
2869         if (err) {
2870                 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2871                        np->full_name, err);
2872                 goto err_detach_tah;
2873         }
2874
2875         /* Set our drvdata last as we don't want them visible until we are
2876          * fully initialized
2877          */
2878         wmb();
2879         dev_set_drvdata(&ofdev->dev, dev);
2880
2881         /* There's a new kid in town ! Let's tell everybody */
2882         wake_up_all(&emac_probe_wait);
2883
2884
2885         printk(KERN_INFO "%s: EMAC-%d %s, MAC %pM\n",
2886                ndev->name, dev->cell_index, np->full_name, ndev->dev_addr);
2887
2888         if (dev->phy_mode == PHY_MODE_SGMII)
2889                 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
2890
2891         if (dev->phy.address >= 0)
2892                 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2893                        dev->phy.def->name, dev->phy.address);
2894
2895         emac_dbg_register(dev);
2896
2897         /* Life is good */
2898         return 0;
2899
2900         /* I have a bad feeling about this ... */
2901
2902  err_detach_tah:
2903         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2904                 tah_detach(dev->tah_dev, dev->tah_port);
2905  err_detach_rgmii:
2906         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2907                 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2908  err_detach_zmii:
2909         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2910                 zmii_detach(dev->zmii_dev, dev->zmii_port);
2911  err_unreg_commac:
2912         mal_unregister_commac(dev->mal, &dev->commac);
2913  err_rel_deps:
2914         emac_put_deps(dev);
2915  err_reg_unmap:
2916         iounmap(dev->emacp);
2917  err_irq_unmap:
2918         if (dev->wol_irq != NO_IRQ)
2919                 irq_dispose_mapping(dev->wol_irq);
2920         if (dev->emac_irq != NO_IRQ)
2921                 irq_dispose_mapping(dev->emac_irq);
2922  err_free:
2923         kfree(ndev);
2924  err_gone:
2925         /* if we were on the bootlist, remove us as we won't show up and
2926          * wake up all waiters to notify them in case they were waiting
2927          * on us
2928          */
2929         if (blist) {
2930                 *blist = NULL;
2931                 wake_up_all(&emac_probe_wait);
2932         }
2933         return err;
2934 }
2935
2936 static int __devexit emac_remove(struct of_device *ofdev)
2937 {
2938         struct emac_instance *dev = dev_get_drvdata(&ofdev->dev);
2939
2940         DBG(dev, "remove" NL);
2941
2942         dev_set_drvdata(&ofdev->dev, NULL);
2943
2944         unregister_netdev(dev->ndev);
2945
2946         flush_scheduled_work();
2947
2948         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2949                 tah_detach(dev->tah_dev, dev->tah_port);
2950         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2951                 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2952         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2953                 zmii_detach(dev->zmii_dev, dev->zmii_port);
2954
2955         mal_unregister_commac(dev->mal, &dev->commac);
2956         emac_put_deps(dev);
2957
2958         emac_dbg_unregister(dev);
2959         iounmap(dev->emacp);
2960
2961         if (dev->wol_irq != NO_IRQ)
2962                 irq_dispose_mapping(dev->wol_irq);
2963         if (dev->emac_irq != NO_IRQ)
2964                 irq_dispose_mapping(dev->emac_irq);
2965
2966         kfree(dev->ndev);
2967
2968         return 0;
2969 }
2970
2971 /* XXX Features in here should be replaced by properties... */
2972 static struct of_device_id emac_match[] =
2973 {
2974         {
2975                 .type           = "network",
2976                 .compatible     = "ibm,emac",
2977         },
2978         {
2979                 .type           = "network",
2980                 .compatible     = "ibm,emac4",
2981         },
2982         {
2983                 .type           = "network",
2984                 .compatible     = "ibm,emac4sync",
2985         },
2986         {},
2987 };
2988
2989 static struct of_platform_driver emac_driver = {
2990         .name = "emac",
2991         .match_table = emac_match,
2992
2993         .probe = emac_probe,
2994         .remove = emac_remove,
2995 };
2996
2997 static void __init emac_make_bootlist(void)
2998 {
2999         struct device_node *np = NULL;
3000         int j, max, i = 0, k;
3001         int cell_indices[EMAC_BOOT_LIST_SIZE];
3002
3003         /* Collect EMACs */
3004         while((np = of_find_all_nodes(np)) != NULL) {
3005                 const u32 *idx;
3006
3007                 if (of_match_node(emac_match, np) == NULL)
3008                         continue;
3009                 if (of_get_property(np, "unused", NULL))
3010                         continue;
3011                 idx = of_get_property(np, "cell-index", NULL);
3012                 if (idx == NULL)
3013                         continue;
3014                 cell_indices[i] = *idx;
3015                 emac_boot_list[i++] = of_node_get(np);
3016                 if (i >= EMAC_BOOT_LIST_SIZE) {
3017                         of_node_put(np);
3018                         break;
3019                 }
3020         }
3021         max = i;
3022
3023         /* Bubble sort them (doh, what a creative algorithm :-) */
3024         for (i = 0; max > 1 && (i < (max - 1)); i++)
3025                 for (j = i; j < max; j++) {
3026                         if (cell_indices[i] > cell_indices[j]) {
3027                                 np = emac_boot_list[i];
3028                                 emac_boot_list[i] = emac_boot_list[j];
3029                                 emac_boot_list[j] = np;
3030                                 k = cell_indices[i];
3031                                 cell_indices[i] = cell_indices[j];
3032                                 cell_indices[j] = k;
3033                         }
3034                 }
3035 }
3036
3037 static int __init emac_init(void)
3038 {
3039         int rc;
3040
3041         printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3042
3043         /* Init debug stuff */
3044         emac_init_debug();
3045
3046         /* Build EMAC boot list */
3047         emac_make_bootlist();
3048
3049         /* Init submodules */
3050         rc = mal_init();
3051         if (rc)
3052                 goto err;
3053         rc = zmii_init();
3054         if (rc)
3055                 goto err_mal;
3056         rc = rgmii_init();
3057         if (rc)
3058                 goto err_zmii;
3059         rc = tah_init();
3060         if (rc)
3061                 goto err_rgmii;
3062         rc = of_register_platform_driver(&emac_driver);
3063         if (rc)
3064                 goto err_tah;
3065
3066         return 0;
3067
3068  err_tah:
3069         tah_exit();
3070  err_rgmii:
3071         rgmii_exit();
3072  err_zmii:
3073         zmii_exit();
3074  err_mal:
3075         mal_exit();
3076  err:
3077         return rc;
3078 }
3079
3080 static void __exit emac_exit(void)
3081 {
3082         int i;
3083
3084         of_unregister_platform_driver(&emac_driver);
3085
3086         tah_exit();
3087         rgmii_exit();
3088         zmii_exit();
3089         mal_exit();
3090         emac_fini_debug();
3091
3092         /* Destroy EMAC boot list */
3093         for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3094                 if (emac_boot_list[i])
3095                         of_node_put(emac_boot_list[i]);
3096 }
3097
3098 module_init(emac_init);
3099 module_exit(emac_exit);