atomic: use <linux/atomic.h>
[linux-2.6.git] / drivers / net / hamradio / dmascc.c
1 /*
2  * Driver for high-speed SCC boards (those with DMA support)
3  * Copyright (C) 1997-2000 Klaus Kudielka
4  *
5  * S5SCC/DMA support by Janko Koleznik S52HI
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22
23 #include <linux/module.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/errno.h>
27 #include <linux/if_arp.h>
28 #include <linux/in.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/kernel.h>
33 #include <linux/mm.h>
34 #include <linux/netdevice.h>
35 #include <linux/slab.h>
36 #include <linux/rtnetlink.h>
37 #include <linux/sockios.h>
38 #include <linux/workqueue.h>
39 #include <linux/atomic.h>
40 #include <asm/dma.h>
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/uaccess.h>
44 #include <net/ax25.h>
45 #include "z8530.h"
46
47
48 /* Number of buffers per channel */
49
50 #define NUM_TX_BUF      2       /* NUM_TX_BUF >= 1 (min. 2 recommended) */
51 #define NUM_RX_BUF      6       /* NUM_RX_BUF >= 1 (min. 2 recommended) */
52 #define BUF_SIZE        1576    /* BUF_SIZE >= mtu + hard_header_len */
53
54
55 /* Cards supported */
56
57 #define HW_PI           { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
58                             0, 8, 1843200, 3686400 }
59 #define HW_PI2          { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
60                             0, 8, 3686400, 7372800 }
61 #define HW_TWIN         { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
62                             0, 4, 6144000, 6144000 }
63 #define HW_S5           { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
64                           0, 8, 4915200, 9830400 }
65
66 #define HARDWARE        { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
67
68 #define TMR_0_HZ        25600   /* Frequency of timer 0 */
69
70 #define TYPE_PI         0
71 #define TYPE_PI2        1
72 #define TYPE_TWIN       2
73 #define TYPE_S5         3
74 #define NUM_TYPES       4
75
76 #define MAX_NUM_DEVS    32
77
78
79 /* SCC chips supported */
80
81 #define Z8530           0
82 #define Z85C30          1
83 #define Z85230          2
84
85 #define CHIPNAMES       { "Z8530", "Z85C30", "Z85230" }
86
87
88 /* I/O registers */
89
90 /* 8530 registers relative to card base */
91 #define SCCB_CMD        0x00
92 #define SCCB_DATA       0x01
93 #define SCCA_CMD        0x02
94 #define SCCA_DATA       0x03
95
96 /* 8253/8254 registers relative to card base */
97 #define TMR_CNT0        0x00
98 #define TMR_CNT1        0x01
99 #define TMR_CNT2        0x02
100 #define TMR_CTRL        0x03
101
102 /* Additional PI/PI2 registers relative to card base */
103 #define PI_DREQ_MASK    0x04
104
105 /* Additional PackeTwin registers relative to card base */
106 #define TWIN_INT_REG    0x08
107 #define TWIN_CLR_TMR1   0x09
108 #define TWIN_CLR_TMR2   0x0a
109 #define TWIN_SPARE_1    0x0b
110 #define TWIN_DMA_CFG    0x08
111 #define TWIN_SERIAL_CFG 0x09
112 #define TWIN_DMA_CLR_FF 0x0a
113 #define TWIN_SPARE_2    0x0b
114
115
116 /* PackeTwin I/O register values */
117
118 /* INT_REG */
119 #define TWIN_SCC_MSK       0x01
120 #define TWIN_TMR1_MSK      0x02
121 #define TWIN_TMR2_MSK      0x04
122 #define TWIN_INT_MSK       0x07
123
124 /* SERIAL_CFG */
125 #define TWIN_DTRA_ON       0x01
126 #define TWIN_DTRB_ON       0x02
127 #define TWIN_EXTCLKA       0x04
128 #define TWIN_EXTCLKB       0x08
129 #define TWIN_LOOPA_ON      0x10
130 #define TWIN_LOOPB_ON      0x20
131 #define TWIN_EI            0x80
132
133 /* DMA_CFG */
134 #define TWIN_DMA_HDX_T1    0x08
135 #define TWIN_DMA_HDX_R1    0x0a
136 #define TWIN_DMA_HDX_T3    0x14
137 #define TWIN_DMA_HDX_R3    0x16
138 #define TWIN_DMA_FDX_T3R1  0x1b
139 #define TWIN_DMA_FDX_T1R3  0x1d
140
141
142 /* Status values */
143
144 #define IDLE      0
145 #define TX_HEAD   1
146 #define TX_DATA   2
147 #define TX_PAUSE  3
148 #define TX_TAIL   4
149 #define RTS_OFF   5
150 #define WAIT      6
151 #define DCD_ON    7
152 #define RX_ON     8
153 #define DCD_OFF   9
154
155
156 /* Ioctls */
157
158 #define SIOCGSCCPARAM SIOCDEVPRIVATE
159 #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
160
161
162 /* Data types */
163
164 struct scc_param {
165         int pclk_hz;            /* frequency of BRG input (don't change) */
166         int brg_tc;             /* BRG terminal count; BRG disabled if < 0 */
167         int nrzi;               /* 0 (nrz), 1 (nrzi) */
168         int clocks;             /* see dmascc_cfg documentation */
169         int txdelay;            /* [1/TMR_0_HZ] */
170         int txtimeout;          /* [1/HZ] */
171         int txtail;             /* [1/TMR_0_HZ] */
172         int waittime;           /* [1/TMR_0_HZ] */
173         int slottime;           /* [1/TMR_0_HZ] */
174         int persist;            /* 1 ... 256 */
175         int dma;                /* -1 (disable), 0, 1, 3 */
176         int txpause;            /* [1/TMR_0_HZ] */
177         int rtsoff;             /* [1/TMR_0_HZ] */
178         int dcdon;              /* [1/TMR_0_HZ] */
179         int dcdoff;             /* [1/TMR_0_HZ] */
180 };
181
182 struct scc_hardware {
183         char *name;
184         int io_region;
185         int io_delta;
186         int io_size;
187         int num_devs;
188         int scc_offset;
189         int tmr_offset;
190         int tmr_hz;
191         int pclk_hz;
192 };
193
194 struct scc_priv {
195         int type;
196         int chip;
197         struct net_device *dev;
198         struct scc_info *info;
199
200         int channel;
201         int card_base, scc_cmd, scc_data;
202         int tmr_cnt, tmr_ctrl, tmr_mode;
203         struct scc_param param;
204         char rx_buf[NUM_RX_BUF][BUF_SIZE];
205         int rx_len[NUM_RX_BUF];
206         int rx_ptr;
207         struct work_struct rx_work;
208         int rx_head, rx_tail, rx_count;
209         int rx_over;
210         char tx_buf[NUM_TX_BUF][BUF_SIZE];
211         int tx_len[NUM_TX_BUF];
212         int tx_ptr;
213         int tx_head, tx_tail, tx_count;
214         int state;
215         unsigned long tx_start;
216         int rr0;
217         spinlock_t *register_lock;      /* Per scc_info */
218         spinlock_t ring_lock;
219 };
220
221 struct scc_info {
222         int irq_used;
223         int twin_serial_cfg;
224         struct net_device *dev[2];
225         struct scc_priv priv[2];
226         struct scc_info *next;
227         spinlock_t register_lock;       /* Per device register lock */
228 };
229
230
231 /* Function declarations */
232 static int setup_adapter(int card_base, int type, int n) __init;
233
234 static void write_scc(struct scc_priv *priv, int reg, int val);
235 static void write_scc_data(struct scc_priv *priv, int val, int fast);
236 static int read_scc(struct scc_priv *priv, int reg);
237 static int read_scc_data(struct scc_priv *priv);
238
239 static int scc_open(struct net_device *dev);
240 static int scc_close(struct net_device *dev);
241 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
242 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
243 static int scc_set_mac_address(struct net_device *dev, void *sa);
244
245 static inline void tx_on(struct scc_priv *priv);
246 static inline void rx_on(struct scc_priv *priv);
247 static inline void rx_off(struct scc_priv *priv);
248 static void start_timer(struct scc_priv *priv, int t, int r15);
249 static inline unsigned char random(void);
250
251 static inline void z8530_isr(struct scc_info *info);
252 static irqreturn_t scc_isr(int irq, void *dev_id);
253 static void rx_isr(struct scc_priv *priv);
254 static void special_condition(struct scc_priv *priv, int rc);
255 static void rx_bh(struct work_struct *);
256 static void tx_isr(struct scc_priv *priv);
257 static void es_isr(struct scc_priv *priv);
258 static void tm_isr(struct scc_priv *priv);
259
260
261 /* Initialization variables */
262
263 static int io[MAX_NUM_DEVS] __initdata = { 0, };
264
265 /* Beware! hw[] is also used in dmascc_exit(). */
266 static struct scc_hardware hw[NUM_TYPES] = HARDWARE;
267
268
269 /* Global variables */
270
271 static struct scc_info *first;
272 static unsigned long rand;
273
274
275 MODULE_AUTHOR("Klaus Kudielka");
276 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
277 module_param_array(io, int, NULL, 0);
278 MODULE_LICENSE("GPL");
279
280 static void __exit dmascc_exit(void)
281 {
282         int i;
283         struct scc_info *info;
284
285         while (first) {
286                 info = first;
287
288                 /* Unregister devices */
289                 for (i = 0; i < 2; i++)
290                         unregister_netdev(info->dev[i]);
291
292                 /* Reset board */
293                 if (info->priv[0].type == TYPE_TWIN)
294                         outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
295                 write_scc(&info->priv[0], R9, FHWRES);
296                 release_region(info->dev[0]->base_addr,
297                                hw[info->priv[0].type].io_size);
298
299                 for (i = 0; i < 2; i++)
300                         free_netdev(info->dev[i]);
301
302                 /* Free memory */
303                 first = info->next;
304                 kfree(info);
305         }
306 }
307
308 static int __init dmascc_init(void)
309 {
310         int h, i, j, n;
311         int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
312             t1[MAX_NUM_DEVS];
313         unsigned t_val;
314         unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
315             counting[MAX_NUM_DEVS];
316
317         /* Initialize random number generator */
318         rand = jiffies;
319         /* Cards found = 0 */
320         n = 0;
321         /* Warning message */
322         if (!io[0])
323                 printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
324
325         /* Run autodetection for each card type */
326         for (h = 0; h < NUM_TYPES; h++) {
327
328                 if (io[0]) {
329                         /* User-specified I/O address regions */
330                         for (i = 0; i < hw[h].num_devs; i++)
331                                 base[i] = 0;
332                         for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
333                                 j = (io[i] -
334                                      hw[h].io_region) / hw[h].io_delta;
335                                 if (j >= 0 && j < hw[h].num_devs &&
336                                     hw[h].io_region +
337                                     j * hw[h].io_delta == io[i]) {
338                                         base[j] = io[i];
339                                 }
340                         }
341                 } else {
342                         /* Default I/O address regions */
343                         for (i = 0; i < hw[h].num_devs; i++) {
344                                 base[i] =
345                                     hw[h].io_region + i * hw[h].io_delta;
346                         }
347                 }
348
349                 /* Check valid I/O address regions */
350                 for (i = 0; i < hw[h].num_devs; i++)
351                         if (base[i]) {
352                                 if (!request_region
353                                     (base[i], hw[h].io_size, "dmascc"))
354                                         base[i] = 0;
355                                 else {
356                                         tcmd[i] =
357                                             base[i] + hw[h].tmr_offset +
358                                             TMR_CTRL;
359                                         t0[i] =
360                                             base[i] + hw[h].tmr_offset +
361                                             TMR_CNT0;
362                                         t1[i] =
363                                             base[i] + hw[h].tmr_offset +
364                                             TMR_CNT1;
365                                 }
366                         }
367
368                 /* Start timers */
369                 for (i = 0; i < hw[h].num_devs; i++)
370                         if (base[i]) {
371                                 /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
372                                 outb(0x36, tcmd[i]);
373                                 outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF,
374                                      t0[i]);
375                                 outb((hw[h].tmr_hz / TMR_0_HZ) >> 8,
376                                      t0[i]);
377                                 /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
378                                 outb(0x70, tcmd[i]);
379                                 outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]);
380                                 outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]);
381                                 start[i] = jiffies;
382                                 delay[i] = 0;
383                                 counting[i] = 1;
384                                 /* Timer 2: LSB+MSB, Mode 0 */
385                                 outb(0xb0, tcmd[i]);
386                         }
387                 time = jiffies;
388                 /* Wait until counter registers are loaded */
389                 udelay(2000000 / TMR_0_HZ);
390
391                 /* Timing loop */
392                 while (jiffies - time < 13) {
393                         for (i = 0; i < hw[h].num_devs; i++)
394                                 if (base[i] && counting[i]) {
395                                         /* Read back Timer 1: latch; read LSB; read MSB */
396                                         outb(0x40, tcmd[i]);
397                                         t_val =
398                                             inb(t1[i]) + (inb(t1[i]) << 8);
399                                         /* Also check whether counter did wrap */
400                                         if (t_val == 0 ||
401                                             t_val > TMR_0_HZ / HZ * 10)
402                                                 counting[i] = 0;
403                                         delay[i] = jiffies - start[i];
404                                 }
405                 }
406
407                 /* Evaluate measurements */
408                 for (i = 0; i < hw[h].num_devs; i++)
409                         if (base[i]) {
410                                 if ((delay[i] >= 9 && delay[i] <= 11) &&
411                                     /* Ok, we have found an adapter */
412                                     (setup_adapter(base[i], h, n) == 0))
413                                         n++;
414                                 else
415                                         release_region(base[i],
416                                                        hw[h].io_size);
417                         }
418
419         }                       /* NUM_TYPES */
420
421         /* If any adapter was successfully initialized, return ok */
422         if (n)
423                 return 0;
424
425         /* If no adapter found, return error */
426         printk(KERN_INFO "dmascc: no adapters found\n");
427         return -EIO;
428 }
429
430 module_init(dmascc_init);
431 module_exit(dmascc_exit);
432
433 static void __init dev_setup(struct net_device *dev)
434 {
435         dev->type = ARPHRD_AX25;
436         dev->hard_header_len = AX25_MAX_HEADER_LEN;
437         dev->mtu = 1500;
438         dev->addr_len = AX25_ADDR_LEN;
439         dev->tx_queue_len = 64;
440         memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
441         memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
442 }
443
444 static const struct net_device_ops scc_netdev_ops = {
445         .ndo_open = scc_open,
446         .ndo_stop = scc_close,
447         .ndo_start_xmit = scc_send_packet,
448         .ndo_do_ioctl = scc_ioctl,
449         .ndo_set_mac_address = scc_set_mac_address,
450 };
451
452 static int __init setup_adapter(int card_base, int type, int n)
453 {
454         int i, irq, chip;
455         struct scc_info *info;
456         struct net_device *dev;
457         struct scc_priv *priv;
458         unsigned long time;
459         unsigned int irqs;
460         int tmr_base = card_base + hw[type].tmr_offset;
461         int scc_base = card_base + hw[type].scc_offset;
462         char *chipnames[] = CHIPNAMES;
463
464         /* Initialize what is necessary for write_scc and write_scc_data */
465         info = kzalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
466         if (!info) {
467                 printk(KERN_ERR "dmascc: "
468                        "could not allocate memory for %s at %#3x\n",
469                        hw[type].name, card_base);
470                 goto out;
471         }
472
473
474         info->dev[0] = alloc_netdev(0, "", dev_setup);
475         if (!info->dev[0]) {
476                 printk(KERN_ERR "dmascc: "
477                        "could not allocate memory for %s at %#3x\n",
478                        hw[type].name, card_base);
479                 goto out1;
480         }
481
482         info->dev[1] = alloc_netdev(0, "", dev_setup);
483         if (!info->dev[1]) {
484                 printk(KERN_ERR "dmascc: "
485                        "could not allocate memory for %s at %#3x\n",
486                        hw[type].name, card_base);
487                 goto out2;
488         }
489         spin_lock_init(&info->register_lock);
490
491         priv = &info->priv[0];
492         priv->type = type;
493         priv->card_base = card_base;
494         priv->scc_cmd = scc_base + SCCA_CMD;
495         priv->scc_data = scc_base + SCCA_DATA;
496         priv->register_lock = &info->register_lock;
497
498         /* Reset SCC */
499         write_scc(priv, R9, FHWRES | MIE | NV);
500
501         /* Determine type of chip by enabling SDLC/HDLC enhancements */
502         write_scc(priv, R15, SHDLCE);
503         if (!read_scc(priv, R15)) {
504                 /* WR7' not present. This is an ordinary Z8530 SCC. */
505                 chip = Z8530;
506         } else {
507                 /* Put one character in TX FIFO */
508                 write_scc_data(priv, 0, 0);
509                 if (read_scc(priv, R0) & Tx_BUF_EMP) {
510                         /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
511                         chip = Z85230;
512                 } else {
513                         /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
514                         chip = Z85C30;
515                 }
516         }
517         write_scc(priv, R15, 0);
518
519         /* Start IRQ auto-detection */
520         irqs = probe_irq_on();
521
522         /* Enable interrupts */
523         if (type == TYPE_TWIN) {
524                 outb(0, card_base + TWIN_DMA_CFG);
525                 inb(card_base + TWIN_CLR_TMR1);
526                 inb(card_base + TWIN_CLR_TMR2);
527                 info->twin_serial_cfg = TWIN_EI;
528                 outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
529         } else {
530                 write_scc(priv, R15, CTSIE);
531                 write_scc(priv, R0, RES_EXT_INT);
532                 write_scc(priv, R1, EXT_INT_ENAB);
533         }
534
535         /* Start timer */
536         outb(1, tmr_base + TMR_CNT1);
537         outb(0, tmr_base + TMR_CNT1);
538
539         /* Wait and detect IRQ */
540         time = jiffies;
541         while (jiffies - time < 2 + HZ / TMR_0_HZ);
542         irq = probe_irq_off(irqs);
543
544         /* Clear pending interrupt, disable interrupts */
545         if (type == TYPE_TWIN) {
546                 inb(card_base + TWIN_CLR_TMR1);
547         } else {
548                 write_scc(priv, R1, 0);
549                 write_scc(priv, R15, 0);
550                 write_scc(priv, R0, RES_EXT_INT);
551         }
552
553         if (irq <= 0) {
554                 printk(KERN_ERR
555                        "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
556                        hw[type].name, card_base, irq);
557                 goto out3;
558         }
559
560         /* Set up data structures */
561         for (i = 0; i < 2; i++) {
562                 dev = info->dev[i];
563                 priv = &info->priv[i];
564                 priv->type = type;
565                 priv->chip = chip;
566                 priv->dev = dev;
567                 priv->info = info;
568                 priv->channel = i;
569                 spin_lock_init(&priv->ring_lock);
570                 priv->register_lock = &info->register_lock;
571                 priv->card_base = card_base;
572                 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
573                 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
574                 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
575                 priv->tmr_ctrl = tmr_base + TMR_CTRL;
576                 priv->tmr_mode = i ? 0xb0 : 0x70;
577                 priv->param.pclk_hz = hw[type].pclk_hz;
578                 priv->param.brg_tc = -1;
579                 priv->param.clocks = TCTRxCP | RCRTxCP;
580                 priv->param.persist = 256;
581                 priv->param.dma = -1;
582                 INIT_WORK(&priv->rx_work, rx_bh);
583                 dev->ml_priv = priv;
584                 sprintf(dev->name, "dmascc%i", 2 * n + i);
585                 dev->base_addr = card_base;
586                 dev->irq = irq;
587                 dev->netdev_ops = &scc_netdev_ops;
588                 dev->header_ops = &ax25_header_ops;
589         }
590         if (register_netdev(info->dev[0])) {
591                 printk(KERN_ERR "dmascc: could not register %s\n",
592                        info->dev[0]->name);
593                 goto out3;
594         }
595         if (register_netdev(info->dev[1])) {
596                 printk(KERN_ERR "dmascc: could not register %s\n",
597                        info->dev[1]->name);
598                 goto out4;
599         }
600
601
602         info->next = first;
603         first = info;
604         printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n",
605                hw[type].name, chipnames[chip], card_base, irq);
606         return 0;
607
608       out4:
609         unregister_netdev(info->dev[0]);
610       out3:
611         if (info->priv[0].type == TYPE_TWIN)
612                 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
613         write_scc(&info->priv[0], R9, FHWRES);
614         free_netdev(info->dev[1]);
615       out2:
616         free_netdev(info->dev[0]);
617       out1:
618         kfree(info);
619       out:
620         return -1;
621 }
622
623
624 /* Driver functions */
625
626 static void write_scc(struct scc_priv *priv, int reg, int val)
627 {
628         unsigned long flags;
629         switch (priv->type) {
630         case TYPE_S5:
631                 if (reg)
632                         outb(reg, priv->scc_cmd);
633                 outb(val, priv->scc_cmd);
634                 return;
635         case TYPE_TWIN:
636                 if (reg)
637                         outb_p(reg, priv->scc_cmd);
638                 outb_p(val, priv->scc_cmd);
639                 return;
640         default:
641                 spin_lock_irqsave(priv->register_lock, flags);
642                 outb_p(0, priv->card_base + PI_DREQ_MASK);
643                 if (reg)
644                         outb_p(reg, priv->scc_cmd);
645                 outb_p(val, priv->scc_cmd);
646                 outb(1, priv->card_base + PI_DREQ_MASK);
647                 spin_unlock_irqrestore(priv->register_lock, flags);
648                 return;
649         }
650 }
651
652
653 static void write_scc_data(struct scc_priv *priv, int val, int fast)
654 {
655         unsigned long flags;
656         switch (priv->type) {
657         case TYPE_S5:
658                 outb(val, priv->scc_data);
659                 return;
660         case TYPE_TWIN:
661                 outb_p(val, priv->scc_data);
662                 return;
663         default:
664                 if (fast)
665                         outb_p(val, priv->scc_data);
666                 else {
667                         spin_lock_irqsave(priv->register_lock, flags);
668                         outb_p(0, priv->card_base + PI_DREQ_MASK);
669                         outb_p(val, priv->scc_data);
670                         outb(1, priv->card_base + PI_DREQ_MASK);
671                         spin_unlock_irqrestore(priv->register_lock, flags);
672                 }
673                 return;
674         }
675 }
676
677
678 static int read_scc(struct scc_priv *priv, int reg)
679 {
680         int rc;
681         unsigned long flags;
682         switch (priv->type) {
683         case TYPE_S5:
684                 if (reg)
685                         outb(reg, priv->scc_cmd);
686                 return inb(priv->scc_cmd);
687         case TYPE_TWIN:
688                 if (reg)
689                         outb_p(reg, priv->scc_cmd);
690                 return inb_p(priv->scc_cmd);
691         default:
692                 spin_lock_irqsave(priv->register_lock, flags);
693                 outb_p(0, priv->card_base + PI_DREQ_MASK);
694                 if (reg)
695                         outb_p(reg, priv->scc_cmd);
696                 rc = inb_p(priv->scc_cmd);
697                 outb(1, priv->card_base + PI_DREQ_MASK);
698                 spin_unlock_irqrestore(priv->register_lock, flags);
699                 return rc;
700         }
701 }
702
703
704 static int read_scc_data(struct scc_priv *priv)
705 {
706         int rc;
707         unsigned long flags;
708         switch (priv->type) {
709         case TYPE_S5:
710                 return inb(priv->scc_data);
711         case TYPE_TWIN:
712                 return inb_p(priv->scc_data);
713         default:
714                 spin_lock_irqsave(priv->register_lock, flags);
715                 outb_p(0, priv->card_base + PI_DREQ_MASK);
716                 rc = inb_p(priv->scc_data);
717                 outb(1, priv->card_base + PI_DREQ_MASK);
718                 spin_unlock_irqrestore(priv->register_lock, flags);
719                 return rc;
720         }
721 }
722
723
724 static int scc_open(struct net_device *dev)
725 {
726         struct scc_priv *priv = dev->ml_priv;
727         struct scc_info *info = priv->info;
728         int card_base = priv->card_base;
729
730         /* Request IRQ if not already used by other channel */
731         if (!info->irq_used) {
732                 if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
733                         return -EAGAIN;
734                 }
735         }
736         info->irq_used++;
737
738         /* Request DMA if required */
739         if (priv->param.dma >= 0) {
740                 if (request_dma(priv->param.dma, "dmascc")) {
741                         if (--info->irq_used == 0)
742                                 free_irq(dev->irq, info);
743                         return -EAGAIN;
744                 } else {
745                         unsigned long flags = claim_dma_lock();
746                         clear_dma_ff(priv->param.dma);
747                         release_dma_lock(flags);
748                 }
749         }
750
751         /* Initialize local variables */
752         priv->rx_ptr = 0;
753         priv->rx_over = 0;
754         priv->rx_head = priv->rx_tail = priv->rx_count = 0;
755         priv->state = IDLE;
756         priv->tx_head = priv->tx_tail = priv->tx_count = 0;
757         priv->tx_ptr = 0;
758
759         /* Reset channel */
760         write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
761         /* X1 clock, SDLC mode */
762         write_scc(priv, R4, SDLC | X1CLK);
763         /* DMA */
764         write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
765         /* 8 bit RX char, RX disable */
766         write_scc(priv, R3, Rx8);
767         /* 8 bit TX char, TX disable */
768         write_scc(priv, R5, Tx8);
769         /* SDLC address field */
770         write_scc(priv, R6, 0);
771         /* SDLC flag */
772         write_scc(priv, R7, FLAG);
773         switch (priv->chip) {
774         case Z85C30:
775                 /* Select WR7' */
776                 write_scc(priv, R15, SHDLCE);
777                 /* Auto EOM reset */
778                 write_scc(priv, R7, AUTOEOM);
779                 write_scc(priv, R15, 0);
780                 break;
781         case Z85230:
782                 /* Select WR7' */
783                 write_scc(priv, R15, SHDLCE);
784                 /* The following bits are set (see 2.5.2.1):
785                    - Automatic EOM reset
786                    - Interrupt request if RX FIFO is half full
787                    This bit should be ignored in DMA mode (according to the
788                    documentation), but actually isn't. The receiver doesn't work if
789                    it is set. Thus, we have to clear it in DMA mode.
790                    - Interrupt/DMA request if TX FIFO is completely empty
791                    a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
792                    compatibility).
793                    b) If cleared, DMA requests may follow each other very quickly,
794                    filling up the TX FIFO.
795                    Advantage: TX works even in case of high bus latency.
796                    Disadvantage: Edge-triggered DMA request circuitry may miss
797                    a request. No more data is delivered, resulting
798                    in a TX FIFO underrun.
799                    Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
800                    The PackeTwin doesn't. I don't know about the PI, but let's
801                    assume it behaves like the PI2.
802                  */
803                 if (priv->param.dma >= 0) {
804                         if (priv->type == TYPE_TWIN)
805                                 write_scc(priv, R7, AUTOEOM | TXFIFOE);
806                         else
807                                 write_scc(priv, R7, AUTOEOM);
808                 } else {
809                         write_scc(priv, R7, AUTOEOM | RXFIFOH);
810                 }
811                 write_scc(priv, R15, 0);
812                 break;
813         }
814         /* Preset CRC, NRZ(I) encoding */
815         write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
816
817         /* Configure baud rate generator */
818         if (priv->param.brg_tc >= 0) {
819                 /* Program BR generator */
820                 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
821                 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
822                 /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
823                    PackeTwin, not connected on the PI2); set DPLL source to BRG */
824                 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
825                 /* Enable DPLL */
826                 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
827         } else {
828                 /* Disable BR generator */
829                 write_scc(priv, R14, DTRREQ | BRSRC);
830         }
831
832         /* Configure clocks */
833         if (priv->type == TYPE_TWIN) {
834                 /* Disable external TX clock receiver */
835                 outb((info->twin_serial_cfg &=
836                       ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
837                      card_base + TWIN_SERIAL_CFG);
838         }
839         write_scc(priv, R11, priv->param.clocks);
840         if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
841                 /* Enable external TX clock receiver */
842                 outb((info->twin_serial_cfg |=
843                       (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
844                      card_base + TWIN_SERIAL_CFG);
845         }
846
847         /* Configure PackeTwin */
848         if (priv->type == TYPE_TWIN) {
849                 /* Assert DTR, enable interrupts */
850                 outb((info->twin_serial_cfg |= TWIN_EI |
851                       (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
852                      card_base + TWIN_SERIAL_CFG);
853         }
854
855         /* Read current status */
856         priv->rr0 = read_scc(priv, R0);
857         /* Enable DCD interrupt */
858         write_scc(priv, R15, DCDIE);
859
860         netif_start_queue(dev);
861
862         return 0;
863 }
864
865
866 static int scc_close(struct net_device *dev)
867 {
868         struct scc_priv *priv = dev->ml_priv;
869         struct scc_info *info = priv->info;
870         int card_base = priv->card_base;
871
872         netif_stop_queue(dev);
873
874         if (priv->type == TYPE_TWIN) {
875                 /* Drop DTR */
876                 outb((info->twin_serial_cfg &=
877                       (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
878                      card_base + TWIN_SERIAL_CFG);
879         }
880
881         /* Reset channel, free DMA and IRQ */
882         write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
883         if (priv->param.dma >= 0) {
884                 if (priv->type == TYPE_TWIN)
885                         outb(0, card_base + TWIN_DMA_CFG);
886                 free_dma(priv->param.dma);
887         }
888         if (--info->irq_used == 0)
889                 free_irq(dev->irq, info);
890
891         return 0;
892 }
893
894
895 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
896 {
897         struct scc_priv *priv = dev->ml_priv;
898
899         switch (cmd) {
900         case SIOCGSCCPARAM:
901                 if (copy_to_user
902                     (ifr->ifr_data, &priv->param,
903                      sizeof(struct scc_param)))
904                         return -EFAULT;
905                 return 0;
906         case SIOCSSCCPARAM:
907                 if (!capable(CAP_NET_ADMIN))
908                         return -EPERM;
909                 if (netif_running(dev))
910                         return -EAGAIN;
911                 if (copy_from_user
912                     (&priv->param, ifr->ifr_data,
913                      sizeof(struct scc_param)))
914                         return -EFAULT;
915                 return 0;
916         default:
917                 return -EINVAL;
918         }
919 }
920
921
922 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev)
923 {
924         struct scc_priv *priv = dev->ml_priv;
925         unsigned long flags;
926         int i;
927
928         /* Temporarily stop the scheduler feeding us packets */
929         netif_stop_queue(dev);
930
931         /* Transfer data to DMA buffer */
932         i = priv->tx_head;
933         skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1);
934         priv->tx_len[i] = skb->len - 1;
935
936         /* Clear interrupts while we touch our circular buffers */
937
938         spin_lock_irqsave(&priv->ring_lock, flags);
939         /* Move the ring buffer's head */
940         priv->tx_head = (i + 1) % NUM_TX_BUF;
941         priv->tx_count++;
942
943         /* If we just filled up the last buffer, leave queue stopped.
944            The higher layers must wait until we have a DMA buffer
945            to accept the data. */
946         if (priv->tx_count < NUM_TX_BUF)
947                 netif_wake_queue(dev);
948
949         /* Set new TX state */
950         if (priv->state == IDLE) {
951                 /* Assert RTS, start timer */
952                 priv->state = TX_HEAD;
953                 priv->tx_start = jiffies;
954                 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
955                 write_scc(priv, R15, 0);
956                 start_timer(priv, priv->param.txdelay, 0);
957         }
958
959         /* Turn interrupts back on and free buffer */
960         spin_unlock_irqrestore(&priv->ring_lock, flags);
961         dev_kfree_skb(skb);
962
963         return NETDEV_TX_OK;
964 }
965
966
967 static int scc_set_mac_address(struct net_device *dev, void *sa)
968 {
969         memcpy(dev->dev_addr, ((struct sockaddr *) sa)->sa_data,
970                dev->addr_len);
971         return 0;
972 }
973
974
975 static inline void tx_on(struct scc_priv *priv)
976 {
977         int i, n;
978         unsigned long flags;
979
980         if (priv->param.dma >= 0) {
981                 n = (priv->chip == Z85230) ? 3 : 1;
982                 /* Program DMA controller */
983                 flags = claim_dma_lock();
984                 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
985                 set_dma_addr(priv->param.dma,
986                              (int) priv->tx_buf[priv->tx_tail] + n);
987                 set_dma_count(priv->param.dma,
988                               priv->tx_len[priv->tx_tail] - n);
989                 release_dma_lock(flags);
990                 /* Enable TX underrun interrupt */
991                 write_scc(priv, R15, TxUIE);
992                 /* Configure DREQ */
993                 if (priv->type == TYPE_TWIN)
994                         outb((priv->param.dma ==
995                               1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
996                              priv->card_base + TWIN_DMA_CFG);
997                 else
998                         write_scc(priv, R1,
999                                   EXT_INT_ENAB | WT_FN_RDYFN |
1000                                   WT_RDY_ENAB);
1001                 /* Write first byte(s) */
1002                 spin_lock_irqsave(priv->register_lock, flags);
1003                 for (i = 0; i < n; i++)
1004                         write_scc_data(priv,
1005                                        priv->tx_buf[priv->tx_tail][i], 1);
1006                 enable_dma(priv->param.dma);
1007                 spin_unlock_irqrestore(priv->register_lock, flags);
1008         } else {
1009                 write_scc(priv, R15, TxUIE);
1010                 write_scc(priv, R1,
1011                           EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
1012                 tx_isr(priv);
1013         }
1014         /* Reset EOM latch if we do not have the AUTOEOM feature */
1015         if (priv->chip == Z8530)
1016                 write_scc(priv, R0, RES_EOM_L);
1017 }
1018
1019
1020 static inline void rx_on(struct scc_priv *priv)
1021 {
1022         unsigned long flags;
1023
1024         /* Clear RX FIFO */
1025         while (read_scc(priv, R0) & Rx_CH_AV)
1026                 read_scc_data(priv);
1027         priv->rx_over = 0;
1028         if (priv->param.dma >= 0) {
1029                 /* Program DMA controller */
1030                 flags = claim_dma_lock();
1031                 set_dma_mode(priv->param.dma, DMA_MODE_READ);
1032                 set_dma_addr(priv->param.dma,
1033                              (int) priv->rx_buf[priv->rx_head]);
1034                 set_dma_count(priv->param.dma, BUF_SIZE);
1035                 release_dma_lock(flags);
1036                 enable_dma(priv->param.dma);
1037                 /* Configure PackeTwin DMA */
1038                 if (priv->type == TYPE_TWIN) {
1039                         outb((priv->param.dma ==
1040                               1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1041                              priv->card_base + TWIN_DMA_CFG);
1042                 }
1043                 /* Sp. cond. intr. only, ext int enable, RX DMA enable */
1044                 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1045                           WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1046         } else {
1047                 /* Reset current frame */
1048                 priv->rx_ptr = 0;
1049                 /* Intr. on all Rx characters and Sp. cond., ext int enable */
1050                 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1051                           WT_FN_RDYFN);
1052         }
1053         write_scc(priv, R0, ERR_RES);
1054         write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1055 }
1056
1057
1058 static inline void rx_off(struct scc_priv *priv)
1059 {
1060         /* Disable receiver */
1061         write_scc(priv, R3, Rx8);
1062         /* Disable DREQ / RX interrupt */
1063         if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1064                 outb(0, priv->card_base + TWIN_DMA_CFG);
1065         else
1066                 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1067         /* Disable DMA */
1068         if (priv->param.dma >= 0)
1069                 disable_dma(priv->param.dma);
1070 }
1071
1072
1073 static void start_timer(struct scc_priv *priv, int t, int r15)
1074 {
1075         outb(priv->tmr_mode, priv->tmr_ctrl);
1076         if (t == 0) {
1077                 tm_isr(priv);
1078         } else if (t > 0) {
1079                 outb(t & 0xFF, priv->tmr_cnt);
1080                 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1081                 if (priv->type != TYPE_TWIN) {
1082                         write_scc(priv, R15, r15 | CTSIE);
1083                         priv->rr0 |= CTS;
1084                 }
1085         }
1086 }
1087
1088
1089 static inline unsigned char random(void)
1090 {
1091         /* See "Numerical Recipes in C", second edition, p. 284 */
1092         rand = rand * 1664525L + 1013904223L;
1093         return (unsigned char) (rand >> 24);
1094 }
1095
1096 static inline void z8530_isr(struct scc_info *info)
1097 {
1098         int is, i = 100;
1099
1100         while ((is = read_scc(&info->priv[0], R3)) && i--) {
1101                 if (is & CHARxIP) {
1102                         rx_isr(&info->priv[0]);
1103                 } else if (is & CHATxIP) {
1104                         tx_isr(&info->priv[0]);
1105                 } else if (is & CHAEXT) {
1106                         es_isr(&info->priv[0]);
1107                 } else if (is & CHBRxIP) {
1108                         rx_isr(&info->priv[1]);
1109                 } else if (is & CHBTxIP) {
1110                         tx_isr(&info->priv[1]);
1111                 } else {
1112                         es_isr(&info->priv[1]);
1113                 }
1114                 write_scc(&info->priv[0], R0, RES_H_IUS);
1115                 i++;
1116         }
1117         if (i < 0) {
1118                 printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n",
1119                        is);
1120         }
1121         /* Ok, no interrupts pending from this 8530. The INT line should
1122            be inactive now. */
1123 }
1124
1125
1126 static irqreturn_t scc_isr(int irq, void *dev_id)
1127 {
1128         struct scc_info *info = dev_id;
1129
1130         spin_lock(info->priv[0].register_lock);
1131         /* At this point interrupts are enabled, and the interrupt under service
1132            is already acknowledged, but masked off.
1133
1134            Interrupt processing: We loop until we know that the IRQ line is
1135            low. If another positive edge occurs afterwards during the ISR,
1136            another interrupt will be triggered by the interrupt controller
1137            as soon as the IRQ level is enabled again (see asm/irq.h).
1138
1139            Bottom-half handlers will be processed after scc_isr(). This is
1140            important, since we only have small ringbuffers and want new data
1141            to be fetched/delivered immediately. */
1142
1143         if (info->priv[0].type == TYPE_TWIN) {
1144                 int is, card_base = info->priv[0].card_base;
1145                 while ((is = ~inb(card_base + TWIN_INT_REG)) &
1146                        TWIN_INT_MSK) {
1147                         if (is & TWIN_SCC_MSK) {
1148                                 z8530_isr(info);
1149                         } else if (is & TWIN_TMR1_MSK) {
1150                                 inb(card_base + TWIN_CLR_TMR1);
1151                                 tm_isr(&info->priv[0]);
1152                         } else {
1153                                 inb(card_base + TWIN_CLR_TMR2);
1154                                 tm_isr(&info->priv[1]);
1155                         }
1156                 }
1157         } else
1158                 z8530_isr(info);
1159         spin_unlock(info->priv[0].register_lock);
1160         return IRQ_HANDLED;
1161 }
1162
1163
1164 static void rx_isr(struct scc_priv *priv)
1165 {
1166         if (priv->param.dma >= 0) {
1167                 /* Check special condition and perform error reset. See 2.4.7.5. */
1168                 special_condition(priv, read_scc(priv, R1));
1169                 write_scc(priv, R0, ERR_RES);
1170         } else {
1171                 /* Check special condition for each character. Error reset not necessary.
1172                    Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1173                 int rc;
1174                 while (read_scc(priv, R0) & Rx_CH_AV) {
1175                         rc = read_scc(priv, R1);
1176                         if (priv->rx_ptr < BUF_SIZE)
1177                                 priv->rx_buf[priv->rx_head][priv->
1178                                                             rx_ptr++] =
1179                                     read_scc_data(priv);
1180                         else {
1181                                 priv->rx_over = 2;
1182                                 read_scc_data(priv);
1183                         }
1184                         special_condition(priv, rc);
1185                 }
1186         }
1187 }
1188
1189
1190 static void special_condition(struct scc_priv *priv, int rc)
1191 {
1192         int cb;
1193         unsigned long flags;
1194
1195         /* See Figure 2-15. Only overrun and EOF need to be checked. */
1196
1197         if (rc & Rx_OVR) {
1198                 /* Receiver overrun */
1199                 priv->rx_over = 1;
1200                 if (priv->param.dma < 0)
1201                         write_scc(priv, R0, ERR_RES);
1202         } else if (rc & END_FR) {
1203                 /* End of frame. Get byte count */
1204                 if (priv->param.dma >= 0) {
1205                         flags = claim_dma_lock();
1206                         cb = BUF_SIZE - get_dma_residue(priv->param.dma) -
1207                             2;
1208                         release_dma_lock(flags);
1209                 } else {
1210                         cb = priv->rx_ptr - 2;
1211                 }
1212                 if (priv->rx_over) {
1213                         /* We had an overrun */
1214                         priv->dev->stats.rx_errors++;
1215                         if (priv->rx_over == 2)
1216                                 priv->dev->stats.rx_length_errors++;
1217                         else
1218                                 priv->dev->stats.rx_fifo_errors++;
1219                         priv->rx_over = 0;
1220                 } else if (rc & CRC_ERR) {
1221                         /* Count invalid CRC only if packet length >= minimum */
1222                         if (cb >= 15) {
1223                                 priv->dev->stats.rx_errors++;
1224                                 priv->dev->stats.rx_crc_errors++;
1225                         }
1226                 } else {
1227                         if (cb >= 15) {
1228                                 if (priv->rx_count < NUM_RX_BUF - 1) {
1229                                         /* Put good frame in FIFO */
1230                                         priv->rx_len[priv->rx_head] = cb;
1231                                         priv->rx_head =
1232                                             (priv->rx_head +
1233                                              1) % NUM_RX_BUF;
1234                                         priv->rx_count++;
1235                                         schedule_work(&priv->rx_work);
1236                                 } else {
1237                                         priv->dev->stats.rx_errors++;
1238                                         priv->dev->stats.rx_over_errors++;
1239                                 }
1240                         }
1241                 }
1242                 /* Get ready for new frame */
1243                 if (priv->param.dma >= 0) {
1244                         flags = claim_dma_lock();
1245                         set_dma_addr(priv->param.dma,
1246                                      (int) priv->rx_buf[priv->rx_head]);
1247                         set_dma_count(priv->param.dma, BUF_SIZE);
1248                         release_dma_lock(flags);
1249                 } else {
1250                         priv->rx_ptr = 0;
1251                 }
1252         }
1253 }
1254
1255
1256 static void rx_bh(struct work_struct *ugli_api)
1257 {
1258         struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
1259         int i = priv->rx_tail;
1260         int cb;
1261         unsigned long flags;
1262         struct sk_buff *skb;
1263         unsigned char *data;
1264
1265         spin_lock_irqsave(&priv->ring_lock, flags);
1266         while (priv->rx_count) {
1267                 spin_unlock_irqrestore(&priv->ring_lock, flags);
1268                 cb = priv->rx_len[i];
1269                 /* Allocate buffer */
1270                 skb = dev_alloc_skb(cb + 1);
1271                 if (skb == NULL) {
1272                         /* Drop packet */
1273                         priv->dev->stats.rx_dropped++;
1274                 } else {
1275                         /* Fill buffer */
1276                         data = skb_put(skb, cb + 1);
1277                         data[0] = 0;
1278                         memcpy(&data[1], priv->rx_buf[i], cb);
1279                         skb->protocol = ax25_type_trans(skb, priv->dev);
1280                         netif_rx(skb);
1281                         priv->dev->stats.rx_packets++;
1282                         priv->dev->stats.rx_bytes += cb;
1283                 }
1284                 spin_lock_irqsave(&priv->ring_lock, flags);
1285                 /* Move tail */
1286                 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1287                 priv->rx_count--;
1288         }
1289         spin_unlock_irqrestore(&priv->ring_lock, flags);
1290 }
1291
1292
1293 static void tx_isr(struct scc_priv *priv)
1294 {
1295         int i = priv->tx_tail, p = priv->tx_ptr;
1296
1297         /* Suspend TX interrupts if we don't want to send anything.
1298            See Figure 2-22. */
1299         if (p == priv->tx_len[i]) {
1300                 write_scc(priv, R0, RES_Tx_P);
1301                 return;
1302         }
1303
1304         /* Write characters */
1305         while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1306                 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1307         }
1308
1309         /* Reset EOM latch of Z8530 */
1310         if (!priv->tx_ptr && p && priv->chip == Z8530)
1311                 write_scc(priv, R0, RES_EOM_L);
1312
1313         priv->tx_ptr = p;
1314 }
1315
1316
1317 static void es_isr(struct scc_priv *priv)
1318 {
1319         int i, rr0, drr0, res;
1320         unsigned long flags;
1321
1322         /* Read status, reset interrupt bit (open latches) */
1323         rr0 = read_scc(priv, R0);
1324         write_scc(priv, R0, RES_EXT_INT);
1325         drr0 = priv->rr0 ^ rr0;
1326         priv->rr0 = rr0;
1327
1328         /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1329            it might have already been cleared again by AUTOEOM. */
1330         if (priv->state == TX_DATA) {
1331                 /* Get remaining bytes */
1332                 i = priv->tx_tail;
1333                 if (priv->param.dma >= 0) {
1334                         disable_dma(priv->param.dma);
1335                         flags = claim_dma_lock();
1336                         res = get_dma_residue(priv->param.dma);
1337                         release_dma_lock(flags);
1338                 } else {
1339                         res = priv->tx_len[i] - priv->tx_ptr;
1340                         priv->tx_ptr = 0;
1341                 }
1342                 /* Disable DREQ / TX interrupt */
1343                 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1344                         outb(0, priv->card_base + TWIN_DMA_CFG);
1345                 else
1346                         write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1347                 if (res) {
1348                         /* Update packet statistics */
1349                         priv->dev->stats.tx_errors++;
1350                         priv->dev->stats.tx_fifo_errors++;
1351                         /* Other underrun interrupts may already be waiting */
1352                         write_scc(priv, R0, RES_EXT_INT);
1353                         write_scc(priv, R0, RES_EXT_INT);
1354                 } else {
1355                         /* Update packet statistics */
1356                         priv->dev->stats.tx_packets++;
1357                         priv->dev->stats.tx_bytes += priv->tx_len[i];
1358                         /* Remove frame from FIFO */
1359                         priv->tx_tail = (i + 1) % NUM_TX_BUF;
1360                         priv->tx_count--;
1361                         /* Inform upper layers */
1362                         netif_wake_queue(priv->dev);
1363                 }
1364                 /* Switch state */
1365                 write_scc(priv, R15, 0);
1366                 if (priv->tx_count &&
1367                     (jiffies - priv->tx_start) < priv->param.txtimeout) {
1368                         priv->state = TX_PAUSE;
1369                         start_timer(priv, priv->param.txpause, 0);
1370                 } else {
1371                         priv->state = TX_TAIL;
1372                         start_timer(priv, priv->param.txtail, 0);
1373                 }
1374         }
1375
1376         /* DCD transition */
1377         if (drr0 & DCD) {
1378                 if (rr0 & DCD) {
1379                         switch (priv->state) {
1380                         case IDLE:
1381                         case WAIT:
1382                                 priv->state = DCD_ON;
1383                                 write_scc(priv, R15, 0);
1384                                 start_timer(priv, priv->param.dcdon, 0);
1385                         }
1386                 } else {
1387                         switch (priv->state) {
1388                         case RX_ON:
1389                                 rx_off(priv);
1390                                 priv->state = DCD_OFF;
1391                                 write_scc(priv, R15, 0);
1392                                 start_timer(priv, priv->param.dcdoff, 0);
1393                         }
1394                 }
1395         }
1396
1397         /* CTS transition */
1398         if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1399                 tm_isr(priv);
1400
1401 }
1402
1403
1404 static void tm_isr(struct scc_priv *priv)
1405 {
1406         switch (priv->state) {
1407         case TX_HEAD:
1408         case TX_PAUSE:
1409                 tx_on(priv);
1410                 priv->state = TX_DATA;
1411                 break;
1412         case TX_TAIL:
1413                 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1414                 priv->state = RTS_OFF;
1415                 if (priv->type != TYPE_TWIN)
1416                         write_scc(priv, R15, 0);
1417                 start_timer(priv, priv->param.rtsoff, 0);
1418                 break;
1419         case RTS_OFF:
1420                 write_scc(priv, R15, DCDIE);
1421                 priv->rr0 = read_scc(priv, R0);
1422                 if (priv->rr0 & DCD) {
1423                         priv->dev->stats.collisions++;
1424                         rx_on(priv);
1425                         priv->state = RX_ON;
1426                 } else {
1427                         priv->state = WAIT;
1428                         start_timer(priv, priv->param.waittime, DCDIE);
1429                 }
1430                 break;
1431         case WAIT:
1432                 if (priv->tx_count) {
1433                         priv->state = TX_HEAD;
1434                         priv->tx_start = jiffies;
1435                         write_scc(priv, R5,
1436                                   TxCRC_ENAB | RTS | TxENAB | Tx8);
1437                         write_scc(priv, R15, 0);
1438                         start_timer(priv, priv->param.txdelay, 0);
1439                 } else {
1440                         priv->state = IDLE;
1441                         if (priv->type != TYPE_TWIN)
1442                                 write_scc(priv, R15, DCDIE);
1443                 }
1444                 break;
1445         case DCD_ON:
1446         case DCD_OFF:
1447                 write_scc(priv, R15, DCDIE);
1448                 priv->rr0 = read_scc(priv, R0);
1449                 if (priv->rr0 & DCD) {
1450                         rx_on(priv);
1451                         priv->state = RX_ON;
1452                 } else {
1453                         priv->state = WAIT;
1454                         start_timer(priv,
1455                                     random() / priv->param.persist *
1456                                     priv->param.slottime, DCDIE);
1457                 }
1458                 break;
1459         }
1460 }