gianfar: Fix potential soft reset race
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "gianfar_mii.h"
97
98 #define TX_TIMEOUT      (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112                 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122                 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
135                               int amount_pull);
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137                                 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143
144 extern const struct ethtool_ops gfar_ethtool_ops;
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private *priv)
152 {
153         return priv->vlgrp || priv->rx_csum_enable;
154 }
155
156 static int gfar_of_init(struct net_device *dev)
157 {
158         struct device_node *phy, *mdio;
159         const unsigned int *id;
160         const char *model;
161         const char *ctype;
162         const void *mac_addr;
163         const phandle *ph;
164         u64 addr, size;
165         int err = 0;
166         struct gfar_private *priv = netdev_priv(dev);
167         struct device_node *np = priv->node;
168         char bus_name[MII_BUS_ID_SIZE];
169
170         if (!np || !of_device_is_available(np))
171                 return -ENODEV;
172
173         /* get a pointer to the register memory */
174         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
175         priv->regs = ioremap(addr, size);
176
177         if (priv->regs == NULL)
178                 return -ENOMEM;
179
180         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
181
182         model = of_get_property(np, "model", NULL);
183
184         /* If we aren't the FEC we have multiple interrupts */
185         if (model && strcasecmp(model, "FEC")) {
186                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
187
188                 priv->interruptError = irq_of_parse_and_map(np, 2);
189
190                 if (priv->interruptTransmit < 0 ||
191                                 priv->interruptReceive < 0 ||
192                                 priv->interruptError < 0) {
193                         err = -EINVAL;
194                         goto err_out;
195                 }
196         }
197
198         mac_addr = of_get_mac_address(np);
199         if (mac_addr)
200                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
201
202         if (model && !strcasecmp(model, "TSEC"))
203                 priv->device_flags =
204                         FSL_GIANFAR_DEV_HAS_GIGABIT |
205                         FSL_GIANFAR_DEV_HAS_COALESCE |
206                         FSL_GIANFAR_DEV_HAS_RMON |
207                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
208         if (model && !strcasecmp(model, "eTSEC"))
209                 priv->device_flags =
210                         FSL_GIANFAR_DEV_HAS_GIGABIT |
211                         FSL_GIANFAR_DEV_HAS_COALESCE |
212                         FSL_GIANFAR_DEV_HAS_RMON |
213                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
214                         FSL_GIANFAR_DEV_HAS_PADDING |
215                         FSL_GIANFAR_DEV_HAS_CSUM |
216                         FSL_GIANFAR_DEV_HAS_VLAN |
217                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
218                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
219
220         ctype = of_get_property(np, "phy-connection-type", NULL);
221
222         /* We only care about rgmii-id.  The rest are autodetected */
223         if (ctype && !strcmp(ctype, "rgmii-id"))
224                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
225         else
226                 priv->interface = PHY_INTERFACE_MODE_MII;
227
228         if (of_get_property(np, "fsl,magic-packet", NULL))
229                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
230
231         ph = of_get_property(np, "phy-handle", NULL);
232         if (ph == NULL) {
233                 u32 *fixed_link;
234
235                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
236                 if (!fixed_link) {
237                         err = -ENODEV;
238                         goto err_out;
239                 }
240
241                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
242                                 PHY_ID_FMT, "0", fixed_link[0]);
243         } else {
244                 phy = of_find_node_by_phandle(*ph);
245
246                 if (phy == NULL) {
247                         err = -ENODEV;
248                         goto err_out;
249                 }
250
251                 mdio = of_get_parent(phy);
252
253                 id = of_get_property(phy, "reg", NULL);
254
255                 of_node_put(phy);
256                 of_node_put(mdio);
257
258                 gfar_mdio_bus_name(bus_name, mdio);
259                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
260                                 bus_name, *id);
261         }
262
263         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
264         ph = of_get_property(np, "tbi-handle", NULL);
265         if (ph) {
266                 struct device_node *tbi = of_find_node_by_phandle(*ph);
267                 struct of_device *ofdev;
268                 struct mii_bus *bus;
269
270                 if (!tbi)
271                         return 0;
272
273                 mdio = of_get_parent(tbi);
274                 if (!mdio)
275                         return 0;
276
277                 ofdev = of_find_device_by_node(mdio);
278
279                 of_node_put(mdio);
280
281                 id = of_get_property(tbi, "reg", NULL);
282                 if (!id)
283                         return 0;
284
285                 of_node_put(tbi);
286
287                 bus = dev_get_drvdata(&ofdev->dev);
288
289                 priv->tbiphy = bus->phy_map[*id];
290         }
291
292         return 0;
293
294 err_out:
295         iounmap(priv->regs);
296         return err;
297 }
298
299 /* Ioctl MII Interface */
300 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
301 {
302         struct gfar_private *priv = netdev_priv(dev);
303
304         if (!netif_running(dev))
305                 return -EINVAL;
306
307         if (!priv->phydev)
308                 return -ENODEV;
309
310         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
311 }
312
313 /* Set up the ethernet device structure, private data,
314  * and anything else we need before we start */
315 static int gfar_probe(struct of_device *ofdev,
316                 const struct of_device_id *match)
317 {
318         u32 tempval;
319         struct net_device *dev = NULL;
320         struct gfar_private *priv = NULL;
321         DECLARE_MAC_BUF(mac);
322         int err = 0;
323         int len_devname;
324
325         /* Create an ethernet device instance */
326         dev = alloc_etherdev(sizeof (*priv));
327
328         if (NULL == dev)
329                 return -ENOMEM;
330
331         priv = netdev_priv(dev);
332         priv->dev = dev;
333         priv->node = ofdev->node;
334
335         err = gfar_of_init(dev);
336
337         if (err)
338                 goto regs_fail;
339
340         spin_lock_init(&priv->txlock);
341         spin_lock_init(&priv->rxlock);
342         spin_lock_init(&priv->bflock);
343         INIT_WORK(&priv->reset_task, gfar_reset_task);
344
345         dev_set_drvdata(&ofdev->dev, priv);
346
347         /* Stop the DMA engine now, in case it was running before */
348         /* (The firmware could have used it, and left it running). */
349         gfar_halt(dev);
350
351         /* Reset MAC layer */
352         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
353
354         /* We need to delay at least 3 TX clocks */
355         udelay(2);
356
357         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
358         gfar_write(&priv->regs->maccfg1, tempval);
359
360         /* Initialize MACCFG2. */
361         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
362
363         /* Initialize ECNTRL */
364         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
365
366         /* Set the dev->base_addr to the gfar reg region */
367         dev->base_addr = (unsigned long) (priv->regs);
368
369         SET_NETDEV_DEV(dev, &ofdev->dev);
370
371         /* Fill in the dev structure */
372         dev->open = gfar_enet_open;
373         dev->hard_start_xmit = gfar_start_xmit;
374         dev->tx_timeout = gfar_timeout;
375         dev->watchdog_timeo = TX_TIMEOUT;
376         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
377 #ifdef CONFIG_NET_POLL_CONTROLLER
378         dev->poll_controller = gfar_netpoll;
379 #endif
380         dev->stop = gfar_close;
381         dev->change_mtu = gfar_change_mtu;
382         dev->mtu = 1500;
383         dev->set_multicast_list = gfar_set_multi;
384
385         dev->ethtool_ops = &gfar_ethtool_ops;
386         dev->do_ioctl = gfar_ioctl;
387
388         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
389                 priv->rx_csum_enable = 1;
390                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
391         } else
392                 priv->rx_csum_enable = 0;
393
394         priv->vlgrp = NULL;
395
396         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
397                 dev->vlan_rx_register = gfar_vlan_rx_register;
398
399                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
400         }
401
402         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
403                 priv->extended_hash = 1;
404                 priv->hash_width = 9;
405
406                 priv->hash_regs[0] = &priv->regs->igaddr0;
407                 priv->hash_regs[1] = &priv->regs->igaddr1;
408                 priv->hash_regs[2] = &priv->regs->igaddr2;
409                 priv->hash_regs[3] = &priv->regs->igaddr3;
410                 priv->hash_regs[4] = &priv->regs->igaddr4;
411                 priv->hash_regs[5] = &priv->regs->igaddr5;
412                 priv->hash_regs[6] = &priv->regs->igaddr6;
413                 priv->hash_regs[7] = &priv->regs->igaddr7;
414                 priv->hash_regs[8] = &priv->regs->gaddr0;
415                 priv->hash_regs[9] = &priv->regs->gaddr1;
416                 priv->hash_regs[10] = &priv->regs->gaddr2;
417                 priv->hash_regs[11] = &priv->regs->gaddr3;
418                 priv->hash_regs[12] = &priv->regs->gaddr4;
419                 priv->hash_regs[13] = &priv->regs->gaddr5;
420                 priv->hash_regs[14] = &priv->regs->gaddr6;
421                 priv->hash_regs[15] = &priv->regs->gaddr7;
422
423         } else {
424                 priv->extended_hash = 0;
425                 priv->hash_width = 8;
426
427                 priv->hash_regs[0] = &priv->regs->gaddr0;
428                 priv->hash_regs[1] = &priv->regs->gaddr1;
429                 priv->hash_regs[2] = &priv->regs->gaddr2;
430                 priv->hash_regs[3] = &priv->regs->gaddr3;
431                 priv->hash_regs[4] = &priv->regs->gaddr4;
432                 priv->hash_regs[5] = &priv->regs->gaddr5;
433                 priv->hash_regs[6] = &priv->regs->gaddr6;
434                 priv->hash_regs[7] = &priv->regs->gaddr7;
435         }
436
437         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
438                 priv->padding = DEFAULT_PADDING;
439         else
440                 priv->padding = 0;
441
442         if (dev->features & NETIF_F_IP_CSUM)
443                 dev->hard_header_len += GMAC_FCB_LEN;
444
445         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
446         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
447         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
448         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
449
450         priv->txcoalescing = DEFAULT_TX_COALESCE;
451         priv->txic = DEFAULT_TXIC;
452         priv->rxcoalescing = DEFAULT_RX_COALESCE;
453         priv->rxic = DEFAULT_RXIC;
454
455         /* Enable most messages by default */
456         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
457
458         /* Carrier starts down, phylib will bring it up */
459         netif_carrier_off(dev);
460
461         err = register_netdev(dev);
462
463         if (err) {
464                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
465                                 dev->name);
466                 goto register_fail;
467         }
468
469         /* fill out IRQ number and name fields */
470         len_devname = strlen(dev->name);
471         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
472         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
473                 strncpy(&priv->int_name_tx[len_devname],
474                         "_tx", sizeof("_tx") + 1);
475
476                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
477                 strncpy(&priv->int_name_rx[len_devname],
478                         "_rx", sizeof("_rx") + 1);
479
480                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
481                 strncpy(&priv->int_name_er[len_devname],
482                         "_er", sizeof("_er") + 1);
483         } else
484                 priv->int_name_tx[len_devname] = '\0';
485
486         /* Create all the sysfs files */
487         gfar_init_sysfs(dev);
488
489         /* Print out the device info */
490         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
491
492         /* Even more device info helps when determining which kernel */
493         /* provided which set of benchmarks. */
494         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
495         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
496                dev->name, priv->rx_ring_size, priv->tx_ring_size);
497
498         return 0;
499
500 register_fail:
501         iounmap(priv->regs);
502 regs_fail:
503         free_netdev(dev);
504         return err;
505 }
506
507 static int gfar_remove(struct of_device *ofdev)
508 {
509         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
510
511         dev_set_drvdata(&ofdev->dev, NULL);
512
513         iounmap(priv->regs);
514         free_netdev(priv->dev);
515
516         return 0;
517 }
518
519 #ifdef CONFIG_PM
520 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
521 {
522         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
523         struct net_device *dev = priv->dev;
524         unsigned long flags;
525         u32 tempval;
526
527         int magic_packet = priv->wol_en &&
528                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
529
530         netif_device_detach(dev);
531
532         if (netif_running(dev)) {
533                 spin_lock_irqsave(&priv->txlock, flags);
534                 spin_lock(&priv->rxlock);
535
536                 gfar_halt_nodisable(dev);
537
538                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
539                 tempval = gfar_read(&priv->regs->maccfg1);
540
541                 tempval &= ~MACCFG1_TX_EN;
542
543                 if (!magic_packet)
544                         tempval &= ~MACCFG1_RX_EN;
545
546                 gfar_write(&priv->regs->maccfg1, tempval);
547
548                 spin_unlock(&priv->rxlock);
549                 spin_unlock_irqrestore(&priv->txlock, flags);
550
551                 napi_disable(&priv->napi);
552
553                 if (magic_packet) {
554                         /* Enable interrupt on Magic Packet */
555                         gfar_write(&priv->regs->imask, IMASK_MAG);
556
557                         /* Enable Magic Packet mode */
558                         tempval = gfar_read(&priv->regs->maccfg2);
559                         tempval |= MACCFG2_MPEN;
560                         gfar_write(&priv->regs->maccfg2, tempval);
561                 } else {
562                         phy_stop(priv->phydev);
563                 }
564         }
565
566         return 0;
567 }
568
569 static int gfar_resume(struct of_device *ofdev)
570 {
571         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
572         struct net_device *dev = priv->dev;
573         unsigned long flags;
574         u32 tempval;
575         int magic_packet = priv->wol_en &&
576                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
577
578         if (!netif_running(dev)) {
579                 netif_device_attach(dev);
580                 return 0;
581         }
582
583         if (!magic_packet && priv->phydev)
584                 phy_start(priv->phydev);
585
586         /* Disable Magic Packet mode, in case something
587          * else woke us up.
588          */
589
590         spin_lock_irqsave(&priv->txlock, flags);
591         spin_lock(&priv->rxlock);
592
593         tempval = gfar_read(&priv->regs->maccfg2);
594         tempval &= ~MACCFG2_MPEN;
595         gfar_write(&priv->regs->maccfg2, tempval);
596
597         gfar_start(dev);
598
599         spin_unlock(&priv->rxlock);
600         spin_unlock_irqrestore(&priv->txlock, flags);
601
602         netif_device_attach(dev);
603
604         napi_enable(&priv->napi);
605
606         return 0;
607 }
608 #else
609 #define gfar_suspend NULL
610 #define gfar_resume NULL
611 #endif
612
613 /* Reads the controller's registers to determine what interface
614  * connects it to the PHY.
615  */
616 static phy_interface_t gfar_get_interface(struct net_device *dev)
617 {
618         struct gfar_private *priv = netdev_priv(dev);
619         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
620
621         if (ecntrl & ECNTRL_SGMII_MODE)
622                 return PHY_INTERFACE_MODE_SGMII;
623
624         if (ecntrl & ECNTRL_TBI_MODE) {
625                 if (ecntrl & ECNTRL_REDUCED_MODE)
626                         return PHY_INTERFACE_MODE_RTBI;
627                 else
628                         return PHY_INTERFACE_MODE_TBI;
629         }
630
631         if (ecntrl & ECNTRL_REDUCED_MODE) {
632                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
633                         return PHY_INTERFACE_MODE_RMII;
634                 else {
635                         phy_interface_t interface = priv->interface;
636
637                         /*
638                          * This isn't autodetected right now, so it must
639                          * be set by the device tree or platform code.
640                          */
641                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
642                                 return PHY_INTERFACE_MODE_RGMII_ID;
643
644                         return PHY_INTERFACE_MODE_RGMII;
645                 }
646         }
647
648         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
649                 return PHY_INTERFACE_MODE_GMII;
650
651         return PHY_INTERFACE_MODE_MII;
652 }
653
654
655 /* Initializes driver's PHY state, and attaches to the PHY.
656  * Returns 0 on success.
657  */
658 static int init_phy(struct net_device *dev)
659 {
660         struct gfar_private *priv = netdev_priv(dev);
661         uint gigabit_support =
662                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
663                 SUPPORTED_1000baseT_Full : 0;
664         struct phy_device *phydev;
665         phy_interface_t interface;
666
667         priv->oldlink = 0;
668         priv->oldspeed = 0;
669         priv->oldduplex = -1;
670
671         interface = gfar_get_interface(dev);
672
673         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
674
675         if (interface == PHY_INTERFACE_MODE_SGMII)
676                 gfar_configure_serdes(dev);
677
678         if (IS_ERR(phydev)) {
679                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
680                 return PTR_ERR(phydev);
681         }
682
683         /* Remove any features not supported by the controller */
684         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
685         phydev->advertising = phydev->supported;
686
687         priv->phydev = phydev;
688
689         return 0;
690 }
691
692 /*
693  * Initialize TBI PHY interface for communicating with the
694  * SERDES lynx PHY on the chip.  We communicate with this PHY
695  * through the MDIO bus on each controller, treating it as a
696  * "normal" PHY at the address found in the TBIPA register.  We assume
697  * that the TBIPA register is valid.  Either the MDIO bus code will set
698  * it to a value that doesn't conflict with other PHYs on the bus, or the
699  * value doesn't matter, as there are no other PHYs on the bus.
700  */
701 static void gfar_configure_serdes(struct net_device *dev)
702 {
703         struct gfar_private *priv = netdev_priv(dev);
704
705         if (!priv->tbiphy) {
706                 printk(KERN_WARNING "SGMII mode requires that the device "
707                                 "tree specify a tbi-handle\n");
708                 return;
709         }
710
711         /*
712          * If the link is already up, we must already be ok, and don't need to
713          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
714          * everything for us?  Resetting it takes the link down and requires
715          * several seconds for it to come back.
716          */
717         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
718                 return;
719
720         /* Single clk mode, mii mode off(for serdes communication) */
721         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
722
723         phy_write(priv->tbiphy, MII_ADVERTISE,
724                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
725                         ADVERTISE_1000XPSE_ASYM);
726
727         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
728                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
729 }
730
731 static void init_registers(struct net_device *dev)
732 {
733         struct gfar_private *priv = netdev_priv(dev);
734
735         /* Clear IEVENT */
736         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
737
738         /* Initialize IMASK */
739         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
740
741         /* Init hash registers to zero */
742         gfar_write(&priv->regs->igaddr0, 0);
743         gfar_write(&priv->regs->igaddr1, 0);
744         gfar_write(&priv->regs->igaddr2, 0);
745         gfar_write(&priv->regs->igaddr3, 0);
746         gfar_write(&priv->regs->igaddr4, 0);
747         gfar_write(&priv->regs->igaddr5, 0);
748         gfar_write(&priv->regs->igaddr6, 0);
749         gfar_write(&priv->regs->igaddr7, 0);
750
751         gfar_write(&priv->regs->gaddr0, 0);
752         gfar_write(&priv->regs->gaddr1, 0);
753         gfar_write(&priv->regs->gaddr2, 0);
754         gfar_write(&priv->regs->gaddr3, 0);
755         gfar_write(&priv->regs->gaddr4, 0);
756         gfar_write(&priv->regs->gaddr5, 0);
757         gfar_write(&priv->regs->gaddr6, 0);
758         gfar_write(&priv->regs->gaddr7, 0);
759
760         /* Zero out the rmon mib registers if it has them */
761         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
762                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
763
764                 /* Mask off the CAM interrupts */
765                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
766                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
767         }
768
769         /* Initialize the max receive buffer length */
770         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
771
772         /* Initialize the Minimum Frame Length Register */
773         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
774 }
775
776
777 /* Halt the receive and transmit queues */
778 static void gfar_halt_nodisable(struct net_device *dev)
779 {
780         struct gfar_private *priv = netdev_priv(dev);
781         struct gfar __iomem *regs = priv->regs;
782         u32 tempval;
783
784         /* Mask all interrupts */
785         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
786
787         /* Clear all interrupts */
788         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
789
790         /* Stop the DMA, and wait for it to stop */
791         tempval = gfar_read(&priv->regs->dmactrl);
792         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
793             != (DMACTRL_GRS | DMACTRL_GTS)) {
794                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
795                 gfar_write(&priv->regs->dmactrl, tempval);
796
797                 while (!(gfar_read(&priv->regs->ievent) &
798                          (IEVENT_GRSC | IEVENT_GTSC)))
799                         cpu_relax();
800         }
801 }
802
803 /* Halt the receive and transmit queues */
804 void gfar_halt(struct net_device *dev)
805 {
806         struct gfar_private *priv = netdev_priv(dev);
807         struct gfar __iomem *regs = priv->regs;
808         u32 tempval;
809
810         gfar_halt_nodisable(dev);
811
812         /* Disable Rx and Tx */
813         tempval = gfar_read(&regs->maccfg1);
814         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
815         gfar_write(&regs->maccfg1, tempval);
816 }
817
818 void stop_gfar(struct net_device *dev)
819 {
820         struct gfar_private *priv = netdev_priv(dev);
821         struct gfar __iomem *regs = priv->regs;
822         unsigned long flags;
823
824         phy_stop(priv->phydev);
825
826         /* Lock it down */
827         spin_lock_irqsave(&priv->txlock, flags);
828         spin_lock(&priv->rxlock);
829
830         gfar_halt(dev);
831
832         spin_unlock(&priv->rxlock);
833         spin_unlock_irqrestore(&priv->txlock, flags);
834
835         /* Free the IRQs */
836         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
837                 free_irq(priv->interruptError, dev);
838                 free_irq(priv->interruptTransmit, dev);
839                 free_irq(priv->interruptReceive, dev);
840         } else {
841                 free_irq(priv->interruptTransmit, dev);
842         }
843
844         free_skb_resources(priv);
845
846         dma_free_coherent(&dev->dev,
847                         sizeof(struct txbd8)*priv->tx_ring_size
848                         + sizeof(struct rxbd8)*priv->rx_ring_size,
849                         priv->tx_bd_base,
850                         gfar_read(&regs->tbase0));
851 }
852
853 /* If there are any tx skbs or rx skbs still around, free them.
854  * Then free tx_skbuff and rx_skbuff */
855 static void free_skb_resources(struct gfar_private *priv)
856 {
857         struct rxbd8 *rxbdp;
858         struct txbd8 *txbdp;
859         int i, j;
860
861         /* Go through all the buffer descriptors and free their data buffers */
862         txbdp = priv->tx_bd_base;
863
864         for (i = 0; i < priv->tx_ring_size; i++) {
865                 if (!priv->tx_skbuff[i])
866                         continue;
867
868                 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
869                                 txbdp->length, DMA_TO_DEVICE);
870                 txbdp->lstatus = 0;
871                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
872                         txbdp++;
873                         dma_unmap_page(&priv->dev->dev, txbdp->bufPtr,
874                                         txbdp->length, DMA_TO_DEVICE);
875                 }
876                 txbdp++;
877                 dev_kfree_skb_any(priv->tx_skbuff[i]);
878                 priv->tx_skbuff[i] = NULL;
879         }
880
881         kfree(priv->tx_skbuff);
882
883         rxbdp = priv->rx_bd_base;
884
885         /* rx_skbuff is not guaranteed to be allocated, so only
886          * free it and its contents if it is allocated */
887         if(priv->rx_skbuff != NULL) {
888                 for (i = 0; i < priv->rx_ring_size; i++) {
889                         if (priv->rx_skbuff[i]) {
890                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
891                                                 priv->rx_buffer_size,
892                                                 DMA_FROM_DEVICE);
893
894                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
895                                 priv->rx_skbuff[i] = NULL;
896                         }
897
898                         rxbdp->lstatus = 0;
899                         rxbdp->bufPtr = 0;
900
901                         rxbdp++;
902                 }
903
904                 kfree(priv->rx_skbuff);
905         }
906 }
907
908 void gfar_start(struct net_device *dev)
909 {
910         struct gfar_private *priv = netdev_priv(dev);
911         struct gfar __iomem *regs = priv->regs;
912         u32 tempval;
913
914         /* Enable Rx and Tx in MACCFG1 */
915         tempval = gfar_read(&regs->maccfg1);
916         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
917         gfar_write(&regs->maccfg1, tempval);
918
919         /* Initialize DMACTRL to have WWR and WOP */
920         tempval = gfar_read(&priv->regs->dmactrl);
921         tempval |= DMACTRL_INIT_SETTINGS;
922         gfar_write(&priv->regs->dmactrl, tempval);
923
924         /* Make sure we aren't stopped */
925         tempval = gfar_read(&priv->regs->dmactrl);
926         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
927         gfar_write(&priv->regs->dmactrl, tempval);
928
929         /* Clear THLT/RHLT, so that the DMA starts polling now */
930         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
931         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
932
933         /* Unmask the interrupts we look for */
934         gfar_write(&regs->imask, IMASK_DEFAULT);
935
936         dev->trans_start = jiffies;
937 }
938
939 /* Bring the controller up and running */
940 int startup_gfar(struct net_device *dev)
941 {
942         struct txbd8 *txbdp;
943         struct rxbd8 *rxbdp;
944         dma_addr_t addr = 0;
945         unsigned long vaddr;
946         int i;
947         struct gfar_private *priv = netdev_priv(dev);
948         struct gfar __iomem *regs = priv->regs;
949         int err = 0;
950         u32 rctrl = 0;
951         u32 attrs = 0;
952
953         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
954
955         /* Allocate memory for the buffer descriptors */
956         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
957                         sizeof (struct txbd8) * priv->tx_ring_size +
958                         sizeof (struct rxbd8) * priv->rx_ring_size,
959                         &addr, GFP_KERNEL);
960
961         if (vaddr == 0) {
962                 if (netif_msg_ifup(priv))
963                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
964                                         dev->name);
965                 return -ENOMEM;
966         }
967
968         priv->tx_bd_base = (struct txbd8 *) vaddr;
969
970         /* enet DMA only understands physical addresses */
971         gfar_write(&regs->tbase0, addr);
972
973         /* Start the rx descriptor ring where the tx ring leaves off */
974         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
975         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
976         priv->rx_bd_base = (struct rxbd8 *) vaddr;
977         gfar_write(&regs->rbase0, addr);
978
979         /* Setup the skbuff rings */
980         priv->tx_skbuff =
981             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
982                                         priv->tx_ring_size, GFP_KERNEL);
983
984         if (NULL == priv->tx_skbuff) {
985                 if (netif_msg_ifup(priv))
986                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
987                                         dev->name);
988                 err = -ENOMEM;
989                 goto tx_skb_fail;
990         }
991
992         for (i = 0; i < priv->tx_ring_size; i++)
993                 priv->tx_skbuff[i] = NULL;
994
995         priv->rx_skbuff =
996             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
997                                         priv->rx_ring_size, GFP_KERNEL);
998
999         if (NULL == priv->rx_skbuff) {
1000                 if (netif_msg_ifup(priv))
1001                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1002                                         dev->name);
1003                 err = -ENOMEM;
1004                 goto rx_skb_fail;
1005         }
1006
1007         for (i = 0; i < priv->rx_ring_size; i++)
1008                 priv->rx_skbuff[i] = NULL;
1009
1010         /* Initialize some variables in our dev structure */
1011         priv->num_txbdfree = priv->tx_ring_size;
1012         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1013         priv->cur_rx = priv->rx_bd_base;
1014         priv->skb_curtx = priv->skb_dirtytx = 0;
1015         priv->skb_currx = 0;
1016
1017         /* Initialize Transmit Descriptor Ring */
1018         txbdp = priv->tx_bd_base;
1019         for (i = 0; i < priv->tx_ring_size; i++) {
1020                 txbdp->lstatus = 0;
1021                 txbdp->bufPtr = 0;
1022                 txbdp++;
1023         }
1024
1025         /* Set the last descriptor in the ring to indicate wrap */
1026         txbdp--;
1027         txbdp->status |= TXBD_WRAP;
1028
1029         rxbdp = priv->rx_bd_base;
1030         for (i = 0; i < priv->rx_ring_size; i++) {
1031                 struct sk_buff *skb;
1032
1033                 skb = gfar_new_skb(dev);
1034
1035                 if (!skb) {
1036                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1037                                         dev->name);
1038
1039                         goto err_rxalloc_fail;
1040                 }
1041
1042                 priv->rx_skbuff[i] = skb;
1043
1044                 gfar_new_rxbdp(dev, rxbdp, skb);
1045
1046                 rxbdp++;
1047         }
1048
1049         /* Set the last descriptor in the ring to wrap */
1050         rxbdp--;
1051         rxbdp->status |= RXBD_WRAP;
1052
1053         /* If the device has multiple interrupts, register for
1054          * them.  Otherwise, only register for the one */
1055         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1056                 /* Install our interrupt handlers for Error,
1057                  * Transmit, and Receive */
1058                 if (request_irq(priv->interruptError, gfar_error,
1059                                 0, priv->int_name_er, dev) < 0) {
1060                         if (netif_msg_intr(priv))
1061                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1062                                         dev->name, priv->interruptError);
1063
1064                         err = -1;
1065                         goto err_irq_fail;
1066                 }
1067
1068                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1069                                 0, priv->int_name_tx, dev) < 0) {
1070                         if (netif_msg_intr(priv))
1071                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1072                                         dev->name, priv->interruptTransmit);
1073
1074                         err = -1;
1075
1076                         goto tx_irq_fail;
1077                 }
1078
1079                 if (request_irq(priv->interruptReceive, gfar_receive,
1080                                 0, priv->int_name_rx, dev) < 0) {
1081                         if (netif_msg_intr(priv))
1082                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1083                                                 dev->name, priv->interruptReceive);
1084
1085                         err = -1;
1086                         goto rx_irq_fail;
1087                 }
1088         } else {
1089                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1090                                 0, priv->int_name_tx, dev) < 0) {
1091                         if (netif_msg_intr(priv))
1092                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1093                                         dev->name, priv->interruptTransmit);
1094
1095                         err = -1;
1096                         goto err_irq_fail;
1097                 }
1098         }
1099
1100         phy_start(priv->phydev);
1101
1102         /* Configure the coalescing support */
1103         gfar_write(&regs->txic, 0);
1104         if (priv->txcoalescing)
1105                 gfar_write(&regs->txic, priv->txic);
1106
1107         gfar_write(&regs->rxic, 0);
1108         if (priv->rxcoalescing)
1109                 gfar_write(&regs->rxic, priv->rxic);
1110
1111         if (priv->rx_csum_enable)
1112                 rctrl |= RCTRL_CHECKSUMMING;
1113
1114         if (priv->extended_hash) {
1115                 rctrl |= RCTRL_EXTHASH;
1116
1117                 gfar_clear_exact_match(dev);
1118                 rctrl |= RCTRL_EMEN;
1119         }
1120
1121         if (priv->padding) {
1122                 rctrl &= ~RCTRL_PAL_MASK;
1123                 rctrl |= RCTRL_PADDING(priv->padding);
1124         }
1125
1126         /* Init rctrl based on our settings */
1127         gfar_write(&priv->regs->rctrl, rctrl);
1128
1129         if (dev->features & NETIF_F_IP_CSUM)
1130                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1131
1132         /* Set the extraction length and index */
1133         attrs = ATTRELI_EL(priv->rx_stash_size) |
1134                 ATTRELI_EI(priv->rx_stash_index);
1135
1136         gfar_write(&priv->regs->attreli, attrs);
1137
1138         /* Start with defaults, and add stashing or locking
1139          * depending on the approprate variables */
1140         attrs = ATTR_INIT_SETTINGS;
1141
1142         if (priv->bd_stash_en)
1143                 attrs |= ATTR_BDSTASH;
1144
1145         if (priv->rx_stash_size != 0)
1146                 attrs |= ATTR_BUFSTASH;
1147
1148         gfar_write(&priv->regs->attr, attrs);
1149
1150         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1151         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1152         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1153
1154         /* Start the controller */
1155         gfar_start(dev);
1156
1157         return 0;
1158
1159 rx_irq_fail:
1160         free_irq(priv->interruptTransmit, dev);
1161 tx_irq_fail:
1162         free_irq(priv->interruptError, dev);
1163 err_irq_fail:
1164 err_rxalloc_fail:
1165 rx_skb_fail:
1166         free_skb_resources(priv);
1167 tx_skb_fail:
1168         dma_free_coherent(&dev->dev,
1169                         sizeof(struct txbd8)*priv->tx_ring_size
1170                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1171                         priv->tx_bd_base,
1172                         gfar_read(&regs->tbase0));
1173
1174         return err;
1175 }
1176
1177 /* Called when something needs to use the ethernet device */
1178 /* Returns 0 for success. */
1179 static int gfar_enet_open(struct net_device *dev)
1180 {
1181         struct gfar_private *priv = netdev_priv(dev);
1182         int err;
1183
1184         napi_enable(&priv->napi);
1185
1186         /* Initialize a bunch of registers */
1187         init_registers(dev);
1188
1189         gfar_set_mac_address(dev);
1190
1191         err = init_phy(dev);
1192
1193         if(err) {
1194                 napi_disable(&priv->napi);
1195                 return err;
1196         }
1197
1198         err = startup_gfar(dev);
1199         if (err) {
1200                 napi_disable(&priv->napi);
1201                 return err;
1202         }
1203
1204         netif_start_queue(dev);
1205
1206         return err;
1207 }
1208
1209 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1210 {
1211         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1212
1213         cacheable_memzero(fcb, GMAC_FCB_LEN);
1214
1215         return fcb;
1216 }
1217
1218 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1219 {
1220         u8 flags = 0;
1221
1222         /* If we're here, it's a IP packet with a TCP or UDP
1223          * payload.  We set it to checksum, using a pseudo-header
1224          * we provide
1225          */
1226         flags = TXFCB_DEFAULT;
1227
1228         /* Tell the controller what the protocol is */
1229         /* And provide the already calculated phcs */
1230         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1231                 flags |= TXFCB_UDP;
1232                 fcb->phcs = udp_hdr(skb)->check;
1233         } else
1234                 fcb->phcs = tcp_hdr(skb)->check;
1235
1236         /* l3os is the distance between the start of the
1237          * frame (skb->data) and the start of the IP hdr.
1238          * l4os is the distance between the start of the
1239          * l3 hdr and the l4 hdr */
1240         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1241         fcb->l4os = skb_network_header_len(skb);
1242
1243         fcb->flags = flags;
1244 }
1245
1246 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1247 {
1248         fcb->flags |= TXFCB_VLN;
1249         fcb->vlctl = vlan_tx_tag_get(skb);
1250 }
1251
1252 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1253                                struct txbd8 *base, int ring_size)
1254 {
1255         struct txbd8 *new_bd = bdp + stride;
1256
1257         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1258 }
1259
1260 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1261                 int ring_size)
1262 {
1263         return skip_txbd(bdp, 1, base, ring_size);
1264 }
1265
1266 /* This is called by the kernel when a frame is ready for transmission. */
1267 /* It is pointed to by the dev->hard_start_xmit function pointer */
1268 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1269 {
1270         struct gfar_private *priv = netdev_priv(dev);
1271         struct txfcb *fcb = NULL;
1272         struct txbd8 *txbdp, *txbdp_start, *base;
1273         u32 lstatus;
1274         int i;
1275         u32 bufaddr;
1276         unsigned long flags;
1277         unsigned int nr_frags, length;
1278
1279         base = priv->tx_bd_base;
1280
1281         /* total number of fragments in the SKB */
1282         nr_frags = skb_shinfo(skb)->nr_frags;
1283
1284         spin_lock_irqsave(&priv->txlock, flags);
1285
1286         /* check if there is space to queue this packet */
1287         if (nr_frags > priv->num_txbdfree) {
1288                 /* no space, stop the queue */
1289                 netif_stop_queue(dev);
1290                 dev->stats.tx_fifo_errors++;
1291                 spin_unlock_irqrestore(&priv->txlock, flags);
1292                 return NETDEV_TX_BUSY;
1293         }
1294
1295         /* Update transmit stats */
1296         dev->stats.tx_bytes += skb->len;
1297
1298         txbdp = txbdp_start = priv->cur_tx;
1299
1300         if (nr_frags == 0) {
1301                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1302         } else {
1303                 /* Place the fragment addresses and lengths into the TxBDs */
1304                 for (i = 0; i < nr_frags; i++) {
1305                         /* Point at the next BD, wrapping as needed */
1306                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1307
1308                         length = skb_shinfo(skb)->frags[i].size;
1309
1310                         lstatus = txbdp->lstatus | length |
1311                                 BD_LFLAG(TXBD_READY);
1312
1313                         /* Handle the last BD specially */
1314                         if (i == nr_frags - 1)
1315                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1316
1317                         bufaddr = dma_map_page(&dev->dev,
1318                                         skb_shinfo(skb)->frags[i].page,
1319                                         skb_shinfo(skb)->frags[i].page_offset,
1320                                         length,
1321                                         DMA_TO_DEVICE);
1322
1323                         /* set the TxBD length and buffer pointer */
1324                         txbdp->bufPtr = bufaddr;
1325                         txbdp->lstatus = lstatus;
1326                 }
1327
1328                 lstatus = txbdp_start->lstatus;
1329         }
1330
1331         /* Set up checksumming */
1332         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1333                 fcb = gfar_add_fcb(skb);
1334                 lstatus |= BD_LFLAG(TXBD_TOE);
1335                 gfar_tx_checksum(skb, fcb);
1336         }
1337
1338         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1339                 if (unlikely(NULL == fcb)) {
1340                         fcb = gfar_add_fcb(skb);
1341                         lstatus |= BD_LFLAG(TXBD_TOE);
1342                 }
1343
1344                 gfar_tx_vlan(skb, fcb);
1345         }
1346
1347         /* setup the TxBD length and buffer pointer for the first BD */
1348         priv->tx_skbuff[priv->skb_curtx] = skb;
1349         txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data,
1350                         skb_headlen(skb), DMA_TO_DEVICE);
1351
1352         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1353
1354         /*
1355          * The powerpc-specific eieio() is used, as wmb() has too strong
1356          * semantics (it requires synchronization between cacheable and
1357          * uncacheable mappings, which eieio doesn't provide and which we
1358          * don't need), thus requiring a more expensive sync instruction.  At
1359          * some point, the set of architecture-independent barrier functions
1360          * should be expanded to include weaker barriers.
1361          */
1362         eieio();
1363
1364         txbdp_start->lstatus = lstatus;
1365
1366         /* Update the current skb pointer to the next entry we will use
1367          * (wrapping if necessary) */
1368         priv->skb_curtx = (priv->skb_curtx + 1) &
1369                 TX_RING_MOD_MASK(priv->tx_ring_size);
1370
1371         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1372
1373         /* reduce TxBD free count */
1374         priv->num_txbdfree -= (nr_frags + 1);
1375
1376         dev->trans_start = jiffies;
1377
1378         /* If the next BD still needs to be cleaned up, then the bds
1379            are full.  We need to tell the kernel to stop sending us stuff. */
1380         if (!priv->num_txbdfree) {
1381                 netif_stop_queue(dev);
1382
1383                 dev->stats.tx_fifo_errors++;
1384         }
1385
1386         /* Tell the DMA to go go go */
1387         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1388
1389         /* Unlock priv */
1390         spin_unlock_irqrestore(&priv->txlock, flags);
1391
1392         return 0;
1393 }
1394
1395 /* Stops the kernel queue, and halts the controller */
1396 static int gfar_close(struct net_device *dev)
1397 {
1398         struct gfar_private *priv = netdev_priv(dev);
1399
1400         napi_disable(&priv->napi);
1401
1402         cancel_work_sync(&priv->reset_task);
1403         stop_gfar(dev);
1404
1405         /* Disconnect from the PHY */
1406         phy_disconnect(priv->phydev);
1407         priv->phydev = NULL;
1408
1409         netif_stop_queue(dev);
1410
1411         return 0;
1412 }
1413
1414 /* Changes the mac address if the controller is not running. */
1415 static int gfar_set_mac_address(struct net_device *dev)
1416 {
1417         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1418
1419         return 0;
1420 }
1421
1422
1423 /* Enables and disables VLAN insertion/extraction */
1424 static void gfar_vlan_rx_register(struct net_device *dev,
1425                 struct vlan_group *grp)
1426 {
1427         struct gfar_private *priv = netdev_priv(dev);
1428         unsigned long flags;
1429         u32 tempval;
1430
1431         spin_lock_irqsave(&priv->rxlock, flags);
1432
1433         priv->vlgrp = grp;
1434
1435         if (grp) {
1436                 /* Enable VLAN tag insertion */
1437                 tempval = gfar_read(&priv->regs->tctrl);
1438                 tempval |= TCTRL_VLINS;
1439
1440                 gfar_write(&priv->regs->tctrl, tempval);
1441
1442                 /* Enable VLAN tag extraction */
1443                 tempval = gfar_read(&priv->regs->rctrl);
1444                 tempval |= RCTRL_VLEX;
1445                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1446                 gfar_write(&priv->regs->rctrl, tempval);
1447         } else {
1448                 /* Disable VLAN tag insertion */
1449                 tempval = gfar_read(&priv->regs->tctrl);
1450                 tempval &= ~TCTRL_VLINS;
1451                 gfar_write(&priv->regs->tctrl, tempval);
1452
1453                 /* Disable VLAN tag extraction */
1454                 tempval = gfar_read(&priv->regs->rctrl);
1455                 tempval &= ~RCTRL_VLEX;
1456                 /* If parse is no longer required, then disable parser */
1457                 if (tempval & RCTRL_REQ_PARSER)
1458                         tempval |= RCTRL_PRSDEP_INIT;
1459                 else
1460                         tempval &= ~RCTRL_PRSDEP_INIT;
1461                 gfar_write(&priv->regs->rctrl, tempval);
1462         }
1463
1464         gfar_change_mtu(dev, dev->mtu);
1465
1466         spin_unlock_irqrestore(&priv->rxlock, flags);
1467 }
1468
1469 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1470 {
1471         int tempsize, tempval;
1472         struct gfar_private *priv = netdev_priv(dev);
1473         int oldsize = priv->rx_buffer_size;
1474         int frame_size = new_mtu + ETH_HLEN;
1475
1476         if (priv->vlgrp)
1477                 frame_size += VLAN_HLEN;
1478
1479         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1480                 if (netif_msg_drv(priv))
1481                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1482                                         dev->name);
1483                 return -EINVAL;
1484         }
1485
1486         if (gfar_uses_fcb(priv))
1487                 frame_size += GMAC_FCB_LEN;
1488
1489         frame_size += priv->padding;
1490
1491         tempsize =
1492             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1493             INCREMENTAL_BUFFER_SIZE;
1494
1495         /* Only stop and start the controller if it isn't already
1496          * stopped, and we changed something */
1497         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1498                 stop_gfar(dev);
1499
1500         priv->rx_buffer_size = tempsize;
1501
1502         dev->mtu = new_mtu;
1503
1504         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1505         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1506
1507         /* If the mtu is larger than the max size for standard
1508          * ethernet frames (ie, a jumbo frame), then set maccfg2
1509          * to allow huge frames, and to check the length */
1510         tempval = gfar_read(&priv->regs->maccfg2);
1511
1512         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1513                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1514         else
1515                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1516
1517         gfar_write(&priv->regs->maccfg2, tempval);
1518
1519         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1520                 startup_gfar(dev);
1521
1522         return 0;
1523 }
1524
1525 /* gfar_reset_task gets scheduled when a packet has not been
1526  * transmitted after a set amount of time.
1527  * For now, assume that clearing out all the structures, and
1528  * starting over will fix the problem.
1529  */
1530 static void gfar_reset_task(struct work_struct *work)
1531 {
1532         struct gfar_private *priv = container_of(work, struct gfar_private,
1533                         reset_task);
1534         struct net_device *dev = priv->dev;
1535
1536         if (dev->flags & IFF_UP) {
1537                 stop_gfar(dev);
1538                 startup_gfar(dev);
1539         }
1540
1541         netif_tx_schedule_all(dev);
1542 }
1543
1544 static void gfar_timeout(struct net_device *dev)
1545 {
1546         struct gfar_private *priv = netdev_priv(dev);
1547
1548         dev->stats.tx_errors++;
1549         schedule_work(&priv->reset_task);
1550 }
1551
1552 /* Interrupt Handler for Transmit complete */
1553 static int gfar_clean_tx_ring(struct net_device *dev)
1554 {
1555         struct gfar_private *priv = netdev_priv(dev);
1556         struct txbd8 *bdp;
1557         struct txbd8 *lbdp = NULL;
1558         struct txbd8 *base = priv->tx_bd_base;
1559         struct sk_buff *skb;
1560         int skb_dirtytx;
1561         int tx_ring_size = priv->tx_ring_size;
1562         int frags = 0;
1563         int i;
1564         int howmany = 0;
1565         u32 lstatus;
1566
1567         bdp = priv->dirty_tx;
1568         skb_dirtytx = priv->skb_dirtytx;
1569
1570         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1571                 frags = skb_shinfo(skb)->nr_frags;
1572                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1573
1574                 lstatus = lbdp->lstatus;
1575
1576                 /* Only clean completed frames */
1577                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1578                                 (lstatus & BD_LENGTH_MASK))
1579                         break;
1580
1581                 dma_unmap_single(&dev->dev,
1582                                 bdp->bufPtr,
1583                                 bdp->length,
1584                                 DMA_TO_DEVICE);
1585
1586                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1587                 bdp = next_txbd(bdp, base, tx_ring_size);
1588
1589                 for (i = 0; i < frags; i++) {
1590                         dma_unmap_page(&dev->dev,
1591                                         bdp->bufPtr,
1592                                         bdp->length,
1593                                         DMA_TO_DEVICE);
1594                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1595                         bdp = next_txbd(bdp, base, tx_ring_size);
1596                 }
1597
1598                 dev_kfree_skb_any(skb);
1599                 priv->tx_skbuff[skb_dirtytx] = NULL;
1600
1601                 skb_dirtytx = (skb_dirtytx + 1) &
1602                         TX_RING_MOD_MASK(tx_ring_size);
1603
1604                 howmany++;
1605                 priv->num_txbdfree += frags + 1;
1606         }
1607
1608         /* If we freed a buffer, we can restart transmission, if necessary */
1609         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1610                 netif_wake_queue(dev);
1611
1612         /* Update dirty indicators */
1613         priv->skb_dirtytx = skb_dirtytx;
1614         priv->dirty_tx = bdp;
1615
1616         dev->stats.tx_packets += howmany;
1617
1618         return howmany;
1619 }
1620
1621 static void gfar_schedule_cleanup(struct net_device *dev)
1622 {
1623         struct gfar_private *priv = netdev_priv(dev);
1624         unsigned long flags;
1625
1626         spin_lock_irqsave(&priv->txlock, flags);
1627         spin_lock(&priv->rxlock);
1628
1629         if (netif_rx_schedule_prep(&priv->napi)) {
1630                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1631                 __netif_rx_schedule(&priv->napi);
1632         }
1633
1634         spin_unlock(&priv->rxlock);
1635         spin_unlock_irqrestore(&priv->txlock, flags);
1636 }
1637
1638 /* Interrupt Handler for Transmit complete */
1639 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1640 {
1641         gfar_schedule_cleanup((struct net_device *)dev_id);
1642         return IRQ_HANDLED;
1643 }
1644
1645 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1646                 struct sk_buff *skb)
1647 {
1648         struct gfar_private *priv = netdev_priv(dev);
1649         u32 lstatus;
1650
1651         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1652                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1653
1654         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1655
1656         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1657                 lstatus |= BD_LFLAG(RXBD_WRAP);
1658
1659         eieio();
1660
1661         bdp->lstatus = lstatus;
1662 }
1663
1664
1665 struct sk_buff * gfar_new_skb(struct net_device *dev)
1666 {
1667         unsigned int alignamount;
1668         struct gfar_private *priv = netdev_priv(dev);
1669         struct sk_buff *skb = NULL;
1670
1671         /* We have to allocate the skb, so keep trying till we succeed */
1672         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1673
1674         if (!skb)
1675                 return NULL;
1676
1677         alignamount = RXBUF_ALIGNMENT -
1678                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1679
1680         /* We need the data buffer to be aligned properly.  We will reserve
1681          * as many bytes as needed to align the data properly
1682          */
1683         skb_reserve(skb, alignamount);
1684
1685         return skb;
1686 }
1687
1688 static inline void count_errors(unsigned short status, struct net_device *dev)
1689 {
1690         struct gfar_private *priv = netdev_priv(dev);
1691         struct net_device_stats *stats = &dev->stats;
1692         struct gfar_extra_stats *estats = &priv->extra_stats;
1693
1694         /* If the packet was truncated, none of the other errors
1695          * matter */
1696         if (status & RXBD_TRUNCATED) {
1697                 stats->rx_length_errors++;
1698
1699                 estats->rx_trunc++;
1700
1701                 return;
1702         }
1703         /* Count the errors, if there were any */
1704         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1705                 stats->rx_length_errors++;
1706
1707                 if (status & RXBD_LARGE)
1708                         estats->rx_large++;
1709                 else
1710                         estats->rx_short++;
1711         }
1712         if (status & RXBD_NONOCTET) {
1713                 stats->rx_frame_errors++;
1714                 estats->rx_nonoctet++;
1715         }
1716         if (status & RXBD_CRCERR) {
1717                 estats->rx_crcerr++;
1718                 stats->rx_crc_errors++;
1719         }
1720         if (status & RXBD_OVERRUN) {
1721                 estats->rx_overrun++;
1722                 stats->rx_crc_errors++;
1723         }
1724 }
1725
1726 irqreturn_t gfar_receive(int irq, void *dev_id)
1727 {
1728         gfar_schedule_cleanup((struct net_device *)dev_id);
1729         return IRQ_HANDLED;
1730 }
1731
1732 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1733 {
1734         /* If valid headers were found, and valid sums
1735          * were verified, then we tell the kernel that no
1736          * checksumming is necessary.  Otherwise, it is */
1737         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1738                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1739         else
1740                 skb->ip_summed = CHECKSUM_NONE;
1741 }
1742
1743
1744 /* gfar_process_frame() -- handle one incoming packet if skb
1745  * isn't NULL.  */
1746 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1747                               int amount_pull)
1748 {
1749         struct gfar_private *priv = netdev_priv(dev);
1750         struct rxfcb *fcb = NULL;
1751
1752         int ret;
1753
1754         /* fcb is at the beginning if exists */
1755         fcb = (struct rxfcb *)skb->data;
1756
1757         /* Remove the FCB from the skb */
1758         /* Remove the padded bytes, if there are any */
1759         if (amount_pull)
1760                 skb_pull(skb, amount_pull);
1761
1762         if (priv->rx_csum_enable)
1763                 gfar_rx_checksum(skb, fcb);
1764
1765         /* Tell the skb what kind of packet this is */
1766         skb->protocol = eth_type_trans(skb, dev);
1767
1768         /* Send the packet up the stack */
1769         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1770                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1771         else
1772                 ret = netif_receive_skb(skb);
1773
1774         if (NET_RX_DROP == ret)
1775                 priv->extra_stats.kernel_dropped++;
1776
1777         return 0;
1778 }
1779
1780 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1781  *   until the budget/quota has been reached. Returns the number
1782  *   of frames handled
1783  */
1784 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1785 {
1786         struct rxbd8 *bdp, *base;
1787         struct sk_buff *skb;
1788         int pkt_len;
1789         int amount_pull;
1790         int howmany = 0;
1791         struct gfar_private *priv = netdev_priv(dev);
1792
1793         /* Get the first full descriptor */
1794         bdp = priv->cur_rx;
1795         base = priv->rx_bd_base;
1796
1797         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1798                 priv->padding;
1799
1800         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1801                 struct sk_buff *newskb;
1802                 rmb();
1803
1804                 /* Add another skb for the future */
1805                 newskb = gfar_new_skb(dev);
1806
1807                 skb = priv->rx_skbuff[priv->skb_currx];
1808
1809                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1810                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1811
1812                 /* We drop the frame if we failed to allocate a new buffer */
1813                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1814                                  bdp->status & RXBD_ERR)) {
1815                         count_errors(bdp->status, dev);
1816
1817                         if (unlikely(!newskb))
1818                                 newskb = skb;
1819                         else if (skb)
1820                                 dev_kfree_skb_any(skb);
1821                 } else {
1822                         /* Increment the number of packets */
1823                         dev->stats.rx_packets++;
1824                         howmany++;
1825
1826                         if (likely(skb)) {
1827                                 pkt_len = bdp->length - ETH_FCS_LEN;
1828                                 /* Remove the FCS from the packet length */
1829                                 skb_put(skb, pkt_len);
1830                                 dev->stats.rx_bytes += pkt_len;
1831
1832                                 gfar_process_frame(dev, skb, amount_pull);
1833
1834                         } else {
1835                                 if (netif_msg_rx_err(priv))
1836                                         printk(KERN_WARNING
1837                                                "%s: Missing skb!\n", dev->name);
1838                                 dev->stats.rx_dropped++;
1839                                 priv->extra_stats.rx_skbmissing++;
1840                         }
1841
1842                 }
1843
1844                 priv->rx_skbuff[priv->skb_currx] = newskb;
1845
1846                 /* Setup the new bdp */
1847                 gfar_new_rxbdp(dev, bdp, newskb);
1848
1849                 /* Update to the next pointer */
1850                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1851
1852                 /* update to point at the next skb */
1853                 priv->skb_currx =
1854                     (priv->skb_currx + 1) &
1855                     RX_RING_MOD_MASK(priv->rx_ring_size);
1856         }
1857
1858         /* Update the current rxbd pointer to be the next one */
1859         priv->cur_rx = bdp;
1860
1861         return howmany;
1862 }
1863
1864 static int gfar_poll(struct napi_struct *napi, int budget)
1865 {
1866         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1867         struct net_device *dev = priv->dev;
1868         int tx_cleaned = 0;
1869         int rx_cleaned = 0;
1870         unsigned long flags;
1871
1872         /* Clear IEVENT, so interrupts aren't called again
1873          * because of the packets that have already arrived */
1874         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1875
1876         /* If we fail to get the lock, don't bother with the TX BDs */
1877         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1878                 tx_cleaned = gfar_clean_tx_ring(dev);
1879                 spin_unlock_irqrestore(&priv->txlock, flags);
1880         }
1881
1882         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1883
1884         if (tx_cleaned)
1885                 return budget;
1886
1887         if (rx_cleaned < budget) {
1888                 netif_rx_complete(napi);
1889
1890                 /* Clear the halt bit in RSTAT */
1891                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1892
1893                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1894
1895                 /* If we are coalescing interrupts, update the timer */
1896                 /* Otherwise, clear it */
1897                 if (likely(priv->rxcoalescing)) {
1898                         gfar_write(&priv->regs->rxic, 0);
1899                         gfar_write(&priv->regs->rxic, priv->rxic);
1900                 }
1901                 if (likely(priv->txcoalescing)) {
1902                         gfar_write(&priv->regs->txic, 0);
1903                         gfar_write(&priv->regs->txic, priv->txic);
1904                 }
1905         }
1906
1907         return rx_cleaned;
1908 }
1909
1910 #ifdef CONFIG_NET_POLL_CONTROLLER
1911 /*
1912  * Polling 'interrupt' - used by things like netconsole to send skbs
1913  * without having to re-enable interrupts. It's not called while
1914  * the interrupt routine is executing.
1915  */
1916 static void gfar_netpoll(struct net_device *dev)
1917 {
1918         struct gfar_private *priv = netdev_priv(dev);
1919
1920         /* If the device has multiple interrupts, run tx/rx */
1921         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1922                 disable_irq(priv->interruptTransmit);
1923                 disable_irq(priv->interruptReceive);
1924                 disable_irq(priv->interruptError);
1925                 gfar_interrupt(priv->interruptTransmit, dev);
1926                 enable_irq(priv->interruptError);
1927                 enable_irq(priv->interruptReceive);
1928                 enable_irq(priv->interruptTransmit);
1929         } else {
1930                 disable_irq(priv->interruptTransmit);
1931                 gfar_interrupt(priv->interruptTransmit, dev);
1932                 enable_irq(priv->interruptTransmit);
1933         }
1934 }
1935 #endif
1936
1937 /* The interrupt handler for devices with one interrupt */
1938 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1939 {
1940         struct net_device *dev = dev_id;
1941         struct gfar_private *priv = netdev_priv(dev);
1942
1943         /* Save ievent for future reference */
1944         u32 events = gfar_read(&priv->regs->ievent);
1945
1946         /* Check for reception */
1947         if (events & IEVENT_RX_MASK)
1948                 gfar_receive(irq, dev_id);
1949
1950         /* Check for transmit completion */
1951         if (events & IEVENT_TX_MASK)
1952                 gfar_transmit(irq, dev_id);
1953
1954         /* Check for errors */
1955         if (events & IEVENT_ERR_MASK)
1956                 gfar_error(irq, dev_id);
1957
1958         return IRQ_HANDLED;
1959 }
1960
1961 /* Called every time the controller might need to be made
1962  * aware of new link state.  The PHY code conveys this
1963  * information through variables in the phydev structure, and this
1964  * function converts those variables into the appropriate
1965  * register values, and can bring down the device if needed.
1966  */
1967 static void adjust_link(struct net_device *dev)
1968 {
1969         struct gfar_private *priv = netdev_priv(dev);
1970         struct gfar __iomem *regs = priv->regs;
1971         unsigned long flags;
1972         struct phy_device *phydev = priv->phydev;
1973         int new_state = 0;
1974
1975         spin_lock_irqsave(&priv->txlock, flags);
1976         if (phydev->link) {
1977                 u32 tempval = gfar_read(&regs->maccfg2);
1978                 u32 ecntrl = gfar_read(&regs->ecntrl);
1979
1980                 /* Now we make sure that we can be in full duplex mode.
1981                  * If not, we operate in half-duplex mode. */
1982                 if (phydev->duplex != priv->oldduplex) {
1983                         new_state = 1;
1984                         if (!(phydev->duplex))
1985                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1986                         else
1987                                 tempval |= MACCFG2_FULL_DUPLEX;
1988
1989                         priv->oldduplex = phydev->duplex;
1990                 }
1991
1992                 if (phydev->speed != priv->oldspeed) {
1993                         new_state = 1;
1994                         switch (phydev->speed) {
1995                         case 1000:
1996                                 tempval =
1997                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1998
1999                                 ecntrl &= ~(ECNTRL_R100);
2000                                 break;
2001                         case 100:
2002                         case 10:
2003                                 tempval =
2004                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2005
2006                                 /* Reduced mode distinguishes
2007                                  * between 10 and 100 */
2008                                 if (phydev->speed == SPEED_100)
2009                                         ecntrl |= ECNTRL_R100;
2010                                 else
2011                                         ecntrl &= ~(ECNTRL_R100);
2012                                 break;
2013                         default:
2014                                 if (netif_msg_link(priv))
2015                                         printk(KERN_WARNING
2016                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2017                                                 dev->name, phydev->speed);
2018                                 break;
2019                         }
2020
2021                         priv->oldspeed = phydev->speed;
2022                 }
2023
2024                 gfar_write(&regs->maccfg2, tempval);
2025                 gfar_write(&regs->ecntrl, ecntrl);
2026
2027                 if (!priv->oldlink) {
2028                         new_state = 1;
2029                         priv->oldlink = 1;
2030                 }
2031         } else if (priv->oldlink) {
2032                 new_state = 1;
2033                 priv->oldlink = 0;
2034                 priv->oldspeed = 0;
2035                 priv->oldduplex = -1;
2036         }
2037
2038         if (new_state && netif_msg_link(priv))
2039                 phy_print_status(phydev);
2040
2041         spin_unlock_irqrestore(&priv->txlock, flags);
2042 }
2043
2044 /* Update the hash table based on the current list of multicast
2045  * addresses we subscribe to.  Also, change the promiscuity of
2046  * the device based on the flags (this function is called
2047  * whenever dev->flags is changed */
2048 static void gfar_set_multi(struct net_device *dev)
2049 {
2050         struct dev_mc_list *mc_ptr;
2051         struct gfar_private *priv = netdev_priv(dev);
2052         struct gfar __iomem *regs = priv->regs;
2053         u32 tempval;
2054
2055         if(dev->flags & IFF_PROMISC) {
2056                 /* Set RCTRL to PROM */
2057                 tempval = gfar_read(&regs->rctrl);
2058                 tempval |= RCTRL_PROM;
2059                 gfar_write(&regs->rctrl, tempval);
2060         } else {
2061                 /* Set RCTRL to not PROM */
2062                 tempval = gfar_read(&regs->rctrl);
2063                 tempval &= ~(RCTRL_PROM);
2064                 gfar_write(&regs->rctrl, tempval);
2065         }
2066
2067         if(dev->flags & IFF_ALLMULTI) {
2068                 /* Set the hash to rx all multicast frames */
2069                 gfar_write(&regs->igaddr0, 0xffffffff);
2070                 gfar_write(&regs->igaddr1, 0xffffffff);
2071                 gfar_write(&regs->igaddr2, 0xffffffff);
2072                 gfar_write(&regs->igaddr3, 0xffffffff);
2073                 gfar_write(&regs->igaddr4, 0xffffffff);
2074                 gfar_write(&regs->igaddr5, 0xffffffff);
2075                 gfar_write(&regs->igaddr6, 0xffffffff);
2076                 gfar_write(&regs->igaddr7, 0xffffffff);
2077                 gfar_write(&regs->gaddr0, 0xffffffff);
2078                 gfar_write(&regs->gaddr1, 0xffffffff);
2079                 gfar_write(&regs->gaddr2, 0xffffffff);
2080                 gfar_write(&regs->gaddr3, 0xffffffff);
2081                 gfar_write(&regs->gaddr4, 0xffffffff);
2082                 gfar_write(&regs->gaddr5, 0xffffffff);
2083                 gfar_write(&regs->gaddr6, 0xffffffff);
2084                 gfar_write(&regs->gaddr7, 0xffffffff);
2085         } else {
2086                 int em_num;
2087                 int idx;
2088
2089                 /* zero out the hash */
2090                 gfar_write(&regs->igaddr0, 0x0);
2091                 gfar_write(&regs->igaddr1, 0x0);
2092                 gfar_write(&regs->igaddr2, 0x0);
2093                 gfar_write(&regs->igaddr3, 0x0);
2094                 gfar_write(&regs->igaddr4, 0x0);
2095                 gfar_write(&regs->igaddr5, 0x0);
2096                 gfar_write(&regs->igaddr6, 0x0);
2097                 gfar_write(&regs->igaddr7, 0x0);
2098                 gfar_write(&regs->gaddr0, 0x0);
2099                 gfar_write(&regs->gaddr1, 0x0);
2100                 gfar_write(&regs->gaddr2, 0x0);
2101                 gfar_write(&regs->gaddr3, 0x0);
2102                 gfar_write(&regs->gaddr4, 0x0);
2103                 gfar_write(&regs->gaddr5, 0x0);
2104                 gfar_write(&regs->gaddr6, 0x0);
2105                 gfar_write(&regs->gaddr7, 0x0);
2106
2107                 /* If we have extended hash tables, we need to
2108                  * clear the exact match registers to prepare for
2109                  * setting them */
2110                 if (priv->extended_hash) {
2111                         em_num = GFAR_EM_NUM + 1;
2112                         gfar_clear_exact_match(dev);
2113                         idx = 1;
2114                 } else {
2115                         idx = 0;
2116                         em_num = 0;
2117                 }
2118
2119                 if(dev->mc_count == 0)
2120                         return;
2121
2122                 /* Parse the list, and set the appropriate bits */
2123                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2124                         if (idx < em_num) {
2125                                 gfar_set_mac_for_addr(dev, idx,
2126                                                 mc_ptr->dmi_addr);
2127                                 idx++;
2128                         } else
2129                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2130                 }
2131         }
2132
2133         return;
2134 }
2135
2136
2137 /* Clears each of the exact match registers to zero, so they
2138  * don't interfere with normal reception */
2139 static void gfar_clear_exact_match(struct net_device *dev)
2140 {
2141         int idx;
2142         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2143
2144         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2145                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2146 }
2147
2148 /* Set the appropriate hash bit for the given addr */
2149 /* The algorithm works like so:
2150  * 1) Take the Destination Address (ie the multicast address), and
2151  * do a CRC on it (little endian), and reverse the bits of the
2152  * result.
2153  * 2) Use the 8 most significant bits as a hash into a 256-entry
2154  * table.  The table is controlled through 8 32-bit registers:
2155  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2156  * gaddr7.  This means that the 3 most significant bits in the
2157  * hash index which gaddr register to use, and the 5 other bits
2158  * indicate which bit (assuming an IBM numbering scheme, which
2159  * for PowerPC (tm) is usually the case) in the register holds
2160  * the entry. */
2161 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2162 {
2163         u32 tempval;
2164         struct gfar_private *priv = netdev_priv(dev);
2165         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2166         int width = priv->hash_width;
2167         u8 whichbit = (result >> (32 - width)) & 0x1f;
2168         u8 whichreg = result >> (32 - width + 5);
2169         u32 value = (1 << (31-whichbit));
2170
2171         tempval = gfar_read(priv->hash_regs[whichreg]);
2172         tempval |= value;
2173         gfar_write(priv->hash_regs[whichreg], tempval);
2174
2175         return;
2176 }
2177
2178
2179 /* There are multiple MAC Address register pairs on some controllers
2180  * This function sets the numth pair to a given address
2181  */
2182 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2183 {
2184         struct gfar_private *priv = netdev_priv(dev);
2185         int idx;
2186         char tmpbuf[MAC_ADDR_LEN];
2187         u32 tempval;
2188         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2189
2190         macptr += num*2;
2191
2192         /* Now copy it into the mac registers backwards, cuz */
2193         /* little endian is silly */
2194         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2195                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2196
2197         gfar_write(macptr, *((u32 *) (tmpbuf)));
2198
2199         tempval = *((u32 *) (tmpbuf + 4));
2200
2201         gfar_write(macptr+1, tempval);
2202 }
2203
2204 /* GFAR error interrupt handler */
2205 static irqreturn_t gfar_error(int irq, void *dev_id)
2206 {
2207         struct net_device *dev = dev_id;
2208         struct gfar_private *priv = netdev_priv(dev);
2209
2210         /* Save ievent for future reference */
2211         u32 events = gfar_read(&priv->regs->ievent);
2212
2213         /* Clear IEVENT */
2214         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2215
2216         /* Magic Packet is not an error. */
2217         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2218             (events & IEVENT_MAG))
2219                 events &= ~IEVENT_MAG;
2220
2221         /* Hmm... */
2222         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2223                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2224                        dev->name, events, gfar_read(&priv->regs->imask));
2225
2226         /* Update the error counters */
2227         if (events & IEVENT_TXE) {
2228                 dev->stats.tx_errors++;
2229
2230                 if (events & IEVENT_LC)
2231                         dev->stats.tx_window_errors++;
2232                 if (events & IEVENT_CRL)
2233                         dev->stats.tx_aborted_errors++;
2234                 if (events & IEVENT_XFUN) {
2235                         if (netif_msg_tx_err(priv))
2236                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2237                                        "packet dropped.\n", dev->name);
2238                         dev->stats.tx_dropped++;
2239                         priv->extra_stats.tx_underrun++;
2240
2241                         /* Reactivate the Tx Queues */
2242                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2243                 }
2244                 if (netif_msg_tx_err(priv))
2245                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2246         }
2247         if (events & IEVENT_BSY) {
2248                 dev->stats.rx_errors++;
2249                 priv->extra_stats.rx_bsy++;
2250
2251                 gfar_receive(irq, dev_id);
2252
2253                 if (netif_msg_rx_err(priv))
2254                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2255                                dev->name, gfar_read(&priv->regs->rstat));
2256         }
2257         if (events & IEVENT_BABR) {
2258                 dev->stats.rx_errors++;
2259                 priv->extra_stats.rx_babr++;
2260
2261                 if (netif_msg_rx_err(priv))
2262                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2263         }
2264         if (events & IEVENT_EBERR) {
2265                 priv->extra_stats.eberr++;
2266                 if (netif_msg_rx_err(priv))
2267                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2268         }
2269         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2270                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2271
2272         if (events & IEVENT_BABT) {
2273                 priv->extra_stats.tx_babt++;
2274                 if (netif_msg_tx_err(priv))
2275                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2276         }
2277         return IRQ_HANDLED;
2278 }
2279
2280 /* work with hotplug and coldplug */
2281 MODULE_ALIAS("platform:fsl-gianfar");
2282
2283 static struct of_device_id gfar_match[] =
2284 {
2285         {
2286                 .type = "network",
2287                 .compatible = "gianfar",
2288         },
2289         {},
2290 };
2291
2292 /* Structure for a device driver */
2293 static struct of_platform_driver gfar_driver = {
2294         .name = "fsl-gianfar",
2295         .match_table = gfar_match,
2296
2297         .probe = gfar_probe,
2298         .remove = gfar_remove,
2299         .suspend = gfar_suspend,
2300         .resume = gfar_resume,
2301 };
2302
2303 static int __init gfar_init(void)
2304 {
2305         int err = gfar_mdio_init();
2306
2307         if (err)
2308                 return err;
2309
2310         err = of_register_platform_driver(&gfar_driver);
2311
2312         if (err)
2313                 gfar_mdio_exit();
2314
2315         return err;
2316 }
2317
2318 static void __exit gfar_exit(void)
2319 {
2320         of_unregister_platform_driver(&gfar_driver);
2321         gfar_mdio_exit();
2322 }
2323
2324 module_init(gfar_init);
2325 module_exit(gfar_exit);
2326