gianfar: Optimize interrupt coalescing configuration
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "gianfar_mii.h"
97
98 #define TX_TIMEOUT      (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112                 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122                 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
135 static void gfar_vlan_rx_register(struct net_device *netdev,
136                                 struct vlan_group *grp);
137 void gfar_halt(struct net_device *dev);
138 static void gfar_halt_nodisable(struct net_device *dev);
139 void gfar_start(struct net_device *dev);
140 static void gfar_clear_exact_match(struct net_device *dev);
141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
142
143 extern const struct ethtool_ops gfar_ethtool_ops;
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 /* Returns 1 if incoming frames use an FCB */
150 static inline int gfar_uses_fcb(struct gfar_private *priv)
151 {
152         return (priv->vlan_enable || priv->rx_csum_enable);
153 }
154
155 static int gfar_of_init(struct net_device *dev)
156 {
157         struct device_node *phy, *mdio;
158         const unsigned int *id;
159         const char *model;
160         const char *ctype;
161         const void *mac_addr;
162         const phandle *ph;
163         u64 addr, size;
164         int err = 0;
165         struct gfar_private *priv = netdev_priv(dev);
166         struct device_node *np = priv->node;
167         char bus_name[MII_BUS_ID_SIZE];
168
169         if (!np || !of_device_is_available(np))
170                 return -ENODEV;
171
172         /* get a pointer to the register memory */
173         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
174         priv->regs = ioremap(addr, size);
175
176         if (priv->regs == NULL)
177                 return -ENOMEM;
178
179         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
180
181         model = of_get_property(np, "model", NULL);
182
183         /* If we aren't the FEC we have multiple interrupts */
184         if (model && strcasecmp(model, "FEC")) {
185                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
186
187                 priv->interruptError = irq_of_parse_and_map(np, 2);
188
189                 if (priv->interruptTransmit < 0 ||
190                                 priv->interruptReceive < 0 ||
191                                 priv->interruptError < 0) {
192                         err = -EINVAL;
193                         goto err_out;
194                 }
195         }
196
197         mac_addr = of_get_mac_address(np);
198         if (mac_addr)
199                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
200
201         if (model && !strcasecmp(model, "TSEC"))
202                 priv->device_flags =
203                         FSL_GIANFAR_DEV_HAS_GIGABIT |
204                         FSL_GIANFAR_DEV_HAS_COALESCE |
205                         FSL_GIANFAR_DEV_HAS_RMON |
206                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
207         if (model && !strcasecmp(model, "eTSEC"))
208                 priv->device_flags =
209                         FSL_GIANFAR_DEV_HAS_GIGABIT |
210                         FSL_GIANFAR_DEV_HAS_COALESCE |
211                         FSL_GIANFAR_DEV_HAS_RMON |
212                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
213                         FSL_GIANFAR_DEV_HAS_CSUM |
214                         FSL_GIANFAR_DEV_HAS_VLAN |
215                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
216                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
217
218         ctype = of_get_property(np, "phy-connection-type", NULL);
219
220         /* We only care about rgmii-id.  The rest are autodetected */
221         if (ctype && !strcmp(ctype, "rgmii-id"))
222                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
223         else
224                 priv->interface = PHY_INTERFACE_MODE_MII;
225
226         if (of_get_property(np, "fsl,magic-packet", NULL))
227                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
228
229         ph = of_get_property(np, "phy-handle", NULL);
230         if (ph == NULL) {
231                 u32 *fixed_link;
232
233                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
234                 if (!fixed_link) {
235                         err = -ENODEV;
236                         goto err_out;
237                 }
238
239                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, PHY_ID_FMT, "0",
240                                 fixed_link[0]);
241         } else {
242                 phy = of_find_node_by_phandle(*ph);
243
244                 if (phy == NULL) {
245                         err = -ENODEV;
246                         goto err_out;
247                 }
248
249                 mdio = of_get_parent(phy);
250
251                 id = of_get_property(phy, "reg", NULL);
252
253                 of_node_put(phy);
254                 of_node_put(mdio);
255
256                 gfar_mdio_bus_name(bus_name, mdio);
257                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, "%s:%02x",
258                                 bus_name, *id);
259         }
260
261         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
262         ph = of_get_property(np, "tbi-handle", NULL);
263         if (ph) {
264                 struct device_node *tbi = of_find_node_by_phandle(*ph);
265                 struct of_device *ofdev;
266                 struct mii_bus *bus;
267
268                 if (!tbi)
269                         return 0;
270
271                 mdio = of_get_parent(tbi);
272                 if (!mdio)
273                         return 0;
274
275                 ofdev = of_find_device_by_node(mdio);
276
277                 of_node_put(mdio);
278
279                 id = of_get_property(tbi, "reg", NULL);
280                 if (!id)
281                         return 0;
282
283                 of_node_put(tbi);
284
285                 bus = dev_get_drvdata(&ofdev->dev);
286
287                 priv->tbiphy = bus->phy_map[*id];
288         }
289
290         return 0;
291
292 err_out:
293         iounmap(priv->regs);
294         return err;
295 }
296
297 /* Set up the ethernet device structure, private data,
298  * and anything else we need before we start */
299 static int gfar_probe(struct of_device *ofdev,
300                 const struct of_device_id *match)
301 {
302         u32 tempval;
303         struct net_device *dev = NULL;
304         struct gfar_private *priv = NULL;
305         int err = 0;
306         DECLARE_MAC_BUF(mac);
307
308         /* Create an ethernet device instance */
309         dev = alloc_etherdev(sizeof (*priv));
310
311         if (NULL == dev)
312                 return -ENOMEM;
313
314         priv = netdev_priv(dev);
315         priv->dev = dev;
316         priv->node = ofdev->node;
317
318         err = gfar_of_init(dev);
319
320         if (err)
321                 goto regs_fail;
322
323         spin_lock_init(&priv->txlock);
324         spin_lock_init(&priv->rxlock);
325         spin_lock_init(&priv->bflock);
326         INIT_WORK(&priv->reset_task, gfar_reset_task);
327
328         dev_set_drvdata(&ofdev->dev, priv);
329
330         /* Stop the DMA engine now, in case it was running before */
331         /* (The firmware could have used it, and left it running). */
332         gfar_halt(dev);
333
334         /* Reset MAC layer */
335         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
336
337         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
338         gfar_write(&priv->regs->maccfg1, tempval);
339
340         /* Initialize MACCFG2. */
341         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
342
343         /* Initialize ECNTRL */
344         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
345
346         /* Set the dev->base_addr to the gfar reg region */
347         dev->base_addr = (unsigned long) (priv->regs);
348
349         SET_NETDEV_DEV(dev, &ofdev->dev);
350
351         /* Fill in the dev structure */
352         dev->open = gfar_enet_open;
353         dev->hard_start_xmit = gfar_start_xmit;
354         dev->tx_timeout = gfar_timeout;
355         dev->watchdog_timeo = TX_TIMEOUT;
356         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
357 #ifdef CONFIG_NET_POLL_CONTROLLER
358         dev->poll_controller = gfar_netpoll;
359 #endif
360         dev->stop = gfar_close;
361         dev->change_mtu = gfar_change_mtu;
362         dev->mtu = 1500;
363         dev->set_multicast_list = gfar_set_multi;
364
365         dev->ethtool_ops = &gfar_ethtool_ops;
366
367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
368                 priv->rx_csum_enable = 1;
369                 dev->features |= NETIF_F_IP_CSUM;
370         } else
371                 priv->rx_csum_enable = 0;
372
373         priv->vlgrp = NULL;
374
375         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
376                 dev->vlan_rx_register = gfar_vlan_rx_register;
377
378                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
379
380                 priv->vlan_enable = 1;
381         }
382
383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
384                 priv->extended_hash = 1;
385                 priv->hash_width = 9;
386
387                 priv->hash_regs[0] = &priv->regs->igaddr0;
388                 priv->hash_regs[1] = &priv->regs->igaddr1;
389                 priv->hash_regs[2] = &priv->regs->igaddr2;
390                 priv->hash_regs[3] = &priv->regs->igaddr3;
391                 priv->hash_regs[4] = &priv->regs->igaddr4;
392                 priv->hash_regs[5] = &priv->regs->igaddr5;
393                 priv->hash_regs[6] = &priv->regs->igaddr6;
394                 priv->hash_regs[7] = &priv->regs->igaddr7;
395                 priv->hash_regs[8] = &priv->regs->gaddr0;
396                 priv->hash_regs[9] = &priv->regs->gaddr1;
397                 priv->hash_regs[10] = &priv->regs->gaddr2;
398                 priv->hash_regs[11] = &priv->regs->gaddr3;
399                 priv->hash_regs[12] = &priv->regs->gaddr4;
400                 priv->hash_regs[13] = &priv->regs->gaddr5;
401                 priv->hash_regs[14] = &priv->regs->gaddr6;
402                 priv->hash_regs[15] = &priv->regs->gaddr7;
403
404         } else {
405                 priv->extended_hash = 0;
406                 priv->hash_width = 8;
407
408                 priv->hash_regs[0] = &priv->regs->gaddr0;
409                 priv->hash_regs[1] = &priv->regs->gaddr1;
410                 priv->hash_regs[2] = &priv->regs->gaddr2;
411                 priv->hash_regs[3] = &priv->regs->gaddr3;
412                 priv->hash_regs[4] = &priv->regs->gaddr4;
413                 priv->hash_regs[5] = &priv->regs->gaddr5;
414                 priv->hash_regs[6] = &priv->regs->gaddr6;
415                 priv->hash_regs[7] = &priv->regs->gaddr7;
416         }
417
418         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
419                 priv->padding = DEFAULT_PADDING;
420         else
421                 priv->padding = 0;
422
423         if (dev->features & NETIF_F_IP_CSUM)
424                 dev->hard_header_len += GMAC_FCB_LEN;
425
426         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
427         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
428         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
429
430         priv->txcoalescing = DEFAULT_TX_COALESCE;
431         priv->txic = DEFAULT_TXIC;
432         priv->rxcoalescing = DEFAULT_RX_COALESCE;
433         priv->rxic = DEFAULT_RXIC;
434
435         /* Enable most messages by default */
436         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
437
438         /* Carrier starts down, phylib will bring it up */
439         netif_carrier_off(dev);
440
441         err = register_netdev(dev);
442
443         if (err) {
444                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
445                                 dev->name);
446                 goto register_fail;
447         }
448
449         /* Create all the sysfs files */
450         gfar_init_sysfs(dev);
451
452         /* Print out the device info */
453         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
454
455         /* Even more device info helps when determining which kernel */
456         /* provided which set of benchmarks. */
457         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
458         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
459                dev->name, priv->rx_ring_size, priv->tx_ring_size);
460
461         return 0;
462
463 register_fail:
464         iounmap(priv->regs);
465 regs_fail:
466         free_netdev(dev);
467         return err;
468 }
469
470 static int gfar_remove(struct of_device *ofdev)
471 {
472         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
473
474         dev_set_drvdata(&ofdev->dev, NULL);
475
476         iounmap(priv->regs);
477         free_netdev(priv->dev);
478
479         return 0;
480 }
481
482 #ifdef CONFIG_PM
483 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
484 {
485         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
486         struct net_device *dev = priv->dev;
487         unsigned long flags;
488         u32 tempval;
489
490         int magic_packet = priv->wol_en &&
491                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
492
493         netif_device_detach(dev);
494
495         if (netif_running(dev)) {
496                 spin_lock_irqsave(&priv->txlock, flags);
497                 spin_lock(&priv->rxlock);
498
499                 gfar_halt_nodisable(dev);
500
501                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
502                 tempval = gfar_read(&priv->regs->maccfg1);
503
504                 tempval &= ~MACCFG1_TX_EN;
505
506                 if (!magic_packet)
507                         tempval &= ~MACCFG1_RX_EN;
508
509                 gfar_write(&priv->regs->maccfg1, tempval);
510
511                 spin_unlock(&priv->rxlock);
512                 spin_unlock_irqrestore(&priv->txlock, flags);
513
514                 napi_disable(&priv->napi);
515
516                 if (magic_packet) {
517                         /* Enable interrupt on Magic Packet */
518                         gfar_write(&priv->regs->imask, IMASK_MAG);
519
520                         /* Enable Magic Packet mode */
521                         tempval = gfar_read(&priv->regs->maccfg2);
522                         tempval |= MACCFG2_MPEN;
523                         gfar_write(&priv->regs->maccfg2, tempval);
524                 } else {
525                         phy_stop(priv->phydev);
526                 }
527         }
528
529         return 0;
530 }
531
532 static int gfar_resume(struct of_device *ofdev)
533 {
534         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
535         struct net_device *dev = priv->dev;
536         unsigned long flags;
537         u32 tempval;
538         int magic_packet = priv->wol_en &&
539                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
540
541         if (!netif_running(dev)) {
542                 netif_device_attach(dev);
543                 return 0;
544         }
545
546         if (!magic_packet && priv->phydev)
547                 phy_start(priv->phydev);
548
549         /* Disable Magic Packet mode, in case something
550          * else woke us up.
551          */
552
553         spin_lock_irqsave(&priv->txlock, flags);
554         spin_lock(&priv->rxlock);
555
556         tempval = gfar_read(&priv->regs->maccfg2);
557         tempval &= ~MACCFG2_MPEN;
558         gfar_write(&priv->regs->maccfg2, tempval);
559
560         gfar_start(dev);
561
562         spin_unlock(&priv->rxlock);
563         spin_unlock_irqrestore(&priv->txlock, flags);
564
565         netif_device_attach(dev);
566
567         napi_enable(&priv->napi);
568
569         return 0;
570 }
571 #else
572 #define gfar_suspend NULL
573 #define gfar_resume NULL
574 #endif
575
576 /* Reads the controller's registers to determine what interface
577  * connects it to the PHY.
578  */
579 static phy_interface_t gfar_get_interface(struct net_device *dev)
580 {
581         struct gfar_private *priv = netdev_priv(dev);
582         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
583
584         if (ecntrl & ECNTRL_SGMII_MODE)
585                 return PHY_INTERFACE_MODE_SGMII;
586
587         if (ecntrl & ECNTRL_TBI_MODE) {
588                 if (ecntrl & ECNTRL_REDUCED_MODE)
589                         return PHY_INTERFACE_MODE_RTBI;
590                 else
591                         return PHY_INTERFACE_MODE_TBI;
592         }
593
594         if (ecntrl & ECNTRL_REDUCED_MODE) {
595                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
596                         return PHY_INTERFACE_MODE_RMII;
597                 else {
598                         phy_interface_t interface = priv->interface;
599
600                         /*
601                          * This isn't autodetected right now, so it must
602                          * be set by the device tree or platform code.
603                          */
604                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
605                                 return PHY_INTERFACE_MODE_RGMII_ID;
606
607                         return PHY_INTERFACE_MODE_RGMII;
608                 }
609         }
610
611         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
612                 return PHY_INTERFACE_MODE_GMII;
613
614         return PHY_INTERFACE_MODE_MII;
615 }
616
617
618 /* Initializes driver's PHY state, and attaches to the PHY.
619  * Returns 0 on success.
620  */
621 static int init_phy(struct net_device *dev)
622 {
623         struct gfar_private *priv = netdev_priv(dev);
624         uint gigabit_support =
625                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
626                 SUPPORTED_1000baseT_Full : 0;
627         struct phy_device *phydev;
628         phy_interface_t interface;
629
630         priv->oldlink = 0;
631         priv->oldspeed = 0;
632         priv->oldduplex = -1;
633
634         interface = gfar_get_interface(dev);
635
636         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
637
638         if (interface == PHY_INTERFACE_MODE_SGMII)
639                 gfar_configure_serdes(dev);
640
641         if (IS_ERR(phydev)) {
642                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
643                 return PTR_ERR(phydev);
644         }
645
646         /* Remove any features not supported by the controller */
647         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
648         phydev->advertising = phydev->supported;
649
650         priv->phydev = phydev;
651
652         return 0;
653 }
654
655 /*
656  * Initialize TBI PHY interface for communicating with the
657  * SERDES lynx PHY on the chip.  We communicate with this PHY
658  * through the MDIO bus on each controller, treating it as a
659  * "normal" PHY at the address found in the TBIPA register.  We assume
660  * that the TBIPA register is valid.  Either the MDIO bus code will set
661  * it to a value that doesn't conflict with other PHYs on the bus, or the
662  * value doesn't matter, as there are no other PHYs on the bus.
663  */
664 static void gfar_configure_serdes(struct net_device *dev)
665 {
666         struct gfar_private *priv = netdev_priv(dev);
667
668         if (!priv->tbiphy) {
669                 printk(KERN_WARNING "SGMII mode requires that the device "
670                                 "tree specify a tbi-handle\n");
671                 return;
672         }
673
674         /*
675          * If the link is already up, we must already be ok, and don't need to
676          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
677          * everything for us?  Resetting it takes the link down and requires
678          * several seconds for it to come back.
679          */
680         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
681                 return;
682
683         /* Single clk mode, mii mode off(for serdes communication) */
684         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
685
686         phy_write(priv->tbiphy, MII_ADVERTISE,
687                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
688                         ADVERTISE_1000XPSE_ASYM);
689
690         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
691                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
692 }
693
694 static void init_registers(struct net_device *dev)
695 {
696         struct gfar_private *priv = netdev_priv(dev);
697
698         /* Clear IEVENT */
699         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
700
701         /* Initialize IMASK */
702         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
703
704         /* Init hash registers to zero */
705         gfar_write(&priv->regs->igaddr0, 0);
706         gfar_write(&priv->regs->igaddr1, 0);
707         gfar_write(&priv->regs->igaddr2, 0);
708         gfar_write(&priv->regs->igaddr3, 0);
709         gfar_write(&priv->regs->igaddr4, 0);
710         gfar_write(&priv->regs->igaddr5, 0);
711         gfar_write(&priv->regs->igaddr6, 0);
712         gfar_write(&priv->regs->igaddr7, 0);
713
714         gfar_write(&priv->regs->gaddr0, 0);
715         gfar_write(&priv->regs->gaddr1, 0);
716         gfar_write(&priv->regs->gaddr2, 0);
717         gfar_write(&priv->regs->gaddr3, 0);
718         gfar_write(&priv->regs->gaddr4, 0);
719         gfar_write(&priv->regs->gaddr5, 0);
720         gfar_write(&priv->regs->gaddr6, 0);
721         gfar_write(&priv->regs->gaddr7, 0);
722
723         /* Zero out the rmon mib registers if it has them */
724         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
725                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
726
727                 /* Mask off the CAM interrupts */
728                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
729                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
730         }
731
732         /* Initialize the max receive buffer length */
733         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
734
735         /* Initialize the Minimum Frame Length Register */
736         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
737 }
738
739
740 /* Halt the receive and transmit queues */
741 static void gfar_halt_nodisable(struct net_device *dev)
742 {
743         struct gfar_private *priv = netdev_priv(dev);
744         struct gfar __iomem *regs = priv->regs;
745         u32 tempval;
746
747         /* Mask all interrupts */
748         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
749
750         /* Clear all interrupts */
751         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
752
753         /* Stop the DMA, and wait for it to stop */
754         tempval = gfar_read(&priv->regs->dmactrl);
755         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
756             != (DMACTRL_GRS | DMACTRL_GTS)) {
757                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
758                 gfar_write(&priv->regs->dmactrl, tempval);
759
760                 while (!(gfar_read(&priv->regs->ievent) &
761                          (IEVENT_GRSC | IEVENT_GTSC)))
762                         cpu_relax();
763         }
764 }
765
766 /* Halt the receive and transmit queues */
767 void gfar_halt(struct net_device *dev)
768 {
769         struct gfar_private *priv = netdev_priv(dev);
770         struct gfar __iomem *regs = priv->regs;
771         u32 tempval;
772
773         gfar_halt_nodisable(dev);
774
775         /* Disable Rx and Tx */
776         tempval = gfar_read(&regs->maccfg1);
777         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
778         gfar_write(&regs->maccfg1, tempval);
779 }
780
781 void stop_gfar(struct net_device *dev)
782 {
783         struct gfar_private *priv = netdev_priv(dev);
784         struct gfar __iomem *regs = priv->regs;
785         unsigned long flags;
786
787         phy_stop(priv->phydev);
788
789         /* Lock it down */
790         spin_lock_irqsave(&priv->txlock, flags);
791         spin_lock(&priv->rxlock);
792
793         gfar_halt(dev);
794
795         spin_unlock(&priv->rxlock);
796         spin_unlock_irqrestore(&priv->txlock, flags);
797
798         /* Free the IRQs */
799         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
800                 free_irq(priv->interruptError, dev);
801                 free_irq(priv->interruptTransmit, dev);
802                 free_irq(priv->interruptReceive, dev);
803         } else {
804                 free_irq(priv->interruptTransmit, dev);
805         }
806
807         free_skb_resources(priv);
808
809         dma_free_coherent(&dev->dev,
810                         sizeof(struct txbd8)*priv->tx_ring_size
811                         + sizeof(struct rxbd8)*priv->rx_ring_size,
812                         priv->tx_bd_base,
813                         gfar_read(&regs->tbase0));
814 }
815
816 /* If there are any tx skbs or rx skbs still around, free them.
817  * Then free tx_skbuff and rx_skbuff */
818 static void free_skb_resources(struct gfar_private *priv)
819 {
820         struct rxbd8 *rxbdp;
821         struct txbd8 *txbdp;
822         int i;
823
824         /* Go through all the buffer descriptors and free their data buffers */
825         txbdp = priv->tx_bd_base;
826
827         for (i = 0; i < priv->tx_ring_size; i++) {
828
829                 if (priv->tx_skbuff[i]) {
830                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
831                                         txbdp->length,
832                                         DMA_TO_DEVICE);
833                         dev_kfree_skb_any(priv->tx_skbuff[i]);
834                         priv->tx_skbuff[i] = NULL;
835                 }
836
837                 txbdp++;
838         }
839
840         kfree(priv->tx_skbuff);
841
842         rxbdp = priv->rx_bd_base;
843
844         /* rx_skbuff is not guaranteed to be allocated, so only
845          * free it and its contents if it is allocated */
846         if(priv->rx_skbuff != NULL) {
847                 for (i = 0; i < priv->rx_ring_size; i++) {
848                         if (priv->rx_skbuff[i]) {
849                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
850                                                 priv->rx_buffer_size,
851                                                 DMA_FROM_DEVICE);
852
853                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
854                                 priv->rx_skbuff[i] = NULL;
855                         }
856
857                         rxbdp->status = 0;
858                         rxbdp->length = 0;
859                         rxbdp->bufPtr = 0;
860
861                         rxbdp++;
862                 }
863
864                 kfree(priv->rx_skbuff);
865         }
866 }
867
868 void gfar_start(struct net_device *dev)
869 {
870         struct gfar_private *priv = netdev_priv(dev);
871         struct gfar __iomem *regs = priv->regs;
872         u32 tempval;
873
874         /* Enable Rx and Tx in MACCFG1 */
875         tempval = gfar_read(&regs->maccfg1);
876         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
877         gfar_write(&regs->maccfg1, tempval);
878
879         /* Initialize DMACTRL to have WWR and WOP */
880         tempval = gfar_read(&priv->regs->dmactrl);
881         tempval |= DMACTRL_INIT_SETTINGS;
882         gfar_write(&priv->regs->dmactrl, tempval);
883
884         /* Make sure we aren't stopped */
885         tempval = gfar_read(&priv->regs->dmactrl);
886         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
887         gfar_write(&priv->regs->dmactrl, tempval);
888
889         /* Clear THLT/RHLT, so that the DMA starts polling now */
890         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
891         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
892
893         /* Unmask the interrupts we look for */
894         gfar_write(&regs->imask, IMASK_DEFAULT);
895 }
896
897 /* Bring the controller up and running */
898 int startup_gfar(struct net_device *dev)
899 {
900         struct txbd8 *txbdp;
901         struct rxbd8 *rxbdp;
902         dma_addr_t addr = 0;
903         unsigned long vaddr;
904         int i;
905         struct gfar_private *priv = netdev_priv(dev);
906         struct gfar __iomem *regs = priv->regs;
907         int err = 0;
908         u32 rctrl = 0;
909         u32 attrs = 0;
910
911         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
912
913         /* Allocate memory for the buffer descriptors */
914         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
915                         sizeof (struct txbd8) * priv->tx_ring_size +
916                         sizeof (struct rxbd8) * priv->rx_ring_size,
917                         &addr, GFP_KERNEL);
918
919         if (vaddr == 0) {
920                 if (netif_msg_ifup(priv))
921                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
922                                         dev->name);
923                 return -ENOMEM;
924         }
925
926         priv->tx_bd_base = (struct txbd8 *) vaddr;
927
928         /* enet DMA only understands physical addresses */
929         gfar_write(&regs->tbase0, addr);
930
931         /* Start the rx descriptor ring where the tx ring leaves off */
932         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
933         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
934         priv->rx_bd_base = (struct rxbd8 *) vaddr;
935         gfar_write(&regs->rbase0, addr);
936
937         /* Setup the skbuff rings */
938         priv->tx_skbuff =
939             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
940                                         priv->tx_ring_size, GFP_KERNEL);
941
942         if (NULL == priv->tx_skbuff) {
943                 if (netif_msg_ifup(priv))
944                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
945                                         dev->name);
946                 err = -ENOMEM;
947                 goto tx_skb_fail;
948         }
949
950         for (i = 0; i < priv->tx_ring_size; i++)
951                 priv->tx_skbuff[i] = NULL;
952
953         priv->rx_skbuff =
954             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
955                                         priv->rx_ring_size, GFP_KERNEL);
956
957         if (NULL == priv->rx_skbuff) {
958                 if (netif_msg_ifup(priv))
959                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
960                                         dev->name);
961                 err = -ENOMEM;
962                 goto rx_skb_fail;
963         }
964
965         for (i = 0; i < priv->rx_ring_size; i++)
966                 priv->rx_skbuff[i] = NULL;
967
968         /* Initialize some variables in our dev structure */
969         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
970         priv->cur_rx = priv->rx_bd_base;
971         priv->skb_curtx = priv->skb_dirtytx = 0;
972         priv->skb_currx = 0;
973
974         /* Initialize Transmit Descriptor Ring */
975         txbdp = priv->tx_bd_base;
976         for (i = 0; i < priv->tx_ring_size; i++) {
977                 txbdp->status = 0;
978                 txbdp->length = 0;
979                 txbdp->bufPtr = 0;
980                 txbdp++;
981         }
982
983         /* Set the last descriptor in the ring to indicate wrap */
984         txbdp--;
985         txbdp->status |= TXBD_WRAP;
986
987         rxbdp = priv->rx_bd_base;
988         for (i = 0; i < priv->rx_ring_size; i++) {
989                 struct sk_buff *skb;
990
991                 skb = gfar_new_skb(dev);
992
993                 if (!skb) {
994                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
995                                         dev->name);
996
997                         goto err_rxalloc_fail;
998                 }
999
1000                 priv->rx_skbuff[i] = skb;
1001
1002                 gfar_new_rxbdp(dev, rxbdp, skb);
1003
1004                 rxbdp++;
1005         }
1006
1007         /* Set the last descriptor in the ring to wrap */
1008         rxbdp--;
1009         rxbdp->status |= RXBD_WRAP;
1010
1011         /* If the device has multiple interrupts, register for
1012          * them.  Otherwise, only register for the one */
1013         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1014                 /* Install our interrupt handlers for Error,
1015                  * Transmit, and Receive */
1016                 if (request_irq(priv->interruptError, gfar_error,
1017                                 0, "enet_error", dev) < 0) {
1018                         if (netif_msg_intr(priv))
1019                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1020                                         dev->name, priv->interruptError);
1021
1022                         err = -1;
1023                         goto err_irq_fail;
1024                 }
1025
1026                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1027                                 0, "enet_tx", dev) < 0) {
1028                         if (netif_msg_intr(priv))
1029                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1030                                         dev->name, priv->interruptTransmit);
1031
1032                         err = -1;
1033
1034                         goto tx_irq_fail;
1035                 }
1036
1037                 if (request_irq(priv->interruptReceive, gfar_receive,
1038                                 0, "enet_rx", dev) < 0) {
1039                         if (netif_msg_intr(priv))
1040                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1041                                                 dev->name, priv->interruptReceive);
1042
1043                         err = -1;
1044                         goto rx_irq_fail;
1045                 }
1046         } else {
1047                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1048                                 0, "gfar_interrupt", dev) < 0) {
1049                         if (netif_msg_intr(priv))
1050                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1051                                         dev->name, priv->interruptError);
1052
1053                         err = -1;
1054                         goto err_irq_fail;
1055                 }
1056         }
1057
1058         phy_start(priv->phydev);
1059
1060         /* Configure the coalescing support */
1061         gfar_write(&regs->txic, 0);
1062         if (priv->txcoalescing)
1063                 gfar_write(&regs->txic, priv->txic);
1064
1065         gfar_write(&regs->rxic, 0);
1066         if (priv->rxcoalescing)
1067                 gfar_write(&regs->rxic, priv->rxic);
1068
1069         if (priv->rx_csum_enable)
1070                 rctrl |= RCTRL_CHECKSUMMING;
1071
1072         if (priv->extended_hash) {
1073                 rctrl |= RCTRL_EXTHASH;
1074
1075                 gfar_clear_exact_match(dev);
1076                 rctrl |= RCTRL_EMEN;
1077         }
1078
1079         if (priv->vlan_enable)
1080                 rctrl |= RCTRL_VLAN;
1081
1082         if (priv->padding) {
1083                 rctrl &= ~RCTRL_PAL_MASK;
1084                 rctrl |= RCTRL_PADDING(priv->padding);
1085         }
1086
1087         /* Init rctrl based on our settings */
1088         gfar_write(&priv->regs->rctrl, rctrl);
1089
1090         if (dev->features & NETIF_F_IP_CSUM)
1091                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1092
1093         /* Set the extraction length and index */
1094         attrs = ATTRELI_EL(priv->rx_stash_size) |
1095                 ATTRELI_EI(priv->rx_stash_index);
1096
1097         gfar_write(&priv->regs->attreli, attrs);
1098
1099         /* Start with defaults, and add stashing or locking
1100          * depending on the approprate variables */
1101         attrs = ATTR_INIT_SETTINGS;
1102
1103         if (priv->bd_stash_en)
1104                 attrs |= ATTR_BDSTASH;
1105
1106         if (priv->rx_stash_size != 0)
1107                 attrs |= ATTR_BUFSTASH;
1108
1109         gfar_write(&priv->regs->attr, attrs);
1110
1111         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1112         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1113         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1114
1115         /* Start the controller */
1116         gfar_start(dev);
1117
1118         return 0;
1119
1120 rx_irq_fail:
1121         free_irq(priv->interruptTransmit, dev);
1122 tx_irq_fail:
1123         free_irq(priv->interruptError, dev);
1124 err_irq_fail:
1125 err_rxalloc_fail:
1126 rx_skb_fail:
1127         free_skb_resources(priv);
1128 tx_skb_fail:
1129         dma_free_coherent(&dev->dev,
1130                         sizeof(struct txbd8)*priv->tx_ring_size
1131                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1132                         priv->tx_bd_base,
1133                         gfar_read(&regs->tbase0));
1134
1135         return err;
1136 }
1137
1138 /* Called when something needs to use the ethernet device */
1139 /* Returns 0 for success. */
1140 static int gfar_enet_open(struct net_device *dev)
1141 {
1142         struct gfar_private *priv = netdev_priv(dev);
1143         int err;
1144
1145         napi_enable(&priv->napi);
1146
1147         /* Initialize a bunch of registers */
1148         init_registers(dev);
1149
1150         gfar_set_mac_address(dev);
1151
1152         err = init_phy(dev);
1153
1154         if(err) {
1155                 napi_disable(&priv->napi);
1156                 return err;
1157         }
1158
1159         err = startup_gfar(dev);
1160         if (err) {
1161                 napi_disable(&priv->napi);
1162                 return err;
1163         }
1164
1165         netif_start_queue(dev);
1166
1167         return err;
1168 }
1169
1170 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1171 {
1172         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1173
1174         memset(fcb, 0, GMAC_FCB_LEN);
1175
1176         return fcb;
1177 }
1178
1179 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1180 {
1181         u8 flags = 0;
1182
1183         /* If we're here, it's a IP packet with a TCP or UDP
1184          * payload.  We set it to checksum, using a pseudo-header
1185          * we provide
1186          */
1187         flags = TXFCB_DEFAULT;
1188
1189         /* Tell the controller what the protocol is */
1190         /* And provide the already calculated phcs */
1191         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1192                 flags |= TXFCB_UDP;
1193                 fcb->phcs = udp_hdr(skb)->check;
1194         } else
1195                 fcb->phcs = tcp_hdr(skb)->check;
1196
1197         /* l3os is the distance between the start of the
1198          * frame (skb->data) and the start of the IP hdr.
1199          * l4os is the distance between the start of the
1200          * l3 hdr and the l4 hdr */
1201         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1202         fcb->l4os = skb_network_header_len(skb);
1203
1204         fcb->flags = flags;
1205 }
1206
1207 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1208 {
1209         fcb->flags |= TXFCB_VLN;
1210         fcb->vlctl = vlan_tx_tag_get(skb);
1211 }
1212
1213 /* This is called by the kernel when a frame is ready for transmission. */
1214 /* It is pointed to by the dev->hard_start_xmit function pointer */
1215 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1216 {
1217         struct gfar_private *priv = netdev_priv(dev);
1218         struct txfcb *fcb = NULL;
1219         struct txbd8 *txbdp;
1220         u16 status;
1221         unsigned long flags;
1222
1223         /* Update transmit stats */
1224         dev->stats.tx_bytes += skb->len;
1225
1226         /* Lock priv now */
1227         spin_lock_irqsave(&priv->txlock, flags);
1228
1229         /* Point at the first free tx descriptor */
1230         txbdp = priv->cur_tx;
1231
1232         /* Clear all but the WRAP status flags */
1233         status = txbdp->status & TXBD_WRAP;
1234
1235         /* Set up checksumming */
1236         if (likely((dev->features & NETIF_F_IP_CSUM)
1237                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1238                 fcb = gfar_add_fcb(skb, txbdp);
1239                 status |= TXBD_TOE;
1240                 gfar_tx_checksum(skb, fcb);
1241         }
1242
1243         if (priv->vlan_enable &&
1244                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1245                 if (unlikely(NULL == fcb)) {
1246                         fcb = gfar_add_fcb(skb, txbdp);
1247                         status |= TXBD_TOE;
1248                 }
1249
1250                 gfar_tx_vlan(skb, fcb);
1251         }
1252
1253         /* Set buffer length and pointer */
1254         txbdp->length = skb->len;
1255         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1256                         skb->len, DMA_TO_DEVICE);
1257
1258         /* Save the skb pointer so we can free it later */
1259         priv->tx_skbuff[priv->skb_curtx] = skb;
1260
1261         /* Update the current skb pointer (wrapping if this was the last) */
1262         priv->skb_curtx =
1263             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1264
1265         /* Flag the BD as interrupt-causing */
1266         status |= TXBD_INTERRUPT;
1267
1268         /* Flag the BD as ready to go, last in frame, and  */
1269         /* in need of CRC */
1270         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1271
1272         dev->trans_start = jiffies;
1273
1274         /* The powerpc-specific eieio() is used, as wmb() has too strong
1275          * semantics (it requires synchronization between cacheable and
1276          * uncacheable mappings, which eieio doesn't provide and which we
1277          * don't need), thus requiring a more expensive sync instruction.  At
1278          * some point, the set of architecture-independent barrier functions
1279          * should be expanded to include weaker barriers.
1280          */
1281
1282         eieio();
1283         txbdp->status = status;
1284
1285         /* If this was the last BD in the ring, the next one */
1286         /* is at the beginning of the ring */
1287         if (txbdp->status & TXBD_WRAP)
1288                 txbdp = priv->tx_bd_base;
1289         else
1290                 txbdp++;
1291
1292         /* If the next BD still needs to be cleaned up, then the bds
1293            are full.  We need to tell the kernel to stop sending us stuff. */
1294         if (txbdp == priv->dirty_tx) {
1295                 netif_stop_queue(dev);
1296
1297                 dev->stats.tx_fifo_errors++;
1298         }
1299
1300         /* Update the current txbd to the next one */
1301         priv->cur_tx = txbdp;
1302
1303         /* Tell the DMA to go go go */
1304         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1305
1306         /* Unlock priv */
1307         spin_unlock_irqrestore(&priv->txlock, flags);
1308
1309         return 0;
1310 }
1311
1312 /* Stops the kernel queue, and halts the controller */
1313 static int gfar_close(struct net_device *dev)
1314 {
1315         struct gfar_private *priv = netdev_priv(dev);
1316
1317         napi_disable(&priv->napi);
1318
1319         cancel_work_sync(&priv->reset_task);
1320         stop_gfar(dev);
1321
1322         /* Disconnect from the PHY */
1323         phy_disconnect(priv->phydev);
1324         priv->phydev = NULL;
1325
1326         netif_stop_queue(dev);
1327
1328         return 0;
1329 }
1330
1331 /* Changes the mac address if the controller is not running. */
1332 static int gfar_set_mac_address(struct net_device *dev)
1333 {
1334         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1335
1336         return 0;
1337 }
1338
1339
1340 /* Enables and disables VLAN insertion/extraction */
1341 static void gfar_vlan_rx_register(struct net_device *dev,
1342                 struct vlan_group *grp)
1343 {
1344         struct gfar_private *priv = netdev_priv(dev);
1345         unsigned long flags;
1346         u32 tempval;
1347
1348         spin_lock_irqsave(&priv->rxlock, flags);
1349
1350         priv->vlgrp = grp;
1351
1352         if (grp) {
1353                 /* Enable VLAN tag insertion */
1354                 tempval = gfar_read(&priv->regs->tctrl);
1355                 tempval |= TCTRL_VLINS;
1356
1357                 gfar_write(&priv->regs->tctrl, tempval);
1358
1359                 /* Enable VLAN tag extraction */
1360                 tempval = gfar_read(&priv->regs->rctrl);
1361                 tempval |= RCTRL_VLEX;
1362                 gfar_write(&priv->regs->rctrl, tempval);
1363         } else {
1364                 /* Disable VLAN tag insertion */
1365                 tempval = gfar_read(&priv->regs->tctrl);
1366                 tempval &= ~TCTRL_VLINS;
1367                 gfar_write(&priv->regs->tctrl, tempval);
1368
1369                 /* Disable VLAN tag extraction */
1370                 tempval = gfar_read(&priv->regs->rctrl);
1371                 tempval &= ~RCTRL_VLEX;
1372                 gfar_write(&priv->regs->rctrl, tempval);
1373         }
1374
1375         spin_unlock_irqrestore(&priv->rxlock, flags);
1376 }
1377
1378 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1379 {
1380         int tempsize, tempval;
1381         struct gfar_private *priv = netdev_priv(dev);
1382         int oldsize = priv->rx_buffer_size;
1383         int frame_size = new_mtu + ETH_HLEN;
1384
1385         if (priv->vlan_enable)
1386                 frame_size += VLAN_HLEN;
1387
1388         if (gfar_uses_fcb(priv))
1389                 frame_size += GMAC_FCB_LEN;
1390
1391         frame_size += priv->padding;
1392
1393         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1394                 if (netif_msg_drv(priv))
1395                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1396                                         dev->name);
1397                 return -EINVAL;
1398         }
1399
1400         tempsize =
1401             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1402             INCREMENTAL_BUFFER_SIZE;
1403
1404         /* Only stop and start the controller if it isn't already
1405          * stopped, and we changed something */
1406         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1407                 stop_gfar(dev);
1408
1409         priv->rx_buffer_size = tempsize;
1410
1411         dev->mtu = new_mtu;
1412
1413         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1414         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1415
1416         /* If the mtu is larger than the max size for standard
1417          * ethernet frames (ie, a jumbo frame), then set maccfg2
1418          * to allow huge frames, and to check the length */
1419         tempval = gfar_read(&priv->regs->maccfg2);
1420
1421         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1422                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1423         else
1424                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1425
1426         gfar_write(&priv->regs->maccfg2, tempval);
1427
1428         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1429                 startup_gfar(dev);
1430
1431         return 0;
1432 }
1433
1434 /* gfar_reset_task gets scheduled when a packet has not been
1435  * transmitted after a set amount of time.
1436  * For now, assume that clearing out all the structures, and
1437  * starting over will fix the problem.
1438  */
1439 static void gfar_reset_task(struct work_struct *work)
1440 {
1441         struct gfar_private *priv = container_of(work, struct gfar_private,
1442                         reset_task);
1443         struct net_device *dev = priv->dev;
1444
1445         if (dev->flags & IFF_UP) {
1446                 stop_gfar(dev);
1447                 startup_gfar(dev);
1448         }
1449
1450         netif_tx_schedule_all(dev);
1451 }
1452
1453 static void gfar_timeout(struct net_device *dev)
1454 {
1455         struct gfar_private *priv = netdev_priv(dev);
1456
1457         dev->stats.tx_errors++;
1458         schedule_work(&priv->reset_task);
1459 }
1460
1461 /* Interrupt Handler for Transmit complete */
1462 static int gfar_clean_tx_ring(struct net_device *dev)
1463 {
1464         struct txbd8 *bdp;
1465         struct gfar_private *priv = netdev_priv(dev);
1466         int howmany = 0;
1467
1468         bdp = priv->dirty_tx;
1469         while ((bdp->status & TXBD_READY) == 0) {
1470                 /* If dirty_tx and cur_tx are the same, then either the */
1471                 /* ring is empty or full now (it could only be full in the beginning, */
1472                 /* obviously).  If it is empty, we are done. */
1473                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1474                         break;
1475
1476                 howmany++;
1477
1478                 /* Deferred means some collisions occurred during transmit, */
1479                 /* but we eventually sent the packet. */
1480                 if (bdp->status & TXBD_DEF)
1481                         dev->stats.collisions++;
1482
1483                 /* Unmap the DMA memory */
1484                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1485                                 bdp->length, DMA_TO_DEVICE);
1486
1487                 /* Free the sk buffer associated with this TxBD */
1488                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1489
1490                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1491                 priv->skb_dirtytx =
1492                     (priv->skb_dirtytx +
1493                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1494
1495                 /* Clean BD length for empty detection */
1496                 bdp->length = 0;
1497
1498                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1499                 if (bdp->status & TXBD_WRAP)
1500                         bdp = priv->tx_bd_base;
1501                 else
1502                         bdp++;
1503
1504                 /* Move dirty_tx to be the next bd */
1505                 priv->dirty_tx = bdp;
1506
1507                 /* We freed a buffer, so now we can restart transmission */
1508                 if (netif_queue_stopped(dev))
1509                         netif_wake_queue(dev);
1510         } /* while ((bdp->status & TXBD_READY) == 0) */
1511
1512         dev->stats.tx_packets += howmany;
1513
1514         return howmany;
1515 }
1516
1517 /* Interrupt Handler for Transmit complete */
1518 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1519 {
1520         struct net_device *dev = (struct net_device *) dev_id;
1521         struct gfar_private *priv = netdev_priv(dev);
1522
1523         /* Clear IEVENT */
1524         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1525
1526         /* Lock priv */
1527         spin_lock(&priv->txlock);
1528
1529         gfar_clean_tx_ring(dev);
1530
1531         /* If we are coalescing the interrupts, reset the timer */
1532         /* Otherwise, clear it */
1533         if (likely(priv->txcoalescing)) {
1534                 gfar_write(&priv->regs->txic, 0);
1535                 gfar_write(&priv->regs->txic, priv->txic);
1536         }
1537
1538         spin_unlock(&priv->txlock);
1539
1540         return IRQ_HANDLED;
1541 }
1542
1543 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1544                 struct sk_buff *skb)
1545 {
1546         struct gfar_private *priv = netdev_priv(dev);
1547         u32 * status_len = (u32 *)bdp;
1548         u16 flags;
1549
1550         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1551                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1552
1553         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1554
1555         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1556                 flags |= RXBD_WRAP;
1557
1558         eieio();
1559
1560         *status_len = (u32)flags << 16;
1561 }
1562
1563
1564 struct sk_buff * gfar_new_skb(struct net_device *dev)
1565 {
1566         unsigned int alignamount;
1567         struct gfar_private *priv = netdev_priv(dev);
1568         struct sk_buff *skb = NULL;
1569
1570         /* We have to allocate the skb, so keep trying till we succeed */
1571         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1572
1573         if (!skb)
1574                 return NULL;
1575
1576         alignamount = RXBUF_ALIGNMENT -
1577                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1578
1579         /* We need the data buffer to be aligned properly.  We will reserve
1580          * as many bytes as needed to align the data properly
1581          */
1582         skb_reserve(skb, alignamount);
1583
1584         return skb;
1585 }
1586
1587 static inline void count_errors(unsigned short status, struct net_device *dev)
1588 {
1589         struct gfar_private *priv = netdev_priv(dev);
1590         struct net_device_stats *stats = &dev->stats;
1591         struct gfar_extra_stats *estats = &priv->extra_stats;
1592
1593         /* If the packet was truncated, none of the other errors
1594          * matter */
1595         if (status & RXBD_TRUNCATED) {
1596                 stats->rx_length_errors++;
1597
1598                 estats->rx_trunc++;
1599
1600                 return;
1601         }
1602         /* Count the errors, if there were any */
1603         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1604                 stats->rx_length_errors++;
1605
1606                 if (status & RXBD_LARGE)
1607                         estats->rx_large++;
1608                 else
1609                         estats->rx_short++;
1610         }
1611         if (status & RXBD_NONOCTET) {
1612                 stats->rx_frame_errors++;
1613                 estats->rx_nonoctet++;
1614         }
1615         if (status & RXBD_CRCERR) {
1616                 estats->rx_crcerr++;
1617                 stats->rx_crc_errors++;
1618         }
1619         if (status & RXBD_OVERRUN) {
1620                 estats->rx_overrun++;
1621                 stats->rx_crc_errors++;
1622         }
1623 }
1624
1625 irqreturn_t gfar_receive(int irq, void *dev_id)
1626 {
1627         struct net_device *dev = (struct net_device *) dev_id;
1628         struct gfar_private *priv = netdev_priv(dev);
1629         u32 tempval;
1630
1631         /* support NAPI */
1632         /* Clear IEVENT, so interrupts aren't called again
1633          * because of the packets that have already arrived */
1634         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1635
1636         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1637                 tempval = gfar_read(&priv->regs->imask);
1638                 tempval &= IMASK_RTX_DISABLED;
1639                 gfar_write(&priv->regs->imask, tempval);
1640
1641                 __netif_rx_schedule(dev, &priv->napi);
1642         } else {
1643                 if (netif_msg_rx_err(priv))
1644                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1645                                 dev->name, gfar_read(&priv->regs->ievent),
1646                                 gfar_read(&priv->regs->imask));
1647         }
1648
1649         return IRQ_HANDLED;
1650 }
1651
1652 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1653 {
1654         /* If valid headers were found, and valid sums
1655          * were verified, then we tell the kernel that no
1656          * checksumming is necessary.  Otherwise, it is */
1657         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1658                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1659         else
1660                 skb->ip_summed = CHECKSUM_NONE;
1661 }
1662
1663
1664 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1665 {
1666         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1667
1668         /* Remove the FCB from the skb */
1669         skb_pull(skb, GMAC_FCB_LEN);
1670
1671         return fcb;
1672 }
1673
1674 /* gfar_process_frame() -- handle one incoming packet if skb
1675  * isn't NULL.  */
1676 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1677                 int length)
1678 {
1679         struct gfar_private *priv = netdev_priv(dev);
1680         struct rxfcb *fcb = NULL;
1681
1682         if (NULL == skb) {
1683                 if (netif_msg_rx_err(priv))
1684                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1685                 dev->stats.rx_dropped++;
1686                 priv->extra_stats.rx_skbmissing++;
1687         } else {
1688                 int ret;
1689
1690                 /* Prep the skb for the packet */
1691                 skb_put(skb, length);
1692
1693                 /* Grab the FCB if there is one */
1694                 if (gfar_uses_fcb(priv))
1695                         fcb = gfar_get_fcb(skb);
1696
1697                 /* Remove the padded bytes, if there are any */
1698                 if (priv->padding)
1699                         skb_pull(skb, priv->padding);
1700
1701                 if (priv->rx_csum_enable)
1702                         gfar_rx_checksum(skb, fcb);
1703
1704                 /* Tell the skb what kind of packet this is */
1705                 skb->protocol = eth_type_trans(skb, dev);
1706
1707                 /* Send the packet up the stack */
1708                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1709                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1710                                                        fcb->vlctl);
1711                 } else
1712                         ret = netif_receive_skb(skb);
1713
1714                 if (NET_RX_DROP == ret)
1715                         priv->extra_stats.kernel_dropped++;
1716         }
1717
1718         return 0;
1719 }
1720
1721 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1722  *   until the budget/quota has been reached. Returns the number
1723  *   of frames handled
1724  */
1725 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1726 {
1727         struct rxbd8 *bdp;
1728         struct sk_buff *skb;
1729         u16 pkt_len;
1730         int howmany = 0;
1731         struct gfar_private *priv = netdev_priv(dev);
1732
1733         /* Get the first full descriptor */
1734         bdp = priv->cur_rx;
1735
1736         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1737                 struct sk_buff *newskb;
1738                 rmb();
1739
1740                 /* Add another skb for the future */
1741                 newskb = gfar_new_skb(dev);
1742
1743                 skb = priv->rx_skbuff[priv->skb_currx];
1744
1745                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1746                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1747
1748                 /* We drop the frame if we failed to allocate a new buffer */
1749                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1750                                  bdp->status & RXBD_ERR)) {
1751                         count_errors(bdp->status, dev);
1752
1753                         if (unlikely(!newskb))
1754                                 newskb = skb;
1755
1756                         if (skb)
1757                                 dev_kfree_skb_any(skb);
1758                 } else {
1759                         /* Increment the number of packets */
1760                         dev->stats.rx_packets++;
1761                         howmany++;
1762
1763                         /* Remove the FCS from the packet length */
1764                         pkt_len = bdp->length - 4;
1765
1766                         gfar_process_frame(dev, skb, pkt_len);
1767
1768                         dev->stats.rx_bytes += pkt_len;
1769                 }
1770
1771                 priv->rx_skbuff[priv->skb_currx] = newskb;
1772
1773                 /* Setup the new bdp */
1774                 gfar_new_rxbdp(dev, bdp, newskb);
1775
1776                 /* Update to the next pointer */
1777                 if (bdp->status & RXBD_WRAP)
1778                         bdp = priv->rx_bd_base;
1779                 else
1780                         bdp++;
1781
1782                 /* update to point at the next skb */
1783                 priv->skb_currx =
1784                     (priv->skb_currx + 1) &
1785                     RX_RING_MOD_MASK(priv->rx_ring_size);
1786         }
1787
1788         /* Update the current rxbd pointer to be the next one */
1789         priv->cur_rx = bdp;
1790
1791         return howmany;
1792 }
1793
1794 static int gfar_poll(struct napi_struct *napi, int budget)
1795 {
1796         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1797         struct net_device *dev = priv->dev;
1798         int howmany;
1799         unsigned long flags;
1800
1801         /* If we fail to get the lock, don't bother with the TX BDs */
1802         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1803                 gfar_clean_tx_ring(dev);
1804                 spin_unlock_irqrestore(&priv->txlock, flags);
1805         }
1806
1807         howmany = gfar_clean_rx_ring(dev, budget);
1808
1809         if (howmany < budget) {
1810                 netif_rx_complete(dev, napi);
1811
1812                 /* Clear the halt bit in RSTAT */
1813                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1814
1815                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1816
1817                 /* If we are coalescing interrupts, update the timer */
1818                 /* Otherwise, clear it */
1819                 if (likely(priv->rxcoalescing)) {
1820                         gfar_write(&priv->regs->rxic, 0);
1821                         gfar_write(&priv->regs->rxic, priv->rxic);
1822                 }
1823         }
1824
1825         return howmany;
1826 }
1827
1828 #ifdef CONFIG_NET_POLL_CONTROLLER
1829 /*
1830  * Polling 'interrupt' - used by things like netconsole to send skbs
1831  * without having to re-enable interrupts. It's not called while
1832  * the interrupt routine is executing.
1833  */
1834 static void gfar_netpoll(struct net_device *dev)
1835 {
1836         struct gfar_private *priv = netdev_priv(dev);
1837
1838         /* If the device has multiple interrupts, run tx/rx */
1839         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1840                 disable_irq(priv->interruptTransmit);
1841                 disable_irq(priv->interruptReceive);
1842                 disable_irq(priv->interruptError);
1843                 gfar_interrupt(priv->interruptTransmit, dev);
1844                 enable_irq(priv->interruptError);
1845                 enable_irq(priv->interruptReceive);
1846                 enable_irq(priv->interruptTransmit);
1847         } else {
1848                 disable_irq(priv->interruptTransmit);
1849                 gfar_interrupt(priv->interruptTransmit, dev);
1850                 enable_irq(priv->interruptTransmit);
1851         }
1852 }
1853 #endif
1854
1855 /* The interrupt handler for devices with one interrupt */
1856 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1857 {
1858         struct net_device *dev = dev_id;
1859         struct gfar_private *priv = netdev_priv(dev);
1860
1861         /* Save ievent for future reference */
1862         u32 events = gfar_read(&priv->regs->ievent);
1863
1864         /* Check for reception */
1865         if (events & IEVENT_RX_MASK)
1866                 gfar_receive(irq, dev_id);
1867
1868         /* Check for transmit completion */
1869         if (events & IEVENT_TX_MASK)
1870                 gfar_transmit(irq, dev_id);
1871
1872         /* Check for errors */
1873         if (events & IEVENT_ERR_MASK)
1874                 gfar_error(irq, dev_id);
1875
1876         return IRQ_HANDLED;
1877 }
1878
1879 /* Called every time the controller might need to be made
1880  * aware of new link state.  The PHY code conveys this
1881  * information through variables in the phydev structure, and this
1882  * function converts those variables into the appropriate
1883  * register values, and can bring down the device if needed.
1884  */
1885 static void adjust_link(struct net_device *dev)
1886 {
1887         struct gfar_private *priv = netdev_priv(dev);
1888         struct gfar __iomem *regs = priv->regs;
1889         unsigned long flags;
1890         struct phy_device *phydev = priv->phydev;
1891         int new_state = 0;
1892
1893         spin_lock_irqsave(&priv->txlock, flags);
1894         if (phydev->link) {
1895                 u32 tempval = gfar_read(&regs->maccfg2);
1896                 u32 ecntrl = gfar_read(&regs->ecntrl);
1897
1898                 /* Now we make sure that we can be in full duplex mode.
1899                  * If not, we operate in half-duplex mode. */
1900                 if (phydev->duplex != priv->oldduplex) {
1901                         new_state = 1;
1902                         if (!(phydev->duplex))
1903                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1904                         else
1905                                 tempval |= MACCFG2_FULL_DUPLEX;
1906
1907                         priv->oldduplex = phydev->duplex;
1908                 }
1909
1910                 if (phydev->speed != priv->oldspeed) {
1911                         new_state = 1;
1912                         switch (phydev->speed) {
1913                         case 1000:
1914                                 tempval =
1915                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1916                                 break;
1917                         case 100:
1918                         case 10:
1919                                 tempval =
1920                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1921
1922                                 /* Reduced mode distinguishes
1923                                  * between 10 and 100 */
1924                                 if (phydev->speed == SPEED_100)
1925                                         ecntrl |= ECNTRL_R100;
1926                                 else
1927                                         ecntrl &= ~(ECNTRL_R100);
1928                                 break;
1929                         default:
1930                                 if (netif_msg_link(priv))
1931                                         printk(KERN_WARNING
1932                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1933                                                 dev->name, phydev->speed);
1934                                 break;
1935                         }
1936
1937                         priv->oldspeed = phydev->speed;
1938                 }
1939
1940                 gfar_write(&regs->maccfg2, tempval);
1941                 gfar_write(&regs->ecntrl, ecntrl);
1942
1943                 if (!priv->oldlink) {
1944                         new_state = 1;
1945                         priv->oldlink = 1;
1946                 }
1947         } else if (priv->oldlink) {
1948                 new_state = 1;
1949                 priv->oldlink = 0;
1950                 priv->oldspeed = 0;
1951                 priv->oldduplex = -1;
1952         }
1953
1954         if (new_state && netif_msg_link(priv))
1955                 phy_print_status(phydev);
1956
1957         spin_unlock_irqrestore(&priv->txlock, flags);
1958 }
1959
1960 /* Update the hash table based on the current list of multicast
1961  * addresses we subscribe to.  Also, change the promiscuity of
1962  * the device based on the flags (this function is called
1963  * whenever dev->flags is changed */
1964 static void gfar_set_multi(struct net_device *dev)
1965 {
1966         struct dev_mc_list *mc_ptr;
1967         struct gfar_private *priv = netdev_priv(dev);
1968         struct gfar __iomem *regs = priv->regs;
1969         u32 tempval;
1970
1971         if(dev->flags & IFF_PROMISC) {
1972                 /* Set RCTRL to PROM */
1973                 tempval = gfar_read(&regs->rctrl);
1974                 tempval |= RCTRL_PROM;
1975                 gfar_write(&regs->rctrl, tempval);
1976         } else {
1977                 /* Set RCTRL to not PROM */
1978                 tempval = gfar_read(&regs->rctrl);
1979                 tempval &= ~(RCTRL_PROM);
1980                 gfar_write(&regs->rctrl, tempval);
1981         }
1982
1983         if(dev->flags & IFF_ALLMULTI) {
1984                 /* Set the hash to rx all multicast frames */
1985                 gfar_write(&regs->igaddr0, 0xffffffff);
1986                 gfar_write(&regs->igaddr1, 0xffffffff);
1987                 gfar_write(&regs->igaddr2, 0xffffffff);
1988                 gfar_write(&regs->igaddr3, 0xffffffff);
1989                 gfar_write(&regs->igaddr4, 0xffffffff);
1990                 gfar_write(&regs->igaddr5, 0xffffffff);
1991                 gfar_write(&regs->igaddr6, 0xffffffff);
1992                 gfar_write(&regs->igaddr7, 0xffffffff);
1993                 gfar_write(&regs->gaddr0, 0xffffffff);
1994                 gfar_write(&regs->gaddr1, 0xffffffff);
1995                 gfar_write(&regs->gaddr2, 0xffffffff);
1996                 gfar_write(&regs->gaddr3, 0xffffffff);
1997                 gfar_write(&regs->gaddr4, 0xffffffff);
1998                 gfar_write(&regs->gaddr5, 0xffffffff);
1999                 gfar_write(&regs->gaddr6, 0xffffffff);
2000                 gfar_write(&regs->gaddr7, 0xffffffff);
2001         } else {
2002                 int em_num;
2003                 int idx;
2004
2005                 /* zero out the hash */
2006                 gfar_write(&regs->igaddr0, 0x0);
2007                 gfar_write(&regs->igaddr1, 0x0);
2008                 gfar_write(&regs->igaddr2, 0x0);
2009                 gfar_write(&regs->igaddr3, 0x0);
2010                 gfar_write(&regs->igaddr4, 0x0);
2011                 gfar_write(&regs->igaddr5, 0x0);
2012                 gfar_write(&regs->igaddr6, 0x0);
2013                 gfar_write(&regs->igaddr7, 0x0);
2014                 gfar_write(&regs->gaddr0, 0x0);
2015                 gfar_write(&regs->gaddr1, 0x0);
2016                 gfar_write(&regs->gaddr2, 0x0);
2017                 gfar_write(&regs->gaddr3, 0x0);
2018                 gfar_write(&regs->gaddr4, 0x0);
2019                 gfar_write(&regs->gaddr5, 0x0);
2020                 gfar_write(&regs->gaddr6, 0x0);
2021                 gfar_write(&regs->gaddr7, 0x0);
2022
2023                 /* If we have extended hash tables, we need to
2024                  * clear the exact match registers to prepare for
2025                  * setting them */
2026                 if (priv->extended_hash) {
2027                         em_num = GFAR_EM_NUM + 1;
2028                         gfar_clear_exact_match(dev);
2029                         idx = 1;
2030                 } else {
2031                         idx = 0;
2032                         em_num = 0;
2033                 }
2034
2035                 if(dev->mc_count == 0)
2036                         return;
2037
2038                 /* Parse the list, and set the appropriate bits */
2039                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2040                         if (idx < em_num) {
2041                                 gfar_set_mac_for_addr(dev, idx,
2042                                                 mc_ptr->dmi_addr);
2043                                 idx++;
2044                         } else
2045                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2046                 }
2047         }
2048
2049         return;
2050 }
2051
2052
2053 /* Clears each of the exact match registers to zero, so they
2054  * don't interfere with normal reception */
2055 static void gfar_clear_exact_match(struct net_device *dev)
2056 {
2057         int idx;
2058         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2059
2060         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2061                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2062 }
2063
2064 /* Set the appropriate hash bit for the given addr */
2065 /* The algorithm works like so:
2066  * 1) Take the Destination Address (ie the multicast address), and
2067  * do a CRC on it (little endian), and reverse the bits of the
2068  * result.
2069  * 2) Use the 8 most significant bits as a hash into a 256-entry
2070  * table.  The table is controlled through 8 32-bit registers:
2071  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2072  * gaddr7.  This means that the 3 most significant bits in the
2073  * hash index which gaddr register to use, and the 5 other bits
2074  * indicate which bit (assuming an IBM numbering scheme, which
2075  * for PowerPC (tm) is usually the case) in the register holds
2076  * the entry. */
2077 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2078 {
2079         u32 tempval;
2080         struct gfar_private *priv = netdev_priv(dev);
2081         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2082         int width = priv->hash_width;
2083         u8 whichbit = (result >> (32 - width)) & 0x1f;
2084         u8 whichreg = result >> (32 - width + 5);
2085         u32 value = (1 << (31-whichbit));
2086
2087         tempval = gfar_read(priv->hash_regs[whichreg]);
2088         tempval |= value;
2089         gfar_write(priv->hash_regs[whichreg], tempval);
2090
2091         return;
2092 }
2093
2094
2095 /* There are multiple MAC Address register pairs on some controllers
2096  * This function sets the numth pair to a given address
2097  */
2098 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2099 {
2100         struct gfar_private *priv = netdev_priv(dev);
2101         int idx;
2102         char tmpbuf[MAC_ADDR_LEN];
2103         u32 tempval;
2104         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2105
2106         macptr += num*2;
2107
2108         /* Now copy it into the mac registers backwards, cuz */
2109         /* little endian is silly */
2110         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2111                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2112
2113         gfar_write(macptr, *((u32 *) (tmpbuf)));
2114
2115         tempval = *((u32 *) (tmpbuf + 4));
2116
2117         gfar_write(macptr+1, tempval);
2118 }
2119
2120 /* GFAR error interrupt handler */
2121 static irqreturn_t gfar_error(int irq, void *dev_id)
2122 {
2123         struct net_device *dev = dev_id;
2124         struct gfar_private *priv = netdev_priv(dev);
2125
2126         /* Save ievent for future reference */
2127         u32 events = gfar_read(&priv->regs->ievent);
2128
2129         /* Clear IEVENT */
2130         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2131
2132         /* Magic Packet is not an error. */
2133         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2134             (events & IEVENT_MAG))
2135                 events &= ~IEVENT_MAG;
2136
2137         /* Hmm... */
2138         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2139                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2140                        dev->name, events, gfar_read(&priv->regs->imask));
2141
2142         /* Update the error counters */
2143         if (events & IEVENT_TXE) {
2144                 dev->stats.tx_errors++;
2145
2146                 if (events & IEVENT_LC)
2147                         dev->stats.tx_window_errors++;
2148                 if (events & IEVENT_CRL)
2149                         dev->stats.tx_aborted_errors++;
2150                 if (events & IEVENT_XFUN) {
2151                         if (netif_msg_tx_err(priv))
2152                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2153                                        "packet dropped.\n", dev->name);
2154                         dev->stats.tx_dropped++;
2155                         priv->extra_stats.tx_underrun++;
2156
2157                         /* Reactivate the Tx Queues */
2158                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2159                 }
2160                 if (netif_msg_tx_err(priv))
2161                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2162         }
2163         if (events & IEVENT_BSY) {
2164                 dev->stats.rx_errors++;
2165                 priv->extra_stats.rx_bsy++;
2166
2167                 gfar_receive(irq, dev_id);
2168
2169                 if (netif_msg_rx_err(priv))
2170                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2171                                dev->name, gfar_read(&priv->regs->rstat));
2172         }
2173         if (events & IEVENT_BABR) {
2174                 dev->stats.rx_errors++;
2175                 priv->extra_stats.rx_babr++;
2176
2177                 if (netif_msg_rx_err(priv))
2178                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2179         }
2180         if (events & IEVENT_EBERR) {
2181                 priv->extra_stats.eberr++;
2182                 if (netif_msg_rx_err(priv))
2183                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2184         }
2185         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2186                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2187
2188         if (events & IEVENT_BABT) {
2189                 priv->extra_stats.tx_babt++;
2190                 if (netif_msg_tx_err(priv))
2191                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2192         }
2193         return IRQ_HANDLED;
2194 }
2195
2196 /* work with hotplug and coldplug */
2197 MODULE_ALIAS("platform:fsl-gianfar");
2198
2199 static struct of_device_id gfar_match[] =
2200 {
2201         {
2202                 .type = "network",
2203                 .compatible = "gianfar",
2204         },
2205         {},
2206 };
2207
2208 /* Structure for a device driver */
2209 static struct of_platform_driver gfar_driver = {
2210         .name = "fsl-gianfar",
2211         .match_table = gfar_match,
2212
2213         .probe = gfar_probe,
2214         .remove = gfar_remove,
2215         .suspend = gfar_suspend,
2216         .resume = gfar_resume,
2217 };
2218
2219 static int __init gfar_init(void)
2220 {
2221         int err = gfar_mdio_init();
2222
2223         if (err)
2224                 return err;
2225
2226         err = of_register_platform_driver(&gfar_driver);
2227
2228         if (err)
2229                 gfar_mdio_exit();
2230
2231         return err;
2232 }
2233
2234 static void __exit gfar_exit(void)
2235 {
2236         of_unregister_platform_driver(&gfar_driver);
2237         gfar_mdio_exit();
2238 }
2239
2240 module_init(gfar_init);
2241 module_exit(gfar_exit);
2242