gianfar: Convert gianfar to an of_platform_driver
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "gianfar_mii.h"
97
98 #define TX_TIMEOUT      (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112                 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122                 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
135 static void gfar_vlan_rx_register(struct net_device *netdev,
136                                 struct vlan_group *grp);
137 void gfar_halt(struct net_device *dev);
138 static void gfar_halt_nodisable(struct net_device *dev);
139 void gfar_start(struct net_device *dev);
140 static void gfar_clear_exact_match(struct net_device *dev);
141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
142
143 extern const struct ethtool_ops gfar_ethtool_ops;
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 /* Returns 1 if incoming frames use an FCB */
150 static inline int gfar_uses_fcb(struct gfar_private *priv)
151 {
152         return (priv->vlan_enable || priv->rx_csum_enable);
153 }
154
155 static int gfar_of_init(struct net_device *dev)
156 {
157         struct device_node *phy, *mdio;
158         const unsigned int *id;
159         const char *model;
160         const char *ctype;
161         const void *mac_addr;
162         const phandle *ph;
163         u64 addr, size;
164         int err = 0;
165         struct gfar_private *priv = netdev_priv(dev);
166         struct device_node *np = priv->node;
167         char bus_name[MII_BUS_ID_SIZE];
168
169         if (!np || !of_device_is_available(np))
170                 return -ENODEV;
171
172         /* get a pointer to the register memory */
173         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
174         priv->regs = ioremap(addr, size);
175
176         if (priv->regs == NULL)
177                 return -ENOMEM;
178
179         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
180
181         model = of_get_property(np, "model", NULL);
182
183         /* If we aren't the FEC we have multiple interrupts */
184         if (model && strcasecmp(model, "FEC")) {
185                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
186
187                 priv->interruptError = irq_of_parse_and_map(np, 2);
188
189                 if (priv->interruptTransmit < 0 ||
190                                 priv->interruptReceive < 0 ||
191                                 priv->interruptError < 0) {
192                         err = -EINVAL;
193                         goto err_out;
194                 }
195         }
196
197         mac_addr = of_get_mac_address(np);
198         if (mac_addr)
199                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
200
201         if (model && !strcasecmp(model, "TSEC"))
202                 priv->device_flags =
203                         FSL_GIANFAR_DEV_HAS_GIGABIT |
204                         FSL_GIANFAR_DEV_HAS_COALESCE |
205                         FSL_GIANFAR_DEV_HAS_RMON |
206                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
207         if (model && !strcasecmp(model, "eTSEC"))
208                 priv->device_flags =
209                         FSL_GIANFAR_DEV_HAS_GIGABIT |
210                         FSL_GIANFAR_DEV_HAS_COALESCE |
211                         FSL_GIANFAR_DEV_HAS_RMON |
212                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
213                         FSL_GIANFAR_DEV_HAS_CSUM |
214                         FSL_GIANFAR_DEV_HAS_VLAN |
215                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
216                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
217
218         ctype = of_get_property(np, "phy-connection-type", NULL);
219
220         /* We only care about rgmii-id.  The rest are autodetected */
221         if (ctype && !strcmp(ctype, "rgmii-id"))
222                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
223         else
224                 priv->interface = PHY_INTERFACE_MODE_MII;
225
226         if (of_get_property(np, "fsl,magic-packet", NULL))
227                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
228
229         ph = of_get_property(np, "phy-handle", NULL);
230         if (ph == NULL) {
231                 u32 *fixed_link;
232
233                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
234                 if (!fixed_link) {
235                         err = -ENODEV;
236                         goto err_out;
237                 }
238
239                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, PHY_ID_FMT, "0",
240                                 fixed_link[0]);
241         } else {
242                 phy = of_find_node_by_phandle(*ph);
243
244                 if (phy == NULL) {
245                         err = -ENODEV;
246                         goto err_out;
247                 }
248
249                 mdio = of_get_parent(phy);
250
251                 id = of_get_property(phy, "reg", NULL);
252
253                 of_node_put(phy);
254                 of_node_put(mdio);
255
256                 gfar_mdio_bus_name(bus_name, mdio);
257                 snprintf(priv->phy_bus_id, BUS_ID_SIZE, "%s:%02x",
258                                 bus_name, *id);
259         }
260
261         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
262         ph = of_get_property(np, "tbi-handle", NULL);
263         if (ph) {
264                 struct device_node *tbi = of_find_node_by_phandle(*ph);
265                 struct of_device *ofdev;
266                 struct mii_bus *bus;
267
268                 if (!tbi)
269                         return 0;
270
271                 mdio = of_get_parent(tbi);
272                 if (!mdio)
273                         return 0;
274
275                 ofdev = of_find_device_by_node(mdio);
276
277                 of_node_put(mdio);
278
279                 id = of_get_property(tbi, "reg", NULL);
280                 if (!id)
281                         return 0;
282
283                 of_node_put(tbi);
284
285                 bus = dev_get_drvdata(&ofdev->dev);
286
287                 priv->tbiphy = bus->phy_map[*id];
288         }
289
290         return 0;
291
292 err_out:
293         iounmap(priv->regs);
294         return err;
295 }
296
297 /* Set up the ethernet device structure, private data,
298  * and anything else we need before we start */
299 static int gfar_probe(struct of_device *ofdev,
300                 const struct of_device_id *match)
301 {
302         u32 tempval;
303         struct net_device *dev = NULL;
304         struct gfar_private *priv = NULL;
305         int err = 0;
306         DECLARE_MAC_BUF(mac);
307
308         /* Create an ethernet device instance */
309         dev = alloc_etherdev(sizeof (*priv));
310
311         if (NULL == dev)
312                 return -ENOMEM;
313
314         priv = netdev_priv(dev);
315         priv->dev = dev;
316         priv->node = ofdev->node;
317
318         err = gfar_of_init(dev);
319
320         if (err)
321                 goto regs_fail;
322
323         spin_lock_init(&priv->txlock);
324         spin_lock_init(&priv->rxlock);
325         spin_lock_init(&priv->bflock);
326         INIT_WORK(&priv->reset_task, gfar_reset_task);
327
328         dev_set_drvdata(&ofdev->dev, priv);
329
330         /* Stop the DMA engine now, in case it was running before */
331         /* (The firmware could have used it, and left it running). */
332         gfar_halt(dev);
333
334         /* Reset MAC layer */
335         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
336
337         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
338         gfar_write(&priv->regs->maccfg1, tempval);
339
340         /* Initialize MACCFG2. */
341         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
342
343         /* Initialize ECNTRL */
344         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
345
346         /* Set the dev->base_addr to the gfar reg region */
347         dev->base_addr = (unsigned long) (priv->regs);
348
349         SET_NETDEV_DEV(dev, &ofdev->dev);
350
351         /* Fill in the dev structure */
352         dev->open = gfar_enet_open;
353         dev->hard_start_xmit = gfar_start_xmit;
354         dev->tx_timeout = gfar_timeout;
355         dev->watchdog_timeo = TX_TIMEOUT;
356         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
357 #ifdef CONFIG_NET_POLL_CONTROLLER
358         dev->poll_controller = gfar_netpoll;
359 #endif
360         dev->stop = gfar_close;
361         dev->change_mtu = gfar_change_mtu;
362         dev->mtu = 1500;
363         dev->set_multicast_list = gfar_set_multi;
364
365         dev->ethtool_ops = &gfar_ethtool_ops;
366
367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
368                 priv->rx_csum_enable = 1;
369                 dev->features |= NETIF_F_IP_CSUM;
370         } else
371                 priv->rx_csum_enable = 0;
372
373         priv->vlgrp = NULL;
374
375         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
376                 dev->vlan_rx_register = gfar_vlan_rx_register;
377
378                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
379
380                 priv->vlan_enable = 1;
381         }
382
383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
384                 priv->extended_hash = 1;
385                 priv->hash_width = 9;
386
387                 priv->hash_regs[0] = &priv->regs->igaddr0;
388                 priv->hash_regs[1] = &priv->regs->igaddr1;
389                 priv->hash_regs[2] = &priv->regs->igaddr2;
390                 priv->hash_regs[3] = &priv->regs->igaddr3;
391                 priv->hash_regs[4] = &priv->regs->igaddr4;
392                 priv->hash_regs[5] = &priv->regs->igaddr5;
393                 priv->hash_regs[6] = &priv->regs->igaddr6;
394                 priv->hash_regs[7] = &priv->regs->igaddr7;
395                 priv->hash_regs[8] = &priv->regs->gaddr0;
396                 priv->hash_regs[9] = &priv->regs->gaddr1;
397                 priv->hash_regs[10] = &priv->regs->gaddr2;
398                 priv->hash_regs[11] = &priv->regs->gaddr3;
399                 priv->hash_regs[12] = &priv->regs->gaddr4;
400                 priv->hash_regs[13] = &priv->regs->gaddr5;
401                 priv->hash_regs[14] = &priv->regs->gaddr6;
402                 priv->hash_regs[15] = &priv->regs->gaddr7;
403
404         } else {
405                 priv->extended_hash = 0;
406                 priv->hash_width = 8;
407
408                 priv->hash_regs[0] = &priv->regs->gaddr0;
409                 priv->hash_regs[1] = &priv->regs->gaddr1;
410                 priv->hash_regs[2] = &priv->regs->gaddr2;
411                 priv->hash_regs[3] = &priv->regs->gaddr3;
412                 priv->hash_regs[4] = &priv->regs->gaddr4;
413                 priv->hash_regs[5] = &priv->regs->gaddr5;
414                 priv->hash_regs[6] = &priv->regs->gaddr6;
415                 priv->hash_regs[7] = &priv->regs->gaddr7;
416         }
417
418         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
419                 priv->padding = DEFAULT_PADDING;
420         else
421                 priv->padding = 0;
422
423         if (dev->features & NETIF_F_IP_CSUM)
424                 dev->hard_header_len += GMAC_FCB_LEN;
425
426         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
427         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
428         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
429
430         priv->txcoalescing = DEFAULT_TX_COALESCE;
431         priv->txcount = DEFAULT_TXCOUNT;
432         priv->txtime = DEFAULT_TXTIME;
433         priv->rxcoalescing = DEFAULT_RX_COALESCE;
434         priv->rxcount = DEFAULT_RXCOUNT;
435         priv->rxtime = DEFAULT_RXTIME;
436
437         /* Enable most messages by default */
438         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
439
440         /* Carrier starts down, phylib will bring it up */
441         netif_carrier_off(dev);
442
443         err = register_netdev(dev);
444
445         if (err) {
446                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
447                                 dev->name);
448                 goto register_fail;
449         }
450
451         /* Create all the sysfs files */
452         gfar_init_sysfs(dev);
453
454         /* Print out the device info */
455         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
456
457         /* Even more device info helps when determining which kernel */
458         /* provided which set of benchmarks. */
459         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
460         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
461                dev->name, priv->rx_ring_size, priv->tx_ring_size);
462
463         return 0;
464
465 register_fail:
466         iounmap(priv->regs);
467 regs_fail:
468         free_netdev(dev);
469         return err;
470 }
471
472 static int gfar_remove(struct of_device *ofdev)
473 {
474         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
475
476         dev_set_drvdata(&ofdev->dev, NULL);
477
478         iounmap(priv->regs);
479         free_netdev(priv->dev);
480
481         return 0;
482 }
483
484 #ifdef CONFIG_PM
485 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
486 {
487         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
488         struct net_device *dev = priv->dev;
489         unsigned long flags;
490         u32 tempval;
491
492         int magic_packet = priv->wol_en &&
493                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
494
495         netif_device_detach(dev);
496
497         if (netif_running(dev)) {
498                 spin_lock_irqsave(&priv->txlock, flags);
499                 spin_lock(&priv->rxlock);
500
501                 gfar_halt_nodisable(dev);
502
503                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
504                 tempval = gfar_read(&priv->regs->maccfg1);
505
506                 tempval &= ~MACCFG1_TX_EN;
507
508                 if (!magic_packet)
509                         tempval &= ~MACCFG1_RX_EN;
510
511                 gfar_write(&priv->regs->maccfg1, tempval);
512
513                 spin_unlock(&priv->rxlock);
514                 spin_unlock_irqrestore(&priv->txlock, flags);
515
516                 napi_disable(&priv->napi);
517
518                 if (magic_packet) {
519                         /* Enable interrupt on Magic Packet */
520                         gfar_write(&priv->regs->imask, IMASK_MAG);
521
522                         /* Enable Magic Packet mode */
523                         tempval = gfar_read(&priv->regs->maccfg2);
524                         tempval |= MACCFG2_MPEN;
525                         gfar_write(&priv->regs->maccfg2, tempval);
526                 } else {
527                         phy_stop(priv->phydev);
528                 }
529         }
530
531         return 0;
532 }
533
534 static int gfar_resume(struct of_device *ofdev)
535 {
536         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
537         struct net_device *dev = priv->dev;
538         unsigned long flags;
539         u32 tempval;
540         int magic_packet = priv->wol_en &&
541                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
542
543         if (!netif_running(dev)) {
544                 netif_device_attach(dev);
545                 return 0;
546         }
547
548         if (!magic_packet && priv->phydev)
549                 phy_start(priv->phydev);
550
551         /* Disable Magic Packet mode, in case something
552          * else woke us up.
553          */
554
555         spin_lock_irqsave(&priv->txlock, flags);
556         spin_lock(&priv->rxlock);
557
558         tempval = gfar_read(&priv->regs->maccfg2);
559         tempval &= ~MACCFG2_MPEN;
560         gfar_write(&priv->regs->maccfg2, tempval);
561
562         gfar_start(dev);
563
564         spin_unlock(&priv->rxlock);
565         spin_unlock_irqrestore(&priv->txlock, flags);
566
567         netif_device_attach(dev);
568
569         napi_enable(&priv->napi);
570
571         return 0;
572 }
573 #else
574 #define gfar_suspend NULL
575 #define gfar_resume NULL
576 #endif
577
578 /* Reads the controller's registers to determine what interface
579  * connects it to the PHY.
580  */
581 static phy_interface_t gfar_get_interface(struct net_device *dev)
582 {
583         struct gfar_private *priv = netdev_priv(dev);
584         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
585
586         if (ecntrl & ECNTRL_SGMII_MODE)
587                 return PHY_INTERFACE_MODE_SGMII;
588
589         if (ecntrl & ECNTRL_TBI_MODE) {
590                 if (ecntrl & ECNTRL_REDUCED_MODE)
591                         return PHY_INTERFACE_MODE_RTBI;
592                 else
593                         return PHY_INTERFACE_MODE_TBI;
594         }
595
596         if (ecntrl & ECNTRL_REDUCED_MODE) {
597                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
598                         return PHY_INTERFACE_MODE_RMII;
599                 else {
600                         phy_interface_t interface = priv->interface;
601
602                         /*
603                          * This isn't autodetected right now, so it must
604                          * be set by the device tree or platform code.
605                          */
606                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
607                                 return PHY_INTERFACE_MODE_RGMII_ID;
608
609                         return PHY_INTERFACE_MODE_RGMII;
610                 }
611         }
612
613         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
614                 return PHY_INTERFACE_MODE_GMII;
615
616         return PHY_INTERFACE_MODE_MII;
617 }
618
619
620 /* Initializes driver's PHY state, and attaches to the PHY.
621  * Returns 0 on success.
622  */
623 static int init_phy(struct net_device *dev)
624 {
625         struct gfar_private *priv = netdev_priv(dev);
626         uint gigabit_support =
627                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
628                 SUPPORTED_1000baseT_Full : 0;
629         struct phy_device *phydev;
630         phy_interface_t interface;
631
632         priv->oldlink = 0;
633         priv->oldspeed = 0;
634         priv->oldduplex = -1;
635
636         interface = gfar_get_interface(dev);
637
638         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
639
640         if (interface == PHY_INTERFACE_MODE_SGMII)
641                 gfar_configure_serdes(dev);
642
643         if (IS_ERR(phydev)) {
644                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
645                 return PTR_ERR(phydev);
646         }
647
648         /* Remove any features not supported by the controller */
649         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
650         phydev->advertising = phydev->supported;
651
652         priv->phydev = phydev;
653
654         return 0;
655 }
656
657 /*
658  * Initialize TBI PHY interface for communicating with the
659  * SERDES lynx PHY on the chip.  We communicate with this PHY
660  * through the MDIO bus on each controller, treating it as a
661  * "normal" PHY at the address found in the TBIPA register.  We assume
662  * that the TBIPA register is valid.  Either the MDIO bus code will set
663  * it to a value that doesn't conflict with other PHYs on the bus, or the
664  * value doesn't matter, as there are no other PHYs on the bus.
665  */
666 static void gfar_configure_serdes(struct net_device *dev)
667 {
668         struct gfar_private *priv = netdev_priv(dev);
669
670         if (!priv->tbiphy) {
671                 printk(KERN_WARNING "SGMII mode requires that the device "
672                                 "tree specify a tbi-handle\n");
673                 return;
674         }
675
676         /*
677          * If the link is already up, we must already be ok, and don't need to
678          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
679          * everything for us?  Resetting it takes the link down and requires
680          * several seconds for it to come back.
681          */
682         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
683                 return;
684
685         /* Single clk mode, mii mode off(for serdes communication) */
686         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
687
688         phy_write(priv->tbiphy, MII_ADVERTISE,
689                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
690                         ADVERTISE_1000XPSE_ASYM);
691
692         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
693                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
694 }
695
696 static void init_registers(struct net_device *dev)
697 {
698         struct gfar_private *priv = netdev_priv(dev);
699
700         /* Clear IEVENT */
701         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
702
703         /* Initialize IMASK */
704         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
705
706         /* Init hash registers to zero */
707         gfar_write(&priv->regs->igaddr0, 0);
708         gfar_write(&priv->regs->igaddr1, 0);
709         gfar_write(&priv->regs->igaddr2, 0);
710         gfar_write(&priv->regs->igaddr3, 0);
711         gfar_write(&priv->regs->igaddr4, 0);
712         gfar_write(&priv->regs->igaddr5, 0);
713         gfar_write(&priv->regs->igaddr6, 0);
714         gfar_write(&priv->regs->igaddr7, 0);
715
716         gfar_write(&priv->regs->gaddr0, 0);
717         gfar_write(&priv->regs->gaddr1, 0);
718         gfar_write(&priv->regs->gaddr2, 0);
719         gfar_write(&priv->regs->gaddr3, 0);
720         gfar_write(&priv->regs->gaddr4, 0);
721         gfar_write(&priv->regs->gaddr5, 0);
722         gfar_write(&priv->regs->gaddr6, 0);
723         gfar_write(&priv->regs->gaddr7, 0);
724
725         /* Zero out the rmon mib registers if it has them */
726         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
727                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
728
729                 /* Mask off the CAM interrupts */
730                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
731                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
732         }
733
734         /* Initialize the max receive buffer length */
735         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
736
737         /* Initialize the Minimum Frame Length Register */
738         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
739 }
740
741
742 /* Halt the receive and transmit queues */
743 static void gfar_halt_nodisable(struct net_device *dev)
744 {
745         struct gfar_private *priv = netdev_priv(dev);
746         struct gfar __iomem *regs = priv->regs;
747         u32 tempval;
748
749         /* Mask all interrupts */
750         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
751
752         /* Clear all interrupts */
753         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
754
755         /* Stop the DMA, and wait for it to stop */
756         tempval = gfar_read(&priv->regs->dmactrl);
757         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
758             != (DMACTRL_GRS | DMACTRL_GTS)) {
759                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
760                 gfar_write(&priv->regs->dmactrl, tempval);
761
762                 while (!(gfar_read(&priv->regs->ievent) &
763                          (IEVENT_GRSC | IEVENT_GTSC)))
764                         cpu_relax();
765         }
766 }
767
768 /* Halt the receive and transmit queues */
769 void gfar_halt(struct net_device *dev)
770 {
771         struct gfar_private *priv = netdev_priv(dev);
772         struct gfar __iomem *regs = priv->regs;
773         u32 tempval;
774
775         gfar_halt_nodisable(dev);
776
777         /* Disable Rx and Tx */
778         tempval = gfar_read(&regs->maccfg1);
779         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
780         gfar_write(&regs->maccfg1, tempval);
781 }
782
783 void stop_gfar(struct net_device *dev)
784 {
785         struct gfar_private *priv = netdev_priv(dev);
786         struct gfar __iomem *regs = priv->regs;
787         unsigned long flags;
788
789         phy_stop(priv->phydev);
790
791         /* Lock it down */
792         spin_lock_irqsave(&priv->txlock, flags);
793         spin_lock(&priv->rxlock);
794
795         gfar_halt(dev);
796
797         spin_unlock(&priv->rxlock);
798         spin_unlock_irqrestore(&priv->txlock, flags);
799
800         /* Free the IRQs */
801         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
802                 free_irq(priv->interruptError, dev);
803                 free_irq(priv->interruptTransmit, dev);
804                 free_irq(priv->interruptReceive, dev);
805         } else {
806                 free_irq(priv->interruptTransmit, dev);
807         }
808
809         free_skb_resources(priv);
810
811         dma_free_coherent(&dev->dev,
812                         sizeof(struct txbd8)*priv->tx_ring_size
813                         + sizeof(struct rxbd8)*priv->rx_ring_size,
814                         priv->tx_bd_base,
815                         gfar_read(&regs->tbase0));
816 }
817
818 /* If there are any tx skbs or rx skbs still around, free them.
819  * Then free tx_skbuff and rx_skbuff */
820 static void free_skb_resources(struct gfar_private *priv)
821 {
822         struct rxbd8 *rxbdp;
823         struct txbd8 *txbdp;
824         int i;
825
826         /* Go through all the buffer descriptors and free their data buffers */
827         txbdp = priv->tx_bd_base;
828
829         for (i = 0; i < priv->tx_ring_size; i++) {
830
831                 if (priv->tx_skbuff[i]) {
832                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
833                                         txbdp->length,
834                                         DMA_TO_DEVICE);
835                         dev_kfree_skb_any(priv->tx_skbuff[i]);
836                         priv->tx_skbuff[i] = NULL;
837                 }
838
839                 txbdp++;
840         }
841
842         kfree(priv->tx_skbuff);
843
844         rxbdp = priv->rx_bd_base;
845
846         /* rx_skbuff is not guaranteed to be allocated, so only
847          * free it and its contents if it is allocated */
848         if(priv->rx_skbuff != NULL) {
849                 for (i = 0; i < priv->rx_ring_size; i++) {
850                         if (priv->rx_skbuff[i]) {
851                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
852                                                 priv->rx_buffer_size,
853                                                 DMA_FROM_DEVICE);
854
855                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
856                                 priv->rx_skbuff[i] = NULL;
857                         }
858
859                         rxbdp->status = 0;
860                         rxbdp->length = 0;
861                         rxbdp->bufPtr = 0;
862
863                         rxbdp++;
864                 }
865
866                 kfree(priv->rx_skbuff);
867         }
868 }
869
870 void gfar_start(struct net_device *dev)
871 {
872         struct gfar_private *priv = netdev_priv(dev);
873         struct gfar __iomem *regs = priv->regs;
874         u32 tempval;
875
876         /* Enable Rx and Tx in MACCFG1 */
877         tempval = gfar_read(&regs->maccfg1);
878         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
879         gfar_write(&regs->maccfg1, tempval);
880
881         /* Initialize DMACTRL to have WWR and WOP */
882         tempval = gfar_read(&priv->regs->dmactrl);
883         tempval |= DMACTRL_INIT_SETTINGS;
884         gfar_write(&priv->regs->dmactrl, tempval);
885
886         /* Make sure we aren't stopped */
887         tempval = gfar_read(&priv->regs->dmactrl);
888         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
889         gfar_write(&priv->regs->dmactrl, tempval);
890
891         /* Clear THLT/RHLT, so that the DMA starts polling now */
892         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
893         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
894
895         /* Unmask the interrupts we look for */
896         gfar_write(&regs->imask, IMASK_DEFAULT);
897 }
898
899 /* Bring the controller up and running */
900 int startup_gfar(struct net_device *dev)
901 {
902         struct txbd8 *txbdp;
903         struct rxbd8 *rxbdp;
904         dma_addr_t addr = 0;
905         unsigned long vaddr;
906         int i;
907         struct gfar_private *priv = netdev_priv(dev);
908         struct gfar __iomem *regs = priv->regs;
909         int err = 0;
910         u32 rctrl = 0;
911         u32 attrs = 0;
912
913         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
914
915         /* Allocate memory for the buffer descriptors */
916         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
917                         sizeof (struct txbd8) * priv->tx_ring_size +
918                         sizeof (struct rxbd8) * priv->rx_ring_size,
919                         &addr, GFP_KERNEL);
920
921         if (vaddr == 0) {
922                 if (netif_msg_ifup(priv))
923                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
924                                         dev->name);
925                 return -ENOMEM;
926         }
927
928         priv->tx_bd_base = (struct txbd8 *) vaddr;
929
930         /* enet DMA only understands physical addresses */
931         gfar_write(&regs->tbase0, addr);
932
933         /* Start the rx descriptor ring where the tx ring leaves off */
934         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
935         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
936         priv->rx_bd_base = (struct rxbd8 *) vaddr;
937         gfar_write(&regs->rbase0, addr);
938
939         /* Setup the skbuff rings */
940         priv->tx_skbuff =
941             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
942                                         priv->tx_ring_size, GFP_KERNEL);
943
944         if (NULL == priv->tx_skbuff) {
945                 if (netif_msg_ifup(priv))
946                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
947                                         dev->name);
948                 err = -ENOMEM;
949                 goto tx_skb_fail;
950         }
951
952         for (i = 0; i < priv->tx_ring_size; i++)
953                 priv->tx_skbuff[i] = NULL;
954
955         priv->rx_skbuff =
956             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
957                                         priv->rx_ring_size, GFP_KERNEL);
958
959         if (NULL == priv->rx_skbuff) {
960                 if (netif_msg_ifup(priv))
961                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
962                                         dev->name);
963                 err = -ENOMEM;
964                 goto rx_skb_fail;
965         }
966
967         for (i = 0; i < priv->rx_ring_size; i++)
968                 priv->rx_skbuff[i] = NULL;
969
970         /* Initialize some variables in our dev structure */
971         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
972         priv->cur_rx = priv->rx_bd_base;
973         priv->skb_curtx = priv->skb_dirtytx = 0;
974         priv->skb_currx = 0;
975
976         /* Initialize Transmit Descriptor Ring */
977         txbdp = priv->tx_bd_base;
978         for (i = 0; i < priv->tx_ring_size; i++) {
979                 txbdp->status = 0;
980                 txbdp->length = 0;
981                 txbdp->bufPtr = 0;
982                 txbdp++;
983         }
984
985         /* Set the last descriptor in the ring to indicate wrap */
986         txbdp--;
987         txbdp->status |= TXBD_WRAP;
988
989         rxbdp = priv->rx_bd_base;
990         for (i = 0; i < priv->rx_ring_size; i++) {
991                 struct sk_buff *skb;
992
993                 skb = gfar_new_skb(dev);
994
995                 if (!skb) {
996                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
997                                         dev->name);
998
999                         goto err_rxalloc_fail;
1000                 }
1001
1002                 priv->rx_skbuff[i] = skb;
1003
1004                 gfar_new_rxbdp(dev, rxbdp, skb);
1005
1006                 rxbdp++;
1007         }
1008
1009         /* Set the last descriptor in the ring to wrap */
1010         rxbdp--;
1011         rxbdp->status |= RXBD_WRAP;
1012
1013         /* If the device has multiple interrupts, register for
1014          * them.  Otherwise, only register for the one */
1015         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1016                 /* Install our interrupt handlers for Error,
1017                  * Transmit, and Receive */
1018                 if (request_irq(priv->interruptError, gfar_error,
1019                                 0, "enet_error", dev) < 0) {
1020                         if (netif_msg_intr(priv))
1021                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1022                                         dev->name, priv->interruptError);
1023
1024                         err = -1;
1025                         goto err_irq_fail;
1026                 }
1027
1028                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1029                                 0, "enet_tx", dev) < 0) {
1030                         if (netif_msg_intr(priv))
1031                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1032                                         dev->name, priv->interruptTransmit);
1033
1034                         err = -1;
1035
1036                         goto tx_irq_fail;
1037                 }
1038
1039                 if (request_irq(priv->interruptReceive, gfar_receive,
1040                                 0, "enet_rx", dev) < 0) {
1041                         if (netif_msg_intr(priv))
1042                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1043                                                 dev->name, priv->interruptReceive);
1044
1045                         err = -1;
1046                         goto rx_irq_fail;
1047                 }
1048         } else {
1049                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1050                                 0, "gfar_interrupt", dev) < 0) {
1051                         if (netif_msg_intr(priv))
1052                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1053                                         dev->name, priv->interruptError);
1054
1055                         err = -1;
1056                         goto err_irq_fail;
1057                 }
1058         }
1059
1060         phy_start(priv->phydev);
1061
1062         /* Configure the coalescing support */
1063         if (priv->txcoalescing)
1064                 gfar_write(&regs->txic,
1065                            mk_ic_value(priv->txcount, priv->txtime));
1066         else
1067                 gfar_write(&regs->txic, 0);
1068
1069         if (priv->rxcoalescing)
1070                 gfar_write(&regs->rxic,
1071                            mk_ic_value(priv->rxcount, priv->rxtime));
1072         else
1073                 gfar_write(&regs->rxic, 0);
1074
1075         if (priv->rx_csum_enable)
1076                 rctrl |= RCTRL_CHECKSUMMING;
1077
1078         if (priv->extended_hash) {
1079                 rctrl |= RCTRL_EXTHASH;
1080
1081                 gfar_clear_exact_match(dev);
1082                 rctrl |= RCTRL_EMEN;
1083         }
1084
1085         if (priv->vlan_enable)
1086                 rctrl |= RCTRL_VLAN;
1087
1088         if (priv->padding) {
1089                 rctrl &= ~RCTRL_PAL_MASK;
1090                 rctrl |= RCTRL_PADDING(priv->padding);
1091         }
1092
1093         /* Init rctrl based on our settings */
1094         gfar_write(&priv->regs->rctrl, rctrl);
1095
1096         if (dev->features & NETIF_F_IP_CSUM)
1097                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1098
1099         /* Set the extraction length and index */
1100         attrs = ATTRELI_EL(priv->rx_stash_size) |
1101                 ATTRELI_EI(priv->rx_stash_index);
1102
1103         gfar_write(&priv->regs->attreli, attrs);
1104
1105         /* Start with defaults, and add stashing or locking
1106          * depending on the approprate variables */
1107         attrs = ATTR_INIT_SETTINGS;
1108
1109         if (priv->bd_stash_en)
1110                 attrs |= ATTR_BDSTASH;
1111
1112         if (priv->rx_stash_size != 0)
1113                 attrs |= ATTR_BUFSTASH;
1114
1115         gfar_write(&priv->regs->attr, attrs);
1116
1117         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1118         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1119         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1120
1121         /* Start the controller */
1122         gfar_start(dev);
1123
1124         return 0;
1125
1126 rx_irq_fail:
1127         free_irq(priv->interruptTransmit, dev);
1128 tx_irq_fail:
1129         free_irq(priv->interruptError, dev);
1130 err_irq_fail:
1131 err_rxalloc_fail:
1132 rx_skb_fail:
1133         free_skb_resources(priv);
1134 tx_skb_fail:
1135         dma_free_coherent(&dev->dev,
1136                         sizeof(struct txbd8)*priv->tx_ring_size
1137                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1138                         priv->tx_bd_base,
1139                         gfar_read(&regs->tbase0));
1140
1141         return err;
1142 }
1143
1144 /* Called when something needs to use the ethernet device */
1145 /* Returns 0 for success. */
1146 static int gfar_enet_open(struct net_device *dev)
1147 {
1148         struct gfar_private *priv = netdev_priv(dev);
1149         int err;
1150
1151         napi_enable(&priv->napi);
1152
1153         /* Initialize a bunch of registers */
1154         init_registers(dev);
1155
1156         gfar_set_mac_address(dev);
1157
1158         err = init_phy(dev);
1159
1160         if(err) {
1161                 napi_disable(&priv->napi);
1162                 return err;
1163         }
1164
1165         err = startup_gfar(dev);
1166         if (err) {
1167                 napi_disable(&priv->napi);
1168                 return err;
1169         }
1170
1171         netif_start_queue(dev);
1172
1173         return err;
1174 }
1175
1176 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1177 {
1178         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1179
1180         memset(fcb, 0, GMAC_FCB_LEN);
1181
1182         return fcb;
1183 }
1184
1185 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1186 {
1187         u8 flags = 0;
1188
1189         /* If we're here, it's a IP packet with a TCP or UDP
1190          * payload.  We set it to checksum, using a pseudo-header
1191          * we provide
1192          */
1193         flags = TXFCB_DEFAULT;
1194
1195         /* Tell the controller what the protocol is */
1196         /* And provide the already calculated phcs */
1197         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1198                 flags |= TXFCB_UDP;
1199                 fcb->phcs = udp_hdr(skb)->check;
1200         } else
1201                 fcb->phcs = tcp_hdr(skb)->check;
1202
1203         /* l3os is the distance between the start of the
1204          * frame (skb->data) and the start of the IP hdr.
1205          * l4os is the distance between the start of the
1206          * l3 hdr and the l4 hdr */
1207         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1208         fcb->l4os = skb_network_header_len(skb);
1209
1210         fcb->flags = flags;
1211 }
1212
1213 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1214 {
1215         fcb->flags |= TXFCB_VLN;
1216         fcb->vlctl = vlan_tx_tag_get(skb);
1217 }
1218
1219 /* This is called by the kernel when a frame is ready for transmission. */
1220 /* It is pointed to by the dev->hard_start_xmit function pointer */
1221 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1222 {
1223         struct gfar_private *priv = netdev_priv(dev);
1224         struct txfcb *fcb = NULL;
1225         struct txbd8 *txbdp;
1226         u16 status;
1227         unsigned long flags;
1228
1229         /* Update transmit stats */
1230         dev->stats.tx_bytes += skb->len;
1231
1232         /* Lock priv now */
1233         spin_lock_irqsave(&priv->txlock, flags);
1234
1235         /* Point at the first free tx descriptor */
1236         txbdp = priv->cur_tx;
1237
1238         /* Clear all but the WRAP status flags */
1239         status = txbdp->status & TXBD_WRAP;
1240
1241         /* Set up checksumming */
1242         if (likely((dev->features & NETIF_F_IP_CSUM)
1243                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1244                 fcb = gfar_add_fcb(skb, txbdp);
1245                 status |= TXBD_TOE;
1246                 gfar_tx_checksum(skb, fcb);
1247         }
1248
1249         if (priv->vlan_enable &&
1250                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1251                 if (unlikely(NULL == fcb)) {
1252                         fcb = gfar_add_fcb(skb, txbdp);
1253                         status |= TXBD_TOE;
1254                 }
1255
1256                 gfar_tx_vlan(skb, fcb);
1257         }
1258
1259         /* Set buffer length and pointer */
1260         txbdp->length = skb->len;
1261         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1262                         skb->len, DMA_TO_DEVICE);
1263
1264         /* Save the skb pointer so we can free it later */
1265         priv->tx_skbuff[priv->skb_curtx] = skb;
1266
1267         /* Update the current skb pointer (wrapping if this was the last) */
1268         priv->skb_curtx =
1269             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1270
1271         /* Flag the BD as interrupt-causing */
1272         status |= TXBD_INTERRUPT;
1273
1274         /* Flag the BD as ready to go, last in frame, and  */
1275         /* in need of CRC */
1276         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1277
1278         dev->trans_start = jiffies;
1279
1280         /* The powerpc-specific eieio() is used, as wmb() has too strong
1281          * semantics (it requires synchronization between cacheable and
1282          * uncacheable mappings, which eieio doesn't provide and which we
1283          * don't need), thus requiring a more expensive sync instruction.  At
1284          * some point, the set of architecture-independent barrier functions
1285          * should be expanded to include weaker barriers.
1286          */
1287
1288         eieio();
1289         txbdp->status = status;
1290
1291         /* If this was the last BD in the ring, the next one */
1292         /* is at the beginning of the ring */
1293         if (txbdp->status & TXBD_WRAP)
1294                 txbdp = priv->tx_bd_base;
1295         else
1296                 txbdp++;
1297
1298         /* If the next BD still needs to be cleaned up, then the bds
1299            are full.  We need to tell the kernel to stop sending us stuff. */
1300         if (txbdp == priv->dirty_tx) {
1301                 netif_stop_queue(dev);
1302
1303                 dev->stats.tx_fifo_errors++;
1304         }
1305
1306         /* Update the current txbd to the next one */
1307         priv->cur_tx = txbdp;
1308
1309         /* Tell the DMA to go go go */
1310         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1311
1312         /* Unlock priv */
1313         spin_unlock_irqrestore(&priv->txlock, flags);
1314
1315         return 0;
1316 }
1317
1318 /* Stops the kernel queue, and halts the controller */
1319 static int gfar_close(struct net_device *dev)
1320 {
1321         struct gfar_private *priv = netdev_priv(dev);
1322
1323         napi_disable(&priv->napi);
1324
1325         cancel_work_sync(&priv->reset_task);
1326         stop_gfar(dev);
1327
1328         /* Disconnect from the PHY */
1329         phy_disconnect(priv->phydev);
1330         priv->phydev = NULL;
1331
1332         netif_stop_queue(dev);
1333
1334         return 0;
1335 }
1336
1337 /* Changes the mac address if the controller is not running. */
1338 static int gfar_set_mac_address(struct net_device *dev)
1339 {
1340         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1341
1342         return 0;
1343 }
1344
1345
1346 /* Enables and disables VLAN insertion/extraction */
1347 static void gfar_vlan_rx_register(struct net_device *dev,
1348                 struct vlan_group *grp)
1349 {
1350         struct gfar_private *priv = netdev_priv(dev);
1351         unsigned long flags;
1352         u32 tempval;
1353
1354         spin_lock_irqsave(&priv->rxlock, flags);
1355
1356         priv->vlgrp = grp;
1357
1358         if (grp) {
1359                 /* Enable VLAN tag insertion */
1360                 tempval = gfar_read(&priv->regs->tctrl);
1361                 tempval |= TCTRL_VLINS;
1362
1363                 gfar_write(&priv->regs->tctrl, tempval);
1364
1365                 /* Enable VLAN tag extraction */
1366                 tempval = gfar_read(&priv->regs->rctrl);
1367                 tempval |= RCTRL_VLEX;
1368                 gfar_write(&priv->regs->rctrl, tempval);
1369         } else {
1370                 /* Disable VLAN tag insertion */
1371                 tempval = gfar_read(&priv->regs->tctrl);
1372                 tempval &= ~TCTRL_VLINS;
1373                 gfar_write(&priv->regs->tctrl, tempval);
1374
1375                 /* Disable VLAN tag extraction */
1376                 tempval = gfar_read(&priv->regs->rctrl);
1377                 tempval &= ~RCTRL_VLEX;
1378                 gfar_write(&priv->regs->rctrl, tempval);
1379         }
1380
1381         spin_unlock_irqrestore(&priv->rxlock, flags);
1382 }
1383
1384 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1385 {
1386         int tempsize, tempval;
1387         struct gfar_private *priv = netdev_priv(dev);
1388         int oldsize = priv->rx_buffer_size;
1389         int frame_size = new_mtu + ETH_HLEN;
1390
1391         if (priv->vlan_enable)
1392                 frame_size += VLAN_HLEN;
1393
1394         if (gfar_uses_fcb(priv))
1395                 frame_size += GMAC_FCB_LEN;
1396
1397         frame_size += priv->padding;
1398
1399         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1400                 if (netif_msg_drv(priv))
1401                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1402                                         dev->name);
1403                 return -EINVAL;
1404         }
1405
1406         tempsize =
1407             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1408             INCREMENTAL_BUFFER_SIZE;
1409
1410         /* Only stop and start the controller if it isn't already
1411          * stopped, and we changed something */
1412         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1413                 stop_gfar(dev);
1414
1415         priv->rx_buffer_size = tempsize;
1416
1417         dev->mtu = new_mtu;
1418
1419         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1420         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1421
1422         /* If the mtu is larger than the max size for standard
1423          * ethernet frames (ie, a jumbo frame), then set maccfg2
1424          * to allow huge frames, and to check the length */
1425         tempval = gfar_read(&priv->regs->maccfg2);
1426
1427         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1428                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1429         else
1430                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1431
1432         gfar_write(&priv->regs->maccfg2, tempval);
1433
1434         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1435                 startup_gfar(dev);
1436
1437         return 0;
1438 }
1439
1440 /* gfar_reset_task gets scheduled when a packet has not been
1441  * transmitted after a set amount of time.
1442  * For now, assume that clearing out all the structures, and
1443  * starting over will fix the problem.
1444  */
1445 static void gfar_reset_task(struct work_struct *work)
1446 {
1447         struct gfar_private *priv = container_of(work, struct gfar_private,
1448                         reset_task);
1449         struct net_device *dev = priv->dev;
1450
1451         if (dev->flags & IFF_UP) {
1452                 stop_gfar(dev);
1453                 startup_gfar(dev);
1454         }
1455
1456         netif_tx_schedule_all(dev);
1457 }
1458
1459 static void gfar_timeout(struct net_device *dev)
1460 {
1461         struct gfar_private *priv = netdev_priv(dev);
1462
1463         dev->stats.tx_errors++;
1464         schedule_work(&priv->reset_task);
1465 }
1466
1467 /* Interrupt Handler for Transmit complete */
1468 static int gfar_clean_tx_ring(struct net_device *dev)
1469 {
1470         struct txbd8 *bdp;
1471         struct gfar_private *priv = netdev_priv(dev);
1472         int howmany = 0;
1473
1474         bdp = priv->dirty_tx;
1475         while ((bdp->status & TXBD_READY) == 0) {
1476                 /* If dirty_tx and cur_tx are the same, then either the */
1477                 /* ring is empty or full now (it could only be full in the beginning, */
1478                 /* obviously).  If it is empty, we are done. */
1479                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1480                         break;
1481
1482                 howmany++;
1483
1484                 /* Deferred means some collisions occurred during transmit, */
1485                 /* but we eventually sent the packet. */
1486                 if (bdp->status & TXBD_DEF)
1487                         dev->stats.collisions++;
1488
1489                 /* Unmap the DMA memory */
1490                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1491                                 bdp->length, DMA_TO_DEVICE);
1492
1493                 /* Free the sk buffer associated with this TxBD */
1494                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1495
1496                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1497                 priv->skb_dirtytx =
1498                     (priv->skb_dirtytx +
1499                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1500
1501                 /* Clean BD length for empty detection */
1502                 bdp->length = 0;
1503
1504                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1505                 if (bdp->status & TXBD_WRAP)
1506                         bdp = priv->tx_bd_base;
1507                 else
1508                         bdp++;
1509
1510                 /* Move dirty_tx to be the next bd */
1511                 priv->dirty_tx = bdp;
1512
1513                 /* We freed a buffer, so now we can restart transmission */
1514                 if (netif_queue_stopped(dev))
1515                         netif_wake_queue(dev);
1516         } /* while ((bdp->status & TXBD_READY) == 0) */
1517
1518         dev->stats.tx_packets += howmany;
1519
1520         return howmany;
1521 }
1522
1523 /* Interrupt Handler for Transmit complete */
1524 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1525 {
1526         struct net_device *dev = (struct net_device *) dev_id;
1527         struct gfar_private *priv = netdev_priv(dev);
1528
1529         /* Clear IEVENT */
1530         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1531
1532         /* Lock priv */
1533         spin_lock(&priv->txlock);
1534
1535         gfar_clean_tx_ring(dev);
1536
1537         /* If we are coalescing the interrupts, reset the timer */
1538         /* Otherwise, clear it */
1539         if (likely(priv->txcoalescing)) {
1540                 gfar_write(&priv->regs->txic, 0);
1541                 gfar_write(&priv->regs->txic,
1542                            mk_ic_value(priv->txcount, priv->txtime));
1543         }
1544
1545         spin_unlock(&priv->txlock);
1546
1547         return IRQ_HANDLED;
1548 }
1549
1550 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1551                 struct sk_buff *skb)
1552 {
1553         struct gfar_private *priv = netdev_priv(dev);
1554         u32 * status_len = (u32 *)bdp;
1555         u16 flags;
1556
1557         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1558                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1559
1560         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1561
1562         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1563                 flags |= RXBD_WRAP;
1564
1565         eieio();
1566
1567         *status_len = (u32)flags << 16;
1568 }
1569
1570
1571 struct sk_buff * gfar_new_skb(struct net_device *dev)
1572 {
1573         unsigned int alignamount;
1574         struct gfar_private *priv = netdev_priv(dev);
1575         struct sk_buff *skb = NULL;
1576
1577         /* We have to allocate the skb, so keep trying till we succeed */
1578         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1579
1580         if (!skb)
1581                 return NULL;
1582
1583         alignamount = RXBUF_ALIGNMENT -
1584                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1585
1586         /* We need the data buffer to be aligned properly.  We will reserve
1587          * as many bytes as needed to align the data properly
1588          */
1589         skb_reserve(skb, alignamount);
1590
1591         return skb;
1592 }
1593
1594 static inline void count_errors(unsigned short status, struct net_device *dev)
1595 {
1596         struct gfar_private *priv = netdev_priv(dev);
1597         struct net_device_stats *stats = &dev->stats;
1598         struct gfar_extra_stats *estats = &priv->extra_stats;
1599
1600         /* If the packet was truncated, none of the other errors
1601          * matter */
1602         if (status & RXBD_TRUNCATED) {
1603                 stats->rx_length_errors++;
1604
1605                 estats->rx_trunc++;
1606
1607                 return;
1608         }
1609         /* Count the errors, if there were any */
1610         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1611                 stats->rx_length_errors++;
1612
1613                 if (status & RXBD_LARGE)
1614                         estats->rx_large++;
1615                 else
1616                         estats->rx_short++;
1617         }
1618         if (status & RXBD_NONOCTET) {
1619                 stats->rx_frame_errors++;
1620                 estats->rx_nonoctet++;
1621         }
1622         if (status & RXBD_CRCERR) {
1623                 estats->rx_crcerr++;
1624                 stats->rx_crc_errors++;
1625         }
1626         if (status & RXBD_OVERRUN) {
1627                 estats->rx_overrun++;
1628                 stats->rx_crc_errors++;
1629         }
1630 }
1631
1632 irqreturn_t gfar_receive(int irq, void *dev_id)
1633 {
1634         struct net_device *dev = (struct net_device *) dev_id;
1635         struct gfar_private *priv = netdev_priv(dev);
1636         u32 tempval;
1637
1638         /* support NAPI */
1639         /* Clear IEVENT, so interrupts aren't called again
1640          * because of the packets that have already arrived */
1641         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1642
1643         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1644                 tempval = gfar_read(&priv->regs->imask);
1645                 tempval &= IMASK_RTX_DISABLED;
1646                 gfar_write(&priv->regs->imask, tempval);
1647
1648                 __netif_rx_schedule(dev, &priv->napi);
1649         } else {
1650                 if (netif_msg_rx_err(priv))
1651                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1652                                 dev->name, gfar_read(&priv->regs->ievent),
1653                                 gfar_read(&priv->regs->imask));
1654         }
1655
1656         return IRQ_HANDLED;
1657 }
1658
1659 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1660 {
1661         /* If valid headers were found, and valid sums
1662          * were verified, then we tell the kernel that no
1663          * checksumming is necessary.  Otherwise, it is */
1664         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1665                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1666         else
1667                 skb->ip_summed = CHECKSUM_NONE;
1668 }
1669
1670
1671 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1672 {
1673         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1674
1675         /* Remove the FCB from the skb */
1676         skb_pull(skb, GMAC_FCB_LEN);
1677
1678         return fcb;
1679 }
1680
1681 /* gfar_process_frame() -- handle one incoming packet if skb
1682  * isn't NULL.  */
1683 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1684                 int length)
1685 {
1686         struct gfar_private *priv = netdev_priv(dev);
1687         struct rxfcb *fcb = NULL;
1688
1689         if (NULL == skb) {
1690                 if (netif_msg_rx_err(priv))
1691                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1692                 dev->stats.rx_dropped++;
1693                 priv->extra_stats.rx_skbmissing++;
1694         } else {
1695                 int ret;
1696
1697                 /* Prep the skb for the packet */
1698                 skb_put(skb, length);
1699
1700                 /* Grab the FCB if there is one */
1701                 if (gfar_uses_fcb(priv))
1702                         fcb = gfar_get_fcb(skb);
1703
1704                 /* Remove the padded bytes, if there are any */
1705                 if (priv->padding)
1706                         skb_pull(skb, priv->padding);
1707
1708                 if (priv->rx_csum_enable)
1709                         gfar_rx_checksum(skb, fcb);
1710
1711                 /* Tell the skb what kind of packet this is */
1712                 skb->protocol = eth_type_trans(skb, dev);
1713
1714                 /* Send the packet up the stack */
1715                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1716                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1717                                                        fcb->vlctl);
1718                 } else
1719                         ret = netif_receive_skb(skb);
1720
1721                 if (NET_RX_DROP == ret)
1722                         priv->extra_stats.kernel_dropped++;
1723         }
1724
1725         return 0;
1726 }
1727
1728 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1729  *   until the budget/quota has been reached. Returns the number
1730  *   of frames handled
1731  */
1732 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1733 {
1734         struct rxbd8 *bdp;
1735         struct sk_buff *skb;
1736         u16 pkt_len;
1737         int howmany = 0;
1738         struct gfar_private *priv = netdev_priv(dev);
1739
1740         /* Get the first full descriptor */
1741         bdp = priv->cur_rx;
1742
1743         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1744                 struct sk_buff *newskb;
1745                 rmb();
1746
1747                 /* Add another skb for the future */
1748                 newskb = gfar_new_skb(dev);
1749
1750                 skb = priv->rx_skbuff[priv->skb_currx];
1751
1752                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1753                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1754
1755                 /* We drop the frame if we failed to allocate a new buffer */
1756                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1757                                  bdp->status & RXBD_ERR)) {
1758                         count_errors(bdp->status, dev);
1759
1760                         if (unlikely(!newskb))
1761                                 newskb = skb;
1762
1763                         if (skb)
1764                                 dev_kfree_skb_any(skb);
1765                 } else {
1766                         /* Increment the number of packets */
1767                         dev->stats.rx_packets++;
1768                         howmany++;
1769
1770                         /* Remove the FCS from the packet length */
1771                         pkt_len = bdp->length - 4;
1772
1773                         gfar_process_frame(dev, skb, pkt_len);
1774
1775                         dev->stats.rx_bytes += pkt_len;
1776                 }
1777
1778                 priv->rx_skbuff[priv->skb_currx] = newskb;
1779
1780                 /* Setup the new bdp */
1781                 gfar_new_rxbdp(dev, bdp, newskb);
1782
1783                 /* Update to the next pointer */
1784                 if (bdp->status & RXBD_WRAP)
1785                         bdp = priv->rx_bd_base;
1786                 else
1787                         bdp++;
1788
1789                 /* update to point at the next skb */
1790                 priv->skb_currx =
1791                     (priv->skb_currx + 1) &
1792                     RX_RING_MOD_MASK(priv->rx_ring_size);
1793         }
1794
1795         /* Update the current rxbd pointer to be the next one */
1796         priv->cur_rx = bdp;
1797
1798         return howmany;
1799 }
1800
1801 static int gfar_poll(struct napi_struct *napi, int budget)
1802 {
1803         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1804         struct net_device *dev = priv->dev;
1805         int howmany;
1806         unsigned long flags;
1807
1808         /* If we fail to get the lock, don't bother with the TX BDs */
1809         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1810                 gfar_clean_tx_ring(dev);
1811                 spin_unlock_irqrestore(&priv->txlock, flags);
1812         }
1813
1814         howmany = gfar_clean_rx_ring(dev, budget);
1815
1816         if (howmany < budget) {
1817                 netif_rx_complete(dev, napi);
1818
1819                 /* Clear the halt bit in RSTAT */
1820                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1821
1822                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1823
1824                 /* If we are coalescing interrupts, update the timer */
1825                 /* Otherwise, clear it */
1826                 if (likely(priv->rxcoalescing)) {
1827                         gfar_write(&priv->regs->rxic, 0);
1828                         gfar_write(&priv->regs->rxic,
1829                                    mk_ic_value(priv->rxcount, priv->rxtime));
1830                 }
1831         }
1832
1833         return howmany;
1834 }
1835
1836 #ifdef CONFIG_NET_POLL_CONTROLLER
1837 /*
1838  * Polling 'interrupt' - used by things like netconsole to send skbs
1839  * without having to re-enable interrupts. It's not called while
1840  * the interrupt routine is executing.
1841  */
1842 static void gfar_netpoll(struct net_device *dev)
1843 {
1844         struct gfar_private *priv = netdev_priv(dev);
1845
1846         /* If the device has multiple interrupts, run tx/rx */
1847         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1848                 disable_irq(priv->interruptTransmit);
1849                 disable_irq(priv->interruptReceive);
1850                 disable_irq(priv->interruptError);
1851                 gfar_interrupt(priv->interruptTransmit, dev);
1852                 enable_irq(priv->interruptError);
1853                 enable_irq(priv->interruptReceive);
1854                 enable_irq(priv->interruptTransmit);
1855         } else {
1856                 disable_irq(priv->interruptTransmit);
1857                 gfar_interrupt(priv->interruptTransmit, dev);
1858                 enable_irq(priv->interruptTransmit);
1859         }
1860 }
1861 #endif
1862
1863 /* The interrupt handler for devices with one interrupt */
1864 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1865 {
1866         struct net_device *dev = dev_id;
1867         struct gfar_private *priv = netdev_priv(dev);
1868
1869         /* Save ievent for future reference */
1870         u32 events = gfar_read(&priv->regs->ievent);
1871
1872         /* Check for reception */
1873         if (events & IEVENT_RX_MASK)
1874                 gfar_receive(irq, dev_id);
1875
1876         /* Check for transmit completion */
1877         if (events & IEVENT_TX_MASK)
1878                 gfar_transmit(irq, dev_id);
1879
1880         /* Check for errors */
1881         if (events & IEVENT_ERR_MASK)
1882                 gfar_error(irq, dev_id);
1883
1884         return IRQ_HANDLED;
1885 }
1886
1887 /* Called every time the controller might need to be made
1888  * aware of new link state.  The PHY code conveys this
1889  * information through variables in the phydev structure, and this
1890  * function converts those variables into the appropriate
1891  * register values, and can bring down the device if needed.
1892  */
1893 static void adjust_link(struct net_device *dev)
1894 {
1895         struct gfar_private *priv = netdev_priv(dev);
1896         struct gfar __iomem *regs = priv->regs;
1897         unsigned long flags;
1898         struct phy_device *phydev = priv->phydev;
1899         int new_state = 0;
1900
1901         spin_lock_irqsave(&priv->txlock, flags);
1902         if (phydev->link) {
1903                 u32 tempval = gfar_read(&regs->maccfg2);
1904                 u32 ecntrl = gfar_read(&regs->ecntrl);
1905
1906                 /* Now we make sure that we can be in full duplex mode.
1907                  * If not, we operate in half-duplex mode. */
1908                 if (phydev->duplex != priv->oldduplex) {
1909                         new_state = 1;
1910                         if (!(phydev->duplex))
1911                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1912                         else
1913                                 tempval |= MACCFG2_FULL_DUPLEX;
1914
1915                         priv->oldduplex = phydev->duplex;
1916                 }
1917
1918                 if (phydev->speed != priv->oldspeed) {
1919                         new_state = 1;
1920                         switch (phydev->speed) {
1921                         case 1000:
1922                                 tempval =
1923                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1924                                 break;
1925                         case 100:
1926                         case 10:
1927                                 tempval =
1928                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1929
1930                                 /* Reduced mode distinguishes
1931                                  * between 10 and 100 */
1932                                 if (phydev->speed == SPEED_100)
1933                                         ecntrl |= ECNTRL_R100;
1934                                 else
1935                                         ecntrl &= ~(ECNTRL_R100);
1936                                 break;
1937                         default:
1938                                 if (netif_msg_link(priv))
1939                                         printk(KERN_WARNING
1940                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1941                                                 dev->name, phydev->speed);
1942                                 break;
1943                         }
1944
1945                         priv->oldspeed = phydev->speed;
1946                 }
1947
1948                 gfar_write(&regs->maccfg2, tempval);
1949                 gfar_write(&regs->ecntrl, ecntrl);
1950
1951                 if (!priv->oldlink) {
1952                         new_state = 1;
1953                         priv->oldlink = 1;
1954                 }
1955         } else if (priv->oldlink) {
1956                 new_state = 1;
1957                 priv->oldlink = 0;
1958                 priv->oldspeed = 0;
1959                 priv->oldduplex = -1;
1960         }
1961
1962         if (new_state && netif_msg_link(priv))
1963                 phy_print_status(phydev);
1964
1965         spin_unlock_irqrestore(&priv->txlock, flags);
1966 }
1967
1968 /* Update the hash table based on the current list of multicast
1969  * addresses we subscribe to.  Also, change the promiscuity of
1970  * the device based on the flags (this function is called
1971  * whenever dev->flags is changed */
1972 static void gfar_set_multi(struct net_device *dev)
1973 {
1974         struct dev_mc_list *mc_ptr;
1975         struct gfar_private *priv = netdev_priv(dev);
1976         struct gfar __iomem *regs = priv->regs;
1977         u32 tempval;
1978
1979         if(dev->flags & IFF_PROMISC) {
1980                 /* Set RCTRL to PROM */
1981                 tempval = gfar_read(&regs->rctrl);
1982                 tempval |= RCTRL_PROM;
1983                 gfar_write(&regs->rctrl, tempval);
1984         } else {
1985                 /* Set RCTRL to not PROM */
1986                 tempval = gfar_read(&regs->rctrl);
1987                 tempval &= ~(RCTRL_PROM);
1988                 gfar_write(&regs->rctrl, tempval);
1989         }
1990
1991         if(dev->flags & IFF_ALLMULTI) {
1992                 /* Set the hash to rx all multicast frames */
1993                 gfar_write(&regs->igaddr0, 0xffffffff);
1994                 gfar_write(&regs->igaddr1, 0xffffffff);
1995                 gfar_write(&regs->igaddr2, 0xffffffff);
1996                 gfar_write(&regs->igaddr3, 0xffffffff);
1997                 gfar_write(&regs->igaddr4, 0xffffffff);
1998                 gfar_write(&regs->igaddr5, 0xffffffff);
1999                 gfar_write(&regs->igaddr6, 0xffffffff);
2000                 gfar_write(&regs->igaddr7, 0xffffffff);
2001                 gfar_write(&regs->gaddr0, 0xffffffff);
2002                 gfar_write(&regs->gaddr1, 0xffffffff);
2003                 gfar_write(&regs->gaddr2, 0xffffffff);
2004                 gfar_write(&regs->gaddr3, 0xffffffff);
2005                 gfar_write(&regs->gaddr4, 0xffffffff);
2006                 gfar_write(&regs->gaddr5, 0xffffffff);
2007                 gfar_write(&regs->gaddr6, 0xffffffff);
2008                 gfar_write(&regs->gaddr7, 0xffffffff);
2009         } else {
2010                 int em_num;
2011                 int idx;
2012
2013                 /* zero out the hash */
2014                 gfar_write(&regs->igaddr0, 0x0);
2015                 gfar_write(&regs->igaddr1, 0x0);
2016                 gfar_write(&regs->igaddr2, 0x0);
2017                 gfar_write(&regs->igaddr3, 0x0);
2018                 gfar_write(&regs->igaddr4, 0x0);
2019                 gfar_write(&regs->igaddr5, 0x0);
2020                 gfar_write(&regs->igaddr6, 0x0);
2021                 gfar_write(&regs->igaddr7, 0x0);
2022                 gfar_write(&regs->gaddr0, 0x0);
2023                 gfar_write(&regs->gaddr1, 0x0);
2024                 gfar_write(&regs->gaddr2, 0x0);
2025                 gfar_write(&regs->gaddr3, 0x0);
2026                 gfar_write(&regs->gaddr4, 0x0);
2027                 gfar_write(&regs->gaddr5, 0x0);
2028                 gfar_write(&regs->gaddr6, 0x0);
2029                 gfar_write(&regs->gaddr7, 0x0);
2030
2031                 /* If we have extended hash tables, we need to
2032                  * clear the exact match registers to prepare for
2033                  * setting them */
2034                 if (priv->extended_hash) {
2035                         em_num = GFAR_EM_NUM + 1;
2036                         gfar_clear_exact_match(dev);
2037                         idx = 1;
2038                 } else {
2039                         idx = 0;
2040                         em_num = 0;
2041                 }
2042
2043                 if(dev->mc_count == 0)
2044                         return;
2045
2046                 /* Parse the list, and set the appropriate bits */
2047                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2048                         if (idx < em_num) {
2049                                 gfar_set_mac_for_addr(dev, idx,
2050                                                 mc_ptr->dmi_addr);
2051                                 idx++;
2052                         } else
2053                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2054                 }
2055         }
2056
2057         return;
2058 }
2059
2060
2061 /* Clears each of the exact match registers to zero, so they
2062  * don't interfere with normal reception */
2063 static void gfar_clear_exact_match(struct net_device *dev)
2064 {
2065         int idx;
2066         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2067
2068         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2069                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2070 }
2071
2072 /* Set the appropriate hash bit for the given addr */
2073 /* The algorithm works like so:
2074  * 1) Take the Destination Address (ie the multicast address), and
2075  * do a CRC on it (little endian), and reverse the bits of the
2076  * result.
2077  * 2) Use the 8 most significant bits as a hash into a 256-entry
2078  * table.  The table is controlled through 8 32-bit registers:
2079  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2080  * gaddr7.  This means that the 3 most significant bits in the
2081  * hash index which gaddr register to use, and the 5 other bits
2082  * indicate which bit (assuming an IBM numbering scheme, which
2083  * for PowerPC (tm) is usually the case) in the register holds
2084  * the entry. */
2085 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2086 {
2087         u32 tempval;
2088         struct gfar_private *priv = netdev_priv(dev);
2089         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2090         int width = priv->hash_width;
2091         u8 whichbit = (result >> (32 - width)) & 0x1f;
2092         u8 whichreg = result >> (32 - width + 5);
2093         u32 value = (1 << (31-whichbit));
2094
2095         tempval = gfar_read(priv->hash_regs[whichreg]);
2096         tempval |= value;
2097         gfar_write(priv->hash_regs[whichreg], tempval);
2098
2099         return;
2100 }
2101
2102
2103 /* There are multiple MAC Address register pairs on some controllers
2104  * This function sets the numth pair to a given address
2105  */
2106 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2107 {
2108         struct gfar_private *priv = netdev_priv(dev);
2109         int idx;
2110         char tmpbuf[MAC_ADDR_LEN];
2111         u32 tempval;
2112         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2113
2114         macptr += num*2;
2115
2116         /* Now copy it into the mac registers backwards, cuz */
2117         /* little endian is silly */
2118         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2119                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2120
2121         gfar_write(macptr, *((u32 *) (tmpbuf)));
2122
2123         tempval = *((u32 *) (tmpbuf + 4));
2124
2125         gfar_write(macptr+1, tempval);
2126 }
2127
2128 /* GFAR error interrupt handler */
2129 static irqreturn_t gfar_error(int irq, void *dev_id)
2130 {
2131         struct net_device *dev = dev_id;
2132         struct gfar_private *priv = netdev_priv(dev);
2133
2134         /* Save ievent for future reference */
2135         u32 events = gfar_read(&priv->regs->ievent);
2136
2137         /* Clear IEVENT */
2138         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2139
2140         /* Magic Packet is not an error. */
2141         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2142             (events & IEVENT_MAG))
2143                 events &= ~IEVENT_MAG;
2144
2145         /* Hmm... */
2146         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2147                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2148                        dev->name, events, gfar_read(&priv->regs->imask));
2149
2150         /* Update the error counters */
2151         if (events & IEVENT_TXE) {
2152                 dev->stats.tx_errors++;
2153
2154                 if (events & IEVENT_LC)
2155                         dev->stats.tx_window_errors++;
2156                 if (events & IEVENT_CRL)
2157                         dev->stats.tx_aborted_errors++;
2158                 if (events & IEVENT_XFUN) {
2159                         if (netif_msg_tx_err(priv))
2160                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2161                                        "packet dropped.\n", dev->name);
2162                         dev->stats.tx_dropped++;
2163                         priv->extra_stats.tx_underrun++;
2164
2165                         /* Reactivate the Tx Queues */
2166                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2167                 }
2168                 if (netif_msg_tx_err(priv))
2169                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2170         }
2171         if (events & IEVENT_BSY) {
2172                 dev->stats.rx_errors++;
2173                 priv->extra_stats.rx_bsy++;
2174
2175                 gfar_receive(irq, dev_id);
2176
2177                 if (netif_msg_rx_err(priv))
2178                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2179                                dev->name, gfar_read(&priv->regs->rstat));
2180         }
2181         if (events & IEVENT_BABR) {
2182                 dev->stats.rx_errors++;
2183                 priv->extra_stats.rx_babr++;
2184
2185                 if (netif_msg_rx_err(priv))
2186                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2187         }
2188         if (events & IEVENT_EBERR) {
2189                 priv->extra_stats.eberr++;
2190                 if (netif_msg_rx_err(priv))
2191                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2192         }
2193         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2194                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2195
2196         if (events & IEVENT_BABT) {
2197                 priv->extra_stats.tx_babt++;
2198                 if (netif_msg_tx_err(priv))
2199                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2200         }
2201         return IRQ_HANDLED;
2202 }
2203
2204 /* work with hotplug and coldplug */
2205 MODULE_ALIAS("platform:fsl-gianfar");
2206
2207 static struct of_device_id gfar_match[] =
2208 {
2209         {
2210                 .type = "network",
2211                 .compatible = "gianfar",
2212         },
2213         {},
2214 };
2215
2216 /* Structure for a device driver */
2217 static struct of_platform_driver gfar_driver = {
2218         .name = "fsl-gianfar",
2219         .match_table = gfar_match,
2220
2221         .probe = gfar_probe,
2222         .remove = gfar_remove,
2223         .suspend = gfar_suspend,
2224         .resume = gfar_resume,
2225 };
2226
2227 static int __init gfar_init(void)
2228 {
2229         int err = gfar_mdio_init();
2230
2231         if (err)
2232                 return err;
2233
2234         err = of_register_platform_driver(&gfar_driver);
2235
2236         if (err)
2237                 gfar_mdio_exit();
2238
2239         return err;
2240 }
2241
2242 static void __exit gfar_exit(void)
2243 {
2244         of_unregister_platform_driver(&gfar_driver);
2245         gfar_mdio_exit();
2246 }
2247
2248 module_init(gfar_init);
2249 module_exit(gfar_exit);
2250