Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through platform_device.  Structures which
29  *  define the configuration needed by the board are defined in a
30  *  board structure in arch/ppc/platforms (though I do not
31  *  discount the possibility that other architectures could one
32  *  day be supported.
33  *
34  *  The Gianfar Ethernet Controller uses a ring of buffer
35  *  descriptors.  The beginning is indicated by a register
36  *  pointing to the physical address of the start of the ring.
37  *  The end is determined by a "wrap" bit being set in the
38  *  last descriptor of the ring.
39  *
40  *  When a packet is received, the RXF bit in the
41  *  IEVENT register is set, triggering an interrupt when the
42  *  corresponding bit in the IMASK register is also set (if
43  *  interrupt coalescing is active, then the interrupt may not
44  *  happen immediately, but will wait until either a set number
45  *  of frames or amount of time have passed).  In NAPI, the
46  *  interrupt handler will signal there is work to be done, and
47  *  exit. This method will start at the last known empty
48  *  descriptor, and process every subsequent descriptor until there
49  *  are none left with data (NAPI will stop after a set number of
50  *  packets to give time to other tasks, but will eventually
51  *  process all the packets).  The data arrives inside a
52  *  pre-allocated skb, and so after the skb is passed up to the
53  *  stack, a new skb must be allocated, and the address field in
54  *  the buffer descriptor must be updated to indicate this new
55  *  skb.
56  *
57  *  When the kernel requests that a packet be transmitted, the
58  *  driver starts where it left off last time, and points the
59  *  descriptor at the buffer which was passed in.  The driver
60  *  then informs the DMA engine that there are packets ready to
61  *  be transmitted.  Once the controller is finished transmitting
62  *  the packet, an interrupt may be triggered (under the same
63  *  conditions as for reception, but depending on the TXF bit).
64  *  The driver then cleans up the buffer.
65  */
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/platform_device.h>
82 #include <linux/ip.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
85 #include <linux/in.h>
86
87 #include <asm/io.h>
88 #include <asm/irq.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
95
96 #include "gianfar.h"
97 #include "gianfar_mii.h"
98
99 #define TX_TIMEOUT      (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113                 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct platform_device *pdev);
123 static int gfar_remove(struct platform_device *pdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
135 static void gfar_vlan_rx_register(struct net_device *netdev,
136                                 struct vlan_group *grp);
137 void gfar_halt(struct net_device *dev);
138 static void gfar_halt_nodisable(struct net_device *dev);
139 void gfar_start(struct net_device *dev);
140 static void gfar_clear_exact_match(struct net_device *dev);
141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
142
143 extern const struct ethtool_ops gfar_ethtool_ops;
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 /* Returns 1 if incoming frames use an FCB */
150 static inline int gfar_uses_fcb(struct gfar_private *priv)
151 {
152         return (priv->vlan_enable || priv->rx_csum_enable);
153 }
154
155 /* Set up the ethernet device structure, private data,
156  * and anything else we need before we start */
157 static int gfar_probe(struct platform_device *pdev)
158 {
159         u32 tempval;
160         struct net_device *dev = NULL;
161         struct gfar_private *priv = NULL;
162         struct gianfar_platform_data *einfo;
163         struct resource *r;
164         int err = 0, irq;
165
166         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
167
168         if (NULL == einfo) {
169                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
170                        pdev->id);
171
172                 return -ENODEV;
173         }
174
175         /* Create an ethernet device instance */
176         dev = alloc_etherdev(sizeof (*priv));
177
178         if (NULL == dev)
179                 return -ENOMEM;
180
181         priv = netdev_priv(dev);
182         priv->dev = dev;
183
184         /* Set the info in the priv to the current info */
185         priv->einfo = einfo;
186
187         /* fill out IRQ fields */
188         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
189                 irq = platform_get_irq_byname(pdev, "tx");
190                 if (irq < 0)
191                         goto regs_fail;
192                 priv->interruptTransmit = irq;
193
194                 irq = platform_get_irq_byname(pdev, "rx");
195                 if (irq < 0)
196                         goto regs_fail;
197                 priv->interruptReceive = irq;
198
199                 irq = platform_get_irq_byname(pdev, "error");
200                 if (irq < 0)
201                         goto regs_fail;
202                 priv->interruptError = irq;
203         } else {
204                 irq = platform_get_irq(pdev, 0);
205                 if (irq < 0)
206                         goto regs_fail;
207                 priv->interruptTransmit = irq;
208         }
209
210         /* get a pointer to the register memory */
211         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
212         priv->regs = ioremap(r->start, sizeof (struct gfar));
213
214         if (NULL == priv->regs) {
215                 err = -ENOMEM;
216                 goto regs_fail;
217         }
218
219         spin_lock_init(&priv->txlock);
220         spin_lock_init(&priv->rxlock);
221         spin_lock_init(&priv->bflock);
222         INIT_WORK(&priv->reset_task, gfar_reset_task);
223
224         platform_set_drvdata(pdev, dev);
225
226         /* Stop the DMA engine now, in case it was running before */
227         /* (The firmware could have used it, and left it running). */
228         /* To do this, we write Graceful Receive Stop and Graceful */
229         /* Transmit Stop, and then wait until the corresponding bits */
230         /* in IEVENT indicate the stops have completed. */
231         tempval = gfar_read(&priv->regs->dmactrl);
232         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
233         gfar_write(&priv->regs->dmactrl, tempval);
234
235         tempval = gfar_read(&priv->regs->dmactrl);
236         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
237         gfar_write(&priv->regs->dmactrl, tempval);
238
239         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
240                 cpu_relax();
241
242         /* Reset MAC layer */
243         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
244
245         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
246         gfar_write(&priv->regs->maccfg1, tempval);
247
248         /* Initialize MACCFG2. */
249         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
250
251         /* Initialize ECNTRL */
252         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
253
254         /* Copy the station address into the dev structure, */
255         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
256
257         /* Set the dev->base_addr to the gfar reg region */
258         dev->base_addr = (unsigned long) (priv->regs);
259
260         SET_NETDEV_DEV(dev, &pdev->dev);
261
262         /* Fill in the dev structure */
263         dev->open = gfar_enet_open;
264         dev->hard_start_xmit = gfar_start_xmit;
265         dev->tx_timeout = gfar_timeout;
266         dev->watchdog_timeo = TX_TIMEOUT;
267         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
268 #ifdef CONFIG_NET_POLL_CONTROLLER
269         dev->poll_controller = gfar_netpoll;
270 #endif
271         dev->stop = gfar_close;
272         dev->change_mtu = gfar_change_mtu;
273         dev->mtu = 1500;
274         dev->set_multicast_list = gfar_set_multi;
275
276         dev->ethtool_ops = &gfar_ethtool_ops;
277
278         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
279                 priv->rx_csum_enable = 1;
280                 dev->features |= NETIF_F_IP_CSUM;
281         } else
282                 priv->rx_csum_enable = 0;
283
284         priv->vlgrp = NULL;
285
286         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
287                 dev->vlan_rx_register = gfar_vlan_rx_register;
288
289                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
290
291                 priv->vlan_enable = 1;
292         }
293
294         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
295                 priv->extended_hash = 1;
296                 priv->hash_width = 9;
297
298                 priv->hash_regs[0] = &priv->regs->igaddr0;
299                 priv->hash_regs[1] = &priv->regs->igaddr1;
300                 priv->hash_regs[2] = &priv->regs->igaddr2;
301                 priv->hash_regs[3] = &priv->regs->igaddr3;
302                 priv->hash_regs[4] = &priv->regs->igaddr4;
303                 priv->hash_regs[5] = &priv->regs->igaddr5;
304                 priv->hash_regs[6] = &priv->regs->igaddr6;
305                 priv->hash_regs[7] = &priv->regs->igaddr7;
306                 priv->hash_regs[8] = &priv->regs->gaddr0;
307                 priv->hash_regs[9] = &priv->regs->gaddr1;
308                 priv->hash_regs[10] = &priv->regs->gaddr2;
309                 priv->hash_regs[11] = &priv->regs->gaddr3;
310                 priv->hash_regs[12] = &priv->regs->gaddr4;
311                 priv->hash_regs[13] = &priv->regs->gaddr5;
312                 priv->hash_regs[14] = &priv->regs->gaddr6;
313                 priv->hash_regs[15] = &priv->regs->gaddr7;
314
315         } else {
316                 priv->extended_hash = 0;
317                 priv->hash_width = 8;
318
319                 priv->hash_regs[0] = &priv->regs->gaddr0;
320                 priv->hash_regs[1] = &priv->regs->gaddr1;
321                 priv->hash_regs[2] = &priv->regs->gaddr2;
322                 priv->hash_regs[3] = &priv->regs->gaddr3;
323                 priv->hash_regs[4] = &priv->regs->gaddr4;
324                 priv->hash_regs[5] = &priv->regs->gaddr5;
325                 priv->hash_regs[6] = &priv->regs->gaddr6;
326                 priv->hash_regs[7] = &priv->regs->gaddr7;
327         }
328
329         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
330                 priv->padding = DEFAULT_PADDING;
331         else
332                 priv->padding = 0;
333
334         if (dev->features & NETIF_F_IP_CSUM)
335                 dev->hard_header_len += GMAC_FCB_LEN;
336
337         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
338         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
339         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
340
341         priv->txcoalescing = DEFAULT_TX_COALESCE;
342         priv->txcount = DEFAULT_TXCOUNT;
343         priv->txtime = DEFAULT_TXTIME;
344         priv->rxcoalescing = DEFAULT_RX_COALESCE;
345         priv->rxcount = DEFAULT_RXCOUNT;
346         priv->rxtime = DEFAULT_RXTIME;
347
348         /* Enable most messages by default */
349         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
350
351         /* Carrier starts down, phylib will bring it up */
352         netif_carrier_off(dev);
353
354         err = register_netdev(dev);
355
356         if (err) {
357                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
358                                 dev->name);
359                 goto register_fail;
360         }
361
362         /* Create all the sysfs files */
363         gfar_init_sysfs(dev);
364
365         /* Print out the device info */
366         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
367
368         /* Even more device info helps when determining which kernel */
369         /* provided which set of benchmarks. */
370         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
371         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
372                dev->name, priv->rx_ring_size, priv->tx_ring_size);
373
374         return 0;
375
376 register_fail:
377         iounmap(priv->regs);
378 regs_fail:
379         free_netdev(dev);
380         return err;
381 }
382
383 static int gfar_remove(struct platform_device *pdev)
384 {
385         struct net_device *dev = platform_get_drvdata(pdev);
386         struct gfar_private *priv = netdev_priv(dev);
387
388         platform_set_drvdata(pdev, NULL);
389
390         iounmap(priv->regs);
391         free_netdev(dev);
392
393         return 0;
394 }
395
396 #ifdef CONFIG_PM
397 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
398 {
399         struct net_device *dev = platform_get_drvdata(pdev);
400         struct gfar_private *priv = netdev_priv(dev);
401         unsigned long flags;
402         u32 tempval;
403
404         int magic_packet = priv->wol_en &&
405                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
406
407         netif_device_detach(dev);
408
409         if (netif_running(dev)) {
410                 spin_lock_irqsave(&priv->txlock, flags);
411                 spin_lock(&priv->rxlock);
412
413                 gfar_halt_nodisable(dev);
414
415                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
416                 tempval = gfar_read(&priv->regs->maccfg1);
417
418                 tempval &= ~MACCFG1_TX_EN;
419
420                 if (!magic_packet)
421                         tempval &= ~MACCFG1_RX_EN;
422
423                 gfar_write(&priv->regs->maccfg1, tempval);
424
425                 spin_unlock(&priv->rxlock);
426                 spin_unlock_irqrestore(&priv->txlock, flags);
427
428                 napi_disable(&priv->napi);
429
430                 if (magic_packet) {
431                         /* Enable interrupt on Magic Packet */
432                         gfar_write(&priv->regs->imask, IMASK_MAG);
433
434                         /* Enable Magic Packet mode */
435                         tempval = gfar_read(&priv->regs->maccfg2);
436                         tempval |= MACCFG2_MPEN;
437                         gfar_write(&priv->regs->maccfg2, tempval);
438                 } else {
439                         phy_stop(priv->phydev);
440                 }
441         }
442
443         return 0;
444 }
445
446 static int gfar_resume(struct platform_device *pdev)
447 {
448         struct net_device *dev = platform_get_drvdata(pdev);
449         struct gfar_private *priv = netdev_priv(dev);
450         unsigned long flags;
451         u32 tempval;
452         int magic_packet = priv->wol_en &&
453                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
454
455         if (!netif_running(dev)) {
456                 netif_device_attach(dev);
457                 return 0;
458         }
459
460         if (!magic_packet && priv->phydev)
461                 phy_start(priv->phydev);
462
463         /* Disable Magic Packet mode, in case something
464          * else woke us up.
465          */
466
467         spin_lock_irqsave(&priv->txlock, flags);
468         spin_lock(&priv->rxlock);
469
470         tempval = gfar_read(&priv->regs->maccfg2);
471         tempval &= ~MACCFG2_MPEN;
472         gfar_write(&priv->regs->maccfg2, tempval);
473
474         gfar_start(dev);
475
476         spin_unlock(&priv->rxlock);
477         spin_unlock_irqrestore(&priv->txlock, flags);
478
479         netif_device_attach(dev);
480
481         napi_enable(&priv->napi);
482
483         return 0;
484 }
485 #else
486 #define gfar_suspend NULL
487 #define gfar_resume NULL
488 #endif
489
490 /* Reads the controller's registers to determine what interface
491  * connects it to the PHY.
492  */
493 static phy_interface_t gfar_get_interface(struct net_device *dev)
494 {
495         struct gfar_private *priv = netdev_priv(dev);
496         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
497
498         if (ecntrl & ECNTRL_SGMII_MODE)
499                 return PHY_INTERFACE_MODE_SGMII;
500
501         if (ecntrl & ECNTRL_TBI_MODE) {
502                 if (ecntrl & ECNTRL_REDUCED_MODE)
503                         return PHY_INTERFACE_MODE_RTBI;
504                 else
505                         return PHY_INTERFACE_MODE_TBI;
506         }
507
508         if (ecntrl & ECNTRL_REDUCED_MODE) {
509                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
510                         return PHY_INTERFACE_MODE_RMII;
511                 else {
512                         phy_interface_t interface = priv->einfo->interface;
513
514                         /*
515                          * This isn't autodetected right now, so it must
516                          * be set by the device tree or platform code.
517                          */
518                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
519                                 return PHY_INTERFACE_MODE_RGMII_ID;
520
521                         return PHY_INTERFACE_MODE_RGMII;
522                 }
523         }
524
525         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
526                 return PHY_INTERFACE_MODE_GMII;
527
528         return PHY_INTERFACE_MODE_MII;
529 }
530
531
532 /* Initializes driver's PHY state, and attaches to the PHY.
533  * Returns 0 on success.
534  */
535 static int init_phy(struct net_device *dev)
536 {
537         struct gfar_private *priv = netdev_priv(dev);
538         uint gigabit_support =
539                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
540                 SUPPORTED_1000baseT_Full : 0;
541         struct phy_device *phydev;
542         char phy_id[BUS_ID_SIZE];
543         phy_interface_t interface;
544
545         priv->oldlink = 0;
546         priv->oldspeed = 0;
547         priv->oldduplex = -1;
548
549         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
550
551         interface = gfar_get_interface(dev);
552
553         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
554
555         if (interface == PHY_INTERFACE_MODE_SGMII)
556                 gfar_configure_serdes(dev);
557
558         if (IS_ERR(phydev)) {
559                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
560                 return PTR_ERR(phydev);
561         }
562
563         /* Remove any features not supported by the controller */
564         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
565         phydev->advertising = phydev->supported;
566
567         priv->phydev = phydev;
568
569         return 0;
570 }
571
572 /*
573  * Initialize TBI PHY interface for communicating with the
574  * SERDES lynx PHY on the chip.  We communicate with this PHY
575  * through the MDIO bus on each controller, treating it as a
576  * "normal" PHY at the address found in the TBIPA register.  We assume
577  * that the TBIPA register is valid.  Either the MDIO bus code will set
578  * it to a value that doesn't conflict with other PHYs on the bus, or the
579  * value doesn't matter, as there are no other PHYs on the bus.
580  */
581 static void gfar_configure_serdes(struct net_device *dev)
582 {
583         struct gfar_private *priv = netdev_priv(dev);
584         struct gfar_mii __iomem *regs =
585                         (void __iomem *)&priv->regs->gfar_mii_regs;
586         int tbipa = gfar_read(&priv->regs->tbipa);
587         struct mii_bus *bus = gfar_get_miibus(priv);
588
589         if (bus)
590                 mutex_lock(&bus->mdio_lock);
591
592         /* If the link is already up, we must already be ok, and don't need to
593          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
594          * everything for us?  Resetting it takes the link down and requires
595          * several seconds for it to come back.
596          */
597         if (gfar_local_mdio_read(regs, tbipa, MII_BMSR) & BMSR_LSTATUS)
598                 goto done;
599
600         /* Single clk mode, mii mode off(for serdes communication) */
601         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
602
603         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
604                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
605                         ADVERTISE_1000XPSE_ASYM);
606
607         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
608                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
609
610         done:
611         if (bus)
612                 mutex_unlock(&bus->mdio_lock);
613 }
614
615 static void init_registers(struct net_device *dev)
616 {
617         struct gfar_private *priv = netdev_priv(dev);
618
619         /* Clear IEVENT */
620         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
621
622         /* Initialize IMASK */
623         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
624
625         /* Init hash registers to zero */
626         gfar_write(&priv->regs->igaddr0, 0);
627         gfar_write(&priv->regs->igaddr1, 0);
628         gfar_write(&priv->regs->igaddr2, 0);
629         gfar_write(&priv->regs->igaddr3, 0);
630         gfar_write(&priv->regs->igaddr4, 0);
631         gfar_write(&priv->regs->igaddr5, 0);
632         gfar_write(&priv->regs->igaddr6, 0);
633         gfar_write(&priv->regs->igaddr7, 0);
634
635         gfar_write(&priv->regs->gaddr0, 0);
636         gfar_write(&priv->regs->gaddr1, 0);
637         gfar_write(&priv->regs->gaddr2, 0);
638         gfar_write(&priv->regs->gaddr3, 0);
639         gfar_write(&priv->regs->gaddr4, 0);
640         gfar_write(&priv->regs->gaddr5, 0);
641         gfar_write(&priv->regs->gaddr6, 0);
642         gfar_write(&priv->regs->gaddr7, 0);
643
644         /* Zero out the rmon mib registers if it has them */
645         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
646                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
647
648                 /* Mask off the CAM interrupts */
649                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
650                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
651         }
652
653         /* Initialize the max receive buffer length */
654         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
655
656         /* Initialize the Minimum Frame Length Register */
657         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
658 }
659
660
661 /* Halt the receive and transmit queues */
662 static void gfar_halt_nodisable(struct net_device *dev)
663 {
664         struct gfar_private *priv = netdev_priv(dev);
665         struct gfar __iomem *regs = priv->regs;
666         u32 tempval;
667
668         /* Mask all interrupts */
669         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
670
671         /* Clear all interrupts */
672         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
673
674         /* Stop the DMA, and wait for it to stop */
675         tempval = gfar_read(&priv->regs->dmactrl);
676         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
677             != (DMACTRL_GRS | DMACTRL_GTS)) {
678                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
679                 gfar_write(&priv->regs->dmactrl, tempval);
680
681                 while (!(gfar_read(&priv->regs->ievent) &
682                          (IEVENT_GRSC | IEVENT_GTSC)))
683                         cpu_relax();
684         }
685 }
686
687 /* Halt the receive and transmit queues */
688 void gfar_halt(struct net_device *dev)
689 {
690         struct gfar_private *priv = netdev_priv(dev);
691         struct gfar __iomem *regs = priv->regs;
692         u32 tempval;
693
694         gfar_halt_nodisable(dev);
695
696         /* Disable Rx and Tx */
697         tempval = gfar_read(&regs->maccfg1);
698         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
699         gfar_write(&regs->maccfg1, tempval);
700 }
701
702 void stop_gfar(struct net_device *dev)
703 {
704         struct gfar_private *priv = netdev_priv(dev);
705         struct gfar __iomem *regs = priv->regs;
706         unsigned long flags;
707
708         phy_stop(priv->phydev);
709
710         /* Lock it down */
711         spin_lock_irqsave(&priv->txlock, flags);
712         spin_lock(&priv->rxlock);
713
714         gfar_halt(dev);
715
716         spin_unlock(&priv->rxlock);
717         spin_unlock_irqrestore(&priv->txlock, flags);
718
719         /* Free the IRQs */
720         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
721                 free_irq(priv->interruptError, dev);
722                 free_irq(priv->interruptTransmit, dev);
723                 free_irq(priv->interruptReceive, dev);
724         } else {
725                 free_irq(priv->interruptTransmit, dev);
726         }
727
728         free_skb_resources(priv);
729
730         dma_free_coherent(&dev->dev,
731                         sizeof(struct txbd8)*priv->tx_ring_size
732                         + sizeof(struct rxbd8)*priv->rx_ring_size,
733                         priv->tx_bd_base,
734                         gfar_read(&regs->tbase0));
735 }
736
737 /* If there are any tx skbs or rx skbs still around, free them.
738  * Then free tx_skbuff and rx_skbuff */
739 static void free_skb_resources(struct gfar_private *priv)
740 {
741         struct rxbd8 *rxbdp;
742         struct txbd8 *txbdp;
743         int i;
744
745         /* Go through all the buffer descriptors and free their data buffers */
746         txbdp = priv->tx_bd_base;
747
748         for (i = 0; i < priv->tx_ring_size; i++) {
749
750                 if (priv->tx_skbuff[i]) {
751                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
752                                         txbdp->length,
753                                         DMA_TO_DEVICE);
754                         dev_kfree_skb_any(priv->tx_skbuff[i]);
755                         priv->tx_skbuff[i] = NULL;
756                 }
757
758                 txbdp++;
759         }
760
761         kfree(priv->tx_skbuff);
762
763         rxbdp = priv->rx_bd_base;
764
765         /* rx_skbuff is not guaranteed to be allocated, so only
766          * free it and its contents if it is allocated */
767         if(priv->rx_skbuff != NULL) {
768                 for (i = 0; i < priv->rx_ring_size; i++) {
769                         if (priv->rx_skbuff[i]) {
770                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
771                                                 priv->rx_buffer_size,
772                                                 DMA_FROM_DEVICE);
773
774                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
775                                 priv->rx_skbuff[i] = NULL;
776                         }
777
778                         rxbdp->status = 0;
779                         rxbdp->length = 0;
780                         rxbdp->bufPtr = 0;
781
782                         rxbdp++;
783                 }
784
785                 kfree(priv->rx_skbuff);
786         }
787 }
788
789 void gfar_start(struct net_device *dev)
790 {
791         struct gfar_private *priv = netdev_priv(dev);
792         struct gfar __iomem *regs = priv->regs;
793         u32 tempval;
794
795         /* Enable Rx and Tx in MACCFG1 */
796         tempval = gfar_read(&regs->maccfg1);
797         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
798         gfar_write(&regs->maccfg1, tempval);
799
800         /* Initialize DMACTRL to have WWR and WOP */
801         tempval = gfar_read(&priv->regs->dmactrl);
802         tempval |= DMACTRL_INIT_SETTINGS;
803         gfar_write(&priv->regs->dmactrl, tempval);
804
805         /* Make sure we aren't stopped */
806         tempval = gfar_read(&priv->regs->dmactrl);
807         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
808         gfar_write(&priv->regs->dmactrl, tempval);
809
810         /* Clear THLT/RHLT, so that the DMA starts polling now */
811         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
812         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
813
814         /* Unmask the interrupts we look for */
815         gfar_write(&regs->imask, IMASK_DEFAULT);
816 }
817
818 /* Bring the controller up and running */
819 int startup_gfar(struct net_device *dev)
820 {
821         struct txbd8 *txbdp;
822         struct rxbd8 *rxbdp;
823         dma_addr_t addr = 0;
824         unsigned long vaddr;
825         int i;
826         struct gfar_private *priv = netdev_priv(dev);
827         struct gfar __iomem *regs = priv->regs;
828         int err = 0;
829         u32 rctrl = 0;
830         u32 attrs = 0;
831
832         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
833
834         /* Allocate memory for the buffer descriptors */
835         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
836                         sizeof (struct txbd8) * priv->tx_ring_size +
837                         sizeof (struct rxbd8) * priv->rx_ring_size,
838                         &addr, GFP_KERNEL);
839
840         if (vaddr == 0) {
841                 if (netif_msg_ifup(priv))
842                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
843                                         dev->name);
844                 return -ENOMEM;
845         }
846
847         priv->tx_bd_base = (struct txbd8 *) vaddr;
848
849         /* enet DMA only understands physical addresses */
850         gfar_write(&regs->tbase0, addr);
851
852         /* Start the rx descriptor ring where the tx ring leaves off */
853         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
854         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
855         priv->rx_bd_base = (struct rxbd8 *) vaddr;
856         gfar_write(&regs->rbase0, addr);
857
858         /* Setup the skbuff rings */
859         priv->tx_skbuff =
860             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
861                                         priv->tx_ring_size, GFP_KERNEL);
862
863         if (NULL == priv->tx_skbuff) {
864                 if (netif_msg_ifup(priv))
865                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
866                                         dev->name);
867                 err = -ENOMEM;
868                 goto tx_skb_fail;
869         }
870
871         for (i = 0; i < priv->tx_ring_size; i++)
872                 priv->tx_skbuff[i] = NULL;
873
874         priv->rx_skbuff =
875             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
876                                         priv->rx_ring_size, GFP_KERNEL);
877
878         if (NULL == priv->rx_skbuff) {
879                 if (netif_msg_ifup(priv))
880                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
881                                         dev->name);
882                 err = -ENOMEM;
883                 goto rx_skb_fail;
884         }
885
886         for (i = 0; i < priv->rx_ring_size; i++)
887                 priv->rx_skbuff[i] = NULL;
888
889         /* Initialize some variables in our dev structure */
890         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
891         priv->cur_rx = priv->rx_bd_base;
892         priv->skb_curtx = priv->skb_dirtytx = 0;
893         priv->skb_currx = 0;
894
895         /* Initialize Transmit Descriptor Ring */
896         txbdp = priv->tx_bd_base;
897         for (i = 0; i < priv->tx_ring_size; i++) {
898                 txbdp->status = 0;
899                 txbdp->length = 0;
900                 txbdp->bufPtr = 0;
901                 txbdp++;
902         }
903
904         /* Set the last descriptor in the ring to indicate wrap */
905         txbdp--;
906         txbdp->status |= TXBD_WRAP;
907
908         rxbdp = priv->rx_bd_base;
909         for (i = 0; i < priv->rx_ring_size; i++) {
910                 struct sk_buff *skb;
911
912                 skb = gfar_new_skb(dev);
913
914                 if (!skb) {
915                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
916                                         dev->name);
917
918                         goto err_rxalloc_fail;
919                 }
920
921                 priv->rx_skbuff[i] = skb;
922
923                 gfar_new_rxbdp(dev, rxbdp, skb);
924
925                 rxbdp++;
926         }
927
928         /* Set the last descriptor in the ring to wrap */
929         rxbdp--;
930         rxbdp->status |= RXBD_WRAP;
931
932         /* If the device has multiple interrupts, register for
933          * them.  Otherwise, only register for the one */
934         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
935                 /* Install our interrupt handlers for Error,
936                  * Transmit, and Receive */
937                 if (request_irq(priv->interruptError, gfar_error,
938                                 0, "enet_error", dev) < 0) {
939                         if (netif_msg_intr(priv))
940                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
941                                         dev->name, priv->interruptError);
942
943                         err = -1;
944                         goto err_irq_fail;
945                 }
946
947                 if (request_irq(priv->interruptTransmit, gfar_transmit,
948                                 0, "enet_tx", dev) < 0) {
949                         if (netif_msg_intr(priv))
950                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
951                                         dev->name, priv->interruptTransmit);
952
953                         err = -1;
954
955                         goto tx_irq_fail;
956                 }
957
958                 if (request_irq(priv->interruptReceive, gfar_receive,
959                                 0, "enet_rx", dev) < 0) {
960                         if (netif_msg_intr(priv))
961                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
962                                                 dev->name, priv->interruptReceive);
963
964                         err = -1;
965                         goto rx_irq_fail;
966                 }
967         } else {
968                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
969                                 0, "gfar_interrupt", dev) < 0) {
970                         if (netif_msg_intr(priv))
971                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
972                                         dev->name, priv->interruptError);
973
974                         err = -1;
975                         goto err_irq_fail;
976                 }
977         }
978
979         phy_start(priv->phydev);
980
981         /* Configure the coalescing support */
982         if (priv->txcoalescing)
983                 gfar_write(&regs->txic,
984                            mk_ic_value(priv->txcount, priv->txtime));
985         else
986                 gfar_write(&regs->txic, 0);
987
988         if (priv->rxcoalescing)
989                 gfar_write(&regs->rxic,
990                            mk_ic_value(priv->rxcount, priv->rxtime));
991         else
992                 gfar_write(&regs->rxic, 0);
993
994         if (priv->rx_csum_enable)
995                 rctrl |= RCTRL_CHECKSUMMING;
996
997         if (priv->extended_hash) {
998                 rctrl |= RCTRL_EXTHASH;
999
1000                 gfar_clear_exact_match(dev);
1001                 rctrl |= RCTRL_EMEN;
1002         }
1003
1004         if (priv->vlan_enable)
1005                 rctrl |= RCTRL_VLAN;
1006
1007         if (priv->padding) {
1008                 rctrl &= ~RCTRL_PAL_MASK;
1009                 rctrl |= RCTRL_PADDING(priv->padding);
1010         }
1011
1012         /* Init rctrl based on our settings */
1013         gfar_write(&priv->regs->rctrl, rctrl);
1014
1015         if (dev->features & NETIF_F_IP_CSUM)
1016                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1017
1018         /* Set the extraction length and index */
1019         attrs = ATTRELI_EL(priv->rx_stash_size) |
1020                 ATTRELI_EI(priv->rx_stash_index);
1021
1022         gfar_write(&priv->regs->attreli, attrs);
1023
1024         /* Start with defaults, and add stashing or locking
1025          * depending on the approprate variables */
1026         attrs = ATTR_INIT_SETTINGS;
1027
1028         if (priv->bd_stash_en)
1029                 attrs |= ATTR_BDSTASH;
1030
1031         if (priv->rx_stash_size != 0)
1032                 attrs |= ATTR_BUFSTASH;
1033
1034         gfar_write(&priv->regs->attr, attrs);
1035
1036         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1037         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1038         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1039
1040         /* Start the controller */
1041         gfar_start(dev);
1042
1043         return 0;
1044
1045 rx_irq_fail:
1046         free_irq(priv->interruptTransmit, dev);
1047 tx_irq_fail:
1048         free_irq(priv->interruptError, dev);
1049 err_irq_fail:
1050 err_rxalloc_fail:
1051 rx_skb_fail:
1052         free_skb_resources(priv);
1053 tx_skb_fail:
1054         dma_free_coherent(&dev->dev,
1055                         sizeof(struct txbd8)*priv->tx_ring_size
1056                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1057                         priv->tx_bd_base,
1058                         gfar_read(&regs->tbase0));
1059
1060         return err;
1061 }
1062
1063 /* Called when something needs to use the ethernet device */
1064 /* Returns 0 for success. */
1065 static int gfar_enet_open(struct net_device *dev)
1066 {
1067         struct gfar_private *priv = netdev_priv(dev);
1068         int err;
1069
1070         napi_enable(&priv->napi);
1071
1072         /* Initialize a bunch of registers */
1073         init_registers(dev);
1074
1075         gfar_set_mac_address(dev);
1076
1077         err = init_phy(dev);
1078
1079         if(err) {
1080                 napi_disable(&priv->napi);
1081                 return err;
1082         }
1083
1084         err = startup_gfar(dev);
1085         if (err) {
1086                 napi_disable(&priv->napi);
1087                 return err;
1088         }
1089
1090         netif_start_queue(dev);
1091
1092         return err;
1093 }
1094
1095 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1096 {
1097         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1098
1099         memset(fcb, 0, GMAC_FCB_LEN);
1100
1101         return fcb;
1102 }
1103
1104 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1105 {
1106         u8 flags = 0;
1107
1108         /* If we're here, it's a IP packet with a TCP or UDP
1109          * payload.  We set it to checksum, using a pseudo-header
1110          * we provide
1111          */
1112         flags = TXFCB_DEFAULT;
1113
1114         /* Tell the controller what the protocol is */
1115         /* And provide the already calculated phcs */
1116         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1117                 flags |= TXFCB_UDP;
1118                 fcb->phcs = udp_hdr(skb)->check;
1119         } else
1120                 fcb->phcs = tcp_hdr(skb)->check;
1121
1122         /* l3os is the distance between the start of the
1123          * frame (skb->data) and the start of the IP hdr.
1124          * l4os is the distance between the start of the
1125          * l3 hdr and the l4 hdr */
1126         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1127         fcb->l4os = skb_network_header_len(skb);
1128
1129         fcb->flags = flags;
1130 }
1131
1132 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1133 {
1134         fcb->flags |= TXFCB_VLN;
1135         fcb->vlctl = vlan_tx_tag_get(skb);
1136 }
1137
1138 /* This is called by the kernel when a frame is ready for transmission. */
1139 /* It is pointed to by the dev->hard_start_xmit function pointer */
1140 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1141 {
1142         struct gfar_private *priv = netdev_priv(dev);
1143         struct txfcb *fcb = NULL;
1144         struct txbd8 *txbdp;
1145         u16 status;
1146         unsigned long flags;
1147
1148         /* Update transmit stats */
1149         dev->stats.tx_bytes += skb->len;
1150
1151         /* Lock priv now */
1152         spin_lock_irqsave(&priv->txlock, flags);
1153
1154         /* Point at the first free tx descriptor */
1155         txbdp = priv->cur_tx;
1156
1157         /* Clear all but the WRAP status flags */
1158         status = txbdp->status & TXBD_WRAP;
1159
1160         /* Set up checksumming */
1161         if (likely((dev->features & NETIF_F_IP_CSUM)
1162                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1163                 fcb = gfar_add_fcb(skb, txbdp);
1164                 status |= TXBD_TOE;
1165                 gfar_tx_checksum(skb, fcb);
1166         }
1167
1168         if (priv->vlan_enable &&
1169                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1170                 if (unlikely(NULL == fcb)) {
1171                         fcb = gfar_add_fcb(skb, txbdp);
1172                         status |= TXBD_TOE;
1173                 }
1174
1175                 gfar_tx_vlan(skb, fcb);
1176         }
1177
1178         /* Set buffer length and pointer */
1179         txbdp->length = skb->len;
1180         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1181                         skb->len, DMA_TO_DEVICE);
1182
1183         /* Save the skb pointer so we can free it later */
1184         priv->tx_skbuff[priv->skb_curtx] = skb;
1185
1186         /* Update the current skb pointer (wrapping if this was the last) */
1187         priv->skb_curtx =
1188             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1189
1190         /* Flag the BD as interrupt-causing */
1191         status |= TXBD_INTERRUPT;
1192
1193         /* Flag the BD as ready to go, last in frame, and  */
1194         /* in need of CRC */
1195         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1196
1197         dev->trans_start = jiffies;
1198
1199         /* The powerpc-specific eieio() is used, as wmb() has too strong
1200          * semantics (it requires synchronization between cacheable and
1201          * uncacheable mappings, which eieio doesn't provide and which we
1202          * don't need), thus requiring a more expensive sync instruction.  At
1203          * some point, the set of architecture-independent barrier functions
1204          * should be expanded to include weaker barriers.
1205          */
1206
1207         eieio();
1208         txbdp->status = status;
1209
1210         /* If this was the last BD in the ring, the next one */
1211         /* is at the beginning of the ring */
1212         if (txbdp->status & TXBD_WRAP)
1213                 txbdp = priv->tx_bd_base;
1214         else
1215                 txbdp++;
1216
1217         /* If the next BD still needs to be cleaned up, then the bds
1218            are full.  We need to tell the kernel to stop sending us stuff. */
1219         if (txbdp == priv->dirty_tx) {
1220                 netif_stop_queue(dev);
1221
1222                 dev->stats.tx_fifo_errors++;
1223         }
1224
1225         /* Update the current txbd to the next one */
1226         priv->cur_tx = txbdp;
1227
1228         /* Tell the DMA to go go go */
1229         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1230
1231         /* Unlock priv */
1232         spin_unlock_irqrestore(&priv->txlock, flags);
1233
1234         return 0;
1235 }
1236
1237 /* Stops the kernel queue, and halts the controller */
1238 static int gfar_close(struct net_device *dev)
1239 {
1240         struct gfar_private *priv = netdev_priv(dev);
1241
1242         napi_disable(&priv->napi);
1243
1244         cancel_work_sync(&priv->reset_task);
1245         stop_gfar(dev);
1246
1247         /* Disconnect from the PHY */
1248         phy_disconnect(priv->phydev);
1249         priv->phydev = NULL;
1250
1251         netif_stop_queue(dev);
1252
1253         return 0;
1254 }
1255
1256 /* Changes the mac address if the controller is not running. */
1257 static int gfar_set_mac_address(struct net_device *dev)
1258 {
1259         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1260
1261         return 0;
1262 }
1263
1264
1265 /* Enables and disables VLAN insertion/extraction */
1266 static void gfar_vlan_rx_register(struct net_device *dev,
1267                 struct vlan_group *grp)
1268 {
1269         struct gfar_private *priv = netdev_priv(dev);
1270         unsigned long flags;
1271         u32 tempval;
1272
1273         spin_lock_irqsave(&priv->rxlock, flags);
1274
1275         priv->vlgrp = grp;
1276
1277         if (grp) {
1278                 /* Enable VLAN tag insertion */
1279                 tempval = gfar_read(&priv->regs->tctrl);
1280                 tempval |= TCTRL_VLINS;
1281
1282                 gfar_write(&priv->regs->tctrl, tempval);
1283
1284                 /* Enable VLAN tag extraction */
1285                 tempval = gfar_read(&priv->regs->rctrl);
1286                 tempval |= RCTRL_VLEX;
1287                 gfar_write(&priv->regs->rctrl, tempval);
1288         } else {
1289                 /* Disable VLAN tag insertion */
1290                 tempval = gfar_read(&priv->regs->tctrl);
1291                 tempval &= ~TCTRL_VLINS;
1292                 gfar_write(&priv->regs->tctrl, tempval);
1293
1294                 /* Disable VLAN tag extraction */
1295                 tempval = gfar_read(&priv->regs->rctrl);
1296                 tempval &= ~RCTRL_VLEX;
1297                 gfar_write(&priv->regs->rctrl, tempval);
1298         }
1299
1300         spin_unlock_irqrestore(&priv->rxlock, flags);
1301 }
1302
1303 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1304 {
1305         int tempsize, tempval;
1306         struct gfar_private *priv = netdev_priv(dev);
1307         int oldsize = priv->rx_buffer_size;
1308         int frame_size = new_mtu + ETH_HLEN;
1309
1310         if (priv->vlan_enable)
1311                 frame_size += VLAN_HLEN;
1312
1313         if (gfar_uses_fcb(priv))
1314                 frame_size += GMAC_FCB_LEN;
1315
1316         frame_size += priv->padding;
1317
1318         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1319                 if (netif_msg_drv(priv))
1320                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1321                                         dev->name);
1322                 return -EINVAL;
1323         }
1324
1325         tempsize =
1326             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1327             INCREMENTAL_BUFFER_SIZE;
1328
1329         /* Only stop and start the controller if it isn't already
1330          * stopped, and we changed something */
1331         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1332                 stop_gfar(dev);
1333
1334         priv->rx_buffer_size = tempsize;
1335
1336         dev->mtu = new_mtu;
1337
1338         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1339         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1340
1341         /* If the mtu is larger than the max size for standard
1342          * ethernet frames (ie, a jumbo frame), then set maccfg2
1343          * to allow huge frames, and to check the length */
1344         tempval = gfar_read(&priv->regs->maccfg2);
1345
1346         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1347                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1348         else
1349                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1350
1351         gfar_write(&priv->regs->maccfg2, tempval);
1352
1353         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1354                 startup_gfar(dev);
1355
1356         return 0;
1357 }
1358
1359 /* gfar_reset_task gets scheduled when a packet has not been
1360  * transmitted after a set amount of time.
1361  * For now, assume that clearing out all the structures, and
1362  * starting over will fix the problem.
1363  */
1364 static void gfar_reset_task(struct work_struct *work)
1365 {
1366         struct gfar_private *priv = container_of(work, struct gfar_private,
1367                         reset_task);
1368         struct net_device *dev = priv->dev;
1369
1370         if (dev->flags & IFF_UP) {
1371                 stop_gfar(dev);
1372                 startup_gfar(dev);
1373         }
1374
1375         netif_tx_schedule_all(dev);
1376 }
1377
1378 static void gfar_timeout(struct net_device *dev)
1379 {
1380         struct gfar_private *priv = netdev_priv(dev);
1381
1382         dev->stats.tx_errors++;
1383         schedule_work(&priv->reset_task);
1384 }
1385
1386 /* Interrupt Handler for Transmit complete */
1387 static int gfar_clean_tx_ring(struct net_device *dev)
1388 {
1389         struct txbd8 *bdp;
1390         struct gfar_private *priv = netdev_priv(dev);
1391         int howmany = 0;
1392
1393         bdp = priv->dirty_tx;
1394         while ((bdp->status & TXBD_READY) == 0) {
1395                 /* If dirty_tx and cur_tx are the same, then either the */
1396                 /* ring is empty or full now (it could only be full in the beginning, */
1397                 /* obviously).  If it is empty, we are done. */
1398                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1399                         break;
1400
1401                 howmany++;
1402
1403                 /* Deferred means some collisions occurred during transmit, */
1404                 /* but we eventually sent the packet. */
1405                 if (bdp->status & TXBD_DEF)
1406                         dev->stats.collisions++;
1407
1408                 /* Free the sk buffer associated with this TxBD */
1409                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1410
1411                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1412                 priv->skb_dirtytx =
1413                     (priv->skb_dirtytx +
1414                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1415
1416                 /* Clean BD length for empty detection */
1417                 bdp->length = 0;
1418
1419                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1420                 if (bdp->status & TXBD_WRAP)
1421                         bdp = priv->tx_bd_base;
1422                 else
1423                         bdp++;
1424
1425                 /* Move dirty_tx to be the next bd */
1426                 priv->dirty_tx = bdp;
1427
1428                 /* We freed a buffer, so now we can restart transmission */
1429                 if (netif_queue_stopped(dev))
1430                         netif_wake_queue(dev);
1431         } /* while ((bdp->status & TXBD_READY) == 0) */
1432
1433         dev->stats.tx_packets += howmany;
1434
1435         return howmany;
1436 }
1437
1438 /* Interrupt Handler for Transmit complete */
1439 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1440 {
1441         struct net_device *dev = (struct net_device *) dev_id;
1442         struct gfar_private *priv = netdev_priv(dev);
1443
1444         /* Clear IEVENT */
1445         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1446
1447         /* Lock priv */
1448         spin_lock(&priv->txlock);
1449
1450         gfar_clean_tx_ring(dev);
1451
1452         /* If we are coalescing the interrupts, reset the timer */
1453         /* Otherwise, clear it */
1454         if (likely(priv->txcoalescing)) {
1455                 gfar_write(&priv->regs->txic, 0);
1456                 gfar_write(&priv->regs->txic,
1457                            mk_ic_value(priv->txcount, priv->txtime));
1458         }
1459
1460         spin_unlock(&priv->txlock);
1461
1462         return IRQ_HANDLED;
1463 }
1464
1465 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1466                 struct sk_buff *skb)
1467 {
1468         struct gfar_private *priv = netdev_priv(dev);
1469         u32 * status_len = (u32 *)bdp;
1470         u16 flags;
1471
1472         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1473                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1474
1475         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1476
1477         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1478                 flags |= RXBD_WRAP;
1479
1480         eieio();
1481
1482         *status_len = (u32)flags << 16;
1483 }
1484
1485
1486 struct sk_buff * gfar_new_skb(struct net_device *dev)
1487 {
1488         unsigned int alignamount;
1489         struct gfar_private *priv = netdev_priv(dev);
1490         struct sk_buff *skb = NULL;
1491
1492         /* We have to allocate the skb, so keep trying till we succeed */
1493         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1494
1495         if (!skb)
1496                 return NULL;
1497
1498         alignamount = RXBUF_ALIGNMENT -
1499                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1500
1501         /* We need the data buffer to be aligned properly.  We will reserve
1502          * as many bytes as needed to align the data properly
1503          */
1504         skb_reserve(skb, alignamount);
1505
1506         return skb;
1507 }
1508
1509 static inline void count_errors(unsigned short status, struct net_device *dev)
1510 {
1511         struct gfar_private *priv = netdev_priv(dev);
1512         struct net_device_stats *stats = &dev->stats;
1513         struct gfar_extra_stats *estats = &priv->extra_stats;
1514
1515         /* If the packet was truncated, none of the other errors
1516          * matter */
1517         if (status & RXBD_TRUNCATED) {
1518                 stats->rx_length_errors++;
1519
1520                 estats->rx_trunc++;
1521
1522                 return;
1523         }
1524         /* Count the errors, if there were any */
1525         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1526                 stats->rx_length_errors++;
1527
1528                 if (status & RXBD_LARGE)
1529                         estats->rx_large++;
1530                 else
1531                         estats->rx_short++;
1532         }
1533         if (status & RXBD_NONOCTET) {
1534                 stats->rx_frame_errors++;
1535                 estats->rx_nonoctet++;
1536         }
1537         if (status & RXBD_CRCERR) {
1538                 estats->rx_crcerr++;
1539                 stats->rx_crc_errors++;
1540         }
1541         if (status & RXBD_OVERRUN) {
1542                 estats->rx_overrun++;
1543                 stats->rx_crc_errors++;
1544         }
1545 }
1546
1547 irqreturn_t gfar_receive(int irq, void *dev_id)
1548 {
1549         struct net_device *dev = (struct net_device *) dev_id;
1550         struct gfar_private *priv = netdev_priv(dev);
1551         u32 tempval;
1552
1553         /* support NAPI */
1554         /* Clear IEVENT, so interrupts aren't called again
1555          * because of the packets that have already arrived */
1556         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1557
1558         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1559                 tempval = gfar_read(&priv->regs->imask);
1560                 tempval &= IMASK_RTX_DISABLED;
1561                 gfar_write(&priv->regs->imask, tempval);
1562
1563                 __netif_rx_schedule(dev, &priv->napi);
1564         } else {
1565                 if (netif_msg_rx_err(priv))
1566                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1567                                 dev->name, gfar_read(&priv->regs->ievent),
1568                                 gfar_read(&priv->regs->imask));
1569         }
1570
1571         return IRQ_HANDLED;
1572 }
1573
1574 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1575 {
1576         /* If valid headers were found, and valid sums
1577          * were verified, then we tell the kernel that no
1578          * checksumming is necessary.  Otherwise, it is */
1579         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1580                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1581         else
1582                 skb->ip_summed = CHECKSUM_NONE;
1583 }
1584
1585
1586 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1587 {
1588         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1589
1590         /* Remove the FCB from the skb */
1591         skb_pull(skb, GMAC_FCB_LEN);
1592
1593         return fcb;
1594 }
1595
1596 /* gfar_process_frame() -- handle one incoming packet if skb
1597  * isn't NULL.  */
1598 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1599                 int length)
1600 {
1601         struct gfar_private *priv = netdev_priv(dev);
1602         struct rxfcb *fcb = NULL;
1603
1604         if (NULL == skb) {
1605                 if (netif_msg_rx_err(priv))
1606                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1607                 dev->stats.rx_dropped++;
1608                 priv->extra_stats.rx_skbmissing++;
1609         } else {
1610                 int ret;
1611
1612                 /* Prep the skb for the packet */
1613                 skb_put(skb, length);
1614
1615                 /* Grab the FCB if there is one */
1616                 if (gfar_uses_fcb(priv))
1617                         fcb = gfar_get_fcb(skb);
1618
1619                 /* Remove the padded bytes, if there are any */
1620                 if (priv->padding)
1621                         skb_pull(skb, priv->padding);
1622
1623                 if (priv->rx_csum_enable)
1624                         gfar_rx_checksum(skb, fcb);
1625
1626                 /* Tell the skb what kind of packet this is */
1627                 skb->protocol = eth_type_trans(skb, dev);
1628
1629                 /* Send the packet up the stack */
1630                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1631                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1632                                                        fcb->vlctl);
1633                 } else
1634                         ret = netif_receive_skb(skb);
1635
1636                 if (NET_RX_DROP == ret)
1637                         priv->extra_stats.kernel_dropped++;
1638         }
1639
1640         return 0;
1641 }
1642
1643 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1644  *   until the budget/quota has been reached. Returns the number
1645  *   of frames handled
1646  */
1647 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1648 {
1649         struct rxbd8 *bdp;
1650         struct sk_buff *skb;
1651         u16 pkt_len;
1652         int howmany = 0;
1653         struct gfar_private *priv = netdev_priv(dev);
1654
1655         /* Get the first full descriptor */
1656         bdp = priv->cur_rx;
1657
1658         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1659                 struct sk_buff *newskb;
1660                 rmb();
1661
1662                 /* Add another skb for the future */
1663                 newskb = gfar_new_skb(dev);
1664
1665                 skb = priv->rx_skbuff[priv->skb_currx];
1666
1667                 /* We drop the frame if we failed to allocate a new buffer */
1668                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1669                                  bdp->status & RXBD_ERR)) {
1670                         count_errors(bdp->status, dev);
1671
1672                         if (unlikely(!newskb))
1673                                 newskb = skb;
1674
1675                         if (skb) {
1676                                 dma_unmap_single(&priv->dev->dev,
1677                                                 bdp->bufPtr,
1678                                                 priv->rx_buffer_size,
1679                                                 DMA_FROM_DEVICE);
1680
1681                                 dev_kfree_skb_any(skb);
1682                         }
1683                 } else {
1684                         /* Increment the number of packets */
1685                         dev->stats.rx_packets++;
1686                         howmany++;
1687
1688                         /* Remove the FCS from the packet length */
1689                         pkt_len = bdp->length - 4;
1690
1691                         gfar_process_frame(dev, skb, pkt_len);
1692
1693                         dev->stats.rx_bytes += pkt_len;
1694                 }
1695
1696                 dev->last_rx = jiffies;
1697
1698                 priv->rx_skbuff[priv->skb_currx] = newskb;
1699
1700                 /* Setup the new bdp */
1701                 gfar_new_rxbdp(dev, bdp, newskb);
1702
1703                 /* Update to the next pointer */
1704                 if (bdp->status & RXBD_WRAP)
1705                         bdp = priv->rx_bd_base;
1706                 else
1707                         bdp++;
1708
1709                 /* update to point at the next skb */
1710                 priv->skb_currx =
1711                     (priv->skb_currx + 1) &
1712                     RX_RING_MOD_MASK(priv->rx_ring_size);
1713         }
1714
1715         /* Update the current rxbd pointer to be the next one */
1716         priv->cur_rx = bdp;
1717
1718         return howmany;
1719 }
1720
1721 static int gfar_poll(struct napi_struct *napi, int budget)
1722 {
1723         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1724         struct net_device *dev = priv->dev;
1725         int howmany;
1726         unsigned long flags;
1727
1728         /* If we fail to get the lock, don't bother with the TX BDs */
1729         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1730                 gfar_clean_tx_ring(dev);
1731                 spin_unlock_irqrestore(&priv->txlock, flags);
1732         }
1733
1734         howmany = gfar_clean_rx_ring(dev, budget);
1735
1736         if (howmany < budget) {
1737                 netif_rx_complete(dev, napi);
1738
1739                 /* Clear the halt bit in RSTAT */
1740                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1741
1742                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1743
1744                 /* If we are coalescing interrupts, update the timer */
1745                 /* Otherwise, clear it */
1746                 if (likely(priv->rxcoalescing)) {
1747                         gfar_write(&priv->regs->rxic, 0);
1748                         gfar_write(&priv->regs->rxic,
1749                                    mk_ic_value(priv->rxcount, priv->rxtime));
1750                 }
1751         }
1752
1753         return howmany;
1754 }
1755
1756 #ifdef CONFIG_NET_POLL_CONTROLLER
1757 /*
1758  * Polling 'interrupt' - used by things like netconsole to send skbs
1759  * without having to re-enable interrupts. It's not called while
1760  * the interrupt routine is executing.
1761  */
1762 static void gfar_netpoll(struct net_device *dev)
1763 {
1764         struct gfar_private *priv = netdev_priv(dev);
1765
1766         /* If the device has multiple interrupts, run tx/rx */
1767         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1768                 disable_irq(priv->interruptTransmit);
1769                 disable_irq(priv->interruptReceive);
1770                 disable_irq(priv->interruptError);
1771                 gfar_interrupt(priv->interruptTransmit, dev);
1772                 enable_irq(priv->interruptError);
1773                 enable_irq(priv->interruptReceive);
1774                 enable_irq(priv->interruptTransmit);
1775         } else {
1776                 disable_irq(priv->interruptTransmit);
1777                 gfar_interrupt(priv->interruptTransmit, dev);
1778                 enable_irq(priv->interruptTransmit);
1779         }
1780 }
1781 #endif
1782
1783 /* The interrupt handler for devices with one interrupt */
1784 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1785 {
1786         struct net_device *dev = dev_id;
1787         struct gfar_private *priv = netdev_priv(dev);
1788
1789         /* Save ievent for future reference */
1790         u32 events = gfar_read(&priv->regs->ievent);
1791
1792         /* Check for reception */
1793         if (events & IEVENT_RX_MASK)
1794                 gfar_receive(irq, dev_id);
1795
1796         /* Check for transmit completion */
1797         if (events & IEVENT_TX_MASK)
1798                 gfar_transmit(irq, dev_id);
1799
1800         /* Check for errors */
1801         if (events & IEVENT_ERR_MASK)
1802                 gfar_error(irq, dev_id);
1803
1804         return IRQ_HANDLED;
1805 }
1806
1807 /* Called every time the controller might need to be made
1808  * aware of new link state.  The PHY code conveys this
1809  * information through variables in the phydev structure, and this
1810  * function converts those variables into the appropriate
1811  * register values, and can bring down the device if needed.
1812  */
1813 static void adjust_link(struct net_device *dev)
1814 {
1815         struct gfar_private *priv = netdev_priv(dev);
1816         struct gfar __iomem *regs = priv->regs;
1817         unsigned long flags;
1818         struct phy_device *phydev = priv->phydev;
1819         int new_state = 0;
1820
1821         spin_lock_irqsave(&priv->txlock, flags);
1822         if (phydev->link) {
1823                 u32 tempval = gfar_read(&regs->maccfg2);
1824                 u32 ecntrl = gfar_read(&regs->ecntrl);
1825
1826                 /* Now we make sure that we can be in full duplex mode.
1827                  * If not, we operate in half-duplex mode. */
1828                 if (phydev->duplex != priv->oldduplex) {
1829                         new_state = 1;
1830                         if (!(phydev->duplex))
1831                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1832                         else
1833                                 tempval |= MACCFG2_FULL_DUPLEX;
1834
1835                         priv->oldduplex = phydev->duplex;
1836                 }
1837
1838                 if (phydev->speed != priv->oldspeed) {
1839                         new_state = 1;
1840                         switch (phydev->speed) {
1841                         case 1000:
1842                                 tempval =
1843                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1844                                 break;
1845                         case 100:
1846                         case 10:
1847                                 tempval =
1848                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1849
1850                                 /* Reduced mode distinguishes
1851                                  * between 10 and 100 */
1852                                 if (phydev->speed == SPEED_100)
1853                                         ecntrl |= ECNTRL_R100;
1854                                 else
1855                                         ecntrl &= ~(ECNTRL_R100);
1856                                 break;
1857                         default:
1858                                 if (netif_msg_link(priv))
1859                                         printk(KERN_WARNING
1860                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1861                                                 dev->name, phydev->speed);
1862                                 break;
1863                         }
1864
1865                         priv->oldspeed = phydev->speed;
1866                 }
1867
1868                 gfar_write(&regs->maccfg2, tempval);
1869                 gfar_write(&regs->ecntrl, ecntrl);
1870
1871                 if (!priv->oldlink) {
1872                         new_state = 1;
1873                         priv->oldlink = 1;
1874                 }
1875         } else if (priv->oldlink) {
1876                 new_state = 1;
1877                 priv->oldlink = 0;
1878                 priv->oldspeed = 0;
1879                 priv->oldduplex = -1;
1880         }
1881
1882         if (new_state && netif_msg_link(priv))
1883                 phy_print_status(phydev);
1884
1885         spin_unlock_irqrestore(&priv->txlock, flags);
1886 }
1887
1888 /* Update the hash table based on the current list of multicast
1889  * addresses we subscribe to.  Also, change the promiscuity of
1890  * the device based on the flags (this function is called
1891  * whenever dev->flags is changed */
1892 static void gfar_set_multi(struct net_device *dev)
1893 {
1894         struct dev_mc_list *mc_ptr;
1895         struct gfar_private *priv = netdev_priv(dev);
1896         struct gfar __iomem *regs = priv->regs;
1897         u32 tempval;
1898
1899         if(dev->flags & IFF_PROMISC) {
1900                 /* Set RCTRL to PROM */
1901                 tempval = gfar_read(&regs->rctrl);
1902                 tempval |= RCTRL_PROM;
1903                 gfar_write(&regs->rctrl, tempval);
1904         } else {
1905                 /* Set RCTRL to not PROM */
1906                 tempval = gfar_read(&regs->rctrl);
1907                 tempval &= ~(RCTRL_PROM);
1908                 gfar_write(&regs->rctrl, tempval);
1909         }
1910
1911         if(dev->flags & IFF_ALLMULTI) {
1912                 /* Set the hash to rx all multicast frames */
1913                 gfar_write(&regs->igaddr0, 0xffffffff);
1914                 gfar_write(&regs->igaddr1, 0xffffffff);
1915                 gfar_write(&regs->igaddr2, 0xffffffff);
1916                 gfar_write(&regs->igaddr3, 0xffffffff);
1917                 gfar_write(&regs->igaddr4, 0xffffffff);
1918                 gfar_write(&regs->igaddr5, 0xffffffff);
1919                 gfar_write(&regs->igaddr6, 0xffffffff);
1920                 gfar_write(&regs->igaddr7, 0xffffffff);
1921                 gfar_write(&regs->gaddr0, 0xffffffff);
1922                 gfar_write(&regs->gaddr1, 0xffffffff);
1923                 gfar_write(&regs->gaddr2, 0xffffffff);
1924                 gfar_write(&regs->gaddr3, 0xffffffff);
1925                 gfar_write(&regs->gaddr4, 0xffffffff);
1926                 gfar_write(&regs->gaddr5, 0xffffffff);
1927                 gfar_write(&regs->gaddr6, 0xffffffff);
1928                 gfar_write(&regs->gaddr7, 0xffffffff);
1929         } else {
1930                 int em_num;
1931                 int idx;
1932
1933                 /* zero out the hash */
1934                 gfar_write(&regs->igaddr0, 0x0);
1935                 gfar_write(&regs->igaddr1, 0x0);
1936                 gfar_write(&regs->igaddr2, 0x0);
1937                 gfar_write(&regs->igaddr3, 0x0);
1938                 gfar_write(&regs->igaddr4, 0x0);
1939                 gfar_write(&regs->igaddr5, 0x0);
1940                 gfar_write(&regs->igaddr6, 0x0);
1941                 gfar_write(&regs->igaddr7, 0x0);
1942                 gfar_write(&regs->gaddr0, 0x0);
1943                 gfar_write(&regs->gaddr1, 0x0);
1944                 gfar_write(&regs->gaddr2, 0x0);
1945                 gfar_write(&regs->gaddr3, 0x0);
1946                 gfar_write(&regs->gaddr4, 0x0);
1947                 gfar_write(&regs->gaddr5, 0x0);
1948                 gfar_write(&regs->gaddr6, 0x0);
1949                 gfar_write(&regs->gaddr7, 0x0);
1950
1951                 /* If we have extended hash tables, we need to
1952                  * clear the exact match registers to prepare for
1953                  * setting them */
1954                 if (priv->extended_hash) {
1955                         em_num = GFAR_EM_NUM + 1;
1956                         gfar_clear_exact_match(dev);
1957                         idx = 1;
1958                 } else {
1959                         idx = 0;
1960                         em_num = 0;
1961                 }
1962
1963                 if(dev->mc_count == 0)
1964                         return;
1965
1966                 /* Parse the list, and set the appropriate bits */
1967                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1968                         if (idx < em_num) {
1969                                 gfar_set_mac_for_addr(dev, idx,
1970                                                 mc_ptr->dmi_addr);
1971                                 idx++;
1972                         } else
1973                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1974                 }
1975         }
1976
1977         return;
1978 }
1979
1980
1981 /* Clears each of the exact match registers to zero, so they
1982  * don't interfere with normal reception */
1983 static void gfar_clear_exact_match(struct net_device *dev)
1984 {
1985         int idx;
1986         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1987
1988         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1989                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1990 }
1991
1992 /* Set the appropriate hash bit for the given addr */
1993 /* The algorithm works like so:
1994  * 1) Take the Destination Address (ie the multicast address), and
1995  * do a CRC on it (little endian), and reverse the bits of the
1996  * result.
1997  * 2) Use the 8 most significant bits as a hash into a 256-entry
1998  * table.  The table is controlled through 8 32-bit registers:
1999  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2000  * gaddr7.  This means that the 3 most significant bits in the
2001  * hash index which gaddr register to use, and the 5 other bits
2002  * indicate which bit (assuming an IBM numbering scheme, which
2003  * for PowerPC (tm) is usually the case) in the register holds
2004  * the entry. */
2005 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2006 {
2007         u32 tempval;
2008         struct gfar_private *priv = netdev_priv(dev);
2009         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2010         int width = priv->hash_width;
2011         u8 whichbit = (result >> (32 - width)) & 0x1f;
2012         u8 whichreg = result >> (32 - width + 5);
2013         u32 value = (1 << (31-whichbit));
2014
2015         tempval = gfar_read(priv->hash_regs[whichreg]);
2016         tempval |= value;
2017         gfar_write(priv->hash_regs[whichreg], tempval);
2018
2019         return;
2020 }
2021
2022
2023 /* There are multiple MAC Address register pairs on some controllers
2024  * This function sets the numth pair to a given address
2025  */
2026 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2027 {
2028         struct gfar_private *priv = netdev_priv(dev);
2029         int idx;
2030         char tmpbuf[MAC_ADDR_LEN];
2031         u32 tempval;
2032         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2033
2034         macptr += num*2;
2035
2036         /* Now copy it into the mac registers backwards, cuz */
2037         /* little endian is silly */
2038         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2039                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2040
2041         gfar_write(macptr, *((u32 *) (tmpbuf)));
2042
2043         tempval = *((u32 *) (tmpbuf + 4));
2044
2045         gfar_write(macptr+1, tempval);
2046 }
2047
2048 /* GFAR error interrupt handler */
2049 static irqreturn_t gfar_error(int irq, void *dev_id)
2050 {
2051         struct net_device *dev = dev_id;
2052         struct gfar_private *priv = netdev_priv(dev);
2053
2054         /* Save ievent for future reference */
2055         u32 events = gfar_read(&priv->regs->ievent);
2056
2057         /* Clear IEVENT */
2058         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2059
2060         /* Magic Packet is not an error. */
2061         if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2062             (events & IEVENT_MAG))
2063                 events &= ~IEVENT_MAG;
2064
2065         /* Hmm... */
2066         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2067                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2068                        dev->name, events, gfar_read(&priv->regs->imask));
2069
2070         /* Update the error counters */
2071         if (events & IEVENT_TXE) {
2072                 dev->stats.tx_errors++;
2073
2074                 if (events & IEVENT_LC)
2075                         dev->stats.tx_window_errors++;
2076                 if (events & IEVENT_CRL)
2077                         dev->stats.tx_aborted_errors++;
2078                 if (events & IEVENT_XFUN) {
2079                         if (netif_msg_tx_err(priv))
2080                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2081                                        "packet dropped.\n", dev->name);
2082                         dev->stats.tx_dropped++;
2083                         priv->extra_stats.tx_underrun++;
2084
2085                         /* Reactivate the Tx Queues */
2086                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2087                 }
2088                 if (netif_msg_tx_err(priv))
2089                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2090         }
2091         if (events & IEVENT_BSY) {
2092                 dev->stats.rx_errors++;
2093                 priv->extra_stats.rx_bsy++;
2094
2095                 gfar_receive(irq, dev_id);
2096
2097                 if (netif_msg_rx_err(priv))
2098                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2099                                dev->name, gfar_read(&priv->regs->rstat));
2100         }
2101         if (events & IEVENT_BABR) {
2102                 dev->stats.rx_errors++;
2103                 priv->extra_stats.rx_babr++;
2104
2105                 if (netif_msg_rx_err(priv))
2106                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2107         }
2108         if (events & IEVENT_EBERR) {
2109                 priv->extra_stats.eberr++;
2110                 if (netif_msg_rx_err(priv))
2111                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2112         }
2113         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2114                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2115
2116         if (events & IEVENT_BABT) {
2117                 priv->extra_stats.tx_babt++;
2118                 if (netif_msg_tx_err(priv))
2119                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2120         }
2121         return IRQ_HANDLED;
2122 }
2123
2124 /* work with hotplug and coldplug */
2125 MODULE_ALIAS("platform:fsl-gianfar");
2126
2127 /* Structure for a device driver */
2128 static struct platform_driver gfar_driver = {
2129         .probe = gfar_probe,
2130         .remove = gfar_remove,
2131         .suspend = gfar_suspend,
2132         .resume = gfar_resume,
2133         .driver = {
2134                 .name = "fsl-gianfar",
2135                 .owner = THIS_MODULE,
2136         },
2137 };
2138
2139 static int __init gfar_init(void)
2140 {
2141         int err = gfar_mdio_init();
2142
2143         if (err)
2144                 return err;
2145
2146         err = platform_driver_register(&gfar_driver);
2147
2148         if (err)
2149                 gfar_mdio_exit();
2150
2151         return err;
2152 }
2153
2154 static void __exit gfar_exit(void)
2155 {
2156         platform_driver_unregister(&gfar_driver);
2157         gfar_mdio_exit();
2158 }
2159
2160 module_init(gfar_init);
2161 module_exit(gfar_exit);
2162