gianfar: Add per queue structure support
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12  *
13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
14  * Copyright 2007 MontaVista Software, Inc.
15  *
16  * This program is free software; you can redistribute  it and/or modify it
17  * under  the terms of  the GNU General  Public License as published by the
18  * Free Software Foundation;  either version 2 of the  License, or (at your
19  * option) any later version.
20  *
21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
22  *  RA 11 31 24.2
23  *  Dec +69 19 52
24  *  V 3.84
25  *  B-V +1.62
26  *
27  *  Theory of operation
28  *
29  *  The driver is initialized through of_device. Configuration information
30  *  is therefore conveyed through an OF-style device tree.
31  *
32  *  The Gianfar Ethernet Controller uses a ring of buffer
33  *  descriptors.  The beginning is indicated by a register
34  *  pointing to the physical address of the start of the ring.
35  *  The end is determined by a "wrap" bit being set in the
36  *  last descriptor of the ring.
37  *
38  *  When a packet is received, the RXF bit in the
39  *  IEVENT register is set, triggering an interrupt when the
40  *  corresponding bit in the IMASK register is also set (if
41  *  interrupt coalescing is active, then the interrupt may not
42  *  happen immediately, but will wait until either a set number
43  *  of frames or amount of time have passed).  In NAPI, the
44  *  interrupt handler will signal there is work to be done, and
45  *  exit. This method will start at the last known empty
46  *  descriptor, and process every subsequent descriptor until there
47  *  are none left with data (NAPI will stop after a set number of
48  *  packets to give time to other tasks, but will eventually
49  *  process all the packets).  The data arrives inside a
50  *  pre-allocated skb, and so after the skb is passed up to the
51  *  stack, a new skb must be allocated, and the address field in
52  *  the buffer descriptor must be updated to indicate this new
53  *  skb.
54  *
55  *  When the kernel requests that a packet be transmitted, the
56  *  driver starts where it left off last time, and points the
57  *  descriptor at the buffer which was passed in.  The driver
58  *  then informs the DMA engine that there are packets ready to
59  *  be transmitted.  Once the controller is finished transmitting
60  *  the packet, an interrupt may be triggered (under the same
61  *  conditions as for reception, but depending on the TXF bit).
62  *  The driver then cleans up the buffer.
63  */
64
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
78 #include <linux/mm.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
81 #include <linux/ip.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
84 #include <linux/in.h>
85
86 #include <asm/io.h>
87 #include <asm/irq.h>
88 #include <asm/uaccess.h>
89 #include <linux/module.h>
90 #include <linux/dma-mapping.h>
91 #include <linux/crc32.h>
92 #include <linux/mii.h>
93 #include <linux/phy.h>
94 #include <linux/phy_fixed.h>
95 #include <linux/of.h>
96
97 #include "gianfar.h"
98 #include "fsl_pq_mdio.h"
99
100 #define TX_TIMEOUT      (1*HZ)
101 #undef BRIEF_GFAR_ERRORS
102 #undef VERBOSE_GFAR_ERRORS
103
104 const char gfar_driver_name[] = "Gianfar Ethernet";
105 const char gfar_driver_version[] = "1.3";
106
107 static int gfar_enet_open(struct net_device *dev);
108 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
109 static void gfar_reset_task(struct work_struct *work);
110 static void gfar_timeout(struct net_device *dev);
111 static int gfar_close(struct net_device *dev);
112 struct sk_buff *gfar_new_skb(struct net_device *dev);
113 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
114                 struct sk_buff *skb);
115 static int gfar_set_mac_address(struct net_device *dev);
116 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
117 static irqreturn_t gfar_error(int irq, void *dev_id);
118 static irqreturn_t gfar_transmit(int irq, void *dev_id);
119 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
120 static void adjust_link(struct net_device *dev);
121 static void init_registers(struct net_device *dev);
122 static int init_phy(struct net_device *dev);
123 static int gfar_probe(struct of_device *ofdev,
124                 const struct of_device_id *match);
125 static int gfar_remove(struct of_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
133 #endif
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137                               int amount_pull);
138 static void gfar_vlan_rx_register(struct net_device *netdev,
139                                 struct vlan_group *grp);
140 void gfar_halt(struct net_device *dev);
141 static void gfar_halt_nodisable(struct net_device *dev);
142 void gfar_start(struct net_device *dev);
143 static void gfar_clear_exact_match(struct net_device *dev);
144 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
145 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146
147 MODULE_AUTHOR("Freescale Semiconductor, Inc");
148 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
149 MODULE_LICENSE("GPL");
150
151 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
152                             dma_addr_t buf)
153 {
154         struct net_device *dev = rx_queue->dev;
155         u32 lstatus;
156
157         bdp->bufPtr = buf;
158
159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
161                 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163         eieio();
164
165         bdp->lstatus = lstatus;
166 }
167
168 static int gfar_init_bds(struct net_device *ndev)
169 {
170         struct gfar_private *priv = netdev_priv(ndev);
171         struct gfar_priv_tx_q *tx_queue = NULL;
172         struct gfar_priv_rx_q *rx_queue = NULL;
173         struct txbd8 *txbdp;
174         struct rxbd8 *rxbdp;
175         int i;
176
177         tx_queue = priv->tx_queue;
178         rx_queue = priv->rx_queue;
179
180         /* Initialize some variables in our dev structure */
181         tx_queue->num_txbdfree = tx_queue->tx_ring_size;
182         tx_queue->dirty_tx = tx_queue->cur_tx = tx_queue->tx_bd_base;
183         rx_queue->cur_rx = rx_queue->rx_bd_base;
184         tx_queue->skb_curtx = tx_queue->skb_dirtytx = 0;
185         rx_queue->skb_currx = 0;
186
187         /* Initialize Transmit Descriptor Ring */
188         txbdp = tx_queue->tx_bd_base;
189         for (i = 0; i < tx_queue->tx_ring_size; i++) {
190                 txbdp->lstatus = 0;
191                 txbdp->bufPtr = 0;
192                 txbdp++;
193         }
194
195         /* Set the last descriptor in the ring to indicate wrap */
196         txbdp--;
197         txbdp->status |= TXBD_WRAP;
198
199         rxbdp = rx_queue->rx_bd_base;
200         for (i = 0; i < rx_queue->rx_ring_size; i++) {
201                 struct sk_buff *skb = rx_queue->rx_skbuff[i];
202
203                 if (skb) {
204                         gfar_init_rxbdp(rx_queue, rxbdp, rxbdp->bufPtr);
205                 } else {
206                         skb = gfar_new_skb(ndev);
207                         if (!skb) {
208                                 pr_err("%s: Can't allocate RX buffers\n",
209                                        ndev->name);
210                                 return -ENOMEM;
211                         }
212                         rx_queue->rx_skbuff[i] = skb;
213
214                         gfar_new_rxbdp(rx_queue, rxbdp, skb);
215                 }
216
217                 rxbdp++;
218         }
219
220         return 0;
221 }
222
223 static int gfar_alloc_skb_resources(struct net_device *ndev)
224 {
225         void *vaddr;
226         int i;
227         struct gfar_private *priv = netdev_priv(ndev);
228         struct device *dev = &priv->ofdev->dev;
229         struct gfar_priv_tx_q *tx_queue = NULL;
230         struct gfar_priv_rx_q *rx_queue = NULL;
231
232         tx_queue = priv->tx_queue;
233         rx_queue = priv->rx_queue;
234
235         /* Allocate memory for the buffer descriptors */
236         vaddr = dma_alloc_coherent(dev,
237                         sizeof(*tx_queue->tx_bd_base) * tx_queue->tx_ring_size +
238                         sizeof(*rx_queue->rx_bd_base) * rx_queue->rx_ring_size,
239                         &tx_queue->tx_bd_dma_base, GFP_KERNEL);
240         if (!vaddr) {
241                 if (netif_msg_ifup(priv))
242                         pr_err("%s: Could not allocate buffer descriptors!\n",
243                                ndev->name);
244                 return -ENOMEM;
245         }
246
247         tx_queue->tx_bd_base = vaddr;
248         tx_queue->dev = ndev;
249
250         /* Start the rx descriptor ring where the tx ring leaves off */
251         vaddr = vaddr + sizeof(*tx_queue->tx_bd_base) * tx_queue->tx_ring_size;
252         rx_queue->rx_bd_base = vaddr;
253         rx_queue->dev = ndev;
254
255         /* Setup the skbuff rings */
256         tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
257                                   tx_queue->tx_ring_size, GFP_KERNEL);
258         if (!tx_queue->tx_skbuff) {
259                 if (netif_msg_ifup(priv))
260                         pr_err("%s: Could not allocate tx_skbuff\n",
261                                ndev->name);
262                 goto cleanup;
263         }
264
265         for (i = 0; i < tx_queue->tx_ring_size; i++)
266                 tx_queue->tx_skbuff[i] = NULL;
267
268         rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
269                                   rx_queue->rx_ring_size, GFP_KERNEL);
270         if (!rx_queue->rx_skbuff) {
271                 if (netif_msg_ifup(priv))
272                         pr_err("%s: Could not allocate rx_skbuff\n",
273                                ndev->name);
274                 goto cleanup;
275         }
276
277         for (i = 0; i < rx_queue->rx_ring_size; i++)
278                 rx_queue->rx_skbuff[i] = NULL;
279
280         if (gfar_init_bds(ndev))
281                 goto cleanup;
282
283         return 0;
284
285 cleanup:
286         free_skb_resources(priv);
287         return -ENOMEM;
288 }
289
290 static void gfar_init_mac(struct net_device *ndev)
291 {
292         struct gfar_private *priv = netdev_priv(ndev);
293         struct gfar __iomem *regs = priv->regs;
294         struct gfar_priv_tx_q *tx_queue = NULL;
295         struct gfar_priv_rx_q *rx_queue = NULL;
296         u32 rctrl = 0;
297         u32 tctrl = 0;
298         u32 attrs = 0;
299
300         tx_queue = priv->tx_queue;
301         rx_queue = priv->rx_queue;
302
303         /* enet DMA only understands physical addresses */
304         gfar_write(&regs->tbase0, tx_queue->tx_bd_dma_base);
305         gfar_write(&regs->rbase0, tx_queue->tx_bd_dma_base +
306                                   sizeof(*tx_queue->tx_bd_base) *
307                                   tx_queue->tx_ring_size);
308
309         /* Configure the coalescing support */
310         gfar_write(&regs->txic, 0);
311         if (tx_queue->txcoalescing)
312                 gfar_write(&regs->txic, tx_queue->txic);
313
314         gfar_write(&regs->rxic, 0);
315         if (rx_queue->rxcoalescing)
316                 gfar_write(&regs->rxic, rx_queue->rxic);
317
318         if (priv->rx_csum_enable)
319                 rctrl |= RCTRL_CHECKSUMMING;
320
321         if (priv->extended_hash) {
322                 rctrl |= RCTRL_EXTHASH;
323
324                 gfar_clear_exact_match(ndev);
325                 rctrl |= RCTRL_EMEN;
326         }
327
328         if (priv->padding) {
329                 rctrl &= ~RCTRL_PAL_MASK;
330                 rctrl |= RCTRL_PADDING(priv->padding);
331         }
332
333         /* keep vlan related bits if it's enabled */
334         if (priv->vlgrp) {
335                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
336                 tctrl |= TCTRL_VLINS;
337         }
338
339         /* Init rctrl based on our settings */
340         gfar_write(&regs->rctrl, rctrl);
341
342         if (ndev->features & NETIF_F_IP_CSUM)
343                 tctrl |= TCTRL_INIT_CSUM;
344
345         gfar_write(&regs->tctrl, tctrl);
346
347         /* Set the extraction length and index */
348         attrs = ATTRELI_EL(priv->rx_stash_size) |
349                 ATTRELI_EI(priv->rx_stash_index);
350
351         gfar_write(&regs->attreli, attrs);
352
353         /* Start with defaults, and add stashing or locking
354          * depending on the approprate variables */
355         attrs = ATTR_INIT_SETTINGS;
356
357         if (priv->bd_stash_en)
358                 attrs |= ATTR_BDSTASH;
359
360         if (priv->rx_stash_size != 0)
361                 attrs |= ATTR_BUFSTASH;
362
363         gfar_write(&regs->attr, attrs);
364
365         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
366         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
367         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
368 }
369
370 static const struct net_device_ops gfar_netdev_ops = {
371         .ndo_open = gfar_enet_open,
372         .ndo_start_xmit = gfar_start_xmit,
373         .ndo_stop = gfar_close,
374         .ndo_change_mtu = gfar_change_mtu,
375         .ndo_set_multicast_list = gfar_set_multi,
376         .ndo_tx_timeout = gfar_timeout,
377         .ndo_do_ioctl = gfar_ioctl,
378         .ndo_vlan_rx_register = gfar_vlan_rx_register,
379         .ndo_set_mac_address = eth_mac_addr,
380         .ndo_validate_addr = eth_validate_addr,
381 #ifdef CONFIG_NET_POLL_CONTROLLER
382         .ndo_poll_controller = gfar_netpoll,
383 #endif
384 };
385
386 /* Returns 1 if incoming frames use an FCB */
387 static inline int gfar_uses_fcb(struct gfar_private *priv)
388 {
389         return priv->vlgrp || priv->rx_csum_enable;
390 }
391
392 static int gfar_of_init(struct net_device *dev)
393 {
394         const char *model;
395         const char *ctype;
396         const void *mac_addr;
397         u64 addr, size;
398         int err = 0;
399         struct gfar_private *priv = netdev_priv(dev);
400         struct device_node *np = priv->node;
401         const u32 *stash;
402         const u32 *stash_len;
403         const u32 *stash_idx;
404
405         if (!np || !of_device_is_available(np))
406                 return -ENODEV;
407
408         /* get a pointer to the register memory */
409         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
410         priv->regs = ioremap(addr, size);
411
412         if (priv->regs == NULL)
413                 return -ENOMEM;
414
415         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
416
417         model = of_get_property(np, "model", NULL);
418
419         /* If we aren't the FEC we have multiple interrupts */
420         if (model && strcasecmp(model, "FEC")) {
421                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
422
423                 priv->interruptError = irq_of_parse_and_map(np, 2);
424
425                 if (priv->interruptTransmit < 0 ||
426                                 priv->interruptReceive < 0 ||
427                                 priv->interruptError < 0) {
428                         err = -EINVAL;
429                         goto err_out;
430                 }
431         }
432
433         stash = of_get_property(np, "bd-stash", NULL);
434
435         if (stash) {
436                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
437                 priv->bd_stash_en = 1;
438         }
439
440         stash_len = of_get_property(np, "rx-stash-len", NULL);
441
442         if (stash_len)
443                 priv->rx_stash_size = *stash_len;
444
445         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
446
447         if (stash_idx)
448                 priv->rx_stash_index = *stash_idx;
449
450         if (stash_len || stash_idx)
451                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
452
453         mac_addr = of_get_mac_address(np);
454         if (mac_addr)
455                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
456
457         if (model && !strcasecmp(model, "TSEC"))
458                 priv->device_flags =
459                         FSL_GIANFAR_DEV_HAS_GIGABIT |
460                         FSL_GIANFAR_DEV_HAS_COALESCE |
461                         FSL_GIANFAR_DEV_HAS_RMON |
462                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
463         if (model && !strcasecmp(model, "eTSEC"))
464                 priv->device_flags =
465                         FSL_GIANFAR_DEV_HAS_GIGABIT |
466                         FSL_GIANFAR_DEV_HAS_COALESCE |
467                         FSL_GIANFAR_DEV_HAS_RMON |
468                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
469                         FSL_GIANFAR_DEV_HAS_PADDING |
470                         FSL_GIANFAR_DEV_HAS_CSUM |
471                         FSL_GIANFAR_DEV_HAS_VLAN |
472                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
473                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
474
475         ctype = of_get_property(np, "phy-connection-type", NULL);
476
477         /* We only care about rgmii-id.  The rest are autodetected */
478         if (ctype && !strcmp(ctype, "rgmii-id"))
479                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
480         else
481                 priv->interface = PHY_INTERFACE_MODE_MII;
482
483         if (of_get_property(np, "fsl,magic-packet", NULL))
484                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
485
486         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
487
488         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
489         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
490
491         return 0;
492
493 err_out:
494         iounmap(priv->regs);
495         return err;
496 }
497
498 /* Ioctl MII Interface */
499 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
500 {
501         struct gfar_private *priv = netdev_priv(dev);
502
503         if (!netif_running(dev))
504                 return -EINVAL;
505
506         if (!priv->phydev)
507                 return -ENODEV;
508
509         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
510 }
511
512 /* Set up the ethernet device structure, private data,
513  * and anything else we need before we start */
514 static int gfar_probe(struct of_device *ofdev,
515                 const struct of_device_id *match)
516 {
517         u32 tempval;
518         struct net_device *dev = NULL;
519         struct gfar_private *priv = NULL;
520         int err = 0;
521         int len_devname;
522
523         /* Create an ethernet device instance */
524         dev = alloc_etherdev(sizeof (*priv));
525
526         if (NULL == dev)
527                 return -ENOMEM;
528
529         priv = netdev_priv(dev);
530         priv->ndev = dev;
531         priv->ofdev = ofdev;
532         priv->node = ofdev->node;
533         SET_NETDEV_DEV(dev, &ofdev->dev);
534
535         err = gfar_of_init(dev);
536
537         if (err)
538                 goto regs_fail;
539
540         priv->tx_queue = (struct gfar_priv_tx_q *)kmalloc(
541                                 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
542         if (!priv->tx_queue)
543                 goto regs_fail;
544
545         priv->rx_queue = (struct gfar_priv_rx_q *)kmalloc(
546                                 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
547         if (!priv->rx_queue)
548                 goto rx_queue_fail;
549
550         spin_lock_init(&priv->tx_queue->txlock);
551         spin_lock_init(&priv->rx_queue->rxlock);
552         spin_lock_init(&priv->bflock);
553         INIT_WORK(&priv->reset_task, gfar_reset_task);
554
555         dev_set_drvdata(&ofdev->dev, priv);
556
557         /* Stop the DMA engine now, in case it was running before */
558         /* (The firmware could have used it, and left it running). */
559         gfar_halt(dev);
560
561         /* Reset MAC layer */
562         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
563
564         /* We need to delay at least 3 TX clocks */
565         udelay(2);
566
567         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
568         gfar_write(&priv->regs->maccfg1, tempval);
569
570         /* Initialize MACCFG2. */
571         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
572
573         /* Initialize ECNTRL */
574         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
575
576         /* Set the dev->base_addr to the gfar reg region */
577         dev->base_addr = (unsigned long) (priv->regs);
578
579         SET_NETDEV_DEV(dev, &ofdev->dev);
580
581         /* Fill in the dev structure */
582         dev->watchdog_timeo = TX_TIMEOUT;
583         dev->mtu = 1500;
584         dev->netdev_ops = &gfar_netdev_ops;
585         dev->ethtool_ops = &gfar_ethtool_ops;
586
587         /* Register for napi ...NAPI is for each rx_queue */
588         netif_napi_add(dev, &priv->rx_queue->napi, gfar_poll, GFAR_DEV_WEIGHT);
589
590         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
591                 priv->rx_csum_enable = 1;
592                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
593         } else
594                 priv->rx_csum_enable = 0;
595
596         priv->vlgrp = NULL;
597
598         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
599                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
600
601         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
602                 priv->extended_hash = 1;
603                 priv->hash_width = 9;
604
605                 priv->hash_regs[0] = &priv->regs->igaddr0;
606                 priv->hash_regs[1] = &priv->regs->igaddr1;
607                 priv->hash_regs[2] = &priv->regs->igaddr2;
608                 priv->hash_regs[3] = &priv->regs->igaddr3;
609                 priv->hash_regs[4] = &priv->regs->igaddr4;
610                 priv->hash_regs[5] = &priv->regs->igaddr5;
611                 priv->hash_regs[6] = &priv->regs->igaddr6;
612                 priv->hash_regs[7] = &priv->regs->igaddr7;
613                 priv->hash_regs[8] = &priv->regs->gaddr0;
614                 priv->hash_regs[9] = &priv->regs->gaddr1;
615                 priv->hash_regs[10] = &priv->regs->gaddr2;
616                 priv->hash_regs[11] = &priv->regs->gaddr3;
617                 priv->hash_regs[12] = &priv->regs->gaddr4;
618                 priv->hash_regs[13] = &priv->regs->gaddr5;
619                 priv->hash_regs[14] = &priv->regs->gaddr6;
620                 priv->hash_regs[15] = &priv->regs->gaddr7;
621
622         } else {
623                 priv->extended_hash = 0;
624                 priv->hash_width = 8;
625
626                 priv->hash_regs[0] = &priv->regs->gaddr0;
627                 priv->hash_regs[1] = &priv->regs->gaddr1;
628                 priv->hash_regs[2] = &priv->regs->gaddr2;
629                 priv->hash_regs[3] = &priv->regs->gaddr3;
630                 priv->hash_regs[4] = &priv->regs->gaddr4;
631                 priv->hash_regs[5] = &priv->regs->gaddr5;
632                 priv->hash_regs[6] = &priv->regs->gaddr6;
633                 priv->hash_regs[7] = &priv->regs->gaddr7;
634         }
635
636         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
637                 priv->padding = DEFAULT_PADDING;
638         else
639                 priv->padding = 0;
640
641         if (dev->features & NETIF_F_IP_CSUM)
642                 dev->hard_header_len += GMAC_FCB_LEN;
643
644         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
645
646         /* Initializing some of the rx/tx queue level parameters */
647         priv->tx_queue->tx_ring_size = DEFAULT_TX_RING_SIZE;
648         priv->tx_queue->num_txbdfree = DEFAULT_TX_RING_SIZE;
649         priv->tx_queue->txcoalescing = DEFAULT_TX_COALESCE;
650         priv->tx_queue->txic = DEFAULT_TXIC;
651
652         priv->rx_queue->rx_ring_size = DEFAULT_RX_RING_SIZE;
653         priv->rx_queue->rxcoalescing = DEFAULT_RX_COALESCE;
654         priv->rx_queue->rxic = DEFAULT_RXIC;
655
656         /* Enable most messages by default */
657         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
658
659         /* Carrier starts down, phylib will bring it up */
660         netif_carrier_off(dev);
661
662         err = register_netdev(dev);
663
664         if (err) {
665                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
666                                 dev->name);
667                 goto register_fail;
668         }
669
670         device_init_wakeup(&dev->dev,
671                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
672
673         /* fill out IRQ number and name fields */
674         len_devname = strlen(dev->name);
675         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
676         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
677                 strncpy(&priv->int_name_tx[len_devname],
678                         "_tx", sizeof("_tx") + 1);
679
680                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
681                 strncpy(&priv->int_name_rx[len_devname],
682                         "_rx", sizeof("_rx") + 1);
683
684                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
685                 strncpy(&priv->int_name_er[len_devname],
686                         "_er", sizeof("_er") + 1);
687         } else
688                 priv->int_name_tx[len_devname] = '\0';
689
690         /* Create all the sysfs files */
691         gfar_init_sysfs(dev);
692
693         /* Print out the device info */
694         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
695
696         /* Even more device info helps when determining which kernel */
697         /* provided which set of benchmarks. */
698         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
699         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
700                dev->name, priv->rx_queue->rx_ring_size, priv->tx_queue->tx_ring_size);
701
702         return 0;
703
704 register_fail:
705         iounmap(priv->regs);
706         kfree(priv->rx_queue);
707 rx_queue_fail:
708         kfree(priv->tx_queue);
709 regs_fail:
710         if (priv->phy_node)
711                 of_node_put(priv->phy_node);
712         if (priv->tbi_node)
713                 of_node_put(priv->tbi_node);
714         free_netdev(dev);
715         return err;
716 }
717
718 static int gfar_remove(struct of_device *ofdev)
719 {
720         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
721
722         if (priv->phy_node)
723                 of_node_put(priv->phy_node);
724         if (priv->tbi_node)
725                 of_node_put(priv->tbi_node);
726
727         dev_set_drvdata(&ofdev->dev, NULL);
728
729         unregister_netdev(priv->ndev);
730         iounmap(priv->regs);
731         free_netdev(priv->ndev);
732
733         return 0;
734 }
735
736 #ifdef CONFIG_PM
737
738 static int gfar_suspend(struct device *dev)
739 {
740         struct gfar_private *priv = dev_get_drvdata(dev);
741         struct net_device *ndev = priv->ndev;
742         struct gfar_priv_tx_q *tx_queue = NULL;
743         struct gfar_priv_rx_q *rx_queue = NULL;
744         unsigned long flags;
745         u32 tempval;
746
747         int magic_packet = priv->wol_en &&
748                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
749
750         netif_device_detach(ndev);
751         tx_queue = priv->tx_queue;
752         rx_queue = priv->rx_queue;
753
754         if (netif_running(ndev)) {
755                 spin_lock_irqsave(&tx_queue->txlock, flags);
756                 spin_lock(&rx_queue->rxlock);
757
758                 gfar_halt_nodisable(ndev);
759
760                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
761                 tempval = gfar_read(&priv->regs->maccfg1);
762
763                 tempval &= ~MACCFG1_TX_EN;
764
765                 if (!magic_packet)
766                         tempval &= ~MACCFG1_RX_EN;
767
768                 gfar_write(&priv->regs->maccfg1, tempval);
769
770                 spin_unlock(&rx_queue->rxlock);
771                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
772
773                 napi_disable(&rx_queue->napi);
774
775                 if (magic_packet) {
776                         /* Enable interrupt on Magic Packet */
777                         gfar_write(&priv->regs->imask, IMASK_MAG);
778
779                         /* Enable Magic Packet mode */
780                         tempval = gfar_read(&priv->regs->maccfg2);
781                         tempval |= MACCFG2_MPEN;
782                         gfar_write(&priv->regs->maccfg2, tempval);
783                 } else {
784                         phy_stop(priv->phydev);
785                 }
786         }
787
788         return 0;
789 }
790
791 static int gfar_resume(struct device *dev)
792 {
793         struct gfar_private *priv = dev_get_drvdata(dev);
794         struct net_device *ndev = priv->ndev;
795         struct gfar_priv_tx_q *tx_queue = NULL;
796         struct gfar_priv_rx_q *rx_queue = NULL;
797         unsigned long flags;
798         u32 tempval;
799         int magic_packet = priv->wol_en &&
800                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
801
802         if (!netif_running(ndev)) {
803                 netif_device_attach(ndev);
804                 return 0;
805         }
806
807         if (!magic_packet && priv->phydev)
808                 phy_start(priv->phydev);
809
810         /* Disable Magic Packet mode, in case something
811          * else woke us up.
812          */
813         rx_queue = priv->rx_queue;
814         tx_queue = priv->tx_queue;
815
816         spin_lock_irqsave(&tx_queue->txlock, flags);
817         spin_lock(&rx_queue->rxlock);
818
819         tempval = gfar_read(&priv->regs->maccfg2);
820         tempval &= ~MACCFG2_MPEN;
821         gfar_write(&priv->regs->maccfg2, tempval);
822
823         gfar_start(ndev);
824
825         spin_unlock(&rx_queue->rxlock);
826         spin_unlock_irqrestore(&tx_queue->txlock, flags);
827
828         netif_device_attach(ndev);
829
830         napi_enable(&rx_queue->napi);
831
832         return 0;
833 }
834
835 static int gfar_restore(struct device *dev)
836 {
837         struct gfar_private *priv = dev_get_drvdata(dev);
838         struct net_device *ndev = priv->ndev;
839
840         if (!netif_running(ndev))
841                 return 0;
842
843         gfar_init_bds(ndev);
844         init_registers(ndev);
845         gfar_set_mac_address(ndev);
846         gfar_init_mac(ndev);
847         gfar_start(ndev);
848
849         priv->oldlink = 0;
850         priv->oldspeed = 0;
851         priv->oldduplex = -1;
852
853         if (priv->phydev)
854                 phy_start(priv->phydev);
855
856         netif_device_attach(ndev);
857         napi_enable(&priv->napi);
858
859         return 0;
860 }
861
862 static struct dev_pm_ops gfar_pm_ops = {
863         .suspend = gfar_suspend,
864         .resume = gfar_resume,
865         .freeze = gfar_suspend,
866         .thaw = gfar_resume,
867         .restore = gfar_restore,
868 };
869
870 #define GFAR_PM_OPS (&gfar_pm_ops)
871
872 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
873 {
874         return gfar_suspend(&ofdev->dev);
875 }
876
877 static int gfar_legacy_resume(struct of_device *ofdev)
878 {
879         return gfar_resume(&ofdev->dev);
880 }
881
882 #else
883
884 #define GFAR_PM_OPS NULL
885 #define gfar_legacy_suspend NULL
886 #define gfar_legacy_resume NULL
887
888 #endif
889
890 /* Reads the controller's registers to determine what interface
891  * connects it to the PHY.
892  */
893 static phy_interface_t gfar_get_interface(struct net_device *dev)
894 {
895         struct gfar_private *priv = netdev_priv(dev);
896         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
897
898         if (ecntrl & ECNTRL_SGMII_MODE)
899                 return PHY_INTERFACE_MODE_SGMII;
900
901         if (ecntrl & ECNTRL_TBI_MODE) {
902                 if (ecntrl & ECNTRL_REDUCED_MODE)
903                         return PHY_INTERFACE_MODE_RTBI;
904                 else
905                         return PHY_INTERFACE_MODE_TBI;
906         }
907
908         if (ecntrl & ECNTRL_REDUCED_MODE) {
909                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
910                         return PHY_INTERFACE_MODE_RMII;
911                 else {
912                         phy_interface_t interface = priv->interface;
913
914                         /*
915                          * This isn't autodetected right now, so it must
916                          * be set by the device tree or platform code.
917                          */
918                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
919                                 return PHY_INTERFACE_MODE_RGMII_ID;
920
921                         return PHY_INTERFACE_MODE_RGMII;
922                 }
923         }
924
925         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
926                 return PHY_INTERFACE_MODE_GMII;
927
928         return PHY_INTERFACE_MODE_MII;
929 }
930
931
932 /* Initializes driver's PHY state, and attaches to the PHY.
933  * Returns 0 on success.
934  */
935 static int init_phy(struct net_device *dev)
936 {
937         struct gfar_private *priv = netdev_priv(dev);
938         uint gigabit_support =
939                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
940                 SUPPORTED_1000baseT_Full : 0;
941         phy_interface_t interface;
942
943         priv->oldlink = 0;
944         priv->oldspeed = 0;
945         priv->oldduplex = -1;
946
947         interface = gfar_get_interface(dev);
948
949         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
950                                       interface);
951         if (!priv->phydev)
952                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
953                                                          interface);
954         if (!priv->phydev) {
955                 dev_err(&dev->dev, "could not attach to PHY\n");
956                 return -ENODEV;
957         }
958
959         if (interface == PHY_INTERFACE_MODE_SGMII)
960                 gfar_configure_serdes(dev);
961
962         /* Remove any features not supported by the controller */
963         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
964         priv->phydev->advertising = priv->phydev->supported;
965
966         return 0;
967 }
968
969 /*
970  * Initialize TBI PHY interface for communicating with the
971  * SERDES lynx PHY on the chip.  We communicate with this PHY
972  * through the MDIO bus on each controller, treating it as a
973  * "normal" PHY at the address found in the TBIPA register.  We assume
974  * that the TBIPA register is valid.  Either the MDIO bus code will set
975  * it to a value that doesn't conflict with other PHYs on the bus, or the
976  * value doesn't matter, as there are no other PHYs on the bus.
977  */
978 static void gfar_configure_serdes(struct net_device *dev)
979 {
980         struct gfar_private *priv = netdev_priv(dev);
981         struct phy_device *tbiphy;
982
983         if (!priv->tbi_node) {
984                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
985                                     "device tree specify a tbi-handle\n");
986                 return;
987         }
988
989         tbiphy = of_phy_find_device(priv->tbi_node);
990         if (!tbiphy) {
991                 dev_err(&dev->dev, "error: Could not get TBI device\n");
992                 return;
993         }
994
995         /*
996          * If the link is already up, we must already be ok, and don't need to
997          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
998          * everything for us?  Resetting it takes the link down and requires
999          * several seconds for it to come back.
1000          */
1001         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1002                 return;
1003
1004         /* Single clk mode, mii mode off(for serdes communication) */
1005         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1006
1007         phy_write(tbiphy, MII_ADVERTISE,
1008                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1009                         ADVERTISE_1000XPSE_ASYM);
1010
1011         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1012                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1013 }
1014
1015 static void init_registers(struct net_device *dev)
1016 {
1017         struct gfar_private *priv = netdev_priv(dev);
1018
1019         /* Clear IEVENT */
1020         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
1021
1022         /* Initialize IMASK */
1023         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
1024
1025         /* Init hash registers to zero */
1026         gfar_write(&priv->regs->igaddr0, 0);
1027         gfar_write(&priv->regs->igaddr1, 0);
1028         gfar_write(&priv->regs->igaddr2, 0);
1029         gfar_write(&priv->regs->igaddr3, 0);
1030         gfar_write(&priv->regs->igaddr4, 0);
1031         gfar_write(&priv->regs->igaddr5, 0);
1032         gfar_write(&priv->regs->igaddr6, 0);
1033         gfar_write(&priv->regs->igaddr7, 0);
1034
1035         gfar_write(&priv->regs->gaddr0, 0);
1036         gfar_write(&priv->regs->gaddr1, 0);
1037         gfar_write(&priv->regs->gaddr2, 0);
1038         gfar_write(&priv->regs->gaddr3, 0);
1039         gfar_write(&priv->regs->gaddr4, 0);
1040         gfar_write(&priv->regs->gaddr5, 0);
1041         gfar_write(&priv->regs->gaddr6, 0);
1042         gfar_write(&priv->regs->gaddr7, 0);
1043
1044         /* Zero out the rmon mib registers if it has them */
1045         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1046                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
1047
1048                 /* Mask off the CAM interrupts */
1049                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
1050                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
1051         }
1052
1053         /* Initialize the max receive buffer length */
1054         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1055
1056         /* Initialize the Minimum Frame Length Register */
1057         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
1058 }
1059
1060
1061 /* Halt the receive and transmit queues */
1062 static void gfar_halt_nodisable(struct net_device *dev)
1063 {
1064         struct gfar_private *priv = netdev_priv(dev);
1065         struct gfar __iomem *regs = priv->regs;
1066         u32 tempval;
1067
1068         /* Mask all interrupts */
1069         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1070
1071         /* Clear all interrupts */
1072         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1073
1074         /* Stop the DMA, and wait for it to stop */
1075         tempval = gfar_read(&priv->regs->dmactrl);
1076         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1077             != (DMACTRL_GRS | DMACTRL_GTS)) {
1078                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1079                 gfar_write(&priv->regs->dmactrl, tempval);
1080
1081                 while (!(gfar_read(&priv->regs->ievent) &
1082                          (IEVENT_GRSC | IEVENT_GTSC)))
1083                         cpu_relax();
1084         }
1085 }
1086
1087 /* Halt the receive and transmit queues */
1088 void gfar_halt(struct net_device *dev)
1089 {
1090         struct gfar_private *priv = netdev_priv(dev);
1091         struct gfar __iomem *regs = priv->regs;
1092         u32 tempval;
1093
1094         gfar_halt_nodisable(dev);
1095
1096         /* Disable Rx and Tx */
1097         tempval = gfar_read(&regs->maccfg1);
1098         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1099         gfar_write(&regs->maccfg1, tempval);
1100 }
1101
1102 void stop_gfar(struct net_device *dev)
1103 {
1104         struct gfar_private *priv = netdev_priv(dev);
1105         struct gfar_priv_tx_q *tx_queue = NULL;
1106         struct gfar_priv_rx_q *rx_queue = NULL;
1107         unsigned long flags;
1108
1109         phy_stop(priv->phydev);
1110
1111         tx_queue = priv->tx_queue;
1112         rx_queue = priv->rx_queue;
1113
1114         /* Lock it down */
1115         spin_lock_irqsave(&tx_queue->txlock, flags);
1116         spin_lock(&rx_queue->rxlock);
1117
1118         gfar_halt(dev);
1119
1120         spin_unlock(&rx_queue->rxlock);
1121         spin_unlock_irqrestore(&tx_queue->txlock, flags);
1122
1123         /* Free the IRQs */
1124         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1125                 free_irq(priv->interruptError, dev);
1126                 free_irq(priv->interruptTransmit, dev);
1127                 free_irq(priv->interruptReceive, dev);
1128         } else {
1129                 free_irq(priv->interruptTransmit, dev);
1130         }
1131
1132         free_skb_resources(priv);
1133 }
1134
1135 /* If there are any tx skbs or rx skbs still around, free them.
1136  * Then free tx_skbuff and rx_skbuff */
1137 static void free_skb_resources(struct gfar_private *priv)
1138 {
1139         struct device *dev = &priv->ofdev->dev;
1140         struct rxbd8 *rxbdp;
1141         struct txbd8 *txbdp;
1142         struct gfar_priv_tx_q *tx_queue = NULL;
1143         struct gfar_priv_rx_q *rx_queue = NULL;
1144         int i, j;
1145
1146         /* Go through all the buffer descriptors and free their data buffers */
1147         tx_queue = priv->tx_queue;
1148         txbdp = tx_queue->tx_bd_base;
1149
1150         if (!tx_queue->tx_skbuff)
1151                 goto skip_tx_skbuff;
1152
1153         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1154                 if (!tx_queue->tx_skbuff[i])
1155                         continue;
1156
1157                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1158                                 txbdp->length, DMA_TO_DEVICE);
1159                 txbdp->lstatus = 0;
1160                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; j++) {
1161                         txbdp++;
1162                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1163                                         txbdp->length, DMA_TO_DEVICE);
1164                 }
1165                 txbdp++;
1166                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1167                 tx_queue->tx_skbuff[i] = NULL;
1168         }
1169
1170         kfree(tx_queue->tx_skbuff);
1171 skip_tx_skbuff:
1172
1173         rx_queue = priv->rx_queue;
1174         rxbdp = rx_queue->rx_bd_base;
1175
1176         if (!rx_queue->rx_skbuff)
1177                 goto skip_rx_skbuff;
1178
1179         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1180                 if (rx_queue->rx_skbuff[i]) {
1181                         dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
1182                                          priv->rx_buffer_size,
1183                                         DMA_FROM_DEVICE);
1184                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1185                         rx_queue->rx_skbuff[i] = NULL;
1186                 }
1187
1188                 rxbdp->lstatus = 0;
1189                 rxbdp->bufPtr = 0;
1190                 rxbdp++;
1191         }
1192
1193         kfree(rx_queue->rx_skbuff);
1194 skip_rx_skbuff:
1195
1196         dma_free_coherent(dev, sizeof(*txbdp) * tx_queue->tx_ring_size +
1197                                sizeof(*rxbdp) * rx_queue->rx_ring_size,
1198                           tx_queue->tx_bd_base, tx_queue->tx_bd_dma_base);
1199 }
1200
1201 void gfar_start(struct net_device *dev)
1202 {
1203         struct gfar_private *priv = netdev_priv(dev);
1204         struct gfar_priv_tx_q *tx_queue;
1205         struct gfar_priv_rx_q *rx_queue;
1206         struct gfar __iomem *regs = priv->regs;
1207         u32 tempval;
1208
1209         /* Enable Rx and Tx in MACCFG1 */
1210         tempval = gfar_read(&regs->maccfg1);
1211         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1212         gfar_write(&regs->maccfg1, tempval);
1213
1214         /* Initialize DMACTRL to have WWR and WOP */
1215         tempval = gfar_read(&priv->regs->dmactrl);
1216         tempval |= DMACTRL_INIT_SETTINGS;
1217         gfar_write(&priv->regs->dmactrl, tempval);
1218
1219         /* Make sure we aren't stopped */
1220         tempval = gfar_read(&priv->regs->dmactrl);
1221         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1222         gfar_write(&priv->regs->dmactrl, tempval);
1223
1224         /* Clear THLT/RHLT, so that the DMA starts polling now */
1225         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
1226         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
1227
1228         /* Unmask the interrupts we look for */
1229         gfar_write(&regs->imask, IMASK_DEFAULT);
1230
1231         dev->trans_start = jiffies;
1232 }
1233
1234 /* Bring the controller up and running */
1235 int startup_gfar(struct net_device *ndev)
1236 {
1237         struct gfar_private *priv = netdev_priv(ndev);
1238         struct gfar __iomem *regs = priv->regs;
1239         int err;
1240
1241         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1242
1243         err = gfar_alloc_skb_resources(ndev);
1244         if (err)
1245                 return err;
1246
1247         gfar_init_mac(ndev);
1248
1249         /* If the device has multiple interrupts, register for
1250          * them.  Otherwise, only register for the one */
1251         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1252                 /* Install our interrupt handlers for Error,
1253                  * Transmit, and Receive */
1254                 err = request_irq(priv->interruptError, gfar_error, 0,
1255                                   priv->int_name_er, ndev);
1256                 if (err) {
1257                         if (netif_msg_intr(priv))
1258                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1259                                        priv->interruptError);
1260                         goto err_irq_fail;
1261                 }
1262
1263                 err = request_irq(priv->interruptTransmit, gfar_transmit, 0,
1264                                   priv->int_name_tx, ndev);
1265                 if (err) {
1266                         if (netif_msg_intr(priv))
1267                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1268                                        priv->interruptTransmit);
1269                         goto tx_irq_fail;
1270                 }
1271
1272                 err = request_irq(priv->interruptReceive, gfar_receive, 0,
1273                                   priv->int_name_rx, ndev);
1274                 if (err) {
1275                         if (netif_msg_intr(priv))
1276                                 pr_err("%s: Can't get IRQ %d (receive0)\n",
1277                                        ndev->name, priv->interruptReceive);
1278                         goto rx_irq_fail;
1279                 }
1280         } else {
1281                 err = request_irq(priv->interruptTransmit, gfar_interrupt,
1282                                 0, priv->int_name_tx, ndev);
1283                 if (err) {
1284                         if (netif_msg_intr(priv))
1285                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1286                                        priv->interruptTransmit);
1287                         goto err_irq_fail;
1288                 }
1289         }
1290
1291         /* Start the controller */
1292         gfar_start(ndev);
1293
1294         phy_start(priv->phydev);
1295
1296         return 0;
1297
1298 rx_irq_fail:
1299         free_irq(priv->interruptTransmit, ndev);
1300 tx_irq_fail:
1301         free_irq(priv->interruptError, ndev);
1302 err_irq_fail:
1303         free_skb_resources(priv);
1304         return err;
1305 }
1306
1307 /* Called when something needs to use the ethernet device */
1308 /* Returns 0 for success. */
1309 static int gfar_enet_open(struct net_device *dev)
1310 {
1311         struct gfar_private *priv = netdev_priv(dev);
1312         int err;
1313
1314         napi_enable(&priv->rx_queue->napi);
1315
1316         skb_queue_head_init(&priv->rx_recycle);
1317
1318         /* Initialize a bunch of registers */
1319         init_registers(dev);
1320
1321         gfar_set_mac_address(dev);
1322
1323         err = init_phy(dev);
1324
1325         if (err) {
1326                 napi_disable(&priv->rx_queue->napi);
1327                 return err;
1328         }
1329
1330         err = startup_gfar(dev);
1331         if (err) {
1332                 napi_disable(&priv->rx_queue->napi);
1333                 return err;
1334         }
1335
1336         netif_start_queue(dev);
1337
1338         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1339
1340         return err;
1341 }
1342
1343 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1344 {
1345         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1346
1347         memset(fcb, 0, GMAC_FCB_LEN);
1348
1349         return fcb;
1350 }
1351
1352 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1353 {
1354         u8 flags = 0;
1355
1356         /* If we're here, it's a IP packet with a TCP or UDP
1357          * payload.  We set it to checksum, using a pseudo-header
1358          * we provide
1359          */
1360         flags = TXFCB_DEFAULT;
1361
1362         /* Tell the controller what the protocol is */
1363         /* And provide the already calculated phcs */
1364         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1365                 flags |= TXFCB_UDP;
1366                 fcb->phcs = udp_hdr(skb)->check;
1367         } else
1368                 fcb->phcs = tcp_hdr(skb)->check;
1369
1370         /* l3os is the distance between the start of the
1371          * frame (skb->data) and the start of the IP hdr.
1372          * l4os is the distance between the start of the
1373          * l3 hdr and the l4 hdr */
1374         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1375         fcb->l4os = skb_network_header_len(skb);
1376
1377         fcb->flags = flags;
1378 }
1379
1380 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1381 {
1382         fcb->flags |= TXFCB_VLN;
1383         fcb->vlctl = vlan_tx_tag_get(skb);
1384 }
1385
1386 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1387                                struct txbd8 *base, int ring_size)
1388 {
1389         struct txbd8 *new_bd = bdp + stride;
1390
1391         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1392 }
1393
1394 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1395                 int ring_size)
1396 {
1397         return skip_txbd(bdp, 1, base, ring_size);
1398 }
1399
1400 /* This is called by the kernel when a frame is ready for transmission. */
1401 /* It is pointed to by the dev->hard_start_xmit function pointer */
1402 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1403 {
1404         struct gfar_private *priv = netdev_priv(dev);
1405         struct gfar_priv_tx_q *tx_queue = NULL;
1406         struct txfcb *fcb = NULL;
1407         struct txbd8 *txbdp, *txbdp_start, *base;
1408         u32 lstatus;
1409         int i;
1410         u32 bufaddr;
1411         unsigned long flags;
1412         unsigned int nr_frags, length;
1413
1414         tx_queue = priv->tx_queue;
1415         base = tx_queue->tx_bd_base;
1416
1417         /* make space for additional header when fcb is needed */
1418         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1419                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1420                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1421                 struct sk_buff *skb_new;
1422
1423                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1424                 if (!skb_new) {
1425                         dev->stats.tx_errors++;
1426                         kfree_skb(skb);
1427                         return NETDEV_TX_OK;
1428                 }
1429                 kfree_skb(skb);
1430                 skb = skb_new;
1431         }
1432
1433         /* total number of fragments in the SKB */
1434         nr_frags = skb_shinfo(skb)->nr_frags;
1435
1436         spin_lock_irqsave(&tx_queue->txlock, flags);
1437
1438         /* check if there is space to queue this packet */
1439         if ((nr_frags+1) > tx_queue->num_txbdfree) {
1440                 /* no space, stop the queue */
1441                 netif_stop_queue(dev);
1442                 dev->stats.tx_fifo_errors++;
1443                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1444                 return NETDEV_TX_BUSY;
1445         }
1446
1447         /* Update transmit stats */
1448         dev->stats.tx_bytes += skb->len;
1449
1450         txbdp = txbdp_start = tx_queue->cur_tx;
1451
1452         if (nr_frags == 0) {
1453                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1454         } else {
1455                 /* Place the fragment addresses and lengths into the TxBDs */
1456                 for (i = 0; i < nr_frags; i++) {
1457                         /* Point at the next BD, wrapping as needed */
1458                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1459
1460                         length = skb_shinfo(skb)->frags[i].size;
1461
1462                         lstatus = txbdp->lstatus | length |
1463                                 BD_LFLAG(TXBD_READY);
1464
1465                         /* Handle the last BD specially */
1466                         if (i == nr_frags - 1)
1467                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1468
1469                         bufaddr = dma_map_page(&priv->ofdev->dev,
1470                                         skb_shinfo(skb)->frags[i].page,
1471                                         skb_shinfo(skb)->frags[i].page_offset,
1472                                         length,
1473                                         DMA_TO_DEVICE);
1474
1475                         /* set the TxBD length and buffer pointer */
1476                         txbdp->bufPtr = bufaddr;
1477                         txbdp->lstatus = lstatus;
1478                 }
1479
1480                 lstatus = txbdp_start->lstatus;
1481         }
1482
1483         /* Set up checksumming */
1484         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1485                 fcb = gfar_add_fcb(skb);
1486                 lstatus |= BD_LFLAG(TXBD_TOE);
1487                 gfar_tx_checksum(skb, fcb);
1488         }
1489
1490         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1491                 if (unlikely(NULL == fcb)) {
1492                         fcb = gfar_add_fcb(skb);
1493                         lstatus |= BD_LFLAG(TXBD_TOE);
1494                 }
1495
1496                 gfar_tx_vlan(skb, fcb);
1497         }
1498
1499         /* setup the TxBD length and buffer pointer for the first BD */
1500         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1501         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1502                         skb_headlen(skb), DMA_TO_DEVICE);
1503
1504         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1505
1506         /*
1507          * The powerpc-specific eieio() is used, as wmb() has too strong
1508          * semantics (it requires synchronization between cacheable and
1509          * uncacheable mappings, which eieio doesn't provide and which we
1510          * don't need), thus requiring a more expensive sync instruction.  At
1511          * some point, the set of architecture-independent barrier functions
1512          * should be expanded to include weaker barriers.
1513          */
1514         eieio();
1515
1516         txbdp_start->lstatus = lstatus;
1517
1518         /* Update the current skb pointer to the next entry we will use
1519          * (wrapping if necessary) */
1520         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1521                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1522
1523         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1524
1525         /* reduce TxBD free count */
1526         tx_queue->num_txbdfree -= (nr_frags + 1);
1527
1528         dev->trans_start = jiffies;
1529
1530         /* If the next BD still needs to be cleaned up, then the bds
1531            are full.  We need to tell the kernel to stop sending us stuff. */
1532         if (!tx_queue->num_txbdfree) {
1533                 netif_stop_queue(dev);
1534
1535                 dev->stats.tx_fifo_errors++;
1536         }
1537
1538         /* Tell the DMA to go go go */
1539         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1540
1541         /* Unlock priv */
1542         spin_unlock_irqrestore(&tx_queue->txlock, flags);
1543
1544         return NETDEV_TX_OK;
1545 }
1546
1547 /* Stops the kernel queue, and halts the controller */
1548 static int gfar_close(struct net_device *dev)
1549 {
1550         struct gfar_private *priv = netdev_priv(dev);
1551
1552         napi_disable(&priv->rx_queue->napi);
1553
1554         skb_queue_purge(&priv->rx_recycle);
1555         cancel_work_sync(&priv->reset_task);
1556         stop_gfar(dev);
1557
1558         /* Disconnect from the PHY */
1559         phy_disconnect(priv->phydev);
1560         priv->phydev = NULL;
1561
1562         netif_stop_queue(dev);
1563
1564         return 0;
1565 }
1566
1567 /* Changes the mac address if the controller is not running. */
1568 static int gfar_set_mac_address(struct net_device *dev)
1569 {
1570         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1571
1572         return 0;
1573 }
1574
1575
1576 /* Enables and disables VLAN insertion/extraction */
1577 static void gfar_vlan_rx_register(struct net_device *dev,
1578                 struct vlan_group *grp)
1579 {
1580         struct gfar_private *priv = netdev_priv(dev);
1581         struct gfar_priv_rx_q *rx_queue = NULL;
1582         unsigned long flags;
1583         u32 tempval;
1584
1585         rx_queue = priv->rx_queue;
1586         spin_lock_irqsave(&rx_queue->rxlock, flags);
1587
1588         priv->vlgrp = grp;
1589
1590         if (grp) {
1591                 /* Enable VLAN tag insertion */
1592                 tempval = gfar_read(&priv->regs->tctrl);
1593                 tempval |= TCTRL_VLINS;
1594
1595                 gfar_write(&priv->regs->tctrl, tempval);
1596
1597                 /* Enable VLAN tag extraction */
1598                 tempval = gfar_read(&priv->regs->rctrl);
1599                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1600                 gfar_write(&priv->regs->rctrl, tempval);
1601         } else {
1602                 /* Disable VLAN tag insertion */
1603                 tempval = gfar_read(&priv->regs->tctrl);
1604                 tempval &= ~TCTRL_VLINS;
1605                 gfar_write(&priv->regs->tctrl, tempval);
1606
1607                 /* Disable VLAN tag extraction */
1608                 tempval = gfar_read(&priv->regs->rctrl);
1609                 tempval &= ~RCTRL_VLEX;
1610                 /* If parse is no longer required, then disable parser */
1611                 if (tempval & RCTRL_REQ_PARSER)
1612                         tempval |= RCTRL_PRSDEP_INIT;
1613                 else
1614                         tempval &= ~RCTRL_PRSDEP_INIT;
1615                 gfar_write(&priv->regs->rctrl, tempval);
1616         }
1617
1618         gfar_change_mtu(dev, dev->mtu);
1619
1620         spin_unlock_irqrestore(&rx_queue->rxlock, flags);
1621 }
1622
1623 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1624 {
1625         int tempsize, tempval;
1626         struct gfar_private *priv = netdev_priv(dev);
1627         int oldsize = priv->rx_buffer_size;
1628         int frame_size = new_mtu + ETH_HLEN;
1629
1630         if (priv->vlgrp)
1631                 frame_size += VLAN_HLEN;
1632
1633         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1634                 if (netif_msg_drv(priv))
1635                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1636                                         dev->name);
1637                 return -EINVAL;
1638         }
1639
1640         if (gfar_uses_fcb(priv))
1641                 frame_size += GMAC_FCB_LEN;
1642
1643         frame_size += priv->padding;
1644
1645         tempsize =
1646             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1647             INCREMENTAL_BUFFER_SIZE;
1648
1649         /* Only stop and start the controller if it isn't already
1650          * stopped, and we changed something */
1651         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1652                 stop_gfar(dev);
1653
1654         priv->rx_buffer_size = tempsize;
1655
1656         dev->mtu = new_mtu;
1657
1658         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1659         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1660
1661         /* If the mtu is larger than the max size for standard
1662          * ethernet frames (ie, a jumbo frame), then set maccfg2
1663          * to allow huge frames, and to check the length */
1664         tempval = gfar_read(&priv->regs->maccfg2);
1665
1666         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1667                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1668         else
1669                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1670
1671         gfar_write(&priv->regs->maccfg2, tempval);
1672
1673         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1674                 startup_gfar(dev);
1675
1676         return 0;
1677 }
1678
1679 /* gfar_reset_task gets scheduled when a packet has not been
1680  * transmitted after a set amount of time.
1681  * For now, assume that clearing out all the structures, and
1682  * starting over will fix the problem.
1683  */
1684 static void gfar_reset_task(struct work_struct *work)
1685 {
1686         struct gfar_private *priv = container_of(work, struct gfar_private,
1687                         reset_task);
1688         struct net_device *dev = priv->ndev;
1689
1690         if (dev->flags & IFF_UP) {
1691                 netif_stop_queue(dev);
1692                 stop_gfar(dev);
1693                 startup_gfar(dev);
1694                 netif_start_queue(dev);
1695         }
1696
1697         netif_tx_schedule_all(dev);
1698 }
1699
1700 static void gfar_timeout(struct net_device *dev)
1701 {
1702         struct gfar_private *priv = netdev_priv(dev);
1703
1704         dev->stats.tx_errors++;
1705         schedule_work(&priv->reset_task);
1706 }
1707
1708 /* Interrupt Handler for Transmit complete */
1709 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1710 {
1711         struct net_device *dev = tx_queue->dev;
1712         struct gfar_private *priv = netdev_priv(dev);
1713         struct gfar_priv_rx_q *rx_queue = NULL;
1714         struct txbd8 *bdp;
1715         struct txbd8 *lbdp = NULL;
1716         struct txbd8 *base = tx_queue->tx_bd_base;
1717         struct sk_buff *skb;
1718         int skb_dirtytx;
1719         int tx_ring_size = tx_queue->tx_ring_size;
1720         int frags = 0;
1721         int i;
1722         int howmany = 0;
1723         u32 lstatus;
1724
1725         rx_queue = priv->rx_queue;
1726         bdp = tx_queue->dirty_tx;
1727         skb_dirtytx = tx_queue->skb_dirtytx;
1728
1729         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
1730                 frags = skb_shinfo(skb)->nr_frags;
1731                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1732
1733                 lstatus = lbdp->lstatus;
1734
1735                 /* Only clean completed frames */
1736                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1737                                 (lstatus & BD_LENGTH_MASK))
1738                         break;
1739
1740                 dma_unmap_single(&priv->ofdev->dev,
1741                                 bdp->bufPtr,
1742                                 bdp->length,
1743                                 DMA_TO_DEVICE);
1744
1745                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1746                 bdp = next_txbd(bdp, base, tx_ring_size);
1747
1748                 for (i = 0; i < frags; i++) {
1749                         dma_unmap_page(&priv->ofdev->dev,
1750                                         bdp->bufPtr,
1751                                         bdp->length,
1752                                         DMA_TO_DEVICE);
1753                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1754                         bdp = next_txbd(bdp, base, tx_ring_size);
1755                 }
1756
1757                 /*
1758                  * If there's room in the queue (limit it to rx_buffer_size)
1759                  * we add this skb back into the pool, if it's the right size
1760                  */
1761                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
1762                                 skb_recycle_check(skb, priv->rx_buffer_size +
1763                                         RXBUF_ALIGNMENT))
1764                         __skb_queue_head(&priv->rx_recycle, skb);
1765                 else
1766                         dev_kfree_skb_any(skb);
1767
1768                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
1769
1770                 skb_dirtytx = (skb_dirtytx + 1) &
1771                         TX_RING_MOD_MASK(tx_ring_size);
1772
1773                 howmany++;
1774                 tx_queue->num_txbdfree += frags + 1;
1775         }
1776
1777         /* If we freed a buffer, we can restart transmission, if necessary */
1778         if (netif_queue_stopped(dev) && tx_queue->num_txbdfree)
1779                 netif_wake_queue(dev);
1780
1781         /* Update dirty indicators */
1782         tx_queue->skb_dirtytx = skb_dirtytx;
1783         tx_queue->dirty_tx = bdp;
1784
1785         dev->stats.tx_packets += howmany;
1786
1787         return howmany;
1788 }
1789
1790 static void gfar_schedule_cleanup(struct net_device *dev)
1791 {
1792         struct gfar_private *priv = netdev_priv(dev);
1793         struct gfar_priv_tx_q *tx_queue = NULL;
1794         struct gfar_priv_rx_q *rx_queue = NULL;
1795         unsigned long flags;
1796
1797         rx_queue = priv->rx_queue;
1798         tx_queue = priv->tx_queue;
1799         spin_lock_irqsave(&tx_queue->txlock, flags);
1800         spin_lock(&rx_queue->rxlock);
1801
1802         if (napi_schedule_prep(&rx_queue->napi)) {
1803                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1804                 __napi_schedule(&rx_queue->napi);
1805         } else {
1806                 /*
1807                  * Clear IEVENT, so interrupts aren't called again
1808                  * because of the packets that have already arrived.
1809                  */
1810                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1811         }
1812
1813         spin_unlock(&rx_queue->rxlock);
1814         spin_unlock_irqrestore(&tx_queue->txlock, flags);
1815 }
1816
1817 /* Interrupt Handler for Transmit complete */
1818 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1819 {
1820         gfar_schedule_cleanup((struct net_device *)dev_id);
1821         return IRQ_HANDLED;
1822 }
1823
1824 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
1825                 struct sk_buff *skb)
1826 {
1827         struct net_device *dev = rx_queue->dev;
1828         struct gfar_private *priv = netdev_priv(dev);
1829         dma_addr_t buf;
1830
1831         buf = dma_map_single(&priv->ofdev->dev, skb->data,
1832                              priv->rx_buffer_size, DMA_FROM_DEVICE);
1833         gfar_init_rxbdp(rx_queue, bdp, buf);
1834 }
1835
1836
1837 struct sk_buff * gfar_new_skb(struct net_device *dev)
1838 {
1839         unsigned int alignamount;
1840         struct gfar_private *priv = netdev_priv(dev);
1841         struct sk_buff *skb = NULL;
1842
1843         skb = __skb_dequeue(&priv->rx_recycle);
1844         if (!skb)
1845                 skb = netdev_alloc_skb(dev,
1846                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1847
1848         if (!skb)
1849                 return NULL;
1850
1851         alignamount = RXBUF_ALIGNMENT -
1852                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1853
1854         /* We need the data buffer to be aligned properly.  We will reserve
1855          * as many bytes as needed to align the data properly
1856          */
1857         skb_reserve(skb, alignamount);
1858
1859         return skb;
1860 }
1861
1862 static inline void count_errors(unsigned short status, struct net_device *dev)
1863 {
1864         struct gfar_private *priv = netdev_priv(dev);
1865         struct net_device_stats *stats = &dev->stats;
1866         struct gfar_extra_stats *estats = &priv->extra_stats;
1867
1868         /* If the packet was truncated, none of the other errors
1869          * matter */
1870         if (status & RXBD_TRUNCATED) {
1871                 stats->rx_length_errors++;
1872
1873                 estats->rx_trunc++;
1874
1875                 return;
1876         }
1877         /* Count the errors, if there were any */
1878         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1879                 stats->rx_length_errors++;
1880
1881                 if (status & RXBD_LARGE)
1882                         estats->rx_large++;
1883                 else
1884                         estats->rx_short++;
1885         }
1886         if (status & RXBD_NONOCTET) {
1887                 stats->rx_frame_errors++;
1888                 estats->rx_nonoctet++;
1889         }
1890         if (status & RXBD_CRCERR) {
1891                 estats->rx_crcerr++;
1892                 stats->rx_crc_errors++;
1893         }
1894         if (status & RXBD_OVERRUN) {
1895                 estats->rx_overrun++;
1896                 stats->rx_crc_errors++;
1897         }
1898 }
1899
1900 irqreturn_t gfar_receive(int irq, void *dev_id)
1901 {
1902         gfar_schedule_cleanup((struct net_device *)dev_id);
1903         return IRQ_HANDLED;
1904 }
1905
1906 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1907 {
1908         /* If valid headers were found, and valid sums
1909          * were verified, then we tell the kernel that no
1910          * checksumming is necessary.  Otherwise, it is */
1911         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1912                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1913         else
1914                 skb->ip_summed = CHECKSUM_NONE;
1915 }
1916
1917
1918 /* gfar_process_frame() -- handle one incoming packet if skb
1919  * isn't NULL.  */
1920 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1921                               int amount_pull)
1922 {
1923         struct gfar_private *priv = netdev_priv(dev);
1924         struct rxfcb *fcb = NULL;
1925
1926         int ret;
1927
1928         /* fcb is at the beginning if exists */
1929         fcb = (struct rxfcb *)skb->data;
1930
1931         /* Remove the FCB from the skb */
1932         /* Remove the padded bytes, if there are any */
1933         if (amount_pull)
1934                 skb_pull(skb, amount_pull);
1935
1936         if (priv->rx_csum_enable)
1937                 gfar_rx_checksum(skb, fcb);
1938
1939         /* Tell the skb what kind of packet this is */
1940         skb->protocol = eth_type_trans(skb, dev);
1941
1942         /* Send the packet up the stack */
1943         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1944                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1945         else
1946                 ret = netif_receive_skb(skb);
1947
1948         if (NET_RX_DROP == ret)
1949                 priv->extra_stats.kernel_dropped++;
1950
1951         return 0;
1952 }
1953
1954 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1955  *   until the budget/quota has been reached. Returns the number
1956  *   of frames handled
1957  */
1958 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1959 {
1960         struct net_device *dev = rx_queue->dev;
1961         struct rxbd8 *bdp, *base;
1962         struct sk_buff *skb;
1963         int pkt_len;
1964         int amount_pull;
1965         int howmany = 0;
1966         struct gfar_private *priv = netdev_priv(dev);
1967
1968         /* Get the first full descriptor */
1969         bdp = rx_queue->cur_rx;
1970         base = rx_queue->rx_bd_base;
1971
1972         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1973                 priv->padding;
1974
1975         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1976                 struct sk_buff *newskb;
1977                 rmb();
1978
1979                 /* Add another skb for the future */
1980                 newskb = gfar_new_skb(dev);
1981
1982                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1983
1984                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1985                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1986
1987                 /* We drop the frame if we failed to allocate a new buffer */
1988                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1989                                  bdp->status & RXBD_ERR)) {
1990                         count_errors(bdp->status, dev);
1991
1992                         if (unlikely(!newskb))
1993                                 newskb = skb;
1994                         else if (skb) {
1995                                 /*
1996                                  * We need to reset ->data to what it
1997                                  * was before gfar_new_skb() re-aligned
1998                                  * it to an RXBUF_ALIGNMENT boundary
1999                                  * before we put the skb back on the
2000                                  * recycle list.
2001                                  */
2002                                 skb->data = skb->head + NET_SKB_PAD;
2003                                 __skb_queue_head(&priv->rx_recycle, skb);
2004                         }
2005                 } else {
2006                         /* Increment the number of packets */
2007                         dev->stats.rx_packets++;
2008                         howmany++;
2009
2010                         if (likely(skb)) {
2011                                 pkt_len = bdp->length - ETH_FCS_LEN;
2012                                 /* Remove the FCS from the packet length */
2013                                 skb_put(skb, pkt_len);
2014                                 dev->stats.rx_bytes += pkt_len;
2015
2016                                 if (in_irq() || irqs_disabled())
2017                                         printk("Interrupt problem!\n");
2018                                 gfar_process_frame(dev, skb, amount_pull);
2019
2020                         } else {
2021                                 if (netif_msg_rx_err(priv))
2022                                         printk(KERN_WARNING
2023                                                "%s: Missing skb!\n", dev->name);
2024                                 dev->stats.rx_dropped++;
2025                                 priv->extra_stats.rx_skbmissing++;
2026                         }
2027
2028                 }
2029
2030                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2031
2032                 /* Setup the new bdp */
2033                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2034
2035                 /* Update to the next pointer */
2036                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2037
2038                 /* update to point at the next skb */
2039                 rx_queue->skb_currx =
2040                     (rx_queue->skb_currx + 1) &
2041                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2042         }
2043
2044         /* Update the current rxbd pointer to be the next one */
2045         rx_queue->cur_rx = bdp;
2046
2047         return howmany;
2048 }
2049
2050 static int gfar_poll(struct napi_struct *napi, int budget)
2051 {
2052         struct gfar_priv_rx_q *rx_queue = container_of(napi,
2053                         struct gfar_priv_rx_q, napi);
2054         struct net_device *dev = rx_queue->dev;
2055         struct gfar_private *priv = netdev_priv(dev);
2056         struct gfar_priv_tx_q *tx_queue = NULL;
2057         int tx_cleaned = 0;
2058         int rx_cleaned = 0;
2059         unsigned long flags;
2060
2061         /* Clear IEVENT, so interrupts aren't called again
2062          * because of the packets that have already arrived */
2063         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
2064         tx_queue = priv->tx_queue;
2065
2066         /* If we fail to get the lock, don't bother with the TX BDs */
2067         if (spin_trylock_irqsave(&tx_queue->txlock, flags)) {
2068                 tx_cleaned = gfar_clean_tx_ring(tx_queue);
2069                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2070         }
2071
2072         rx_cleaned = gfar_clean_rx_ring(rx_queue, budget);
2073
2074         if (tx_cleaned)
2075                 return budget;
2076
2077         if (rx_cleaned < budget) {
2078                 napi_complete(napi);
2079
2080                 /* Clear the halt bit in RSTAT */
2081                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
2082
2083                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
2084
2085                 /* If we are coalescing interrupts, update the timer */
2086                 /* Otherwise, clear it */
2087                 if (likely(rx_queue->rxcoalescing)) {
2088                         gfar_write(&priv->regs->rxic, 0);
2089                         gfar_write(&priv->regs->rxic, rx_queue->rxic);
2090                 }
2091                 if (likely(tx_queue->txcoalescing)) {
2092                         gfar_write(&priv->regs->txic, 0);
2093                         gfar_write(&priv->regs->txic, tx_queue->txic);
2094                 }
2095         }
2096
2097         return rx_cleaned;
2098 }
2099
2100 #ifdef CONFIG_NET_POLL_CONTROLLER
2101 /*
2102  * Polling 'interrupt' - used by things like netconsole to send skbs
2103  * without having to re-enable interrupts. It's not called while
2104  * the interrupt routine is executing.
2105  */
2106 static void gfar_netpoll(struct net_device *dev)
2107 {
2108         struct gfar_private *priv = netdev_priv(dev);
2109
2110         /* If the device has multiple interrupts, run tx/rx */
2111         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2112                 disable_irq(priv->interruptTransmit);
2113                 disable_irq(priv->interruptReceive);
2114                 disable_irq(priv->interruptError);
2115                 gfar_interrupt(priv->interruptTransmit, dev);
2116                 enable_irq(priv->interruptError);
2117                 enable_irq(priv->interruptReceive);
2118                 enable_irq(priv->interruptTransmit);
2119         } else {
2120                 disable_irq(priv->interruptTransmit);
2121                 gfar_interrupt(priv->interruptTransmit, dev);
2122                 enable_irq(priv->interruptTransmit);
2123         }
2124 }
2125 #endif
2126
2127 /* The interrupt handler for devices with one interrupt */
2128 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
2129 {
2130         struct net_device *dev = dev_id;
2131         struct gfar_private *priv = netdev_priv(dev);
2132
2133         /* Save ievent for future reference */
2134         u32 events = gfar_read(&priv->regs->ievent);
2135
2136         /* Check for reception */
2137         if (events & IEVENT_RX_MASK)
2138                 gfar_receive(irq, dev_id);
2139
2140         /* Check for transmit completion */
2141         if (events & IEVENT_TX_MASK)
2142                 gfar_transmit(irq, dev_id);
2143
2144         /* Check for errors */
2145         if (events & IEVENT_ERR_MASK)
2146                 gfar_error(irq, dev_id);
2147
2148         return IRQ_HANDLED;
2149 }
2150
2151 /* Called every time the controller might need to be made
2152  * aware of new link state.  The PHY code conveys this
2153  * information through variables in the phydev structure, and this
2154  * function converts those variables into the appropriate
2155  * register values, and can bring down the device if needed.
2156  */
2157 static void adjust_link(struct net_device *dev)
2158 {
2159         struct gfar_private *priv = netdev_priv(dev);
2160         struct gfar_priv_tx_q *tx_queue = NULL;
2161         struct gfar __iomem *regs = priv->regs;
2162         unsigned long flags;
2163         struct phy_device *phydev = priv->phydev;
2164         int new_state = 0;
2165
2166         tx_queue = priv->tx_queue;
2167         spin_lock_irqsave(&tx_queue->txlock, flags);
2168         if (phydev->link) {
2169                 u32 tempval = gfar_read(&regs->maccfg2);
2170                 u32 ecntrl = gfar_read(&regs->ecntrl);
2171
2172                 /* Now we make sure that we can be in full duplex mode.
2173                  * If not, we operate in half-duplex mode. */
2174                 if (phydev->duplex != priv->oldduplex) {
2175                         new_state = 1;
2176                         if (!(phydev->duplex))
2177                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2178                         else
2179                                 tempval |= MACCFG2_FULL_DUPLEX;
2180
2181                         priv->oldduplex = phydev->duplex;
2182                 }
2183
2184                 if (phydev->speed != priv->oldspeed) {
2185                         new_state = 1;
2186                         switch (phydev->speed) {
2187                         case 1000:
2188                                 tempval =
2189                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2190
2191                                 ecntrl &= ~(ECNTRL_R100);
2192                                 break;
2193                         case 100:
2194                         case 10:
2195                                 tempval =
2196                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2197
2198                                 /* Reduced mode distinguishes
2199                                  * between 10 and 100 */
2200                                 if (phydev->speed == SPEED_100)
2201                                         ecntrl |= ECNTRL_R100;
2202                                 else
2203                                         ecntrl &= ~(ECNTRL_R100);
2204                                 break;
2205                         default:
2206                                 if (netif_msg_link(priv))
2207                                         printk(KERN_WARNING
2208                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2209                                                 dev->name, phydev->speed);
2210                                 break;
2211                         }
2212
2213                         priv->oldspeed = phydev->speed;
2214                 }
2215
2216                 gfar_write(&regs->maccfg2, tempval);
2217                 gfar_write(&regs->ecntrl, ecntrl);
2218
2219                 if (!priv->oldlink) {
2220                         new_state = 1;
2221                         priv->oldlink = 1;
2222                 }
2223         } else if (priv->oldlink) {
2224                 new_state = 1;
2225                 priv->oldlink = 0;
2226                 priv->oldspeed = 0;
2227                 priv->oldduplex = -1;
2228         }
2229
2230         if (new_state && netif_msg_link(priv))
2231                 phy_print_status(phydev);
2232
2233         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2234 }
2235
2236 /* Update the hash table based on the current list of multicast
2237  * addresses we subscribe to.  Also, change the promiscuity of
2238  * the device based on the flags (this function is called
2239  * whenever dev->flags is changed */
2240 static void gfar_set_multi(struct net_device *dev)
2241 {
2242         struct dev_mc_list *mc_ptr;
2243         struct gfar_private *priv = netdev_priv(dev);
2244         struct gfar __iomem *regs = priv->regs;
2245         u32 tempval;
2246
2247         if (dev->flags & IFF_PROMISC) {
2248                 /* Set RCTRL to PROM */
2249                 tempval = gfar_read(&regs->rctrl);
2250                 tempval |= RCTRL_PROM;
2251                 gfar_write(&regs->rctrl, tempval);
2252         } else {
2253                 /* Set RCTRL to not PROM */
2254                 tempval = gfar_read(&regs->rctrl);
2255                 tempval &= ~(RCTRL_PROM);
2256                 gfar_write(&regs->rctrl, tempval);
2257         }
2258
2259         if (dev->flags & IFF_ALLMULTI) {
2260                 /* Set the hash to rx all multicast frames */
2261                 gfar_write(&regs->igaddr0, 0xffffffff);
2262                 gfar_write(&regs->igaddr1, 0xffffffff);
2263                 gfar_write(&regs->igaddr2, 0xffffffff);
2264                 gfar_write(&regs->igaddr3, 0xffffffff);
2265                 gfar_write(&regs->igaddr4, 0xffffffff);
2266                 gfar_write(&regs->igaddr5, 0xffffffff);
2267                 gfar_write(&regs->igaddr6, 0xffffffff);
2268                 gfar_write(&regs->igaddr7, 0xffffffff);
2269                 gfar_write(&regs->gaddr0, 0xffffffff);
2270                 gfar_write(&regs->gaddr1, 0xffffffff);
2271                 gfar_write(&regs->gaddr2, 0xffffffff);
2272                 gfar_write(&regs->gaddr3, 0xffffffff);
2273                 gfar_write(&regs->gaddr4, 0xffffffff);
2274                 gfar_write(&regs->gaddr5, 0xffffffff);
2275                 gfar_write(&regs->gaddr6, 0xffffffff);
2276                 gfar_write(&regs->gaddr7, 0xffffffff);
2277         } else {
2278                 int em_num;
2279                 int idx;
2280
2281                 /* zero out the hash */
2282                 gfar_write(&regs->igaddr0, 0x0);
2283                 gfar_write(&regs->igaddr1, 0x0);
2284                 gfar_write(&regs->igaddr2, 0x0);
2285                 gfar_write(&regs->igaddr3, 0x0);
2286                 gfar_write(&regs->igaddr4, 0x0);
2287                 gfar_write(&regs->igaddr5, 0x0);
2288                 gfar_write(&regs->igaddr6, 0x0);
2289                 gfar_write(&regs->igaddr7, 0x0);
2290                 gfar_write(&regs->gaddr0, 0x0);
2291                 gfar_write(&regs->gaddr1, 0x0);
2292                 gfar_write(&regs->gaddr2, 0x0);
2293                 gfar_write(&regs->gaddr3, 0x0);
2294                 gfar_write(&regs->gaddr4, 0x0);
2295                 gfar_write(&regs->gaddr5, 0x0);
2296                 gfar_write(&regs->gaddr6, 0x0);
2297                 gfar_write(&regs->gaddr7, 0x0);
2298
2299                 /* If we have extended hash tables, we need to
2300                  * clear the exact match registers to prepare for
2301                  * setting them */
2302                 if (priv->extended_hash) {
2303                         em_num = GFAR_EM_NUM + 1;
2304                         gfar_clear_exact_match(dev);
2305                         idx = 1;
2306                 } else {
2307                         idx = 0;
2308                         em_num = 0;
2309                 }
2310
2311                 if (dev->mc_count == 0)
2312                         return;
2313
2314                 /* Parse the list, and set the appropriate bits */
2315                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2316                         if (idx < em_num) {
2317                                 gfar_set_mac_for_addr(dev, idx,
2318                                                 mc_ptr->dmi_addr);
2319                                 idx++;
2320                         } else
2321                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2322                 }
2323         }
2324
2325         return;
2326 }
2327
2328
2329 /* Clears each of the exact match registers to zero, so they
2330  * don't interfere with normal reception */
2331 static void gfar_clear_exact_match(struct net_device *dev)
2332 {
2333         int idx;
2334         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2335
2336         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2337                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2338 }
2339
2340 /* Set the appropriate hash bit for the given addr */
2341 /* The algorithm works like so:
2342  * 1) Take the Destination Address (ie the multicast address), and
2343  * do a CRC on it (little endian), and reverse the bits of the
2344  * result.
2345  * 2) Use the 8 most significant bits as a hash into a 256-entry
2346  * table.  The table is controlled through 8 32-bit registers:
2347  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2348  * gaddr7.  This means that the 3 most significant bits in the
2349  * hash index which gaddr register to use, and the 5 other bits
2350  * indicate which bit (assuming an IBM numbering scheme, which
2351  * for PowerPC (tm) is usually the case) in the register holds
2352  * the entry. */
2353 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2354 {
2355         u32 tempval;
2356         struct gfar_private *priv = netdev_priv(dev);
2357         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2358         int width = priv->hash_width;
2359         u8 whichbit = (result >> (32 - width)) & 0x1f;
2360         u8 whichreg = result >> (32 - width + 5);
2361         u32 value = (1 << (31-whichbit));
2362
2363         tempval = gfar_read(priv->hash_regs[whichreg]);
2364         tempval |= value;
2365         gfar_write(priv->hash_regs[whichreg], tempval);
2366
2367         return;
2368 }
2369
2370
2371 /* There are multiple MAC Address register pairs on some controllers
2372  * This function sets the numth pair to a given address
2373  */
2374 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2375 {
2376         struct gfar_private *priv = netdev_priv(dev);
2377         int idx;
2378         char tmpbuf[MAC_ADDR_LEN];
2379         u32 tempval;
2380         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2381
2382         macptr += num*2;
2383
2384         /* Now copy it into the mac registers backwards, cuz */
2385         /* little endian is silly */
2386         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2387                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2388
2389         gfar_write(macptr, *((u32 *) (tmpbuf)));
2390
2391         tempval = *((u32 *) (tmpbuf + 4));
2392
2393         gfar_write(macptr+1, tempval);
2394 }
2395
2396 /* GFAR error interrupt handler */
2397 static irqreturn_t gfar_error(int irq, void *dev_id)
2398 {
2399         struct net_device *dev = dev_id;
2400         struct gfar_private *priv = netdev_priv(dev);
2401
2402         /* Save ievent for future reference */
2403         u32 events = gfar_read(&priv->regs->ievent);
2404
2405         /* Clear IEVENT */
2406         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2407
2408         /* Magic Packet is not an error. */
2409         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2410             (events & IEVENT_MAG))
2411                 events &= ~IEVENT_MAG;
2412
2413         /* Hmm... */
2414         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2415                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2416                        dev->name, events, gfar_read(&priv->regs->imask));
2417
2418         /* Update the error counters */
2419         if (events & IEVENT_TXE) {
2420                 dev->stats.tx_errors++;
2421
2422                 if (events & IEVENT_LC)
2423                         dev->stats.tx_window_errors++;
2424                 if (events & IEVENT_CRL)
2425                         dev->stats.tx_aborted_errors++;
2426                 if (events & IEVENT_XFUN) {
2427                         if (netif_msg_tx_err(priv))
2428                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2429                                        "packet dropped.\n", dev->name);
2430                         dev->stats.tx_dropped++;
2431                         priv->extra_stats.tx_underrun++;
2432
2433                         /* Reactivate the Tx Queues */
2434                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2435                 }
2436                 if (netif_msg_tx_err(priv))
2437                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2438         }
2439         if (events & IEVENT_BSY) {
2440                 dev->stats.rx_errors++;
2441                 priv->extra_stats.rx_bsy++;
2442
2443                 gfar_receive(irq, dev_id);
2444
2445                 if (netif_msg_rx_err(priv))
2446                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2447                                dev->name, gfar_read(&priv->regs->rstat));
2448         }
2449         if (events & IEVENT_BABR) {
2450                 dev->stats.rx_errors++;
2451                 priv->extra_stats.rx_babr++;
2452
2453                 if (netif_msg_rx_err(priv))
2454                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2455         }
2456         if (events & IEVENT_EBERR) {
2457                 priv->extra_stats.eberr++;
2458                 if (netif_msg_rx_err(priv))
2459                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2460         }
2461         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2462                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2463
2464         if (events & IEVENT_BABT) {
2465                 priv->extra_stats.tx_babt++;
2466                 if (netif_msg_tx_err(priv))
2467                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2468         }
2469         return IRQ_HANDLED;
2470 }
2471
2472 static struct of_device_id gfar_match[] =
2473 {
2474         {
2475                 .type = "network",
2476                 .compatible = "gianfar",
2477         },
2478         {},
2479 };
2480 MODULE_DEVICE_TABLE(of, gfar_match);
2481
2482 /* Structure for a device driver */
2483 static struct of_platform_driver gfar_driver = {
2484         .name = "fsl-gianfar",
2485         .match_table = gfar_match,
2486
2487         .probe = gfar_probe,
2488         .remove = gfar_remove,
2489         .suspend = gfar_legacy_suspend,
2490         .resume = gfar_legacy_resume,
2491         .driver.pm = GFAR_PM_OPS,
2492 };
2493
2494 static int __init gfar_init(void)
2495 {
2496         return of_register_platform_driver(&gfar_driver);
2497 }
2498
2499 static void __exit gfar_exit(void)
2500 {
2501         of_unregister_platform_driver(&gfar_driver);
2502 }
2503
2504 module_init(gfar_init);
2505 module_exit(gfar_exit);
2506