gianfar: Fix stashing support
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "fsl_pq_mdio.h"
97
98 #define TX_TIMEOUT      (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112                 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122                 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
135                               int amount_pull);
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137                                 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143
144 MODULE_AUTHOR("Freescale Semiconductor, Inc");
145 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
146 MODULE_LICENSE("GPL");
147
148 /* Returns 1 if incoming frames use an FCB */
149 static inline int gfar_uses_fcb(struct gfar_private *priv)
150 {
151         return priv->vlgrp || priv->rx_csum_enable;
152 }
153
154 static int gfar_of_init(struct net_device *dev)
155 {
156         struct device_node *phy, *mdio;
157         const unsigned int *id;
158         const char *model;
159         const char *ctype;
160         const void *mac_addr;
161         const phandle *ph;
162         u64 addr, size;
163         int err = 0;
164         struct gfar_private *priv = netdev_priv(dev);
165         struct device_node *np = priv->node;
166         char bus_name[MII_BUS_ID_SIZE];
167         const u32 *stash;
168         const u32 *stash_len;
169         const u32 *stash_idx;
170
171         if (!np || !of_device_is_available(np))
172                 return -ENODEV;
173
174         /* get a pointer to the register memory */
175         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
176         priv->regs = ioremap(addr, size);
177
178         if (priv->regs == NULL)
179                 return -ENOMEM;
180
181         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
182
183         model = of_get_property(np, "model", NULL);
184
185         /* If we aren't the FEC we have multiple interrupts */
186         if (model && strcasecmp(model, "FEC")) {
187                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
188
189                 priv->interruptError = irq_of_parse_and_map(np, 2);
190
191                 if (priv->interruptTransmit < 0 ||
192                                 priv->interruptReceive < 0 ||
193                                 priv->interruptError < 0) {
194                         err = -EINVAL;
195                         goto err_out;
196                 }
197         }
198
199         stash = of_get_property(np, "bd-stash", NULL);
200
201         if(stash) {
202                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
203                 priv->bd_stash_en = 1;
204         }
205
206         stash_len = of_get_property(np, "rx-stash-len", NULL);
207
208         if (stash_len)
209                 priv->rx_stash_size = *stash_len;
210
211         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
212
213         if (stash_idx)
214                 priv->rx_stash_index = *stash_idx;
215
216         if (stash_len || stash_idx)
217                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
218
219         mac_addr = of_get_mac_address(np);
220         if (mac_addr)
221                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
222
223         if (model && !strcasecmp(model, "TSEC"))
224                 priv->device_flags =
225                         FSL_GIANFAR_DEV_HAS_GIGABIT |
226                         FSL_GIANFAR_DEV_HAS_COALESCE |
227                         FSL_GIANFAR_DEV_HAS_RMON |
228                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
229         if (model && !strcasecmp(model, "eTSEC"))
230                 priv->device_flags =
231                         FSL_GIANFAR_DEV_HAS_GIGABIT |
232                         FSL_GIANFAR_DEV_HAS_COALESCE |
233                         FSL_GIANFAR_DEV_HAS_RMON |
234                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
235                         FSL_GIANFAR_DEV_HAS_PADDING |
236                         FSL_GIANFAR_DEV_HAS_CSUM |
237                         FSL_GIANFAR_DEV_HAS_VLAN |
238                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
239                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
240
241         ctype = of_get_property(np, "phy-connection-type", NULL);
242
243         /* We only care about rgmii-id.  The rest are autodetected */
244         if (ctype && !strcmp(ctype, "rgmii-id"))
245                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
246         else
247                 priv->interface = PHY_INTERFACE_MODE_MII;
248
249         if (of_get_property(np, "fsl,magic-packet", NULL))
250                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
251
252         ph = of_get_property(np, "phy-handle", NULL);
253         if (ph == NULL) {
254                 u32 *fixed_link;
255
256                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
257                 if (!fixed_link) {
258                         err = -ENODEV;
259                         goto err_out;
260                 }
261
262                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
263                                 PHY_ID_FMT, "0", fixed_link[0]);
264         } else {
265                 phy = of_find_node_by_phandle(*ph);
266
267                 if (phy == NULL) {
268                         err = -ENODEV;
269                         goto err_out;
270                 }
271
272                 mdio = of_get_parent(phy);
273
274                 id = of_get_property(phy, "reg", NULL);
275
276                 of_node_put(phy);
277                 of_node_put(mdio);
278
279                 fsl_pq_mdio_bus_name(bus_name, mdio);
280                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
281                                 bus_name, *id);
282         }
283
284         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
285         ph = of_get_property(np, "tbi-handle", NULL);
286         if (ph) {
287                 struct device_node *tbi = of_find_node_by_phandle(*ph);
288                 struct of_device *ofdev;
289                 struct mii_bus *bus;
290
291                 if (!tbi)
292                         return 0;
293
294                 mdio = of_get_parent(tbi);
295                 if (!mdio)
296                         return 0;
297
298                 ofdev = of_find_device_by_node(mdio);
299
300                 of_node_put(mdio);
301
302                 id = of_get_property(tbi, "reg", NULL);
303                 if (!id)
304                         return 0;
305
306                 of_node_put(tbi);
307
308                 bus = dev_get_drvdata(&ofdev->dev);
309
310                 priv->tbiphy = bus->phy_map[*id];
311         }
312
313         return 0;
314
315 err_out:
316         iounmap(priv->regs);
317         return err;
318 }
319
320 /* Ioctl MII Interface */
321 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
322 {
323         struct gfar_private *priv = netdev_priv(dev);
324
325         if (!netif_running(dev))
326                 return -EINVAL;
327
328         if (!priv->phydev)
329                 return -ENODEV;
330
331         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
332 }
333
334 /* Set up the ethernet device structure, private data,
335  * and anything else we need before we start */
336 static int gfar_probe(struct of_device *ofdev,
337                 const struct of_device_id *match)
338 {
339         u32 tempval;
340         struct net_device *dev = NULL;
341         struct gfar_private *priv = NULL;
342         DECLARE_MAC_BUF(mac);
343         int err = 0;
344         int len_devname;
345
346         /* Create an ethernet device instance */
347         dev = alloc_etherdev(sizeof (*priv));
348
349         if (NULL == dev)
350                 return -ENOMEM;
351
352         priv = netdev_priv(dev);
353         priv->dev = dev;
354         priv->node = ofdev->node;
355
356         err = gfar_of_init(dev);
357
358         if (err)
359                 goto regs_fail;
360
361         spin_lock_init(&priv->txlock);
362         spin_lock_init(&priv->rxlock);
363         spin_lock_init(&priv->bflock);
364         INIT_WORK(&priv->reset_task, gfar_reset_task);
365
366         dev_set_drvdata(&ofdev->dev, priv);
367
368         /* Stop the DMA engine now, in case it was running before */
369         /* (The firmware could have used it, and left it running). */
370         gfar_halt(dev);
371
372         /* Reset MAC layer */
373         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
374
375         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
376         gfar_write(&priv->regs->maccfg1, tempval);
377
378         /* Initialize MACCFG2. */
379         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
380
381         /* Initialize ECNTRL */
382         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
383
384         /* Set the dev->base_addr to the gfar reg region */
385         dev->base_addr = (unsigned long) (priv->regs);
386
387         SET_NETDEV_DEV(dev, &ofdev->dev);
388
389         /* Fill in the dev structure */
390         dev->open = gfar_enet_open;
391         dev->hard_start_xmit = gfar_start_xmit;
392         dev->tx_timeout = gfar_timeout;
393         dev->watchdog_timeo = TX_TIMEOUT;
394         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
395 #ifdef CONFIG_NET_POLL_CONTROLLER
396         dev->poll_controller = gfar_netpoll;
397 #endif
398         dev->stop = gfar_close;
399         dev->change_mtu = gfar_change_mtu;
400         dev->mtu = 1500;
401         dev->set_multicast_list = gfar_set_multi;
402
403         dev->ethtool_ops = &gfar_ethtool_ops;
404         dev->do_ioctl = gfar_ioctl;
405
406         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
407                 priv->rx_csum_enable = 1;
408                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
409         } else
410                 priv->rx_csum_enable = 0;
411
412         priv->vlgrp = NULL;
413
414         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
415                 dev->vlan_rx_register = gfar_vlan_rx_register;
416
417                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
418         }
419
420         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
421                 priv->extended_hash = 1;
422                 priv->hash_width = 9;
423
424                 priv->hash_regs[0] = &priv->regs->igaddr0;
425                 priv->hash_regs[1] = &priv->regs->igaddr1;
426                 priv->hash_regs[2] = &priv->regs->igaddr2;
427                 priv->hash_regs[3] = &priv->regs->igaddr3;
428                 priv->hash_regs[4] = &priv->regs->igaddr4;
429                 priv->hash_regs[5] = &priv->regs->igaddr5;
430                 priv->hash_regs[6] = &priv->regs->igaddr6;
431                 priv->hash_regs[7] = &priv->regs->igaddr7;
432                 priv->hash_regs[8] = &priv->regs->gaddr0;
433                 priv->hash_regs[9] = &priv->regs->gaddr1;
434                 priv->hash_regs[10] = &priv->regs->gaddr2;
435                 priv->hash_regs[11] = &priv->regs->gaddr3;
436                 priv->hash_regs[12] = &priv->regs->gaddr4;
437                 priv->hash_regs[13] = &priv->regs->gaddr5;
438                 priv->hash_regs[14] = &priv->regs->gaddr6;
439                 priv->hash_regs[15] = &priv->regs->gaddr7;
440
441         } else {
442                 priv->extended_hash = 0;
443                 priv->hash_width = 8;
444
445                 priv->hash_regs[0] = &priv->regs->gaddr0;
446                 priv->hash_regs[1] = &priv->regs->gaddr1;
447                 priv->hash_regs[2] = &priv->regs->gaddr2;
448                 priv->hash_regs[3] = &priv->regs->gaddr3;
449                 priv->hash_regs[4] = &priv->regs->gaddr4;
450                 priv->hash_regs[5] = &priv->regs->gaddr5;
451                 priv->hash_regs[6] = &priv->regs->gaddr6;
452                 priv->hash_regs[7] = &priv->regs->gaddr7;
453         }
454
455         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
456                 priv->padding = DEFAULT_PADDING;
457         else
458                 priv->padding = 0;
459
460         if (dev->features & NETIF_F_IP_CSUM)
461                 dev->hard_header_len += GMAC_FCB_LEN;
462
463         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
464         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
465         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
466         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
467
468         priv->txcoalescing = DEFAULT_TX_COALESCE;
469         priv->txic = DEFAULT_TXIC;
470         priv->rxcoalescing = DEFAULT_RX_COALESCE;
471         priv->rxic = DEFAULT_RXIC;
472
473         /* Enable most messages by default */
474         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
475
476         /* Carrier starts down, phylib will bring it up */
477         netif_carrier_off(dev);
478
479         err = register_netdev(dev);
480
481         if (err) {
482                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
483                                 dev->name);
484                 goto register_fail;
485         }
486
487         device_init_wakeup(&dev->dev,
488                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
489
490         /* fill out IRQ number and name fields */
491         len_devname = strlen(dev->name);
492         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
493         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
494                 strncpy(&priv->int_name_tx[len_devname],
495                         "_tx", sizeof("_tx") + 1);
496
497                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
498                 strncpy(&priv->int_name_rx[len_devname],
499                         "_rx", sizeof("_rx") + 1);
500
501                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
502                 strncpy(&priv->int_name_er[len_devname],
503                         "_er", sizeof("_er") + 1);
504         } else
505                 priv->int_name_tx[len_devname] = '\0';
506
507         /* Create all the sysfs files */
508         gfar_init_sysfs(dev);
509
510         /* Print out the device info */
511         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
512
513         /* Even more device info helps when determining which kernel */
514         /* provided which set of benchmarks. */
515         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
516         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
517                dev->name, priv->rx_ring_size, priv->tx_ring_size);
518
519         return 0;
520
521 register_fail:
522         iounmap(priv->regs);
523 regs_fail:
524         free_netdev(dev);
525         return err;
526 }
527
528 static int gfar_remove(struct of_device *ofdev)
529 {
530         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
531
532         dev_set_drvdata(&ofdev->dev, NULL);
533
534         iounmap(priv->regs);
535         free_netdev(priv->dev);
536
537         return 0;
538 }
539
540 #ifdef CONFIG_PM
541 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
542 {
543         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
544         struct net_device *dev = priv->dev;
545         unsigned long flags;
546         u32 tempval;
547
548         int magic_packet = priv->wol_en &&
549                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
550
551         netif_device_detach(dev);
552
553         if (netif_running(dev)) {
554                 spin_lock_irqsave(&priv->txlock, flags);
555                 spin_lock(&priv->rxlock);
556
557                 gfar_halt_nodisable(dev);
558
559                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
560                 tempval = gfar_read(&priv->regs->maccfg1);
561
562                 tempval &= ~MACCFG1_TX_EN;
563
564                 if (!magic_packet)
565                         tempval &= ~MACCFG1_RX_EN;
566
567                 gfar_write(&priv->regs->maccfg1, tempval);
568
569                 spin_unlock(&priv->rxlock);
570                 spin_unlock_irqrestore(&priv->txlock, flags);
571
572                 napi_disable(&priv->napi);
573
574                 if (magic_packet) {
575                         /* Enable interrupt on Magic Packet */
576                         gfar_write(&priv->regs->imask, IMASK_MAG);
577
578                         /* Enable Magic Packet mode */
579                         tempval = gfar_read(&priv->regs->maccfg2);
580                         tempval |= MACCFG2_MPEN;
581                         gfar_write(&priv->regs->maccfg2, tempval);
582                 } else {
583                         phy_stop(priv->phydev);
584                 }
585         }
586
587         return 0;
588 }
589
590 static int gfar_resume(struct of_device *ofdev)
591 {
592         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
593         struct net_device *dev = priv->dev;
594         unsigned long flags;
595         u32 tempval;
596         int magic_packet = priv->wol_en &&
597                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
598
599         if (!netif_running(dev)) {
600                 netif_device_attach(dev);
601                 return 0;
602         }
603
604         if (!magic_packet && priv->phydev)
605                 phy_start(priv->phydev);
606
607         /* Disable Magic Packet mode, in case something
608          * else woke us up.
609          */
610
611         spin_lock_irqsave(&priv->txlock, flags);
612         spin_lock(&priv->rxlock);
613
614         tempval = gfar_read(&priv->regs->maccfg2);
615         tempval &= ~MACCFG2_MPEN;
616         gfar_write(&priv->regs->maccfg2, tempval);
617
618         gfar_start(dev);
619
620         spin_unlock(&priv->rxlock);
621         spin_unlock_irqrestore(&priv->txlock, flags);
622
623         netif_device_attach(dev);
624
625         napi_enable(&priv->napi);
626
627         return 0;
628 }
629 #else
630 #define gfar_suspend NULL
631 #define gfar_resume NULL
632 #endif
633
634 /* Reads the controller's registers to determine what interface
635  * connects it to the PHY.
636  */
637 static phy_interface_t gfar_get_interface(struct net_device *dev)
638 {
639         struct gfar_private *priv = netdev_priv(dev);
640         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
641
642         if (ecntrl & ECNTRL_SGMII_MODE)
643                 return PHY_INTERFACE_MODE_SGMII;
644
645         if (ecntrl & ECNTRL_TBI_MODE) {
646                 if (ecntrl & ECNTRL_REDUCED_MODE)
647                         return PHY_INTERFACE_MODE_RTBI;
648                 else
649                         return PHY_INTERFACE_MODE_TBI;
650         }
651
652         if (ecntrl & ECNTRL_REDUCED_MODE) {
653                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
654                         return PHY_INTERFACE_MODE_RMII;
655                 else {
656                         phy_interface_t interface = priv->interface;
657
658                         /*
659                          * This isn't autodetected right now, so it must
660                          * be set by the device tree or platform code.
661                          */
662                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
663                                 return PHY_INTERFACE_MODE_RGMII_ID;
664
665                         return PHY_INTERFACE_MODE_RGMII;
666                 }
667         }
668
669         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
670                 return PHY_INTERFACE_MODE_GMII;
671
672         return PHY_INTERFACE_MODE_MII;
673 }
674
675
676 /* Initializes driver's PHY state, and attaches to the PHY.
677  * Returns 0 on success.
678  */
679 static int init_phy(struct net_device *dev)
680 {
681         struct gfar_private *priv = netdev_priv(dev);
682         uint gigabit_support =
683                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
684                 SUPPORTED_1000baseT_Full : 0;
685         struct phy_device *phydev;
686         phy_interface_t interface;
687
688         priv->oldlink = 0;
689         priv->oldspeed = 0;
690         priv->oldduplex = -1;
691
692         interface = gfar_get_interface(dev);
693
694         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
695
696         if (interface == PHY_INTERFACE_MODE_SGMII)
697                 gfar_configure_serdes(dev);
698
699         if (IS_ERR(phydev)) {
700                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
701                 return PTR_ERR(phydev);
702         }
703
704         /* Remove any features not supported by the controller */
705         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
706         phydev->advertising = phydev->supported;
707
708         priv->phydev = phydev;
709
710         return 0;
711 }
712
713 /*
714  * Initialize TBI PHY interface for communicating with the
715  * SERDES lynx PHY on the chip.  We communicate with this PHY
716  * through the MDIO bus on each controller, treating it as a
717  * "normal" PHY at the address found in the TBIPA register.  We assume
718  * that the TBIPA register is valid.  Either the MDIO bus code will set
719  * it to a value that doesn't conflict with other PHYs on the bus, or the
720  * value doesn't matter, as there are no other PHYs on the bus.
721  */
722 static void gfar_configure_serdes(struct net_device *dev)
723 {
724         struct gfar_private *priv = netdev_priv(dev);
725
726         if (!priv->tbiphy) {
727                 printk(KERN_WARNING "SGMII mode requires that the device "
728                                 "tree specify a tbi-handle\n");
729                 return;
730         }
731
732         /*
733          * If the link is already up, we must already be ok, and don't need to
734          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
735          * everything for us?  Resetting it takes the link down and requires
736          * several seconds for it to come back.
737          */
738         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
739                 return;
740
741         /* Single clk mode, mii mode off(for serdes communication) */
742         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
743
744         phy_write(priv->tbiphy, MII_ADVERTISE,
745                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
746                         ADVERTISE_1000XPSE_ASYM);
747
748         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
749                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
750 }
751
752 static void init_registers(struct net_device *dev)
753 {
754         struct gfar_private *priv = netdev_priv(dev);
755
756         /* Clear IEVENT */
757         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
758
759         /* Initialize IMASK */
760         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
761
762         /* Init hash registers to zero */
763         gfar_write(&priv->regs->igaddr0, 0);
764         gfar_write(&priv->regs->igaddr1, 0);
765         gfar_write(&priv->regs->igaddr2, 0);
766         gfar_write(&priv->regs->igaddr3, 0);
767         gfar_write(&priv->regs->igaddr4, 0);
768         gfar_write(&priv->regs->igaddr5, 0);
769         gfar_write(&priv->regs->igaddr6, 0);
770         gfar_write(&priv->regs->igaddr7, 0);
771
772         gfar_write(&priv->regs->gaddr0, 0);
773         gfar_write(&priv->regs->gaddr1, 0);
774         gfar_write(&priv->regs->gaddr2, 0);
775         gfar_write(&priv->regs->gaddr3, 0);
776         gfar_write(&priv->regs->gaddr4, 0);
777         gfar_write(&priv->regs->gaddr5, 0);
778         gfar_write(&priv->regs->gaddr6, 0);
779         gfar_write(&priv->regs->gaddr7, 0);
780
781         /* Zero out the rmon mib registers if it has them */
782         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
783                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
784
785                 /* Mask off the CAM interrupts */
786                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
787                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
788         }
789
790         /* Initialize the max receive buffer length */
791         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
792
793         /* Initialize the Minimum Frame Length Register */
794         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
795 }
796
797
798 /* Halt the receive and transmit queues */
799 static void gfar_halt_nodisable(struct net_device *dev)
800 {
801         struct gfar_private *priv = netdev_priv(dev);
802         struct gfar __iomem *regs = priv->regs;
803         u32 tempval;
804
805         /* Mask all interrupts */
806         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
807
808         /* Clear all interrupts */
809         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
810
811         /* Stop the DMA, and wait for it to stop */
812         tempval = gfar_read(&priv->regs->dmactrl);
813         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
814             != (DMACTRL_GRS | DMACTRL_GTS)) {
815                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
816                 gfar_write(&priv->regs->dmactrl, tempval);
817
818                 while (!(gfar_read(&priv->regs->ievent) &
819                          (IEVENT_GRSC | IEVENT_GTSC)))
820                         cpu_relax();
821         }
822 }
823
824 /* Halt the receive and transmit queues */
825 void gfar_halt(struct net_device *dev)
826 {
827         struct gfar_private *priv = netdev_priv(dev);
828         struct gfar __iomem *regs = priv->regs;
829         u32 tempval;
830
831         gfar_halt_nodisable(dev);
832
833         /* Disable Rx and Tx */
834         tempval = gfar_read(&regs->maccfg1);
835         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
836         gfar_write(&regs->maccfg1, tempval);
837 }
838
839 void stop_gfar(struct net_device *dev)
840 {
841         struct gfar_private *priv = netdev_priv(dev);
842         struct gfar __iomem *regs = priv->regs;
843         unsigned long flags;
844
845         phy_stop(priv->phydev);
846
847         /* Lock it down */
848         spin_lock_irqsave(&priv->txlock, flags);
849         spin_lock(&priv->rxlock);
850
851         gfar_halt(dev);
852
853         spin_unlock(&priv->rxlock);
854         spin_unlock_irqrestore(&priv->txlock, flags);
855
856         /* Free the IRQs */
857         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
858                 free_irq(priv->interruptError, dev);
859                 free_irq(priv->interruptTransmit, dev);
860                 free_irq(priv->interruptReceive, dev);
861         } else {
862                 free_irq(priv->interruptTransmit, dev);
863         }
864
865         free_skb_resources(priv);
866
867         dma_free_coherent(&dev->dev,
868                         sizeof(struct txbd8)*priv->tx_ring_size
869                         + sizeof(struct rxbd8)*priv->rx_ring_size,
870                         priv->tx_bd_base,
871                         gfar_read(&regs->tbase0));
872 }
873
874 /* If there are any tx skbs or rx skbs still around, free them.
875  * Then free tx_skbuff and rx_skbuff */
876 static void free_skb_resources(struct gfar_private *priv)
877 {
878         struct rxbd8 *rxbdp;
879         struct txbd8 *txbdp;
880         int i, j;
881
882         /* Go through all the buffer descriptors and free their data buffers */
883         txbdp = priv->tx_bd_base;
884
885         for (i = 0; i < priv->tx_ring_size; i++) {
886                 if (!priv->tx_skbuff[i])
887                         continue;
888
889                 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
890                                 txbdp->length, DMA_TO_DEVICE);
891                 txbdp->lstatus = 0;
892                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
893                         txbdp++;
894                         dma_unmap_page(&priv->dev->dev, txbdp->bufPtr,
895                                         txbdp->length, DMA_TO_DEVICE);
896                 }
897                 txbdp++;
898                 dev_kfree_skb_any(priv->tx_skbuff[i]);
899                 priv->tx_skbuff[i] = NULL;
900         }
901
902         kfree(priv->tx_skbuff);
903
904         rxbdp = priv->rx_bd_base;
905
906         /* rx_skbuff is not guaranteed to be allocated, so only
907          * free it and its contents if it is allocated */
908         if(priv->rx_skbuff != NULL) {
909                 for (i = 0; i < priv->rx_ring_size; i++) {
910                         if (priv->rx_skbuff[i]) {
911                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
912                                                 priv->rx_buffer_size,
913                                                 DMA_FROM_DEVICE);
914
915                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
916                                 priv->rx_skbuff[i] = NULL;
917                         }
918
919                         rxbdp->lstatus = 0;
920                         rxbdp->bufPtr = 0;
921
922                         rxbdp++;
923                 }
924
925                 kfree(priv->rx_skbuff);
926         }
927 }
928
929 void gfar_start(struct net_device *dev)
930 {
931         struct gfar_private *priv = netdev_priv(dev);
932         struct gfar __iomem *regs = priv->regs;
933         u32 tempval;
934
935         /* Enable Rx and Tx in MACCFG1 */
936         tempval = gfar_read(&regs->maccfg1);
937         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
938         gfar_write(&regs->maccfg1, tempval);
939
940         /* Initialize DMACTRL to have WWR and WOP */
941         tempval = gfar_read(&priv->regs->dmactrl);
942         tempval |= DMACTRL_INIT_SETTINGS;
943         gfar_write(&priv->regs->dmactrl, tempval);
944
945         /* Make sure we aren't stopped */
946         tempval = gfar_read(&priv->regs->dmactrl);
947         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
948         gfar_write(&priv->regs->dmactrl, tempval);
949
950         /* Clear THLT/RHLT, so that the DMA starts polling now */
951         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
952         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
953
954         /* Unmask the interrupts we look for */
955         gfar_write(&regs->imask, IMASK_DEFAULT);
956
957         dev->trans_start = jiffies;
958 }
959
960 /* Bring the controller up and running */
961 int startup_gfar(struct net_device *dev)
962 {
963         struct txbd8 *txbdp;
964         struct rxbd8 *rxbdp;
965         dma_addr_t addr = 0;
966         unsigned long vaddr;
967         int i;
968         struct gfar_private *priv = netdev_priv(dev);
969         struct gfar __iomem *regs = priv->regs;
970         int err = 0;
971         u32 rctrl = 0;
972         u32 attrs = 0;
973
974         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
975
976         /* Allocate memory for the buffer descriptors */
977         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
978                         sizeof (struct txbd8) * priv->tx_ring_size +
979                         sizeof (struct rxbd8) * priv->rx_ring_size,
980                         &addr, GFP_KERNEL);
981
982         if (vaddr == 0) {
983                 if (netif_msg_ifup(priv))
984                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
985                                         dev->name);
986                 return -ENOMEM;
987         }
988
989         priv->tx_bd_base = (struct txbd8 *) vaddr;
990
991         /* enet DMA only understands physical addresses */
992         gfar_write(&regs->tbase0, addr);
993
994         /* Start the rx descriptor ring where the tx ring leaves off */
995         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
996         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
997         priv->rx_bd_base = (struct rxbd8 *) vaddr;
998         gfar_write(&regs->rbase0, addr);
999
1000         /* Setup the skbuff rings */
1001         priv->tx_skbuff =
1002             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1003                                         priv->tx_ring_size, GFP_KERNEL);
1004
1005         if (NULL == priv->tx_skbuff) {
1006                 if (netif_msg_ifup(priv))
1007                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
1008                                         dev->name);
1009                 err = -ENOMEM;
1010                 goto tx_skb_fail;
1011         }
1012
1013         for (i = 0; i < priv->tx_ring_size; i++)
1014                 priv->tx_skbuff[i] = NULL;
1015
1016         priv->rx_skbuff =
1017             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1018                                         priv->rx_ring_size, GFP_KERNEL);
1019
1020         if (NULL == priv->rx_skbuff) {
1021                 if (netif_msg_ifup(priv))
1022                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1023                                         dev->name);
1024                 err = -ENOMEM;
1025                 goto rx_skb_fail;
1026         }
1027
1028         for (i = 0; i < priv->rx_ring_size; i++)
1029                 priv->rx_skbuff[i] = NULL;
1030
1031         /* Initialize some variables in our dev structure */
1032         priv->num_txbdfree = priv->tx_ring_size;
1033         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1034         priv->cur_rx = priv->rx_bd_base;
1035         priv->skb_curtx = priv->skb_dirtytx = 0;
1036         priv->skb_currx = 0;
1037
1038         /* Initialize Transmit Descriptor Ring */
1039         txbdp = priv->tx_bd_base;
1040         for (i = 0; i < priv->tx_ring_size; i++) {
1041                 txbdp->lstatus = 0;
1042                 txbdp->bufPtr = 0;
1043                 txbdp++;
1044         }
1045
1046         /* Set the last descriptor in the ring to indicate wrap */
1047         txbdp--;
1048         txbdp->status |= TXBD_WRAP;
1049
1050         rxbdp = priv->rx_bd_base;
1051         for (i = 0; i < priv->rx_ring_size; i++) {
1052                 struct sk_buff *skb;
1053
1054                 skb = gfar_new_skb(dev);
1055
1056                 if (!skb) {
1057                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1058                                         dev->name);
1059
1060                         goto err_rxalloc_fail;
1061                 }
1062
1063                 priv->rx_skbuff[i] = skb;
1064
1065                 gfar_new_rxbdp(dev, rxbdp, skb);
1066
1067                 rxbdp++;
1068         }
1069
1070         /* Set the last descriptor in the ring to wrap */
1071         rxbdp--;
1072         rxbdp->status |= RXBD_WRAP;
1073
1074         /* If the device has multiple interrupts, register for
1075          * them.  Otherwise, only register for the one */
1076         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1077                 /* Install our interrupt handlers for Error,
1078                  * Transmit, and Receive */
1079                 if (request_irq(priv->interruptError, gfar_error,
1080                                 0, priv->int_name_er, dev) < 0) {
1081                         if (netif_msg_intr(priv))
1082                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1083                                         dev->name, priv->interruptError);
1084
1085                         err = -1;
1086                         goto err_irq_fail;
1087                 }
1088
1089                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1090                                 0, priv->int_name_tx, dev) < 0) {
1091                         if (netif_msg_intr(priv))
1092                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1093                                         dev->name, priv->interruptTransmit);
1094
1095                         err = -1;
1096
1097                         goto tx_irq_fail;
1098                 }
1099
1100                 if (request_irq(priv->interruptReceive, gfar_receive,
1101                                 0, priv->int_name_rx, dev) < 0) {
1102                         if (netif_msg_intr(priv))
1103                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1104                                                 dev->name, priv->interruptReceive);
1105
1106                         err = -1;
1107                         goto rx_irq_fail;
1108                 }
1109         } else {
1110                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1111                                 0, priv->int_name_tx, dev) < 0) {
1112                         if (netif_msg_intr(priv))
1113                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1114                                         dev->name, priv->interruptTransmit);
1115
1116                         err = -1;
1117                         goto err_irq_fail;
1118                 }
1119         }
1120
1121         phy_start(priv->phydev);
1122
1123         /* Configure the coalescing support */
1124         gfar_write(&regs->txic, 0);
1125         if (priv->txcoalescing)
1126                 gfar_write(&regs->txic, priv->txic);
1127
1128         gfar_write(&regs->rxic, 0);
1129         if (priv->rxcoalescing)
1130                 gfar_write(&regs->rxic, priv->rxic);
1131
1132         if (priv->rx_csum_enable)
1133                 rctrl |= RCTRL_CHECKSUMMING;
1134
1135         if (priv->extended_hash) {
1136                 rctrl |= RCTRL_EXTHASH;
1137
1138                 gfar_clear_exact_match(dev);
1139                 rctrl |= RCTRL_EMEN;
1140         }
1141
1142         if (priv->padding) {
1143                 rctrl &= ~RCTRL_PAL_MASK;
1144                 rctrl |= RCTRL_PADDING(priv->padding);
1145         }
1146
1147         /* Init rctrl based on our settings */
1148         gfar_write(&priv->regs->rctrl, rctrl);
1149
1150         if (dev->features & NETIF_F_IP_CSUM)
1151                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1152
1153         /* Set the extraction length and index */
1154         attrs = ATTRELI_EL(priv->rx_stash_size) |
1155                 ATTRELI_EI(priv->rx_stash_index);
1156
1157         gfar_write(&priv->regs->attreli, attrs);
1158
1159         /* Start with defaults, and add stashing or locking
1160          * depending on the approprate variables */
1161         attrs = ATTR_INIT_SETTINGS;
1162
1163         if (priv->bd_stash_en)
1164                 attrs |= ATTR_BDSTASH;
1165
1166         if (priv->rx_stash_size != 0)
1167                 attrs |= ATTR_BUFSTASH;
1168
1169         gfar_write(&priv->regs->attr, attrs);
1170
1171         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1172         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1173         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1174
1175         /* Start the controller */
1176         gfar_start(dev);
1177
1178         return 0;
1179
1180 rx_irq_fail:
1181         free_irq(priv->interruptTransmit, dev);
1182 tx_irq_fail:
1183         free_irq(priv->interruptError, dev);
1184 err_irq_fail:
1185 err_rxalloc_fail:
1186 rx_skb_fail:
1187         free_skb_resources(priv);
1188 tx_skb_fail:
1189         dma_free_coherent(&dev->dev,
1190                         sizeof(struct txbd8)*priv->tx_ring_size
1191                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1192                         priv->tx_bd_base,
1193                         gfar_read(&regs->tbase0));
1194
1195         return err;
1196 }
1197
1198 /* Called when something needs to use the ethernet device */
1199 /* Returns 0 for success. */
1200 static int gfar_enet_open(struct net_device *dev)
1201 {
1202         struct gfar_private *priv = netdev_priv(dev);
1203         int err;
1204
1205         napi_enable(&priv->napi);
1206
1207         skb_queue_head_init(&priv->rx_recycle);
1208
1209         /* Initialize a bunch of registers */
1210         init_registers(dev);
1211
1212         gfar_set_mac_address(dev);
1213
1214         err = init_phy(dev);
1215
1216         if(err) {
1217                 napi_disable(&priv->napi);
1218                 return err;
1219         }
1220
1221         err = startup_gfar(dev);
1222         if (err) {
1223                 napi_disable(&priv->napi);
1224                 return err;
1225         }
1226
1227         netif_start_queue(dev);
1228
1229         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1230
1231         return err;
1232 }
1233
1234 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1235 {
1236         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1237
1238         cacheable_memzero(fcb, GMAC_FCB_LEN);
1239
1240         return fcb;
1241 }
1242
1243 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1244 {
1245         u8 flags = 0;
1246
1247         /* If we're here, it's a IP packet with a TCP or UDP
1248          * payload.  We set it to checksum, using a pseudo-header
1249          * we provide
1250          */
1251         flags = TXFCB_DEFAULT;
1252
1253         /* Tell the controller what the protocol is */
1254         /* And provide the already calculated phcs */
1255         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1256                 flags |= TXFCB_UDP;
1257                 fcb->phcs = udp_hdr(skb)->check;
1258         } else
1259                 fcb->phcs = tcp_hdr(skb)->check;
1260
1261         /* l3os is the distance between the start of the
1262          * frame (skb->data) and the start of the IP hdr.
1263          * l4os is the distance between the start of the
1264          * l3 hdr and the l4 hdr */
1265         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1266         fcb->l4os = skb_network_header_len(skb);
1267
1268         fcb->flags = flags;
1269 }
1270
1271 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1272 {
1273         fcb->flags |= TXFCB_VLN;
1274         fcb->vlctl = vlan_tx_tag_get(skb);
1275 }
1276
1277 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1278                                struct txbd8 *base, int ring_size)
1279 {
1280         struct txbd8 *new_bd = bdp + stride;
1281
1282         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1283 }
1284
1285 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1286                 int ring_size)
1287 {
1288         return skip_txbd(bdp, 1, base, ring_size);
1289 }
1290
1291 /* This is called by the kernel when a frame is ready for transmission. */
1292 /* It is pointed to by the dev->hard_start_xmit function pointer */
1293 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1294 {
1295         struct gfar_private *priv = netdev_priv(dev);
1296         struct txfcb *fcb = NULL;
1297         struct txbd8 *txbdp, *txbdp_start, *base;
1298         u32 lstatus;
1299         int i;
1300         u32 bufaddr;
1301         unsigned long flags;
1302         unsigned int nr_frags, length;
1303
1304         base = priv->tx_bd_base;
1305
1306         /* total number of fragments in the SKB */
1307         nr_frags = skb_shinfo(skb)->nr_frags;
1308
1309         spin_lock_irqsave(&priv->txlock, flags);
1310
1311         /* check if there is space to queue this packet */
1312         if (nr_frags > priv->num_txbdfree) {
1313                 /* no space, stop the queue */
1314                 netif_stop_queue(dev);
1315                 dev->stats.tx_fifo_errors++;
1316                 spin_unlock_irqrestore(&priv->txlock, flags);
1317                 return NETDEV_TX_BUSY;
1318         }
1319
1320         /* Update transmit stats */
1321         dev->stats.tx_bytes += skb->len;
1322
1323         txbdp = txbdp_start = priv->cur_tx;
1324
1325         if (nr_frags == 0) {
1326                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1327         } else {
1328                 /* Place the fragment addresses and lengths into the TxBDs */
1329                 for (i = 0; i < nr_frags; i++) {
1330                         /* Point at the next BD, wrapping as needed */
1331                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1332
1333                         length = skb_shinfo(skb)->frags[i].size;
1334
1335                         lstatus = txbdp->lstatus | length |
1336                                 BD_LFLAG(TXBD_READY);
1337
1338                         /* Handle the last BD specially */
1339                         if (i == nr_frags - 1)
1340                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1341
1342                         bufaddr = dma_map_page(&dev->dev,
1343                                         skb_shinfo(skb)->frags[i].page,
1344                                         skb_shinfo(skb)->frags[i].page_offset,
1345                                         length,
1346                                         DMA_TO_DEVICE);
1347
1348                         /* set the TxBD length and buffer pointer */
1349                         txbdp->bufPtr = bufaddr;
1350                         txbdp->lstatus = lstatus;
1351                 }
1352
1353                 lstatus = txbdp_start->lstatus;
1354         }
1355
1356         /* Set up checksumming */
1357         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1358                 fcb = gfar_add_fcb(skb);
1359                 lstatus |= BD_LFLAG(TXBD_TOE);
1360                 gfar_tx_checksum(skb, fcb);
1361         }
1362
1363         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1364                 if (unlikely(NULL == fcb)) {
1365                         fcb = gfar_add_fcb(skb);
1366                         lstatus |= BD_LFLAG(TXBD_TOE);
1367                 }
1368
1369                 gfar_tx_vlan(skb, fcb);
1370         }
1371
1372         /* setup the TxBD length and buffer pointer for the first BD */
1373         priv->tx_skbuff[priv->skb_curtx] = skb;
1374         txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data,
1375                         skb_headlen(skb), DMA_TO_DEVICE);
1376
1377         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1378
1379         /*
1380          * The powerpc-specific eieio() is used, as wmb() has too strong
1381          * semantics (it requires synchronization between cacheable and
1382          * uncacheable mappings, which eieio doesn't provide and which we
1383          * don't need), thus requiring a more expensive sync instruction.  At
1384          * some point, the set of architecture-independent barrier functions
1385          * should be expanded to include weaker barriers.
1386          */
1387         eieio();
1388
1389         txbdp_start->lstatus = lstatus;
1390
1391         /* Update the current skb pointer to the next entry we will use
1392          * (wrapping if necessary) */
1393         priv->skb_curtx = (priv->skb_curtx + 1) &
1394                 TX_RING_MOD_MASK(priv->tx_ring_size);
1395
1396         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1397
1398         /* reduce TxBD free count */
1399         priv->num_txbdfree -= (nr_frags + 1);
1400
1401         dev->trans_start = jiffies;
1402
1403         /* If the next BD still needs to be cleaned up, then the bds
1404            are full.  We need to tell the kernel to stop sending us stuff. */
1405         if (!priv->num_txbdfree) {
1406                 netif_stop_queue(dev);
1407
1408                 dev->stats.tx_fifo_errors++;
1409         }
1410
1411         /* Tell the DMA to go go go */
1412         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1413
1414         /* Unlock priv */
1415         spin_unlock_irqrestore(&priv->txlock, flags);
1416
1417         return 0;
1418 }
1419
1420 /* Stops the kernel queue, and halts the controller */
1421 static int gfar_close(struct net_device *dev)
1422 {
1423         struct gfar_private *priv = netdev_priv(dev);
1424
1425         napi_disable(&priv->napi);
1426
1427         skb_queue_purge(&priv->rx_recycle);
1428         cancel_work_sync(&priv->reset_task);
1429         stop_gfar(dev);
1430
1431         /* Disconnect from the PHY */
1432         phy_disconnect(priv->phydev);
1433         priv->phydev = NULL;
1434
1435         netif_stop_queue(dev);
1436
1437         return 0;
1438 }
1439
1440 /* Changes the mac address if the controller is not running. */
1441 static int gfar_set_mac_address(struct net_device *dev)
1442 {
1443         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1444
1445         return 0;
1446 }
1447
1448
1449 /* Enables and disables VLAN insertion/extraction */
1450 static void gfar_vlan_rx_register(struct net_device *dev,
1451                 struct vlan_group *grp)
1452 {
1453         struct gfar_private *priv = netdev_priv(dev);
1454         unsigned long flags;
1455         u32 tempval;
1456
1457         spin_lock_irqsave(&priv->rxlock, flags);
1458
1459         priv->vlgrp = grp;
1460
1461         if (grp) {
1462                 /* Enable VLAN tag insertion */
1463                 tempval = gfar_read(&priv->regs->tctrl);
1464                 tempval |= TCTRL_VLINS;
1465
1466                 gfar_write(&priv->regs->tctrl, tempval);
1467
1468                 /* Enable VLAN tag extraction */
1469                 tempval = gfar_read(&priv->regs->rctrl);
1470                 tempval |= RCTRL_VLEX;
1471                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1472                 gfar_write(&priv->regs->rctrl, tempval);
1473         } else {
1474                 /* Disable VLAN tag insertion */
1475                 tempval = gfar_read(&priv->regs->tctrl);
1476                 tempval &= ~TCTRL_VLINS;
1477                 gfar_write(&priv->regs->tctrl, tempval);
1478
1479                 /* Disable VLAN tag extraction */
1480                 tempval = gfar_read(&priv->regs->rctrl);
1481                 tempval &= ~RCTRL_VLEX;
1482                 /* If parse is no longer required, then disable parser */
1483                 if (tempval & RCTRL_REQ_PARSER)
1484                         tempval |= RCTRL_PRSDEP_INIT;
1485                 else
1486                         tempval &= ~RCTRL_PRSDEP_INIT;
1487                 gfar_write(&priv->regs->rctrl, tempval);
1488         }
1489
1490         gfar_change_mtu(dev, dev->mtu);
1491
1492         spin_unlock_irqrestore(&priv->rxlock, flags);
1493 }
1494
1495 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1496 {
1497         int tempsize, tempval;
1498         struct gfar_private *priv = netdev_priv(dev);
1499         int oldsize = priv->rx_buffer_size;
1500         int frame_size = new_mtu + ETH_HLEN;
1501
1502         if (priv->vlgrp)
1503                 frame_size += VLAN_HLEN;
1504
1505         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1506                 if (netif_msg_drv(priv))
1507                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1508                                         dev->name);
1509                 return -EINVAL;
1510         }
1511
1512         if (gfar_uses_fcb(priv))
1513                 frame_size += GMAC_FCB_LEN;
1514
1515         frame_size += priv->padding;
1516
1517         tempsize =
1518             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1519             INCREMENTAL_BUFFER_SIZE;
1520
1521         /* Only stop and start the controller if it isn't already
1522          * stopped, and we changed something */
1523         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1524                 stop_gfar(dev);
1525
1526         priv->rx_buffer_size = tempsize;
1527
1528         dev->mtu = new_mtu;
1529
1530         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1531         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1532
1533         /* If the mtu is larger than the max size for standard
1534          * ethernet frames (ie, a jumbo frame), then set maccfg2
1535          * to allow huge frames, and to check the length */
1536         tempval = gfar_read(&priv->regs->maccfg2);
1537
1538         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1539                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1540         else
1541                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1542
1543         gfar_write(&priv->regs->maccfg2, tempval);
1544
1545         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1546                 startup_gfar(dev);
1547
1548         return 0;
1549 }
1550
1551 /* gfar_reset_task gets scheduled when a packet has not been
1552  * transmitted after a set amount of time.
1553  * For now, assume that clearing out all the structures, and
1554  * starting over will fix the problem.
1555  */
1556 static void gfar_reset_task(struct work_struct *work)
1557 {
1558         struct gfar_private *priv = container_of(work, struct gfar_private,
1559                         reset_task);
1560         struct net_device *dev = priv->dev;
1561
1562         if (dev->flags & IFF_UP) {
1563                 stop_gfar(dev);
1564                 startup_gfar(dev);
1565         }
1566
1567         netif_tx_schedule_all(dev);
1568 }
1569
1570 static void gfar_timeout(struct net_device *dev)
1571 {
1572         struct gfar_private *priv = netdev_priv(dev);
1573
1574         dev->stats.tx_errors++;
1575         schedule_work(&priv->reset_task);
1576 }
1577
1578 /* Interrupt Handler for Transmit complete */
1579 static int gfar_clean_tx_ring(struct net_device *dev)
1580 {
1581         struct gfar_private *priv = netdev_priv(dev);
1582         struct txbd8 *bdp;
1583         struct txbd8 *lbdp = NULL;
1584         struct txbd8 *base = priv->tx_bd_base;
1585         struct sk_buff *skb;
1586         int skb_dirtytx;
1587         int tx_ring_size = priv->tx_ring_size;
1588         int frags = 0;
1589         int i;
1590         int howmany = 0;
1591         u32 lstatus;
1592
1593         bdp = priv->dirty_tx;
1594         skb_dirtytx = priv->skb_dirtytx;
1595
1596         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1597                 frags = skb_shinfo(skb)->nr_frags;
1598                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1599
1600                 lstatus = lbdp->lstatus;
1601
1602                 /* Only clean completed frames */
1603                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1604                                 (lstatus & BD_LENGTH_MASK))
1605                         break;
1606
1607                 dma_unmap_single(&dev->dev,
1608                                 bdp->bufPtr,
1609                                 bdp->length,
1610                                 DMA_TO_DEVICE);
1611
1612                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1613                 bdp = next_txbd(bdp, base, tx_ring_size);
1614
1615                 for (i = 0; i < frags; i++) {
1616                         dma_unmap_page(&dev->dev,
1617                                         bdp->bufPtr,
1618                                         bdp->length,
1619                                         DMA_TO_DEVICE);
1620                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1621                         bdp = next_txbd(bdp, base, tx_ring_size);
1622                 }
1623
1624                 /*
1625                  * If there's room in the queue (limit it to rx_buffer_size)
1626                  * we add this skb back into the pool, if it's the right size
1627                  */
1628                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1629                                 skb_recycle_check(skb, priv->rx_buffer_size +
1630                                         RXBUF_ALIGNMENT))
1631                         __skb_queue_head(&priv->rx_recycle, skb);
1632                 else
1633                         dev_kfree_skb_any(skb);
1634
1635                 priv->tx_skbuff[skb_dirtytx] = NULL;
1636
1637                 skb_dirtytx = (skb_dirtytx + 1) &
1638                         TX_RING_MOD_MASK(tx_ring_size);
1639
1640                 howmany++;
1641                 priv->num_txbdfree += frags + 1;
1642         }
1643
1644         /* If we freed a buffer, we can restart transmission, if necessary */
1645         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1646                 netif_wake_queue(dev);
1647
1648         /* Update dirty indicators */
1649         priv->skb_dirtytx = skb_dirtytx;
1650         priv->dirty_tx = bdp;
1651
1652         dev->stats.tx_packets += howmany;
1653
1654         return howmany;
1655 }
1656
1657 static void gfar_schedule_cleanup(struct net_device *dev)
1658 {
1659         struct gfar_private *priv = netdev_priv(dev);
1660         unsigned long flags;
1661
1662         spin_lock_irqsave(&priv->txlock, flags);
1663         spin_lock(&priv->rxlock);
1664
1665         if (napi_schedule_prep(&priv->napi)) {
1666                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1667                 __napi_schedule(&priv->napi);
1668         }
1669
1670         spin_unlock(&priv->rxlock);
1671         spin_unlock_irqrestore(&priv->txlock, flags);
1672 }
1673
1674 /* Interrupt Handler for Transmit complete */
1675 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1676 {
1677         gfar_schedule_cleanup((struct net_device *)dev_id);
1678         return IRQ_HANDLED;
1679 }
1680
1681 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1682                 struct sk_buff *skb)
1683 {
1684         struct gfar_private *priv = netdev_priv(dev);
1685         u32 lstatus;
1686
1687         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1688                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1689
1690         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1691
1692         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1693                 lstatus |= BD_LFLAG(RXBD_WRAP);
1694
1695         eieio();
1696
1697         bdp->lstatus = lstatus;
1698 }
1699
1700
1701 struct sk_buff * gfar_new_skb(struct net_device *dev)
1702 {
1703         unsigned int alignamount;
1704         struct gfar_private *priv = netdev_priv(dev);
1705         struct sk_buff *skb = NULL;
1706
1707         skb = __skb_dequeue(&priv->rx_recycle);
1708         if (!skb)
1709                 skb = netdev_alloc_skb(dev,
1710                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1711
1712         if (!skb)
1713                 return NULL;
1714
1715         alignamount = RXBUF_ALIGNMENT -
1716                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1717
1718         /* We need the data buffer to be aligned properly.  We will reserve
1719          * as many bytes as needed to align the data properly
1720          */
1721         skb_reserve(skb, alignamount);
1722
1723         return skb;
1724 }
1725
1726 static inline void count_errors(unsigned short status, struct net_device *dev)
1727 {
1728         struct gfar_private *priv = netdev_priv(dev);
1729         struct net_device_stats *stats = &dev->stats;
1730         struct gfar_extra_stats *estats = &priv->extra_stats;
1731
1732         /* If the packet was truncated, none of the other errors
1733          * matter */
1734         if (status & RXBD_TRUNCATED) {
1735                 stats->rx_length_errors++;
1736
1737                 estats->rx_trunc++;
1738
1739                 return;
1740         }
1741         /* Count the errors, if there were any */
1742         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1743                 stats->rx_length_errors++;
1744
1745                 if (status & RXBD_LARGE)
1746                         estats->rx_large++;
1747                 else
1748                         estats->rx_short++;
1749         }
1750         if (status & RXBD_NONOCTET) {
1751                 stats->rx_frame_errors++;
1752                 estats->rx_nonoctet++;
1753         }
1754         if (status & RXBD_CRCERR) {
1755                 estats->rx_crcerr++;
1756                 stats->rx_crc_errors++;
1757         }
1758         if (status & RXBD_OVERRUN) {
1759                 estats->rx_overrun++;
1760                 stats->rx_crc_errors++;
1761         }
1762 }
1763
1764 irqreturn_t gfar_receive(int irq, void *dev_id)
1765 {
1766         gfar_schedule_cleanup((struct net_device *)dev_id);
1767         return IRQ_HANDLED;
1768 }
1769
1770 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1771 {
1772         /* If valid headers were found, and valid sums
1773          * were verified, then we tell the kernel that no
1774          * checksumming is necessary.  Otherwise, it is */
1775         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1776                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1777         else
1778                 skb->ip_summed = CHECKSUM_NONE;
1779 }
1780
1781
1782 /* gfar_process_frame() -- handle one incoming packet if skb
1783  * isn't NULL.  */
1784 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1785                               int amount_pull)
1786 {
1787         struct gfar_private *priv = netdev_priv(dev);
1788         struct rxfcb *fcb = NULL;
1789
1790         int ret;
1791
1792         /* fcb is at the beginning if exists */
1793         fcb = (struct rxfcb *)skb->data;
1794
1795         /* Remove the FCB from the skb */
1796         /* Remove the padded bytes, if there are any */
1797         if (amount_pull)
1798                 skb_pull(skb, amount_pull);
1799
1800         if (priv->rx_csum_enable)
1801                 gfar_rx_checksum(skb, fcb);
1802
1803         /* Tell the skb what kind of packet this is */
1804         skb->protocol = eth_type_trans(skb, dev);
1805
1806         /* Send the packet up the stack */
1807         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1808                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1809         else
1810                 ret = netif_receive_skb(skb);
1811
1812         if (NET_RX_DROP == ret)
1813                 priv->extra_stats.kernel_dropped++;
1814
1815         return 0;
1816 }
1817
1818 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1819  *   until the budget/quota has been reached. Returns the number
1820  *   of frames handled
1821  */
1822 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1823 {
1824         struct rxbd8 *bdp, *base;
1825         struct sk_buff *skb;
1826         int pkt_len;
1827         int amount_pull;
1828         int howmany = 0;
1829         struct gfar_private *priv = netdev_priv(dev);
1830
1831         /* Get the first full descriptor */
1832         bdp = priv->cur_rx;
1833         base = priv->rx_bd_base;
1834
1835         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1836                 priv->padding;
1837
1838         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1839                 struct sk_buff *newskb;
1840                 rmb();
1841
1842                 /* Add another skb for the future */
1843                 newskb = gfar_new_skb(dev);
1844
1845                 skb = priv->rx_skbuff[priv->skb_currx];
1846
1847                 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1848                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1849
1850                 /* We drop the frame if we failed to allocate a new buffer */
1851                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1852                                  bdp->status & RXBD_ERR)) {
1853                         count_errors(bdp->status, dev);
1854
1855                         if (unlikely(!newskb))
1856                                 newskb = skb;
1857                         else if (skb)
1858                                 __skb_queue_head(&priv->rx_recycle, skb);
1859                 } else {
1860                         /* Increment the number of packets */
1861                         dev->stats.rx_packets++;
1862                         howmany++;
1863
1864                         if (likely(skb)) {
1865                                 pkt_len = bdp->length - ETH_FCS_LEN;
1866                                 /* Remove the FCS from the packet length */
1867                                 skb_put(skb, pkt_len);
1868                                 dev->stats.rx_bytes += pkt_len;
1869
1870                                 if (in_irq() || irqs_disabled())
1871                                         printk("Interrupt problem!\n");
1872                                 gfar_process_frame(dev, skb, amount_pull);
1873
1874                         } else {
1875                                 if (netif_msg_rx_err(priv))
1876                                         printk(KERN_WARNING
1877                                                "%s: Missing skb!\n", dev->name);
1878                                 dev->stats.rx_dropped++;
1879                                 priv->extra_stats.rx_skbmissing++;
1880                         }
1881
1882                 }
1883
1884                 priv->rx_skbuff[priv->skb_currx] = newskb;
1885
1886                 /* Setup the new bdp */
1887                 gfar_new_rxbdp(dev, bdp, newskb);
1888
1889                 /* Update to the next pointer */
1890                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1891
1892                 /* update to point at the next skb */
1893                 priv->skb_currx =
1894                     (priv->skb_currx + 1) &
1895                     RX_RING_MOD_MASK(priv->rx_ring_size);
1896         }
1897
1898         /* Update the current rxbd pointer to be the next one */
1899         priv->cur_rx = bdp;
1900
1901         return howmany;
1902 }
1903
1904 static int gfar_poll(struct napi_struct *napi, int budget)
1905 {
1906         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1907         struct net_device *dev = priv->dev;
1908         int tx_cleaned = 0;
1909         int rx_cleaned = 0;
1910         unsigned long flags;
1911
1912         /* Clear IEVENT, so interrupts aren't called again
1913          * because of the packets that have already arrived */
1914         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1915
1916         /* If we fail to get the lock, don't bother with the TX BDs */
1917         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1918                 tx_cleaned = gfar_clean_tx_ring(dev);
1919                 spin_unlock_irqrestore(&priv->txlock, flags);
1920         }
1921
1922         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1923
1924         if (tx_cleaned)
1925                 return budget;
1926
1927         if (rx_cleaned < budget) {
1928                 napi_complete(napi);
1929
1930                 /* Clear the halt bit in RSTAT */
1931                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1932
1933                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1934
1935                 /* If we are coalescing interrupts, update the timer */
1936                 /* Otherwise, clear it */
1937                 if (likely(priv->rxcoalescing)) {
1938                         gfar_write(&priv->regs->rxic, 0);
1939                         gfar_write(&priv->regs->rxic, priv->rxic);
1940                 }
1941                 if (likely(priv->txcoalescing)) {
1942                         gfar_write(&priv->regs->txic, 0);
1943                         gfar_write(&priv->regs->txic, priv->txic);
1944                 }
1945         }
1946
1947         return rx_cleaned;
1948 }
1949
1950 #ifdef CONFIG_NET_POLL_CONTROLLER
1951 /*
1952  * Polling 'interrupt' - used by things like netconsole to send skbs
1953  * without having to re-enable interrupts. It's not called while
1954  * the interrupt routine is executing.
1955  */
1956 static void gfar_netpoll(struct net_device *dev)
1957 {
1958         struct gfar_private *priv = netdev_priv(dev);
1959
1960         /* If the device has multiple interrupts, run tx/rx */
1961         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1962                 disable_irq(priv->interruptTransmit);
1963                 disable_irq(priv->interruptReceive);
1964                 disable_irq(priv->interruptError);
1965                 gfar_interrupt(priv->interruptTransmit, dev);
1966                 enable_irq(priv->interruptError);
1967                 enable_irq(priv->interruptReceive);
1968                 enable_irq(priv->interruptTransmit);
1969         } else {
1970                 disable_irq(priv->interruptTransmit);
1971                 gfar_interrupt(priv->interruptTransmit, dev);
1972                 enable_irq(priv->interruptTransmit);
1973         }
1974 }
1975 #endif
1976
1977 /* The interrupt handler for devices with one interrupt */
1978 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1979 {
1980         struct net_device *dev = dev_id;
1981         struct gfar_private *priv = netdev_priv(dev);
1982
1983         /* Save ievent for future reference */
1984         u32 events = gfar_read(&priv->regs->ievent);
1985
1986         /* Check for reception */
1987         if (events & IEVENT_RX_MASK)
1988                 gfar_receive(irq, dev_id);
1989
1990         /* Check for transmit completion */
1991         if (events & IEVENT_TX_MASK)
1992                 gfar_transmit(irq, dev_id);
1993
1994         /* Check for errors */
1995         if (events & IEVENT_ERR_MASK)
1996                 gfar_error(irq, dev_id);
1997
1998         return IRQ_HANDLED;
1999 }
2000
2001 /* Called every time the controller might need to be made
2002  * aware of new link state.  The PHY code conveys this
2003  * information through variables in the phydev structure, and this
2004  * function converts those variables into the appropriate
2005  * register values, and can bring down the device if needed.
2006  */
2007 static void adjust_link(struct net_device *dev)
2008 {
2009         struct gfar_private *priv = netdev_priv(dev);
2010         struct gfar __iomem *regs = priv->regs;
2011         unsigned long flags;
2012         struct phy_device *phydev = priv->phydev;
2013         int new_state = 0;
2014
2015         spin_lock_irqsave(&priv->txlock, flags);
2016         if (phydev->link) {
2017                 u32 tempval = gfar_read(&regs->maccfg2);
2018                 u32 ecntrl = gfar_read(&regs->ecntrl);
2019
2020                 /* Now we make sure that we can be in full duplex mode.
2021                  * If not, we operate in half-duplex mode. */
2022                 if (phydev->duplex != priv->oldduplex) {
2023                         new_state = 1;
2024                         if (!(phydev->duplex))
2025                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2026                         else
2027                                 tempval |= MACCFG2_FULL_DUPLEX;
2028
2029                         priv->oldduplex = phydev->duplex;
2030                 }
2031
2032                 if (phydev->speed != priv->oldspeed) {
2033                         new_state = 1;
2034                         switch (phydev->speed) {
2035                         case 1000:
2036                                 tempval =
2037                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2038
2039                                 ecntrl &= ~(ECNTRL_R100);
2040                                 break;
2041                         case 100:
2042                         case 10:
2043                                 tempval =
2044                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2045
2046                                 /* Reduced mode distinguishes
2047                                  * between 10 and 100 */
2048                                 if (phydev->speed == SPEED_100)
2049                                         ecntrl |= ECNTRL_R100;
2050                                 else
2051                                         ecntrl &= ~(ECNTRL_R100);
2052                                 break;
2053                         default:
2054                                 if (netif_msg_link(priv))
2055                                         printk(KERN_WARNING
2056                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2057                                                 dev->name, phydev->speed);
2058                                 break;
2059                         }
2060
2061                         priv->oldspeed = phydev->speed;
2062                 }
2063
2064                 gfar_write(&regs->maccfg2, tempval);
2065                 gfar_write(&regs->ecntrl, ecntrl);
2066
2067                 if (!priv->oldlink) {
2068                         new_state = 1;
2069                         priv->oldlink = 1;
2070                 }
2071         } else if (priv->oldlink) {
2072                 new_state = 1;
2073                 priv->oldlink = 0;
2074                 priv->oldspeed = 0;
2075                 priv->oldduplex = -1;
2076         }
2077
2078         if (new_state && netif_msg_link(priv))
2079                 phy_print_status(phydev);
2080
2081         spin_unlock_irqrestore(&priv->txlock, flags);
2082 }
2083
2084 /* Update the hash table based on the current list of multicast
2085  * addresses we subscribe to.  Also, change the promiscuity of
2086  * the device based on the flags (this function is called
2087  * whenever dev->flags is changed */
2088 static void gfar_set_multi(struct net_device *dev)
2089 {
2090         struct dev_mc_list *mc_ptr;
2091         struct gfar_private *priv = netdev_priv(dev);
2092         struct gfar __iomem *regs = priv->regs;
2093         u32 tempval;
2094
2095         if(dev->flags & IFF_PROMISC) {
2096                 /* Set RCTRL to PROM */
2097                 tempval = gfar_read(&regs->rctrl);
2098                 tempval |= RCTRL_PROM;
2099                 gfar_write(&regs->rctrl, tempval);
2100         } else {
2101                 /* Set RCTRL to not PROM */
2102                 tempval = gfar_read(&regs->rctrl);
2103                 tempval &= ~(RCTRL_PROM);
2104                 gfar_write(&regs->rctrl, tempval);
2105         }
2106
2107         if(dev->flags & IFF_ALLMULTI) {
2108                 /* Set the hash to rx all multicast frames */
2109                 gfar_write(&regs->igaddr0, 0xffffffff);
2110                 gfar_write(&regs->igaddr1, 0xffffffff);
2111                 gfar_write(&regs->igaddr2, 0xffffffff);
2112                 gfar_write(&regs->igaddr3, 0xffffffff);
2113                 gfar_write(&regs->igaddr4, 0xffffffff);
2114                 gfar_write(&regs->igaddr5, 0xffffffff);
2115                 gfar_write(&regs->igaddr6, 0xffffffff);
2116                 gfar_write(&regs->igaddr7, 0xffffffff);
2117                 gfar_write(&regs->gaddr0, 0xffffffff);
2118                 gfar_write(&regs->gaddr1, 0xffffffff);
2119                 gfar_write(&regs->gaddr2, 0xffffffff);
2120                 gfar_write(&regs->gaddr3, 0xffffffff);
2121                 gfar_write(&regs->gaddr4, 0xffffffff);
2122                 gfar_write(&regs->gaddr5, 0xffffffff);
2123                 gfar_write(&regs->gaddr6, 0xffffffff);
2124                 gfar_write(&regs->gaddr7, 0xffffffff);
2125         } else {
2126                 int em_num;
2127                 int idx;
2128
2129                 /* zero out the hash */
2130                 gfar_write(&regs->igaddr0, 0x0);
2131                 gfar_write(&regs->igaddr1, 0x0);
2132                 gfar_write(&regs->igaddr2, 0x0);
2133                 gfar_write(&regs->igaddr3, 0x0);
2134                 gfar_write(&regs->igaddr4, 0x0);
2135                 gfar_write(&regs->igaddr5, 0x0);
2136                 gfar_write(&regs->igaddr6, 0x0);
2137                 gfar_write(&regs->igaddr7, 0x0);
2138                 gfar_write(&regs->gaddr0, 0x0);
2139                 gfar_write(&regs->gaddr1, 0x0);
2140                 gfar_write(&regs->gaddr2, 0x0);
2141                 gfar_write(&regs->gaddr3, 0x0);
2142                 gfar_write(&regs->gaddr4, 0x0);
2143                 gfar_write(&regs->gaddr5, 0x0);
2144                 gfar_write(&regs->gaddr6, 0x0);
2145                 gfar_write(&regs->gaddr7, 0x0);
2146
2147                 /* If we have extended hash tables, we need to
2148                  * clear the exact match registers to prepare for
2149                  * setting them */
2150                 if (priv->extended_hash) {
2151                         em_num = GFAR_EM_NUM + 1;
2152                         gfar_clear_exact_match(dev);
2153                         idx = 1;
2154                 } else {
2155                         idx = 0;
2156                         em_num = 0;
2157                 }
2158
2159                 if(dev->mc_count == 0)
2160                         return;
2161
2162                 /* Parse the list, and set the appropriate bits */
2163                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2164                         if (idx < em_num) {
2165                                 gfar_set_mac_for_addr(dev, idx,
2166                                                 mc_ptr->dmi_addr);
2167                                 idx++;
2168                         } else
2169                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2170                 }
2171         }
2172
2173         return;
2174 }
2175
2176
2177 /* Clears each of the exact match registers to zero, so they
2178  * don't interfere with normal reception */
2179 static void gfar_clear_exact_match(struct net_device *dev)
2180 {
2181         int idx;
2182         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2183
2184         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2185                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2186 }
2187
2188 /* Set the appropriate hash bit for the given addr */
2189 /* The algorithm works like so:
2190  * 1) Take the Destination Address (ie the multicast address), and
2191  * do a CRC on it (little endian), and reverse the bits of the
2192  * result.
2193  * 2) Use the 8 most significant bits as a hash into a 256-entry
2194  * table.  The table is controlled through 8 32-bit registers:
2195  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2196  * gaddr7.  This means that the 3 most significant bits in the
2197  * hash index which gaddr register to use, and the 5 other bits
2198  * indicate which bit (assuming an IBM numbering scheme, which
2199  * for PowerPC (tm) is usually the case) in the register holds
2200  * the entry. */
2201 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2202 {
2203         u32 tempval;
2204         struct gfar_private *priv = netdev_priv(dev);
2205         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2206         int width = priv->hash_width;
2207         u8 whichbit = (result >> (32 - width)) & 0x1f;
2208         u8 whichreg = result >> (32 - width + 5);
2209         u32 value = (1 << (31-whichbit));
2210
2211         tempval = gfar_read(priv->hash_regs[whichreg]);
2212         tempval |= value;
2213         gfar_write(priv->hash_regs[whichreg], tempval);
2214
2215         return;
2216 }
2217
2218
2219 /* There are multiple MAC Address register pairs on some controllers
2220  * This function sets the numth pair to a given address
2221  */
2222 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2223 {
2224         struct gfar_private *priv = netdev_priv(dev);
2225         int idx;
2226         char tmpbuf[MAC_ADDR_LEN];
2227         u32 tempval;
2228         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2229
2230         macptr += num*2;
2231
2232         /* Now copy it into the mac registers backwards, cuz */
2233         /* little endian is silly */
2234         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2235                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2236
2237         gfar_write(macptr, *((u32 *) (tmpbuf)));
2238
2239         tempval = *((u32 *) (tmpbuf + 4));
2240
2241         gfar_write(macptr+1, tempval);
2242 }
2243
2244 /* GFAR error interrupt handler */
2245 static irqreturn_t gfar_error(int irq, void *dev_id)
2246 {
2247         struct net_device *dev = dev_id;
2248         struct gfar_private *priv = netdev_priv(dev);
2249
2250         /* Save ievent for future reference */
2251         u32 events = gfar_read(&priv->regs->ievent);
2252
2253         /* Clear IEVENT */
2254         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2255
2256         /* Magic Packet is not an error. */
2257         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2258             (events & IEVENT_MAG))
2259                 events &= ~IEVENT_MAG;
2260
2261         /* Hmm... */
2262         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2263                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2264                        dev->name, events, gfar_read(&priv->regs->imask));
2265
2266         /* Update the error counters */
2267         if (events & IEVENT_TXE) {
2268                 dev->stats.tx_errors++;
2269
2270                 if (events & IEVENT_LC)
2271                         dev->stats.tx_window_errors++;
2272                 if (events & IEVENT_CRL)
2273                         dev->stats.tx_aborted_errors++;
2274                 if (events & IEVENT_XFUN) {
2275                         if (netif_msg_tx_err(priv))
2276                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2277                                        "packet dropped.\n", dev->name);
2278                         dev->stats.tx_dropped++;
2279                         priv->extra_stats.tx_underrun++;
2280
2281                         /* Reactivate the Tx Queues */
2282                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2283                 }
2284                 if (netif_msg_tx_err(priv))
2285                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2286         }
2287         if (events & IEVENT_BSY) {
2288                 dev->stats.rx_errors++;
2289                 priv->extra_stats.rx_bsy++;
2290
2291                 gfar_receive(irq, dev_id);
2292
2293                 if (netif_msg_rx_err(priv))
2294                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2295                                dev->name, gfar_read(&priv->regs->rstat));
2296         }
2297         if (events & IEVENT_BABR) {
2298                 dev->stats.rx_errors++;
2299                 priv->extra_stats.rx_babr++;
2300
2301                 if (netif_msg_rx_err(priv))
2302                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2303         }
2304         if (events & IEVENT_EBERR) {
2305                 priv->extra_stats.eberr++;
2306                 if (netif_msg_rx_err(priv))
2307                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2308         }
2309         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2310                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2311
2312         if (events & IEVENT_BABT) {
2313                 priv->extra_stats.tx_babt++;
2314                 if (netif_msg_tx_err(priv))
2315                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2316         }
2317         return IRQ_HANDLED;
2318 }
2319
2320 /* work with hotplug and coldplug */
2321 MODULE_ALIAS("platform:fsl-gianfar");
2322
2323 static struct of_device_id gfar_match[] =
2324 {
2325         {
2326                 .type = "network",
2327                 .compatible = "gianfar",
2328         },
2329         {},
2330 };
2331
2332 /* Structure for a device driver */
2333 static struct of_platform_driver gfar_driver = {
2334         .name = "fsl-gianfar",
2335         .match_table = gfar_match,
2336
2337         .probe = gfar_probe,
2338         .remove = gfar_remove,
2339         .suspend = gfar_suspend,
2340         .resume = gfar_resume,
2341 };
2342
2343 static int __init gfar_init(void)
2344 {
2345         return of_register_platform_driver(&gfar_driver);
2346 }
2347
2348 static void __exit gfar_exit(void)
2349 {
2350         of_unregister_platform_driver(&gfar_driver);
2351 }
2352
2353 module_init(gfar_init);
2354 module_exit(gfar_exit);
2355