remove bogus CONFIG_GFAR_NAPI's
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through platform_device.  Structures which
29  *  define the configuration needed by the board are defined in a
30  *  board structure in arch/ppc/platforms (though I do not
31  *  discount the possibility that other architectures could one
32  *  day be supported.
33  *
34  *  The Gianfar Ethernet Controller uses a ring of buffer
35  *  descriptors.  The beginning is indicated by a register
36  *  pointing to the physical address of the start of the ring.
37  *  The end is determined by a "wrap" bit being set in the
38  *  last descriptor of the ring.
39  *
40  *  When a packet is received, the RXF bit in the
41  *  IEVENT register is set, triggering an interrupt when the
42  *  corresponding bit in the IMASK register is also set (if
43  *  interrupt coalescing is active, then the interrupt may not
44  *  happen immediately, but will wait until either a set number
45  *  of frames or amount of time have passed).  In NAPI, the
46  *  interrupt handler will signal there is work to be done, and
47  *  exit. This method will start at the last known empty
48  *  descriptor, and process every subsequent descriptor until there
49  *  are none left with data (NAPI will stop after a set number of
50  *  packets to give time to other tasks, but will eventually
51  *  process all the packets).  The data arrives inside a
52  *  pre-allocated skb, and so after the skb is passed up to the
53  *  stack, a new skb must be allocated, and the address field in
54  *  the buffer descriptor must be updated to indicate this new
55  *  skb.
56  *
57  *  When the kernel requests that a packet be transmitted, the
58  *  driver starts where it left off last time, and points the
59  *  descriptor at the buffer which was passed in.  The driver
60  *  then informs the DMA engine that there are packets ready to
61  *  be transmitted.  Once the controller is finished transmitting
62  *  the packet, an interrupt may be triggered (under the same
63  *  conditions as for reception, but depending on the TXF bit).
64  *  The driver then cleans up the buffer.
65  */
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/platform_device.h>
82 #include <linux/ip.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
85 #include <linux/in.h>
86
87 #include <asm/io.h>
88 #include <asm/irq.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
95
96 #include "gianfar.h"
97 #include "gianfar_mii.h"
98
99 #define TX_TIMEOUT      (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112                 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct platform_device *pdev);
122 static int gfar_remove(struct platform_device *pdev);
123 static void free_skb_resources(struct gfar_private *priv);
124 static void gfar_set_multi(struct net_device *dev);
125 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
126 static void gfar_configure_serdes(struct net_device *dev);
127 static int gfar_poll(struct napi_struct *napi, int budget);
128 #ifdef CONFIG_NET_POLL_CONTROLLER
129 static void gfar_netpoll(struct net_device *dev);
130 #endif
131 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
132 static int gfar_clean_tx_ring(struct net_device *dev);
133 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
134 static void gfar_vlan_rx_register(struct net_device *netdev,
135                                 struct vlan_group *grp);
136 void gfar_halt(struct net_device *dev);
137 #ifdef CONFIG_PM
138 static void gfar_halt_nodisable(struct net_device *dev);
139 #endif
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143
144 extern const struct ethtool_ops gfar_ethtool_ops;
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private *priv)
152 {
153         return (priv->vlan_enable || priv->rx_csum_enable);
154 }
155
156 /* Set up the ethernet device structure, private data,
157  * and anything else we need before we start */
158 static int gfar_probe(struct platform_device *pdev)
159 {
160         u32 tempval;
161         struct net_device *dev = NULL;
162         struct gfar_private *priv = NULL;
163         struct gianfar_platform_data *einfo;
164         struct resource *r;
165         int err = 0;
166         DECLARE_MAC_BUF(mac);
167
168         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
169
170         if (NULL == einfo) {
171                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
172                        pdev->id);
173
174                 return -ENODEV;
175         }
176
177         /* Create an ethernet device instance */
178         dev = alloc_etherdev(sizeof (*priv));
179
180         if (NULL == dev)
181                 return -ENOMEM;
182
183         priv = netdev_priv(dev);
184         priv->dev = dev;
185
186         /* Set the info in the priv to the current info */
187         priv->einfo = einfo;
188
189         /* fill out IRQ fields */
190         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
191                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
192                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
193                 priv->interruptError = platform_get_irq_byname(pdev, "error");
194                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
195                         goto regs_fail;
196         } else {
197                 priv->interruptTransmit = platform_get_irq(pdev, 0);
198                 if (priv->interruptTransmit < 0)
199                         goto regs_fail;
200         }
201
202         /* get a pointer to the register memory */
203         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
204         priv->regs = ioremap(r->start, sizeof (struct gfar));
205
206         if (NULL == priv->regs) {
207                 err = -ENOMEM;
208                 goto regs_fail;
209         }
210
211         spin_lock_init(&priv->txlock);
212         spin_lock_init(&priv->rxlock);
213         spin_lock_init(&priv->bflock);
214
215         platform_set_drvdata(pdev, dev);
216
217         /* Stop the DMA engine now, in case it was running before */
218         /* (The firmware could have used it, and left it running). */
219         /* To do this, we write Graceful Receive Stop and Graceful */
220         /* Transmit Stop, and then wait until the corresponding bits */
221         /* in IEVENT indicate the stops have completed. */
222         tempval = gfar_read(&priv->regs->dmactrl);
223         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
224         gfar_write(&priv->regs->dmactrl, tempval);
225
226         tempval = gfar_read(&priv->regs->dmactrl);
227         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
228         gfar_write(&priv->regs->dmactrl, tempval);
229
230         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
231                 cpu_relax();
232
233         /* Reset MAC layer */
234         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
235
236         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
237         gfar_write(&priv->regs->maccfg1, tempval);
238
239         /* Initialize MACCFG2. */
240         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
241
242         /* Initialize ECNTRL */
243         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
244
245         /* Copy the station address into the dev structure, */
246         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
247
248         /* Set the dev->base_addr to the gfar reg region */
249         dev->base_addr = (unsigned long) (priv->regs);
250
251         SET_NETDEV_DEV(dev, &pdev->dev);
252
253         /* Fill in the dev structure */
254         dev->open = gfar_enet_open;
255         dev->hard_start_xmit = gfar_start_xmit;
256         dev->tx_timeout = gfar_timeout;
257         dev->watchdog_timeo = TX_TIMEOUT;
258         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
259 #ifdef CONFIG_NET_POLL_CONTROLLER
260         dev->poll_controller = gfar_netpoll;
261 #endif
262         dev->stop = gfar_close;
263         dev->change_mtu = gfar_change_mtu;
264         dev->mtu = 1500;
265         dev->set_multicast_list = gfar_set_multi;
266
267         dev->ethtool_ops = &gfar_ethtool_ops;
268
269         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
270                 priv->rx_csum_enable = 1;
271                 dev->features |= NETIF_F_IP_CSUM;
272         } else
273                 priv->rx_csum_enable = 0;
274
275         priv->vlgrp = NULL;
276
277         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
278                 dev->vlan_rx_register = gfar_vlan_rx_register;
279
280                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
281
282                 priv->vlan_enable = 1;
283         }
284
285         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
286                 priv->extended_hash = 1;
287                 priv->hash_width = 9;
288
289                 priv->hash_regs[0] = &priv->regs->igaddr0;
290                 priv->hash_regs[1] = &priv->regs->igaddr1;
291                 priv->hash_regs[2] = &priv->regs->igaddr2;
292                 priv->hash_regs[3] = &priv->regs->igaddr3;
293                 priv->hash_regs[4] = &priv->regs->igaddr4;
294                 priv->hash_regs[5] = &priv->regs->igaddr5;
295                 priv->hash_regs[6] = &priv->regs->igaddr6;
296                 priv->hash_regs[7] = &priv->regs->igaddr7;
297                 priv->hash_regs[8] = &priv->regs->gaddr0;
298                 priv->hash_regs[9] = &priv->regs->gaddr1;
299                 priv->hash_regs[10] = &priv->regs->gaddr2;
300                 priv->hash_regs[11] = &priv->regs->gaddr3;
301                 priv->hash_regs[12] = &priv->regs->gaddr4;
302                 priv->hash_regs[13] = &priv->regs->gaddr5;
303                 priv->hash_regs[14] = &priv->regs->gaddr6;
304                 priv->hash_regs[15] = &priv->regs->gaddr7;
305
306         } else {
307                 priv->extended_hash = 0;
308                 priv->hash_width = 8;
309
310                 priv->hash_regs[0] = &priv->regs->gaddr0;
311                 priv->hash_regs[1] = &priv->regs->gaddr1;
312                 priv->hash_regs[2] = &priv->regs->gaddr2;
313                 priv->hash_regs[3] = &priv->regs->gaddr3;
314                 priv->hash_regs[4] = &priv->regs->gaddr4;
315                 priv->hash_regs[5] = &priv->regs->gaddr5;
316                 priv->hash_regs[6] = &priv->regs->gaddr6;
317                 priv->hash_regs[7] = &priv->regs->gaddr7;
318         }
319
320         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
321                 priv->padding = DEFAULT_PADDING;
322         else
323                 priv->padding = 0;
324
325         if (dev->features & NETIF_F_IP_CSUM)
326                 dev->hard_header_len += GMAC_FCB_LEN;
327
328         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
329         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
330         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
331
332         priv->txcoalescing = DEFAULT_TX_COALESCE;
333         priv->txcount = DEFAULT_TXCOUNT;
334         priv->txtime = DEFAULT_TXTIME;
335         priv->rxcoalescing = DEFAULT_RX_COALESCE;
336         priv->rxcount = DEFAULT_RXCOUNT;
337         priv->rxtime = DEFAULT_RXTIME;
338
339         /* Enable most messages by default */
340         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
341
342         err = register_netdev(dev);
343
344         if (err) {
345                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
346                                 dev->name);
347                 goto register_fail;
348         }
349
350         /* Create all the sysfs files */
351         gfar_init_sysfs(dev);
352
353         /* Print out the device info */
354         printk(KERN_INFO DEVICE_NAME "%s\n",
355                dev->name, print_mac(mac, dev->dev_addr));
356
357         /* Even more device info helps when determining which kernel */
358         /* provided which set of benchmarks. */
359         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
360         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
361                dev->name, priv->rx_ring_size, priv->tx_ring_size);
362
363         return 0;
364
365 register_fail:
366         iounmap(priv->regs);
367 regs_fail:
368         free_netdev(dev);
369         return err;
370 }
371
372 static int gfar_remove(struct platform_device *pdev)
373 {
374         struct net_device *dev = platform_get_drvdata(pdev);
375         struct gfar_private *priv = netdev_priv(dev);
376
377         platform_set_drvdata(pdev, NULL);
378
379         iounmap(priv->regs);
380         free_netdev(dev);
381
382         return 0;
383 }
384
385 #ifdef CONFIG_PM
386 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
387 {
388         struct net_device *dev = platform_get_drvdata(pdev);
389         struct gfar_private *priv = netdev_priv(dev);
390         unsigned long flags;
391         u32 tempval;
392
393         int magic_packet = priv->wol_en &&
394                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
395
396         netif_device_detach(dev);
397
398         if (netif_running(dev)) {
399                 spin_lock_irqsave(&priv->txlock, flags);
400                 spin_lock(&priv->rxlock);
401
402                 gfar_halt_nodisable(dev);
403
404                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
405                 tempval = gfar_read(&priv->regs->maccfg1);
406
407                 tempval &= ~MACCFG1_TX_EN;
408
409                 if (!magic_packet)
410                         tempval &= ~MACCFG1_RX_EN;
411
412                 gfar_write(&priv->regs->maccfg1, tempval);
413
414                 spin_unlock(&priv->rxlock);
415                 spin_unlock_irqrestore(&priv->txlock, flags);
416
417                 napi_disable(&priv->napi);
418
419                 if (magic_packet) {
420                         /* Enable interrupt on Magic Packet */
421                         gfar_write(&priv->regs->imask, IMASK_MAG);
422
423                         /* Enable Magic Packet mode */
424                         tempval = gfar_read(&priv->regs->maccfg2);
425                         tempval |= MACCFG2_MPEN;
426                         gfar_write(&priv->regs->maccfg2, tempval);
427                 } else {
428                         phy_stop(priv->phydev);
429                 }
430         }
431
432         return 0;
433 }
434
435 static int gfar_resume(struct platform_device *pdev)
436 {
437         struct net_device *dev = platform_get_drvdata(pdev);
438         struct gfar_private *priv = netdev_priv(dev);
439         unsigned long flags;
440         u32 tempval;
441         int magic_packet = priv->wol_en &&
442                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
443
444         if (!netif_running(dev)) {
445                 netif_device_attach(dev);
446                 return 0;
447         }
448
449         if (!magic_packet && priv->phydev)
450                 phy_start(priv->phydev);
451
452         /* Disable Magic Packet mode, in case something
453          * else woke us up.
454          */
455
456         spin_lock_irqsave(&priv->txlock, flags);
457         spin_lock(&priv->rxlock);
458
459         tempval = gfar_read(&priv->regs->maccfg2);
460         tempval &= ~MACCFG2_MPEN;
461         gfar_write(&priv->regs->maccfg2, tempval);
462
463         gfar_start(dev);
464
465         spin_unlock(&priv->rxlock);
466         spin_unlock_irqrestore(&priv->txlock, flags);
467
468         netif_device_attach(dev);
469
470         napi_enable(&priv->napi);
471
472         return 0;
473 }
474 #else
475 #define gfar_suspend NULL
476 #define gfar_resume NULL
477 #endif
478
479 /* Reads the controller's registers to determine what interface
480  * connects it to the PHY.
481  */
482 static phy_interface_t gfar_get_interface(struct net_device *dev)
483 {
484         struct gfar_private *priv = netdev_priv(dev);
485         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
486
487         if (ecntrl & ECNTRL_SGMII_MODE)
488                 return PHY_INTERFACE_MODE_SGMII;
489
490         if (ecntrl & ECNTRL_TBI_MODE) {
491                 if (ecntrl & ECNTRL_REDUCED_MODE)
492                         return PHY_INTERFACE_MODE_RTBI;
493                 else
494                         return PHY_INTERFACE_MODE_TBI;
495         }
496
497         if (ecntrl & ECNTRL_REDUCED_MODE) {
498                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
499                         return PHY_INTERFACE_MODE_RMII;
500                 else {
501                         phy_interface_t interface = priv->einfo->interface;
502
503                         /*
504                          * This isn't autodetected right now, so it must
505                          * be set by the device tree or platform code.
506                          */
507                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
508                                 return PHY_INTERFACE_MODE_RGMII_ID;
509
510                         return PHY_INTERFACE_MODE_RGMII;
511                 }
512         }
513
514         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
515                 return PHY_INTERFACE_MODE_GMII;
516
517         return PHY_INTERFACE_MODE_MII;
518 }
519
520
521 /* Initializes driver's PHY state, and attaches to the PHY.
522  * Returns 0 on success.
523  */
524 static int init_phy(struct net_device *dev)
525 {
526         struct gfar_private *priv = netdev_priv(dev);
527         uint gigabit_support =
528                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
529                 SUPPORTED_1000baseT_Full : 0;
530         struct phy_device *phydev;
531         char phy_id[BUS_ID_SIZE];
532         phy_interface_t interface;
533
534         priv->oldlink = 0;
535         priv->oldspeed = 0;
536         priv->oldduplex = -1;
537
538         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
539
540         interface = gfar_get_interface(dev);
541
542         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
543
544         if (interface == PHY_INTERFACE_MODE_SGMII)
545                 gfar_configure_serdes(dev);
546
547         if (IS_ERR(phydev)) {
548                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
549                 return PTR_ERR(phydev);
550         }
551
552         /* Remove any features not supported by the controller */
553         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
554         phydev->advertising = phydev->supported;
555
556         priv->phydev = phydev;
557
558         return 0;
559 }
560
561 /*
562  * Initialize TBI PHY interface for communicating with the
563  * SERDES lynx PHY on the chip.  We communicate with this PHY
564  * through the MDIO bus on each controller, treating it as a
565  * "normal" PHY at the address found in the TBIPA register.  We assume
566  * that the TBIPA register is valid.  Either the MDIO bus code will set
567  * it to a value that doesn't conflict with other PHYs on the bus, or the
568  * value doesn't matter, as there are no other PHYs on the bus.
569  */
570 static void gfar_configure_serdes(struct net_device *dev)
571 {
572         struct gfar_private *priv = netdev_priv(dev);
573         struct gfar_mii __iomem *regs =
574                         (void __iomem *)&priv->regs->gfar_mii_regs;
575         int tbipa = gfar_read(&priv->regs->tbipa);
576
577         /* Single clk mode, mii mode off(for serdes communication) */
578         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
579
580         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
581                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
582                         ADVERTISE_1000XPSE_ASYM);
583
584         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
585                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
586 }
587
588 static void init_registers(struct net_device *dev)
589 {
590         struct gfar_private *priv = netdev_priv(dev);
591
592         /* Clear IEVENT */
593         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
594
595         /* Initialize IMASK */
596         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
597
598         /* Init hash registers to zero */
599         gfar_write(&priv->regs->igaddr0, 0);
600         gfar_write(&priv->regs->igaddr1, 0);
601         gfar_write(&priv->regs->igaddr2, 0);
602         gfar_write(&priv->regs->igaddr3, 0);
603         gfar_write(&priv->regs->igaddr4, 0);
604         gfar_write(&priv->regs->igaddr5, 0);
605         gfar_write(&priv->regs->igaddr6, 0);
606         gfar_write(&priv->regs->igaddr7, 0);
607
608         gfar_write(&priv->regs->gaddr0, 0);
609         gfar_write(&priv->regs->gaddr1, 0);
610         gfar_write(&priv->regs->gaddr2, 0);
611         gfar_write(&priv->regs->gaddr3, 0);
612         gfar_write(&priv->regs->gaddr4, 0);
613         gfar_write(&priv->regs->gaddr5, 0);
614         gfar_write(&priv->regs->gaddr6, 0);
615         gfar_write(&priv->regs->gaddr7, 0);
616
617         /* Zero out the rmon mib registers if it has them */
618         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
619                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
620
621                 /* Mask off the CAM interrupts */
622                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
623                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
624         }
625
626         /* Initialize the max receive buffer length */
627         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
628
629         /* Initialize the Minimum Frame Length Register */
630         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
631 }
632
633
634 #ifdef CONFIG_PM
635 /* Halt the receive and transmit queues */
636 static void gfar_halt_nodisable(struct net_device *dev)
637 {
638         struct gfar_private *priv = netdev_priv(dev);
639         struct gfar __iomem *regs = priv->regs;
640         u32 tempval;
641
642         /* Mask all interrupts */
643         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
644
645         /* Clear all interrupts */
646         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
647
648         /* Stop the DMA, and wait for it to stop */
649         tempval = gfar_read(&priv->regs->dmactrl);
650         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
651             != (DMACTRL_GRS | DMACTRL_GTS)) {
652                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
653                 gfar_write(&priv->regs->dmactrl, tempval);
654
655                 while (!(gfar_read(&priv->regs->ievent) &
656                          (IEVENT_GRSC | IEVENT_GTSC)))
657                         cpu_relax();
658         }
659 }
660 #endif
661
662 /* Halt the receive and transmit queues */
663 void gfar_halt(struct net_device *dev)
664 {
665         struct gfar_private *priv = netdev_priv(dev);
666         struct gfar __iomem *regs = priv->regs;
667         u32 tempval;
668
669         /* Disable Rx and Tx */
670         tempval = gfar_read(&regs->maccfg1);
671         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
672         gfar_write(&regs->maccfg1, tempval);
673 }
674
675 void stop_gfar(struct net_device *dev)
676 {
677         struct gfar_private *priv = netdev_priv(dev);
678         struct gfar __iomem *regs = priv->regs;
679         unsigned long flags;
680
681         phy_stop(priv->phydev);
682
683         /* Lock it down */
684         spin_lock_irqsave(&priv->txlock, flags);
685         spin_lock(&priv->rxlock);
686
687         gfar_halt(dev);
688
689         spin_unlock(&priv->rxlock);
690         spin_unlock_irqrestore(&priv->txlock, flags);
691
692         /* Free the IRQs */
693         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
694                 free_irq(priv->interruptError, dev);
695                 free_irq(priv->interruptTransmit, dev);
696                 free_irq(priv->interruptReceive, dev);
697         } else {
698                 free_irq(priv->interruptTransmit, dev);
699         }
700
701         free_skb_resources(priv);
702
703         dma_free_coherent(&dev->dev,
704                         sizeof(struct txbd8)*priv->tx_ring_size
705                         + sizeof(struct rxbd8)*priv->rx_ring_size,
706                         priv->tx_bd_base,
707                         gfar_read(&regs->tbase0));
708 }
709
710 /* If there are any tx skbs or rx skbs still around, free them.
711  * Then free tx_skbuff and rx_skbuff */
712 static void free_skb_resources(struct gfar_private *priv)
713 {
714         struct rxbd8 *rxbdp;
715         struct txbd8 *txbdp;
716         int i;
717
718         /* Go through all the buffer descriptors and free their data buffers */
719         txbdp = priv->tx_bd_base;
720
721         for (i = 0; i < priv->tx_ring_size; i++) {
722
723                 if (priv->tx_skbuff[i]) {
724                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
725                                         txbdp->length,
726                                         DMA_TO_DEVICE);
727                         dev_kfree_skb_any(priv->tx_skbuff[i]);
728                         priv->tx_skbuff[i] = NULL;
729                 }
730
731                 txbdp++;
732         }
733
734         kfree(priv->tx_skbuff);
735
736         rxbdp = priv->rx_bd_base;
737
738         /* rx_skbuff is not guaranteed to be allocated, so only
739          * free it and its contents if it is allocated */
740         if(priv->rx_skbuff != NULL) {
741                 for (i = 0; i < priv->rx_ring_size; i++) {
742                         if (priv->rx_skbuff[i]) {
743                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
744                                                 priv->rx_buffer_size,
745                                                 DMA_FROM_DEVICE);
746
747                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
748                                 priv->rx_skbuff[i] = NULL;
749                         }
750
751                         rxbdp->status = 0;
752                         rxbdp->length = 0;
753                         rxbdp->bufPtr = 0;
754
755                         rxbdp++;
756                 }
757
758                 kfree(priv->rx_skbuff);
759         }
760 }
761
762 void gfar_start(struct net_device *dev)
763 {
764         struct gfar_private *priv = netdev_priv(dev);
765         struct gfar __iomem *regs = priv->regs;
766         u32 tempval;
767
768         /* Enable Rx and Tx in MACCFG1 */
769         tempval = gfar_read(&regs->maccfg1);
770         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
771         gfar_write(&regs->maccfg1, tempval);
772
773         /* Initialize DMACTRL to have WWR and WOP */
774         tempval = gfar_read(&priv->regs->dmactrl);
775         tempval |= DMACTRL_INIT_SETTINGS;
776         gfar_write(&priv->regs->dmactrl, tempval);
777
778         /* Make sure we aren't stopped */
779         tempval = gfar_read(&priv->regs->dmactrl);
780         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
781         gfar_write(&priv->regs->dmactrl, tempval);
782
783         /* Clear THLT/RHLT, so that the DMA starts polling now */
784         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
785         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
786
787         /* Unmask the interrupts we look for */
788         gfar_write(&regs->imask, IMASK_DEFAULT);
789 }
790
791 /* Bring the controller up and running */
792 int startup_gfar(struct net_device *dev)
793 {
794         struct txbd8 *txbdp;
795         struct rxbd8 *rxbdp;
796         dma_addr_t addr = 0;
797         unsigned long vaddr;
798         int i;
799         struct gfar_private *priv = netdev_priv(dev);
800         struct gfar __iomem *regs = priv->regs;
801         int err = 0;
802         u32 rctrl = 0;
803         u32 attrs = 0;
804
805         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
806
807         /* Allocate memory for the buffer descriptors */
808         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
809                         sizeof (struct txbd8) * priv->tx_ring_size +
810                         sizeof (struct rxbd8) * priv->rx_ring_size,
811                         &addr, GFP_KERNEL);
812
813         if (vaddr == 0) {
814                 if (netif_msg_ifup(priv))
815                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
816                                         dev->name);
817                 return -ENOMEM;
818         }
819
820         priv->tx_bd_base = (struct txbd8 *) vaddr;
821
822         /* enet DMA only understands physical addresses */
823         gfar_write(&regs->tbase0, addr);
824
825         /* Start the rx descriptor ring where the tx ring leaves off */
826         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
827         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
828         priv->rx_bd_base = (struct rxbd8 *) vaddr;
829         gfar_write(&regs->rbase0, addr);
830
831         /* Setup the skbuff rings */
832         priv->tx_skbuff =
833             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
834                                         priv->tx_ring_size, GFP_KERNEL);
835
836         if (NULL == priv->tx_skbuff) {
837                 if (netif_msg_ifup(priv))
838                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
839                                         dev->name);
840                 err = -ENOMEM;
841                 goto tx_skb_fail;
842         }
843
844         for (i = 0; i < priv->tx_ring_size; i++)
845                 priv->tx_skbuff[i] = NULL;
846
847         priv->rx_skbuff =
848             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
849                                         priv->rx_ring_size, GFP_KERNEL);
850
851         if (NULL == priv->rx_skbuff) {
852                 if (netif_msg_ifup(priv))
853                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
854                                         dev->name);
855                 err = -ENOMEM;
856                 goto rx_skb_fail;
857         }
858
859         for (i = 0; i < priv->rx_ring_size; i++)
860                 priv->rx_skbuff[i] = NULL;
861
862         /* Initialize some variables in our dev structure */
863         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
864         priv->cur_rx = priv->rx_bd_base;
865         priv->skb_curtx = priv->skb_dirtytx = 0;
866         priv->skb_currx = 0;
867
868         /* Initialize Transmit Descriptor Ring */
869         txbdp = priv->tx_bd_base;
870         for (i = 0; i < priv->tx_ring_size; i++) {
871                 txbdp->status = 0;
872                 txbdp->length = 0;
873                 txbdp->bufPtr = 0;
874                 txbdp++;
875         }
876
877         /* Set the last descriptor in the ring to indicate wrap */
878         txbdp--;
879         txbdp->status |= TXBD_WRAP;
880
881         rxbdp = priv->rx_bd_base;
882         for (i = 0; i < priv->rx_ring_size; i++) {
883                 struct sk_buff *skb;
884
885                 skb = gfar_new_skb(dev);
886
887                 if (!skb) {
888                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
889                                         dev->name);
890
891                         goto err_rxalloc_fail;
892                 }
893
894                 priv->rx_skbuff[i] = skb;
895
896                 gfar_new_rxbdp(dev, rxbdp, skb);
897
898                 rxbdp++;
899         }
900
901         /* Set the last descriptor in the ring to wrap */
902         rxbdp--;
903         rxbdp->status |= RXBD_WRAP;
904
905         /* If the device has multiple interrupts, register for
906          * them.  Otherwise, only register for the one */
907         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
908                 /* Install our interrupt handlers for Error,
909                  * Transmit, and Receive */
910                 if (request_irq(priv->interruptError, gfar_error,
911                                 0, "enet_error", dev) < 0) {
912                         if (netif_msg_intr(priv))
913                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
914                                         dev->name, priv->interruptError);
915
916                         err = -1;
917                         goto err_irq_fail;
918                 }
919
920                 if (request_irq(priv->interruptTransmit, gfar_transmit,
921                                 0, "enet_tx", dev) < 0) {
922                         if (netif_msg_intr(priv))
923                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
924                                         dev->name, priv->interruptTransmit);
925
926                         err = -1;
927
928                         goto tx_irq_fail;
929                 }
930
931                 if (request_irq(priv->interruptReceive, gfar_receive,
932                                 0, "enet_rx", dev) < 0) {
933                         if (netif_msg_intr(priv))
934                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
935                                                 dev->name, priv->interruptReceive);
936
937                         err = -1;
938                         goto rx_irq_fail;
939                 }
940         } else {
941                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
942                                 0, "gfar_interrupt", dev) < 0) {
943                         if (netif_msg_intr(priv))
944                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
945                                         dev->name, priv->interruptError);
946
947                         err = -1;
948                         goto err_irq_fail;
949                 }
950         }
951
952         phy_start(priv->phydev);
953
954         /* Configure the coalescing support */
955         if (priv->txcoalescing)
956                 gfar_write(&regs->txic,
957                            mk_ic_value(priv->txcount, priv->txtime));
958         else
959                 gfar_write(&regs->txic, 0);
960
961         if (priv->rxcoalescing)
962                 gfar_write(&regs->rxic,
963                            mk_ic_value(priv->rxcount, priv->rxtime));
964         else
965                 gfar_write(&regs->rxic, 0);
966
967         if (priv->rx_csum_enable)
968                 rctrl |= RCTRL_CHECKSUMMING;
969
970         if (priv->extended_hash) {
971                 rctrl |= RCTRL_EXTHASH;
972
973                 gfar_clear_exact_match(dev);
974                 rctrl |= RCTRL_EMEN;
975         }
976
977         if (priv->vlan_enable)
978                 rctrl |= RCTRL_VLAN;
979
980         if (priv->padding) {
981                 rctrl &= ~RCTRL_PAL_MASK;
982                 rctrl |= RCTRL_PADDING(priv->padding);
983         }
984
985         /* Init rctrl based on our settings */
986         gfar_write(&priv->regs->rctrl, rctrl);
987
988         if (dev->features & NETIF_F_IP_CSUM)
989                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
990
991         /* Set the extraction length and index */
992         attrs = ATTRELI_EL(priv->rx_stash_size) |
993                 ATTRELI_EI(priv->rx_stash_index);
994
995         gfar_write(&priv->regs->attreli, attrs);
996
997         /* Start with defaults, and add stashing or locking
998          * depending on the approprate variables */
999         attrs = ATTR_INIT_SETTINGS;
1000
1001         if (priv->bd_stash_en)
1002                 attrs |= ATTR_BDSTASH;
1003
1004         if (priv->rx_stash_size != 0)
1005                 attrs |= ATTR_BUFSTASH;
1006
1007         gfar_write(&priv->regs->attr, attrs);
1008
1009         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1010         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1011         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1012
1013         /* Start the controller */
1014         gfar_start(dev);
1015
1016         return 0;
1017
1018 rx_irq_fail:
1019         free_irq(priv->interruptTransmit, dev);
1020 tx_irq_fail:
1021         free_irq(priv->interruptError, dev);
1022 err_irq_fail:
1023 err_rxalloc_fail:
1024 rx_skb_fail:
1025         free_skb_resources(priv);
1026 tx_skb_fail:
1027         dma_free_coherent(&dev->dev,
1028                         sizeof(struct txbd8)*priv->tx_ring_size
1029                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1030                         priv->tx_bd_base,
1031                         gfar_read(&regs->tbase0));
1032
1033         return err;
1034 }
1035
1036 /* Called when something needs to use the ethernet device */
1037 /* Returns 0 for success. */
1038 static int gfar_enet_open(struct net_device *dev)
1039 {
1040         struct gfar_private *priv = netdev_priv(dev);
1041         int err;
1042
1043         napi_enable(&priv->napi);
1044
1045         /* Initialize a bunch of registers */
1046         init_registers(dev);
1047
1048         gfar_set_mac_address(dev);
1049
1050         err = init_phy(dev);
1051
1052         if(err) {
1053                 napi_disable(&priv->napi);
1054                 return err;
1055         }
1056
1057         err = startup_gfar(dev);
1058         if (err) {
1059                 napi_disable(&priv->napi);
1060                 return err;
1061         }
1062
1063         netif_start_queue(dev);
1064
1065         return err;
1066 }
1067
1068 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1069 {
1070         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1071
1072         memset(fcb, 0, GMAC_FCB_LEN);
1073
1074         return fcb;
1075 }
1076
1077 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1078 {
1079         u8 flags = 0;
1080
1081         /* If we're here, it's a IP packet with a TCP or UDP
1082          * payload.  We set it to checksum, using a pseudo-header
1083          * we provide
1084          */
1085         flags = TXFCB_DEFAULT;
1086
1087         /* Tell the controller what the protocol is */
1088         /* And provide the already calculated phcs */
1089         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1090                 flags |= TXFCB_UDP;
1091                 fcb->phcs = udp_hdr(skb)->check;
1092         } else
1093                 fcb->phcs = tcp_hdr(skb)->check;
1094
1095         /* l3os is the distance between the start of the
1096          * frame (skb->data) and the start of the IP hdr.
1097          * l4os is the distance between the start of the
1098          * l3 hdr and the l4 hdr */
1099         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1100         fcb->l4os = skb_network_header_len(skb);
1101
1102         fcb->flags = flags;
1103 }
1104
1105 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1106 {
1107         fcb->flags |= TXFCB_VLN;
1108         fcb->vlctl = vlan_tx_tag_get(skb);
1109 }
1110
1111 /* This is called by the kernel when a frame is ready for transmission. */
1112 /* It is pointed to by the dev->hard_start_xmit function pointer */
1113 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1114 {
1115         struct gfar_private *priv = netdev_priv(dev);
1116         struct txfcb *fcb = NULL;
1117         struct txbd8 *txbdp;
1118         u16 status;
1119         unsigned long flags;
1120
1121         /* Update transmit stats */
1122         dev->stats.tx_bytes += skb->len;
1123
1124         /* Lock priv now */
1125         spin_lock_irqsave(&priv->txlock, flags);
1126
1127         /* Point at the first free tx descriptor */
1128         txbdp = priv->cur_tx;
1129
1130         /* Clear all but the WRAP status flags */
1131         status = txbdp->status & TXBD_WRAP;
1132
1133         /* Set up checksumming */
1134         if (likely((dev->features & NETIF_F_IP_CSUM)
1135                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1136                 fcb = gfar_add_fcb(skb, txbdp);
1137                 status |= TXBD_TOE;
1138                 gfar_tx_checksum(skb, fcb);
1139         }
1140
1141         if (priv->vlan_enable &&
1142                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1143                 if (unlikely(NULL == fcb)) {
1144                         fcb = gfar_add_fcb(skb, txbdp);
1145                         status |= TXBD_TOE;
1146                 }
1147
1148                 gfar_tx_vlan(skb, fcb);
1149         }
1150
1151         /* Set buffer length and pointer */
1152         txbdp->length = skb->len;
1153         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1154                         skb->len, DMA_TO_DEVICE);
1155
1156         /* Save the skb pointer so we can free it later */
1157         priv->tx_skbuff[priv->skb_curtx] = skb;
1158
1159         /* Update the current skb pointer (wrapping if this was the last) */
1160         priv->skb_curtx =
1161             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1162
1163         /* Flag the BD as interrupt-causing */
1164         status |= TXBD_INTERRUPT;
1165
1166         /* Flag the BD as ready to go, last in frame, and  */
1167         /* in need of CRC */
1168         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1169
1170         dev->trans_start = jiffies;
1171
1172         /* The powerpc-specific eieio() is used, as wmb() has too strong
1173          * semantics (it requires synchronization between cacheable and
1174          * uncacheable mappings, which eieio doesn't provide and which we
1175          * don't need), thus requiring a more expensive sync instruction.  At
1176          * some point, the set of architecture-independent barrier functions
1177          * should be expanded to include weaker barriers.
1178          */
1179
1180         eieio();
1181         txbdp->status = status;
1182
1183         /* If this was the last BD in the ring, the next one */
1184         /* is at the beginning of the ring */
1185         if (txbdp->status & TXBD_WRAP)
1186                 txbdp = priv->tx_bd_base;
1187         else
1188                 txbdp++;
1189
1190         /* If the next BD still needs to be cleaned up, then the bds
1191            are full.  We need to tell the kernel to stop sending us stuff. */
1192         if (txbdp == priv->dirty_tx) {
1193                 netif_stop_queue(dev);
1194
1195                 dev->stats.tx_fifo_errors++;
1196         }
1197
1198         /* Update the current txbd to the next one */
1199         priv->cur_tx = txbdp;
1200
1201         /* Tell the DMA to go go go */
1202         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1203
1204         /* Unlock priv */
1205         spin_unlock_irqrestore(&priv->txlock, flags);
1206
1207         return 0;
1208 }
1209
1210 /* Stops the kernel queue, and halts the controller */
1211 static int gfar_close(struct net_device *dev)
1212 {
1213         struct gfar_private *priv = netdev_priv(dev);
1214
1215         napi_disable(&priv->napi);
1216
1217         stop_gfar(dev);
1218
1219         /* Disconnect from the PHY */
1220         phy_disconnect(priv->phydev);
1221         priv->phydev = NULL;
1222
1223         netif_stop_queue(dev);
1224
1225         return 0;
1226 }
1227
1228 /* Changes the mac address if the controller is not running. */
1229 static int gfar_set_mac_address(struct net_device *dev)
1230 {
1231         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1232
1233         return 0;
1234 }
1235
1236
1237 /* Enables and disables VLAN insertion/extraction */
1238 static void gfar_vlan_rx_register(struct net_device *dev,
1239                 struct vlan_group *grp)
1240 {
1241         struct gfar_private *priv = netdev_priv(dev);
1242         unsigned long flags;
1243         u32 tempval;
1244
1245         spin_lock_irqsave(&priv->rxlock, flags);
1246
1247         priv->vlgrp = grp;
1248
1249         if (grp) {
1250                 /* Enable VLAN tag insertion */
1251                 tempval = gfar_read(&priv->regs->tctrl);
1252                 tempval |= TCTRL_VLINS;
1253
1254                 gfar_write(&priv->regs->tctrl, tempval);
1255
1256                 /* Enable VLAN tag extraction */
1257                 tempval = gfar_read(&priv->regs->rctrl);
1258                 tempval |= RCTRL_VLEX;
1259                 gfar_write(&priv->regs->rctrl, tempval);
1260         } else {
1261                 /* Disable VLAN tag insertion */
1262                 tempval = gfar_read(&priv->regs->tctrl);
1263                 tempval &= ~TCTRL_VLINS;
1264                 gfar_write(&priv->regs->tctrl, tempval);
1265
1266                 /* Disable VLAN tag extraction */
1267                 tempval = gfar_read(&priv->regs->rctrl);
1268                 tempval &= ~RCTRL_VLEX;
1269                 gfar_write(&priv->regs->rctrl, tempval);
1270         }
1271
1272         spin_unlock_irqrestore(&priv->rxlock, flags);
1273 }
1274
1275 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1276 {
1277         int tempsize, tempval;
1278         struct gfar_private *priv = netdev_priv(dev);
1279         int oldsize = priv->rx_buffer_size;
1280         int frame_size = new_mtu + ETH_HLEN;
1281
1282         if (priv->vlan_enable)
1283                 frame_size += VLAN_HLEN;
1284
1285         if (gfar_uses_fcb(priv))
1286                 frame_size += GMAC_FCB_LEN;
1287
1288         frame_size += priv->padding;
1289
1290         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1291                 if (netif_msg_drv(priv))
1292                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1293                                         dev->name);
1294                 return -EINVAL;
1295         }
1296
1297         tempsize =
1298             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1299             INCREMENTAL_BUFFER_SIZE;
1300
1301         /* Only stop and start the controller if it isn't already
1302          * stopped, and we changed something */
1303         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1304                 stop_gfar(dev);
1305
1306         priv->rx_buffer_size = tempsize;
1307
1308         dev->mtu = new_mtu;
1309
1310         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1311         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1312
1313         /* If the mtu is larger than the max size for standard
1314          * ethernet frames (ie, a jumbo frame), then set maccfg2
1315          * to allow huge frames, and to check the length */
1316         tempval = gfar_read(&priv->regs->maccfg2);
1317
1318         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1319                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1320         else
1321                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1322
1323         gfar_write(&priv->regs->maccfg2, tempval);
1324
1325         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1326                 startup_gfar(dev);
1327
1328         return 0;
1329 }
1330
1331 /* gfar_timeout gets called when a packet has not been
1332  * transmitted after a set amount of time.
1333  * For now, assume that clearing out all the structures, and
1334  * starting over will fix the problem. */
1335 static void gfar_timeout(struct net_device *dev)
1336 {
1337         dev->stats.tx_errors++;
1338
1339         if (dev->flags & IFF_UP) {
1340                 stop_gfar(dev);
1341                 startup_gfar(dev);
1342         }
1343
1344         netif_tx_schedule_all(dev);
1345 }
1346
1347 /* Interrupt Handler for Transmit complete */
1348 static int gfar_clean_tx_ring(struct net_device *dev)
1349 {
1350         struct txbd8 *bdp;
1351         struct gfar_private *priv = netdev_priv(dev);
1352         int howmany = 0;
1353
1354         bdp = priv->dirty_tx;
1355         while ((bdp->status & TXBD_READY) == 0) {
1356                 /* If dirty_tx and cur_tx are the same, then either the */
1357                 /* ring is empty or full now (it could only be full in the beginning, */
1358                 /* obviously).  If it is empty, we are done. */
1359                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1360                         break;
1361
1362                 howmany++;
1363
1364                 /* Deferred means some collisions occurred during transmit, */
1365                 /* but we eventually sent the packet. */
1366                 if (bdp->status & TXBD_DEF)
1367                         dev->stats.collisions++;
1368
1369                 /* Free the sk buffer associated with this TxBD */
1370                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1371
1372                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1373                 priv->skb_dirtytx =
1374                     (priv->skb_dirtytx +
1375                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1376
1377                 /* Clean BD length for empty detection */
1378                 bdp->length = 0;
1379
1380                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1381                 if (bdp->status & TXBD_WRAP)
1382                         bdp = priv->tx_bd_base;
1383                 else
1384                         bdp++;
1385
1386                 /* Move dirty_tx to be the next bd */
1387                 priv->dirty_tx = bdp;
1388
1389                 /* We freed a buffer, so now we can restart transmission */
1390                 if (netif_queue_stopped(dev))
1391                         netif_wake_queue(dev);
1392         } /* while ((bdp->status & TXBD_READY) == 0) */
1393
1394         dev->stats.tx_packets += howmany;
1395
1396         return howmany;
1397 }
1398
1399 /* Interrupt Handler for Transmit complete */
1400 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1401 {
1402         struct net_device *dev = (struct net_device *) dev_id;
1403         struct gfar_private *priv = netdev_priv(dev);
1404
1405         /* Clear IEVENT */
1406         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1407
1408         /* Lock priv */
1409         spin_lock(&priv->txlock);
1410
1411         gfar_clean_tx_ring(dev);
1412
1413         /* If we are coalescing the interrupts, reset the timer */
1414         /* Otherwise, clear it */
1415         if (likely(priv->txcoalescing)) {
1416                 gfar_write(&priv->regs->txic, 0);
1417                 gfar_write(&priv->regs->txic,
1418                            mk_ic_value(priv->txcount, priv->txtime));
1419         }
1420
1421         spin_unlock(&priv->txlock);
1422
1423         return IRQ_HANDLED;
1424 }
1425
1426 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1427                 struct sk_buff *skb)
1428 {
1429         struct gfar_private *priv = netdev_priv(dev);
1430         u32 * status_len = (u32 *)bdp;
1431         u16 flags;
1432
1433         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1434                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1435
1436         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1437
1438         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1439                 flags |= RXBD_WRAP;
1440
1441         eieio();
1442
1443         *status_len = (u32)flags << 16;
1444 }
1445
1446
1447 struct sk_buff * gfar_new_skb(struct net_device *dev)
1448 {
1449         unsigned int alignamount;
1450         struct gfar_private *priv = netdev_priv(dev);
1451         struct sk_buff *skb = NULL;
1452
1453         /* We have to allocate the skb, so keep trying till we succeed */
1454         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1455
1456         if (!skb)
1457                 return NULL;
1458
1459         alignamount = RXBUF_ALIGNMENT -
1460                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1461
1462         /* We need the data buffer to be aligned properly.  We will reserve
1463          * as many bytes as needed to align the data properly
1464          */
1465         skb_reserve(skb, alignamount);
1466
1467         return skb;
1468 }
1469
1470 static inline void count_errors(unsigned short status, struct net_device *dev)
1471 {
1472         struct gfar_private *priv = netdev_priv(dev);
1473         struct net_device_stats *stats = &dev->stats;
1474         struct gfar_extra_stats *estats = &priv->extra_stats;
1475
1476         /* If the packet was truncated, none of the other errors
1477          * matter */
1478         if (status & RXBD_TRUNCATED) {
1479                 stats->rx_length_errors++;
1480
1481                 estats->rx_trunc++;
1482
1483                 return;
1484         }
1485         /* Count the errors, if there were any */
1486         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1487                 stats->rx_length_errors++;
1488
1489                 if (status & RXBD_LARGE)
1490                         estats->rx_large++;
1491                 else
1492                         estats->rx_short++;
1493         }
1494         if (status & RXBD_NONOCTET) {
1495                 stats->rx_frame_errors++;
1496                 estats->rx_nonoctet++;
1497         }
1498         if (status & RXBD_CRCERR) {
1499                 estats->rx_crcerr++;
1500                 stats->rx_crc_errors++;
1501         }
1502         if (status & RXBD_OVERRUN) {
1503                 estats->rx_overrun++;
1504                 stats->rx_crc_errors++;
1505         }
1506 }
1507
1508 irqreturn_t gfar_receive(int irq, void *dev_id)
1509 {
1510         struct net_device *dev = (struct net_device *) dev_id;
1511         struct gfar_private *priv = netdev_priv(dev);
1512         u32 tempval;
1513
1514         /* support NAPI */
1515         /* Clear IEVENT, so interrupts aren't called again
1516          * because of the packets that have already arrived */
1517         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1518
1519         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1520                 tempval = gfar_read(&priv->regs->imask);
1521                 tempval &= IMASK_RTX_DISABLED;
1522                 gfar_write(&priv->regs->imask, tempval);
1523
1524                 __netif_rx_schedule(dev, &priv->napi);
1525         } else {
1526                 if (netif_msg_rx_err(priv))
1527                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1528                                 dev->name, gfar_read(&priv->regs->ievent),
1529                                 gfar_read(&priv->regs->imask));
1530         }
1531
1532         return IRQ_HANDLED;
1533 }
1534
1535 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1536 {
1537         /* If valid headers were found, and valid sums
1538          * were verified, then we tell the kernel that no
1539          * checksumming is necessary.  Otherwise, it is */
1540         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1541                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1542         else
1543                 skb->ip_summed = CHECKSUM_NONE;
1544 }
1545
1546
1547 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1548 {
1549         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1550
1551         /* Remove the FCB from the skb */
1552         skb_pull(skb, GMAC_FCB_LEN);
1553
1554         return fcb;
1555 }
1556
1557 /* gfar_process_frame() -- handle one incoming packet if skb
1558  * isn't NULL.  */
1559 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1560                 int length)
1561 {
1562         struct gfar_private *priv = netdev_priv(dev);
1563         struct rxfcb *fcb = NULL;
1564
1565         if (NULL == skb) {
1566                 if (netif_msg_rx_err(priv))
1567                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1568                 dev->stats.rx_dropped++;
1569                 priv->extra_stats.rx_skbmissing++;
1570         } else {
1571                 int ret;
1572
1573                 /* Prep the skb for the packet */
1574                 skb_put(skb, length);
1575
1576                 /* Grab the FCB if there is one */
1577                 if (gfar_uses_fcb(priv))
1578                         fcb = gfar_get_fcb(skb);
1579
1580                 /* Remove the padded bytes, if there are any */
1581                 if (priv->padding)
1582                         skb_pull(skb, priv->padding);
1583
1584                 if (priv->rx_csum_enable)
1585                         gfar_rx_checksum(skb, fcb);
1586
1587                 /* Tell the skb what kind of packet this is */
1588                 skb->protocol = eth_type_trans(skb, dev);
1589
1590                 /* Send the packet up the stack */
1591                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1592                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1593                                                        fcb->vlctl);
1594                 } else
1595                         ret = netif_receive_skb(skb);
1596
1597                 if (NET_RX_DROP == ret)
1598                         priv->extra_stats.kernel_dropped++;
1599         }
1600
1601         return 0;
1602 }
1603
1604 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1605  *   until the budget/quota has been reached. Returns the number
1606  *   of frames handled
1607  */
1608 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1609 {
1610         struct rxbd8 *bdp;
1611         struct sk_buff *skb;
1612         u16 pkt_len;
1613         int howmany = 0;
1614         struct gfar_private *priv = netdev_priv(dev);
1615
1616         /* Get the first full descriptor */
1617         bdp = priv->cur_rx;
1618
1619         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1620                 struct sk_buff *newskb;
1621                 rmb();
1622
1623                 /* Add another skb for the future */
1624                 newskb = gfar_new_skb(dev);
1625
1626                 skb = priv->rx_skbuff[priv->skb_currx];
1627
1628                 /* We drop the frame if we failed to allocate a new buffer */
1629                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1630                                  bdp->status & RXBD_ERR)) {
1631                         count_errors(bdp->status, dev);
1632
1633                         if (unlikely(!newskb))
1634                                 newskb = skb;
1635
1636                         if (skb) {
1637                                 dma_unmap_single(&priv->dev->dev,
1638                                                 bdp->bufPtr,
1639                                                 priv->rx_buffer_size,
1640                                                 DMA_FROM_DEVICE);
1641
1642                                 dev_kfree_skb_any(skb);
1643                         }
1644                 } else {
1645                         /* Increment the number of packets */
1646                         dev->stats.rx_packets++;
1647                         howmany++;
1648
1649                         /* Remove the FCS from the packet length */
1650                         pkt_len = bdp->length - 4;
1651
1652                         gfar_process_frame(dev, skb, pkt_len);
1653
1654                         dev->stats.rx_bytes += pkt_len;
1655                 }
1656
1657                 dev->last_rx = jiffies;
1658
1659                 priv->rx_skbuff[priv->skb_currx] = newskb;
1660
1661                 /* Setup the new bdp */
1662                 gfar_new_rxbdp(dev, bdp, newskb);
1663
1664                 /* Update to the next pointer */
1665                 if (bdp->status & RXBD_WRAP)
1666                         bdp = priv->rx_bd_base;
1667                 else
1668                         bdp++;
1669
1670                 /* update to point at the next skb */
1671                 priv->skb_currx =
1672                     (priv->skb_currx + 1) &
1673                     RX_RING_MOD_MASK(priv->rx_ring_size);
1674         }
1675
1676         /* Update the current rxbd pointer to be the next one */
1677         priv->cur_rx = bdp;
1678
1679         return howmany;
1680 }
1681
1682 static int gfar_poll(struct napi_struct *napi, int budget)
1683 {
1684         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1685         struct net_device *dev = priv->dev;
1686         int howmany;
1687         unsigned long flags;
1688
1689         /* If we fail to get the lock, don't bother with the TX BDs */
1690         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1691                 gfar_clean_tx_ring(dev);
1692                 spin_unlock_irqrestore(&priv->txlock, flags);
1693         }
1694
1695         howmany = gfar_clean_rx_ring(dev, budget);
1696
1697         if (howmany < budget) {
1698                 netif_rx_complete(dev, napi);
1699
1700                 /* Clear the halt bit in RSTAT */
1701                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1702
1703                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1704
1705                 /* If we are coalescing interrupts, update the timer */
1706                 /* Otherwise, clear it */
1707                 if (likely(priv->rxcoalescing)) {
1708                         gfar_write(&priv->regs->rxic, 0);
1709                         gfar_write(&priv->regs->rxic,
1710                                    mk_ic_value(priv->rxcount, priv->rxtime));
1711                 }
1712         }
1713
1714         return howmany;
1715 }
1716
1717 #ifdef CONFIG_NET_POLL_CONTROLLER
1718 /*
1719  * Polling 'interrupt' - used by things like netconsole to send skbs
1720  * without having to re-enable interrupts. It's not called while
1721  * the interrupt routine is executing.
1722  */
1723 static void gfar_netpoll(struct net_device *dev)
1724 {
1725         struct gfar_private *priv = netdev_priv(dev);
1726
1727         /* If the device has multiple interrupts, run tx/rx */
1728         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1729                 disable_irq(priv->interruptTransmit);
1730                 disable_irq(priv->interruptReceive);
1731                 disable_irq(priv->interruptError);
1732                 gfar_interrupt(priv->interruptTransmit, dev);
1733                 enable_irq(priv->interruptError);
1734                 enable_irq(priv->interruptReceive);
1735                 enable_irq(priv->interruptTransmit);
1736         } else {
1737                 disable_irq(priv->interruptTransmit);
1738                 gfar_interrupt(priv->interruptTransmit, dev);
1739                 enable_irq(priv->interruptTransmit);
1740         }
1741 }
1742 #endif
1743
1744 /* The interrupt handler for devices with one interrupt */
1745 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1746 {
1747         struct net_device *dev = dev_id;
1748         struct gfar_private *priv = netdev_priv(dev);
1749
1750         /* Save ievent for future reference */
1751         u32 events = gfar_read(&priv->regs->ievent);
1752
1753         /* Check for reception */
1754         if (events & IEVENT_RX_MASK)
1755                 gfar_receive(irq, dev_id);
1756
1757         /* Check for transmit completion */
1758         if (events & IEVENT_TX_MASK)
1759                 gfar_transmit(irq, dev_id);
1760
1761         /* Check for errors */
1762         if (events & IEVENT_ERR_MASK)
1763                 gfar_error(irq, dev_id);
1764
1765         return IRQ_HANDLED;
1766 }
1767
1768 /* Called every time the controller might need to be made
1769  * aware of new link state.  The PHY code conveys this
1770  * information through variables in the phydev structure, and this
1771  * function converts those variables into the appropriate
1772  * register values, and can bring down the device if needed.
1773  */
1774 static void adjust_link(struct net_device *dev)
1775 {
1776         struct gfar_private *priv = netdev_priv(dev);
1777         struct gfar __iomem *regs = priv->regs;
1778         unsigned long flags;
1779         struct phy_device *phydev = priv->phydev;
1780         int new_state = 0;
1781
1782         spin_lock_irqsave(&priv->txlock, flags);
1783         if (phydev->link) {
1784                 u32 tempval = gfar_read(&regs->maccfg2);
1785                 u32 ecntrl = gfar_read(&regs->ecntrl);
1786
1787                 /* Now we make sure that we can be in full duplex mode.
1788                  * If not, we operate in half-duplex mode. */
1789                 if (phydev->duplex != priv->oldduplex) {
1790                         new_state = 1;
1791                         if (!(phydev->duplex))
1792                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1793                         else
1794                                 tempval |= MACCFG2_FULL_DUPLEX;
1795
1796                         priv->oldduplex = phydev->duplex;
1797                 }
1798
1799                 if (phydev->speed != priv->oldspeed) {
1800                         new_state = 1;
1801                         switch (phydev->speed) {
1802                         case 1000:
1803                                 tempval =
1804                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1805                                 break;
1806                         case 100:
1807                         case 10:
1808                                 tempval =
1809                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1810
1811                                 /* Reduced mode distinguishes
1812                                  * between 10 and 100 */
1813                                 if (phydev->speed == SPEED_100)
1814                                         ecntrl |= ECNTRL_R100;
1815                                 else
1816                                         ecntrl &= ~(ECNTRL_R100);
1817                                 break;
1818                         default:
1819                                 if (netif_msg_link(priv))
1820                                         printk(KERN_WARNING
1821                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1822                                                 dev->name, phydev->speed);
1823                                 break;
1824                         }
1825
1826                         priv->oldspeed = phydev->speed;
1827                 }
1828
1829                 gfar_write(&regs->maccfg2, tempval);
1830                 gfar_write(&regs->ecntrl, ecntrl);
1831
1832                 if (!priv->oldlink) {
1833                         new_state = 1;
1834                         priv->oldlink = 1;
1835                 }
1836         } else if (priv->oldlink) {
1837                 new_state = 1;
1838                 priv->oldlink = 0;
1839                 priv->oldspeed = 0;
1840                 priv->oldduplex = -1;
1841         }
1842
1843         if (new_state && netif_msg_link(priv))
1844                 phy_print_status(phydev);
1845
1846         spin_unlock_irqrestore(&priv->txlock, flags);
1847 }
1848
1849 /* Update the hash table based on the current list of multicast
1850  * addresses we subscribe to.  Also, change the promiscuity of
1851  * the device based on the flags (this function is called
1852  * whenever dev->flags is changed */
1853 static void gfar_set_multi(struct net_device *dev)
1854 {
1855         struct dev_mc_list *mc_ptr;
1856         struct gfar_private *priv = netdev_priv(dev);
1857         struct gfar __iomem *regs = priv->regs;
1858         u32 tempval;
1859
1860         if(dev->flags & IFF_PROMISC) {
1861                 /* Set RCTRL to PROM */
1862                 tempval = gfar_read(&regs->rctrl);
1863                 tempval |= RCTRL_PROM;
1864                 gfar_write(&regs->rctrl, tempval);
1865         } else {
1866                 /* Set RCTRL to not PROM */
1867                 tempval = gfar_read(&regs->rctrl);
1868                 tempval &= ~(RCTRL_PROM);
1869                 gfar_write(&regs->rctrl, tempval);
1870         }
1871
1872         if(dev->flags & IFF_ALLMULTI) {
1873                 /* Set the hash to rx all multicast frames */
1874                 gfar_write(&regs->igaddr0, 0xffffffff);
1875                 gfar_write(&regs->igaddr1, 0xffffffff);
1876                 gfar_write(&regs->igaddr2, 0xffffffff);
1877                 gfar_write(&regs->igaddr3, 0xffffffff);
1878                 gfar_write(&regs->igaddr4, 0xffffffff);
1879                 gfar_write(&regs->igaddr5, 0xffffffff);
1880                 gfar_write(&regs->igaddr6, 0xffffffff);
1881                 gfar_write(&regs->igaddr7, 0xffffffff);
1882                 gfar_write(&regs->gaddr0, 0xffffffff);
1883                 gfar_write(&regs->gaddr1, 0xffffffff);
1884                 gfar_write(&regs->gaddr2, 0xffffffff);
1885                 gfar_write(&regs->gaddr3, 0xffffffff);
1886                 gfar_write(&regs->gaddr4, 0xffffffff);
1887                 gfar_write(&regs->gaddr5, 0xffffffff);
1888                 gfar_write(&regs->gaddr6, 0xffffffff);
1889                 gfar_write(&regs->gaddr7, 0xffffffff);
1890         } else {
1891                 int em_num;
1892                 int idx;
1893
1894                 /* zero out the hash */
1895                 gfar_write(&regs->igaddr0, 0x0);
1896                 gfar_write(&regs->igaddr1, 0x0);
1897                 gfar_write(&regs->igaddr2, 0x0);
1898                 gfar_write(&regs->igaddr3, 0x0);
1899                 gfar_write(&regs->igaddr4, 0x0);
1900                 gfar_write(&regs->igaddr5, 0x0);
1901                 gfar_write(&regs->igaddr6, 0x0);
1902                 gfar_write(&regs->igaddr7, 0x0);
1903                 gfar_write(&regs->gaddr0, 0x0);
1904                 gfar_write(&regs->gaddr1, 0x0);
1905                 gfar_write(&regs->gaddr2, 0x0);
1906                 gfar_write(&regs->gaddr3, 0x0);
1907                 gfar_write(&regs->gaddr4, 0x0);
1908                 gfar_write(&regs->gaddr5, 0x0);
1909                 gfar_write(&regs->gaddr6, 0x0);
1910                 gfar_write(&regs->gaddr7, 0x0);
1911
1912                 /* If we have extended hash tables, we need to
1913                  * clear the exact match registers to prepare for
1914                  * setting them */
1915                 if (priv->extended_hash) {
1916                         em_num = GFAR_EM_NUM + 1;
1917                         gfar_clear_exact_match(dev);
1918                         idx = 1;
1919                 } else {
1920                         idx = 0;
1921                         em_num = 0;
1922                 }
1923
1924                 if(dev->mc_count == 0)
1925                         return;
1926
1927                 /* Parse the list, and set the appropriate bits */
1928                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1929                         if (idx < em_num) {
1930                                 gfar_set_mac_for_addr(dev, idx,
1931                                                 mc_ptr->dmi_addr);
1932                                 idx++;
1933                         } else
1934                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1935                 }
1936         }
1937
1938         return;
1939 }
1940
1941
1942 /* Clears each of the exact match registers to zero, so they
1943  * don't interfere with normal reception */
1944 static void gfar_clear_exact_match(struct net_device *dev)
1945 {
1946         int idx;
1947         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1948
1949         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1950                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1951 }
1952
1953 /* Set the appropriate hash bit for the given addr */
1954 /* The algorithm works like so:
1955  * 1) Take the Destination Address (ie the multicast address), and
1956  * do a CRC on it (little endian), and reverse the bits of the
1957  * result.
1958  * 2) Use the 8 most significant bits as a hash into a 256-entry
1959  * table.  The table is controlled through 8 32-bit registers:
1960  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1961  * gaddr7.  This means that the 3 most significant bits in the
1962  * hash index which gaddr register to use, and the 5 other bits
1963  * indicate which bit (assuming an IBM numbering scheme, which
1964  * for PowerPC (tm) is usually the case) in the register holds
1965  * the entry. */
1966 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1967 {
1968         u32 tempval;
1969         struct gfar_private *priv = netdev_priv(dev);
1970         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1971         int width = priv->hash_width;
1972         u8 whichbit = (result >> (32 - width)) & 0x1f;
1973         u8 whichreg = result >> (32 - width + 5);
1974         u32 value = (1 << (31-whichbit));
1975
1976         tempval = gfar_read(priv->hash_regs[whichreg]);
1977         tempval |= value;
1978         gfar_write(priv->hash_regs[whichreg], tempval);
1979
1980         return;
1981 }
1982
1983
1984 /* There are multiple MAC Address register pairs on some controllers
1985  * This function sets the numth pair to a given address
1986  */
1987 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1988 {
1989         struct gfar_private *priv = netdev_priv(dev);
1990         int idx;
1991         char tmpbuf[MAC_ADDR_LEN];
1992         u32 tempval;
1993         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1994
1995         macptr += num*2;
1996
1997         /* Now copy it into the mac registers backwards, cuz */
1998         /* little endian is silly */
1999         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2000                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2001
2002         gfar_write(macptr, *((u32 *) (tmpbuf)));
2003
2004         tempval = *((u32 *) (tmpbuf + 4));
2005
2006         gfar_write(macptr+1, tempval);
2007 }
2008
2009 /* GFAR error interrupt handler */
2010 static irqreturn_t gfar_error(int irq, void *dev_id)
2011 {
2012         struct net_device *dev = dev_id;
2013         struct gfar_private *priv = netdev_priv(dev);
2014
2015         /* Save ievent for future reference */
2016         u32 events = gfar_read(&priv->regs->ievent);
2017
2018         /* Clear IEVENT */
2019         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2020
2021         /* Magic Packet is not an error. */
2022         if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2023             (events & IEVENT_MAG))
2024                 events &= ~IEVENT_MAG;
2025
2026         /* Hmm... */
2027         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2028                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2029                        dev->name, events, gfar_read(&priv->regs->imask));
2030
2031         /* Update the error counters */
2032         if (events & IEVENT_TXE) {
2033                 dev->stats.tx_errors++;
2034
2035                 if (events & IEVENT_LC)
2036                         dev->stats.tx_window_errors++;
2037                 if (events & IEVENT_CRL)
2038                         dev->stats.tx_aborted_errors++;
2039                 if (events & IEVENT_XFUN) {
2040                         if (netif_msg_tx_err(priv))
2041                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2042                                        "packet dropped.\n", dev->name);
2043                         dev->stats.tx_dropped++;
2044                         priv->extra_stats.tx_underrun++;
2045
2046                         /* Reactivate the Tx Queues */
2047                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2048                 }
2049                 if (netif_msg_tx_err(priv))
2050                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2051         }
2052         if (events & IEVENT_BSY) {
2053                 dev->stats.rx_errors++;
2054                 priv->extra_stats.rx_bsy++;
2055
2056                 gfar_receive(irq, dev_id);
2057
2058                 if (netif_msg_rx_err(priv))
2059                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2060                                dev->name, gfar_read(&priv->regs->rstat));
2061         }
2062         if (events & IEVENT_BABR) {
2063                 dev->stats.rx_errors++;
2064                 priv->extra_stats.rx_babr++;
2065
2066                 if (netif_msg_rx_err(priv))
2067                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2068         }
2069         if (events & IEVENT_EBERR) {
2070                 priv->extra_stats.eberr++;
2071                 if (netif_msg_rx_err(priv))
2072                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2073         }
2074         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2075                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2076
2077         if (events & IEVENT_BABT) {
2078                 priv->extra_stats.tx_babt++;
2079                 if (netif_msg_tx_err(priv))
2080                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2081         }
2082         return IRQ_HANDLED;
2083 }
2084
2085 /* work with hotplug and coldplug */
2086 MODULE_ALIAS("platform:fsl-gianfar");
2087
2088 /* Structure for a device driver */
2089 static struct platform_driver gfar_driver = {
2090         .probe = gfar_probe,
2091         .remove = gfar_remove,
2092         .suspend = gfar_suspend,
2093         .resume = gfar_resume,
2094         .driver = {
2095                 .name = "fsl-gianfar",
2096                 .owner = THIS_MODULE,
2097         },
2098 };
2099
2100 static int __init gfar_init(void)
2101 {
2102         int err = gfar_mdio_init();
2103
2104         if (err)
2105                 return err;
2106
2107         err = platform_driver_register(&gfar_driver);
2108
2109         if (err)
2110                 gfar_mdio_exit();
2111
2112         return err;
2113 }
2114
2115 static void __exit gfar_exit(void)
2116 {
2117         platform_driver_unregister(&gfar_driver);
2118         gfar_mdio_exit();
2119 }
2120
2121 module_init(gfar_init);
2122 module_exit(gfar_exit);
2123