gianfar: Fix build with CONFIG_PM enabled
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "fsl_pq_mdio.h"
97
98 #define TX_TIMEOUT      (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112                 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122                 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
135                               int amount_pull);
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137                                 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 static const struct net_device_ops gfar_netdev_ops = {
150         .ndo_open = gfar_enet_open,
151         .ndo_start_xmit = gfar_start_xmit,
152         .ndo_stop = gfar_close,
153         .ndo_change_mtu = gfar_change_mtu,
154         .ndo_set_multicast_list = gfar_set_multi,
155         .ndo_tx_timeout = gfar_timeout,
156         .ndo_do_ioctl = gfar_ioctl,
157         .ndo_vlan_rx_register = gfar_vlan_rx_register,
158 #ifdef CONFIG_NET_POLL_CONTROLLER
159         .ndo_poll_controller = gfar_netpoll,
160 #endif
161 };
162
163 /* Returns 1 if incoming frames use an FCB */
164 static inline int gfar_uses_fcb(struct gfar_private *priv)
165 {
166         return priv->vlgrp || priv->rx_csum_enable;
167 }
168
169 static int gfar_of_init(struct net_device *dev)
170 {
171         struct device_node *phy, *mdio;
172         const unsigned int *id;
173         const char *model;
174         const char *ctype;
175         const void *mac_addr;
176         const phandle *ph;
177         u64 addr, size;
178         int err = 0;
179         struct gfar_private *priv = netdev_priv(dev);
180         struct device_node *np = priv->node;
181         char bus_name[MII_BUS_ID_SIZE];
182         const u32 *stash;
183         const u32 *stash_len;
184         const u32 *stash_idx;
185
186         if (!np || !of_device_is_available(np))
187                 return -ENODEV;
188
189         /* get a pointer to the register memory */
190         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
191         priv->regs = ioremap(addr, size);
192
193         if (priv->regs == NULL)
194                 return -ENOMEM;
195
196         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
197
198         model = of_get_property(np, "model", NULL);
199
200         /* If we aren't the FEC we have multiple interrupts */
201         if (model && strcasecmp(model, "FEC")) {
202                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
203
204                 priv->interruptError = irq_of_parse_and_map(np, 2);
205
206                 if (priv->interruptTransmit < 0 ||
207                                 priv->interruptReceive < 0 ||
208                                 priv->interruptError < 0) {
209                         err = -EINVAL;
210                         goto err_out;
211                 }
212         }
213
214         stash = of_get_property(np, "bd-stash", NULL);
215
216         if(stash) {
217                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
218                 priv->bd_stash_en = 1;
219         }
220
221         stash_len = of_get_property(np, "rx-stash-len", NULL);
222
223         if (stash_len)
224                 priv->rx_stash_size = *stash_len;
225
226         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
227
228         if (stash_idx)
229                 priv->rx_stash_index = *stash_idx;
230
231         if (stash_len || stash_idx)
232                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
233
234         mac_addr = of_get_mac_address(np);
235         if (mac_addr)
236                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
237
238         if (model && !strcasecmp(model, "TSEC"))
239                 priv->device_flags =
240                         FSL_GIANFAR_DEV_HAS_GIGABIT |
241                         FSL_GIANFAR_DEV_HAS_COALESCE |
242                         FSL_GIANFAR_DEV_HAS_RMON |
243                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
244         if (model && !strcasecmp(model, "eTSEC"))
245                 priv->device_flags =
246                         FSL_GIANFAR_DEV_HAS_GIGABIT |
247                         FSL_GIANFAR_DEV_HAS_COALESCE |
248                         FSL_GIANFAR_DEV_HAS_RMON |
249                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
250                         FSL_GIANFAR_DEV_HAS_PADDING |
251                         FSL_GIANFAR_DEV_HAS_CSUM |
252                         FSL_GIANFAR_DEV_HAS_VLAN |
253                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
254                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
255
256         ctype = of_get_property(np, "phy-connection-type", NULL);
257
258         /* We only care about rgmii-id.  The rest are autodetected */
259         if (ctype && !strcmp(ctype, "rgmii-id"))
260                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
261         else
262                 priv->interface = PHY_INTERFACE_MODE_MII;
263
264         if (of_get_property(np, "fsl,magic-packet", NULL))
265                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
266
267         ph = of_get_property(np, "phy-handle", NULL);
268         if (ph == NULL) {
269                 u32 *fixed_link;
270
271                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
272                 if (!fixed_link) {
273                         err = -ENODEV;
274                         goto err_out;
275                 }
276
277                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
278                                 PHY_ID_FMT, "0", fixed_link[0]);
279         } else {
280                 phy = of_find_node_by_phandle(*ph);
281
282                 if (phy == NULL) {
283                         err = -ENODEV;
284                         goto err_out;
285                 }
286
287                 mdio = of_get_parent(phy);
288
289                 id = of_get_property(phy, "reg", NULL);
290
291                 of_node_put(phy);
292                 of_node_put(mdio);
293
294                 fsl_pq_mdio_bus_name(bus_name, mdio);
295                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
296                                 bus_name, *id);
297         }
298
299         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
300         ph = of_get_property(np, "tbi-handle", NULL);
301         if (ph) {
302                 struct device_node *tbi = of_find_node_by_phandle(*ph);
303                 struct of_device *ofdev;
304                 struct mii_bus *bus;
305
306                 if (!tbi)
307                         return 0;
308
309                 mdio = of_get_parent(tbi);
310                 if (!mdio)
311                         return 0;
312
313                 ofdev = of_find_device_by_node(mdio);
314
315                 of_node_put(mdio);
316
317                 id = of_get_property(tbi, "reg", NULL);
318                 if (!id)
319                         return 0;
320
321                 of_node_put(tbi);
322
323                 bus = dev_get_drvdata(&ofdev->dev);
324
325                 priv->tbiphy = bus->phy_map[*id];
326         }
327
328         return 0;
329
330 err_out:
331         iounmap(priv->regs);
332         return err;
333 }
334
335 /* Ioctl MII Interface */
336 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
337 {
338         struct gfar_private *priv = netdev_priv(dev);
339
340         if (!netif_running(dev))
341                 return -EINVAL;
342
343         if (!priv->phydev)
344                 return -ENODEV;
345
346         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
347 }
348
349 /* Set up the ethernet device structure, private data,
350  * and anything else we need before we start */
351 static int gfar_probe(struct of_device *ofdev,
352                 const struct of_device_id *match)
353 {
354         u32 tempval;
355         struct net_device *dev = NULL;
356         struct gfar_private *priv = NULL;
357         DECLARE_MAC_BUF(mac);
358         int err = 0;
359         int len_devname;
360
361         /* Create an ethernet device instance */
362         dev = alloc_etherdev(sizeof (*priv));
363
364         if (NULL == dev)
365                 return -ENOMEM;
366
367         priv = netdev_priv(dev);
368         priv->ndev = dev;
369         priv->ofdev = ofdev;
370         priv->node = ofdev->node;
371         SET_NETDEV_DEV(dev, &ofdev->dev);
372
373         err = gfar_of_init(dev);
374
375         if (err)
376                 goto regs_fail;
377
378         spin_lock_init(&priv->txlock);
379         spin_lock_init(&priv->rxlock);
380         spin_lock_init(&priv->bflock);
381         INIT_WORK(&priv->reset_task, gfar_reset_task);
382
383         dev_set_drvdata(&ofdev->dev, priv);
384
385         /* Stop the DMA engine now, in case it was running before */
386         /* (The firmware could have used it, and left it running). */
387         gfar_halt(dev);
388
389         /* Reset MAC layer */
390         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
391
392         /* We need to delay at least 3 TX clocks */
393         udelay(2);
394
395         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
396         gfar_write(&priv->regs->maccfg1, tempval);
397
398         /* Initialize MACCFG2. */
399         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
400
401         /* Initialize ECNTRL */
402         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
403
404         /* Set the dev->base_addr to the gfar reg region */
405         dev->base_addr = (unsigned long) (priv->regs);
406
407         SET_NETDEV_DEV(dev, &ofdev->dev);
408
409         /* Fill in the dev structure */
410         dev->watchdog_timeo = TX_TIMEOUT;
411         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
412         dev->mtu = 1500;
413
414         dev->netdev_ops = &gfar_netdev_ops;
415         dev->ethtool_ops = &gfar_ethtool_ops;
416
417         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
418                 priv->rx_csum_enable = 1;
419                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
420         } else
421                 priv->rx_csum_enable = 0;
422
423         priv->vlgrp = NULL;
424
425         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
426                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
427
428         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
429                 priv->extended_hash = 1;
430                 priv->hash_width = 9;
431
432                 priv->hash_regs[0] = &priv->regs->igaddr0;
433                 priv->hash_regs[1] = &priv->regs->igaddr1;
434                 priv->hash_regs[2] = &priv->regs->igaddr2;
435                 priv->hash_regs[3] = &priv->regs->igaddr3;
436                 priv->hash_regs[4] = &priv->regs->igaddr4;
437                 priv->hash_regs[5] = &priv->regs->igaddr5;
438                 priv->hash_regs[6] = &priv->regs->igaddr6;
439                 priv->hash_regs[7] = &priv->regs->igaddr7;
440                 priv->hash_regs[8] = &priv->regs->gaddr0;
441                 priv->hash_regs[9] = &priv->regs->gaddr1;
442                 priv->hash_regs[10] = &priv->regs->gaddr2;
443                 priv->hash_regs[11] = &priv->regs->gaddr3;
444                 priv->hash_regs[12] = &priv->regs->gaddr4;
445                 priv->hash_regs[13] = &priv->regs->gaddr5;
446                 priv->hash_regs[14] = &priv->regs->gaddr6;
447                 priv->hash_regs[15] = &priv->regs->gaddr7;
448
449         } else {
450                 priv->extended_hash = 0;
451                 priv->hash_width = 8;
452
453                 priv->hash_regs[0] = &priv->regs->gaddr0;
454                 priv->hash_regs[1] = &priv->regs->gaddr1;
455                 priv->hash_regs[2] = &priv->regs->gaddr2;
456                 priv->hash_regs[3] = &priv->regs->gaddr3;
457                 priv->hash_regs[4] = &priv->regs->gaddr4;
458                 priv->hash_regs[5] = &priv->regs->gaddr5;
459                 priv->hash_regs[6] = &priv->regs->gaddr6;
460                 priv->hash_regs[7] = &priv->regs->gaddr7;
461         }
462
463         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
464                 priv->padding = DEFAULT_PADDING;
465         else
466                 priv->padding = 0;
467
468         if (dev->features & NETIF_F_IP_CSUM)
469                 dev->hard_header_len += GMAC_FCB_LEN;
470
471         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
472         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
473         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
474         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
475
476         priv->txcoalescing = DEFAULT_TX_COALESCE;
477         priv->txic = DEFAULT_TXIC;
478         priv->rxcoalescing = DEFAULT_RX_COALESCE;
479         priv->rxic = DEFAULT_RXIC;
480
481         /* Enable most messages by default */
482         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
483
484         /* Carrier starts down, phylib will bring it up */
485         netif_carrier_off(dev);
486
487         err = register_netdev(dev);
488
489         if (err) {
490                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
491                                 dev->name);
492                 goto register_fail;
493         }
494
495         device_init_wakeup(&dev->dev,
496                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
497
498         /* fill out IRQ number and name fields */
499         len_devname = strlen(dev->name);
500         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
501         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
502                 strncpy(&priv->int_name_tx[len_devname],
503                         "_tx", sizeof("_tx") + 1);
504
505                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
506                 strncpy(&priv->int_name_rx[len_devname],
507                         "_rx", sizeof("_rx") + 1);
508
509                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
510                 strncpy(&priv->int_name_er[len_devname],
511                         "_er", sizeof("_er") + 1);
512         } else
513                 priv->int_name_tx[len_devname] = '\0';
514
515         /* Create all the sysfs files */
516         gfar_init_sysfs(dev);
517
518         /* Print out the device info */
519         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
520
521         /* Even more device info helps when determining which kernel */
522         /* provided which set of benchmarks. */
523         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
524         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
525                dev->name, priv->rx_ring_size, priv->tx_ring_size);
526
527         return 0;
528
529 register_fail:
530         iounmap(priv->regs);
531 regs_fail:
532         free_netdev(dev);
533         return err;
534 }
535
536 static int gfar_remove(struct of_device *ofdev)
537 {
538         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
539
540         dev_set_drvdata(&ofdev->dev, NULL);
541
542         iounmap(priv->regs);
543         free_netdev(priv->ndev);
544
545         return 0;
546 }
547
548 #ifdef CONFIG_PM
549 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
550 {
551         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
552         struct net_device *dev = priv->ndev;
553         unsigned long flags;
554         u32 tempval;
555
556         int magic_packet = priv->wol_en &&
557                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
558
559         netif_device_detach(dev);
560
561         if (netif_running(dev)) {
562                 spin_lock_irqsave(&priv->txlock, flags);
563                 spin_lock(&priv->rxlock);
564
565                 gfar_halt_nodisable(dev);
566
567                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
568                 tempval = gfar_read(&priv->regs->maccfg1);
569
570                 tempval &= ~MACCFG1_TX_EN;
571
572                 if (!magic_packet)
573                         tempval &= ~MACCFG1_RX_EN;
574
575                 gfar_write(&priv->regs->maccfg1, tempval);
576
577                 spin_unlock(&priv->rxlock);
578                 spin_unlock_irqrestore(&priv->txlock, flags);
579
580                 napi_disable(&priv->napi);
581
582                 if (magic_packet) {
583                         /* Enable interrupt on Magic Packet */
584                         gfar_write(&priv->regs->imask, IMASK_MAG);
585
586                         /* Enable Magic Packet mode */
587                         tempval = gfar_read(&priv->regs->maccfg2);
588                         tempval |= MACCFG2_MPEN;
589                         gfar_write(&priv->regs->maccfg2, tempval);
590                 } else {
591                         phy_stop(priv->phydev);
592                 }
593         }
594
595         return 0;
596 }
597
598 static int gfar_resume(struct of_device *ofdev)
599 {
600         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
601         struct net_device *dev = priv->ndev;
602         unsigned long flags;
603         u32 tempval;
604         int magic_packet = priv->wol_en &&
605                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
606
607         if (!netif_running(dev)) {
608                 netif_device_attach(dev);
609                 return 0;
610         }
611
612         if (!magic_packet && priv->phydev)
613                 phy_start(priv->phydev);
614
615         /* Disable Magic Packet mode, in case something
616          * else woke us up.
617          */
618
619         spin_lock_irqsave(&priv->txlock, flags);
620         spin_lock(&priv->rxlock);
621
622         tempval = gfar_read(&priv->regs->maccfg2);
623         tempval &= ~MACCFG2_MPEN;
624         gfar_write(&priv->regs->maccfg2, tempval);
625
626         gfar_start(dev);
627
628         spin_unlock(&priv->rxlock);
629         spin_unlock_irqrestore(&priv->txlock, flags);
630
631         netif_device_attach(dev);
632
633         napi_enable(&priv->napi);
634
635         return 0;
636 }
637 #else
638 #define gfar_suspend NULL
639 #define gfar_resume NULL
640 #endif
641
642 /* Reads the controller's registers to determine what interface
643  * connects it to the PHY.
644  */
645 static phy_interface_t gfar_get_interface(struct net_device *dev)
646 {
647         struct gfar_private *priv = netdev_priv(dev);
648         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
649
650         if (ecntrl & ECNTRL_SGMII_MODE)
651                 return PHY_INTERFACE_MODE_SGMII;
652
653         if (ecntrl & ECNTRL_TBI_MODE) {
654                 if (ecntrl & ECNTRL_REDUCED_MODE)
655                         return PHY_INTERFACE_MODE_RTBI;
656                 else
657                         return PHY_INTERFACE_MODE_TBI;
658         }
659
660         if (ecntrl & ECNTRL_REDUCED_MODE) {
661                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
662                         return PHY_INTERFACE_MODE_RMII;
663                 else {
664                         phy_interface_t interface = priv->interface;
665
666                         /*
667                          * This isn't autodetected right now, so it must
668                          * be set by the device tree or platform code.
669                          */
670                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
671                                 return PHY_INTERFACE_MODE_RGMII_ID;
672
673                         return PHY_INTERFACE_MODE_RGMII;
674                 }
675         }
676
677         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
678                 return PHY_INTERFACE_MODE_GMII;
679
680         return PHY_INTERFACE_MODE_MII;
681 }
682
683
684 /* Initializes driver's PHY state, and attaches to the PHY.
685  * Returns 0 on success.
686  */
687 static int init_phy(struct net_device *dev)
688 {
689         struct gfar_private *priv = netdev_priv(dev);
690         uint gigabit_support =
691                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
692                 SUPPORTED_1000baseT_Full : 0;
693         struct phy_device *phydev;
694         phy_interface_t interface;
695
696         priv->oldlink = 0;
697         priv->oldspeed = 0;
698         priv->oldduplex = -1;
699
700         interface = gfar_get_interface(dev);
701
702         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
703
704         if (interface == PHY_INTERFACE_MODE_SGMII)
705                 gfar_configure_serdes(dev);
706
707         if (IS_ERR(phydev)) {
708                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
709                 return PTR_ERR(phydev);
710         }
711
712         /* Remove any features not supported by the controller */
713         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
714         phydev->advertising = phydev->supported;
715
716         priv->phydev = phydev;
717
718         return 0;
719 }
720
721 /*
722  * Initialize TBI PHY interface for communicating with the
723  * SERDES lynx PHY on the chip.  We communicate with this PHY
724  * through the MDIO bus on each controller, treating it as a
725  * "normal" PHY at the address found in the TBIPA register.  We assume
726  * that the TBIPA register is valid.  Either the MDIO bus code will set
727  * it to a value that doesn't conflict with other PHYs on the bus, or the
728  * value doesn't matter, as there are no other PHYs on the bus.
729  */
730 static void gfar_configure_serdes(struct net_device *dev)
731 {
732         struct gfar_private *priv = netdev_priv(dev);
733
734         if (!priv->tbiphy) {
735                 printk(KERN_WARNING "SGMII mode requires that the device "
736                                 "tree specify a tbi-handle\n");
737                 return;
738         }
739
740         /*
741          * If the link is already up, we must already be ok, and don't need to
742          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
743          * everything for us?  Resetting it takes the link down and requires
744          * several seconds for it to come back.
745          */
746         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
747                 return;
748
749         /* Single clk mode, mii mode off(for serdes communication) */
750         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
751
752         phy_write(priv->tbiphy, MII_ADVERTISE,
753                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
754                         ADVERTISE_1000XPSE_ASYM);
755
756         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
757                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
758 }
759
760 static void init_registers(struct net_device *dev)
761 {
762         struct gfar_private *priv = netdev_priv(dev);
763
764         /* Clear IEVENT */
765         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
766
767         /* Initialize IMASK */
768         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
769
770         /* Init hash registers to zero */
771         gfar_write(&priv->regs->igaddr0, 0);
772         gfar_write(&priv->regs->igaddr1, 0);
773         gfar_write(&priv->regs->igaddr2, 0);
774         gfar_write(&priv->regs->igaddr3, 0);
775         gfar_write(&priv->regs->igaddr4, 0);
776         gfar_write(&priv->regs->igaddr5, 0);
777         gfar_write(&priv->regs->igaddr6, 0);
778         gfar_write(&priv->regs->igaddr7, 0);
779
780         gfar_write(&priv->regs->gaddr0, 0);
781         gfar_write(&priv->regs->gaddr1, 0);
782         gfar_write(&priv->regs->gaddr2, 0);
783         gfar_write(&priv->regs->gaddr3, 0);
784         gfar_write(&priv->regs->gaddr4, 0);
785         gfar_write(&priv->regs->gaddr5, 0);
786         gfar_write(&priv->regs->gaddr6, 0);
787         gfar_write(&priv->regs->gaddr7, 0);
788
789         /* Zero out the rmon mib registers if it has them */
790         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
791                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
792
793                 /* Mask off the CAM interrupts */
794                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
795                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
796         }
797
798         /* Initialize the max receive buffer length */
799         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
800
801         /* Initialize the Minimum Frame Length Register */
802         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
803 }
804
805
806 /* Halt the receive and transmit queues */
807 static void gfar_halt_nodisable(struct net_device *dev)
808 {
809         struct gfar_private *priv = netdev_priv(dev);
810         struct gfar __iomem *regs = priv->regs;
811         u32 tempval;
812
813         /* Mask all interrupts */
814         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
815
816         /* Clear all interrupts */
817         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
818
819         /* Stop the DMA, and wait for it to stop */
820         tempval = gfar_read(&priv->regs->dmactrl);
821         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
822             != (DMACTRL_GRS | DMACTRL_GTS)) {
823                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
824                 gfar_write(&priv->regs->dmactrl, tempval);
825
826                 while (!(gfar_read(&priv->regs->ievent) &
827                          (IEVENT_GRSC | IEVENT_GTSC)))
828                         cpu_relax();
829         }
830 }
831
832 /* Halt the receive and transmit queues */
833 void gfar_halt(struct net_device *dev)
834 {
835         struct gfar_private *priv = netdev_priv(dev);
836         struct gfar __iomem *regs = priv->regs;
837         u32 tempval;
838
839         gfar_halt_nodisable(dev);
840
841         /* Disable Rx and Tx */
842         tempval = gfar_read(&regs->maccfg1);
843         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
844         gfar_write(&regs->maccfg1, tempval);
845 }
846
847 void stop_gfar(struct net_device *dev)
848 {
849         struct gfar_private *priv = netdev_priv(dev);
850         struct gfar __iomem *regs = priv->regs;
851         unsigned long flags;
852
853         phy_stop(priv->phydev);
854
855         /* Lock it down */
856         spin_lock_irqsave(&priv->txlock, flags);
857         spin_lock(&priv->rxlock);
858
859         gfar_halt(dev);
860
861         spin_unlock(&priv->rxlock);
862         spin_unlock_irqrestore(&priv->txlock, flags);
863
864         /* Free the IRQs */
865         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
866                 free_irq(priv->interruptError, dev);
867                 free_irq(priv->interruptTransmit, dev);
868                 free_irq(priv->interruptReceive, dev);
869         } else {
870                 free_irq(priv->interruptTransmit, dev);
871         }
872
873         free_skb_resources(priv);
874
875         dma_free_coherent(&priv->ofdev->dev,
876                         sizeof(struct txbd8)*priv->tx_ring_size
877                         + sizeof(struct rxbd8)*priv->rx_ring_size,
878                         priv->tx_bd_base,
879                         gfar_read(&regs->tbase0));
880 }
881
882 /* If there are any tx skbs or rx skbs still around, free them.
883  * Then free tx_skbuff and rx_skbuff */
884 static void free_skb_resources(struct gfar_private *priv)
885 {
886         struct rxbd8 *rxbdp;
887         struct txbd8 *txbdp;
888         int i, j;
889
890         /* Go through all the buffer descriptors and free their data buffers */
891         txbdp = priv->tx_bd_base;
892
893         for (i = 0; i < priv->tx_ring_size; i++) {
894                 if (!priv->tx_skbuff[i])
895                         continue;
896
897                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
898                                 txbdp->length, DMA_TO_DEVICE);
899                 txbdp->lstatus = 0;
900                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
901                         txbdp++;
902                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
903                                         txbdp->length, DMA_TO_DEVICE);
904                 }
905                 txbdp++;
906                 dev_kfree_skb_any(priv->tx_skbuff[i]);
907                 priv->tx_skbuff[i] = NULL;
908         }
909
910         kfree(priv->tx_skbuff);
911
912         rxbdp = priv->rx_bd_base;
913
914         /* rx_skbuff is not guaranteed to be allocated, so only
915          * free it and its contents if it is allocated */
916         if(priv->rx_skbuff != NULL) {
917                 for (i = 0; i < priv->rx_ring_size; i++) {
918                         if (priv->rx_skbuff[i]) {
919                                 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
920                                                 priv->rx_buffer_size,
921                                                 DMA_FROM_DEVICE);
922
923                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
924                                 priv->rx_skbuff[i] = NULL;
925                         }
926
927                         rxbdp->lstatus = 0;
928                         rxbdp->bufPtr = 0;
929
930                         rxbdp++;
931                 }
932
933                 kfree(priv->rx_skbuff);
934         }
935 }
936
937 void gfar_start(struct net_device *dev)
938 {
939         struct gfar_private *priv = netdev_priv(dev);
940         struct gfar __iomem *regs = priv->regs;
941         u32 tempval;
942
943         /* Enable Rx and Tx in MACCFG1 */
944         tempval = gfar_read(&regs->maccfg1);
945         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
946         gfar_write(&regs->maccfg1, tempval);
947
948         /* Initialize DMACTRL to have WWR and WOP */
949         tempval = gfar_read(&priv->regs->dmactrl);
950         tempval |= DMACTRL_INIT_SETTINGS;
951         gfar_write(&priv->regs->dmactrl, tempval);
952
953         /* Make sure we aren't stopped */
954         tempval = gfar_read(&priv->regs->dmactrl);
955         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
956         gfar_write(&priv->regs->dmactrl, tempval);
957
958         /* Clear THLT/RHLT, so that the DMA starts polling now */
959         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
960         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
961
962         /* Unmask the interrupts we look for */
963         gfar_write(&regs->imask, IMASK_DEFAULT);
964
965         dev->trans_start = jiffies;
966 }
967
968 /* Bring the controller up and running */
969 int startup_gfar(struct net_device *dev)
970 {
971         struct txbd8 *txbdp;
972         struct rxbd8 *rxbdp;
973         dma_addr_t addr = 0;
974         unsigned long vaddr;
975         int i;
976         struct gfar_private *priv = netdev_priv(dev);
977         struct gfar __iomem *regs = priv->regs;
978         int err = 0;
979         u32 rctrl = 0;
980         u32 attrs = 0;
981
982         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
983
984         /* Allocate memory for the buffer descriptors */
985         vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
986                         sizeof (struct txbd8) * priv->tx_ring_size +
987                         sizeof (struct rxbd8) * priv->rx_ring_size,
988                         &addr, GFP_KERNEL);
989
990         if (vaddr == 0) {
991                 if (netif_msg_ifup(priv))
992                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
993                                         dev->name);
994                 return -ENOMEM;
995         }
996
997         priv->tx_bd_base = (struct txbd8 *) vaddr;
998
999         /* enet DMA only understands physical addresses */
1000         gfar_write(&regs->tbase0, addr);
1001
1002         /* Start the rx descriptor ring where the tx ring leaves off */
1003         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
1004         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
1005         priv->rx_bd_base = (struct rxbd8 *) vaddr;
1006         gfar_write(&regs->rbase0, addr);
1007
1008         /* Setup the skbuff rings */
1009         priv->tx_skbuff =
1010             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1011                                         priv->tx_ring_size, GFP_KERNEL);
1012
1013         if (NULL == priv->tx_skbuff) {
1014                 if (netif_msg_ifup(priv))
1015                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
1016                                         dev->name);
1017                 err = -ENOMEM;
1018                 goto tx_skb_fail;
1019         }
1020
1021         for (i = 0; i < priv->tx_ring_size; i++)
1022                 priv->tx_skbuff[i] = NULL;
1023
1024         priv->rx_skbuff =
1025             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1026                                         priv->rx_ring_size, GFP_KERNEL);
1027
1028         if (NULL == priv->rx_skbuff) {
1029                 if (netif_msg_ifup(priv))
1030                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1031                                         dev->name);
1032                 err = -ENOMEM;
1033                 goto rx_skb_fail;
1034         }
1035
1036         for (i = 0; i < priv->rx_ring_size; i++)
1037                 priv->rx_skbuff[i] = NULL;
1038
1039         /* Initialize some variables in our dev structure */
1040         priv->num_txbdfree = priv->tx_ring_size;
1041         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1042         priv->cur_rx = priv->rx_bd_base;
1043         priv->skb_curtx = priv->skb_dirtytx = 0;
1044         priv->skb_currx = 0;
1045
1046         /* Initialize Transmit Descriptor Ring */
1047         txbdp = priv->tx_bd_base;
1048         for (i = 0; i < priv->tx_ring_size; i++) {
1049                 txbdp->lstatus = 0;
1050                 txbdp->bufPtr = 0;
1051                 txbdp++;
1052         }
1053
1054         /* Set the last descriptor in the ring to indicate wrap */
1055         txbdp--;
1056         txbdp->status |= TXBD_WRAP;
1057
1058         rxbdp = priv->rx_bd_base;
1059         for (i = 0; i < priv->rx_ring_size; i++) {
1060                 struct sk_buff *skb;
1061
1062                 skb = gfar_new_skb(dev);
1063
1064                 if (!skb) {
1065                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1066                                         dev->name);
1067
1068                         goto err_rxalloc_fail;
1069                 }
1070
1071                 priv->rx_skbuff[i] = skb;
1072
1073                 gfar_new_rxbdp(dev, rxbdp, skb);
1074
1075                 rxbdp++;
1076         }
1077
1078         /* Set the last descriptor in the ring to wrap */
1079         rxbdp--;
1080         rxbdp->status |= RXBD_WRAP;
1081
1082         /* If the device has multiple interrupts, register for
1083          * them.  Otherwise, only register for the one */
1084         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1085                 /* Install our interrupt handlers for Error,
1086                  * Transmit, and Receive */
1087                 if (request_irq(priv->interruptError, gfar_error,
1088                                 0, priv->int_name_er, dev) < 0) {
1089                         if (netif_msg_intr(priv))
1090                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1091                                         dev->name, priv->interruptError);
1092
1093                         err = -1;
1094                         goto err_irq_fail;
1095                 }
1096
1097                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1098                                 0, priv->int_name_tx, dev) < 0) {
1099                         if (netif_msg_intr(priv))
1100                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1101                                         dev->name, priv->interruptTransmit);
1102
1103                         err = -1;
1104
1105                         goto tx_irq_fail;
1106                 }
1107
1108                 if (request_irq(priv->interruptReceive, gfar_receive,
1109                                 0, priv->int_name_rx, dev) < 0) {
1110                         if (netif_msg_intr(priv))
1111                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1112                                                 dev->name, priv->interruptReceive);
1113
1114                         err = -1;
1115                         goto rx_irq_fail;
1116                 }
1117         } else {
1118                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1119                                 0, priv->int_name_tx, dev) < 0) {
1120                         if (netif_msg_intr(priv))
1121                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1122                                         dev->name, priv->interruptTransmit);
1123
1124                         err = -1;
1125                         goto err_irq_fail;
1126                 }
1127         }
1128
1129         phy_start(priv->phydev);
1130
1131         /* Configure the coalescing support */
1132         gfar_write(&regs->txic, 0);
1133         if (priv->txcoalescing)
1134                 gfar_write(&regs->txic, priv->txic);
1135
1136         gfar_write(&regs->rxic, 0);
1137         if (priv->rxcoalescing)
1138                 gfar_write(&regs->rxic, priv->rxic);
1139
1140         if (priv->rx_csum_enable)
1141                 rctrl |= RCTRL_CHECKSUMMING;
1142
1143         if (priv->extended_hash) {
1144                 rctrl |= RCTRL_EXTHASH;
1145
1146                 gfar_clear_exact_match(dev);
1147                 rctrl |= RCTRL_EMEN;
1148         }
1149
1150         if (priv->padding) {
1151                 rctrl &= ~RCTRL_PAL_MASK;
1152                 rctrl |= RCTRL_PADDING(priv->padding);
1153         }
1154
1155         /* Init rctrl based on our settings */
1156         gfar_write(&priv->regs->rctrl, rctrl);
1157
1158         if (dev->features & NETIF_F_IP_CSUM)
1159                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1160
1161         /* Set the extraction length and index */
1162         attrs = ATTRELI_EL(priv->rx_stash_size) |
1163                 ATTRELI_EI(priv->rx_stash_index);
1164
1165         gfar_write(&priv->regs->attreli, attrs);
1166
1167         /* Start with defaults, and add stashing or locking
1168          * depending on the approprate variables */
1169         attrs = ATTR_INIT_SETTINGS;
1170
1171         if (priv->bd_stash_en)
1172                 attrs |= ATTR_BDSTASH;
1173
1174         if (priv->rx_stash_size != 0)
1175                 attrs |= ATTR_BUFSTASH;
1176
1177         gfar_write(&priv->regs->attr, attrs);
1178
1179         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1180         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1181         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1182
1183         /* Start the controller */
1184         gfar_start(dev);
1185
1186         return 0;
1187
1188 rx_irq_fail:
1189         free_irq(priv->interruptTransmit, dev);
1190 tx_irq_fail:
1191         free_irq(priv->interruptError, dev);
1192 err_irq_fail:
1193 err_rxalloc_fail:
1194 rx_skb_fail:
1195         free_skb_resources(priv);
1196 tx_skb_fail:
1197         dma_free_coherent(&priv->ofdev->dev,
1198                         sizeof(struct txbd8)*priv->tx_ring_size
1199                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1200                         priv->tx_bd_base,
1201                         gfar_read(&regs->tbase0));
1202
1203         return err;
1204 }
1205
1206 /* Called when something needs to use the ethernet device */
1207 /* Returns 0 for success. */
1208 static int gfar_enet_open(struct net_device *dev)
1209 {
1210         struct gfar_private *priv = netdev_priv(dev);
1211         int err;
1212
1213         napi_enable(&priv->napi);
1214
1215         skb_queue_head_init(&priv->rx_recycle);
1216
1217         /* Initialize a bunch of registers */
1218         init_registers(dev);
1219
1220         gfar_set_mac_address(dev);
1221
1222         err = init_phy(dev);
1223
1224         if(err) {
1225                 napi_disable(&priv->napi);
1226                 return err;
1227         }
1228
1229         err = startup_gfar(dev);
1230         if (err) {
1231                 napi_disable(&priv->napi);
1232                 return err;
1233         }
1234
1235         netif_start_queue(dev);
1236
1237         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1238
1239         return err;
1240 }
1241
1242 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1243 {
1244         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1245
1246         cacheable_memzero(fcb, GMAC_FCB_LEN);
1247
1248         return fcb;
1249 }
1250
1251 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1252 {
1253         u8 flags = 0;
1254
1255         /* If we're here, it's a IP packet with a TCP or UDP
1256          * payload.  We set it to checksum, using a pseudo-header
1257          * we provide
1258          */
1259         flags = TXFCB_DEFAULT;
1260
1261         /* Tell the controller what the protocol is */
1262         /* And provide the already calculated phcs */
1263         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1264                 flags |= TXFCB_UDP;
1265                 fcb->phcs = udp_hdr(skb)->check;
1266         } else
1267                 fcb->phcs = tcp_hdr(skb)->check;
1268
1269         /* l3os is the distance between the start of the
1270          * frame (skb->data) and the start of the IP hdr.
1271          * l4os is the distance between the start of the
1272          * l3 hdr and the l4 hdr */
1273         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1274         fcb->l4os = skb_network_header_len(skb);
1275
1276         fcb->flags = flags;
1277 }
1278
1279 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1280 {
1281         fcb->flags |= TXFCB_VLN;
1282         fcb->vlctl = vlan_tx_tag_get(skb);
1283 }
1284
1285 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1286                                struct txbd8 *base, int ring_size)
1287 {
1288         struct txbd8 *new_bd = bdp + stride;
1289
1290         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1291 }
1292
1293 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1294                 int ring_size)
1295 {
1296         return skip_txbd(bdp, 1, base, ring_size);
1297 }
1298
1299 /* This is called by the kernel when a frame is ready for transmission. */
1300 /* It is pointed to by the dev->hard_start_xmit function pointer */
1301 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1302 {
1303         struct gfar_private *priv = netdev_priv(dev);
1304         struct txfcb *fcb = NULL;
1305         struct txbd8 *txbdp, *txbdp_start, *base;
1306         u32 lstatus;
1307         int i;
1308         u32 bufaddr;
1309         unsigned long flags;
1310         unsigned int nr_frags, length;
1311
1312         base = priv->tx_bd_base;
1313
1314         /* total number of fragments in the SKB */
1315         nr_frags = skb_shinfo(skb)->nr_frags;
1316
1317         spin_lock_irqsave(&priv->txlock, flags);
1318
1319         /* check if there is space to queue this packet */
1320         if ((nr_frags+1) > priv->num_txbdfree) {
1321                 /* no space, stop the queue */
1322                 netif_stop_queue(dev);
1323                 dev->stats.tx_fifo_errors++;
1324                 spin_unlock_irqrestore(&priv->txlock, flags);
1325                 return NETDEV_TX_BUSY;
1326         }
1327
1328         /* Update transmit stats */
1329         dev->stats.tx_bytes += skb->len;
1330
1331         txbdp = txbdp_start = priv->cur_tx;
1332
1333         if (nr_frags == 0) {
1334                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1335         } else {
1336                 /* Place the fragment addresses and lengths into the TxBDs */
1337                 for (i = 0; i < nr_frags; i++) {
1338                         /* Point at the next BD, wrapping as needed */
1339                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1340
1341                         length = skb_shinfo(skb)->frags[i].size;
1342
1343                         lstatus = txbdp->lstatus | length |
1344                                 BD_LFLAG(TXBD_READY);
1345
1346                         /* Handle the last BD specially */
1347                         if (i == nr_frags - 1)
1348                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1349
1350                         bufaddr = dma_map_page(&priv->ofdev->dev,
1351                                         skb_shinfo(skb)->frags[i].page,
1352                                         skb_shinfo(skb)->frags[i].page_offset,
1353                                         length,
1354                                         DMA_TO_DEVICE);
1355
1356                         /* set the TxBD length and buffer pointer */
1357                         txbdp->bufPtr = bufaddr;
1358                         txbdp->lstatus = lstatus;
1359                 }
1360
1361                 lstatus = txbdp_start->lstatus;
1362         }
1363
1364         /* Set up checksumming */
1365         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1366                 fcb = gfar_add_fcb(skb);
1367                 lstatus |= BD_LFLAG(TXBD_TOE);
1368                 gfar_tx_checksum(skb, fcb);
1369         }
1370
1371         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1372                 if (unlikely(NULL == fcb)) {
1373                         fcb = gfar_add_fcb(skb);
1374                         lstatus |= BD_LFLAG(TXBD_TOE);
1375                 }
1376
1377                 gfar_tx_vlan(skb, fcb);
1378         }
1379
1380         /* setup the TxBD length and buffer pointer for the first BD */
1381         priv->tx_skbuff[priv->skb_curtx] = skb;
1382         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1383                         skb_headlen(skb), DMA_TO_DEVICE);
1384
1385         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1386
1387         /*
1388          * The powerpc-specific eieio() is used, as wmb() has too strong
1389          * semantics (it requires synchronization between cacheable and
1390          * uncacheable mappings, which eieio doesn't provide and which we
1391          * don't need), thus requiring a more expensive sync instruction.  At
1392          * some point, the set of architecture-independent barrier functions
1393          * should be expanded to include weaker barriers.
1394          */
1395         eieio();
1396
1397         txbdp_start->lstatus = lstatus;
1398
1399         /* Update the current skb pointer to the next entry we will use
1400          * (wrapping if necessary) */
1401         priv->skb_curtx = (priv->skb_curtx + 1) &
1402                 TX_RING_MOD_MASK(priv->tx_ring_size);
1403
1404         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1405
1406         /* reduce TxBD free count */
1407         priv->num_txbdfree -= (nr_frags + 1);
1408
1409         dev->trans_start = jiffies;
1410
1411         /* If the next BD still needs to be cleaned up, then the bds
1412            are full.  We need to tell the kernel to stop sending us stuff. */
1413         if (!priv->num_txbdfree) {
1414                 netif_stop_queue(dev);
1415
1416                 dev->stats.tx_fifo_errors++;
1417         }
1418
1419         /* Tell the DMA to go go go */
1420         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1421
1422         /* Unlock priv */
1423         spin_unlock_irqrestore(&priv->txlock, flags);
1424
1425         return 0;
1426 }
1427
1428 /* Stops the kernel queue, and halts the controller */
1429 static int gfar_close(struct net_device *dev)
1430 {
1431         struct gfar_private *priv = netdev_priv(dev);
1432
1433         napi_disable(&priv->napi);
1434
1435         skb_queue_purge(&priv->rx_recycle);
1436         cancel_work_sync(&priv->reset_task);
1437         stop_gfar(dev);
1438
1439         /* Disconnect from the PHY */
1440         phy_disconnect(priv->phydev);
1441         priv->phydev = NULL;
1442
1443         netif_stop_queue(dev);
1444
1445         return 0;
1446 }
1447
1448 /* Changes the mac address if the controller is not running. */
1449 static int gfar_set_mac_address(struct net_device *dev)
1450 {
1451         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1452
1453         return 0;
1454 }
1455
1456
1457 /* Enables and disables VLAN insertion/extraction */
1458 static void gfar_vlan_rx_register(struct net_device *dev,
1459                 struct vlan_group *grp)
1460 {
1461         struct gfar_private *priv = netdev_priv(dev);
1462         unsigned long flags;
1463         u32 tempval;
1464
1465         spin_lock_irqsave(&priv->rxlock, flags);
1466
1467         priv->vlgrp = grp;
1468
1469         if (grp) {
1470                 /* Enable VLAN tag insertion */
1471                 tempval = gfar_read(&priv->regs->tctrl);
1472                 tempval |= TCTRL_VLINS;
1473
1474                 gfar_write(&priv->regs->tctrl, tempval);
1475
1476                 /* Enable VLAN tag extraction */
1477                 tempval = gfar_read(&priv->regs->rctrl);
1478                 tempval |= RCTRL_VLEX;
1479                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1480                 gfar_write(&priv->regs->rctrl, tempval);
1481         } else {
1482                 /* Disable VLAN tag insertion */
1483                 tempval = gfar_read(&priv->regs->tctrl);
1484                 tempval &= ~TCTRL_VLINS;
1485                 gfar_write(&priv->regs->tctrl, tempval);
1486
1487                 /* Disable VLAN tag extraction */
1488                 tempval = gfar_read(&priv->regs->rctrl);
1489                 tempval &= ~RCTRL_VLEX;
1490                 /* If parse is no longer required, then disable parser */
1491                 if (tempval & RCTRL_REQ_PARSER)
1492                         tempval |= RCTRL_PRSDEP_INIT;
1493                 else
1494                         tempval &= ~RCTRL_PRSDEP_INIT;
1495                 gfar_write(&priv->regs->rctrl, tempval);
1496         }
1497
1498         gfar_change_mtu(dev, dev->mtu);
1499
1500         spin_unlock_irqrestore(&priv->rxlock, flags);
1501 }
1502
1503 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1504 {
1505         int tempsize, tempval;
1506         struct gfar_private *priv = netdev_priv(dev);
1507         int oldsize = priv->rx_buffer_size;
1508         int frame_size = new_mtu + ETH_HLEN;
1509
1510         if (priv->vlgrp)
1511                 frame_size += VLAN_HLEN;
1512
1513         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1514                 if (netif_msg_drv(priv))
1515                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1516                                         dev->name);
1517                 return -EINVAL;
1518         }
1519
1520         if (gfar_uses_fcb(priv))
1521                 frame_size += GMAC_FCB_LEN;
1522
1523         frame_size += priv->padding;
1524
1525         tempsize =
1526             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1527             INCREMENTAL_BUFFER_SIZE;
1528
1529         /* Only stop and start the controller if it isn't already
1530          * stopped, and we changed something */
1531         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1532                 stop_gfar(dev);
1533
1534         priv->rx_buffer_size = tempsize;
1535
1536         dev->mtu = new_mtu;
1537
1538         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1539         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1540
1541         /* If the mtu is larger than the max size for standard
1542          * ethernet frames (ie, a jumbo frame), then set maccfg2
1543          * to allow huge frames, and to check the length */
1544         tempval = gfar_read(&priv->regs->maccfg2);
1545
1546         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1547                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1548         else
1549                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1550
1551         gfar_write(&priv->regs->maccfg2, tempval);
1552
1553         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1554                 startup_gfar(dev);
1555
1556         return 0;
1557 }
1558
1559 /* gfar_reset_task gets scheduled when a packet has not been
1560  * transmitted after a set amount of time.
1561  * For now, assume that clearing out all the structures, and
1562  * starting over will fix the problem.
1563  */
1564 static void gfar_reset_task(struct work_struct *work)
1565 {
1566         struct gfar_private *priv = container_of(work, struct gfar_private,
1567                         reset_task);
1568         struct net_device *dev = priv->ndev;
1569
1570         if (dev->flags & IFF_UP) {
1571                 stop_gfar(dev);
1572                 startup_gfar(dev);
1573         }
1574
1575         netif_tx_schedule_all(dev);
1576 }
1577
1578 static void gfar_timeout(struct net_device *dev)
1579 {
1580         struct gfar_private *priv = netdev_priv(dev);
1581
1582         dev->stats.tx_errors++;
1583         schedule_work(&priv->reset_task);
1584 }
1585
1586 /* Interrupt Handler for Transmit complete */
1587 static int gfar_clean_tx_ring(struct net_device *dev)
1588 {
1589         struct gfar_private *priv = netdev_priv(dev);
1590         struct txbd8 *bdp;
1591         struct txbd8 *lbdp = NULL;
1592         struct txbd8 *base = priv->tx_bd_base;
1593         struct sk_buff *skb;
1594         int skb_dirtytx;
1595         int tx_ring_size = priv->tx_ring_size;
1596         int frags = 0;
1597         int i;
1598         int howmany = 0;
1599         u32 lstatus;
1600
1601         bdp = priv->dirty_tx;
1602         skb_dirtytx = priv->skb_dirtytx;
1603
1604         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1605                 frags = skb_shinfo(skb)->nr_frags;
1606                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1607
1608                 lstatus = lbdp->lstatus;
1609
1610                 /* Only clean completed frames */
1611                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1612                                 (lstatus & BD_LENGTH_MASK))
1613                         break;
1614
1615                 dma_unmap_single(&priv->ofdev->dev,
1616                                 bdp->bufPtr,
1617                                 bdp->length,
1618                                 DMA_TO_DEVICE);
1619
1620                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1621                 bdp = next_txbd(bdp, base, tx_ring_size);
1622
1623                 for (i = 0; i < frags; i++) {
1624                         dma_unmap_page(&priv->ofdev->dev,
1625                                         bdp->bufPtr,
1626                                         bdp->length,
1627                                         DMA_TO_DEVICE);
1628                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1629                         bdp = next_txbd(bdp, base, tx_ring_size);
1630                 }
1631
1632                 /*
1633                  * If there's room in the queue (limit it to rx_buffer_size)
1634                  * we add this skb back into the pool, if it's the right size
1635                  */
1636                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1637                                 skb_recycle_check(skb, priv->rx_buffer_size +
1638                                         RXBUF_ALIGNMENT))
1639                         __skb_queue_head(&priv->rx_recycle, skb);
1640                 else
1641                         dev_kfree_skb_any(skb);
1642
1643                 priv->tx_skbuff[skb_dirtytx] = NULL;
1644
1645                 skb_dirtytx = (skb_dirtytx + 1) &
1646                         TX_RING_MOD_MASK(tx_ring_size);
1647
1648                 howmany++;
1649                 priv->num_txbdfree += frags + 1;
1650         }
1651
1652         /* If we freed a buffer, we can restart transmission, if necessary */
1653         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1654                 netif_wake_queue(dev);
1655
1656         /* Update dirty indicators */
1657         priv->skb_dirtytx = skb_dirtytx;
1658         priv->dirty_tx = bdp;
1659
1660         dev->stats.tx_packets += howmany;
1661
1662         return howmany;
1663 }
1664
1665 static void gfar_schedule_cleanup(struct net_device *dev)
1666 {
1667         struct gfar_private *priv = netdev_priv(dev);
1668         unsigned long flags;
1669
1670         spin_lock_irqsave(&priv->txlock, flags);
1671         spin_lock(&priv->rxlock);
1672
1673         if (napi_schedule_prep(&priv->napi)) {
1674                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1675                 __napi_schedule(&priv->napi);
1676         } else {
1677                 /*
1678                  * Clear IEVENT, so interrupts aren't called again
1679                  * because of the packets that have already arrived.
1680                  */
1681                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1682         }
1683
1684         spin_unlock(&priv->rxlock);
1685         spin_unlock_irqrestore(&priv->txlock, flags);
1686 }
1687
1688 /* Interrupt Handler for Transmit complete */
1689 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1690 {
1691         gfar_schedule_cleanup((struct net_device *)dev_id);
1692         return IRQ_HANDLED;
1693 }
1694
1695 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1696                 struct sk_buff *skb)
1697 {
1698         struct gfar_private *priv = netdev_priv(dev);
1699         u32 lstatus;
1700
1701         bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1702                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1703
1704         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1705
1706         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1707                 lstatus |= BD_LFLAG(RXBD_WRAP);
1708
1709         eieio();
1710
1711         bdp->lstatus = lstatus;
1712 }
1713
1714
1715 struct sk_buff * gfar_new_skb(struct net_device *dev)
1716 {
1717         unsigned int alignamount;
1718         struct gfar_private *priv = netdev_priv(dev);
1719         struct sk_buff *skb = NULL;
1720
1721         skb = __skb_dequeue(&priv->rx_recycle);
1722         if (!skb)
1723                 skb = netdev_alloc_skb(dev,
1724                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1725
1726         if (!skb)
1727                 return NULL;
1728
1729         alignamount = RXBUF_ALIGNMENT -
1730                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1731
1732         /* We need the data buffer to be aligned properly.  We will reserve
1733          * as many bytes as needed to align the data properly
1734          */
1735         skb_reserve(skb, alignamount);
1736
1737         return skb;
1738 }
1739
1740 static inline void count_errors(unsigned short status, struct net_device *dev)
1741 {
1742         struct gfar_private *priv = netdev_priv(dev);
1743         struct net_device_stats *stats = &dev->stats;
1744         struct gfar_extra_stats *estats = &priv->extra_stats;
1745
1746         /* If the packet was truncated, none of the other errors
1747          * matter */
1748         if (status & RXBD_TRUNCATED) {
1749                 stats->rx_length_errors++;
1750
1751                 estats->rx_trunc++;
1752
1753                 return;
1754         }
1755         /* Count the errors, if there were any */
1756         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1757                 stats->rx_length_errors++;
1758
1759                 if (status & RXBD_LARGE)
1760                         estats->rx_large++;
1761                 else
1762                         estats->rx_short++;
1763         }
1764         if (status & RXBD_NONOCTET) {
1765                 stats->rx_frame_errors++;
1766                 estats->rx_nonoctet++;
1767         }
1768         if (status & RXBD_CRCERR) {
1769                 estats->rx_crcerr++;
1770                 stats->rx_crc_errors++;
1771         }
1772         if (status & RXBD_OVERRUN) {
1773                 estats->rx_overrun++;
1774                 stats->rx_crc_errors++;
1775         }
1776 }
1777
1778 irqreturn_t gfar_receive(int irq, void *dev_id)
1779 {
1780         gfar_schedule_cleanup((struct net_device *)dev_id);
1781         return IRQ_HANDLED;
1782 }
1783
1784 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1785 {
1786         /* If valid headers were found, and valid sums
1787          * were verified, then we tell the kernel that no
1788          * checksumming is necessary.  Otherwise, it is */
1789         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1790                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1791         else
1792                 skb->ip_summed = CHECKSUM_NONE;
1793 }
1794
1795
1796 /* gfar_process_frame() -- handle one incoming packet if skb
1797  * isn't NULL.  */
1798 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1799                               int amount_pull)
1800 {
1801         struct gfar_private *priv = netdev_priv(dev);
1802         struct rxfcb *fcb = NULL;
1803
1804         int ret;
1805
1806         /* fcb is at the beginning if exists */
1807         fcb = (struct rxfcb *)skb->data;
1808
1809         /* Remove the FCB from the skb */
1810         /* Remove the padded bytes, if there are any */
1811         if (amount_pull)
1812                 skb_pull(skb, amount_pull);
1813
1814         if (priv->rx_csum_enable)
1815                 gfar_rx_checksum(skb, fcb);
1816
1817         /* Tell the skb what kind of packet this is */
1818         skb->protocol = eth_type_trans(skb, dev);
1819
1820         /* Send the packet up the stack */
1821         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1822                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1823         else
1824                 ret = netif_receive_skb(skb);
1825
1826         if (NET_RX_DROP == ret)
1827                 priv->extra_stats.kernel_dropped++;
1828
1829         return 0;
1830 }
1831
1832 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1833  *   until the budget/quota has been reached. Returns the number
1834  *   of frames handled
1835  */
1836 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1837 {
1838         struct rxbd8 *bdp, *base;
1839         struct sk_buff *skb;
1840         int pkt_len;
1841         int amount_pull;
1842         int howmany = 0;
1843         struct gfar_private *priv = netdev_priv(dev);
1844
1845         /* Get the first full descriptor */
1846         bdp = priv->cur_rx;
1847         base = priv->rx_bd_base;
1848
1849         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1850                 priv->padding;
1851
1852         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1853                 struct sk_buff *newskb;
1854                 rmb();
1855
1856                 /* Add another skb for the future */
1857                 newskb = gfar_new_skb(dev);
1858
1859                 skb = priv->rx_skbuff[priv->skb_currx];
1860
1861                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1862                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1863
1864                 /* We drop the frame if we failed to allocate a new buffer */
1865                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1866                                  bdp->status & RXBD_ERR)) {
1867                         count_errors(bdp->status, dev);
1868
1869                         if (unlikely(!newskb))
1870                                 newskb = skb;
1871                         else if (skb)
1872                                 __skb_queue_head(&priv->rx_recycle, skb);
1873                 } else {
1874                         /* Increment the number of packets */
1875                         dev->stats.rx_packets++;
1876                         howmany++;
1877
1878                         if (likely(skb)) {
1879                                 pkt_len = bdp->length - ETH_FCS_LEN;
1880                                 /* Remove the FCS from the packet length */
1881                                 skb_put(skb, pkt_len);
1882                                 dev->stats.rx_bytes += pkt_len;
1883
1884                                 if (in_irq() || irqs_disabled())
1885                                         printk("Interrupt problem!\n");
1886                                 gfar_process_frame(dev, skb, amount_pull);
1887
1888                         } else {
1889                                 if (netif_msg_rx_err(priv))
1890                                         printk(KERN_WARNING
1891                                                "%s: Missing skb!\n", dev->name);
1892                                 dev->stats.rx_dropped++;
1893                                 priv->extra_stats.rx_skbmissing++;
1894                         }
1895
1896                 }
1897
1898                 priv->rx_skbuff[priv->skb_currx] = newskb;
1899
1900                 /* Setup the new bdp */
1901                 gfar_new_rxbdp(dev, bdp, newskb);
1902
1903                 /* Update to the next pointer */
1904                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1905
1906                 /* update to point at the next skb */
1907                 priv->skb_currx =
1908                     (priv->skb_currx + 1) &
1909                     RX_RING_MOD_MASK(priv->rx_ring_size);
1910         }
1911
1912         /* Update the current rxbd pointer to be the next one */
1913         priv->cur_rx = bdp;
1914
1915         return howmany;
1916 }
1917
1918 static int gfar_poll(struct napi_struct *napi, int budget)
1919 {
1920         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1921         struct net_device *dev = priv->ndev;
1922         int tx_cleaned = 0;
1923         int rx_cleaned = 0;
1924         unsigned long flags;
1925
1926         /* Clear IEVENT, so interrupts aren't called again
1927          * because of the packets that have already arrived */
1928         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1929
1930         /* If we fail to get the lock, don't bother with the TX BDs */
1931         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1932                 tx_cleaned = gfar_clean_tx_ring(dev);
1933                 spin_unlock_irqrestore(&priv->txlock, flags);
1934         }
1935
1936         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1937
1938         if (tx_cleaned)
1939                 return budget;
1940
1941         if (rx_cleaned < budget) {
1942                 napi_complete(napi);
1943
1944                 /* Clear the halt bit in RSTAT */
1945                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1946
1947                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1948
1949                 /* If we are coalescing interrupts, update the timer */
1950                 /* Otherwise, clear it */
1951                 if (likely(priv->rxcoalescing)) {
1952                         gfar_write(&priv->regs->rxic, 0);
1953                         gfar_write(&priv->regs->rxic, priv->rxic);
1954                 }
1955                 if (likely(priv->txcoalescing)) {
1956                         gfar_write(&priv->regs->txic, 0);
1957                         gfar_write(&priv->regs->txic, priv->txic);
1958                 }
1959         }
1960
1961         return rx_cleaned;
1962 }
1963
1964 #ifdef CONFIG_NET_POLL_CONTROLLER
1965 /*
1966  * Polling 'interrupt' - used by things like netconsole to send skbs
1967  * without having to re-enable interrupts. It's not called while
1968  * the interrupt routine is executing.
1969  */
1970 static void gfar_netpoll(struct net_device *dev)
1971 {
1972         struct gfar_private *priv = netdev_priv(dev);
1973
1974         /* If the device has multiple interrupts, run tx/rx */
1975         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1976                 disable_irq(priv->interruptTransmit);
1977                 disable_irq(priv->interruptReceive);
1978                 disable_irq(priv->interruptError);
1979                 gfar_interrupt(priv->interruptTransmit, dev);
1980                 enable_irq(priv->interruptError);
1981                 enable_irq(priv->interruptReceive);
1982                 enable_irq(priv->interruptTransmit);
1983         } else {
1984                 disable_irq(priv->interruptTransmit);
1985                 gfar_interrupt(priv->interruptTransmit, dev);
1986                 enable_irq(priv->interruptTransmit);
1987         }
1988 }
1989 #endif
1990
1991 /* The interrupt handler for devices with one interrupt */
1992 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1993 {
1994         struct net_device *dev = dev_id;
1995         struct gfar_private *priv = netdev_priv(dev);
1996
1997         /* Save ievent for future reference */
1998         u32 events = gfar_read(&priv->regs->ievent);
1999
2000         /* Check for reception */
2001         if (events & IEVENT_RX_MASK)
2002                 gfar_receive(irq, dev_id);
2003
2004         /* Check for transmit completion */
2005         if (events & IEVENT_TX_MASK)
2006                 gfar_transmit(irq, dev_id);
2007
2008         /* Check for errors */
2009         if (events & IEVENT_ERR_MASK)
2010                 gfar_error(irq, dev_id);
2011
2012         return IRQ_HANDLED;
2013 }
2014
2015 /* Called every time the controller might need to be made
2016  * aware of new link state.  The PHY code conveys this
2017  * information through variables in the phydev structure, and this
2018  * function converts those variables into the appropriate
2019  * register values, and can bring down the device if needed.
2020  */
2021 static void adjust_link(struct net_device *dev)
2022 {
2023         struct gfar_private *priv = netdev_priv(dev);
2024         struct gfar __iomem *regs = priv->regs;
2025         unsigned long flags;
2026         struct phy_device *phydev = priv->phydev;
2027         int new_state = 0;
2028
2029         spin_lock_irqsave(&priv->txlock, flags);
2030         if (phydev->link) {
2031                 u32 tempval = gfar_read(&regs->maccfg2);
2032                 u32 ecntrl = gfar_read(&regs->ecntrl);
2033
2034                 /* Now we make sure that we can be in full duplex mode.
2035                  * If not, we operate in half-duplex mode. */
2036                 if (phydev->duplex != priv->oldduplex) {
2037                         new_state = 1;
2038                         if (!(phydev->duplex))
2039                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2040                         else
2041                                 tempval |= MACCFG2_FULL_DUPLEX;
2042
2043                         priv->oldduplex = phydev->duplex;
2044                 }
2045
2046                 if (phydev->speed != priv->oldspeed) {
2047                         new_state = 1;
2048                         switch (phydev->speed) {
2049                         case 1000:
2050                                 tempval =
2051                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2052
2053                                 ecntrl &= ~(ECNTRL_R100);
2054                                 break;
2055                         case 100:
2056                         case 10:
2057                                 tempval =
2058                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2059
2060                                 /* Reduced mode distinguishes
2061                                  * between 10 and 100 */
2062                                 if (phydev->speed == SPEED_100)
2063                                         ecntrl |= ECNTRL_R100;
2064                                 else
2065                                         ecntrl &= ~(ECNTRL_R100);
2066                                 break;
2067                         default:
2068                                 if (netif_msg_link(priv))
2069                                         printk(KERN_WARNING
2070                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2071                                                 dev->name, phydev->speed);
2072                                 break;
2073                         }
2074
2075                         priv->oldspeed = phydev->speed;
2076                 }
2077
2078                 gfar_write(&regs->maccfg2, tempval);
2079                 gfar_write(&regs->ecntrl, ecntrl);
2080
2081                 if (!priv->oldlink) {
2082                         new_state = 1;
2083                         priv->oldlink = 1;
2084                 }
2085         } else if (priv->oldlink) {
2086                 new_state = 1;
2087                 priv->oldlink = 0;
2088                 priv->oldspeed = 0;
2089                 priv->oldduplex = -1;
2090         }
2091
2092         if (new_state && netif_msg_link(priv))
2093                 phy_print_status(phydev);
2094
2095         spin_unlock_irqrestore(&priv->txlock, flags);
2096 }
2097
2098 /* Update the hash table based on the current list of multicast
2099  * addresses we subscribe to.  Also, change the promiscuity of
2100  * the device based on the flags (this function is called
2101  * whenever dev->flags is changed */
2102 static void gfar_set_multi(struct net_device *dev)
2103 {
2104         struct dev_mc_list *mc_ptr;
2105         struct gfar_private *priv = netdev_priv(dev);
2106         struct gfar __iomem *regs = priv->regs;
2107         u32 tempval;
2108
2109         if(dev->flags & IFF_PROMISC) {
2110                 /* Set RCTRL to PROM */
2111                 tempval = gfar_read(&regs->rctrl);
2112                 tempval |= RCTRL_PROM;
2113                 gfar_write(&regs->rctrl, tempval);
2114         } else {
2115                 /* Set RCTRL to not PROM */
2116                 tempval = gfar_read(&regs->rctrl);
2117                 tempval &= ~(RCTRL_PROM);
2118                 gfar_write(&regs->rctrl, tempval);
2119         }
2120
2121         if(dev->flags & IFF_ALLMULTI) {
2122                 /* Set the hash to rx all multicast frames */
2123                 gfar_write(&regs->igaddr0, 0xffffffff);
2124                 gfar_write(&regs->igaddr1, 0xffffffff);
2125                 gfar_write(&regs->igaddr2, 0xffffffff);
2126                 gfar_write(&regs->igaddr3, 0xffffffff);
2127                 gfar_write(&regs->igaddr4, 0xffffffff);
2128                 gfar_write(&regs->igaddr5, 0xffffffff);
2129                 gfar_write(&regs->igaddr6, 0xffffffff);
2130                 gfar_write(&regs->igaddr7, 0xffffffff);
2131                 gfar_write(&regs->gaddr0, 0xffffffff);
2132                 gfar_write(&regs->gaddr1, 0xffffffff);
2133                 gfar_write(&regs->gaddr2, 0xffffffff);
2134                 gfar_write(&regs->gaddr3, 0xffffffff);
2135                 gfar_write(&regs->gaddr4, 0xffffffff);
2136                 gfar_write(&regs->gaddr5, 0xffffffff);
2137                 gfar_write(&regs->gaddr6, 0xffffffff);
2138                 gfar_write(&regs->gaddr7, 0xffffffff);
2139         } else {
2140                 int em_num;
2141                 int idx;
2142
2143                 /* zero out the hash */
2144                 gfar_write(&regs->igaddr0, 0x0);
2145                 gfar_write(&regs->igaddr1, 0x0);
2146                 gfar_write(&regs->igaddr2, 0x0);
2147                 gfar_write(&regs->igaddr3, 0x0);
2148                 gfar_write(&regs->igaddr4, 0x0);
2149                 gfar_write(&regs->igaddr5, 0x0);
2150                 gfar_write(&regs->igaddr6, 0x0);
2151                 gfar_write(&regs->igaddr7, 0x0);
2152                 gfar_write(&regs->gaddr0, 0x0);
2153                 gfar_write(&regs->gaddr1, 0x0);
2154                 gfar_write(&regs->gaddr2, 0x0);
2155                 gfar_write(&regs->gaddr3, 0x0);
2156                 gfar_write(&regs->gaddr4, 0x0);
2157                 gfar_write(&regs->gaddr5, 0x0);
2158                 gfar_write(&regs->gaddr6, 0x0);
2159                 gfar_write(&regs->gaddr7, 0x0);
2160
2161                 /* If we have extended hash tables, we need to
2162                  * clear the exact match registers to prepare for
2163                  * setting them */
2164                 if (priv->extended_hash) {
2165                         em_num = GFAR_EM_NUM + 1;
2166                         gfar_clear_exact_match(dev);
2167                         idx = 1;
2168                 } else {
2169                         idx = 0;
2170                         em_num = 0;
2171                 }
2172
2173                 if(dev->mc_count == 0)
2174                         return;
2175
2176                 /* Parse the list, and set the appropriate bits */
2177                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2178                         if (idx < em_num) {
2179                                 gfar_set_mac_for_addr(dev, idx,
2180                                                 mc_ptr->dmi_addr);
2181                                 idx++;
2182                         } else
2183                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2184                 }
2185         }
2186
2187         return;
2188 }
2189
2190
2191 /* Clears each of the exact match registers to zero, so they
2192  * don't interfere with normal reception */
2193 static void gfar_clear_exact_match(struct net_device *dev)
2194 {
2195         int idx;
2196         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2197
2198         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2199                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2200 }
2201
2202 /* Set the appropriate hash bit for the given addr */
2203 /* The algorithm works like so:
2204  * 1) Take the Destination Address (ie the multicast address), and
2205  * do a CRC on it (little endian), and reverse the bits of the
2206  * result.
2207  * 2) Use the 8 most significant bits as a hash into a 256-entry
2208  * table.  The table is controlled through 8 32-bit registers:
2209  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2210  * gaddr7.  This means that the 3 most significant bits in the
2211  * hash index which gaddr register to use, and the 5 other bits
2212  * indicate which bit (assuming an IBM numbering scheme, which
2213  * for PowerPC (tm) is usually the case) in the register holds
2214  * the entry. */
2215 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2216 {
2217         u32 tempval;
2218         struct gfar_private *priv = netdev_priv(dev);
2219         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2220         int width = priv->hash_width;
2221         u8 whichbit = (result >> (32 - width)) & 0x1f;
2222         u8 whichreg = result >> (32 - width + 5);
2223         u32 value = (1 << (31-whichbit));
2224
2225         tempval = gfar_read(priv->hash_regs[whichreg]);
2226         tempval |= value;
2227         gfar_write(priv->hash_regs[whichreg], tempval);
2228
2229         return;
2230 }
2231
2232
2233 /* There are multiple MAC Address register pairs on some controllers
2234  * This function sets the numth pair to a given address
2235  */
2236 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2237 {
2238         struct gfar_private *priv = netdev_priv(dev);
2239         int idx;
2240         char tmpbuf[MAC_ADDR_LEN];
2241         u32 tempval;
2242         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2243
2244         macptr += num*2;
2245
2246         /* Now copy it into the mac registers backwards, cuz */
2247         /* little endian is silly */
2248         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2249                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2250
2251         gfar_write(macptr, *((u32 *) (tmpbuf)));
2252
2253         tempval = *((u32 *) (tmpbuf + 4));
2254
2255         gfar_write(macptr+1, tempval);
2256 }
2257
2258 /* GFAR error interrupt handler */
2259 static irqreturn_t gfar_error(int irq, void *dev_id)
2260 {
2261         struct net_device *dev = dev_id;
2262         struct gfar_private *priv = netdev_priv(dev);
2263
2264         /* Save ievent for future reference */
2265         u32 events = gfar_read(&priv->regs->ievent);
2266
2267         /* Clear IEVENT */
2268         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2269
2270         /* Magic Packet is not an error. */
2271         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2272             (events & IEVENT_MAG))
2273                 events &= ~IEVENT_MAG;
2274
2275         /* Hmm... */
2276         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2277                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2278                        dev->name, events, gfar_read(&priv->regs->imask));
2279
2280         /* Update the error counters */
2281         if (events & IEVENT_TXE) {
2282                 dev->stats.tx_errors++;
2283
2284                 if (events & IEVENT_LC)
2285                         dev->stats.tx_window_errors++;
2286                 if (events & IEVENT_CRL)
2287                         dev->stats.tx_aborted_errors++;
2288                 if (events & IEVENT_XFUN) {
2289                         if (netif_msg_tx_err(priv))
2290                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2291                                        "packet dropped.\n", dev->name);
2292                         dev->stats.tx_dropped++;
2293                         priv->extra_stats.tx_underrun++;
2294
2295                         /* Reactivate the Tx Queues */
2296                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2297                 }
2298                 if (netif_msg_tx_err(priv))
2299                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2300         }
2301         if (events & IEVENT_BSY) {
2302                 dev->stats.rx_errors++;
2303                 priv->extra_stats.rx_bsy++;
2304
2305                 gfar_receive(irq, dev_id);
2306
2307                 if (netif_msg_rx_err(priv))
2308                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2309                                dev->name, gfar_read(&priv->regs->rstat));
2310         }
2311         if (events & IEVENT_BABR) {
2312                 dev->stats.rx_errors++;
2313                 priv->extra_stats.rx_babr++;
2314
2315                 if (netif_msg_rx_err(priv))
2316                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2317         }
2318         if (events & IEVENT_EBERR) {
2319                 priv->extra_stats.eberr++;
2320                 if (netif_msg_rx_err(priv))
2321                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2322         }
2323         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2324                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2325
2326         if (events & IEVENT_BABT) {
2327                 priv->extra_stats.tx_babt++;
2328                 if (netif_msg_tx_err(priv))
2329                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2330         }
2331         return IRQ_HANDLED;
2332 }
2333
2334 /* work with hotplug and coldplug */
2335 MODULE_ALIAS("platform:fsl-gianfar");
2336
2337 static struct of_device_id gfar_match[] =
2338 {
2339         {
2340                 .type = "network",
2341                 .compatible = "gianfar",
2342         },
2343         {},
2344 };
2345
2346 /* Structure for a device driver */
2347 static struct of_platform_driver gfar_driver = {
2348         .name = "fsl-gianfar",
2349         .match_table = gfar_match,
2350
2351         .probe = gfar_probe,
2352         .remove = gfar_remove,
2353         .suspend = gfar_suspend,
2354         .resume = gfar_resume,
2355 };
2356
2357 static int __init gfar_init(void)
2358 {
2359         return of_register_platform_driver(&gfar_driver);
2360 }
2361
2362 static void __exit gfar_exit(void)
2363 {
2364         of_unregister_platform_driver(&gfar_driver);
2365 }
2366
2367 module_init(gfar_init);
2368 module_exit(gfar_exit);
2369