gianfar: Fix compiler and sparse warnings
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12  *
13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
14  * Copyright 2007 MontaVista Software, Inc.
15  *
16  * This program is free software; you can redistribute  it and/or modify it
17  * under  the terms of  the GNU General  Public License as published by the
18  * Free Software Foundation;  either version 2 of the  License, or (at your
19  * option) any later version.
20  *
21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
22  *  RA 11 31 24.2
23  *  Dec +69 19 52
24  *  V 3.84
25  *  B-V +1.62
26  *
27  *  Theory of operation
28  *
29  *  The driver is initialized through of_device. Configuration information
30  *  is therefore conveyed through an OF-style device tree.
31  *
32  *  The Gianfar Ethernet Controller uses a ring of buffer
33  *  descriptors.  The beginning is indicated by a register
34  *  pointing to the physical address of the start of the ring.
35  *  The end is determined by a "wrap" bit being set in the
36  *  last descriptor of the ring.
37  *
38  *  When a packet is received, the RXF bit in the
39  *  IEVENT register is set, triggering an interrupt when the
40  *  corresponding bit in the IMASK register is also set (if
41  *  interrupt coalescing is active, then the interrupt may not
42  *  happen immediately, but will wait until either a set number
43  *  of frames or amount of time have passed).  In NAPI, the
44  *  interrupt handler will signal there is work to be done, and
45  *  exit. This method will start at the last known empty
46  *  descriptor, and process every subsequent descriptor until there
47  *  are none left with data (NAPI will stop after a set number of
48  *  packets to give time to other tasks, but will eventually
49  *  process all the packets).  The data arrives inside a
50  *  pre-allocated skb, and so after the skb is passed up to the
51  *  stack, a new skb must be allocated, and the address field in
52  *  the buffer descriptor must be updated to indicate this new
53  *  skb.
54  *
55  *  When the kernel requests that a packet be transmitted, the
56  *  driver starts where it left off last time, and points the
57  *  descriptor at the buffer which was passed in.  The driver
58  *  then informs the DMA engine that there are packets ready to
59  *  be transmitted.  Once the controller is finished transmitting
60  *  the packet, an interrupt may be triggered (under the same
61  *  conditions as for reception, but depending on the TXF bit).
62  *  The driver then cleans up the buffer.
63  */
64
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
78 #include <linux/mm.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
81 #include <linux/ip.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
84 #include <linux/in.h>
85
86 #include <asm/io.h>
87 #include <asm/irq.h>
88 #include <asm/uaccess.h>
89 #include <linux/module.h>
90 #include <linux/dma-mapping.h>
91 #include <linux/crc32.h>
92 #include <linux/mii.h>
93 #include <linux/phy.h>
94 #include <linux/phy_fixed.h>
95 #include <linux/of.h>
96
97 #include "gianfar.h"
98 #include "fsl_pq_mdio.h"
99
100 #define TX_TIMEOUT      (1*HZ)
101 #undef BRIEF_GFAR_ERRORS
102 #undef VERBOSE_GFAR_ERRORS
103
104 const char gfar_driver_name[] = "Gianfar Ethernet";
105 const char gfar_driver_version[] = "1.3";
106
107 static int gfar_enet_open(struct net_device *dev);
108 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
109 static void gfar_reset_task(struct work_struct *work);
110 static void gfar_timeout(struct net_device *dev);
111 static int gfar_close(struct net_device *dev);
112 struct sk_buff *gfar_new_skb(struct net_device *dev);
113 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
114                 struct sk_buff *skb);
115 static int gfar_set_mac_address(struct net_device *dev);
116 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
117 static irqreturn_t gfar_error(int irq, void *dev_id);
118 static irqreturn_t gfar_transmit(int irq, void *dev_id);
119 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
120 static void adjust_link(struct net_device *dev);
121 static void init_registers(struct net_device *dev);
122 static int init_phy(struct net_device *dev);
123 static int gfar_probe(struct of_device *ofdev,
124                 const struct of_device_id *match);
125 static int gfar_remove(struct of_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
133 #endif
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137                               int amount_pull);
138 static void gfar_vlan_rx_register(struct net_device *netdev,
139                                 struct vlan_group *grp);
140 void gfar_halt(struct net_device *dev);
141 static void gfar_halt_nodisable(struct net_device *dev);
142 void gfar_start(struct net_device *dev);
143 static void gfar_clear_exact_match(struct net_device *dev);
144 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
145 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);
147
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
151
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
153                             dma_addr_t buf)
154 {
155         u32 lstatus;
156
157         bdp->bufPtr = buf;
158
159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
161                 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163         eieio();
164
165         bdp->lstatus = lstatus;
166 }
167
168 static int gfar_init_bds(struct net_device *ndev)
169 {
170         struct gfar_private *priv = netdev_priv(ndev);
171         struct gfar_priv_tx_q *tx_queue = NULL;
172         struct gfar_priv_rx_q *rx_queue = NULL;
173         struct txbd8 *txbdp;
174         struct rxbd8 *rxbdp;
175         int i, j;
176
177         for (i = 0; i < priv->num_tx_queues; i++) {
178                 tx_queue = priv->tx_queue[i];
179                 /* Initialize some variables in our dev structure */
180                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182                 tx_queue->cur_tx = tx_queue->tx_bd_base;
183                 tx_queue->skb_curtx = 0;
184                 tx_queue->skb_dirtytx = 0;
185
186                 /* Initialize Transmit Descriptor Ring */
187                 txbdp = tx_queue->tx_bd_base;
188                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189                         txbdp->lstatus = 0;
190                         txbdp->bufPtr = 0;
191                         txbdp++;
192                 }
193
194                 /* Set the last descriptor in the ring to indicate wrap */
195                 txbdp--;
196                 txbdp->status |= TXBD_WRAP;
197         }
198
199         for (i = 0; i < priv->num_rx_queues; i++) {
200                 rx_queue = priv->rx_queue[i];
201                 rx_queue->cur_rx = rx_queue->rx_bd_base;
202                 rx_queue->skb_currx = 0;
203                 rxbdp = rx_queue->rx_bd_base;
204
205                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
207
208                         if (skb) {
209                                 gfar_init_rxbdp(rx_queue, rxbdp,
210                                                 rxbdp->bufPtr);
211                         } else {
212                                 skb = gfar_new_skb(ndev);
213                                 if (!skb) {
214                                         pr_err("%s: Can't allocate RX buffers\n",
215                                                         ndev->name);
216                                         goto err_rxalloc_fail;
217                                 }
218                                 rx_queue->rx_skbuff[j] = skb;
219
220                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
221                         }
222
223                         rxbdp++;
224                 }
225
226         }
227
228         return 0;
229
230 err_rxalloc_fail:
231         free_skb_resources(priv);
232         return -ENOMEM;
233 }
234
235 static int gfar_alloc_skb_resources(struct net_device *ndev)
236 {
237         void *vaddr;
238         dma_addr_t addr;
239         int i, j, k;
240         struct gfar_private *priv = netdev_priv(ndev);
241         struct device *dev = &priv->ofdev->dev;
242         struct gfar_priv_tx_q *tx_queue = NULL;
243         struct gfar_priv_rx_q *rx_queue = NULL;
244
245         priv->total_tx_ring_size = 0;
246         for (i = 0; i < priv->num_tx_queues; i++)
247                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
248
249         priv->total_rx_ring_size = 0;
250         for (i = 0; i < priv->num_rx_queues; i++)
251                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
252
253         /* Allocate memory for the buffer descriptors */
254         vaddr = dma_alloc_coherent(dev,
255                         sizeof(struct txbd8) * priv->total_tx_ring_size +
256                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
257                         &addr, GFP_KERNEL);
258         if (!vaddr) {
259                 if (netif_msg_ifup(priv))
260                         pr_err("%s: Could not allocate buffer descriptors!\n",
261                                ndev->name);
262                 return -ENOMEM;
263         }
264
265         for (i = 0; i < priv->num_tx_queues; i++) {
266                 tx_queue = priv->tx_queue[i];
267                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
268                 tx_queue->tx_bd_dma_base = addr;
269                 tx_queue->dev = ndev;
270                 /* enet DMA only understands physical addresses */
271                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273         }
274
275         /* Start the rx descriptor ring where the tx ring leaves off */
276         for (i = 0; i < priv->num_rx_queues; i++) {
277                 rx_queue = priv->rx_queue[i];
278                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
279                 rx_queue->rx_bd_dma_base = addr;
280                 rx_queue->dev = ndev;
281                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283         }
284
285         /* Setup the skbuff rings */
286         for (i = 0; i < priv->num_tx_queues; i++) {
287                 tx_queue = priv->tx_queue[i];
288                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
289                                   tx_queue->tx_ring_size, GFP_KERNEL);
290                 if (!tx_queue->tx_skbuff) {
291                         if (netif_msg_ifup(priv))
292                                 pr_err("%s: Could not allocate tx_skbuff\n",
293                                                 ndev->name);
294                         goto cleanup;
295                 }
296
297                 for (k = 0; k < tx_queue->tx_ring_size; k++)
298                         tx_queue->tx_skbuff[k] = NULL;
299         }
300
301         for (i = 0; i < priv->num_rx_queues; i++) {
302                 rx_queue = priv->rx_queue[i];
303                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
304                                   rx_queue->rx_ring_size, GFP_KERNEL);
305
306                 if (!rx_queue->rx_skbuff) {
307                         if (netif_msg_ifup(priv))
308                                 pr_err("%s: Could not allocate rx_skbuff\n",
309                                        ndev->name);
310                         goto cleanup;
311                 }
312
313                 for (j = 0; j < rx_queue->rx_ring_size; j++)
314                         rx_queue->rx_skbuff[j] = NULL;
315         }
316
317         if (gfar_init_bds(ndev))
318                 goto cleanup;
319
320         return 0;
321
322 cleanup:
323         free_skb_resources(priv);
324         return -ENOMEM;
325 }
326
327 static void gfar_init_tx_rx_base(struct gfar_private *priv)
328 {
329         struct gfar __iomem *regs = priv->gfargrp[0].regs;
330         u32 __iomem *baddr;
331         int i;
332
333         baddr = &regs->tbase0;
334         for(i = 0; i < priv->num_tx_queues; i++) {
335                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336                 baddr   += 2;
337         }
338
339         baddr = &regs->rbase0;
340         for(i = 0; i < priv->num_rx_queues; i++) {
341                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342                 baddr   += 2;
343         }
344 }
345
346 static void gfar_init_mac(struct net_device *ndev)
347 {
348         struct gfar_private *priv = netdev_priv(ndev);
349         struct gfar __iomem *regs = priv->gfargrp[0].regs;
350         u32 rctrl = 0;
351         u32 tctrl = 0;
352         u32 attrs = 0;
353
354         /* write the tx/rx base registers */
355         gfar_init_tx_rx_base(priv);
356
357         /* Configure the coalescing support */
358         gfar_configure_coalescing(priv, 0xFF, 0xFF);
359
360         if (priv->rx_filer_enable)
361                 rctrl |= RCTRL_FILREN;
362
363         if (priv->rx_csum_enable)
364                 rctrl |= RCTRL_CHECKSUMMING;
365
366         if (priv->extended_hash) {
367                 rctrl |= RCTRL_EXTHASH;
368
369                 gfar_clear_exact_match(ndev);
370                 rctrl |= RCTRL_EMEN;
371         }
372
373         if (priv->padding) {
374                 rctrl &= ~RCTRL_PAL_MASK;
375                 rctrl |= RCTRL_PADDING(priv->padding);
376         }
377
378         /* keep vlan related bits if it's enabled */
379         if (priv->vlgrp) {
380                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
381                 tctrl |= TCTRL_VLINS;
382         }
383
384         /* Init rctrl based on our settings */
385         gfar_write(&regs->rctrl, rctrl);
386
387         if (ndev->features & NETIF_F_IP_CSUM)
388                 tctrl |= TCTRL_INIT_CSUM;
389
390         tctrl |= TCTRL_TXSCHED_PRIO;
391
392         gfar_write(&regs->tctrl, tctrl);
393
394         /* Set the extraction length and index */
395         attrs = ATTRELI_EL(priv->rx_stash_size) |
396                 ATTRELI_EI(priv->rx_stash_index);
397
398         gfar_write(&regs->attreli, attrs);
399
400         /* Start with defaults, and add stashing or locking
401          * depending on the approprate variables */
402         attrs = ATTR_INIT_SETTINGS;
403
404         if (priv->bd_stash_en)
405                 attrs |= ATTR_BDSTASH;
406
407         if (priv->rx_stash_size != 0)
408                 attrs |= ATTR_BUFSTASH;
409
410         gfar_write(&regs->attr, attrs);
411
412         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
413         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
414         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
415 }
416
417 static const struct net_device_ops gfar_netdev_ops = {
418         .ndo_open = gfar_enet_open,
419         .ndo_start_xmit = gfar_start_xmit,
420         .ndo_stop = gfar_close,
421         .ndo_change_mtu = gfar_change_mtu,
422         .ndo_set_multicast_list = gfar_set_multi,
423         .ndo_tx_timeout = gfar_timeout,
424         .ndo_do_ioctl = gfar_ioctl,
425         .ndo_select_queue = gfar_select_queue,
426         .ndo_vlan_rx_register = gfar_vlan_rx_register,
427         .ndo_set_mac_address = eth_mac_addr,
428         .ndo_validate_addr = eth_validate_addr,
429 #ifdef CONFIG_NET_POLL_CONTROLLER
430         .ndo_poll_controller = gfar_netpoll,
431 #endif
432 };
433
434 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
435 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
436
437 void lock_rx_qs(struct gfar_private *priv)
438 {
439         int i = 0x0;
440
441         for (i = 0; i < priv->num_rx_queues; i++)
442                 spin_lock(&priv->rx_queue[i]->rxlock);
443 }
444
445 void lock_tx_qs(struct gfar_private *priv)
446 {
447         int i = 0x0;
448
449         for (i = 0; i < priv->num_tx_queues; i++)
450                 spin_lock(&priv->tx_queue[i]->txlock);
451 }
452
453 void unlock_rx_qs(struct gfar_private *priv)
454 {
455         int i = 0x0;
456
457         for (i = 0; i < priv->num_rx_queues; i++)
458                 spin_unlock(&priv->rx_queue[i]->rxlock);
459 }
460
461 void unlock_tx_qs(struct gfar_private *priv)
462 {
463         int i = 0x0;
464
465         for (i = 0; i < priv->num_tx_queues; i++)
466                 spin_unlock(&priv->tx_queue[i]->txlock);
467 }
468
469 /* Returns 1 if incoming frames use an FCB */
470 static inline int gfar_uses_fcb(struct gfar_private *priv)
471 {
472         return priv->vlgrp || priv->rx_csum_enable;
473 }
474
475 u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)
476 {
477         return skb_get_queue_mapping(skb);
478 }
479 static void free_tx_pointers(struct gfar_private *priv)
480 {
481         int i = 0;
482
483         for (i = 0; i < priv->num_tx_queues; i++)
484                 kfree(priv->tx_queue[i]);
485 }
486
487 static void free_rx_pointers(struct gfar_private *priv)
488 {
489         int i = 0;
490
491         for (i = 0; i < priv->num_rx_queues; i++)
492                 kfree(priv->rx_queue[i]);
493 }
494
495 static void unmap_group_regs(struct gfar_private *priv)
496 {
497         int i = 0;
498
499         for (i = 0; i < MAXGROUPS; i++)
500                 if (priv->gfargrp[i].regs)
501                         iounmap(priv->gfargrp[i].regs);
502 }
503
504 static void disable_napi(struct gfar_private *priv)
505 {
506         int i = 0;
507
508         for (i = 0; i < priv->num_grps; i++)
509                 napi_disable(&priv->gfargrp[i].napi);
510 }
511
512 static void enable_napi(struct gfar_private *priv)
513 {
514         int i = 0;
515
516         for (i = 0; i < priv->num_grps; i++)
517                 napi_enable(&priv->gfargrp[i].napi);
518 }
519
520 static int gfar_parse_group(struct device_node *np,
521                 struct gfar_private *priv, const char *model)
522 {
523         u32 *queue_mask;
524         u64 addr, size;
525
526         addr = of_translate_address(np,
527                         of_get_address(np, 0, &size, NULL));
528         priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);
529
530         if (!priv->gfargrp[priv->num_grps].regs)
531                 return -ENOMEM;
532
533         priv->gfargrp[priv->num_grps].interruptTransmit =
534                         irq_of_parse_and_map(np, 0);
535
536         /* If we aren't the FEC we have multiple interrupts */
537         if (model && strcasecmp(model, "FEC")) {
538                 priv->gfargrp[priv->num_grps].interruptReceive =
539                         irq_of_parse_and_map(np, 1);
540                 priv->gfargrp[priv->num_grps].interruptError =
541                         irq_of_parse_and_map(np,2);
542                 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
543                         priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
544                         priv->gfargrp[priv->num_grps].interruptError < 0) {
545                         return -EINVAL;
546                 }
547         }
548
549         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
550         priv->gfargrp[priv->num_grps].priv = priv;
551         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
552         if(priv->mode == MQ_MG_MODE) {
553                 queue_mask = (u32 *)of_get_property(np,
554                                         "fsl,rx-bit-map", NULL);
555                 priv->gfargrp[priv->num_grps].rx_bit_map =
556                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
557                 queue_mask = (u32 *)of_get_property(np,
558                                         "fsl,tx-bit-map", NULL);
559                 priv->gfargrp[priv->num_grps].tx_bit_map =
560                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
561         } else {
562                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
563                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
564         }
565         priv->num_grps++;
566
567         return 0;
568 }
569
570 static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
571 {
572         const char *model;
573         const char *ctype;
574         const void *mac_addr;
575         int err = 0, i;
576         struct net_device *dev = NULL;
577         struct gfar_private *priv = NULL;
578         struct device_node *np = ofdev->node;
579         struct device_node *child = NULL;
580         const u32 *stash;
581         const u32 *stash_len;
582         const u32 *stash_idx;
583         unsigned int num_tx_qs, num_rx_qs;
584         u32 *tx_queues, *rx_queues;
585
586         if (!np || !of_device_is_available(np))
587                 return -ENODEV;
588
589         /* parse the num of tx and rx queues */
590         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
591         num_tx_qs = tx_queues ? *tx_queues : 1;
592
593         if (num_tx_qs > MAX_TX_QS) {
594                 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
595                                 num_tx_qs, MAX_TX_QS);
596                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
597                 return -EINVAL;
598         }
599
600         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
601         num_rx_qs = rx_queues ? *rx_queues : 1;
602
603         if (num_rx_qs > MAX_RX_QS) {
604                 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
605                                 num_tx_qs, MAX_TX_QS);
606                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
607                 return -EINVAL;
608         }
609
610         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
611         dev = *pdev;
612         if (NULL == dev)
613                 return -ENOMEM;
614
615         priv = netdev_priv(dev);
616         priv->node = ofdev->node;
617         priv->ndev = dev;
618
619         dev->num_tx_queues = num_tx_qs;
620         dev->real_num_tx_queues = num_tx_qs;
621         priv->num_tx_queues = num_tx_qs;
622         priv->num_rx_queues = num_rx_qs;
623         priv->num_grps = 0x0;
624
625         model = of_get_property(np, "model", NULL);
626
627         for (i = 0; i < MAXGROUPS; i++)
628                 priv->gfargrp[i].regs = NULL;
629
630         /* Parse and initialize group specific information */
631         if (of_device_is_compatible(np, "fsl,etsec2")) {
632                 priv->mode = MQ_MG_MODE;
633                 for_each_child_of_node(np, child) {
634                         err = gfar_parse_group(child, priv, model);
635                         if (err)
636                                 goto err_grp_init;
637                 }
638         } else {
639                 priv->mode = SQ_SG_MODE;
640                 err = gfar_parse_group(np, priv, model);
641                 if(err)
642                         goto err_grp_init;
643         }
644
645         for (i = 0; i < priv->num_tx_queues; i++)
646                priv->tx_queue[i] = NULL;
647         for (i = 0; i < priv->num_rx_queues; i++)
648                 priv->rx_queue[i] = NULL;
649
650         for (i = 0; i < priv->num_tx_queues; i++) {
651                 priv->tx_queue[i] =  (struct gfar_priv_tx_q *)kmalloc(
652                                 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
653                 if (!priv->tx_queue[i]) {
654                         err = -ENOMEM;
655                         goto tx_alloc_failed;
656                 }
657                 priv->tx_queue[i]->tx_skbuff = NULL;
658                 priv->tx_queue[i]->qindex = i;
659                 priv->tx_queue[i]->dev = dev;
660                 spin_lock_init(&(priv->tx_queue[i]->txlock));
661         }
662
663         for (i = 0; i < priv->num_rx_queues; i++) {
664                 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(
665                                         sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
666                 if (!priv->rx_queue[i]) {
667                         err = -ENOMEM;
668                         goto rx_alloc_failed;
669                 }
670                 priv->rx_queue[i]->rx_skbuff = NULL;
671                 priv->rx_queue[i]->qindex = i;
672                 priv->rx_queue[i]->dev = dev;
673                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
674         }
675
676
677         stash = of_get_property(np, "bd-stash", NULL);
678
679         if (stash) {
680                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
681                 priv->bd_stash_en = 1;
682         }
683
684         stash_len = of_get_property(np, "rx-stash-len", NULL);
685
686         if (stash_len)
687                 priv->rx_stash_size = *stash_len;
688
689         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
690
691         if (stash_idx)
692                 priv->rx_stash_index = *stash_idx;
693
694         if (stash_len || stash_idx)
695                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
696
697         mac_addr = of_get_mac_address(np);
698         if (mac_addr)
699                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
700
701         if (model && !strcasecmp(model, "TSEC"))
702                 priv->device_flags =
703                         FSL_GIANFAR_DEV_HAS_GIGABIT |
704                         FSL_GIANFAR_DEV_HAS_COALESCE |
705                         FSL_GIANFAR_DEV_HAS_RMON |
706                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
707         if (model && !strcasecmp(model, "eTSEC"))
708                 priv->device_flags =
709                         FSL_GIANFAR_DEV_HAS_GIGABIT |
710                         FSL_GIANFAR_DEV_HAS_COALESCE |
711                         FSL_GIANFAR_DEV_HAS_RMON |
712                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
713                         FSL_GIANFAR_DEV_HAS_PADDING |
714                         FSL_GIANFAR_DEV_HAS_CSUM |
715                         FSL_GIANFAR_DEV_HAS_VLAN |
716                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
717                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
718
719         ctype = of_get_property(np, "phy-connection-type", NULL);
720
721         /* We only care about rgmii-id.  The rest are autodetected */
722         if (ctype && !strcmp(ctype, "rgmii-id"))
723                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
724         else
725                 priv->interface = PHY_INTERFACE_MODE_MII;
726
727         if (of_get_property(np, "fsl,magic-packet", NULL))
728                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
729
730         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
731
732         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
733         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
734
735         return 0;
736
737 rx_alloc_failed:
738         free_rx_pointers(priv);
739 tx_alloc_failed:
740         free_tx_pointers(priv);
741 err_grp_init:
742         unmap_group_regs(priv);
743         free_netdev(dev);
744         return err;
745 }
746
747 /* Ioctl MII Interface */
748 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
749 {
750         struct gfar_private *priv = netdev_priv(dev);
751
752         if (!netif_running(dev))
753                 return -EINVAL;
754
755         if (!priv->phydev)
756                 return -ENODEV;
757
758         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
759 }
760
761 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
762 {
763         unsigned int new_bit_map = 0x0;
764         int mask = 0x1 << (max_qs - 1), i;
765         for (i = 0; i < max_qs; i++) {
766                 if (bit_map & mask)
767                         new_bit_map = new_bit_map + (1 << i);
768                 mask = mask >> 0x1;
769         }
770         return new_bit_map;
771 }
772
773 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
774                                    u32 class)
775 {
776         u32 rqfpr = FPR_FILER_MASK;
777         u32 rqfcr = 0x0;
778
779         rqfar--;
780         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
781         ftp_rqfpr[rqfar] = rqfpr;
782         ftp_rqfcr[rqfar] = rqfcr;
783         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
784
785         rqfar--;
786         rqfcr = RQFCR_CMP_NOMATCH;
787         ftp_rqfpr[rqfar] = rqfpr;
788         ftp_rqfcr[rqfar] = rqfcr;
789         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
790
791         rqfar--;
792         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
793         rqfpr = class;
794         ftp_rqfcr[rqfar] = rqfcr;
795         ftp_rqfpr[rqfar] = rqfpr;
796         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
797
798         rqfar--;
799         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
800         rqfpr = class;
801         ftp_rqfcr[rqfar] = rqfcr;
802         ftp_rqfpr[rqfar] = rqfpr;
803         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
804
805         return rqfar;
806 }
807
808 static void gfar_init_filer_table(struct gfar_private *priv)
809 {
810         int i = 0x0;
811         u32 rqfar = MAX_FILER_IDX;
812         u32 rqfcr = 0x0;
813         u32 rqfpr = FPR_FILER_MASK;
814
815         /* Default rule */
816         rqfcr = RQFCR_CMP_MATCH;
817         ftp_rqfcr[rqfar] = rqfcr;
818         ftp_rqfpr[rqfar] = rqfpr;
819         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
820
821         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
822         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
823         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
824         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
825         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
826         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
827
828         /* cur_filer_idx indicated the fisrt non-masked rule */
829         priv->cur_filer_idx = rqfar;
830
831         /* Rest are masked rules */
832         rqfcr = RQFCR_CMP_NOMATCH;
833         for (i = 0; i < rqfar; i++) {
834                 ftp_rqfcr[i] = rqfcr;
835                 ftp_rqfpr[i] = rqfpr;
836                 gfar_write_filer(priv, i, rqfcr, rqfpr);
837         }
838 }
839
840 /* Set up the ethernet device structure, private data,
841  * and anything else we need before we start */
842 static int gfar_probe(struct of_device *ofdev,
843                 const struct of_device_id *match)
844 {
845         u32 tempval;
846         struct net_device *dev = NULL;
847         struct gfar_private *priv = NULL;
848         struct gfar __iomem *regs = NULL;
849         int err = 0, i, grp_idx = 0;
850         int len_devname;
851         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
852         u32 isrg = 0;
853         u32 __iomem *baddr;
854
855         err = gfar_of_init(ofdev, &dev);
856
857         if (err)
858                 return err;
859
860         priv = netdev_priv(dev);
861         priv->ndev = dev;
862         priv->ofdev = ofdev;
863         priv->node = ofdev->node;
864         SET_NETDEV_DEV(dev, &ofdev->dev);
865
866         spin_lock_init(&priv->bflock);
867         INIT_WORK(&priv->reset_task, gfar_reset_task);
868
869         dev_set_drvdata(&ofdev->dev, priv);
870         regs = priv->gfargrp[0].regs;
871
872         /* Stop the DMA engine now, in case it was running before */
873         /* (The firmware could have used it, and left it running). */
874         gfar_halt(dev);
875
876         /* Reset MAC layer */
877         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
878
879         /* We need to delay at least 3 TX clocks */
880         udelay(2);
881
882         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
883         gfar_write(&regs->maccfg1, tempval);
884
885         /* Initialize MACCFG2. */
886         gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
887
888         /* Initialize ECNTRL */
889         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
890
891         /* Set the dev->base_addr to the gfar reg region */
892         dev->base_addr = (unsigned long) regs;
893
894         SET_NETDEV_DEV(dev, &ofdev->dev);
895
896         /* Fill in the dev structure */
897         dev->watchdog_timeo = TX_TIMEOUT;
898         dev->mtu = 1500;
899         dev->netdev_ops = &gfar_netdev_ops;
900         dev->ethtool_ops = &gfar_ethtool_ops;
901
902         /* Register for napi ...We are registering NAPI for each grp */
903         for (i = 0; i < priv->num_grps; i++)
904                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
905
906         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
907                 priv->rx_csum_enable = 1;
908                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
909         } else
910                 priv->rx_csum_enable = 0;
911
912         priv->vlgrp = NULL;
913
914         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
915                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
916
917         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
918                 priv->extended_hash = 1;
919                 priv->hash_width = 9;
920
921                 priv->hash_regs[0] = &regs->igaddr0;
922                 priv->hash_regs[1] = &regs->igaddr1;
923                 priv->hash_regs[2] = &regs->igaddr2;
924                 priv->hash_regs[3] = &regs->igaddr3;
925                 priv->hash_regs[4] = &regs->igaddr4;
926                 priv->hash_regs[5] = &regs->igaddr5;
927                 priv->hash_regs[6] = &regs->igaddr6;
928                 priv->hash_regs[7] = &regs->igaddr7;
929                 priv->hash_regs[8] = &regs->gaddr0;
930                 priv->hash_regs[9] = &regs->gaddr1;
931                 priv->hash_regs[10] = &regs->gaddr2;
932                 priv->hash_regs[11] = &regs->gaddr3;
933                 priv->hash_regs[12] = &regs->gaddr4;
934                 priv->hash_regs[13] = &regs->gaddr5;
935                 priv->hash_regs[14] = &regs->gaddr6;
936                 priv->hash_regs[15] = &regs->gaddr7;
937
938         } else {
939                 priv->extended_hash = 0;
940                 priv->hash_width = 8;
941
942                 priv->hash_regs[0] = &regs->gaddr0;
943                 priv->hash_regs[1] = &regs->gaddr1;
944                 priv->hash_regs[2] = &regs->gaddr2;
945                 priv->hash_regs[3] = &regs->gaddr3;
946                 priv->hash_regs[4] = &regs->gaddr4;
947                 priv->hash_regs[5] = &regs->gaddr5;
948                 priv->hash_regs[6] = &regs->gaddr6;
949                 priv->hash_regs[7] = &regs->gaddr7;
950         }
951
952         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
953                 priv->padding = DEFAULT_PADDING;
954         else
955                 priv->padding = 0;
956
957         if (dev->features & NETIF_F_IP_CSUM)
958                 dev->hard_header_len += GMAC_FCB_LEN;
959
960         /* Program the isrg regs only if number of grps > 1 */
961         if (priv->num_grps > 1) {
962                 baddr = &regs->isrg0;
963                 for (i = 0; i < priv->num_grps; i++) {
964                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
965                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
966                         gfar_write(baddr, isrg);
967                         baddr++;
968                         isrg = 0x0;
969                 }
970         }
971
972         /* Need to reverse the bit maps as  bit_map's MSB is q0
973          * but, for_each_bit parses from right to left, which
974          * basically reverses the queue numbers */
975         for (i = 0; i< priv->num_grps; i++) {
976                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
977                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
978                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
979                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
980         }
981
982         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
983          * also assign queues to groups */
984         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
985                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
986                 for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
987                                 priv->num_rx_queues) {
988                         priv->gfargrp[grp_idx].num_rx_queues++;
989                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
990                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
991                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
992                 }
993                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
994                 for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,
995                                 priv->num_tx_queues) {
996                         priv->gfargrp[grp_idx].num_tx_queues++;
997                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
998                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
999                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1000                 }
1001                 priv->gfargrp[grp_idx].rstat = rstat;
1002                 priv->gfargrp[grp_idx].tstat = tstat;
1003                 rstat = tstat =0;
1004         }
1005
1006         gfar_write(&regs->rqueue, rqueue);
1007         gfar_write(&regs->tqueue, tqueue);
1008
1009         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1010
1011         /* Initializing some of the rx/tx queue level parameters */
1012         for (i = 0; i < priv->num_tx_queues; i++) {
1013                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1014                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1015                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1016                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1017         }
1018
1019         for (i = 0; i < priv->num_rx_queues; i++) {
1020                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1021                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1022                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1023         }
1024
1025         /* Enable most messages by default */
1026         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1027
1028         /* Carrier starts down, phylib will bring it up */
1029         netif_carrier_off(dev);
1030
1031         err = register_netdev(dev);
1032
1033         if (err) {
1034                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1035                                 dev->name);
1036                 goto register_fail;
1037         }
1038
1039         device_init_wakeup(&dev->dev,
1040                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1041
1042         /* fill out IRQ number and name fields */
1043         len_devname = strlen(dev->name);
1044         for (i = 0; i < priv->num_grps; i++) {
1045                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1046                                 len_devname);
1047                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1048                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1049                                 "_g", sizeof("_g"));
1050                         priv->gfargrp[i].int_name_tx[
1051                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1052                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1053                                 priv->gfargrp[i].int_name_tx)],
1054                                 "_tx", sizeof("_tx") + 1);
1055
1056                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1057                                         len_devname);
1058                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1059                                         "_g", sizeof("_g"));
1060                         priv->gfargrp[i].int_name_rx[
1061                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1062                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1063                                 priv->gfargrp[i].int_name_rx)],
1064                                 "_rx", sizeof("_rx") + 1);
1065
1066                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1067                                         len_devname);
1068                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1069                                 "_g", sizeof("_g"));
1070                         priv->gfargrp[i].int_name_er[strlen(
1071                                         priv->gfargrp[i].int_name_er)] = i+48;
1072                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1073                                 priv->gfargrp[i].int_name_er)],
1074                                 "_er", sizeof("_er") + 1);
1075                 } else
1076                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1077         }
1078
1079         /* Initialize the filer table */
1080         gfar_init_filer_table(priv);
1081
1082         /* Create all the sysfs files */
1083         gfar_init_sysfs(dev);
1084
1085         /* Print out the device info */
1086         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1087
1088         /* Even more device info helps when determining which kernel */
1089         /* provided which set of benchmarks. */
1090         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1091         for (i = 0; i < priv->num_rx_queues; i++)
1092                 printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",
1093                         dev->name, i, priv->rx_queue[i]->rx_ring_size);
1094         for(i = 0; i < priv->num_tx_queues; i++)
1095                  printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",
1096                         dev->name, i, priv->tx_queue[i]->tx_ring_size);
1097
1098         return 0;
1099
1100 register_fail:
1101         unmap_group_regs(priv);
1102         free_tx_pointers(priv);
1103         free_rx_pointers(priv);
1104         if (priv->phy_node)
1105                 of_node_put(priv->phy_node);
1106         if (priv->tbi_node)
1107                 of_node_put(priv->tbi_node);
1108         free_netdev(dev);
1109         return err;
1110 }
1111
1112 static int gfar_remove(struct of_device *ofdev)
1113 {
1114         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1115
1116         if (priv->phy_node)
1117                 of_node_put(priv->phy_node);
1118         if (priv->tbi_node)
1119                 of_node_put(priv->tbi_node);
1120
1121         dev_set_drvdata(&ofdev->dev, NULL);
1122
1123         unregister_netdev(priv->ndev);
1124         unmap_group_regs(priv);
1125         free_netdev(priv->ndev);
1126
1127         return 0;
1128 }
1129
1130 #ifdef CONFIG_PM
1131
1132 static int gfar_suspend(struct device *dev)
1133 {
1134         struct gfar_private *priv = dev_get_drvdata(dev);
1135         struct net_device *ndev = priv->ndev;
1136         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1137         unsigned long flags;
1138         u32 tempval;
1139
1140         int magic_packet = priv->wol_en &&
1141                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1142
1143         netif_device_detach(ndev);
1144
1145         if (netif_running(ndev)) {
1146
1147                 local_irq_save(flags);
1148                 lock_tx_qs(priv);
1149                 lock_rx_qs(priv);
1150
1151                 gfar_halt_nodisable(ndev);
1152
1153                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1154                 tempval = gfar_read(&regs->maccfg1);
1155
1156                 tempval &= ~MACCFG1_TX_EN;
1157
1158                 if (!magic_packet)
1159                         tempval &= ~MACCFG1_RX_EN;
1160
1161                 gfar_write(&regs->maccfg1, tempval);
1162
1163                 unlock_rx_qs(priv);
1164                 unlock_tx_qs(priv);
1165                 local_irq_restore(flags);
1166
1167                 disable_napi(priv);
1168
1169                 if (magic_packet) {
1170                         /* Enable interrupt on Magic Packet */
1171                         gfar_write(&regs->imask, IMASK_MAG);
1172
1173                         /* Enable Magic Packet mode */
1174                         tempval = gfar_read(&regs->maccfg2);
1175                         tempval |= MACCFG2_MPEN;
1176                         gfar_write(&regs->maccfg2, tempval);
1177                 } else {
1178                         phy_stop(priv->phydev);
1179                 }
1180         }
1181
1182         return 0;
1183 }
1184
1185 static int gfar_resume(struct device *dev)
1186 {
1187         struct gfar_private *priv = dev_get_drvdata(dev);
1188         struct net_device *ndev = priv->ndev;
1189         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1190         unsigned long flags;
1191         u32 tempval;
1192         int magic_packet = priv->wol_en &&
1193                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1194
1195         if (!netif_running(ndev)) {
1196                 netif_device_attach(ndev);
1197                 return 0;
1198         }
1199
1200         if (!magic_packet && priv->phydev)
1201                 phy_start(priv->phydev);
1202
1203         /* Disable Magic Packet mode, in case something
1204          * else woke us up.
1205          */
1206         local_irq_save(flags);
1207         lock_tx_qs(priv);
1208         lock_rx_qs(priv);
1209
1210         tempval = gfar_read(&regs->maccfg2);
1211         tempval &= ~MACCFG2_MPEN;
1212         gfar_write(&regs->maccfg2, tempval);
1213
1214         gfar_start(ndev);
1215
1216         unlock_rx_qs(priv);
1217         unlock_tx_qs(priv);
1218         local_irq_restore(flags);
1219
1220         netif_device_attach(ndev);
1221
1222         enable_napi(priv);
1223
1224         return 0;
1225 }
1226
1227 static int gfar_restore(struct device *dev)
1228 {
1229         struct gfar_private *priv = dev_get_drvdata(dev);
1230         struct net_device *ndev = priv->ndev;
1231
1232         if (!netif_running(ndev))
1233                 return 0;
1234
1235         gfar_init_bds(ndev);
1236         init_registers(ndev);
1237         gfar_set_mac_address(ndev);
1238         gfar_init_mac(ndev);
1239         gfar_start(ndev);
1240
1241         priv->oldlink = 0;
1242         priv->oldspeed = 0;
1243         priv->oldduplex = -1;
1244
1245         if (priv->phydev)
1246                 phy_start(priv->phydev);
1247
1248         netif_device_attach(ndev);
1249         napi_enable(&priv->gfargrp.napi);
1250
1251         return 0;
1252 }
1253
1254 static struct dev_pm_ops gfar_pm_ops = {
1255         .suspend = gfar_suspend,
1256         .resume = gfar_resume,
1257         .freeze = gfar_suspend,
1258         .thaw = gfar_resume,
1259         .restore = gfar_restore,
1260 };
1261
1262 #define GFAR_PM_OPS (&gfar_pm_ops)
1263
1264 static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1265 {
1266         return gfar_suspend(&ofdev->dev);
1267 }
1268
1269 static int gfar_legacy_resume(struct of_device *ofdev)
1270 {
1271         return gfar_resume(&ofdev->dev);
1272 }
1273
1274 #else
1275
1276 #define GFAR_PM_OPS NULL
1277 #define gfar_legacy_suspend NULL
1278 #define gfar_legacy_resume NULL
1279
1280 #endif
1281
1282 /* Reads the controller's registers to determine what interface
1283  * connects it to the PHY.
1284  */
1285 static phy_interface_t gfar_get_interface(struct net_device *dev)
1286 {
1287         struct gfar_private *priv = netdev_priv(dev);
1288         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1289         u32 ecntrl;
1290
1291         ecntrl = gfar_read(&regs->ecntrl);
1292
1293         if (ecntrl & ECNTRL_SGMII_MODE)
1294                 return PHY_INTERFACE_MODE_SGMII;
1295
1296         if (ecntrl & ECNTRL_TBI_MODE) {
1297                 if (ecntrl & ECNTRL_REDUCED_MODE)
1298                         return PHY_INTERFACE_MODE_RTBI;
1299                 else
1300                         return PHY_INTERFACE_MODE_TBI;
1301         }
1302
1303         if (ecntrl & ECNTRL_REDUCED_MODE) {
1304                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1305                         return PHY_INTERFACE_MODE_RMII;
1306                 else {
1307                         phy_interface_t interface = priv->interface;
1308
1309                         /*
1310                          * This isn't autodetected right now, so it must
1311                          * be set by the device tree or platform code.
1312                          */
1313                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1314                                 return PHY_INTERFACE_MODE_RGMII_ID;
1315
1316                         return PHY_INTERFACE_MODE_RGMII;
1317                 }
1318         }
1319
1320         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1321                 return PHY_INTERFACE_MODE_GMII;
1322
1323         return PHY_INTERFACE_MODE_MII;
1324 }
1325
1326
1327 /* Initializes driver's PHY state, and attaches to the PHY.
1328  * Returns 0 on success.
1329  */
1330 static int init_phy(struct net_device *dev)
1331 {
1332         struct gfar_private *priv = netdev_priv(dev);
1333         uint gigabit_support =
1334                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1335                 SUPPORTED_1000baseT_Full : 0;
1336         phy_interface_t interface;
1337
1338         priv->oldlink = 0;
1339         priv->oldspeed = 0;
1340         priv->oldduplex = -1;
1341
1342         interface = gfar_get_interface(dev);
1343
1344         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1345                                       interface);
1346         if (!priv->phydev)
1347                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1348                                                          interface);
1349         if (!priv->phydev) {
1350                 dev_err(&dev->dev, "could not attach to PHY\n");
1351                 return -ENODEV;
1352         }
1353
1354         if (interface == PHY_INTERFACE_MODE_SGMII)
1355                 gfar_configure_serdes(dev);
1356
1357         /* Remove any features not supported by the controller */
1358         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1359         priv->phydev->advertising = priv->phydev->supported;
1360
1361         return 0;
1362 }
1363
1364 /*
1365  * Initialize TBI PHY interface for communicating with the
1366  * SERDES lynx PHY on the chip.  We communicate with this PHY
1367  * through the MDIO bus on each controller, treating it as a
1368  * "normal" PHY at the address found in the TBIPA register.  We assume
1369  * that the TBIPA register is valid.  Either the MDIO bus code will set
1370  * it to a value that doesn't conflict with other PHYs on the bus, or the
1371  * value doesn't matter, as there are no other PHYs on the bus.
1372  */
1373 static void gfar_configure_serdes(struct net_device *dev)
1374 {
1375         struct gfar_private *priv = netdev_priv(dev);
1376         struct phy_device *tbiphy;
1377
1378         if (!priv->tbi_node) {
1379                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1380                                     "device tree specify a tbi-handle\n");
1381                 return;
1382         }
1383
1384         tbiphy = of_phy_find_device(priv->tbi_node);
1385         if (!tbiphy) {
1386                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1387                 return;
1388         }
1389
1390         /*
1391          * If the link is already up, we must already be ok, and don't need to
1392          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1393          * everything for us?  Resetting it takes the link down and requires
1394          * several seconds for it to come back.
1395          */
1396         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1397                 return;
1398
1399         /* Single clk mode, mii mode off(for serdes communication) */
1400         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1401
1402         phy_write(tbiphy, MII_ADVERTISE,
1403                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1404                         ADVERTISE_1000XPSE_ASYM);
1405
1406         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1407                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1408 }
1409
1410 static void init_registers(struct net_device *dev)
1411 {
1412         struct gfar_private *priv = netdev_priv(dev);
1413         struct gfar __iomem *regs = NULL;
1414         int i = 0;
1415
1416         for (i = 0; i < priv->num_grps; i++) {
1417                 regs = priv->gfargrp[i].regs;
1418                 /* Clear IEVENT */
1419                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1420
1421                 /* Initialize IMASK */
1422                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1423         }
1424
1425         regs = priv->gfargrp[0].regs;
1426         /* Init hash registers to zero */
1427         gfar_write(&regs->igaddr0, 0);
1428         gfar_write(&regs->igaddr1, 0);
1429         gfar_write(&regs->igaddr2, 0);
1430         gfar_write(&regs->igaddr3, 0);
1431         gfar_write(&regs->igaddr4, 0);
1432         gfar_write(&regs->igaddr5, 0);
1433         gfar_write(&regs->igaddr6, 0);
1434         gfar_write(&regs->igaddr7, 0);
1435
1436         gfar_write(&regs->gaddr0, 0);
1437         gfar_write(&regs->gaddr1, 0);
1438         gfar_write(&regs->gaddr2, 0);
1439         gfar_write(&regs->gaddr3, 0);
1440         gfar_write(&regs->gaddr4, 0);
1441         gfar_write(&regs->gaddr5, 0);
1442         gfar_write(&regs->gaddr6, 0);
1443         gfar_write(&regs->gaddr7, 0);
1444
1445         /* Zero out the rmon mib registers if it has them */
1446         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1447                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1448
1449                 /* Mask off the CAM interrupts */
1450                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1451                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1452         }
1453
1454         /* Initialize the max receive buffer length */
1455         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1456
1457         /* Initialize the Minimum Frame Length Register */
1458         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1459 }
1460
1461
1462 /* Halt the receive and transmit queues */
1463 static void gfar_halt_nodisable(struct net_device *dev)
1464 {
1465         struct gfar_private *priv = netdev_priv(dev);
1466         struct gfar __iomem *regs = NULL;
1467         u32 tempval;
1468         int i = 0;
1469
1470         for (i = 0; i < priv->num_grps; i++) {
1471                 regs = priv->gfargrp[i].regs;
1472                 /* Mask all interrupts */
1473                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1474
1475                 /* Clear all interrupts */
1476                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1477         }
1478
1479         regs = priv->gfargrp[0].regs;
1480         /* Stop the DMA, and wait for it to stop */
1481         tempval = gfar_read(&regs->dmactrl);
1482         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1483             != (DMACTRL_GRS | DMACTRL_GTS)) {
1484                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1485                 gfar_write(&regs->dmactrl, tempval);
1486
1487                 while (!(gfar_read(&regs->ievent) &
1488                          (IEVENT_GRSC | IEVENT_GTSC)))
1489                         cpu_relax();
1490         }
1491 }
1492
1493 /* Halt the receive and transmit queues */
1494 void gfar_halt(struct net_device *dev)
1495 {
1496         struct gfar_private *priv = netdev_priv(dev);
1497         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1498         u32 tempval;
1499
1500         gfar_halt_nodisable(dev);
1501
1502         /* Disable Rx and Tx */
1503         tempval = gfar_read(&regs->maccfg1);
1504         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1505         gfar_write(&regs->maccfg1, tempval);
1506 }
1507
1508 static void free_grp_irqs(struct gfar_priv_grp *grp)
1509 {
1510         free_irq(grp->interruptError, grp);
1511         free_irq(grp->interruptTransmit, grp);
1512         free_irq(grp->interruptReceive, grp);
1513 }
1514
1515 void stop_gfar(struct net_device *dev)
1516 {
1517         struct gfar_private *priv = netdev_priv(dev);
1518         unsigned long flags;
1519         int i;
1520
1521         phy_stop(priv->phydev);
1522
1523
1524         /* Lock it down */
1525         local_irq_save(flags);
1526         lock_tx_qs(priv);
1527         lock_rx_qs(priv);
1528
1529         gfar_halt(dev);
1530
1531         unlock_rx_qs(priv);
1532         unlock_tx_qs(priv);
1533         local_irq_restore(flags);
1534
1535         /* Free the IRQs */
1536         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1537                 for (i = 0; i < priv->num_grps; i++)
1538                         free_grp_irqs(&priv->gfargrp[i]);
1539         } else {
1540                 for (i = 0; i < priv->num_grps; i++)
1541                         free_irq(priv->gfargrp[i].interruptTransmit,
1542                                         &priv->gfargrp[i]);
1543         }
1544
1545         free_skb_resources(priv);
1546 }
1547
1548 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1549 {
1550         struct txbd8 *txbdp;
1551         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1552         int i, j;
1553
1554         txbdp = tx_queue->tx_bd_base;
1555
1556         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1557                 if (!tx_queue->tx_skbuff[i])
1558                         continue;
1559
1560                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1561                                 txbdp->length, DMA_TO_DEVICE);
1562                 txbdp->lstatus = 0;
1563                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1564                                 j++) {
1565                         txbdp++;
1566                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1567                                         txbdp->length, DMA_TO_DEVICE);
1568                 }
1569                 txbdp++;
1570                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1571                 tx_queue->tx_skbuff[i] = NULL;
1572         }
1573         kfree(tx_queue->tx_skbuff);
1574 }
1575
1576 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1577 {
1578         struct rxbd8 *rxbdp;
1579         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1580         int i;
1581
1582         rxbdp = rx_queue->rx_bd_base;
1583
1584         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1585                 if (rx_queue->rx_skbuff[i]) {
1586                         dma_unmap_single(&priv->ofdev->dev,
1587                                         rxbdp->bufPtr, priv->rx_buffer_size,
1588                                         DMA_FROM_DEVICE);
1589                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1590                         rx_queue->rx_skbuff[i] = NULL;
1591                 }
1592                 rxbdp->lstatus = 0;
1593                 rxbdp->bufPtr = 0;
1594                 rxbdp++;
1595         }
1596         kfree(rx_queue->rx_skbuff);
1597 }
1598
1599 /* If there are any tx skbs or rx skbs still around, free them.
1600  * Then free tx_skbuff and rx_skbuff */
1601 static void free_skb_resources(struct gfar_private *priv)
1602 {
1603         struct gfar_priv_tx_q *tx_queue = NULL;
1604         struct gfar_priv_rx_q *rx_queue = NULL;
1605         int i;
1606
1607         /* Go through all the buffer descriptors and free their data buffers */
1608         for (i = 0; i < priv->num_tx_queues; i++) {
1609                 tx_queue = priv->tx_queue[i];
1610                 if(!tx_queue->tx_skbuff)
1611                         free_skb_tx_queue(tx_queue);
1612         }
1613
1614         for (i = 0; i < priv->num_rx_queues; i++) {
1615                 rx_queue = priv->rx_queue[i];
1616                 if(!rx_queue->rx_skbuff)
1617                         free_skb_rx_queue(rx_queue);
1618         }
1619
1620         dma_free_coherent(&priv->ofdev->dev,
1621                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1622                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1623                         priv->tx_queue[0]->tx_bd_base,
1624                         priv->tx_queue[0]->tx_bd_dma_base);
1625 }
1626
1627 void gfar_start(struct net_device *dev)
1628 {
1629         struct gfar_private *priv = netdev_priv(dev);
1630         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1631         u32 tempval;
1632         int i = 0;
1633
1634         /* Enable Rx and Tx in MACCFG1 */
1635         tempval = gfar_read(&regs->maccfg1);
1636         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1637         gfar_write(&regs->maccfg1, tempval);
1638
1639         /* Initialize DMACTRL to have WWR and WOP */
1640         tempval = gfar_read(&regs->dmactrl);
1641         tempval |= DMACTRL_INIT_SETTINGS;
1642         gfar_write(&regs->dmactrl, tempval);
1643
1644         /* Make sure we aren't stopped */
1645         tempval = gfar_read(&regs->dmactrl);
1646         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1647         gfar_write(&regs->dmactrl, tempval);
1648
1649         for (i = 0; i < priv->num_grps; i++) {
1650                 regs = priv->gfargrp[i].regs;
1651                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1652                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1653                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1654                 /* Unmask the interrupts we look for */
1655                 gfar_write(&regs->imask, IMASK_DEFAULT);
1656         }
1657
1658         dev->trans_start = jiffies;
1659 }
1660
1661 void gfar_configure_coalescing(struct gfar_private *priv,
1662         unsigned long tx_mask, unsigned long rx_mask)
1663 {
1664         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1665         u32 __iomem *baddr;
1666         int i = 0;
1667
1668         /* Backward compatible case ---- even if we enable
1669          * multiple queues, there's only single reg to program
1670          */
1671         gfar_write(&regs->txic, 0);
1672         if(likely(priv->tx_queue[0]->txcoalescing))
1673                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1674
1675         gfar_write(&regs->rxic, 0);
1676         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1677                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1678
1679         if (priv->mode == MQ_MG_MODE) {
1680                 baddr = &regs->txic0;
1681                 for_each_bit (i, &tx_mask, priv->num_tx_queues) {
1682                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1683                                 gfar_write(baddr + i, 0);
1684                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1685                         }
1686                 }
1687
1688                 baddr = &regs->rxic0;
1689                 for_each_bit (i, &rx_mask, priv->num_rx_queues) {
1690                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1691                                 gfar_write(baddr + i, 0);
1692                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1693                         }
1694                 }
1695         }
1696 }
1697
1698 static int register_grp_irqs(struct gfar_priv_grp *grp)
1699 {
1700         struct gfar_private *priv = grp->priv;
1701         struct net_device *dev = priv->ndev;
1702         int err;
1703
1704         /* If the device has multiple interrupts, register for
1705          * them.  Otherwise, only register for the one */
1706         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1707                 /* Install our interrupt handlers for Error,
1708                  * Transmit, and Receive */
1709                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1710                                 grp->int_name_er,grp)) < 0) {
1711                         if (netif_msg_intr(priv))
1712                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1713                                         dev->name, grp->interruptError);
1714
1715                                 goto err_irq_fail;
1716                 }
1717
1718                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1719                                 0, grp->int_name_tx, grp)) < 0) {
1720                         if (netif_msg_intr(priv))
1721                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1722                                         dev->name, grp->interruptTransmit);
1723                         goto tx_irq_fail;
1724                 }
1725
1726                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1727                                 grp->int_name_rx, grp)) < 0) {
1728                         if (netif_msg_intr(priv))
1729                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1730                                         dev->name, grp->interruptReceive);
1731                         goto rx_irq_fail;
1732                 }
1733         } else {
1734                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1735                                 grp->int_name_tx, grp)) < 0) {
1736                         if (netif_msg_intr(priv))
1737                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1738                                         dev->name, grp->interruptTransmit);
1739                         goto err_irq_fail;
1740                 }
1741         }
1742
1743         return 0;
1744
1745 rx_irq_fail:
1746         free_irq(grp->interruptTransmit, grp);
1747 tx_irq_fail:
1748         free_irq(grp->interruptError, grp);
1749 err_irq_fail:
1750         return err;
1751
1752 }
1753
1754 /* Bring the controller up and running */
1755 int startup_gfar(struct net_device *ndev)
1756 {
1757         struct gfar_private *priv = netdev_priv(ndev);
1758         struct gfar __iomem *regs = NULL;
1759         int err, i, j;
1760
1761         for (i = 0; i < priv->num_grps; i++) {
1762                 regs= priv->gfargrp[i].regs;
1763                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1764         }
1765
1766         regs= priv->gfargrp[0].regs;
1767         err = gfar_alloc_skb_resources(ndev);
1768         if (err)
1769                 return err;
1770
1771         gfar_init_mac(ndev);
1772
1773         for (i = 0; i < priv->num_grps; i++) {
1774                 err = register_grp_irqs(&priv->gfargrp[i]);
1775                 if (err) {
1776                         for (j = 0; j < i; j++)
1777                                 free_grp_irqs(&priv->gfargrp[j]);
1778                                 goto irq_fail;
1779                 }
1780         }
1781
1782         /* Start the controller */
1783         gfar_start(ndev);
1784
1785         phy_start(priv->phydev);
1786
1787         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1788
1789         return 0;
1790
1791 irq_fail:
1792         free_skb_resources(priv);
1793         return err;
1794 }
1795
1796 /* Called when something needs to use the ethernet device */
1797 /* Returns 0 for success. */
1798 static int gfar_enet_open(struct net_device *dev)
1799 {
1800         struct gfar_private *priv = netdev_priv(dev);
1801         int err;
1802
1803         enable_napi(priv);
1804
1805         skb_queue_head_init(&priv->rx_recycle);
1806
1807         /* Initialize a bunch of registers */
1808         init_registers(dev);
1809
1810         gfar_set_mac_address(dev);
1811
1812         err = init_phy(dev);
1813
1814         if (err) {
1815                 disable_napi(priv);
1816                 return err;
1817         }
1818
1819         err = startup_gfar(dev);
1820         if (err) {
1821                 disable_napi(priv);
1822                 return err;
1823         }
1824
1825         netif_tx_start_all_queues(dev);
1826
1827         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1828
1829         return err;
1830 }
1831
1832 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1833 {
1834         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1835
1836         memset(fcb, 0, GMAC_FCB_LEN);
1837
1838         return fcb;
1839 }
1840
1841 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1842 {
1843         u8 flags = 0;
1844
1845         /* If we're here, it's a IP packet with a TCP or UDP
1846          * payload.  We set it to checksum, using a pseudo-header
1847          * we provide
1848          */
1849         flags = TXFCB_DEFAULT;
1850
1851         /* Tell the controller what the protocol is */
1852         /* And provide the already calculated phcs */
1853         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1854                 flags |= TXFCB_UDP;
1855                 fcb->phcs = udp_hdr(skb)->check;
1856         } else
1857                 fcb->phcs = tcp_hdr(skb)->check;
1858
1859         /* l3os is the distance between the start of the
1860          * frame (skb->data) and the start of the IP hdr.
1861          * l4os is the distance between the start of the
1862          * l3 hdr and the l4 hdr */
1863         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1864         fcb->l4os = skb_network_header_len(skb);
1865
1866         fcb->flags = flags;
1867 }
1868
1869 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1870 {
1871         fcb->flags |= TXFCB_VLN;
1872         fcb->vlctl = vlan_tx_tag_get(skb);
1873 }
1874
1875 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1876                                struct txbd8 *base, int ring_size)
1877 {
1878         struct txbd8 *new_bd = bdp + stride;
1879
1880         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1881 }
1882
1883 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1884                 int ring_size)
1885 {
1886         return skip_txbd(bdp, 1, base, ring_size);
1887 }
1888
1889 /* This is called by the kernel when a frame is ready for transmission. */
1890 /* It is pointed to by the dev->hard_start_xmit function pointer */
1891 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1892 {
1893         struct gfar_private *priv = netdev_priv(dev);
1894         struct gfar_priv_tx_q *tx_queue = NULL;
1895         struct netdev_queue *txq;
1896         struct gfar __iomem *regs = NULL;
1897         struct txfcb *fcb = NULL;
1898         struct txbd8 *txbdp, *txbdp_start, *base;
1899         u32 lstatus;
1900         int i, rq = 0;
1901         u32 bufaddr;
1902         unsigned long flags;
1903         unsigned int nr_frags, length;
1904
1905
1906         rq = skb->queue_mapping;
1907         tx_queue = priv->tx_queue[rq];
1908         txq = netdev_get_tx_queue(dev, rq);
1909         base = tx_queue->tx_bd_base;
1910         regs = tx_queue->grp->regs;
1911
1912         /* make space for additional header when fcb is needed */
1913         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1914                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1915                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1916                 struct sk_buff *skb_new;
1917
1918                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1919                 if (!skb_new) {
1920                         dev->stats.tx_errors++;
1921                         kfree_skb(skb);
1922                         return NETDEV_TX_OK;
1923                 }
1924                 kfree_skb(skb);
1925                 skb = skb_new;
1926         }
1927
1928         /* total number of fragments in the SKB */
1929         nr_frags = skb_shinfo(skb)->nr_frags;
1930
1931         spin_lock_irqsave(&tx_queue->txlock, flags);
1932
1933         /* check if there is space to queue this packet */
1934         if ((nr_frags+1) > tx_queue->num_txbdfree) {
1935                 /* no space, stop the queue */
1936                 netif_tx_stop_queue(txq);
1937                 dev->stats.tx_fifo_errors++;
1938                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1939                 return NETDEV_TX_BUSY;
1940         }
1941
1942         /* Update transmit stats */
1943         dev->stats.tx_bytes += skb->len;
1944
1945         txbdp = txbdp_start = tx_queue->cur_tx;
1946
1947         if (nr_frags == 0) {
1948                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1949         } else {
1950                 /* Place the fragment addresses and lengths into the TxBDs */
1951                 for (i = 0; i < nr_frags; i++) {
1952                         /* Point at the next BD, wrapping as needed */
1953                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1954
1955                         length = skb_shinfo(skb)->frags[i].size;
1956
1957                         lstatus = txbdp->lstatus | length |
1958                                 BD_LFLAG(TXBD_READY);
1959
1960                         /* Handle the last BD specially */
1961                         if (i == nr_frags - 1)
1962                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1963
1964                         bufaddr = dma_map_page(&priv->ofdev->dev,
1965                                         skb_shinfo(skb)->frags[i].page,
1966                                         skb_shinfo(skb)->frags[i].page_offset,
1967                                         length,
1968                                         DMA_TO_DEVICE);
1969
1970                         /* set the TxBD length and buffer pointer */
1971                         txbdp->bufPtr = bufaddr;
1972                         txbdp->lstatus = lstatus;
1973                 }
1974
1975                 lstatus = txbdp_start->lstatus;
1976         }
1977
1978         /* Set up checksumming */
1979         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1980                 fcb = gfar_add_fcb(skb);
1981                 lstatus |= BD_LFLAG(TXBD_TOE);
1982                 gfar_tx_checksum(skb, fcb);
1983         }
1984
1985         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1986                 if (unlikely(NULL == fcb)) {
1987                         fcb = gfar_add_fcb(skb);
1988                         lstatus |= BD_LFLAG(TXBD_TOE);
1989                 }
1990
1991                 gfar_tx_vlan(skb, fcb);
1992         }
1993
1994         /* setup the TxBD length and buffer pointer for the first BD */
1995         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1996         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1997                         skb_headlen(skb), DMA_TO_DEVICE);
1998
1999         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2000
2001         /*
2002          * The powerpc-specific eieio() is used, as wmb() has too strong
2003          * semantics (it requires synchronization between cacheable and
2004          * uncacheable mappings, which eieio doesn't provide and which we
2005          * don't need), thus requiring a more expensive sync instruction.  At
2006          * some point, the set of architecture-independent barrier functions
2007          * should be expanded to include weaker barriers.
2008          */
2009         eieio();
2010
2011         txbdp_start->lstatus = lstatus;
2012
2013         /* Update the current skb pointer to the next entry we will use
2014          * (wrapping if necessary) */
2015         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2016                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2017
2018         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2019
2020         /* reduce TxBD free count */
2021         tx_queue->num_txbdfree -= (nr_frags + 1);
2022
2023         dev->trans_start = jiffies;
2024
2025         /* If the next BD still needs to be cleaned up, then the bds
2026            are full.  We need to tell the kernel to stop sending us stuff. */
2027         if (!tx_queue->num_txbdfree) {
2028                 netif_tx_stop_queue(txq);
2029
2030                 dev->stats.tx_fifo_errors++;
2031         }
2032
2033         /* Tell the DMA to go go go */
2034         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2035
2036         /* Unlock priv */
2037         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2038
2039         return NETDEV_TX_OK;
2040 }
2041
2042 /* Stops the kernel queue, and halts the controller */
2043 static int gfar_close(struct net_device *dev)
2044 {
2045         struct gfar_private *priv = netdev_priv(dev);
2046
2047         disable_napi(priv);
2048
2049         skb_queue_purge(&priv->rx_recycle);
2050         cancel_work_sync(&priv->reset_task);
2051         stop_gfar(dev);
2052
2053         /* Disconnect from the PHY */
2054         phy_disconnect(priv->phydev);
2055         priv->phydev = NULL;
2056
2057         netif_tx_stop_all_queues(dev);
2058
2059         return 0;
2060 }
2061
2062 /* Changes the mac address if the controller is not running. */
2063 static int gfar_set_mac_address(struct net_device *dev)
2064 {
2065         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2066
2067         return 0;
2068 }
2069
2070
2071 /* Enables and disables VLAN insertion/extraction */
2072 static void gfar_vlan_rx_register(struct net_device *dev,
2073                 struct vlan_group *grp)
2074 {
2075         struct gfar_private *priv = netdev_priv(dev);
2076         struct gfar __iomem *regs = NULL;
2077         unsigned long flags;
2078         u32 tempval;
2079
2080         regs = priv->gfargrp[0].regs;
2081         local_irq_save(flags);
2082         lock_rx_qs(priv);
2083
2084         priv->vlgrp = grp;
2085
2086         if (grp) {
2087                 /* Enable VLAN tag insertion */
2088                 tempval = gfar_read(&regs->tctrl);
2089                 tempval |= TCTRL_VLINS;
2090
2091                 gfar_write(&regs->tctrl, tempval);
2092
2093                 /* Enable VLAN tag extraction */
2094                 tempval = gfar_read(&regs->rctrl);
2095                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2096                 gfar_write(&regs->rctrl, tempval);
2097         } else {
2098                 /* Disable VLAN tag insertion */
2099                 tempval = gfar_read(&regs->tctrl);
2100                 tempval &= ~TCTRL_VLINS;
2101                 gfar_write(&regs->tctrl, tempval);
2102
2103                 /* Disable VLAN tag extraction */
2104                 tempval = gfar_read(&regs->rctrl);
2105                 tempval &= ~RCTRL_VLEX;
2106                 /* If parse is no longer required, then disable parser */
2107                 if (tempval & RCTRL_REQ_PARSER)
2108                         tempval |= RCTRL_PRSDEP_INIT;
2109                 else
2110                         tempval &= ~RCTRL_PRSDEP_INIT;
2111                 gfar_write(&regs->rctrl, tempval);
2112         }
2113
2114         gfar_change_mtu(dev, dev->mtu);
2115
2116         unlock_rx_qs(priv);
2117         local_irq_restore(flags);
2118 }
2119
2120 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2121 {
2122         int tempsize, tempval;
2123         struct gfar_private *priv = netdev_priv(dev);
2124         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2125         int oldsize = priv->rx_buffer_size;
2126         int frame_size = new_mtu + ETH_HLEN;
2127
2128         if (priv->vlgrp)
2129                 frame_size += VLAN_HLEN;
2130
2131         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2132                 if (netif_msg_drv(priv))
2133                         printk(KERN_ERR "%s: Invalid MTU setting\n",
2134                                         dev->name);
2135                 return -EINVAL;
2136         }
2137
2138         if (gfar_uses_fcb(priv))
2139                 frame_size += GMAC_FCB_LEN;
2140
2141         frame_size += priv->padding;
2142
2143         tempsize =
2144             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2145             INCREMENTAL_BUFFER_SIZE;
2146
2147         /* Only stop and start the controller if it isn't already
2148          * stopped, and we changed something */
2149         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2150                 stop_gfar(dev);
2151
2152         priv->rx_buffer_size = tempsize;
2153
2154         dev->mtu = new_mtu;
2155
2156         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2157         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2158
2159         /* If the mtu is larger than the max size for standard
2160          * ethernet frames (ie, a jumbo frame), then set maccfg2
2161          * to allow huge frames, and to check the length */
2162         tempval = gfar_read(&regs->maccfg2);
2163
2164         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2165                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2166         else
2167                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2168
2169         gfar_write(&regs->maccfg2, tempval);
2170
2171         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2172                 startup_gfar(dev);
2173
2174         return 0;
2175 }
2176
2177 /* gfar_reset_task gets scheduled when a packet has not been
2178  * transmitted after a set amount of time.
2179  * For now, assume that clearing out all the structures, and
2180  * starting over will fix the problem.
2181  */
2182 static void gfar_reset_task(struct work_struct *work)
2183 {
2184         struct gfar_private *priv = container_of(work, struct gfar_private,
2185                         reset_task);
2186         struct net_device *dev = priv->ndev;
2187
2188         if (dev->flags & IFF_UP) {
2189                 netif_tx_stop_all_queues(dev);
2190                 stop_gfar(dev);
2191                 startup_gfar(dev);
2192                 netif_tx_start_all_queues(dev);
2193         }
2194
2195         netif_tx_schedule_all(dev);
2196 }
2197
2198 static void gfar_timeout(struct net_device *dev)
2199 {
2200         struct gfar_private *priv = netdev_priv(dev);
2201
2202         dev->stats.tx_errors++;
2203         schedule_work(&priv->reset_task);
2204 }
2205
2206 /* Interrupt Handler for Transmit complete */
2207 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2208 {
2209         struct net_device *dev = tx_queue->dev;
2210         struct gfar_private *priv = netdev_priv(dev);
2211         struct gfar_priv_rx_q *rx_queue = NULL;
2212         struct txbd8 *bdp;
2213         struct txbd8 *lbdp = NULL;
2214         struct txbd8 *base = tx_queue->tx_bd_base;
2215         struct sk_buff *skb;
2216         int skb_dirtytx;
2217         int tx_ring_size = tx_queue->tx_ring_size;
2218         int frags = 0;
2219         int i;
2220         int howmany = 0;
2221         u32 lstatus;
2222
2223         rx_queue = priv->rx_queue[tx_queue->qindex];
2224         bdp = tx_queue->dirty_tx;
2225         skb_dirtytx = tx_queue->skb_dirtytx;
2226
2227         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2228                 frags = skb_shinfo(skb)->nr_frags;
2229                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
2230
2231                 lstatus = lbdp->lstatus;
2232
2233                 /* Only clean completed frames */
2234                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2235                                 (lstatus & BD_LENGTH_MASK))
2236                         break;
2237
2238                 dma_unmap_single(&priv->ofdev->dev,
2239                                 bdp->bufPtr,
2240                                 bdp->length,
2241                                 DMA_TO_DEVICE);
2242
2243                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2244                 bdp = next_txbd(bdp, base, tx_ring_size);
2245
2246                 for (i = 0; i < frags; i++) {
2247                         dma_unmap_page(&priv->ofdev->dev,
2248                                         bdp->bufPtr,
2249                                         bdp->length,
2250                                         DMA_TO_DEVICE);
2251                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2252                         bdp = next_txbd(bdp, base, tx_ring_size);
2253                 }
2254
2255                 /*
2256                  * If there's room in the queue (limit it to rx_buffer_size)
2257                  * we add this skb back into the pool, if it's the right size
2258                  */
2259                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2260                                 skb_recycle_check(skb, priv->rx_buffer_size +
2261                                         RXBUF_ALIGNMENT))
2262                         __skb_queue_head(&priv->rx_recycle, skb);
2263                 else
2264                         dev_kfree_skb_any(skb);
2265
2266                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2267
2268                 skb_dirtytx = (skb_dirtytx + 1) &
2269                         TX_RING_MOD_MASK(tx_ring_size);
2270
2271                 howmany++;
2272                 tx_queue->num_txbdfree += frags + 1;
2273         }
2274
2275         /* If we freed a buffer, we can restart transmission, if necessary */
2276         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2277                 netif_wake_subqueue(dev, tx_queue->qindex);
2278
2279         /* Update dirty indicators */
2280         tx_queue->skb_dirtytx = skb_dirtytx;
2281         tx_queue->dirty_tx = bdp;
2282
2283         dev->stats.tx_packets += howmany;
2284
2285         return howmany;
2286 }
2287
2288 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2289 {
2290         unsigned long flags;
2291
2292         spin_lock_irqsave(&gfargrp->grplock, flags);
2293         if (napi_schedule_prep(&gfargrp->napi)) {
2294                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2295                 __napi_schedule(&gfargrp->napi);
2296         } else {
2297                 /*
2298                  * Clear IEVENT, so interrupts aren't called again
2299                  * because of the packets that have already arrived.
2300                  */
2301                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2302         }
2303         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2304
2305 }
2306
2307 /* Interrupt Handler for Transmit complete */
2308 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2309 {
2310         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2311         return IRQ_HANDLED;
2312 }
2313
2314 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2315                 struct sk_buff *skb)
2316 {
2317         struct net_device *dev = rx_queue->dev;
2318         struct gfar_private *priv = netdev_priv(dev);
2319         dma_addr_t buf;
2320
2321         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2322                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2323         gfar_init_rxbdp(rx_queue, bdp, buf);
2324 }
2325
2326
2327 struct sk_buff * gfar_new_skb(struct net_device *dev)
2328 {
2329         unsigned int alignamount;
2330         struct gfar_private *priv = netdev_priv(dev);
2331         struct sk_buff *skb = NULL;
2332
2333         skb = __skb_dequeue(&priv->rx_recycle);
2334         if (!skb)
2335                 skb = netdev_alloc_skb(dev,
2336                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
2337
2338         if (!skb)
2339                 return NULL;
2340
2341         alignamount = RXBUF_ALIGNMENT -
2342                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
2343
2344         /* We need the data buffer to be aligned properly.  We will reserve
2345          * as many bytes as needed to align the data properly
2346          */
2347         skb_reserve(skb, alignamount);
2348
2349         return skb;
2350 }
2351
2352 static inline void count_errors(unsigned short status, struct net_device *dev)
2353 {
2354         struct gfar_private *priv = netdev_priv(dev);
2355         struct net_device_stats *stats = &dev->stats;
2356         struct gfar_extra_stats *estats = &priv->extra_stats;
2357
2358         /* If the packet was truncated, none of the other errors
2359          * matter */
2360         if (status & RXBD_TRUNCATED) {
2361                 stats->rx_length_errors++;
2362
2363                 estats->rx_trunc++;
2364
2365                 return;
2366         }
2367         /* Count the errors, if there were any */
2368         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2369                 stats->rx_length_errors++;
2370
2371                 if (status & RXBD_LARGE)
2372                         estats->rx_large++;
2373                 else
2374                         estats->rx_short++;
2375         }
2376         if (status & RXBD_NONOCTET) {
2377                 stats->rx_frame_errors++;
2378                 estats->rx_nonoctet++;
2379         }
2380         if (status & RXBD_CRCERR) {
2381                 estats->rx_crcerr++;
2382                 stats->rx_crc_errors++;
2383         }
2384         if (status & RXBD_OVERRUN) {
2385                 estats->rx_overrun++;
2386                 stats->rx_crc_errors++;
2387         }
2388 }
2389
2390 irqreturn_t gfar_receive(int irq, void *grp_id)
2391 {
2392         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2393         return IRQ_HANDLED;
2394 }
2395
2396 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2397 {
2398         /* If valid headers were found, and valid sums
2399          * were verified, then we tell the kernel that no
2400          * checksumming is necessary.  Otherwise, it is */
2401         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2402                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2403         else
2404                 skb->ip_summed = CHECKSUM_NONE;
2405 }
2406
2407
2408 /* gfar_process_frame() -- handle one incoming packet if skb
2409  * isn't NULL.  */
2410 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2411                               int amount_pull)
2412 {
2413         struct gfar_private *priv = netdev_priv(dev);
2414         struct rxfcb *fcb = NULL;
2415
2416         int ret;
2417
2418         /* fcb is at the beginning if exists */
2419         fcb = (struct rxfcb *)skb->data;
2420
2421         /* Remove the FCB from the skb */
2422         skb_set_queue_mapping(skb, fcb->rq);
2423         /* Remove the padded bytes, if there are any */
2424         if (amount_pull)
2425                 skb_pull(skb, amount_pull);
2426
2427         if (priv->rx_csum_enable)
2428                 gfar_rx_checksum(skb, fcb);
2429
2430         /* Tell the skb what kind of packet this is */
2431         skb->protocol = eth_type_trans(skb, dev);
2432
2433         /* Send the packet up the stack */
2434         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2435                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2436         else
2437                 ret = netif_receive_skb(skb);
2438
2439         if (NET_RX_DROP == ret)
2440                 priv->extra_stats.kernel_dropped++;
2441
2442         return 0;
2443 }
2444
2445 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2446  *   until the budget/quota has been reached. Returns the number
2447  *   of frames handled
2448  */
2449 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2450 {
2451         struct net_device *dev = rx_queue->dev;
2452         struct rxbd8 *bdp, *base;
2453         struct sk_buff *skb;
2454         int pkt_len;
2455         int amount_pull;
2456         int howmany = 0;
2457         struct gfar_private *priv = netdev_priv(dev);
2458
2459         /* Get the first full descriptor */
2460         bdp = rx_queue->cur_rx;
2461         base = rx_queue->rx_bd_base;
2462
2463         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
2464                 priv->padding;
2465
2466         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2467                 struct sk_buff *newskb;
2468                 rmb();
2469
2470                 /* Add another skb for the future */
2471                 newskb = gfar_new_skb(dev);
2472
2473                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2474
2475                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2476                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2477
2478                 /* We drop the frame if we failed to allocate a new buffer */
2479                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2480                                  bdp->status & RXBD_ERR)) {
2481                         count_errors(bdp->status, dev);
2482
2483                         if (unlikely(!newskb))
2484                                 newskb = skb;
2485                         else if (skb) {
2486                                 /*
2487                                  * We need to reset ->data to what it
2488                                  * was before gfar_new_skb() re-aligned
2489                                  * it to an RXBUF_ALIGNMENT boundary
2490                                  * before we put the skb back on the
2491                                  * recycle list.
2492                                  */
2493                                 skb->data = skb->head + NET_SKB_PAD;
2494                                 __skb_queue_head(&priv->rx_recycle, skb);
2495                         }
2496                 } else {
2497                         /* Increment the number of packets */
2498                         dev->stats.rx_packets++;
2499                         howmany++;
2500
2501                         if (likely(skb)) {
2502                                 pkt_len = bdp->length - ETH_FCS_LEN;
2503                                 /* Remove the FCS from the packet length */
2504                                 skb_put(skb, pkt_len);
2505                                 dev->stats.rx_bytes += pkt_len;
2506
2507                                 if (in_irq() || irqs_disabled())
2508                                         printk("Interrupt problem!\n");
2509                                 gfar_process_frame(dev, skb, amount_pull);
2510
2511                         } else {
2512                                 if (netif_msg_rx_err(priv))
2513                                         printk(KERN_WARNING
2514                                                "%s: Missing skb!\n", dev->name);
2515                                 dev->stats.rx_dropped++;
2516                                 priv->extra_stats.rx_skbmissing++;
2517                         }
2518
2519                 }
2520
2521                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2522
2523                 /* Setup the new bdp */
2524                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2525
2526                 /* Update to the next pointer */
2527                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2528
2529                 /* update to point at the next skb */
2530                 rx_queue->skb_currx =
2531                     (rx_queue->skb_currx + 1) &
2532                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2533         }
2534
2535         /* Update the current rxbd pointer to be the next one */
2536         rx_queue->cur_rx = bdp;
2537
2538         return howmany;
2539 }
2540
2541 static int gfar_poll(struct napi_struct *napi, int budget)
2542 {
2543         struct gfar_priv_grp *gfargrp = container_of(napi,
2544                         struct gfar_priv_grp, napi);
2545         struct gfar_private *priv = gfargrp->priv;
2546         struct gfar __iomem *regs = gfargrp->regs;
2547         struct gfar_priv_tx_q *tx_queue = NULL;
2548         struct gfar_priv_rx_q *rx_queue = NULL;
2549         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2550         int tx_cleaned = 0, i, left_over_budget = budget;
2551         unsigned long serviced_queues = 0;
2552         int num_queues = 0;
2553         unsigned long flags;
2554
2555         num_queues = gfargrp->num_rx_queues;
2556         budget_per_queue = budget/num_queues;
2557
2558         /* Clear IEVENT, so interrupts aren't called again
2559          * because of the packets that have already arrived */
2560         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2561
2562         while (num_queues && left_over_budget) {
2563
2564                 budget_per_queue = left_over_budget/num_queues;
2565                 left_over_budget = 0;
2566
2567                 for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2568                         if (test_bit(i, &serviced_queues))
2569                                 continue;
2570                         rx_queue = priv->rx_queue[i];
2571                         tx_queue = priv->tx_queue[rx_queue->qindex];
2572
2573                         /* If we fail to get the lock,
2574                          * don't bother with the TX BDs */
2575                         if (spin_trylock_irqsave(&tx_queue->txlock, flags)) {
2576                                 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2577                                 spin_unlock_irqrestore(&tx_queue->txlock,
2578                                                         flags);
2579                         }
2580
2581                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2582                                                         budget_per_queue);
2583                         rx_cleaned += rx_cleaned_per_queue;
2584                         if(rx_cleaned_per_queue < budget_per_queue) {
2585                                 left_over_budget = left_over_budget +
2586                                         (budget_per_queue - rx_cleaned_per_queue);
2587                                 set_bit(i, &serviced_queues);
2588                                 num_queues--;
2589                         }
2590                 }
2591         }
2592
2593         if (tx_cleaned)
2594                 return budget;
2595
2596         if (rx_cleaned < budget) {
2597                 napi_complete(napi);
2598
2599                 /* Clear the halt bit in RSTAT */
2600                 gfar_write(&regs->rstat, gfargrp->rstat);
2601
2602                 gfar_write(&regs->imask, IMASK_DEFAULT);
2603
2604                 /* If we are coalescing interrupts, update the timer */
2605                 /* Otherwise, clear it */
2606                 gfar_configure_coalescing(priv,
2607                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2608         }
2609
2610         return rx_cleaned;
2611 }
2612
2613 #ifdef CONFIG_NET_POLL_CONTROLLER
2614 /*
2615  * Polling 'interrupt' - used by things like netconsole to send skbs
2616  * without having to re-enable interrupts. It's not called while
2617  * the interrupt routine is executing.
2618  */
2619 static void gfar_netpoll(struct net_device *dev)
2620 {
2621         struct gfar_private *priv = netdev_priv(dev);
2622         int i = 0;
2623
2624         /* If the device has multiple interrupts, run tx/rx */
2625         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2626                 for (i = 0; i < priv->num_grps; i++) {
2627                         disable_irq(priv->gfargrp[i].interruptTransmit);
2628                         disable_irq(priv->gfargrp[i].interruptReceive);
2629                         disable_irq(priv->gfargrp[i].interruptError);
2630                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2631                                                 &priv->gfargrp[i]);
2632                         enable_irq(priv->gfargrp[i].interruptError);
2633                         enable_irq(priv->gfargrp[i].interruptReceive);
2634                         enable_irq(priv->gfargrp[i].interruptTransmit);
2635                 }
2636         } else {
2637                 for (i = 0; i < priv->num_grps; i++) {
2638                         disable_irq(priv->gfargrp[i].interruptTransmit);
2639                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2640                                                 &priv->gfargrp[i]);
2641                         enable_irq(priv->gfargrp[i].interruptTransmit);
2642         }
2643 }
2644 #endif
2645
2646 /* The interrupt handler for devices with one interrupt */
2647 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2648 {
2649         struct gfar_priv_grp *gfargrp = grp_id;
2650
2651         /* Save ievent for future reference */
2652         u32 events = gfar_read(&gfargrp->regs->ievent);
2653
2654         /* Check for reception */
2655         if (events & IEVENT_RX_MASK)
2656                 gfar_receive(irq, grp_id);
2657
2658         /* Check for transmit completion */
2659         if (events & IEVENT_TX_MASK)
2660                 gfar_transmit(irq, grp_id);
2661
2662         /* Check for errors */
2663         if (events & IEVENT_ERR_MASK)
2664                 gfar_error(irq, grp_id);
2665
2666         return IRQ_HANDLED;
2667 }
2668
2669 /* Called every time the controller might need to be made
2670  * aware of new link state.  The PHY code conveys this
2671  * information through variables in the phydev structure, and this
2672  * function converts those variables into the appropriate
2673  * register values, and can bring down the device if needed.
2674  */
2675 static void adjust_link(struct net_device *dev)
2676 {
2677         struct gfar_private *priv = netdev_priv(dev);
2678         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2679         unsigned long flags;
2680         struct phy_device *phydev = priv->phydev;
2681         int new_state = 0;
2682
2683         local_irq_save(flags);
2684         lock_tx_qs(priv);
2685
2686         if (phydev->link) {
2687                 u32 tempval = gfar_read(&regs->maccfg2);
2688                 u32 ecntrl = gfar_read(&regs->ecntrl);
2689
2690                 /* Now we make sure that we can be in full duplex mode.
2691                  * If not, we operate in half-duplex mode. */
2692                 if (phydev->duplex != priv->oldduplex) {
2693                         new_state = 1;
2694                         if (!(phydev->duplex))
2695                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2696                         else
2697                                 tempval |= MACCFG2_FULL_DUPLEX;
2698
2699                         priv->oldduplex = phydev->duplex;
2700                 }
2701
2702                 if (phydev->speed != priv->oldspeed) {
2703                         new_state = 1;
2704                         switch (phydev->speed) {
2705                         case 1000:
2706                                 tempval =
2707                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2708
2709                                 ecntrl &= ~(ECNTRL_R100);
2710                                 break;
2711                         case 100:
2712                         case 10:
2713                                 tempval =
2714                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2715
2716                                 /* Reduced mode distinguishes
2717                                  * between 10 and 100 */
2718                                 if (phydev->speed == SPEED_100)
2719                                         ecntrl |= ECNTRL_R100;
2720                                 else
2721                                         ecntrl &= ~(ECNTRL_R100);
2722                                 break;
2723                         default:
2724                                 if (netif_msg_link(priv))
2725                                         printk(KERN_WARNING
2726                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2727                                                 dev->name, phydev->speed);
2728                                 break;
2729                         }
2730
2731                         priv->oldspeed = phydev->speed;
2732                 }
2733
2734                 gfar_write(&regs->maccfg2, tempval);
2735                 gfar_write(&regs->ecntrl, ecntrl);
2736
2737                 if (!priv->oldlink) {
2738                         new_state = 1;
2739                         priv->oldlink = 1;
2740                 }
2741         } else if (priv->oldlink) {
2742                 new_state = 1;
2743                 priv->oldlink = 0;
2744                 priv->oldspeed = 0;
2745                 priv->oldduplex = -1;
2746         }
2747
2748         if (new_state && netif_msg_link(priv))
2749                 phy_print_status(phydev);
2750         unlock_tx_qs(priv);
2751         local_irq_restore(flags);
2752 }
2753
2754 /* Update the hash table based on the current list of multicast
2755  * addresses we subscribe to.  Also, change the promiscuity of
2756  * the device based on the flags (this function is called
2757  * whenever dev->flags is changed */
2758 static void gfar_set_multi(struct net_device *dev)
2759 {
2760         struct dev_mc_list *mc_ptr;
2761         struct gfar_private *priv = netdev_priv(dev);
2762         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2763         u32 tempval;
2764
2765         if (dev->flags & IFF_PROMISC) {
2766                 /* Set RCTRL to PROM */
2767                 tempval = gfar_read(&regs->rctrl);
2768                 tempval |= RCTRL_PROM;
2769                 gfar_write(&regs->rctrl, tempval);
2770         } else {
2771                 /* Set RCTRL to not PROM */
2772                 tempval = gfar_read(&regs->rctrl);
2773                 tempval &= ~(RCTRL_PROM);
2774                 gfar_write(&regs->rctrl, tempval);
2775         }
2776
2777         if (dev->flags & IFF_ALLMULTI) {
2778                 /* Set the hash to rx all multicast frames */
2779                 gfar_write(&regs->igaddr0, 0xffffffff);
2780                 gfar_write(&regs->igaddr1, 0xffffffff);
2781                 gfar_write(&regs->igaddr2, 0xffffffff);
2782                 gfar_write(&regs->igaddr3, 0xffffffff);
2783                 gfar_write(&regs->igaddr4, 0xffffffff);
2784                 gfar_write(&regs->igaddr5, 0xffffffff);
2785                 gfar_write(&regs->igaddr6, 0xffffffff);
2786                 gfar_write(&regs->igaddr7, 0xffffffff);
2787                 gfar_write(&regs->gaddr0, 0xffffffff);
2788                 gfar_write(&regs->gaddr1, 0xffffffff);
2789                 gfar_write(&regs->gaddr2, 0xffffffff);
2790                 gfar_write(&regs->gaddr3, 0xffffffff);
2791                 gfar_write(&regs->gaddr4, 0xffffffff);
2792                 gfar_write(&regs->gaddr5, 0xffffffff);
2793                 gfar_write(&regs->gaddr6, 0xffffffff);
2794                 gfar_write(&regs->gaddr7, 0xffffffff);
2795         } else {
2796                 int em_num;
2797                 int idx;
2798
2799                 /* zero out the hash */
2800                 gfar_write(&regs->igaddr0, 0x0);
2801                 gfar_write(&regs->igaddr1, 0x0);
2802                 gfar_write(&regs->igaddr2, 0x0);
2803                 gfar_write(&regs->igaddr3, 0x0);
2804                 gfar_write(&regs->igaddr4, 0x0);
2805                 gfar_write(&regs->igaddr5, 0x0);
2806                 gfar_write(&regs->igaddr6, 0x0);
2807                 gfar_write(&regs->igaddr7, 0x0);
2808                 gfar_write(&regs->gaddr0, 0x0);
2809                 gfar_write(&regs->gaddr1, 0x0);
2810                 gfar_write(&regs->gaddr2, 0x0);
2811                 gfar_write(&regs->gaddr3, 0x0);
2812                 gfar_write(&regs->gaddr4, 0x0);
2813                 gfar_write(&regs->gaddr5, 0x0);
2814                 gfar_write(&regs->gaddr6, 0x0);
2815                 gfar_write(&regs->gaddr7, 0x0);
2816
2817                 /* If we have extended hash tables, we need to
2818                  * clear the exact match registers to prepare for
2819                  * setting them */
2820                 if (priv->extended_hash) {
2821                         em_num = GFAR_EM_NUM + 1;
2822                         gfar_clear_exact_match(dev);
2823                         idx = 1;
2824                 } else {
2825                         idx = 0;
2826                         em_num = 0;
2827                 }
2828
2829                 if (dev->mc_count == 0)
2830                         return;
2831
2832                 /* Parse the list, and set the appropriate bits */
2833                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2834                         if (idx < em_num) {
2835                                 gfar_set_mac_for_addr(dev, idx,
2836                                                 mc_ptr->dmi_addr);
2837                                 idx++;
2838                         } else
2839                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2840                 }
2841         }
2842
2843         return;
2844 }
2845
2846
2847 /* Clears each of the exact match registers to zero, so they
2848  * don't interfere with normal reception */
2849 static void gfar_clear_exact_match(struct net_device *dev)
2850 {
2851         int idx;
2852         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2853
2854         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2855                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2856 }
2857
2858 /* Set the appropriate hash bit for the given addr */
2859 /* The algorithm works like so:
2860  * 1) Take the Destination Address (ie the multicast address), and
2861  * do a CRC on it (little endian), and reverse the bits of the
2862  * result.
2863  * 2) Use the 8 most significant bits as a hash into a 256-entry
2864  * table.  The table is controlled through 8 32-bit registers:
2865  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2866  * gaddr7.  This means that the 3 most significant bits in the
2867  * hash index which gaddr register to use, and the 5 other bits
2868  * indicate which bit (assuming an IBM numbering scheme, which
2869  * for PowerPC (tm) is usually the case) in the register holds
2870  * the entry. */
2871 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2872 {
2873         u32 tempval;
2874         struct gfar_private *priv = netdev_priv(dev);
2875         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2876         int width = priv->hash_width;
2877         u8 whichbit = (result >> (32 - width)) & 0x1f;
2878         u8 whichreg = result >> (32 - width + 5);
2879         u32 value = (1 << (31-whichbit));
2880
2881         tempval = gfar_read(priv->hash_regs[whichreg]);
2882         tempval |= value;
2883         gfar_write(priv->hash_regs[whichreg], tempval);
2884
2885         return;
2886 }
2887
2888
2889 /* There are multiple MAC Address register pairs on some controllers
2890  * This function sets the numth pair to a given address
2891  */
2892 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2893 {
2894         struct gfar_private *priv = netdev_priv(dev);
2895         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2896         int idx;
2897         char tmpbuf[MAC_ADDR_LEN];
2898         u32 tempval;
2899         u32 __iomem *macptr = &regs->macstnaddr1;
2900
2901         macptr += num*2;
2902
2903         /* Now copy it into the mac registers backwards, cuz */
2904         /* little endian is silly */
2905         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2906                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2907
2908         gfar_write(macptr, *((u32 *) (tmpbuf)));
2909
2910         tempval = *((u32 *) (tmpbuf + 4));
2911
2912         gfar_write(macptr+1, tempval);
2913 }
2914
2915 /* GFAR error interrupt handler */
2916 static irqreturn_t gfar_error(int irq, void *grp_id)
2917 {
2918         struct gfar_priv_grp *gfargrp = grp_id;
2919         struct gfar __iomem *regs = gfargrp->regs;
2920         struct gfar_private *priv= gfargrp->priv;
2921         struct net_device *dev = priv->ndev;
2922
2923         /* Save ievent for future reference */
2924         u32 events = gfar_read(&regs->ievent);
2925
2926         /* Clear IEVENT */
2927         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
2928
2929         /* Magic Packet is not an error. */
2930         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2931             (events & IEVENT_MAG))
2932                 events &= ~IEVENT_MAG;
2933
2934         /* Hmm... */
2935         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2936                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2937                        dev->name, events, gfar_read(&regs->imask));
2938
2939         /* Update the error counters */
2940         if (events & IEVENT_TXE) {
2941                 dev->stats.tx_errors++;
2942
2943                 if (events & IEVENT_LC)
2944                         dev->stats.tx_window_errors++;
2945                 if (events & IEVENT_CRL)
2946                         dev->stats.tx_aborted_errors++;
2947                 if (events & IEVENT_XFUN) {
2948                         if (netif_msg_tx_err(priv))
2949                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2950                                        "packet dropped.\n", dev->name);
2951                         dev->stats.tx_dropped++;
2952                         priv->extra_stats.tx_underrun++;
2953
2954                         /* Reactivate the Tx Queues */
2955                         gfar_write(&regs->tstat, gfargrp->tstat);
2956                 }
2957                 if (netif_msg_tx_err(priv))
2958                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2959         }
2960         if (events & IEVENT_BSY) {
2961                 dev->stats.rx_errors++;
2962                 priv->extra_stats.rx_bsy++;
2963
2964                 gfar_receive(irq, grp_id);
2965
2966                 if (netif_msg_rx_err(priv))
2967                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2968                                dev->name, gfar_read(&regs->rstat));
2969         }
2970         if (events & IEVENT_BABR) {
2971                 dev->stats.rx_errors++;
2972                 priv->extra_stats.rx_babr++;
2973
2974                 if (netif_msg_rx_err(priv))
2975                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2976         }
2977         if (events & IEVENT_EBERR) {
2978                 priv->extra_stats.eberr++;
2979                 if (netif_msg_rx_err(priv))
2980                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2981         }
2982         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2983                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2984
2985         if (events & IEVENT_BABT) {
2986                 priv->extra_stats.tx_babt++;
2987                 if (netif_msg_tx_err(priv))
2988                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2989         }
2990         return IRQ_HANDLED;
2991 }
2992
2993 static struct of_device_id gfar_match[] =
2994 {
2995         {
2996                 .type = "network",
2997                 .compatible = "gianfar",
2998         },
2999         {
3000                 .compatible = "fsl,etsec2",
3001         },
3002         {},
3003 };
3004 MODULE_DEVICE_TABLE(of, gfar_match);
3005
3006 /* Structure for a device driver */
3007 static struct of_platform_driver gfar_driver = {
3008         .name = "fsl-gianfar",
3009         .match_table = gfar_match,
3010
3011         .probe = gfar_probe,
3012         .remove = gfar_remove,
3013         .suspend = gfar_legacy_suspend,
3014         .resume = gfar_legacy_resume,
3015         .driver.pm = GFAR_PM_OPS,
3016 };
3017
3018 static int __init gfar_init(void)
3019 {
3020         return of_register_platform_driver(&gfar_driver);
3021 }
3022
3023 static void __exit gfar_exit(void)
3024 {
3025         of_unregister_platform_driver(&gfar_driver);
3026 }
3027
3028 module_init(gfar_init);
3029 module_exit(gfar_exit);
3030