gianfar: Don't needlessly set the wrap bit for the last RX BD
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84
85 #include <asm/io.h>
86 #include <asm/irq.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
94 #include <linux/of.h>
95
96 #include "gianfar.h"
97 #include "fsl_pq_mdio.h"
98
99 #define TX_TIMEOUT      (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113                 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123                 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
132 #endif
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
136                               int amount_pull);
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138                                 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static const struct net_device_ops gfar_netdev_ops = {
151         .ndo_open = gfar_enet_open,
152         .ndo_start_xmit = gfar_start_xmit,
153         .ndo_stop = gfar_close,
154         .ndo_change_mtu = gfar_change_mtu,
155         .ndo_set_multicast_list = gfar_set_multi,
156         .ndo_tx_timeout = gfar_timeout,
157         .ndo_do_ioctl = gfar_ioctl,
158         .ndo_vlan_rx_register = gfar_vlan_rx_register,
159         .ndo_set_mac_address = eth_mac_addr,
160         .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162         .ndo_poll_controller = gfar_netpoll,
163 #endif
164 };
165
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
168 {
169         return priv->vlgrp || priv->rx_csum_enable;
170 }
171
172 static int gfar_of_init(struct net_device *dev)
173 {
174         const char *model;
175         const char *ctype;
176         const void *mac_addr;
177         u64 addr, size;
178         int err = 0;
179         struct gfar_private *priv = netdev_priv(dev);
180         struct device_node *np = priv->node;
181         const u32 *stash;
182         const u32 *stash_len;
183         const u32 *stash_idx;
184
185         if (!np || !of_device_is_available(np))
186                 return -ENODEV;
187
188         /* get a pointer to the register memory */
189         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190         priv->regs = ioremap(addr, size);
191
192         if (priv->regs == NULL)
193                 return -ENOMEM;
194
195         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
196
197         model = of_get_property(np, "model", NULL);
198
199         /* If we aren't the FEC we have multiple interrupts */
200         if (model && strcasecmp(model, "FEC")) {
201                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
202
203                 priv->interruptError = irq_of_parse_and_map(np, 2);
204
205                 if (priv->interruptTransmit < 0 ||
206                                 priv->interruptReceive < 0 ||
207                                 priv->interruptError < 0) {
208                         err = -EINVAL;
209                         goto err_out;
210                 }
211         }
212
213         stash = of_get_property(np, "bd-stash", NULL);
214
215         if(stash) {
216                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217                 priv->bd_stash_en = 1;
218         }
219
220         stash_len = of_get_property(np, "rx-stash-len", NULL);
221
222         if (stash_len)
223                 priv->rx_stash_size = *stash_len;
224
225         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
226
227         if (stash_idx)
228                 priv->rx_stash_index = *stash_idx;
229
230         if (stash_len || stash_idx)
231                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
232
233         mac_addr = of_get_mac_address(np);
234         if (mac_addr)
235                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
236
237         if (model && !strcasecmp(model, "TSEC"))
238                 priv->device_flags =
239                         FSL_GIANFAR_DEV_HAS_GIGABIT |
240                         FSL_GIANFAR_DEV_HAS_COALESCE |
241                         FSL_GIANFAR_DEV_HAS_RMON |
242                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243         if (model && !strcasecmp(model, "eTSEC"))
244                 priv->device_flags =
245                         FSL_GIANFAR_DEV_HAS_GIGABIT |
246                         FSL_GIANFAR_DEV_HAS_COALESCE |
247                         FSL_GIANFAR_DEV_HAS_RMON |
248                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249                         FSL_GIANFAR_DEV_HAS_PADDING |
250                         FSL_GIANFAR_DEV_HAS_CSUM |
251                         FSL_GIANFAR_DEV_HAS_VLAN |
252                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
254
255         ctype = of_get_property(np, "phy-connection-type", NULL);
256
257         /* We only care about rgmii-id.  The rest are autodetected */
258         if (ctype && !strcmp(ctype, "rgmii-id"))
259                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
260         else
261                 priv->interface = PHY_INTERFACE_MODE_MII;
262
263         if (of_get_property(np, "fsl,magic-packet", NULL))
264                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
265
266         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
267
268         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
269         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
270
271         return 0;
272
273 err_out:
274         iounmap(priv->regs);
275         return err;
276 }
277
278 /* Ioctl MII Interface */
279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
280 {
281         struct gfar_private *priv = netdev_priv(dev);
282
283         if (!netif_running(dev))
284                 return -EINVAL;
285
286         if (!priv->phydev)
287                 return -ENODEV;
288
289         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
290 }
291
292 /* Set up the ethernet device structure, private data,
293  * and anything else we need before we start */
294 static int gfar_probe(struct of_device *ofdev,
295                 const struct of_device_id *match)
296 {
297         u32 tempval;
298         struct net_device *dev = NULL;
299         struct gfar_private *priv = NULL;
300         int err = 0;
301         int len_devname;
302
303         /* Create an ethernet device instance */
304         dev = alloc_etherdev(sizeof (*priv));
305
306         if (NULL == dev)
307                 return -ENOMEM;
308
309         priv = netdev_priv(dev);
310         priv->ndev = dev;
311         priv->ofdev = ofdev;
312         priv->node = ofdev->node;
313         SET_NETDEV_DEV(dev, &ofdev->dev);
314
315         err = gfar_of_init(dev);
316
317         if (err)
318                 goto regs_fail;
319
320         spin_lock_init(&priv->txlock);
321         spin_lock_init(&priv->rxlock);
322         spin_lock_init(&priv->bflock);
323         INIT_WORK(&priv->reset_task, gfar_reset_task);
324
325         dev_set_drvdata(&ofdev->dev, priv);
326
327         /* Stop the DMA engine now, in case it was running before */
328         /* (The firmware could have used it, and left it running). */
329         gfar_halt(dev);
330
331         /* Reset MAC layer */
332         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
333
334         /* We need to delay at least 3 TX clocks */
335         udelay(2);
336
337         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
338         gfar_write(&priv->regs->maccfg1, tempval);
339
340         /* Initialize MACCFG2. */
341         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
342
343         /* Initialize ECNTRL */
344         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
345
346         /* Set the dev->base_addr to the gfar reg region */
347         dev->base_addr = (unsigned long) (priv->regs);
348
349         SET_NETDEV_DEV(dev, &ofdev->dev);
350
351         /* Fill in the dev structure */
352         dev->watchdog_timeo = TX_TIMEOUT;
353         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
354         dev->mtu = 1500;
355
356         dev->netdev_ops = &gfar_netdev_ops;
357         dev->ethtool_ops = &gfar_ethtool_ops;
358
359         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
360                 priv->rx_csum_enable = 1;
361                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
362         } else
363                 priv->rx_csum_enable = 0;
364
365         priv->vlgrp = NULL;
366
367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
368                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
369
370         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
371                 priv->extended_hash = 1;
372                 priv->hash_width = 9;
373
374                 priv->hash_regs[0] = &priv->regs->igaddr0;
375                 priv->hash_regs[1] = &priv->regs->igaddr1;
376                 priv->hash_regs[2] = &priv->regs->igaddr2;
377                 priv->hash_regs[3] = &priv->regs->igaddr3;
378                 priv->hash_regs[4] = &priv->regs->igaddr4;
379                 priv->hash_regs[5] = &priv->regs->igaddr5;
380                 priv->hash_regs[6] = &priv->regs->igaddr6;
381                 priv->hash_regs[7] = &priv->regs->igaddr7;
382                 priv->hash_regs[8] = &priv->regs->gaddr0;
383                 priv->hash_regs[9] = &priv->regs->gaddr1;
384                 priv->hash_regs[10] = &priv->regs->gaddr2;
385                 priv->hash_regs[11] = &priv->regs->gaddr3;
386                 priv->hash_regs[12] = &priv->regs->gaddr4;
387                 priv->hash_regs[13] = &priv->regs->gaddr5;
388                 priv->hash_regs[14] = &priv->regs->gaddr6;
389                 priv->hash_regs[15] = &priv->regs->gaddr7;
390
391         } else {
392                 priv->extended_hash = 0;
393                 priv->hash_width = 8;
394
395                 priv->hash_regs[0] = &priv->regs->gaddr0;
396                 priv->hash_regs[1] = &priv->regs->gaddr1;
397                 priv->hash_regs[2] = &priv->regs->gaddr2;
398                 priv->hash_regs[3] = &priv->regs->gaddr3;
399                 priv->hash_regs[4] = &priv->regs->gaddr4;
400                 priv->hash_regs[5] = &priv->regs->gaddr5;
401                 priv->hash_regs[6] = &priv->regs->gaddr6;
402                 priv->hash_regs[7] = &priv->regs->gaddr7;
403         }
404
405         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
406                 priv->padding = DEFAULT_PADDING;
407         else
408                 priv->padding = 0;
409
410         if (dev->features & NETIF_F_IP_CSUM)
411                 dev->hard_header_len += GMAC_FCB_LEN;
412
413         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
414         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
415         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
416         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
417
418         priv->txcoalescing = DEFAULT_TX_COALESCE;
419         priv->txic = DEFAULT_TXIC;
420         priv->rxcoalescing = DEFAULT_RX_COALESCE;
421         priv->rxic = DEFAULT_RXIC;
422
423         /* Enable most messages by default */
424         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
425
426         /* Carrier starts down, phylib will bring it up */
427         netif_carrier_off(dev);
428
429         err = register_netdev(dev);
430
431         if (err) {
432                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
433                                 dev->name);
434                 goto register_fail;
435         }
436
437         device_init_wakeup(&dev->dev,
438                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
439
440         /* fill out IRQ number and name fields */
441         len_devname = strlen(dev->name);
442         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
443         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
444                 strncpy(&priv->int_name_tx[len_devname],
445                         "_tx", sizeof("_tx") + 1);
446
447                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
448                 strncpy(&priv->int_name_rx[len_devname],
449                         "_rx", sizeof("_rx") + 1);
450
451                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
452                 strncpy(&priv->int_name_er[len_devname],
453                         "_er", sizeof("_er") + 1);
454         } else
455                 priv->int_name_tx[len_devname] = '\0';
456
457         /* Create all the sysfs files */
458         gfar_init_sysfs(dev);
459
460         /* Print out the device info */
461         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
462
463         /* Even more device info helps when determining which kernel */
464         /* provided which set of benchmarks. */
465         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
466         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
467                dev->name, priv->rx_ring_size, priv->tx_ring_size);
468
469         return 0;
470
471 register_fail:
472         iounmap(priv->regs);
473 regs_fail:
474         if (priv->phy_node)
475                 of_node_put(priv->phy_node);
476         if (priv->tbi_node)
477                 of_node_put(priv->tbi_node);
478         free_netdev(dev);
479         return err;
480 }
481
482 static int gfar_remove(struct of_device *ofdev)
483 {
484         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
485
486         if (priv->phy_node)
487                 of_node_put(priv->phy_node);
488         if (priv->tbi_node)
489                 of_node_put(priv->tbi_node);
490
491         dev_set_drvdata(&ofdev->dev, NULL);
492
493         unregister_netdev(priv->ndev);
494         iounmap(priv->regs);
495         free_netdev(priv->ndev);
496
497         return 0;
498 }
499
500 #ifdef CONFIG_PM
501 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
502 {
503         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
504         struct net_device *dev = priv->ndev;
505         unsigned long flags;
506         u32 tempval;
507
508         int magic_packet = priv->wol_en &&
509                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
510
511         netif_device_detach(dev);
512
513         if (netif_running(dev)) {
514                 spin_lock_irqsave(&priv->txlock, flags);
515                 spin_lock(&priv->rxlock);
516
517                 gfar_halt_nodisable(dev);
518
519                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
520                 tempval = gfar_read(&priv->regs->maccfg1);
521
522                 tempval &= ~MACCFG1_TX_EN;
523
524                 if (!magic_packet)
525                         tempval &= ~MACCFG1_RX_EN;
526
527                 gfar_write(&priv->regs->maccfg1, tempval);
528
529                 spin_unlock(&priv->rxlock);
530                 spin_unlock_irqrestore(&priv->txlock, flags);
531
532                 napi_disable(&priv->napi);
533
534                 if (magic_packet) {
535                         /* Enable interrupt on Magic Packet */
536                         gfar_write(&priv->regs->imask, IMASK_MAG);
537
538                         /* Enable Magic Packet mode */
539                         tempval = gfar_read(&priv->regs->maccfg2);
540                         tempval |= MACCFG2_MPEN;
541                         gfar_write(&priv->regs->maccfg2, tempval);
542                 } else {
543                         phy_stop(priv->phydev);
544                 }
545         }
546
547         return 0;
548 }
549
550 static int gfar_resume(struct of_device *ofdev)
551 {
552         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
553         struct net_device *dev = priv->ndev;
554         unsigned long flags;
555         u32 tempval;
556         int magic_packet = priv->wol_en &&
557                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
558
559         if (!netif_running(dev)) {
560                 netif_device_attach(dev);
561                 return 0;
562         }
563
564         if (!magic_packet && priv->phydev)
565                 phy_start(priv->phydev);
566
567         /* Disable Magic Packet mode, in case something
568          * else woke us up.
569          */
570
571         spin_lock_irqsave(&priv->txlock, flags);
572         spin_lock(&priv->rxlock);
573
574         tempval = gfar_read(&priv->regs->maccfg2);
575         tempval &= ~MACCFG2_MPEN;
576         gfar_write(&priv->regs->maccfg2, tempval);
577
578         gfar_start(dev);
579
580         spin_unlock(&priv->rxlock);
581         spin_unlock_irqrestore(&priv->txlock, flags);
582
583         netif_device_attach(dev);
584
585         napi_enable(&priv->napi);
586
587         return 0;
588 }
589 #else
590 #define gfar_suspend NULL
591 #define gfar_resume NULL
592 #endif
593
594 /* Reads the controller's registers to determine what interface
595  * connects it to the PHY.
596  */
597 static phy_interface_t gfar_get_interface(struct net_device *dev)
598 {
599         struct gfar_private *priv = netdev_priv(dev);
600         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
601
602         if (ecntrl & ECNTRL_SGMII_MODE)
603                 return PHY_INTERFACE_MODE_SGMII;
604
605         if (ecntrl & ECNTRL_TBI_MODE) {
606                 if (ecntrl & ECNTRL_REDUCED_MODE)
607                         return PHY_INTERFACE_MODE_RTBI;
608                 else
609                         return PHY_INTERFACE_MODE_TBI;
610         }
611
612         if (ecntrl & ECNTRL_REDUCED_MODE) {
613                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
614                         return PHY_INTERFACE_MODE_RMII;
615                 else {
616                         phy_interface_t interface = priv->interface;
617
618                         /*
619                          * This isn't autodetected right now, so it must
620                          * be set by the device tree or platform code.
621                          */
622                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
623                                 return PHY_INTERFACE_MODE_RGMII_ID;
624
625                         return PHY_INTERFACE_MODE_RGMII;
626                 }
627         }
628
629         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
630                 return PHY_INTERFACE_MODE_GMII;
631
632         return PHY_INTERFACE_MODE_MII;
633 }
634
635
636 /* Initializes driver's PHY state, and attaches to the PHY.
637  * Returns 0 on success.
638  */
639 static int init_phy(struct net_device *dev)
640 {
641         struct gfar_private *priv = netdev_priv(dev);
642         uint gigabit_support =
643                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
644                 SUPPORTED_1000baseT_Full : 0;
645         phy_interface_t interface;
646
647         priv->oldlink = 0;
648         priv->oldspeed = 0;
649         priv->oldduplex = -1;
650
651         interface = gfar_get_interface(dev);
652
653         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
654                                       interface);
655         if (!priv->phydev)
656                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
657                                                          interface);
658         if (!priv->phydev) {
659                 dev_err(&dev->dev, "could not attach to PHY\n");
660                 return -ENODEV;
661         }
662
663         if (interface == PHY_INTERFACE_MODE_SGMII)
664                 gfar_configure_serdes(dev);
665
666         /* Remove any features not supported by the controller */
667         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
668         priv->phydev->advertising = priv->phydev->supported;
669
670         return 0;
671 }
672
673 /*
674  * Initialize TBI PHY interface for communicating with the
675  * SERDES lynx PHY on the chip.  We communicate with this PHY
676  * through the MDIO bus on each controller, treating it as a
677  * "normal" PHY at the address found in the TBIPA register.  We assume
678  * that the TBIPA register is valid.  Either the MDIO bus code will set
679  * it to a value that doesn't conflict with other PHYs on the bus, or the
680  * value doesn't matter, as there are no other PHYs on the bus.
681  */
682 static void gfar_configure_serdes(struct net_device *dev)
683 {
684         struct gfar_private *priv = netdev_priv(dev);
685         struct phy_device *tbiphy;
686
687         if (!priv->tbi_node) {
688                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
689                                     "device tree specify a tbi-handle\n");
690                 return;
691         }
692
693         tbiphy = of_phy_find_device(priv->tbi_node);
694         if (!tbiphy) {
695                 dev_err(&dev->dev, "error: Could not get TBI device\n");
696                 return;
697         }
698
699         /*
700          * If the link is already up, we must already be ok, and don't need to
701          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
702          * everything for us?  Resetting it takes the link down and requires
703          * several seconds for it to come back.
704          */
705         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
706                 return;
707
708         /* Single clk mode, mii mode off(for serdes communication) */
709         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
710
711         phy_write(tbiphy, MII_ADVERTISE,
712                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
713                         ADVERTISE_1000XPSE_ASYM);
714
715         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
716                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
717 }
718
719 static void init_registers(struct net_device *dev)
720 {
721         struct gfar_private *priv = netdev_priv(dev);
722
723         /* Clear IEVENT */
724         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
725
726         /* Initialize IMASK */
727         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
728
729         /* Init hash registers to zero */
730         gfar_write(&priv->regs->igaddr0, 0);
731         gfar_write(&priv->regs->igaddr1, 0);
732         gfar_write(&priv->regs->igaddr2, 0);
733         gfar_write(&priv->regs->igaddr3, 0);
734         gfar_write(&priv->regs->igaddr4, 0);
735         gfar_write(&priv->regs->igaddr5, 0);
736         gfar_write(&priv->regs->igaddr6, 0);
737         gfar_write(&priv->regs->igaddr7, 0);
738
739         gfar_write(&priv->regs->gaddr0, 0);
740         gfar_write(&priv->regs->gaddr1, 0);
741         gfar_write(&priv->regs->gaddr2, 0);
742         gfar_write(&priv->regs->gaddr3, 0);
743         gfar_write(&priv->regs->gaddr4, 0);
744         gfar_write(&priv->regs->gaddr5, 0);
745         gfar_write(&priv->regs->gaddr6, 0);
746         gfar_write(&priv->regs->gaddr7, 0);
747
748         /* Zero out the rmon mib registers if it has them */
749         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
750                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
751
752                 /* Mask off the CAM interrupts */
753                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
754                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
755         }
756
757         /* Initialize the max receive buffer length */
758         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
759
760         /* Initialize the Minimum Frame Length Register */
761         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
762 }
763
764
765 /* Halt the receive and transmit queues */
766 static void gfar_halt_nodisable(struct net_device *dev)
767 {
768         struct gfar_private *priv = netdev_priv(dev);
769         struct gfar __iomem *regs = priv->regs;
770         u32 tempval;
771
772         /* Mask all interrupts */
773         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
774
775         /* Clear all interrupts */
776         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
777
778         /* Stop the DMA, and wait for it to stop */
779         tempval = gfar_read(&priv->regs->dmactrl);
780         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
781             != (DMACTRL_GRS | DMACTRL_GTS)) {
782                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
783                 gfar_write(&priv->regs->dmactrl, tempval);
784
785                 while (!(gfar_read(&priv->regs->ievent) &
786                          (IEVENT_GRSC | IEVENT_GTSC)))
787                         cpu_relax();
788         }
789 }
790
791 /* Halt the receive and transmit queues */
792 void gfar_halt(struct net_device *dev)
793 {
794         struct gfar_private *priv = netdev_priv(dev);
795         struct gfar __iomem *regs = priv->regs;
796         u32 tempval;
797
798         gfar_halt_nodisable(dev);
799
800         /* Disable Rx and Tx */
801         tempval = gfar_read(&regs->maccfg1);
802         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
803         gfar_write(&regs->maccfg1, tempval);
804 }
805
806 void stop_gfar(struct net_device *dev)
807 {
808         struct gfar_private *priv = netdev_priv(dev);
809         unsigned long flags;
810
811         phy_stop(priv->phydev);
812
813         /* Lock it down */
814         spin_lock_irqsave(&priv->txlock, flags);
815         spin_lock(&priv->rxlock);
816
817         gfar_halt(dev);
818
819         spin_unlock(&priv->rxlock);
820         spin_unlock_irqrestore(&priv->txlock, flags);
821
822         /* Free the IRQs */
823         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
824                 free_irq(priv->interruptError, dev);
825                 free_irq(priv->interruptTransmit, dev);
826                 free_irq(priv->interruptReceive, dev);
827         } else {
828                 free_irq(priv->interruptTransmit, dev);
829         }
830
831         free_skb_resources(priv);
832 }
833
834 /* If there are any tx skbs or rx skbs still around, free them.
835  * Then free tx_skbuff and rx_skbuff */
836 static void free_skb_resources(struct gfar_private *priv)
837 {
838         struct device *dev = &priv->ofdev->dev;
839         struct rxbd8 *rxbdp;
840         struct txbd8 *txbdp;
841         int i, j;
842
843         /* Go through all the buffer descriptors and free their data buffers */
844         txbdp = priv->tx_bd_base;
845
846         if (!priv->tx_skbuff)
847                 goto skip_tx_skbuff;
848
849         for (i = 0; i < priv->tx_ring_size; i++) {
850                 if (!priv->tx_skbuff[i])
851                         continue;
852
853                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
854                                 txbdp->length, DMA_TO_DEVICE);
855                 txbdp->lstatus = 0;
856                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
857                         txbdp++;
858                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
859                                         txbdp->length, DMA_TO_DEVICE);
860                 }
861                 txbdp++;
862                 dev_kfree_skb_any(priv->tx_skbuff[i]);
863                 priv->tx_skbuff[i] = NULL;
864         }
865
866         kfree(priv->tx_skbuff);
867 skip_tx_skbuff:
868
869         rxbdp = priv->rx_bd_base;
870
871         if (!priv->rx_skbuff)
872                 goto skip_rx_skbuff;
873
874         for (i = 0; i < priv->rx_ring_size; i++) {
875                 if (priv->rx_skbuff[i]) {
876                         dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
877                                          priv->rx_buffer_size,
878                                         DMA_FROM_DEVICE);
879                         dev_kfree_skb_any(priv->rx_skbuff[i]);
880                         priv->rx_skbuff[i] = NULL;
881                 }
882
883                 rxbdp->lstatus = 0;
884                 rxbdp->bufPtr = 0;
885                 rxbdp++;
886         }
887
888         kfree(priv->rx_skbuff);
889 skip_rx_skbuff:
890
891         dma_free_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
892                                sizeof(*rxbdp) * priv->rx_ring_size,
893                           priv->tx_bd_base, gfar_read(&priv->regs->tbase0));
894 }
895
896 void gfar_start(struct net_device *dev)
897 {
898         struct gfar_private *priv = netdev_priv(dev);
899         struct gfar __iomem *regs = priv->regs;
900         u32 tempval;
901
902         /* Enable Rx and Tx in MACCFG1 */
903         tempval = gfar_read(&regs->maccfg1);
904         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
905         gfar_write(&regs->maccfg1, tempval);
906
907         /* Initialize DMACTRL to have WWR and WOP */
908         tempval = gfar_read(&priv->regs->dmactrl);
909         tempval |= DMACTRL_INIT_SETTINGS;
910         gfar_write(&priv->regs->dmactrl, tempval);
911
912         /* Make sure we aren't stopped */
913         tempval = gfar_read(&priv->regs->dmactrl);
914         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
915         gfar_write(&priv->regs->dmactrl, tempval);
916
917         /* Clear THLT/RHLT, so that the DMA starts polling now */
918         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
919         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
920
921         /* Unmask the interrupts we look for */
922         gfar_write(&regs->imask, IMASK_DEFAULT);
923
924         dev->trans_start = jiffies;
925 }
926
927 /* Bring the controller up and running */
928 int startup_gfar(struct net_device *ndev)
929 {
930         struct txbd8 *txbdp;
931         struct rxbd8 *rxbdp;
932         dma_addr_t addr = 0;
933         void *vaddr;
934         int i;
935         struct gfar_private *priv = netdev_priv(ndev);
936         struct device *dev = &priv->ofdev->dev;
937         struct gfar __iomem *regs = priv->regs;
938         int err;
939         u32 rctrl = 0;
940         u32 tctrl = 0;
941         u32 attrs = 0;
942
943         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
944
945         /* Allocate memory for the buffer descriptors */
946         vaddr = dma_alloc_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size +
947                                         sizeof(*rxbdp) * priv->rx_ring_size,
948                                    &addr, GFP_KERNEL);
949         if (!vaddr) {
950                 if (netif_msg_ifup(priv))
951                         pr_err("%s: Could not allocate buffer descriptors!\n",
952                                ndev->name);
953                 return -ENOMEM;
954         }
955
956         priv->tx_bd_base = vaddr;
957
958         /* enet DMA only understands physical addresses */
959         gfar_write(&regs->tbase0, addr);
960
961         /* Start the rx descriptor ring where the tx ring leaves off */
962         addr = addr + sizeof(*txbdp) * priv->tx_ring_size;
963         vaddr = vaddr + sizeof(*txbdp) * priv->tx_ring_size;
964         priv->rx_bd_base = vaddr;
965         gfar_write(&regs->rbase0, addr);
966
967         /* Setup the skbuff rings */
968         priv->tx_skbuff = kmalloc(sizeof(*priv->tx_skbuff) *
969                                   priv->tx_ring_size, GFP_KERNEL);
970         if (!priv->tx_skbuff) {
971                 if (netif_msg_ifup(priv))
972                         pr_err("%s: Could not allocate tx_skbuff\n",
973                                ndev->name);
974                 err = -ENOMEM;
975                 goto tx_skb_fail;
976         }
977
978         for (i = 0; i < priv->tx_ring_size; i++)
979                 priv->tx_skbuff[i] = NULL;
980
981         priv->rx_skbuff = kmalloc(sizeof(*priv->rx_skbuff) *
982                                   priv->rx_ring_size, GFP_KERNEL);
983         if (!priv->rx_skbuff) {
984                 if (netif_msg_ifup(priv))
985                         pr_err("%s: Could not allocate rx_skbuff\n",
986                                ndev->name);
987                 err = -ENOMEM;
988                 goto rx_skb_fail;
989         }
990
991         for (i = 0; i < priv->rx_ring_size; i++)
992                 priv->rx_skbuff[i] = NULL;
993
994         /* Initialize some variables in our dev structure */
995         priv->num_txbdfree = priv->tx_ring_size;
996         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
997         priv->cur_rx = priv->rx_bd_base;
998         priv->skb_curtx = priv->skb_dirtytx = 0;
999         priv->skb_currx = 0;
1000
1001         /* Initialize Transmit Descriptor Ring */
1002         txbdp = priv->tx_bd_base;
1003         for (i = 0; i < priv->tx_ring_size; i++) {
1004                 txbdp->lstatus = 0;
1005                 txbdp->bufPtr = 0;
1006                 txbdp++;
1007         }
1008
1009         /* Set the last descriptor in the ring to indicate wrap */
1010         txbdp--;
1011         txbdp->status |= TXBD_WRAP;
1012
1013         rxbdp = priv->rx_bd_base;
1014         for (i = 0; i < priv->rx_ring_size; i++) {
1015                 struct sk_buff *skb;
1016
1017                 skb = gfar_new_skb(ndev);
1018                 if (!skb) {
1019                         pr_err("%s: Can't allocate RX buffers\n", ndev->name);
1020                         err = -ENOMEM;
1021                         goto err_rxalloc_fail;
1022                 }
1023
1024                 priv->rx_skbuff[i] = skb;
1025
1026                 gfar_new_rxbdp(ndev, rxbdp, skb);
1027
1028                 rxbdp++;
1029         }
1030
1031         /* If the device has multiple interrupts, register for
1032          * them.  Otherwise, only register for the one */
1033         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1034                 /* Install our interrupt handlers for Error,
1035                  * Transmit, and Receive */
1036                 err = request_irq(priv->interruptError, gfar_error, 0,
1037                                   priv->int_name_er, ndev);
1038                 if (err) {
1039                         if (netif_msg_intr(priv))
1040                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1041                                        priv->interruptError);
1042                         goto err_irq_fail;
1043                 }
1044
1045                 err = request_irq(priv->interruptTransmit, gfar_transmit, 0,
1046                                   priv->int_name_tx, ndev);
1047                 if (err) {
1048                         if (netif_msg_intr(priv))
1049                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1050                                        priv->interruptTransmit);
1051                         goto tx_irq_fail;
1052                 }
1053
1054                 err = request_irq(priv->interruptReceive, gfar_receive, 0,
1055                                   priv->int_name_rx, ndev);
1056                 if (err) {
1057                         if (netif_msg_intr(priv))
1058                                 pr_err("%s: Can't get IRQ %d (receive0)\n",
1059                                        ndev->name, priv->interruptReceive);
1060                         goto rx_irq_fail;
1061                 }
1062         } else {
1063                 err = request_irq(priv->interruptTransmit, gfar_interrupt,
1064                                 0, priv->int_name_tx, ndev);
1065                 if (err) {
1066                         if (netif_msg_intr(priv))
1067                                 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1068                                        priv->interruptTransmit);
1069                         goto err_irq_fail;
1070                 }
1071         }
1072
1073         phy_start(priv->phydev);
1074
1075         /* Configure the coalescing support */
1076         gfar_write(&regs->txic, 0);
1077         if (priv->txcoalescing)
1078                 gfar_write(&regs->txic, priv->txic);
1079
1080         gfar_write(&regs->rxic, 0);
1081         if (priv->rxcoalescing)
1082                 gfar_write(&regs->rxic, priv->rxic);
1083
1084         if (priv->rx_csum_enable)
1085                 rctrl |= RCTRL_CHECKSUMMING;
1086
1087         if (priv->extended_hash) {
1088                 rctrl |= RCTRL_EXTHASH;
1089
1090                 gfar_clear_exact_match(ndev);
1091                 rctrl |= RCTRL_EMEN;
1092         }
1093
1094         if (priv->padding) {
1095                 rctrl &= ~RCTRL_PAL_MASK;
1096                 rctrl |= RCTRL_PADDING(priv->padding);
1097         }
1098
1099         /* keep vlan related bits if it's enabled */
1100         if (priv->vlgrp) {
1101                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
1102                 tctrl |= TCTRL_VLINS;
1103         }
1104
1105         /* Init rctrl based on our settings */
1106         gfar_write(&regs->rctrl, rctrl);
1107
1108         if (ndev->features & NETIF_F_IP_CSUM)
1109                 tctrl |= TCTRL_INIT_CSUM;
1110
1111         gfar_write(&regs->tctrl, tctrl);
1112
1113         /* Set the extraction length and index */
1114         attrs = ATTRELI_EL(priv->rx_stash_size) |
1115                 ATTRELI_EI(priv->rx_stash_index);
1116
1117         gfar_write(&regs->attreli, attrs);
1118
1119         /* Start with defaults, and add stashing or locking
1120          * depending on the approprate variables */
1121         attrs = ATTR_INIT_SETTINGS;
1122
1123         if (priv->bd_stash_en)
1124                 attrs |= ATTR_BDSTASH;
1125
1126         if (priv->rx_stash_size != 0)
1127                 attrs |= ATTR_BUFSTASH;
1128
1129         gfar_write(&regs->attr, attrs);
1130
1131         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
1132         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
1133         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1134
1135         /* Start the controller */
1136         gfar_start(ndev);
1137
1138         return 0;
1139
1140 rx_irq_fail:
1141         free_irq(priv->interruptTransmit, ndev);
1142 tx_irq_fail:
1143         free_irq(priv->interruptError, ndev);
1144 err_irq_fail:
1145 err_rxalloc_fail:
1146 rx_skb_fail:
1147 tx_skb_fail:
1148         free_skb_resources(priv);
1149         return err;
1150 }
1151
1152 /* Called when something needs to use the ethernet device */
1153 /* Returns 0 for success. */
1154 static int gfar_enet_open(struct net_device *dev)
1155 {
1156         struct gfar_private *priv = netdev_priv(dev);
1157         int err;
1158
1159         napi_enable(&priv->napi);
1160
1161         skb_queue_head_init(&priv->rx_recycle);
1162
1163         /* Initialize a bunch of registers */
1164         init_registers(dev);
1165
1166         gfar_set_mac_address(dev);
1167
1168         err = init_phy(dev);
1169
1170         if(err) {
1171                 napi_disable(&priv->napi);
1172                 return err;
1173         }
1174
1175         err = startup_gfar(dev);
1176         if (err) {
1177                 napi_disable(&priv->napi);
1178                 return err;
1179         }
1180
1181         netif_start_queue(dev);
1182
1183         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1184
1185         return err;
1186 }
1187
1188 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1189 {
1190         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1191
1192         memset(fcb, 0, GMAC_FCB_LEN);
1193
1194         return fcb;
1195 }
1196
1197 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1198 {
1199         u8 flags = 0;
1200
1201         /* If we're here, it's a IP packet with a TCP or UDP
1202          * payload.  We set it to checksum, using a pseudo-header
1203          * we provide
1204          */
1205         flags = TXFCB_DEFAULT;
1206
1207         /* Tell the controller what the protocol is */
1208         /* And provide the already calculated phcs */
1209         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1210                 flags |= TXFCB_UDP;
1211                 fcb->phcs = udp_hdr(skb)->check;
1212         } else
1213                 fcb->phcs = tcp_hdr(skb)->check;
1214
1215         /* l3os is the distance between the start of the
1216          * frame (skb->data) and the start of the IP hdr.
1217          * l4os is the distance between the start of the
1218          * l3 hdr and the l4 hdr */
1219         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1220         fcb->l4os = skb_network_header_len(skb);
1221
1222         fcb->flags = flags;
1223 }
1224
1225 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1226 {
1227         fcb->flags |= TXFCB_VLN;
1228         fcb->vlctl = vlan_tx_tag_get(skb);
1229 }
1230
1231 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1232                                struct txbd8 *base, int ring_size)
1233 {
1234         struct txbd8 *new_bd = bdp + stride;
1235
1236         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1237 }
1238
1239 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1240                 int ring_size)
1241 {
1242         return skip_txbd(bdp, 1, base, ring_size);
1243 }
1244
1245 /* This is called by the kernel when a frame is ready for transmission. */
1246 /* It is pointed to by the dev->hard_start_xmit function pointer */
1247 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1248 {
1249         struct gfar_private *priv = netdev_priv(dev);
1250         struct txfcb *fcb = NULL;
1251         struct txbd8 *txbdp, *txbdp_start, *base;
1252         u32 lstatus;
1253         int i;
1254         u32 bufaddr;
1255         unsigned long flags;
1256         unsigned int nr_frags, length;
1257
1258         base = priv->tx_bd_base;
1259
1260         /* make space for additional header when fcb is needed */
1261         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1262                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1263                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1264                 struct sk_buff *skb_new;
1265
1266                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1267                 if (!skb_new) {
1268                         dev->stats.tx_errors++;
1269                         kfree_skb(skb);
1270                         return NETDEV_TX_OK;
1271                 }
1272                 kfree_skb(skb);
1273                 skb = skb_new;
1274         }
1275
1276         /* total number of fragments in the SKB */
1277         nr_frags = skb_shinfo(skb)->nr_frags;
1278
1279         spin_lock_irqsave(&priv->txlock, flags);
1280
1281         /* check if there is space to queue this packet */
1282         if ((nr_frags+1) > priv->num_txbdfree) {
1283                 /* no space, stop the queue */
1284                 netif_stop_queue(dev);
1285                 dev->stats.tx_fifo_errors++;
1286                 spin_unlock_irqrestore(&priv->txlock, flags);
1287                 return NETDEV_TX_BUSY;
1288         }
1289
1290         /* Update transmit stats */
1291         dev->stats.tx_bytes += skb->len;
1292
1293         txbdp = txbdp_start = priv->cur_tx;
1294
1295         if (nr_frags == 0) {
1296                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1297         } else {
1298                 /* Place the fragment addresses and lengths into the TxBDs */
1299                 for (i = 0; i < nr_frags; i++) {
1300                         /* Point at the next BD, wrapping as needed */
1301                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1302
1303                         length = skb_shinfo(skb)->frags[i].size;
1304
1305                         lstatus = txbdp->lstatus | length |
1306                                 BD_LFLAG(TXBD_READY);
1307
1308                         /* Handle the last BD specially */
1309                         if (i == nr_frags - 1)
1310                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1311
1312                         bufaddr = dma_map_page(&priv->ofdev->dev,
1313                                         skb_shinfo(skb)->frags[i].page,
1314                                         skb_shinfo(skb)->frags[i].page_offset,
1315                                         length,
1316                                         DMA_TO_DEVICE);
1317
1318                         /* set the TxBD length and buffer pointer */
1319                         txbdp->bufPtr = bufaddr;
1320                         txbdp->lstatus = lstatus;
1321                 }
1322
1323                 lstatus = txbdp_start->lstatus;
1324         }
1325
1326         /* Set up checksumming */
1327         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1328                 fcb = gfar_add_fcb(skb);
1329                 lstatus |= BD_LFLAG(TXBD_TOE);
1330                 gfar_tx_checksum(skb, fcb);
1331         }
1332
1333         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1334                 if (unlikely(NULL == fcb)) {
1335                         fcb = gfar_add_fcb(skb);
1336                         lstatus |= BD_LFLAG(TXBD_TOE);
1337                 }
1338
1339                 gfar_tx_vlan(skb, fcb);
1340         }
1341
1342         /* setup the TxBD length and buffer pointer for the first BD */
1343         priv->tx_skbuff[priv->skb_curtx] = skb;
1344         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1345                         skb_headlen(skb), DMA_TO_DEVICE);
1346
1347         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1348
1349         /*
1350          * The powerpc-specific eieio() is used, as wmb() has too strong
1351          * semantics (it requires synchronization between cacheable and
1352          * uncacheable mappings, which eieio doesn't provide and which we
1353          * don't need), thus requiring a more expensive sync instruction.  At
1354          * some point, the set of architecture-independent barrier functions
1355          * should be expanded to include weaker barriers.
1356          */
1357         eieio();
1358
1359         txbdp_start->lstatus = lstatus;
1360
1361         /* Update the current skb pointer to the next entry we will use
1362          * (wrapping if necessary) */
1363         priv->skb_curtx = (priv->skb_curtx + 1) &
1364                 TX_RING_MOD_MASK(priv->tx_ring_size);
1365
1366         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1367
1368         /* reduce TxBD free count */
1369         priv->num_txbdfree -= (nr_frags + 1);
1370
1371         dev->trans_start = jiffies;
1372
1373         /* If the next BD still needs to be cleaned up, then the bds
1374            are full.  We need to tell the kernel to stop sending us stuff. */
1375         if (!priv->num_txbdfree) {
1376                 netif_stop_queue(dev);
1377
1378                 dev->stats.tx_fifo_errors++;
1379         }
1380
1381         /* Tell the DMA to go go go */
1382         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1383
1384         /* Unlock priv */
1385         spin_unlock_irqrestore(&priv->txlock, flags);
1386
1387         return NETDEV_TX_OK;
1388 }
1389
1390 /* Stops the kernel queue, and halts the controller */
1391 static int gfar_close(struct net_device *dev)
1392 {
1393         struct gfar_private *priv = netdev_priv(dev);
1394
1395         napi_disable(&priv->napi);
1396
1397         skb_queue_purge(&priv->rx_recycle);
1398         cancel_work_sync(&priv->reset_task);
1399         stop_gfar(dev);
1400
1401         /* Disconnect from the PHY */
1402         phy_disconnect(priv->phydev);
1403         priv->phydev = NULL;
1404
1405         netif_stop_queue(dev);
1406
1407         return 0;
1408 }
1409
1410 /* Changes the mac address if the controller is not running. */
1411 static int gfar_set_mac_address(struct net_device *dev)
1412 {
1413         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1414
1415         return 0;
1416 }
1417
1418
1419 /* Enables and disables VLAN insertion/extraction */
1420 static void gfar_vlan_rx_register(struct net_device *dev,
1421                 struct vlan_group *grp)
1422 {
1423         struct gfar_private *priv = netdev_priv(dev);
1424         unsigned long flags;
1425         u32 tempval;
1426
1427         spin_lock_irqsave(&priv->rxlock, flags);
1428
1429         priv->vlgrp = grp;
1430
1431         if (grp) {
1432                 /* Enable VLAN tag insertion */
1433                 tempval = gfar_read(&priv->regs->tctrl);
1434                 tempval |= TCTRL_VLINS;
1435
1436                 gfar_write(&priv->regs->tctrl, tempval);
1437
1438                 /* Enable VLAN tag extraction */
1439                 tempval = gfar_read(&priv->regs->rctrl);
1440                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1441                 gfar_write(&priv->regs->rctrl, tempval);
1442         } else {
1443                 /* Disable VLAN tag insertion */
1444                 tempval = gfar_read(&priv->regs->tctrl);
1445                 tempval &= ~TCTRL_VLINS;
1446                 gfar_write(&priv->regs->tctrl, tempval);
1447
1448                 /* Disable VLAN tag extraction */
1449                 tempval = gfar_read(&priv->regs->rctrl);
1450                 tempval &= ~RCTRL_VLEX;
1451                 /* If parse is no longer required, then disable parser */
1452                 if (tempval & RCTRL_REQ_PARSER)
1453                         tempval |= RCTRL_PRSDEP_INIT;
1454                 else
1455                         tempval &= ~RCTRL_PRSDEP_INIT;
1456                 gfar_write(&priv->regs->rctrl, tempval);
1457         }
1458
1459         gfar_change_mtu(dev, dev->mtu);
1460
1461         spin_unlock_irqrestore(&priv->rxlock, flags);
1462 }
1463
1464 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1465 {
1466         int tempsize, tempval;
1467         struct gfar_private *priv = netdev_priv(dev);
1468         int oldsize = priv->rx_buffer_size;
1469         int frame_size = new_mtu + ETH_HLEN;
1470
1471         if (priv->vlgrp)
1472                 frame_size += VLAN_HLEN;
1473
1474         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1475                 if (netif_msg_drv(priv))
1476                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1477                                         dev->name);
1478                 return -EINVAL;
1479         }
1480
1481         if (gfar_uses_fcb(priv))
1482                 frame_size += GMAC_FCB_LEN;
1483
1484         frame_size += priv->padding;
1485
1486         tempsize =
1487             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1488             INCREMENTAL_BUFFER_SIZE;
1489
1490         /* Only stop and start the controller if it isn't already
1491          * stopped, and we changed something */
1492         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1493                 stop_gfar(dev);
1494
1495         priv->rx_buffer_size = tempsize;
1496
1497         dev->mtu = new_mtu;
1498
1499         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1500         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1501
1502         /* If the mtu is larger than the max size for standard
1503          * ethernet frames (ie, a jumbo frame), then set maccfg2
1504          * to allow huge frames, and to check the length */
1505         tempval = gfar_read(&priv->regs->maccfg2);
1506
1507         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1508                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1509         else
1510                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1511
1512         gfar_write(&priv->regs->maccfg2, tempval);
1513
1514         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1515                 startup_gfar(dev);
1516
1517         return 0;
1518 }
1519
1520 /* gfar_reset_task gets scheduled when a packet has not been
1521  * transmitted after a set amount of time.
1522  * For now, assume that clearing out all the structures, and
1523  * starting over will fix the problem.
1524  */
1525 static void gfar_reset_task(struct work_struct *work)
1526 {
1527         struct gfar_private *priv = container_of(work, struct gfar_private,
1528                         reset_task);
1529         struct net_device *dev = priv->ndev;
1530
1531         if (dev->flags & IFF_UP) {
1532                 netif_stop_queue(dev);
1533                 stop_gfar(dev);
1534                 startup_gfar(dev);
1535                 netif_start_queue(dev);
1536         }
1537
1538         netif_tx_schedule_all(dev);
1539 }
1540
1541 static void gfar_timeout(struct net_device *dev)
1542 {
1543         struct gfar_private *priv = netdev_priv(dev);
1544
1545         dev->stats.tx_errors++;
1546         schedule_work(&priv->reset_task);
1547 }
1548
1549 /* Interrupt Handler for Transmit complete */
1550 static int gfar_clean_tx_ring(struct net_device *dev)
1551 {
1552         struct gfar_private *priv = netdev_priv(dev);
1553         struct txbd8 *bdp;
1554         struct txbd8 *lbdp = NULL;
1555         struct txbd8 *base = priv->tx_bd_base;
1556         struct sk_buff *skb;
1557         int skb_dirtytx;
1558         int tx_ring_size = priv->tx_ring_size;
1559         int frags = 0;
1560         int i;
1561         int howmany = 0;
1562         u32 lstatus;
1563
1564         bdp = priv->dirty_tx;
1565         skb_dirtytx = priv->skb_dirtytx;
1566
1567         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1568                 frags = skb_shinfo(skb)->nr_frags;
1569                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1570
1571                 lstatus = lbdp->lstatus;
1572
1573                 /* Only clean completed frames */
1574                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1575                                 (lstatus & BD_LENGTH_MASK))
1576                         break;
1577
1578                 dma_unmap_single(&priv->ofdev->dev,
1579                                 bdp->bufPtr,
1580                                 bdp->length,
1581                                 DMA_TO_DEVICE);
1582
1583                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1584                 bdp = next_txbd(bdp, base, tx_ring_size);
1585
1586                 for (i = 0; i < frags; i++) {
1587                         dma_unmap_page(&priv->ofdev->dev,
1588                                         bdp->bufPtr,
1589                                         bdp->length,
1590                                         DMA_TO_DEVICE);
1591                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1592                         bdp = next_txbd(bdp, base, tx_ring_size);
1593                 }
1594
1595                 /*
1596                  * If there's room in the queue (limit it to rx_buffer_size)
1597                  * we add this skb back into the pool, if it's the right size
1598                  */
1599                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1600                                 skb_recycle_check(skb, priv->rx_buffer_size +
1601                                         RXBUF_ALIGNMENT))
1602                         __skb_queue_head(&priv->rx_recycle, skb);
1603                 else
1604                         dev_kfree_skb_any(skb);
1605
1606                 priv->tx_skbuff[skb_dirtytx] = NULL;
1607
1608                 skb_dirtytx = (skb_dirtytx + 1) &
1609                         TX_RING_MOD_MASK(tx_ring_size);
1610
1611                 howmany++;
1612                 priv->num_txbdfree += frags + 1;
1613         }
1614
1615         /* If we freed a buffer, we can restart transmission, if necessary */
1616         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1617                 netif_wake_queue(dev);
1618
1619         /* Update dirty indicators */
1620         priv->skb_dirtytx = skb_dirtytx;
1621         priv->dirty_tx = bdp;
1622
1623         dev->stats.tx_packets += howmany;
1624
1625         return howmany;
1626 }
1627
1628 static void gfar_schedule_cleanup(struct net_device *dev)
1629 {
1630         struct gfar_private *priv = netdev_priv(dev);
1631         unsigned long flags;
1632
1633         spin_lock_irqsave(&priv->txlock, flags);
1634         spin_lock(&priv->rxlock);
1635
1636         if (napi_schedule_prep(&priv->napi)) {
1637                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1638                 __napi_schedule(&priv->napi);
1639         } else {
1640                 /*
1641                  * Clear IEVENT, so interrupts aren't called again
1642                  * because of the packets that have already arrived.
1643                  */
1644                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1645         }
1646
1647         spin_unlock(&priv->rxlock);
1648         spin_unlock_irqrestore(&priv->txlock, flags);
1649 }
1650
1651 /* Interrupt Handler for Transmit complete */
1652 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1653 {
1654         gfar_schedule_cleanup((struct net_device *)dev_id);
1655         return IRQ_HANDLED;
1656 }
1657
1658 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1659                 struct sk_buff *skb)
1660 {
1661         struct gfar_private *priv = netdev_priv(dev);
1662         u32 lstatus;
1663
1664         bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1665                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1666
1667         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1668
1669         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1670                 lstatus |= BD_LFLAG(RXBD_WRAP);
1671
1672         eieio();
1673
1674         bdp->lstatus = lstatus;
1675 }
1676
1677
1678 struct sk_buff * gfar_new_skb(struct net_device *dev)
1679 {
1680         unsigned int alignamount;
1681         struct gfar_private *priv = netdev_priv(dev);
1682         struct sk_buff *skb = NULL;
1683
1684         skb = __skb_dequeue(&priv->rx_recycle);
1685         if (!skb)
1686                 skb = netdev_alloc_skb(dev,
1687                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1688
1689         if (!skb)
1690                 return NULL;
1691
1692         alignamount = RXBUF_ALIGNMENT -
1693                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1694
1695         /* We need the data buffer to be aligned properly.  We will reserve
1696          * as many bytes as needed to align the data properly
1697          */
1698         skb_reserve(skb, alignamount);
1699
1700         return skb;
1701 }
1702
1703 static inline void count_errors(unsigned short status, struct net_device *dev)
1704 {
1705         struct gfar_private *priv = netdev_priv(dev);
1706         struct net_device_stats *stats = &dev->stats;
1707         struct gfar_extra_stats *estats = &priv->extra_stats;
1708
1709         /* If the packet was truncated, none of the other errors
1710          * matter */
1711         if (status & RXBD_TRUNCATED) {
1712                 stats->rx_length_errors++;
1713
1714                 estats->rx_trunc++;
1715
1716                 return;
1717         }
1718         /* Count the errors, if there were any */
1719         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1720                 stats->rx_length_errors++;
1721
1722                 if (status & RXBD_LARGE)
1723                         estats->rx_large++;
1724                 else
1725                         estats->rx_short++;
1726         }
1727         if (status & RXBD_NONOCTET) {
1728                 stats->rx_frame_errors++;
1729                 estats->rx_nonoctet++;
1730         }
1731         if (status & RXBD_CRCERR) {
1732                 estats->rx_crcerr++;
1733                 stats->rx_crc_errors++;
1734         }
1735         if (status & RXBD_OVERRUN) {
1736                 estats->rx_overrun++;
1737                 stats->rx_crc_errors++;
1738         }
1739 }
1740
1741 irqreturn_t gfar_receive(int irq, void *dev_id)
1742 {
1743         gfar_schedule_cleanup((struct net_device *)dev_id);
1744         return IRQ_HANDLED;
1745 }
1746
1747 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1748 {
1749         /* If valid headers were found, and valid sums
1750          * were verified, then we tell the kernel that no
1751          * checksumming is necessary.  Otherwise, it is */
1752         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1753                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1754         else
1755                 skb->ip_summed = CHECKSUM_NONE;
1756 }
1757
1758
1759 /* gfar_process_frame() -- handle one incoming packet if skb
1760  * isn't NULL.  */
1761 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1762                               int amount_pull)
1763 {
1764         struct gfar_private *priv = netdev_priv(dev);
1765         struct rxfcb *fcb = NULL;
1766
1767         int ret;
1768
1769         /* fcb is at the beginning if exists */
1770         fcb = (struct rxfcb *)skb->data;
1771
1772         /* Remove the FCB from the skb */
1773         /* Remove the padded bytes, if there are any */
1774         if (amount_pull)
1775                 skb_pull(skb, amount_pull);
1776
1777         if (priv->rx_csum_enable)
1778                 gfar_rx_checksum(skb, fcb);
1779
1780         /* Tell the skb what kind of packet this is */
1781         skb->protocol = eth_type_trans(skb, dev);
1782
1783         /* Send the packet up the stack */
1784         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1785                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1786         else
1787                 ret = netif_receive_skb(skb);
1788
1789         if (NET_RX_DROP == ret)
1790                 priv->extra_stats.kernel_dropped++;
1791
1792         return 0;
1793 }
1794
1795 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1796  *   until the budget/quota has been reached. Returns the number
1797  *   of frames handled
1798  */
1799 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1800 {
1801         struct rxbd8 *bdp, *base;
1802         struct sk_buff *skb;
1803         int pkt_len;
1804         int amount_pull;
1805         int howmany = 0;
1806         struct gfar_private *priv = netdev_priv(dev);
1807
1808         /* Get the first full descriptor */
1809         bdp = priv->cur_rx;
1810         base = priv->rx_bd_base;
1811
1812         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1813                 priv->padding;
1814
1815         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1816                 struct sk_buff *newskb;
1817                 rmb();
1818
1819                 /* Add another skb for the future */
1820                 newskb = gfar_new_skb(dev);
1821
1822                 skb = priv->rx_skbuff[priv->skb_currx];
1823
1824                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1825                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1826
1827                 /* We drop the frame if we failed to allocate a new buffer */
1828                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1829                                  bdp->status & RXBD_ERR)) {
1830                         count_errors(bdp->status, dev);
1831
1832                         if (unlikely(!newskb))
1833                                 newskb = skb;
1834                         else if (skb) {
1835                                 /*
1836                                  * We need to reset ->data to what it
1837                                  * was before gfar_new_skb() re-aligned
1838                                  * it to an RXBUF_ALIGNMENT boundary
1839                                  * before we put the skb back on the
1840                                  * recycle list.
1841                                  */
1842                                 skb->data = skb->head + NET_SKB_PAD;
1843                                 __skb_queue_head(&priv->rx_recycle, skb);
1844                         }
1845                 } else {
1846                         /* Increment the number of packets */
1847                         dev->stats.rx_packets++;
1848                         howmany++;
1849
1850                         if (likely(skb)) {
1851                                 pkt_len = bdp->length - ETH_FCS_LEN;
1852                                 /* Remove the FCS from the packet length */
1853                                 skb_put(skb, pkt_len);
1854                                 dev->stats.rx_bytes += pkt_len;
1855
1856                                 if (in_irq() || irqs_disabled())
1857                                         printk("Interrupt problem!\n");
1858                                 gfar_process_frame(dev, skb, amount_pull);
1859
1860                         } else {
1861                                 if (netif_msg_rx_err(priv))
1862                                         printk(KERN_WARNING
1863                                                "%s: Missing skb!\n", dev->name);
1864                                 dev->stats.rx_dropped++;
1865                                 priv->extra_stats.rx_skbmissing++;
1866                         }
1867
1868                 }
1869
1870                 priv->rx_skbuff[priv->skb_currx] = newskb;
1871
1872                 /* Setup the new bdp */
1873                 gfar_new_rxbdp(dev, bdp, newskb);
1874
1875                 /* Update to the next pointer */
1876                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1877
1878                 /* update to point at the next skb */
1879                 priv->skb_currx =
1880                     (priv->skb_currx + 1) &
1881                     RX_RING_MOD_MASK(priv->rx_ring_size);
1882         }
1883
1884         /* Update the current rxbd pointer to be the next one */
1885         priv->cur_rx = bdp;
1886
1887         return howmany;
1888 }
1889
1890 static int gfar_poll(struct napi_struct *napi, int budget)
1891 {
1892         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1893         struct net_device *dev = priv->ndev;
1894         int tx_cleaned = 0;
1895         int rx_cleaned = 0;
1896         unsigned long flags;
1897
1898         /* Clear IEVENT, so interrupts aren't called again
1899          * because of the packets that have already arrived */
1900         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1901
1902         /* If we fail to get the lock, don't bother with the TX BDs */
1903         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1904                 tx_cleaned = gfar_clean_tx_ring(dev);
1905                 spin_unlock_irqrestore(&priv->txlock, flags);
1906         }
1907
1908         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1909
1910         if (tx_cleaned)
1911                 return budget;
1912
1913         if (rx_cleaned < budget) {
1914                 napi_complete(napi);
1915
1916                 /* Clear the halt bit in RSTAT */
1917                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1918
1919                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1920
1921                 /* If we are coalescing interrupts, update the timer */
1922                 /* Otherwise, clear it */
1923                 if (likely(priv->rxcoalescing)) {
1924                         gfar_write(&priv->regs->rxic, 0);
1925                         gfar_write(&priv->regs->rxic, priv->rxic);
1926                 }
1927                 if (likely(priv->txcoalescing)) {
1928                         gfar_write(&priv->regs->txic, 0);
1929                         gfar_write(&priv->regs->txic, priv->txic);
1930                 }
1931         }
1932
1933         return rx_cleaned;
1934 }
1935
1936 #ifdef CONFIG_NET_POLL_CONTROLLER
1937 /*
1938  * Polling 'interrupt' - used by things like netconsole to send skbs
1939  * without having to re-enable interrupts. It's not called while
1940  * the interrupt routine is executing.
1941  */
1942 static void gfar_netpoll(struct net_device *dev)
1943 {
1944         struct gfar_private *priv = netdev_priv(dev);
1945
1946         /* If the device has multiple interrupts, run tx/rx */
1947         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1948                 disable_irq(priv->interruptTransmit);
1949                 disable_irq(priv->interruptReceive);
1950                 disable_irq(priv->interruptError);
1951                 gfar_interrupt(priv->interruptTransmit, dev);
1952                 enable_irq(priv->interruptError);
1953                 enable_irq(priv->interruptReceive);
1954                 enable_irq(priv->interruptTransmit);
1955         } else {
1956                 disable_irq(priv->interruptTransmit);
1957                 gfar_interrupt(priv->interruptTransmit, dev);
1958                 enable_irq(priv->interruptTransmit);
1959         }
1960 }
1961 #endif
1962
1963 /* The interrupt handler for devices with one interrupt */
1964 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1965 {
1966         struct net_device *dev = dev_id;
1967         struct gfar_private *priv = netdev_priv(dev);
1968
1969         /* Save ievent for future reference */
1970         u32 events = gfar_read(&priv->regs->ievent);
1971
1972         /* Check for reception */
1973         if (events & IEVENT_RX_MASK)
1974                 gfar_receive(irq, dev_id);
1975
1976         /* Check for transmit completion */
1977         if (events & IEVENT_TX_MASK)
1978                 gfar_transmit(irq, dev_id);
1979
1980         /* Check for errors */
1981         if (events & IEVENT_ERR_MASK)
1982                 gfar_error(irq, dev_id);
1983
1984         return IRQ_HANDLED;
1985 }
1986
1987 /* Called every time the controller might need to be made
1988  * aware of new link state.  The PHY code conveys this
1989  * information through variables in the phydev structure, and this
1990  * function converts those variables into the appropriate
1991  * register values, and can bring down the device if needed.
1992  */
1993 static void adjust_link(struct net_device *dev)
1994 {
1995         struct gfar_private *priv = netdev_priv(dev);
1996         struct gfar __iomem *regs = priv->regs;
1997         unsigned long flags;
1998         struct phy_device *phydev = priv->phydev;
1999         int new_state = 0;
2000
2001         spin_lock_irqsave(&priv->txlock, flags);
2002         if (phydev->link) {
2003                 u32 tempval = gfar_read(&regs->maccfg2);
2004                 u32 ecntrl = gfar_read(&regs->ecntrl);
2005
2006                 /* Now we make sure that we can be in full duplex mode.
2007                  * If not, we operate in half-duplex mode. */
2008                 if (phydev->duplex != priv->oldduplex) {
2009                         new_state = 1;
2010                         if (!(phydev->duplex))
2011                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2012                         else
2013                                 tempval |= MACCFG2_FULL_DUPLEX;
2014
2015                         priv->oldduplex = phydev->duplex;
2016                 }
2017
2018                 if (phydev->speed != priv->oldspeed) {
2019                         new_state = 1;
2020                         switch (phydev->speed) {
2021                         case 1000:
2022                                 tempval =
2023                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2024
2025                                 ecntrl &= ~(ECNTRL_R100);
2026                                 break;
2027                         case 100:
2028                         case 10:
2029                                 tempval =
2030                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2031
2032                                 /* Reduced mode distinguishes
2033                                  * between 10 and 100 */
2034                                 if (phydev->speed == SPEED_100)
2035                                         ecntrl |= ECNTRL_R100;
2036                                 else
2037                                         ecntrl &= ~(ECNTRL_R100);
2038                                 break;
2039                         default:
2040                                 if (netif_msg_link(priv))
2041                                         printk(KERN_WARNING
2042                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2043                                                 dev->name, phydev->speed);
2044                                 break;
2045                         }
2046
2047                         priv->oldspeed = phydev->speed;
2048                 }
2049
2050                 gfar_write(&regs->maccfg2, tempval);
2051                 gfar_write(&regs->ecntrl, ecntrl);
2052
2053                 if (!priv->oldlink) {
2054                         new_state = 1;
2055                         priv->oldlink = 1;
2056                 }
2057         } else if (priv->oldlink) {
2058                 new_state = 1;
2059                 priv->oldlink = 0;
2060                 priv->oldspeed = 0;
2061                 priv->oldduplex = -1;
2062         }
2063
2064         if (new_state && netif_msg_link(priv))
2065                 phy_print_status(phydev);
2066
2067         spin_unlock_irqrestore(&priv->txlock, flags);
2068 }
2069
2070 /* Update the hash table based on the current list of multicast
2071  * addresses we subscribe to.  Also, change the promiscuity of
2072  * the device based on the flags (this function is called
2073  * whenever dev->flags is changed */
2074 static void gfar_set_multi(struct net_device *dev)
2075 {
2076         struct dev_mc_list *mc_ptr;
2077         struct gfar_private *priv = netdev_priv(dev);
2078         struct gfar __iomem *regs = priv->regs;
2079         u32 tempval;
2080
2081         if(dev->flags & IFF_PROMISC) {
2082                 /* Set RCTRL to PROM */
2083                 tempval = gfar_read(&regs->rctrl);
2084                 tempval |= RCTRL_PROM;
2085                 gfar_write(&regs->rctrl, tempval);
2086         } else {
2087                 /* Set RCTRL to not PROM */
2088                 tempval = gfar_read(&regs->rctrl);
2089                 tempval &= ~(RCTRL_PROM);
2090                 gfar_write(&regs->rctrl, tempval);
2091         }
2092
2093         if(dev->flags & IFF_ALLMULTI) {
2094                 /* Set the hash to rx all multicast frames */
2095                 gfar_write(&regs->igaddr0, 0xffffffff);
2096                 gfar_write(&regs->igaddr1, 0xffffffff);
2097                 gfar_write(&regs->igaddr2, 0xffffffff);
2098                 gfar_write(&regs->igaddr3, 0xffffffff);
2099                 gfar_write(&regs->igaddr4, 0xffffffff);
2100                 gfar_write(&regs->igaddr5, 0xffffffff);
2101                 gfar_write(&regs->igaddr6, 0xffffffff);
2102                 gfar_write(&regs->igaddr7, 0xffffffff);
2103                 gfar_write(&regs->gaddr0, 0xffffffff);
2104                 gfar_write(&regs->gaddr1, 0xffffffff);
2105                 gfar_write(&regs->gaddr2, 0xffffffff);
2106                 gfar_write(&regs->gaddr3, 0xffffffff);
2107                 gfar_write(&regs->gaddr4, 0xffffffff);
2108                 gfar_write(&regs->gaddr5, 0xffffffff);
2109                 gfar_write(&regs->gaddr6, 0xffffffff);
2110                 gfar_write(&regs->gaddr7, 0xffffffff);
2111         } else {
2112                 int em_num;
2113                 int idx;
2114
2115                 /* zero out the hash */
2116                 gfar_write(&regs->igaddr0, 0x0);
2117                 gfar_write(&regs->igaddr1, 0x0);
2118                 gfar_write(&regs->igaddr2, 0x0);
2119                 gfar_write(&regs->igaddr3, 0x0);
2120                 gfar_write(&regs->igaddr4, 0x0);
2121                 gfar_write(&regs->igaddr5, 0x0);
2122                 gfar_write(&regs->igaddr6, 0x0);
2123                 gfar_write(&regs->igaddr7, 0x0);
2124                 gfar_write(&regs->gaddr0, 0x0);
2125                 gfar_write(&regs->gaddr1, 0x0);
2126                 gfar_write(&regs->gaddr2, 0x0);
2127                 gfar_write(&regs->gaddr3, 0x0);
2128                 gfar_write(&regs->gaddr4, 0x0);
2129                 gfar_write(&regs->gaddr5, 0x0);
2130                 gfar_write(&regs->gaddr6, 0x0);
2131                 gfar_write(&regs->gaddr7, 0x0);
2132
2133                 /* If we have extended hash tables, we need to
2134                  * clear the exact match registers to prepare for
2135                  * setting them */
2136                 if (priv->extended_hash) {
2137                         em_num = GFAR_EM_NUM + 1;
2138                         gfar_clear_exact_match(dev);
2139                         idx = 1;
2140                 } else {
2141                         idx = 0;
2142                         em_num = 0;
2143                 }
2144
2145                 if(dev->mc_count == 0)
2146                         return;
2147
2148                 /* Parse the list, and set the appropriate bits */
2149                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2150                         if (idx < em_num) {
2151                                 gfar_set_mac_for_addr(dev, idx,
2152                                                 mc_ptr->dmi_addr);
2153                                 idx++;
2154                         } else
2155                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2156                 }
2157         }
2158
2159         return;
2160 }
2161
2162
2163 /* Clears each of the exact match registers to zero, so they
2164  * don't interfere with normal reception */
2165 static void gfar_clear_exact_match(struct net_device *dev)
2166 {
2167         int idx;
2168         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2169
2170         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2171                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2172 }
2173
2174 /* Set the appropriate hash bit for the given addr */
2175 /* The algorithm works like so:
2176  * 1) Take the Destination Address (ie the multicast address), and
2177  * do a CRC on it (little endian), and reverse the bits of the
2178  * result.
2179  * 2) Use the 8 most significant bits as a hash into a 256-entry
2180  * table.  The table is controlled through 8 32-bit registers:
2181  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2182  * gaddr7.  This means that the 3 most significant bits in the
2183  * hash index which gaddr register to use, and the 5 other bits
2184  * indicate which bit (assuming an IBM numbering scheme, which
2185  * for PowerPC (tm) is usually the case) in the register holds
2186  * the entry. */
2187 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2188 {
2189         u32 tempval;
2190         struct gfar_private *priv = netdev_priv(dev);
2191         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2192         int width = priv->hash_width;
2193         u8 whichbit = (result >> (32 - width)) & 0x1f;
2194         u8 whichreg = result >> (32 - width + 5);
2195         u32 value = (1 << (31-whichbit));
2196
2197         tempval = gfar_read(priv->hash_regs[whichreg]);
2198         tempval |= value;
2199         gfar_write(priv->hash_regs[whichreg], tempval);
2200
2201         return;
2202 }
2203
2204
2205 /* There are multiple MAC Address register pairs on some controllers
2206  * This function sets the numth pair to a given address
2207  */
2208 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2209 {
2210         struct gfar_private *priv = netdev_priv(dev);
2211         int idx;
2212         char tmpbuf[MAC_ADDR_LEN];
2213         u32 tempval;
2214         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2215
2216         macptr += num*2;
2217
2218         /* Now copy it into the mac registers backwards, cuz */
2219         /* little endian is silly */
2220         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2221                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2222
2223         gfar_write(macptr, *((u32 *) (tmpbuf)));
2224
2225         tempval = *((u32 *) (tmpbuf + 4));
2226
2227         gfar_write(macptr+1, tempval);
2228 }
2229
2230 /* GFAR error interrupt handler */
2231 static irqreturn_t gfar_error(int irq, void *dev_id)
2232 {
2233         struct net_device *dev = dev_id;
2234         struct gfar_private *priv = netdev_priv(dev);
2235
2236         /* Save ievent for future reference */
2237         u32 events = gfar_read(&priv->regs->ievent);
2238
2239         /* Clear IEVENT */
2240         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2241
2242         /* Magic Packet is not an error. */
2243         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2244             (events & IEVENT_MAG))
2245                 events &= ~IEVENT_MAG;
2246
2247         /* Hmm... */
2248         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2249                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2250                        dev->name, events, gfar_read(&priv->regs->imask));
2251
2252         /* Update the error counters */
2253         if (events & IEVENT_TXE) {
2254                 dev->stats.tx_errors++;
2255
2256                 if (events & IEVENT_LC)
2257                         dev->stats.tx_window_errors++;
2258                 if (events & IEVENT_CRL)
2259                         dev->stats.tx_aborted_errors++;
2260                 if (events & IEVENT_XFUN) {
2261                         if (netif_msg_tx_err(priv))
2262                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2263                                        "packet dropped.\n", dev->name);
2264                         dev->stats.tx_dropped++;
2265                         priv->extra_stats.tx_underrun++;
2266
2267                         /* Reactivate the Tx Queues */
2268                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2269                 }
2270                 if (netif_msg_tx_err(priv))
2271                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2272         }
2273         if (events & IEVENT_BSY) {
2274                 dev->stats.rx_errors++;
2275                 priv->extra_stats.rx_bsy++;
2276
2277                 gfar_receive(irq, dev_id);
2278
2279                 if (netif_msg_rx_err(priv))
2280                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2281                                dev->name, gfar_read(&priv->regs->rstat));
2282         }
2283         if (events & IEVENT_BABR) {
2284                 dev->stats.rx_errors++;
2285                 priv->extra_stats.rx_babr++;
2286
2287                 if (netif_msg_rx_err(priv))
2288                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2289         }
2290         if (events & IEVENT_EBERR) {
2291                 priv->extra_stats.eberr++;
2292                 if (netif_msg_rx_err(priv))
2293                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2294         }
2295         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2296                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2297
2298         if (events & IEVENT_BABT) {
2299                 priv->extra_stats.tx_babt++;
2300                 if (netif_msg_tx_err(priv))
2301                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2302         }
2303         return IRQ_HANDLED;
2304 }
2305
2306 /* work with hotplug and coldplug */
2307 MODULE_ALIAS("platform:fsl-gianfar");
2308
2309 static struct of_device_id gfar_match[] =
2310 {
2311         {
2312                 .type = "network",
2313                 .compatible = "gianfar",
2314         },
2315         {},
2316 };
2317
2318 /* Structure for a device driver */
2319 static struct of_platform_driver gfar_driver = {
2320         .name = "fsl-gianfar",
2321         .match_table = gfar_match,
2322
2323         .probe = gfar_probe,
2324         .remove = gfar_remove,
2325         .suspend = gfar_suspend,
2326         .resume = gfar_resume,
2327 };
2328
2329 static int __init gfar_init(void)
2330 {
2331         return of_register_platform_driver(&gfar_driver);
2332 }
2333
2334 static void __exit gfar_exit(void)
2335 {
2336         of_unregister_platform_driver(&gfar_driver);
2337 }
2338
2339 module_init(gfar_init);
2340 module_exit(gfar_exit);
2341