gianfar: add support for SGMII
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through platform_device.  Structures which
29  *  define the configuration needed by the board are defined in a
30  *  board structure in arch/ppc/platforms (though I do not
31  *  discount the possibility that other architectures could one
32  *  day be supported.
33  *
34  *  The Gianfar Ethernet Controller uses a ring of buffer
35  *  descriptors.  The beginning is indicated by a register
36  *  pointing to the physical address of the start of the ring.
37  *  The end is determined by a "wrap" bit being set in the
38  *  last descriptor of the ring.
39  *
40  *  When a packet is received, the RXF bit in the
41  *  IEVENT register is set, triggering an interrupt when the
42  *  corresponding bit in the IMASK register is also set (if
43  *  interrupt coalescing is active, then the interrupt may not
44  *  happen immediately, but will wait until either a set number
45  *  of frames or amount of time have passed).  In NAPI, the
46  *  interrupt handler will signal there is work to be done, and
47  *  exit.  Without NAPI, the packet(s) will be handled
48  *  immediately.  Both methods will start at the last known empty
49  *  descriptor, and process every subsequent descriptor until there
50  *  are none left with data (NAPI will stop after a set number of
51  *  packets to give time to other tasks, but will eventually
52  *  process all the packets).  The data arrives inside a
53  *  pre-allocated skb, and so after the skb is passed up to the
54  *  stack, a new skb must be allocated, and the address field in
55  *  the buffer descriptor must be updated to indicate this new
56  *  skb.
57  *
58  *  When the kernel requests that a packet be transmitted, the
59  *  driver starts where it left off last time, and points the
60  *  descriptor at the buffer which was passed in.  The driver
61  *  then informs the DMA engine that there are packets ready to
62  *  be transmitted.  Once the controller is finished transmitting
63  *  the packet, an interrupt may be triggered (under the same
64  *  conditions as for reception, but depending on the TXF bit).
65  *  The driver then cleans up the buffer.
66  */
67
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
81 #include <linux/mm.h>
82 #include <linux/platform_device.h>
83 #include <linux/ip.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
86 #include <linux/in.h>
87
88 #include <asm/io.h>
89 #include <asm/irq.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96
97 #include "gianfar.h"
98 #include "gianfar_mii.h"
99
100 #define TX_TIMEOUT      (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
104
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
107 #else
108 #define RECEIVE(x) netif_rx(x)
109 #endif
110
111 const char gfar_driver_name[] = "Gianfar Ethernet";
112 const char gfar_driver_version[] = "1.3";
113
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_timeout(struct net_device *dev);
117 static int gfar_close(struct net_device *dev);
118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
119 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
120 static int gfar_set_mac_address(struct net_device *dev);
121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
122 static irqreturn_t gfar_error(int irq, void *dev_id);
123 static irqreturn_t gfar_transmit(int irq, void *dev_id);
124 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
125 static void adjust_link(struct net_device *dev);
126 static void init_registers(struct net_device *dev);
127 static int init_phy(struct net_device *dev);
128 static int gfar_probe(struct platform_device *pdev);
129 static int gfar_remove(struct platform_device *pdev);
130 static void free_skb_resources(struct gfar_private *priv);
131 static void gfar_set_multi(struct net_device *dev);
132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
133 static void gfar_configure_serdes(struct net_device *dev);
134 extern int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id, int regnum, u16 value);
135 extern int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum);
136 #ifdef CONFIG_GFAR_NAPI
137 static int gfar_poll(struct net_device *dev, int *budget);
138 #endif
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
141 #endif
142 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
143 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
144 static void gfar_vlan_rx_register(struct net_device *netdev,
145                                 struct vlan_group *grp);
146 void gfar_halt(struct net_device *dev);
147 void gfar_start(struct net_device *dev);
148 static void gfar_clear_exact_match(struct net_device *dev);
149 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
150
151 extern const struct ethtool_ops gfar_ethtool_ops;
152
153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
155 MODULE_LICENSE("GPL");
156
157 /* Returns 1 if incoming frames use an FCB */
158 static inline int gfar_uses_fcb(struct gfar_private *priv)
159 {
160         return (priv->vlan_enable || priv->rx_csum_enable);
161 }
162
163 /* Set up the ethernet device structure, private data,
164  * and anything else we need before we start */
165 static int gfar_probe(struct platform_device *pdev)
166 {
167         u32 tempval;
168         struct net_device *dev = NULL;
169         struct gfar_private *priv = NULL;
170         struct gianfar_platform_data *einfo;
171         struct resource *r;
172         int idx;
173         int err = 0;
174
175         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
176
177         if (NULL == einfo) {
178                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
179                        pdev->id);
180
181                 return -ENODEV;
182         }
183
184         /* Create an ethernet device instance */
185         dev = alloc_etherdev(sizeof (*priv));
186
187         if (NULL == dev)
188                 return -ENOMEM;
189
190         priv = netdev_priv(dev);
191
192         /* Set the info in the priv to the current info */
193         priv->einfo = einfo;
194
195         /* fill out IRQ fields */
196         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
197                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
198                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
199                 priv->interruptError = platform_get_irq_byname(pdev, "error");
200                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
201                         goto regs_fail;
202         } else {
203                 priv->interruptTransmit = platform_get_irq(pdev, 0);
204                 if (priv->interruptTransmit < 0)
205                         goto regs_fail;
206         }
207
208         /* get a pointer to the register memory */
209         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
210         priv->regs = ioremap(r->start, sizeof (struct gfar));
211
212         if (NULL == priv->regs) {
213                 err = -ENOMEM;
214                 goto regs_fail;
215         }
216
217         spin_lock_init(&priv->txlock);
218         spin_lock_init(&priv->rxlock);
219
220         platform_set_drvdata(pdev, dev);
221
222         /* Stop the DMA engine now, in case it was running before */
223         /* (The firmware could have used it, and left it running). */
224         /* To do this, we write Graceful Receive Stop and Graceful */
225         /* Transmit Stop, and then wait until the corresponding bits */
226         /* in IEVENT indicate the stops have completed. */
227         tempval = gfar_read(&priv->regs->dmactrl);
228         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
229         gfar_write(&priv->regs->dmactrl, tempval);
230
231         tempval = gfar_read(&priv->regs->dmactrl);
232         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
233         gfar_write(&priv->regs->dmactrl, tempval);
234
235         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
236                 cpu_relax();
237
238         /* Reset MAC layer */
239         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
240
241         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
242         gfar_write(&priv->regs->maccfg1, tempval);
243
244         /* Initialize MACCFG2. */
245         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
246
247         /* Initialize ECNTRL */
248         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
249
250         /* Copy the station address into the dev structure, */
251         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
252
253         /* Set the dev->base_addr to the gfar reg region */
254         dev->base_addr = (unsigned long) (priv->regs);
255
256         SET_MODULE_OWNER(dev);
257         SET_NETDEV_DEV(dev, &pdev->dev);
258
259         /* Fill in the dev structure */
260         dev->open = gfar_enet_open;
261         dev->hard_start_xmit = gfar_start_xmit;
262         dev->tx_timeout = gfar_timeout;
263         dev->watchdog_timeo = TX_TIMEOUT;
264 #ifdef CONFIG_GFAR_NAPI
265         dev->poll = gfar_poll;
266         dev->weight = GFAR_DEV_WEIGHT;
267 #endif
268 #ifdef CONFIG_NET_POLL_CONTROLLER
269         dev->poll_controller = gfar_netpoll;
270 #endif
271         dev->stop = gfar_close;
272         dev->get_stats = gfar_get_stats;
273         dev->change_mtu = gfar_change_mtu;
274         dev->mtu = 1500;
275         dev->set_multicast_list = gfar_set_multi;
276
277         dev->ethtool_ops = &gfar_ethtool_ops;
278
279         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
280                 priv->rx_csum_enable = 1;
281                 dev->features |= NETIF_F_IP_CSUM;
282         } else
283                 priv->rx_csum_enable = 0;
284
285         priv->vlgrp = NULL;
286
287         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
288                 dev->vlan_rx_register = gfar_vlan_rx_register;
289
290                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
291
292                 priv->vlan_enable = 1;
293         }
294
295         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
296                 priv->extended_hash = 1;
297                 priv->hash_width = 9;
298
299                 priv->hash_regs[0] = &priv->regs->igaddr0;
300                 priv->hash_regs[1] = &priv->regs->igaddr1;
301                 priv->hash_regs[2] = &priv->regs->igaddr2;
302                 priv->hash_regs[3] = &priv->regs->igaddr3;
303                 priv->hash_regs[4] = &priv->regs->igaddr4;
304                 priv->hash_regs[5] = &priv->regs->igaddr5;
305                 priv->hash_regs[6] = &priv->regs->igaddr6;
306                 priv->hash_regs[7] = &priv->regs->igaddr7;
307                 priv->hash_regs[8] = &priv->regs->gaddr0;
308                 priv->hash_regs[9] = &priv->regs->gaddr1;
309                 priv->hash_regs[10] = &priv->regs->gaddr2;
310                 priv->hash_regs[11] = &priv->regs->gaddr3;
311                 priv->hash_regs[12] = &priv->regs->gaddr4;
312                 priv->hash_regs[13] = &priv->regs->gaddr5;
313                 priv->hash_regs[14] = &priv->regs->gaddr6;
314                 priv->hash_regs[15] = &priv->regs->gaddr7;
315
316         } else {
317                 priv->extended_hash = 0;
318                 priv->hash_width = 8;
319
320                 priv->hash_regs[0] = &priv->regs->gaddr0;
321                 priv->hash_regs[1] = &priv->regs->gaddr1;
322                 priv->hash_regs[2] = &priv->regs->gaddr2;
323                 priv->hash_regs[3] = &priv->regs->gaddr3;
324                 priv->hash_regs[4] = &priv->regs->gaddr4;
325                 priv->hash_regs[5] = &priv->regs->gaddr5;
326                 priv->hash_regs[6] = &priv->regs->gaddr6;
327                 priv->hash_regs[7] = &priv->regs->gaddr7;
328         }
329
330         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
331                 priv->padding = DEFAULT_PADDING;
332         else
333                 priv->padding = 0;
334
335         if (dev->features & NETIF_F_IP_CSUM)
336                 dev->hard_header_len += GMAC_FCB_LEN;
337
338         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
339         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
340         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
341
342         priv->txcoalescing = DEFAULT_TX_COALESCE;
343         priv->txcount = DEFAULT_TXCOUNT;
344         priv->txtime = DEFAULT_TXTIME;
345         priv->rxcoalescing = DEFAULT_RX_COALESCE;
346         priv->rxcount = DEFAULT_RXCOUNT;
347         priv->rxtime = DEFAULT_RXTIME;
348
349         /* Enable most messages by default */
350         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
351
352         err = register_netdev(dev);
353
354         if (err) {
355                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
356                                 dev->name);
357                 goto register_fail;
358         }
359
360         /* Create all the sysfs files */
361         gfar_init_sysfs(dev);
362
363         /* Print out the device info */
364         printk(KERN_INFO DEVICE_NAME, dev->name);
365         for (idx = 0; idx < 6; idx++)
366                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
367         printk("\n");
368
369         /* Even more device info helps when determining which kernel */
370         /* provided which set of benchmarks. */
371 #ifdef CONFIG_GFAR_NAPI
372         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
373 #else
374         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
375 #endif
376         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
377                dev->name, priv->rx_ring_size, priv->tx_ring_size);
378
379         return 0;
380
381 register_fail:
382         iounmap(priv->regs);
383 regs_fail:
384         free_netdev(dev);
385         return err;
386 }
387
388 static int gfar_remove(struct platform_device *pdev)
389 {
390         struct net_device *dev = platform_get_drvdata(pdev);
391         struct gfar_private *priv = netdev_priv(dev);
392
393         platform_set_drvdata(pdev, NULL);
394
395         iounmap(priv->regs);
396         free_netdev(dev);
397
398         return 0;
399 }
400
401
402 /* Reads the controller's registers to determine what interface
403  * connects it to the PHY.
404  */
405 static phy_interface_t gfar_get_interface(struct net_device *dev)
406 {
407         struct gfar_private *priv = netdev_priv(dev);
408         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
409
410         if (ecntrl & ECNTRL_SGMII_MODE)
411                 return PHY_INTERFACE_MODE_SGMII;
412
413         if (ecntrl & ECNTRL_TBI_MODE) {
414                 if (ecntrl & ECNTRL_REDUCED_MODE)
415                         return PHY_INTERFACE_MODE_RTBI;
416                 else
417                         return PHY_INTERFACE_MODE_TBI;
418         }
419
420         if (ecntrl & ECNTRL_REDUCED_MODE) {
421                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
422                         return PHY_INTERFACE_MODE_RMII;
423                 else
424                         return PHY_INTERFACE_MODE_RGMII;
425         }
426
427         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
428                 return PHY_INTERFACE_MODE_GMII;
429
430         return PHY_INTERFACE_MODE_MII;
431 }
432
433
434 /* Initializes driver's PHY state, and attaches to the PHY.
435  * Returns 0 on success.
436  */
437 static int init_phy(struct net_device *dev)
438 {
439         struct gfar_private *priv = netdev_priv(dev);
440         uint gigabit_support =
441                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
442                 SUPPORTED_1000baseT_Full : 0;
443         struct phy_device *phydev;
444         char phy_id[BUS_ID_SIZE];
445         phy_interface_t interface;
446
447         priv->oldlink = 0;
448         priv->oldspeed = 0;
449         priv->oldduplex = -1;
450
451         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
452
453         interface = gfar_get_interface(dev);
454
455         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
456
457         if (interface == PHY_INTERFACE_MODE_SGMII)
458                 gfar_configure_serdes(dev);
459
460         if (IS_ERR(phydev)) {
461                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
462                 return PTR_ERR(phydev);
463         }
464
465         /* Remove any features not supported by the controller */
466         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
467         phydev->advertising = phydev->supported;
468
469         priv->phydev = phydev;
470
471         return 0;
472 }
473
474 static void gfar_configure_serdes(struct net_device *dev)
475 {
476         struct gfar_private *priv = netdev_priv(dev);
477         struct gfar_mii __iomem *regs =
478                         (void __iomem *)&priv->regs->gfar_mii_regs;
479
480         /* Initialise TBI i/f to communicate with serdes (lynx phy) */
481
482         /* Single clk mode, mii mode off(for aerdes communication) */
483         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_TBICON, TBICON_CLK_SELECT);
484
485         /* Supported pause and full-duplex, no half-duplex */
486         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_ADVERTISE,
487                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
488                         ADVERTISE_1000XPSE_ASYM);
489
490         /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
491         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_BMCR, BMCR_ANENABLE |
492                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
493 }
494
495 static void init_registers(struct net_device *dev)
496 {
497         struct gfar_private *priv = netdev_priv(dev);
498
499         /* Clear IEVENT */
500         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
501
502         /* Initialize IMASK */
503         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
504
505         /* Init hash registers to zero */
506         gfar_write(&priv->regs->igaddr0, 0);
507         gfar_write(&priv->regs->igaddr1, 0);
508         gfar_write(&priv->regs->igaddr2, 0);
509         gfar_write(&priv->regs->igaddr3, 0);
510         gfar_write(&priv->regs->igaddr4, 0);
511         gfar_write(&priv->regs->igaddr5, 0);
512         gfar_write(&priv->regs->igaddr6, 0);
513         gfar_write(&priv->regs->igaddr7, 0);
514
515         gfar_write(&priv->regs->gaddr0, 0);
516         gfar_write(&priv->regs->gaddr1, 0);
517         gfar_write(&priv->regs->gaddr2, 0);
518         gfar_write(&priv->regs->gaddr3, 0);
519         gfar_write(&priv->regs->gaddr4, 0);
520         gfar_write(&priv->regs->gaddr5, 0);
521         gfar_write(&priv->regs->gaddr6, 0);
522         gfar_write(&priv->regs->gaddr7, 0);
523
524         /* Zero out the rmon mib registers if it has them */
525         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
526                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
527
528                 /* Mask off the CAM interrupts */
529                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
530                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
531         }
532
533         /* Initialize the max receive buffer length */
534         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
535
536         /* Initialize the Minimum Frame Length Register */
537         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
538
539         /* Assign the TBI an address which won't conflict with the PHYs */
540         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
541 }
542
543
544 /* Halt the receive and transmit queues */
545 void gfar_halt(struct net_device *dev)
546 {
547         struct gfar_private *priv = netdev_priv(dev);
548         struct gfar __iomem *regs = priv->regs;
549         u32 tempval;
550
551         /* Mask all interrupts */
552         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
553
554         /* Clear all interrupts */
555         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
556
557         /* Stop the DMA, and wait for it to stop */
558         tempval = gfar_read(&priv->regs->dmactrl);
559         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
560             != (DMACTRL_GRS | DMACTRL_GTS)) {
561                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
562                 gfar_write(&priv->regs->dmactrl, tempval);
563
564                 while (!(gfar_read(&priv->regs->ievent) &
565                          (IEVENT_GRSC | IEVENT_GTSC)))
566                         cpu_relax();
567         }
568
569         /* Disable Rx and Tx */
570         tempval = gfar_read(&regs->maccfg1);
571         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
572         gfar_write(&regs->maccfg1, tempval);
573 }
574
575 void stop_gfar(struct net_device *dev)
576 {
577         struct gfar_private *priv = netdev_priv(dev);
578         struct gfar __iomem *regs = priv->regs;
579         unsigned long flags;
580
581         phy_stop(priv->phydev);
582
583         /* Lock it down */
584         spin_lock_irqsave(&priv->txlock, flags);
585         spin_lock(&priv->rxlock);
586
587         gfar_halt(dev);
588
589         spin_unlock(&priv->rxlock);
590         spin_unlock_irqrestore(&priv->txlock, flags);
591
592         /* Free the IRQs */
593         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
594                 free_irq(priv->interruptError, dev);
595                 free_irq(priv->interruptTransmit, dev);
596                 free_irq(priv->interruptReceive, dev);
597         } else {
598                 free_irq(priv->interruptTransmit, dev);
599         }
600
601         free_skb_resources(priv);
602
603         dma_free_coherent(NULL,
604                         sizeof(struct txbd8)*priv->tx_ring_size
605                         + sizeof(struct rxbd8)*priv->rx_ring_size,
606                         priv->tx_bd_base,
607                         gfar_read(&regs->tbase0));
608 }
609
610 /* If there are any tx skbs or rx skbs still around, free them.
611  * Then free tx_skbuff and rx_skbuff */
612 static void free_skb_resources(struct gfar_private *priv)
613 {
614         struct rxbd8 *rxbdp;
615         struct txbd8 *txbdp;
616         int i;
617
618         /* Go through all the buffer descriptors and free their data buffers */
619         txbdp = priv->tx_bd_base;
620
621         for (i = 0; i < priv->tx_ring_size; i++) {
622
623                 if (priv->tx_skbuff[i]) {
624                         dma_unmap_single(NULL, txbdp->bufPtr,
625                                         txbdp->length,
626                                         DMA_TO_DEVICE);
627                         dev_kfree_skb_any(priv->tx_skbuff[i]);
628                         priv->tx_skbuff[i] = NULL;
629                 }
630         }
631
632         kfree(priv->tx_skbuff);
633
634         rxbdp = priv->rx_bd_base;
635
636         /* rx_skbuff is not guaranteed to be allocated, so only
637          * free it and its contents if it is allocated */
638         if(priv->rx_skbuff != NULL) {
639                 for (i = 0; i < priv->rx_ring_size; i++) {
640                         if (priv->rx_skbuff[i]) {
641                                 dma_unmap_single(NULL, rxbdp->bufPtr,
642                                                 priv->rx_buffer_size,
643                                                 DMA_FROM_DEVICE);
644
645                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
646                                 priv->rx_skbuff[i] = NULL;
647                         }
648
649                         rxbdp->status = 0;
650                         rxbdp->length = 0;
651                         rxbdp->bufPtr = 0;
652
653                         rxbdp++;
654                 }
655
656                 kfree(priv->rx_skbuff);
657         }
658 }
659
660 void gfar_start(struct net_device *dev)
661 {
662         struct gfar_private *priv = netdev_priv(dev);
663         struct gfar __iomem *regs = priv->regs;
664         u32 tempval;
665
666         /* Enable Rx and Tx in MACCFG1 */
667         tempval = gfar_read(&regs->maccfg1);
668         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
669         gfar_write(&regs->maccfg1, tempval);
670
671         /* Initialize DMACTRL to have WWR and WOP */
672         tempval = gfar_read(&priv->regs->dmactrl);
673         tempval |= DMACTRL_INIT_SETTINGS;
674         gfar_write(&priv->regs->dmactrl, tempval);
675
676         /* Make sure we aren't stopped */
677         tempval = gfar_read(&priv->regs->dmactrl);
678         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
679         gfar_write(&priv->regs->dmactrl, tempval);
680
681         /* Clear THLT/RHLT, so that the DMA starts polling now */
682         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
683         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
684
685         /* Unmask the interrupts we look for */
686         gfar_write(&regs->imask, IMASK_DEFAULT);
687 }
688
689 /* Bring the controller up and running */
690 int startup_gfar(struct net_device *dev)
691 {
692         struct txbd8 *txbdp;
693         struct rxbd8 *rxbdp;
694         dma_addr_t addr;
695         unsigned long vaddr;
696         int i;
697         struct gfar_private *priv = netdev_priv(dev);
698         struct gfar __iomem *regs = priv->regs;
699         int err = 0;
700         u32 rctrl = 0;
701         u32 attrs = 0;
702
703         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
704
705         /* Allocate memory for the buffer descriptors */
706         vaddr = (unsigned long) dma_alloc_coherent(NULL,
707                         sizeof (struct txbd8) * priv->tx_ring_size +
708                         sizeof (struct rxbd8) * priv->rx_ring_size,
709                         &addr, GFP_KERNEL);
710
711         if (vaddr == 0) {
712                 if (netif_msg_ifup(priv))
713                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
714                                         dev->name);
715                 return -ENOMEM;
716         }
717
718         priv->tx_bd_base = (struct txbd8 *) vaddr;
719
720         /* enet DMA only understands physical addresses */
721         gfar_write(&regs->tbase0, addr);
722
723         /* Start the rx descriptor ring where the tx ring leaves off */
724         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
725         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
726         priv->rx_bd_base = (struct rxbd8 *) vaddr;
727         gfar_write(&regs->rbase0, addr);
728
729         /* Setup the skbuff rings */
730         priv->tx_skbuff =
731             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
732                                         priv->tx_ring_size, GFP_KERNEL);
733
734         if (NULL == priv->tx_skbuff) {
735                 if (netif_msg_ifup(priv))
736                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
737                                         dev->name);
738                 err = -ENOMEM;
739                 goto tx_skb_fail;
740         }
741
742         for (i = 0; i < priv->tx_ring_size; i++)
743                 priv->tx_skbuff[i] = NULL;
744
745         priv->rx_skbuff =
746             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
747                                         priv->rx_ring_size, GFP_KERNEL);
748
749         if (NULL == priv->rx_skbuff) {
750                 if (netif_msg_ifup(priv))
751                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
752                                         dev->name);
753                 err = -ENOMEM;
754                 goto rx_skb_fail;
755         }
756
757         for (i = 0; i < priv->rx_ring_size; i++)
758                 priv->rx_skbuff[i] = NULL;
759
760         /* Initialize some variables in our dev structure */
761         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
762         priv->cur_rx = priv->rx_bd_base;
763         priv->skb_curtx = priv->skb_dirtytx = 0;
764         priv->skb_currx = 0;
765
766         /* Initialize Transmit Descriptor Ring */
767         txbdp = priv->tx_bd_base;
768         for (i = 0; i < priv->tx_ring_size; i++) {
769                 txbdp->status = 0;
770                 txbdp->length = 0;
771                 txbdp->bufPtr = 0;
772                 txbdp++;
773         }
774
775         /* Set the last descriptor in the ring to indicate wrap */
776         txbdp--;
777         txbdp->status |= TXBD_WRAP;
778
779         rxbdp = priv->rx_bd_base;
780         for (i = 0; i < priv->rx_ring_size; i++) {
781                 struct sk_buff *skb = NULL;
782
783                 rxbdp->status = 0;
784
785                 skb = gfar_new_skb(dev, rxbdp);
786
787                 priv->rx_skbuff[i] = skb;
788
789                 rxbdp++;
790         }
791
792         /* Set the last descriptor in the ring to wrap */
793         rxbdp--;
794         rxbdp->status |= RXBD_WRAP;
795
796         /* If the device has multiple interrupts, register for
797          * them.  Otherwise, only register for the one */
798         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
799                 /* Install our interrupt handlers for Error,
800                  * Transmit, and Receive */
801                 if (request_irq(priv->interruptError, gfar_error,
802                                 0, "enet_error", dev) < 0) {
803                         if (netif_msg_intr(priv))
804                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
805                                         dev->name, priv->interruptError);
806
807                         err = -1;
808                         goto err_irq_fail;
809                 }
810
811                 if (request_irq(priv->interruptTransmit, gfar_transmit,
812                                 0, "enet_tx", dev) < 0) {
813                         if (netif_msg_intr(priv))
814                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
815                                         dev->name, priv->interruptTransmit);
816
817                         err = -1;
818
819                         goto tx_irq_fail;
820                 }
821
822                 if (request_irq(priv->interruptReceive, gfar_receive,
823                                 0, "enet_rx", dev) < 0) {
824                         if (netif_msg_intr(priv))
825                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
826                                                 dev->name, priv->interruptReceive);
827
828                         err = -1;
829                         goto rx_irq_fail;
830                 }
831         } else {
832                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
833                                 0, "gfar_interrupt", dev) < 0) {
834                         if (netif_msg_intr(priv))
835                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
836                                         dev->name, priv->interruptError);
837
838                         err = -1;
839                         goto err_irq_fail;
840                 }
841         }
842
843         phy_start(priv->phydev);
844
845         /* Configure the coalescing support */
846         if (priv->txcoalescing)
847                 gfar_write(&regs->txic,
848                            mk_ic_value(priv->txcount, priv->txtime));
849         else
850                 gfar_write(&regs->txic, 0);
851
852         if (priv->rxcoalescing)
853                 gfar_write(&regs->rxic,
854                            mk_ic_value(priv->rxcount, priv->rxtime));
855         else
856                 gfar_write(&regs->rxic, 0);
857
858         if (priv->rx_csum_enable)
859                 rctrl |= RCTRL_CHECKSUMMING;
860
861         if (priv->extended_hash) {
862                 rctrl |= RCTRL_EXTHASH;
863
864                 gfar_clear_exact_match(dev);
865                 rctrl |= RCTRL_EMEN;
866         }
867
868         if (priv->vlan_enable)
869                 rctrl |= RCTRL_VLAN;
870
871         if (priv->padding) {
872                 rctrl &= ~RCTRL_PAL_MASK;
873                 rctrl |= RCTRL_PADDING(priv->padding);
874         }
875
876         /* Init rctrl based on our settings */
877         gfar_write(&priv->regs->rctrl, rctrl);
878
879         if (dev->features & NETIF_F_IP_CSUM)
880                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
881
882         /* Set the extraction length and index */
883         attrs = ATTRELI_EL(priv->rx_stash_size) |
884                 ATTRELI_EI(priv->rx_stash_index);
885
886         gfar_write(&priv->regs->attreli, attrs);
887
888         /* Start with defaults, and add stashing or locking
889          * depending on the approprate variables */
890         attrs = ATTR_INIT_SETTINGS;
891
892         if (priv->bd_stash_en)
893                 attrs |= ATTR_BDSTASH;
894
895         if (priv->rx_stash_size != 0)
896                 attrs |= ATTR_BUFSTASH;
897
898         gfar_write(&priv->regs->attr, attrs);
899
900         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
901         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
902         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
903
904         /* Start the controller */
905         gfar_start(dev);
906
907         return 0;
908
909 rx_irq_fail:
910         free_irq(priv->interruptTransmit, dev);
911 tx_irq_fail:
912         free_irq(priv->interruptError, dev);
913 err_irq_fail:
914 rx_skb_fail:
915         free_skb_resources(priv);
916 tx_skb_fail:
917         dma_free_coherent(NULL,
918                         sizeof(struct txbd8)*priv->tx_ring_size
919                         + sizeof(struct rxbd8)*priv->rx_ring_size,
920                         priv->tx_bd_base,
921                         gfar_read(&regs->tbase0));
922
923         return err;
924 }
925
926 /* Called when something needs to use the ethernet device */
927 /* Returns 0 for success. */
928 static int gfar_enet_open(struct net_device *dev)
929 {
930         int err;
931
932         /* Initialize a bunch of registers */
933         init_registers(dev);
934
935         gfar_set_mac_address(dev);
936
937         err = init_phy(dev);
938
939         if(err)
940                 return err;
941
942         err = startup_gfar(dev);
943
944         netif_start_queue(dev);
945
946         return err;
947 }
948
949 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
950 {
951         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
952
953         memset(fcb, 0, GMAC_FCB_LEN);
954
955         return fcb;
956 }
957
958 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
959 {
960         u8 flags = 0;
961
962         /* If we're here, it's a IP packet with a TCP or UDP
963          * payload.  We set it to checksum, using a pseudo-header
964          * we provide
965          */
966         flags = TXFCB_DEFAULT;
967
968         /* Tell the controller what the protocol is */
969         /* And provide the already calculated phcs */
970         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
971                 flags |= TXFCB_UDP;
972                 fcb->phcs = udp_hdr(skb)->check;
973         } else
974                 fcb->phcs = tcp_hdr(skb)->check;
975
976         /* l3os is the distance between the start of the
977          * frame (skb->data) and the start of the IP hdr.
978          * l4os is the distance between the start of the
979          * l3 hdr and the l4 hdr */
980         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
981         fcb->l4os = skb_network_header_len(skb);
982
983         fcb->flags = flags;
984 }
985
986 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
987 {
988         fcb->flags |= TXFCB_VLN;
989         fcb->vlctl = vlan_tx_tag_get(skb);
990 }
991
992 /* This is called by the kernel when a frame is ready for transmission. */
993 /* It is pointed to by the dev->hard_start_xmit function pointer */
994 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
995 {
996         struct gfar_private *priv = netdev_priv(dev);
997         struct txfcb *fcb = NULL;
998         struct txbd8 *txbdp;
999         u16 status;
1000         unsigned long flags;
1001
1002         /* Update transmit stats */
1003         priv->stats.tx_bytes += skb->len;
1004
1005         /* Lock priv now */
1006         spin_lock_irqsave(&priv->txlock, flags);
1007
1008         /* Point at the first free tx descriptor */
1009         txbdp = priv->cur_tx;
1010
1011         /* Clear all but the WRAP status flags */
1012         status = txbdp->status & TXBD_WRAP;
1013
1014         /* Set up checksumming */
1015         if (likely((dev->features & NETIF_F_IP_CSUM)
1016                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1017                 fcb = gfar_add_fcb(skb, txbdp);
1018                 status |= TXBD_TOE;
1019                 gfar_tx_checksum(skb, fcb);
1020         }
1021
1022         if (priv->vlan_enable &&
1023                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1024                 if (unlikely(NULL == fcb)) {
1025                         fcb = gfar_add_fcb(skb, txbdp);
1026                         status |= TXBD_TOE;
1027                 }
1028
1029                 gfar_tx_vlan(skb, fcb);
1030         }
1031
1032         /* Set buffer length and pointer */
1033         txbdp->length = skb->len;
1034         txbdp->bufPtr = dma_map_single(NULL, skb->data,
1035                         skb->len, DMA_TO_DEVICE);
1036
1037         /* Save the skb pointer so we can free it later */
1038         priv->tx_skbuff[priv->skb_curtx] = skb;
1039
1040         /* Update the current skb pointer (wrapping if this was the last) */
1041         priv->skb_curtx =
1042             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1043
1044         /* Flag the BD as interrupt-causing */
1045         status |= TXBD_INTERRUPT;
1046
1047         /* Flag the BD as ready to go, last in frame, and  */
1048         /* in need of CRC */
1049         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1050
1051         dev->trans_start = jiffies;
1052
1053         /* The powerpc-specific eieio() is used, as wmb() has too strong
1054          * semantics (it requires synchronization between cacheable and
1055          * uncacheable mappings, which eieio doesn't provide and which we
1056          * don't need), thus requiring a more expensive sync instruction.  At
1057          * some point, the set of architecture-independent barrier functions
1058          * should be expanded to include weaker barriers.
1059          */
1060
1061         eieio();
1062         txbdp->status = status;
1063
1064         /* If this was the last BD in the ring, the next one */
1065         /* is at the beginning of the ring */
1066         if (txbdp->status & TXBD_WRAP)
1067                 txbdp = priv->tx_bd_base;
1068         else
1069                 txbdp++;
1070
1071         /* If the next BD still needs to be cleaned up, then the bds
1072            are full.  We need to tell the kernel to stop sending us stuff. */
1073         if (txbdp == priv->dirty_tx) {
1074                 netif_stop_queue(dev);
1075
1076                 priv->stats.tx_fifo_errors++;
1077         }
1078
1079         /* Update the current txbd to the next one */
1080         priv->cur_tx = txbdp;
1081
1082         /* Tell the DMA to go go go */
1083         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1084
1085         /* Unlock priv */
1086         spin_unlock_irqrestore(&priv->txlock, flags);
1087
1088         return 0;
1089 }
1090
1091 /* Stops the kernel queue, and halts the controller */
1092 static int gfar_close(struct net_device *dev)
1093 {
1094         struct gfar_private *priv = netdev_priv(dev);
1095         stop_gfar(dev);
1096
1097         /* Disconnect from the PHY */
1098         phy_disconnect(priv->phydev);
1099         priv->phydev = NULL;
1100
1101         netif_stop_queue(dev);
1102
1103         return 0;
1104 }
1105
1106 /* returns a net_device_stats structure pointer */
1107 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1108 {
1109         struct gfar_private *priv = netdev_priv(dev);
1110
1111         return &(priv->stats);
1112 }
1113
1114 /* Changes the mac address if the controller is not running. */
1115 int gfar_set_mac_address(struct net_device *dev)
1116 {
1117         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1118
1119         return 0;
1120 }
1121
1122
1123 /* Enables and disables VLAN insertion/extraction */
1124 static void gfar_vlan_rx_register(struct net_device *dev,
1125                 struct vlan_group *grp)
1126 {
1127         struct gfar_private *priv = netdev_priv(dev);
1128         unsigned long flags;
1129         u32 tempval;
1130
1131         spin_lock_irqsave(&priv->rxlock, flags);
1132
1133         priv->vlgrp = grp;
1134
1135         if (grp) {
1136                 /* Enable VLAN tag insertion */
1137                 tempval = gfar_read(&priv->regs->tctrl);
1138                 tempval |= TCTRL_VLINS;
1139
1140                 gfar_write(&priv->regs->tctrl, tempval);
1141
1142                 /* Enable VLAN tag extraction */
1143                 tempval = gfar_read(&priv->regs->rctrl);
1144                 tempval |= RCTRL_VLEX;
1145                 gfar_write(&priv->regs->rctrl, tempval);
1146         } else {
1147                 /* Disable VLAN tag insertion */
1148                 tempval = gfar_read(&priv->regs->tctrl);
1149                 tempval &= ~TCTRL_VLINS;
1150                 gfar_write(&priv->regs->tctrl, tempval);
1151
1152                 /* Disable VLAN tag extraction */
1153                 tempval = gfar_read(&priv->regs->rctrl);
1154                 tempval &= ~RCTRL_VLEX;
1155                 gfar_write(&priv->regs->rctrl, tempval);
1156         }
1157
1158         spin_unlock_irqrestore(&priv->rxlock, flags);
1159 }
1160
1161 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1162 {
1163         int tempsize, tempval;
1164         struct gfar_private *priv = netdev_priv(dev);
1165         int oldsize = priv->rx_buffer_size;
1166         int frame_size = new_mtu + ETH_HLEN;
1167
1168         if (priv->vlan_enable)
1169                 frame_size += VLAN_ETH_HLEN;
1170
1171         if (gfar_uses_fcb(priv))
1172                 frame_size += GMAC_FCB_LEN;
1173
1174         frame_size += priv->padding;
1175
1176         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1177                 if (netif_msg_drv(priv))
1178                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1179                                         dev->name);
1180                 return -EINVAL;
1181         }
1182
1183         tempsize =
1184             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1185             INCREMENTAL_BUFFER_SIZE;
1186
1187         /* Only stop and start the controller if it isn't already
1188          * stopped, and we changed something */
1189         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1190                 stop_gfar(dev);
1191
1192         priv->rx_buffer_size = tempsize;
1193
1194         dev->mtu = new_mtu;
1195
1196         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1197         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1198
1199         /* If the mtu is larger than the max size for standard
1200          * ethernet frames (ie, a jumbo frame), then set maccfg2
1201          * to allow huge frames, and to check the length */
1202         tempval = gfar_read(&priv->regs->maccfg2);
1203
1204         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1205                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1206         else
1207                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1208
1209         gfar_write(&priv->regs->maccfg2, tempval);
1210
1211         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1212                 startup_gfar(dev);
1213
1214         return 0;
1215 }
1216
1217 /* gfar_timeout gets called when a packet has not been
1218  * transmitted after a set amount of time.
1219  * For now, assume that clearing out all the structures, and
1220  * starting over will fix the problem. */
1221 static void gfar_timeout(struct net_device *dev)
1222 {
1223         struct gfar_private *priv = netdev_priv(dev);
1224
1225         priv->stats.tx_errors++;
1226
1227         if (dev->flags & IFF_UP) {
1228                 stop_gfar(dev);
1229                 startup_gfar(dev);
1230         }
1231
1232         netif_schedule(dev);
1233 }
1234
1235 /* Interrupt Handler for Transmit complete */
1236 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1237 {
1238         struct net_device *dev = (struct net_device *) dev_id;
1239         struct gfar_private *priv = netdev_priv(dev);
1240         struct txbd8 *bdp;
1241
1242         /* Clear IEVENT */
1243         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1244
1245         /* Lock priv */
1246         spin_lock(&priv->txlock);
1247         bdp = priv->dirty_tx;
1248         while ((bdp->status & TXBD_READY) == 0) {
1249                 /* If dirty_tx and cur_tx are the same, then either the */
1250                 /* ring is empty or full now (it could only be full in the beginning, */
1251                 /* obviously).  If it is empty, we are done. */
1252                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1253                         break;
1254
1255                 priv->stats.tx_packets++;
1256
1257                 /* Deferred means some collisions occurred during transmit, */
1258                 /* but we eventually sent the packet. */
1259                 if (bdp->status & TXBD_DEF)
1260                         priv->stats.collisions++;
1261
1262                 /* Free the sk buffer associated with this TxBD */
1263                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1264                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1265                 priv->skb_dirtytx =
1266                     (priv->skb_dirtytx +
1267                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1268
1269                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1270                 if (bdp->status & TXBD_WRAP)
1271                         bdp = priv->tx_bd_base;
1272                 else
1273                         bdp++;
1274
1275                 /* Move dirty_tx to be the next bd */
1276                 priv->dirty_tx = bdp;
1277
1278                 /* We freed a buffer, so now we can restart transmission */
1279                 if (netif_queue_stopped(dev))
1280                         netif_wake_queue(dev);
1281         } /* while ((bdp->status & TXBD_READY) == 0) */
1282
1283         /* If we are coalescing the interrupts, reset the timer */
1284         /* Otherwise, clear it */
1285         if (priv->txcoalescing)
1286                 gfar_write(&priv->regs->txic,
1287                            mk_ic_value(priv->txcount, priv->txtime));
1288         else
1289                 gfar_write(&priv->regs->txic, 0);
1290
1291         spin_unlock(&priv->txlock);
1292
1293         return IRQ_HANDLED;
1294 }
1295
1296 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1297 {
1298         unsigned int alignamount;
1299         struct gfar_private *priv = netdev_priv(dev);
1300         struct sk_buff *skb = NULL;
1301         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1302
1303         /* We have to allocate the skb, so keep trying till we succeed */
1304         while ((!skb) && timeout--)
1305                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1306
1307         if (NULL == skb)
1308                 return NULL;
1309
1310         alignamount = RXBUF_ALIGNMENT -
1311                 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1312
1313         /* We need the data buffer to be aligned properly.  We will reserve
1314          * as many bytes as needed to align the data properly
1315          */
1316         skb_reserve(skb, alignamount);
1317
1318         bdp->bufPtr = dma_map_single(NULL, skb->data,
1319                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1320
1321         bdp->length = 0;
1322
1323         /* Mark the buffer empty */
1324         eieio();
1325         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1326
1327         return skb;
1328 }
1329
1330 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1331 {
1332         struct net_device_stats *stats = &priv->stats;
1333         struct gfar_extra_stats *estats = &priv->extra_stats;
1334
1335         /* If the packet was truncated, none of the other errors
1336          * matter */
1337         if (status & RXBD_TRUNCATED) {
1338                 stats->rx_length_errors++;
1339
1340                 estats->rx_trunc++;
1341
1342                 return;
1343         }
1344         /* Count the errors, if there were any */
1345         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1346                 stats->rx_length_errors++;
1347
1348                 if (status & RXBD_LARGE)
1349                         estats->rx_large++;
1350                 else
1351                         estats->rx_short++;
1352         }
1353         if (status & RXBD_NONOCTET) {
1354                 stats->rx_frame_errors++;
1355                 estats->rx_nonoctet++;
1356         }
1357         if (status & RXBD_CRCERR) {
1358                 estats->rx_crcerr++;
1359                 stats->rx_crc_errors++;
1360         }
1361         if (status & RXBD_OVERRUN) {
1362                 estats->rx_overrun++;
1363                 stats->rx_crc_errors++;
1364         }
1365 }
1366
1367 irqreturn_t gfar_receive(int irq, void *dev_id)
1368 {
1369         struct net_device *dev = (struct net_device *) dev_id;
1370         struct gfar_private *priv = netdev_priv(dev);
1371 #ifdef CONFIG_GFAR_NAPI
1372         u32 tempval;
1373 #else
1374         unsigned long flags;
1375 #endif
1376
1377         /* Clear IEVENT, so rx interrupt isn't called again
1378          * because of this interrupt */
1379         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1380
1381         /* support NAPI */
1382 #ifdef CONFIG_GFAR_NAPI
1383         if (netif_rx_schedule_prep(dev)) {
1384                 tempval = gfar_read(&priv->regs->imask);
1385                 tempval &= IMASK_RX_DISABLED;
1386                 gfar_write(&priv->regs->imask, tempval);
1387
1388                 __netif_rx_schedule(dev);
1389         } else {
1390                 if (netif_msg_rx_err(priv))
1391                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1392                                 dev->name, gfar_read(&priv->regs->ievent),
1393                                 gfar_read(&priv->regs->imask));
1394         }
1395 #else
1396
1397         spin_lock_irqsave(&priv->rxlock, flags);
1398         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1399
1400         /* If we are coalescing interrupts, update the timer */
1401         /* Otherwise, clear it */
1402         if (priv->rxcoalescing)
1403                 gfar_write(&priv->regs->rxic,
1404                            mk_ic_value(priv->rxcount, priv->rxtime));
1405         else
1406                 gfar_write(&priv->regs->rxic, 0);
1407
1408         spin_unlock_irqrestore(&priv->rxlock, flags);
1409 #endif
1410
1411         return IRQ_HANDLED;
1412 }
1413
1414 static inline int gfar_rx_vlan(struct sk_buff *skb,
1415                 struct vlan_group *vlgrp, unsigned short vlctl)
1416 {
1417 #ifdef CONFIG_GFAR_NAPI
1418         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1419 #else
1420         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1421 #endif
1422 }
1423
1424 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1425 {
1426         /* If valid headers were found, and valid sums
1427          * were verified, then we tell the kernel that no
1428          * checksumming is necessary.  Otherwise, it is */
1429         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1430                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1431         else
1432                 skb->ip_summed = CHECKSUM_NONE;
1433 }
1434
1435
1436 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1437 {
1438         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1439
1440         /* Remove the FCB from the skb */
1441         skb_pull(skb, GMAC_FCB_LEN);
1442
1443         return fcb;
1444 }
1445
1446 /* gfar_process_frame() -- handle one incoming packet if skb
1447  * isn't NULL.  */
1448 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1449                 int length)
1450 {
1451         struct gfar_private *priv = netdev_priv(dev);
1452         struct rxfcb *fcb = NULL;
1453
1454         if (NULL == skb) {
1455                 if (netif_msg_rx_err(priv))
1456                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1457                 priv->stats.rx_dropped++;
1458                 priv->extra_stats.rx_skbmissing++;
1459         } else {
1460                 int ret;
1461
1462                 /* Prep the skb for the packet */
1463                 skb_put(skb, length);
1464
1465                 /* Grab the FCB if there is one */
1466                 if (gfar_uses_fcb(priv))
1467                         fcb = gfar_get_fcb(skb);
1468
1469                 /* Remove the padded bytes, if there are any */
1470                 if (priv->padding)
1471                         skb_pull(skb, priv->padding);
1472
1473                 if (priv->rx_csum_enable)
1474                         gfar_rx_checksum(skb, fcb);
1475
1476                 /* Tell the skb what kind of packet this is */
1477                 skb->protocol = eth_type_trans(skb, dev);
1478
1479                 /* Send the packet up the stack */
1480                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1481                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1482                 else
1483                         ret = RECEIVE(skb);
1484
1485                 if (NET_RX_DROP == ret)
1486                         priv->extra_stats.kernel_dropped++;
1487         }
1488
1489         return 0;
1490 }
1491
1492 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1493  *   until the budget/quota has been reached. Returns the number
1494  *   of frames handled
1495  */
1496 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1497 {
1498         struct rxbd8 *bdp;
1499         struct sk_buff *skb;
1500         u16 pkt_len;
1501         int howmany = 0;
1502         struct gfar_private *priv = netdev_priv(dev);
1503
1504         /* Get the first full descriptor */
1505         bdp = priv->cur_rx;
1506
1507         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1508                 rmb();
1509                 skb = priv->rx_skbuff[priv->skb_currx];
1510
1511                 if (!(bdp->status &
1512                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1513                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1514                         /* Increment the number of packets */
1515                         priv->stats.rx_packets++;
1516                         howmany++;
1517
1518                         /* Remove the FCS from the packet length */
1519                         pkt_len = bdp->length - 4;
1520
1521                         gfar_process_frame(dev, skb, pkt_len);
1522
1523                         priv->stats.rx_bytes += pkt_len;
1524                 } else {
1525                         count_errors(bdp->status, priv);
1526
1527                         if (skb)
1528                                 dev_kfree_skb_any(skb);
1529
1530                         priv->rx_skbuff[priv->skb_currx] = NULL;
1531                 }
1532
1533                 dev->last_rx = jiffies;
1534
1535                 /* Clear the status flags for this buffer */
1536                 bdp->status &= ~RXBD_STATS;
1537
1538                 /* Add another skb for the future */
1539                 skb = gfar_new_skb(dev, bdp);
1540                 priv->rx_skbuff[priv->skb_currx] = skb;
1541
1542                 /* Update to the next pointer */
1543                 if (bdp->status & RXBD_WRAP)
1544                         bdp = priv->rx_bd_base;
1545                 else
1546                         bdp++;
1547
1548                 /* update to point at the next skb */
1549                 priv->skb_currx =
1550                     (priv->skb_currx +
1551                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1552
1553         }
1554
1555         /* Update the current rxbd pointer to be the next one */
1556         priv->cur_rx = bdp;
1557
1558         return howmany;
1559 }
1560
1561 #ifdef CONFIG_GFAR_NAPI
1562 static int gfar_poll(struct net_device *dev, int *budget)
1563 {
1564         int howmany;
1565         struct gfar_private *priv = netdev_priv(dev);
1566         int rx_work_limit = *budget;
1567
1568         if (rx_work_limit > dev->quota)
1569                 rx_work_limit = dev->quota;
1570
1571         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1572
1573         dev->quota -= howmany;
1574         rx_work_limit -= howmany;
1575         *budget -= howmany;
1576
1577         if (rx_work_limit > 0) {
1578                 netif_rx_complete(dev);
1579
1580                 /* Clear the halt bit in RSTAT */
1581                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1582
1583                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1584
1585                 /* If we are coalescing interrupts, update the timer */
1586                 /* Otherwise, clear it */
1587                 if (priv->rxcoalescing)
1588                         gfar_write(&priv->regs->rxic,
1589                                    mk_ic_value(priv->rxcount, priv->rxtime));
1590                 else
1591                         gfar_write(&priv->regs->rxic, 0);
1592         }
1593
1594         /* Return 1 if there's more work to do */
1595         return (rx_work_limit > 0) ? 0 : 1;
1596 }
1597 #endif
1598
1599 #ifdef CONFIG_NET_POLL_CONTROLLER
1600 /*
1601  * Polling 'interrupt' - used by things like netconsole to send skbs
1602  * without having to re-enable interrupts. It's not called while
1603  * the interrupt routine is executing.
1604  */
1605 static void gfar_netpoll(struct net_device *dev)
1606 {
1607         struct gfar_private *priv = netdev_priv(dev);
1608
1609         /* If the device has multiple interrupts, run tx/rx */
1610         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1611                 disable_irq(priv->interruptTransmit);
1612                 disable_irq(priv->interruptReceive);
1613                 disable_irq(priv->interruptError);
1614                 gfar_interrupt(priv->interruptTransmit, dev);
1615                 enable_irq(priv->interruptError);
1616                 enable_irq(priv->interruptReceive);
1617                 enable_irq(priv->interruptTransmit);
1618         } else {
1619                 disable_irq(priv->interruptTransmit);
1620                 gfar_interrupt(priv->interruptTransmit, dev);
1621                 enable_irq(priv->interruptTransmit);
1622         }
1623 }
1624 #endif
1625
1626 /* The interrupt handler for devices with one interrupt */
1627 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1628 {
1629         struct net_device *dev = dev_id;
1630         struct gfar_private *priv = netdev_priv(dev);
1631
1632         /* Save ievent for future reference */
1633         u32 events = gfar_read(&priv->regs->ievent);
1634
1635         /* Check for reception */
1636         if (events & IEVENT_RX_MASK)
1637                 gfar_receive(irq, dev_id);
1638
1639         /* Check for transmit completion */
1640         if (events & IEVENT_TX_MASK)
1641                 gfar_transmit(irq, dev_id);
1642
1643         /* Check for errors */
1644         if (events & IEVENT_ERR_MASK)
1645                 gfar_error(irq, dev_id);
1646
1647         return IRQ_HANDLED;
1648 }
1649
1650 /* Called every time the controller might need to be made
1651  * aware of new link state.  The PHY code conveys this
1652  * information through variables in the phydev structure, and this
1653  * function converts those variables into the appropriate
1654  * register values, and can bring down the device if needed.
1655  */
1656 static void adjust_link(struct net_device *dev)
1657 {
1658         struct gfar_private *priv = netdev_priv(dev);
1659         struct gfar __iomem *regs = priv->regs;
1660         unsigned long flags;
1661         struct phy_device *phydev = priv->phydev;
1662         int new_state = 0;
1663
1664         spin_lock_irqsave(&priv->txlock, flags);
1665         if (phydev->link) {
1666                 u32 tempval = gfar_read(&regs->maccfg2);
1667                 u32 ecntrl = gfar_read(&regs->ecntrl);
1668
1669                 /* Now we make sure that we can be in full duplex mode.
1670                  * If not, we operate in half-duplex mode. */
1671                 if (phydev->duplex != priv->oldduplex) {
1672                         new_state = 1;
1673                         if (!(phydev->duplex))
1674                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1675                         else
1676                                 tempval |= MACCFG2_FULL_DUPLEX;
1677
1678                         priv->oldduplex = phydev->duplex;
1679                 }
1680
1681                 if (phydev->speed != priv->oldspeed) {
1682                         new_state = 1;
1683                         switch (phydev->speed) {
1684                         case 1000:
1685                                 tempval =
1686                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1687                                 break;
1688                         case 100:
1689                         case 10:
1690                                 tempval =
1691                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1692
1693                                 /* Reduced mode distinguishes
1694                                  * between 10 and 100 */
1695                                 if (phydev->speed == SPEED_100)
1696                                         ecntrl |= ECNTRL_R100;
1697                                 else
1698                                         ecntrl &= ~(ECNTRL_R100);
1699                                 break;
1700                         default:
1701                                 if (netif_msg_link(priv))
1702                                         printk(KERN_WARNING
1703                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1704                                                 dev->name, phydev->speed);
1705                                 break;
1706                         }
1707
1708                         priv->oldspeed = phydev->speed;
1709                 }
1710
1711                 gfar_write(&regs->maccfg2, tempval);
1712                 gfar_write(&regs->ecntrl, ecntrl);
1713
1714                 if (!priv->oldlink) {
1715                         new_state = 1;
1716                         priv->oldlink = 1;
1717                         netif_schedule(dev);
1718                 }
1719         } else if (priv->oldlink) {
1720                 new_state = 1;
1721                 priv->oldlink = 0;
1722                 priv->oldspeed = 0;
1723                 priv->oldduplex = -1;
1724         }
1725
1726         if (new_state && netif_msg_link(priv))
1727                 phy_print_status(phydev);
1728
1729         spin_unlock_irqrestore(&priv->txlock, flags);
1730 }
1731
1732 /* Update the hash table based on the current list of multicast
1733  * addresses we subscribe to.  Also, change the promiscuity of
1734  * the device based on the flags (this function is called
1735  * whenever dev->flags is changed */
1736 static void gfar_set_multi(struct net_device *dev)
1737 {
1738         struct dev_mc_list *mc_ptr;
1739         struct gfar_private *priv = netdev_priv(dev);
1740         struct gfar __iomem *regs = priv->regs;
1741         u32 tempval;
1742
1743         if(dev->flags & IFF_PROMISC) {
1744                 /* Set RCTRL to PROM */
1745                 tempval = gfar_read(&regs->rctrl);
1746                 tempval |= RCTRL_PROM;
1747                 gfar_write(&regs->rctrl, tempval);
1748         } else {
1749                 /* Set RCTRL to not PROM */
1750                 tempval = gfar_read(&regs->rctrl);
1751                 tempval &= ~(RCTRL_PROM);
1752                 gfar_write(&regs->rctrl, tempval);
1753         }
1754
1755         if(dev->flags & IFF_ALLMULTI) {
1756                 /* Set the hash to rx all multicast frames */
1757                 gfar_write(&regs->igaddr0, 0xffffffff);
1758                 gfar_write(&regs->igaddr1, 0xffffffff);
1759                 gfar_write(&regs->igaddr2, 0xffffffff);
1760                 gfar_write(&regs->igaddr3, 0xffffffff);
1761                 gfar_write(&regs->igaddr4, 0xffffffff);
1762                 gfar_write(&regs->igaddr5, 0xffffffff);
1763                 gfar_write(&regs->igaddr6, 0xffffffff);
1764                 gfar_write(&regs->igaddr7, 0xffffffff);
1765                 gfar_write(&regs->gaddr0, 0xffffffff);
1766                 gfar_write(&regs->gaddr1, 0xffffffff);
1767                 gfar_write(&regs->gaddr2, 0xffffffff);
1768                 gfar_write(&regs->gaddr3, 0xffffffff);
1769                 gfar_write(&regs->gaddr4, 0xffffffff);
1770                 gfar_write(&regs->gaddr5, 0xffffffff);
1771                 gfar_write(&regs->gaddr6, 0xffffffff);
1772                 gfar_write(&regs->gaddr7, 0xffffffff);
1773         } else {
1774                 int em_num;
1775                 int idx;
1776
1777                 /* zero out the hash */
1778                 gfar_write(&regs->igaddr0, 0x0);
1779                 gfar_write(&regs->igaddr1, 0x0);
1780                 gfar_write(&regs->igaddr2, 0x0);
1781                 gfar_write(&regs->igaddr3, 0x0);
1782                 gfar_write(&regs->igaddr4, 0x0);
1783                 gfar_write(&regs->igaddr5, 0x0);
1784                 gfar_write(&regs->igaddr6, 0x0);
1785                 gfar_write(&regs->igaddr7, 0x0);
1786                 gfar_write(&regs->gaddr0, 0x0);
1787                 gfar_write(&regs->gaddr1, 0x0);
1788                 gfar_write(&regs->gaddr2, 0x0);
1789                 gfar_write(&regs->gaddr3, 0x0);
1790                 gfar_write(&regs->gaddr4, 0x0);
1791                 gfar_write(&regs->gaddr5, 0x0);
1792                 gfar_write(&regs->gaddr6, 0x0);
1793                 gfar_write(&regs->gaddr7, 0x0);
1794
1795                 /* If we have extended hash tables, we need to
1796                  * clear the exact match registers to prepare for
1797                  * setting them */
1798                 if (priv->extended_hash) {
1799                         em_num = GFAR_EM_NUM + 1;
1800                         gfar_clear_exact_match(dev);
1801                         idx = 1;
1802                 } else {
1803                         idx = 0;
1804                         em_num = 0;
1805                 }
1806
1807                 if(dev->mc_count == 0)
1808                         return;
1809
1810                 /* Parse the list, and set the appropriate bits */
1811                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1812                         if (idx < em_num) {
1813                                 gfar_set_mac_for_addr(dev, idx,
1814                                                 mc_ptr->dmi_addr);
1815                                 idx++;
1816                         } else
1817                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1818                 }
1819         }
1820
1821         return;
1822 }
1823
1824
1825 /* Clears each of the exact match registers to zero, so they
1826  * don't interfere with normal reception */
1827 static void gfar_clear_exact_match(struct net_device *dev)
1828 {
1829         int idx;
1830         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1831
1832         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1833                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1834 }
1835
1836 /* Set the appropriate hash bit for the given addr */
1837 /* The algorithm works like so:
1838  * 1) Take the Destination Address (ie the multicast address), and
1839  * do a CRC on it (little endian), and reverse the bits of the
1840  * result.
1841  * 2) Use the 8 most significant bits as a hash into a 256-entry
1842  * table.  The table is controlled through 8 32-bit registers:
1843  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1844  * gaddr7.  This means that the 3 most significant bits in the
1845  * hash index which gaddr register to use, and the 5 other bits
1846  * indicate which bit (assuming an IBM numbering scheme, which
1847  * for PowerPC (tm) is usually the case) in the register holds
1848  * the entry. */
1849 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1850 {
1851         u32 tempval;
1852         struct gfar_private *priv = netdev_priv(dev);
1853         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1854         int width = priv->hash_width;
1855         u8 whichbit = (result >> (32 - width)) & 0x1f;
1856         u8 whichreg = result >> (32 - width + 5);
1857         u32 value = (1 << (31-whichbit));
1858
1859         tempval = gfar_read(priv->hash_regs[whichreg]);
1860         tempval |= value;
1861         gfar_write(priv->hash_regs[whichreg], tempval);
1862
1863         return;
1864 }
1865
1866
1867 /* There are multiple MAC Address register pairs on some controllers
1868  * This function sets the numth pair to a given address
1869  */
1870 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1871 {
1872         struct gfar_private *priv = netdev_priv(dev);
1873         int idx;
1874         char tmpbuf[MAC_ADDR_LEN];
1875         u32 tempval;
1876         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1877
1878         macptr += num*2;
1879
1880         /* Now copy it into the mac registers backwards, cuz */
1881         /* little endian is silly */
1882         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1883                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1884
1885         gfar_write(macptr, *((u32 *) (tmpbuf)));
1886
1887         tempval = *((u32 *) (tmpbuf + 4));
1888
1889         gfar_write(macptr+1, tempval);
1890 }
1891
1892 /* GFAR error interrupt handler */
1893 static irqreturn_t gfar_error(int irq, void *dev_id)
1894 {
1895         struct net_device *dev = dev_id;
1896         struct gfar_private *priv = netdev_priv(dev);
1897
1898         /* Save ievent for future reference */
1899         u32 events = gfar_read(&priv->regs->ievent);
1900
1901         /* Clear IEVENT */
1902         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1903
1904         /* Hmm... */
1905         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1906                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1907                        dev->name, events, gfar_read(&priv->regs->imask));
1908
1909         /* Update the error counters */
1910         if (events & IEVENT_TXE) {
1911                 priv->stats.tx_errors++;
1912
1913                 if (events & IEVENT_LC)
1914                         priv->stats.tx_window_errors++;
1915                 if (events & IEVENT_CRL)
1916                         priv->stats.tx_aborted_errors++;
1917                 if (events & IEVENT_XFUN) {
1918                         if (netif_msg_tx_err(priv))
1919                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1920                                        "packet dropped.\n", dev->name);
1921                         priv->stats.tx_dropped++;
1922                         priv->extra_stats.tx_underrun++;
1923
1924                         /* Reactivate the Tx Queues */
1925                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1926                 }
1927                 if (netif_msg_tx_err(priv))
1928                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1929         }
1930         if (events & IEVENT_BSY) {
1931                 priv->stats.rx_errors++;
1932                 priv->extra_stats.rx_bsy++;
1933
1934                 gfar_receive(irq, dev_id);
1935
1936 #ifndef CONFIG_GFAR_NAPI
1937                 /* Clear the halt bit in RSTAT */
1938                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1939 #endif
1940
1941                 if (netif_msg_rx_err(priv))
1942                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
1943                                dev->name, gfar_read(&priv->regs->rstat));
1944         }
1945         if (events & IEVENT_BABR) {
1946                 priv->stats.rx_errors++;
1947                 priv->extra_stats.rx_babr++;
1948
1949                 if (netif_msg_rx_err(priv))
1950                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1951         }
1952         if (events & IEVENT_EBERR) {
1953                 priv->extra_stats.eberr++;
1954                 if (netif_msg_rx_err(priv))
1955                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
1956         }
1957         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1958                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1959
1960         if (events & IEVENT_BABT) {
1961                 priv->extra_stats.tx_babt++;
1962                 if (netif_msg_tx_err(priv))
1963                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1964         }
1965         return IRQ_HANDLED;
1966 }
1967
1968 /* Structure for a device driver */
1969 static struct platform_driver gfar_driver = {
1970         .probe = gfar_probe,
1971         .remove = gfar_remove,
1972         .driver = {
1973                 .name = "fsl-gianfar",
1974         },
1975 };
1976
1977 static int __init gfar_init(void)
1978 {
1979         int err = gfar_mdio_init();
1980
1981         if (err)
1982                 return err;
1983
1984         err = platform_driver_register(&gfar_driver);
1985
1986         if (err)
1987                 gfar_mdio_exit();
1988
1989         return err;
1990 }
1991
1992 static void __exit gfar_exit(void)
1993 {
1994         platform_driver_unregister(&gfar_driver);
1995         gfar_mdio_exit();
1996 }
1997
1998 module_init(gfar_init);
1999 module_exit(gfar_exit);
2000