baa35144134c8a1459a7d104bc6e74db6123f4aa
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  *
14  * This program is free software; you can redistribute  it and/or modify it
15  * under  the terms of  the GNU General  Public License as published by the
16  * Free Software Foundation;  either version 2 of the  License, or (at your
17  * option) any later version.
18  *
19  *  Gianfar:  AKA Lambda Draconis, "Dragon"
20  *  RA 11 31 24.2
21  *  Dec +69 19 52
22  *  V 3.84
23  *  B-V +1.62
24  *
25  *  Theory of operation
26  *
27  *  The driver is initialized through platform_device.  Structures which
28  *  define the configuration needed by the board are defined in a
29  *  board structure in arch/ppc/platforms (though I do not
30  *  discount the possibility that other architectures could one
31  *  day be supported.
32  *
33  *  The Gianfar Ethernet Controller uses a ring of buffer
34  *  descriptors.  The beginning is indicated by a register
35  *  pointing to the physical address of the start of the ring.
36  *  The end is determined by a "wrap" bit being set in the
37  *  last descriptor of the ring.
38  *
39  *  When a packet is received, the RXF bit in the
40  *  IEVENT register is set, triggering an interrupt when the
41  *  corresponding bit in the IMASK register is also set (if
42  *  interrupt coalescing is active, then the interrupt may not
43  *  happen immediately, but will wait until either a set number
44  *  of frames or amount of time have passed).  In NAPI, the
45  *  interrupt handler will signal there is work to be done, and
46  *  exit.  Without NAPI, the packet(s) will be handled
47  *  immediately.  Both methods will start at the last known empty
48  *  descriptor, and process every subsequent descriptor until there
49  *  are none left with data (NAPI will stop after a set number of
50  *  packets to give time to other tasks, but will eventually
51  *  process all the packets).  The data arrives inside a
52  *  pre-allocated skb, and so after the skb is passed up to the
53  *  stack, a new skb must be allocated, and the address field in
54  *  the buffer descriptor must be updated to indicate this new
55  *  skb.
56  *
57  *  When the kernel requests that a packet be transmitted, the
58  *  driver starts where it left off last time, and points the
59  *  descriptor at the buffer which was passed in.  The driver
60  *  then informs the DMA engine that there are packets ready to
61  *  be transmitted.  Once the controller is finished transmitting
62  *  the packet, an interrupt may be triggered (under the same
63  *  conditions as for reception, but depending on the TXF bit).
64  *  The driver then cleans up the buffer.
65  */
66
67 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
81 #include <linux/mm.h>
82 #include <linux/platform_device.h>
83 #include <linux/ip.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
86 #include <linux/in.h>
87
88 #include <asm/io.h>
89 #include <asm/irq.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96
97 #include "gianfar.h"
98 #include "gianfar_mii.h"
99
100 #define TX_TIMEOUT      (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
104
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
107 #else
108 #define RECEIVE(x) netif_rx(x)
109 #endif
110
111 const char gfar_driver_name[] = "Gianfar Ethernet";
112 const char gfar_driver_version[] = "1.3";
113
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_timeout(struct net_device *dev);
117 static int gfar_close(struct net_device *dev);
118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
119 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
120 static int gfar_set_mac_address(struct net_device *dev);
121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
122 static irqreturn_t gfar_error(int irq, void *dev_id);
123 static irqreturn_t gfar_transmit(int irq, void *dev_id);
124 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
125 static void adjust_link(struct net_device *dev);
126 static void init_registers(struct net_device *dev);
127 static int init_phy(struct net_device *dev);
128 static int gfar_probe(struct platform_device *pdev);
129 static int gfar_remove(struct platform_device *pdev);
130 static void free_skb_resources(struct gfar_private *priv);
131 static void gfar_set_multi(struct net_device *dev);
132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
133 #ifdef CONFIG_GFAR_NAPI
134 static int gfar_poll(struct net_device *dev, int *budget);
135 #endif
136 #ifdef CONFIG_NET_POLL_CONTROLLER
137 static void gfar_netpoll(struct net_device *dev);
138 #endif
139 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
140 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
141 static void gfar_vlan_rx_register(struct net_device *netdev,
142                                 struct vlan_group *grp);
143 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
144 void gfar_halt(struct net_device *dev);
145 void gfar_start(struct net_device *dev);
146 static void gfar_clear_exact_match(struct net_device *dev);
147 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
148
149 extern const struct ethtool_ops gfar_ethtool_ops;
150
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
154
155 /* Returns 1 if incoming frames use an FCB */
156 static inline int gfar_uses_fcb(struct gfar_private *priv)
157 {
158         return (priv->vlan_enable || priv->rx_csum_enable);
159 }
160
161 /* Set up the ethernet device structure, private data,
162  * and anything else we need before we start */
163 static int gfar_probe(struct platform_device *pdev)
164 {
165         u32 tempval;
166         struct net_device *dev = NULL;
167         struct gfar_private *priv = NULL;
168         struct gianfar_platform_data *einfo;
169         struct resource *r;
170         int idx;
171         int err = 0;
172
173         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
174
175         if (NULL == einfo) {
176                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
177                        pdev->id);
178
179                 return -ENODEV;
180         }
181
182         /* Create an ethernet device instance */
183         dev = alloc_etherdev(sizeof (*priv));
184
185         if (NULL == dev)
186                 return -ENOMEM;
187
188         priv = netdev_priv(dev);
189
190         /* Set the info in the priv to the current info */
191         priv->einfo = einfo;
192
193         /* fill out IRQ fields */
194         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
195                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
196                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
197                 priv->interruptError = platform_get_irq_byname(pdev, "error");
198                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
199                         goto regs_fail;
200         } else {
201                 priv->interruptTransmit = platform_get_irq(pdev, 0);
202                 if (priv->interruptTransmit < 0)
203                         goto regs_fail;
204         }
205
206         /* get a pointer to the register memory */
207         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208         priv->regs = ioremap(r->start, sizeof (struct gfar));
209
210         if (NULL == priv->regs) {
211                 err = -ENOMEM;
212                 goto regs_fail;
213         }
214
215         spin_lock_init(&priv->txlock);
216         spin_lock_init(&priv->rxlock);
217
218         platform_set_drvdata(pdev, dev);
219
220         /* Stop the DMA engine now, in case it was running before */
221         /* (The firmware could have used it, and left it running). */
222         /* To do this, we write Graceful Receive Stop and Graceful */
223         /* Transmit Stop, and then wait until the corresponding bits */
224         /* in IEVENT indicate the stops have completed. */
225         tempval = gfar_read(&priv->regs->dmactrl);
226         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
227         gfar_write(&priv->regs->dmactrl, tempval);
228
229         tempval = gfar_read(&priv->regs->dmactrl);
230         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
231         gfar_write(&priv->regs->dmactrl, tempval);
232
233         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
234                 cpu_relax();
235
236         /* Reset MAC layer */
237         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
238
239         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
240         gfar_write(&priv->regs->maccfg1, tempval);
241
242         /* Initialize MACCFG2. */
243         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
244
245         /* Initialize ECNTRL */
246         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
247
248         /* Copy the station address into the dev structure, */
249         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
250
251         /* Set the dev->base_addr to the gfar reg region */
252         dev->base_addr = (unsigned long) (priv->regs);
253
254         SET_MODULE_OWNER(dev);
255         SET_NETDEV_DEV(dev, &pdev->dev);
256
257         /* Fill in the dev structure */
258         dev->open = gfar_enet_open;
259         dev->hard_start_xmit = gfar_start_xmit;
260         dev->tx_timeout = gfar_timeout;
261         dev->watchdog_timeo = TX_TIMEOUT;
262 #ifdef CONFIG_GFAR_NAPI
263         dev->poll = gfar_poll;
264         dev->weight = GFAR_DEV_WEIGHT;
265 #endif
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267         dev->poll_controller = gfar_netpoll;
268 #endif
269         dev->stop = gfar_close;
270         dev->get_stats = gfar_get_stats;
271         dev->change_mtu = gfar_change_mtu;
272         dev->mtu = 1500;
273         dev->set_multicast_list = gfar_set_multi;
274
275         dev->ethtool_ops = &gfar_ethtool_ops;
276
277         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
278                 priv->rx_csum_enable = 1;
279                 dev->features |= NETIF_F_IP_CSUM;
280         } else
281                 priv->rx_csum_enable = 0;
282
283         priv->vlgrp = NULL;
284
285         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
286                 dev->vlan_rx_register = gfar_vlan_rx_register;
287                 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
288
289                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
290
291                 priv->vlan_enable = 1;
292         }
293
294         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
295                 priv->extended_hash = 1;
296                 priv->hash_width = 9;
297
298                 priv->hash_regs[0] = &priv->regs->igaddr0;
299                 priv->hash_regs[1] = &priv->regs->igaddr1;
300                 priv->hash_regs[2] = &priv->regs->igaddr2;
301                 priv->hash_regs[3] = &priv->regs->igaddr3;
302                 priv->hash_regs[4] = &priv->regs->igaddr4;
303                 priv->hash_regs[5] = &priv->regs->igaddr5;
304                 priv->hash_regs[6] = &priv->regs->igaddr6;
305                 priv->hash_regs[7] = &priv->regs->igaddr7;
306                 priv->hash_regs[8] = &priv->regs->gaddr0;
307                 priv->hash_regs[9] = &priv->regs->gaddr1;
308                 priv->hash_regs[10] = &priv->regs->gaddr2;
309                 priv->hash_regs[11] = &priv->regs->gaddr3;
310                 priv->hash_regs[12] = &priv->regs->gaddr4;
311                 priv->hash_regs[13] = &priv->regs->gaddr5;
312                 priv->hash_regs[14] = &priv->regs->gaddr6;
313                 priv->hash_regs[15] = &priv->regs->gaddr7;
314
315         } else {
316                 priv->extended_hash = 0;
317                 priv->hash_width = 8;
318
319                 priv->hash_regs[0] = &priv->regs->gaddr0;
320                 priv->hash_regs[1] = &priv->regs->gaddr1;
321                 priv->hash_regs[2] = &priv->regs->gaddr2;
322                 priv->hash_regs[3] = &priv->regs->gaddr3;
323                 priv->hash_regs[4] = &priv->regs->gaddr4;
324                 priv->hash_regs[5] = &priv->regs->gaddr5;
325                 priv->hash_regs[6] = &priv->regs->gaddr6;
326                 priv->hash_regs[7] = &priv->regs->gaddr7;
327         }
328
329         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
330                 priv->padding = DEFAULT_PADDING;
331         else
332                 priv->padding = 0;
333
334         if (dev->features & NETIF_F_IP_CSUM)
335                 dev->hard_header_len += GMAC_FCB_LEN;
336
337         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
338         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
339         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
340
341         priv->txcoalescing = DEFAULT_TX_COALESCE;
342         priv->txcount = DEFAULT_TXCOUNT;
343         priv->txtime = DEFAULT_TXTIME;
344         priv->rxcoalescing = DEFAULT_RX_COALESCE;
345         priv->rxcount = DEFAULT_RXCOUNT;
346         priv->rxtime = DEFAULT_RXTIME;
347
348         /* Enable most messages by default */
349         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
350
351         err = register_netdev(dev);
352
353         if (err) {
354                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
355                                 dev->name);
356                 goto register_fail;
357         }
358
359         /* Create all the sysfs files */
360         gfar_init_sysfs(dev);
361
362         /* Print out the device info */
363         printk(KERN_INFO DEVICE_NAME, dev->name);
364         for (idx = 0; idx < 6; idx++)
365                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
366         printk("\n");
367
368         /* Even more device info helps when determining which kernel */
369         /* provided which set of benchmarks. */
370 #ifdef CONFIG_GFAR_NAPI
371         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
372 #else
373         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
374 #endif
375         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
376                dev->name, priv->rx_ring_size, priv->tx_ring_size);
377
378         return 0;
379
380 register_fail:
381         iounmap(priv->regs);
382 regs_fail:
383         free_netdev(dev);
384         return err;
385 }
386
387 static int gfar_remove(struct platform_device *pdev)
388 {
389         struct net_device *dev = platform_get_drvdata(pdev);
390         struct gfar_private *priv = netdev_priv(dev);
391
392         platform_set_drvdata(pdev, NULL);
393
394         iounmap(priv->regs);
395         free_netdev(dev);
396
397         return 0;
398 }
399
400
401 /* Reads the controller's registers to determine what interface
402  * connects it to the PHY.
403  */
404 static phy_interface_t gfar_get_interface(struct net_device *dev)
405 {
406         struct gfar_private *priv = netdev_priv(dev);
407         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
408
409         if (ecntrl & ECNTRL_SGMII_MODE)
410                 return PHY_INTERFACE_MODE_SGMII;
411
412         if (ecntrl & ECNTRL_TBI_MODE) {
413                 if (ecntrl & ECNTRL_REDUCED_MODE)
414                         return PHY_INTERFACE_MODE_RTBI;
415                 else
416                         return PHY_INTERFACE_MODE_TBI;
417         }
418
419         if (ecntrl & ECNTRL_REDUCED_MODE) {
420                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
421                         return PHY_INTERFACE_MODE_RMII;
422                 else
423                         return PHY_INTERFACE_MODE_RGMII;
424         }
425
426         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
427                 return PHY_INTERFACE_MODE_GMII;
428
429         return PHY_INTERFACE_MODE_MII;
430 }
431
432
433 /* Initializes driver's PHY state, and attaches to the PHY.
434  * Returns 0 on success.
435  */
436 static int init_phy(struct net_device *dev)
437 {
438         struct gfar_private *priv = netdev_priv(dev);
439         uint gigabit_support =
440                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
441                 SUPPORTED_1000baseT_Full : 0;
442         struct phy_device *phydev;
443         char phy_id[BUS_ID_SIZE];
444         phy_interface_t interface;
445
446         priv->oldlink = 0;
447         priv->oldspeed = 0;
448         priv->oldduplex = -1;
449
450         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
451
452         interface = gfar_get_interface(dev);
453
454         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
455
456         if (IS_ERR(phydev)) {
457                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
458                 return PTR_ERR(phydev);
459         }
460
461         /* Remove any features not supported by the controller */
462         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
463         phydev->advertising = phydev->supported;
464
465         priv->phydev = phydev;
466
467         return 0;
468 }
469
470 static void init_registers(struct net_device *dev)
471 {
472         struct gfar_private *priv = netdev_priv(dev);
473
474         /* Clear IEVENT */
475         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
476
477         /* Initialize IMASK */
478         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
479
480         /* Init hash registers to zero */
481         gfar_write(&priv->regs->igaddr0, 0);
482         gfar_write(&priv->regs->igaddr1, 0);
483         gfar_write(&priv->regs->igaddr2, 0);
484         gfar_write(&priv->regs->igaddr3, 0);
485         gfar_write(&priv->regs->igaddr4, 0);
486         gfar_write(&priv->regs->igaddr5, 0);
487         gfar_write(&priv->regs->igaddr6, 0);
488         gfar_write(&priv->regs->igaddr7, 0);
489
490         gfar_write(&priv->regs->gaddr0, 0);
491         gfar_write(&priv->regs->gaddr1, 0);
492         gfar_write(&priv->regs->gaddr2, 0);
493         gfar_write(&priv->regs->gaddr3, 0);
494         gfar_write(&priv->regs->gaddr4, 0);
495         gfar_write(&priv->regs->gaddr5, 0);
496         gfar_write(&priv->regs->gaddr6, 0);
497         gfar_write(&priv->regs->gaddr7, 0);
498
499         /* Zero out the rmon mib registers if it has them */
500         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
501                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
502
503                 /* Mask off the CAM interrupts */
504                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
505                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
506         }
507
508         /* Initialize the max receive buffer length */
509         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
510
511         /* Initialize the Minimum Frame Length Register */
512         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
513
514         /* Assign the TBI an address which won't conflict with the PHYs */
515         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
516 }
517
518
519 /* Halt the receive and transmit queues */
520 void gfar_halt(struct net_device *dev)
521 {
522         struct gfar_private *priv = netdev_priv(dev);
523         struct gfar __iomem *regs = priv->regs;
524         u32 tempval;
525
526         /* Mask all interrupts */
527         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
528
529         /* Clear all interrupts */
530         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
531
532         /* Stop the DMA, and wait for it to stop */
533         tempval = gfar_read(&priv->regs->dmactrl);
534         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
535             != (DMACTRL_GRS | DMACTRL_GTS)) {
536                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
537                 gfar_write(&priv->regs->dmactrl, tempval);
538
539                 while (!(gfar_read(&priv->regs->ievent) &
540                          (IEVENT_GRSC | IEVENT_GTSC)))
541                         cpu_relax();
542         }
543
544         /* Disable Rx and Tx */
545         tempval = gfar_read(&regs->maccfg1);
546         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
547         gfar_write(&regs->maccfg1, tempval);
548 }
549
550 void stop_gfar(struct net_device *dev)
551 {
552         struct gfar_private *priv = netdev_priv(dev);
553         struct gfar __iomem *regs = priv->regs;
554         unsigned long flags;
555
556         phy_stop(priv->phydev);
557
558         /* Lock it down */
559         spin_lock_irqsave(&priv->txlock, flags);
560         spin_lock(&priv->rxlock);
561
562         gfar_halt(dev);
563
564         spin_unlock(&priv->rxlock);
565         spin_unlock_irqrestore(&priv->txlock, flags);
566
567         /* Free the IRQs */
568         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
569                 free_irq(priv->interruptError, dev);
570                 free_irq(priv->interruptTransmit, dev);
571                 free_irq(priv->interruptReceive, dev);
572         } else {
573                 free_irq(priv->interruptTransmit, dev);
574         }
575
576         free_skb_resources(priv);
577
578         dma_free_coherent(NULL,
579                         sizeof(struct txbd8)*priv->tx_ring_size
580                         + sizeof(struct rxbd8)*priv->rx_ring_size,
581                         priv->tx_bd_base,
582                         gfar_read(&regs->tbase0));
583 }
584
585 /* If there are any tx skbs or rx skbs still around, free them.
586  * Then free tx_skbuff and rx_skbuff */
587 static void free_skb_resources(struct gfar_private *priv)
588 {
589         struct rxbd8 *rxbdp;
590         struct txbd8 *txbdp;
591         int i;
592
593         /* Go through all the buffer descriptors and free their data buffers */
594         txbdp = priv->tx_bd_base;
595
596         for (i = 0; i < priv->tx_ring_size; i++) {
597
598                 if (priv->tx_skbuff[i]) {
599                         dma_unmap_single(NULL, txbdp->bufPtr,
600                                         txbdp->length,
601                                         DMA_TO_DEVICE);
602                         dev_kfree_skb_any(priv->tx_skbuff[i]);
603                         priv->tx_skbuff[i] = NULL;
604                 }
605         }
606
607         kfree(priv->tx_skbuff);
608
609         rxbdp = priv->rx_bd_base;
610
611         /* rx_skbuff is not guaranteed to be allocated, so only
612          * free it and its contents if it is allocated */
613         if(priv->rx_skbuff != NULL) {
614                 for (i = 0; i < priv->rx_ring_size; i++) {
615                         if (priv->rx_skbuff[i]) {
616                                 dma_unmap_single(NULL, rxbdp->bufPtr,
617                                                 priv->rx_buffer_size,
618                                                 DMA_FROM_DEVICE);
619
620                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
621                                 priv->rx_skbuff[i] = NULL;
622                         }
623
624                         rxbdp->status = 0;
625                         rxbdp->length = 0;
626                         rxbdp->bufPtr = 0;
627
628                         rxbdp++;
629                 }
630
631                 kfree(priv->rx_skbuff);
632         }
633 }
634
635 void gfar_start(struct net_device *dev)
636 {
637         struct gfar_private *priv = netdev_priv(dev);
638         struct gfar __iomem *regs = priv->regs;
639         u32 tempval;
640
641         /* Enable Rx and Tx in MACCFG1 */
642         tempval = gfar_read(&regs->maccfg1);
643         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
644         gfar_write(&regs->maccfg1, tempval);
645
646         /* Initialize DMACTRL to have WWR and WOP */
647         tempval = gfar_read(&priv->regs->dmactrl);
648         tempval |= DMACTRL_INIT_SETTINGS;
649         gfar_write(&priv->regs->dmactrl, tempval);
650
651         /* Make sure we aren't stopped */
652         tempval = gfar_read(&priv->regs->dmactrl);
653         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
654         gfar_write(&priv->regs->dmactrl, tempval);
655
656         /* Clear THLT/RHLT, so that the DMA starts polling now */
657         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
658         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
659
660         /* Unmask the interrupts we look for */
661         gfar_write(&regs->imask, IMASK_DEFAULT);
662 }
663
664 /* Bring the controller up and running */
665 int startup_gfar(struct net_device *dev)
666 {
667         struct txbd8 *txbdp;
668         struct rxbd8 *rxbdp;
669         dma_addr_t addr;
670         unsigned long vaddr;
671         int i;
672         struct gfar_private *priv = netdev_priv(dev);
673         struct gfar __iomem *regs = priv->regs;
674         int err = 0;
675         u32 rctrl = 0;
676         u32 attrs = 0;
677
678         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
679
680         /* Allocate memory for the buffer descriptors */
681         vaddr = (unsigned long) dma_alloc_coherent(NULL,
682                         sizeof (struct txbd8) * priv->tx_ring_size +
683                         sizeof (struct rxbd8) * priv->rx_ring_size,
684                         &addr, GFP_KERNEL);
685
686         if (vaddr == 0) {
687                 if (netif_msg_ifup(priv))
688                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
689                                         dev->name);
690                 return -ENOMEM;
691         }
692
693         priv->tx_bd_base = (struct txbd8 *) vaddr;
694
695         /* enet DMA only understands physical addresses */
696         gfar_write(&regs->tbase0, addr);
697
698         /* Start the rx descriptor ring where the tx ring leaves off */
699         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
700         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
701         priv->rx_bd_base = (struct rxbd8 *) vaddr;
702         gfar_write(&regs->rbase0, addr);
703
704         /* Setup the skbuff rings */
705         priv->tx_skbuff =
706             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
707                                         priv->tx_ring_size, GFP_KERNEL);
708
709         if (NULL == priv->tx_skbuff) {
710                 if (netif_msg_ifup(priv))
711                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
712                                         dev->name);
713                 err = -ENOMEM;
714                 goto tx_skb_fail;
715         }
716
717         for (i = 0; i < priv->tx_ring_size; i++)
718                 priv->tx_skbuff[i] = NULL;
719
720         priv->rx_skbuff =
721             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
722                                         priv->rx_ring_size, GFP_KERNEL);
723
724         if (NULL == priv->rx_skbuff) {
725                 if (netif_msg_ifup(priv))
726                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
727                                         dev->name);
728                 err = -ENOMEM;
729                 goto rx_skb_fail;
730         }
731
732         for (i = 0; i < priv->rx_ring_size; i++)
733                 priv->rx_skbuff[i] = NULL;
734
735         /* Initialize some variables in our dev structure */
736         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
737         priv->cur_rx = priv->rx_bd_base;
738         priv->skb_curtx = priv->skb_dirtytx = 0;
739         priv->skb_currx = 0;
740
741         /* Initialize Transmit Descriptor Ring */
742         txbdp = priv->tx_bd_base;
743         for (i = 0; i < priv->tx_ring_size; i++) {
744                 txbdp->status = 0;
745                 txbdp->length = 0;
746                 txbdp->bufPtr = 0;
747                 txbdp++;
748         }
749
750         /* Set the last descriptor in the ring to indicate wrap */
751         txbdp--;
752         txbdp->status |= TXBD_WRAP;
753
754         rxbdp = priv->rx_bd_base;
755         for (i = 0; i < priv->rx_ring_size; i++) {
756                 struct sk_buff *skb = NULL;
757
758                 rxbdp->status = 0;
759
760                 skb = gfar_new_skb(dev, rxbdp);
761
762                 priv->rx_skbuff[i] = skb;
763
764                 rxbdp++;
765         }
766
767         /* Set the last descriptor in the ring to wrap */
768         rxbdp--;
769         rxbdp->status |= RXBD_WRAP;
770
771         /* If the device has multiple interrupts, register for
772          * them.  Otherwise, only register for the one */
773         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
774                 /* Install our interrupt handlers for Error,
775                  * Transmit, and Receive */
776                 if (request_irq(priv->interruptError, gfar_error,
777                                 0, "enet_error", dev) < 0) {
778                         if (netif_msg_intr(priv))
779                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
780                                         dev->name, priv->interruptError);
781
782                         err = -1;
783                         goto err_irq_fail;
784                 }
785
786                 if (request_irq(priv->interruptTransmit, gfar_transmit,
787                                 0, "enet_tx", dev) < 0) {
788                         if (netif_msg_intr(priv))
789                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
790                                         dev->name, priv->interruptTransmit);
791
792                         err = -1;
793
794                         goto tx_irq_fail;
795                 }
796
797                 if (request_irq(priv->interruptReceive, gfar_receive,
798                                 0, "enet_rx", dev) < 0) {
799                         if (netif_msg_intr(priv))
800                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
801                                                 dev->name, priv->interruptReceive);
802
803                         err = -1;
804                         goto rx_irq_fail;
805                 }
806         } else {
807                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
808                                 0, "gfar_interrupt", dev) < 0) {
809                         if (netif_msg_intr(priv))
810                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
811                                         dev->name, priv->interruptError);
812
813                         err = -1;
814                         goto err_irq_fail;
815                 }
816         }
817
818         phy_start(priv->phydev);
819
820         /* Configure the coalescing support */
821         if (priv->txcoalescing)
822                 gfar_write(&regs->txic,
823                            mk_ic_value(priv->txcount, priv->txtime));
824         else
825                 gfar_write(&regs->txic, 0);
826
827         if (priv->rxcoalescing)
828                 gfar_write(&regs->rxic,
829                            mk_ic_value(priv->rxcount, priv->rxtime));
830         else
831                 gfar_write(&regs->rxic, 0);
832
833         if (priv->rx_csum_enable)
834                 rctrl |= RCTRL_CHECKSUMMING;
835
836         if (priv->extended_hash) {
837                 rctrl |= RCTRL_EXTHASH;
838
839                 gfar_clear_exact_match(dev);
840                 rctrl |= RCTRL_EMEN;
841         }
842
843         if (priv->vlan_enable)
844                 rctrl |= RCTRL_VLAN;
845
846         if (priv->padding) {
847                 rctrl &= ~RCTRL_PAL_MASK;
848                 rctrl |= RCTRL_PADDING(priv->padding);
849         }
850
851         /* Init rctrl based on our settings */
852         gfar_write(&priv->regs->rctrl, rctrl);
853
854         if (dev->features & NETIF_F_IP_CSUM)
855                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
856
857         /* Set the extraction length and index */
858         attrs = ATTRELI_EL(priv->rx_stash_size) |
859                 ATTRELI_EI(priv->rx_stash_index);
860
861         gfar_write(&priv->regs->attreli, attrs);
862
863         /* Start with defaults, and add stashing or locking
864          * depending on the approprate variables */
865         attrs = ATTR_INIT_SETTINGS;
866
867         if (priv->bd_stash_en)
868                 attrs |= ATTR_BDSTASH;
869
870         if (priv->rx_stash_size != 0)
871                 attrs |= ATTR_BUFSTASH;
872
873         gfar_write(&priv->regs->attr, attrs);
874
875         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
876         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
877         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
878
879         /* Start the controller */
880         gfar_start(dev);
881
882         return 0;
883
884 rx_irq_fail:
885         free_irq(priv->interruptTransmit, dev);
886 tx_irq_fail:
887         free_irq(priv->interruptError, dev);
888 err_irq_fail:
889 rx_skb_fail:
890         free_skb_resources(priv);
891 tx_skb_fail:
892         dma_free_coherent(NULL,
893                         sizeof(struct txbd8)*priv->tx_ring_size
894                         + sizeof(struct rxbd8)*priv->rx_ring_size,
895                         priv->tx_bd_base,
896                         gfar_read(&regs->tbase0));
897
898         return err;
899 }
900
901 /* Called when something needs to use the ethernet device */
902 /* Returns 0 for success. */
903 static int gfar_enet_open(struct net_device *dev)
904 {
905         int err;
906
907         /* Initialize a bunch of registers */
908         init_registers(dev);
909
910         gfar_set_mac_address(dev);
911
912         err = init_phy(dev);
913
914         if(err)
915                 return err;
916
917         err = startup_gfar(dev);
918
919         netif_start_queue(dev);
920
921         return err;
922 }
923
924 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
925 {
926         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
927
928         memset(fcb, 0, GMAC_FCB_LEN);
929
930         return fcb;
931 }
932
933 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
934 {
935         u8 flags = 0;
936
937         /* If we're here, it's a IP packet with a TCP or UDP
938          * payload.  We set it to checksum, using a pseudo-header
939          * we provide
940          */
941         flags = TXFCB_DEFAULT;
942
943         /* Tell the controller what the protocol is */
944         /* And provide the already calculated phcs */
945         if (skb->nh.iph->protocol == IPPROTO_UDP) {
946                 flags |= TXFCB_UDP;
947                 fcb->phcs = skb->h.uh->check;
948         } else
949                 fcb->phcs = skb->h.th->check;
950
951         /* l3os is the distance between the start of the
952          * frame (skb->data) and the start of the IP hdr.
953          * l4os is the distance between the start of the
954          * l3 hdr and the l4 hdr */
955         fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
956         fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
957
958         fcb->flags = flags;
959 }
960
961 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
962 {
963         fcb->flags |= TXFCB_VLN;
964         fcb->vlctl = vlan_tx_tag_get(skb);
965 }
966
967 /* This is called by the kernel when a frame is ready for transmission. */
968 /* It is pointed to by the dev->hard_start_xmit function pointer */
969 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
970 {
971         struct gfar_private *priv = netdev_priv(dev);
972         struct txfcb *fcb = NULL;
973         struct txbd8 *txbdp;
974         u16 status;
975         unsigned long flags;
976
977         /* Update transmit stats */
978         priv->stats.tx_bytes += skb->len;
979
980         /* Lock priv now */
981         spin_lock_irqsave(&priv->txlock, flags);
982
983         /* Point at the first free tx descriptor */
984         txbdp = priv->cur_tx;
985
986         /* Clear all but the WRAP status flags */
987         status = txbdp->status & TXBD_WRAP;
988
989         /* Set up checksumming */
990         if (likely((dev->features & NETIF_F_IP_CSUM)
991                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
992                 fcb = gfar_add_fcb(skb, txbdp);
993                 status |= TXBD_TOE;
994                 gfar_tx_checksum(skb, fcb);
995         }
996
997         if (priv->vlan_enable &&
998                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
999                 if (unlikely(NULL == fcb)) {
1000                         fcb = gfar_add_fcb(skb, txbdp);
1001                         status |= TXBD_TOE;
1002                 }
1003
1004                 gfar_tx_vlan(skb, fcb);
1005         }
1006
1007         /* Set buffer length and pointer */
1008         txbdp->length = skb->len;
1009         txbdp->bufPtr = dma_map_single(NULL, skb->data,
1010                         skb->len, DMA_TO_DEVICE);
1011
1012         /* Save the skb pointer so we can free it later */
1013         priv->tx_skbuff[priv->skb_curtx] = skb;
1014
1015         /* Update the current skb pointer (wrapping if this was the last) */
1016         priv->skb_curtx =
1017             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1018
1019         /* Flag the BD as interrupt-causing */
1020         status |= TXBD_INTERRUPT;
1021
1022         /* Flag the BD as ready to go, last in frame, and  */
1023         /* in need of CRC */
1024         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1025
1026         dev->trans_start = jiffies;
1027
1028         txbdp->status = status;
1029
1030         /* If this was the last BD in the ring, the next one */
1031         /* is at the beginning of the ring */
1032         if (txbdp->status & TXBD_WRAP)
1033                 txbdp = priv->tx_bd_base;
1034         else
1035                 txbdp++;
1036
1037         /* If the next BD still needs to be cleaned up, then the bds
1038            are full.  We need to tell the kernel to stop sending us stuff. */
1039         if (txbdp == priv->dirty_tx) {
1040                 netif_stop_queue(dev);
1041
1042                 priv->stats.tx_fifo_errors++;
1043         }
1044
1045         /* Update the current txbd to the next one */
1046         priv->cur_tx = txbdp;
1047
1048         /* Tell the DMA to go go go */
1049         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1050
1051         /* Unlock priv */
1052         spin_unlock_irqrestore(&priv->txlock, flags);
1053
1054         return 0;
1055 }
1056
1057 /* Stops the kernel queue, and halts the controller */
1058 static int gfar_close(struct net_device *dev)
1059 {
1060         struct gfar_private *priv = netdev_priv(dev);
1061         stop_gfar(dev);
1062
1063         /* Disconnect from the PHY */
1064         phy_disconnect(priv->phydev);
1065         priv->phydev = NULL;
1066
1067         netif_stop_queue(dev);
1068
1069         return 0;
1070 }
1071
1072 /* returns a net_device_stats structure pointer */
1073 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1074 {
1075         struct gfar_private *priv = netdev_priv(dev);
1076
1077         return &(priv->stats);
1078 }
1079
1080 /* Changes the mac address if the controller is not running. */
1081 int gfar_set_mac_address(struct net_device *dev)
1082 {
1083         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1084
1085         return 0;
1086 }
1087
1088
1089 /* Enables and disables VLAN insertion/extraction */
1090 static void gfar_vlan_rx_register(struct net_device *dev,
1091                 struct vlan_group *grp)
1092 {
1093         struct gfar_private *priv = netdev_priv(dev);
1094         unsigned long flags;
1095         u32 tempval;
1096
1097         spin_lock_irqsave(&priv->rxlock, flags);
1098
1099         priv->vlgrp = grp;
1100
1101         if (grp) {
1102                 /* Enable VLAN tag insertion */
1103                 tempval = gfar_read(&priv->regs->tctrl);
1104                 tempval |= TCTRL_VLINS;
1105
1106                 gfar_write(&priv->regs->tctrl, tempval);
1107
1108                 /* Enable VLAN tag extraction */
1109                 tempval = gfar_read(&priv->regs->rctrl);
1110                 tempval |= RCTRL_VLEX;
1111                 gfar_write(&priv->regs->rctrl, tempval);
1112         } else {
1113                 /* Disable VLAN tag insertion */
1114                 tempval = gfar_read(&priv->regs->tctrl);
1115                 tempval &= ~TCTRL_VLINS;
1116                 gfar_write(&priv->regs->tctrl, tempval);
1117
1118                 /* Disable VLAN tag extraction */
1119                 tempval = gfar_read(&priv->regs->rctrl);
1120                 tempval &= ~RCTRL_VLEX;
1121                 gfar_write(&priv->regs->rctrl, tempval);
1122         }
1123
1124         spin_unlock_irqrestore(&priv->rxlock, flags);
1125 }
1126
1127
1128 static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1129 {
1130         struct gfar_private *priv = netdev_priv(dev);
1131         unsigned long flags;
1132
1133         spin_lock_irqsave(&priv->rxlock, flags);
1134
1135         if (priv->vlgrp)
1136                 priv->vlgrp->vlan_devices[vid] = NULL;
1137
1138         spin_unlock_irqrestore(&priv->rxlock, flags);
1139 }
1140
1141
1142 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1143 {
1144         int tempsize, tempval;
1145         struct gfar_private *priv = netdev_priv(dev);
1146         int oldsize = priv->rx_buffer_size;
1147         int frame_size = new_mtu + ETH_HLEN;
1148
1149         if (priv->vlan_enable)
1150                 frame_size += VLAN_ETH_HLEN;
1151
1152         if (gfar_uses_fcb(priv))
1153                 frame_size += GMAC_FCB_LEN;
1154
1155         frame_size += priv->padding;
1156
1157         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1158                 if (netif_msg_drv(priv))
1159                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1160                                         dev->name);
1161                 return -EINVAL;
1162         }
1163
1164         tempsize =
1165             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1166             INCREMENTAL_BUFFER_SIZE;
1167
1168         /* Only stop and start the controller if it isn't already
1169          * stopped, and we changed something */
1170         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1171                 stop_gfar(dev);
1172
1173         priv->rx_buffer_size = tempsize;
1174
1175         dev->mtu = new_mtu;
1176
1177         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1178         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1179
1180         /* If the mtu is larger than the max size for standard
1181          * ethernet frames (ie, a jumbo frame), then set maccfg2
1182          * to allow huge frames, and to check the length */
1183         tempval = gfar_read(&priv->regs->maccfg2);
1184
1185         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1186                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1187         else
1188                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1189
1190         gfar_write(&priv->regs->maccfg2, tempval);
1191
1192         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1193                 startup_gfar(dev);
1194
1195         return 0;
1196 }
1197
1198 /* gfar_timeout gets called when a packet has not been
1199  * transmitted after a set amount of time.
1200  * For now, assume that clearing out all the structures, and
1201  * starting over will fix the problem. */
1202 static void gfar_timeout(struct net_device *dev)
1203 {
1204         struct gfar_private *priv = netdev_priv(dev);
1205
1206         priv->stats.tx_errors++;
1207
1208         if (dev->flags & IFF_UP) {
1209                 stop_gfar(dev);
1210                 startup_gfar(dev);
1211         }
1212
1213         netif_schedule(dev);
1214 }
1215
1216 /* Interrupt Handler for Transmit complete */
1217 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1218 {
1219         struct net_device *dev = (struct net_device *) dev_id;
1220         struct gfar_private *priv = netdev_priv(dev);
1221         struct txbd8 *bdp;
1222
1223         /* Clear IEVENT */
1224         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1225
1226         /* Lock priv */
1227         spin_lock(&priv->txlock);
1228         bdp = priv->dirty_tx;
1229         while ((bdp->status & TXBD_READY) == 0) {
1230                 /* If dirty_tx and cur_tx are the same, then either the */
1231                 /* ring is empty or full now (it could only be full in the beginning, */
1232                 /* obviously).  If it is empty, we are done. */
1233                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1234                         break;
1235
1236                 priv->stats.tx_packets++;
1237
1238                 /* Deferred means some collisions occurred during transmit, */
1239                 /* but we eventually sent the packet. */
1240                 if (bdp->status & TXBD_DEF)
1241                         priv->stats.collisions++;
1242
1243                 /* Free the sk buffer associated with this TxBD */
1244                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1245                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1246                 priv->skb_dirtytx =
1247                     (priv->skb_dirtytx +
1248                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1249
1250                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1251                 if (bdp->status & TXBD_WRAP)
1252                         bdp = priv->tx_bd_base;
1253                 else
1254                         bdp++;
1255
1256                 /* Move dirty_tx to be the next bd */
1257                 priv->dirty_tx = bdp;
1258
1259                 /* We freed a buffer, so now we can restart transmission */
1260                 if (netif_queue_stopped(dev))
1261                         netif_wake_queue(dev);
1262         } /* while ((bdp->status & TXBD_READY) == 0) */
1263
1264         /* If we are coalescing the interrupts, reset the timer */
1265         /* Otherwise, clear it */
1266         if (priv->txcoalescing)
1267                 gfar_write(&priv->regs->txic,
1268                            mk_ic_value(priv->txcount, priv->txtime));
1269         else
1270                 gfar_write(&priv->regs->txic, 0);
1271
1272         spin_unlock(&priv->txlock);
1273
1274         return IRQ_HANDLED;
1275 }
1276
1277 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1278 {
1279         unsigned int alignamount;
1280         struct gfar_private *priv = netdev_priv(dev);
1281         struct sk_buff *skb = NULL;
1282         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1283
1284         /* We have to allocate the skb, so keep trying till we succeed */
1285         while ((!skb) && timeout--)
1286                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1287
1288         if (NULL == skb)
1289                 return NULL;
1290
1291         alignamount = RXBUF_ALIGNMENT -
1292                 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1293
1294         /* We need the data buffer to be aligned properly.  We will reserve
1295          * as many bytes as needed to align the data properly
1296          */
1297         skb_reserve(skb, alignamount);
1298
1299         skb->dev = dev;
1300
1301         bdp->bufPtr = dma_map_single(NULL, skb->data,
1302                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1303
1304         bdp->length = 0;
1305
1306         /* Mark the buffer empty */
1307         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1308
1309         return skb;
1310 }
1311
1312 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1313 {
1314         struct net_device_stats *stats = &priv->stats;
1315         struct gfar_extra_stats *estats = &priv->extra_stats;
1316
1317         /* If the packet was truncated, none of the other errors
1318          * matter */
1319         if (status & RXBD_TRUNCATED) {
1320                 stats->rx_length_errors++;
1321
1322                 estats->rx_trunc++;
1323
1324                 return;
1325         }
1326         /* Count the errors, if there were any */
1327         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1328                 stats->rx_length_errors++;
1329
1330                 if (status & RXBD_LARGE)
1331                         estats->rx_large++;
1332                 else
1333                         estats->rx_short++;
1334         }
1335         if (status & RXBD_NONOCTET) {
1336                 stats->rx_frame_errors++;
1337                 estats->rx_nonoctet++;
1338         }
1339         if (status & RXBD_CRCERR) {
1340                 estats->rx_crcerr++;
1341                 stats->rx_crc_errors++;
1342         }
1343         if (status & RXBD_OVERRUN) {
1344                 estats->rx_overrun++;
1345                 stats->rx_crc_errors++;
1346         }
1347 }
1348
1349 irqreturn_t gfar_receive(int irq, void *dev_id)
1350 {
1351         struct net_device *dev = (struct net_device *) dev_id;
1352         struct gfar_private *priv = netdev_priv(dev);
1353 #ifdef CONFIG_GFAR_NAPI
1354         u32 tempval;
1355 #else
1356         unsigned long flags;
1357 #endif
1358
1359         /* Clear IEVENT, so rx interrupt isn't called again
1360          * because of this interrupt */
1361         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1362
1363         /* support NAPI */
1364 #ifdef CONFIG_GFAR_NAPI
1365         if (netif_rx_schedule_prep(dev)) {
1366                 tempval = gfar_read(&priv->regs->imask);
1367                 tempval &= IMASK_RX_DISABLED;
1368                 gfar_write(&priv->regs->imask, tempval);
1369
1370                 __netif_rx_schedule(dev);
1371         } else {
1372                 if (netif_msg_rx_err(priv))
1373                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1374                                 dev->name, gfar_read(&priv->regs->ievent),
1375                                 gfar_read(&priv->regs->imask));
1376         }
1377 #else
1378
1379         spin_lock_irqsave(&priv->rxlock, flags);
1380         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1381
1382         /* If we are coalescing interrupts, update the timer */
1383         /* Otherwise, clear it */
1384         if (priv->rxcoalescing)
1385                 gfar_write(&priv->regs->rxic,
1386                            mk_ic_value(priv->rxcount, priv->rxtime));
1387         else
1388                 gfar_write(&priv->regs->rxic, 0);
1389
1390         spin_unlock_irqrestore(&priv->rxlock, flags);
1391 #endif
1392
1393         return IRQ_HANDLED;
1394 }
1395
1396 static inline int gfar_rx_vlan(struct sk_buff *skb,
1397                 struct vlan_group *vlgrp, unsigned short vlctl)
1398 {
1399 #ifdef CONFIG_GFAR_NAPI
1400         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1401 #else
1402         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1403 #endif
1404 }
1405
1406 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1407 {
1408         /* If valid headers were found, and valid sums
1409          * were verified, then we tell the kernel that no
1410          * checksumming is necessary.  Otherwise, it is */
1411         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1412                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1413         else
1414                 skb->ip_summed = CHECKSUM_NONE;
1415 }
1416
1417
1418 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1419 {
1420         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1421
1422         /* Remove the FCB from the skb */
1423         skb_pull(skb, GMAC_FCB_LEN);
1424
1425         return fcb;
1426 }
1427
1428 /* gfar_process_frame() -- handle one incoming packet if skb
1429  * isn't NULL.  */
1430 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1431                 int length)
1432 {
1433         struct gfar_private *priv = netdev_priv(dev);
1434         struct rxfcb *fcb = NULL;
1435
1436         if (NULL == skb) {
1437                 if (netif_msg_rx_err(priv))
1438                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1439                 priv->stats.rx_dropped++;
1440                 priv->extra_stats.rx_skbmissing++;
1441         } else {
1442                 int ret;
1443
1444                 /* Prep the skb for the packet */
1445                 skb_put(skb, length);
1446
1447                 /* Grab the FCB if there is one */
1448                 if (gfar_uses_fcb(priv))
1449                         fcb = gfar_get_fcb(skb);
1450
1451                 /* Remove the padded bytes, if there are any */
1452                 if (priv->padding)
1453                         skb_pull(skb, priv->padding);
1454
1455                 if (priv->rx_csum_enable)
1456                         gfar_rx_checksum(skb, fcb);
1457
1458                 /* Tell the skb what kind of packet this is */
1459                 skb->protocol = eth_type_trans(skb, dev);
1460
1461                 /* Send the packet up the stack */
1462                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1463                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1464                 else
1465                         ret = RECEIVE(skb);
1466
1467                 if (NET_RX_DROP == ret)
1468                         priv->extra_stats.kernel_dropped++;
1469         }
1470
1471         return 0;
1472 }
1473
1474 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1475  *   until the budget/quota has been reached. Returns the number
1476  *   of frames handled
1477  */
1478 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1479 {
1480         struct rxbd8 *bdp;
1481         struct sk_buff *skb;
1482         u16 pkt_len;
1483         int howmany = 0;
1484         struct gfar_private *priv = netdev_priv(dev);
1485
1486         /* Get the first full descriptor */
1487         bdp = priv->cur_rx;
1488
1489         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1490                 skb = priv->rx_skbuff[priv->skb_currx];
1491
1492                 if (!(bdp->status &
1493                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1494                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1495                         /* Increment the number of packets */
1496                         priv->stats.rx_packets++;
1497                         howmany++;
1498
1499                         /* Remove the FCS from the packet length */
1500                         pkt_len = bdp->length - 4;
1501
1502                         gfar_process_frame(dev, skb, pkt_len);
1503
1504                         priv->stats.rx_bytes += pkt_len;
1505                 } else {
1506                         count_errors(bdp->status, priv);
1507
1508                         if (skb)
1509                                 dev_kfree_skb_any(skb);
1510
1511                         priv->rx_skbuff[priv->skb_currx] = NULL;
1512                 }
1513
1514                 dev->last_rx = jiffies;
1515
1516                 /* Clear the status flags for this buffer */
1517                 bdp->status &= ~RXBD_STATS;
1518
1519                 /* Add another skb for the future */
1520                 skb = gfar_new_skb(dev, bdp);
1521                 priv->rx_skbuff[priv->skb_currx] = skb;
1522
1523                 /* Update to the next pointer */
1524                 if (bdp->status & RXBD_WRAP)
1525                         bdp = priv->rx_bd_base;
1526                 else
1527                         bdp++;
1528
1529                 /* update to point at the next skb */
1530                 priv->skb_currx =
1531                     (priv->skb_currx +
1532                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1533
1534         }
1535
1536         /* Update the current rxbd pointer to be the next one */
1537         priv->cur_rx = bdp;
1538
1539         return howmany;
1540 }
1541
1542 #ifdef CONFIG_GFAR_NAPI
1543 static int gfar_poll(struct net_device *dev, int *budget)
1544 {
1545         int howmany;
1546         struct gfar_private *priv = netdev_priv(dev);
1547         int rx_work_limit = *budget;
1548
1549         if (rx_work_limit > dev->quota)
1550                 rx_work_limit = dev->quota;
1551
1552         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1553
1554         dev->quota -= howmany;
1555         rx_work_limit -= howmany;
1556         *budget -= howmany;
1557
1558         if (rx_work_limit > 0) {
1559                 netif_rx_complete(dev);
1560
1561                 /* Clear the halt bit in RSTAT */
1562                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1563
1564                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1565
1566                 /* If we are coalescing interrupts, update the timer */
1567                 /* Otherwise, clear it */
1568                 if (priv->rxcoalescing)
1569                         gfar_write(&priv->regs->rxic,
1570                                    mk_ic_value(priv->rxcount, priv->rxtime));
1571                 else
1572                         gfar_write(&priv->regs->rxic, 0);
1573         }
1574
1575         /* Return 1 if there's more work to do */
1576         return (rx_work_limit > 0) ? 0 : 1;
1577 }
1578 #endif
1579
1580 #ifdef CONFIG_NET_POLL_CONTROLLER
1581 /*
1582  * Polling 'interrupt' - used by things like netconsole to send skbs
1583  * without having to re-enable interrupts. It's not called while
1584  * the interrupt routine is executing.
1585  */
1586 static void gfar_netpoll(struct net_device *dev)
1587 {
1588         struct gfar_private *priv = netdev_priv(dev);
1589
1590         /* If the device has multiple interrupts, run tx/rx */
1591         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1592                 disable_irq(priv->interruptTransmit);
1593                 disable_irq(priv->interruptReceive);
1594                 disable_irq(priv->interruptError);
1595                 gfar_interrupt(priv->interruptTransmit, dev);
1596                 enable_irq(priv->interruptError);
1597                 enable_irq(priv->interruptReceive);
1598                 enable_irq(priv->interruptTransmit);
1599         } else {
1600                 disable_irq(priv->interruptTransmit);
1601                 gfar_interrupt(priv->interruptTransmit, dev);
1602                 enable_irq(priv->interruptTransmit);
1603         }
1604 }
1605 #endif
1606
1607 /* The interrupt handler for devices with one interrupt */
1608 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1609 {
1610         struct net_device *dev = dev_id;
1611         struct gfar_private *priv = netdev_priv(dev);
1612
1613         /* Save ievent for future reference */
1614         u32 events = gfar_read(&priv->regs->ievent);
1615
1616         /* Clear IEVENT */
1617         gfar_write(&priv->regs->ievent, events);
1618
1619         /* Check for reception */
1620         if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1621                 gfar_receive(irq, dev_id);
1622
1623         /* Check for transmit completion */
1624         if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1625                 gfar_transmit(irq, dev_id);
1626
1627         /* Update error statistics */
1628         if (events & IEVENT_TXE) {
1629                 priv->stats.tx_errors++;
1630
1631                 if (events & IEVENT_LC)
1632                         priv->stats.tx_window_errors++;
1633                 if (events & IEVENT_CRL)
1634                         priv->stats.tx_aborted_errors++;
1635                 if (events & IEVENT_XFUN) {
1636                         if (netif_msg_tx_err(priv))
1637                                 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1638                         priv->stats.tx_dropped++;
1639                         priv->extra_stats.tx_underrun++;
1640
1641                         /* Reactivate the Tx Queues */
1642                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1643                 }
1644         }
1645         if (events & IEVENT_BSY) {
1646                 priv->stats.rx_errors++;
1647                 priv->extra_stats.rx_bsy++;
1648
1649                 gfar_receive(irq, dev_id);
1650
1651 #ifndef CONFIG_GFAR_NAPI
1652                 /* Clear the halt bit in RSTAT */
1653                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1654 #endif
1655
1656                 if (netif_msg_rx_err(priv))
1657                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1658                                         dev->name,
1659                                         gfar_read(&priv->regs->rstat));
1660         }
1661         if (events & IEVENT_BABR) {
1662                 priv->stats.rx_errors++;
1663                 priv->extra_stats.rx_babr++;
1664
1665                 if (netif_msg_rx_err(priv))
1666                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1667         }
1668         if (events & IEVENT_EBERR) {
1669                 priv->extra_stats.eberr++;
1670                 if (netif_msg_rx_err(priv))
1671                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1672         }
1673         if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1674                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1675
1676         if (events & IEVENT_BABT) {
1677                 priv->extra_stats.tx_babt++;
1678                 if (netif_msg_rx_err(priv))
1679                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1680         }
1681
1682         return IRQ_HANDLED;
1683 }
1684
1685 /* Called every time the controller might need to be made
1686  * aware of new link state.  The PHY code conveys this
1687  * information through variables in the phydev structure, and this
1688  * function converts those variables into the appropriate
1689  * register values, and can bring down the device if needed.
1690  */
1691 static void adjust_link(struct net_device *dev)
1692 {
1693         struct gfar_private *priv = netdev_priv(dev);
1694         struct gfar __iomem *regs = priv->regs;
1695         unsigned long flags;
1696         struct phy_device *phydev = priv->phydev;
1697         int new_state = 0;
1698
1699         spin_lock_irqsave(&priv->txlock, flags);
1700         if (phydev->link) {
1701                 u32 tempval = gfar_read(&regs->maccfg2);
1702                 u32 ecntrl = gfar_read(&regs->ecntrl);
1703
1704                 /* Now we make sure that we can be in full duplex mode.
1705                  * If not, we operate in half-duplex mode. */
1706                 if (phydev->duplex != priv->oldduplex) {
1707                         new_state = 1;
1708                         if (!(phydev->duplex))
1709                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1710                         else
1711                                 tempval |= MACCFG2_FULL_DUPLEX;
1712
1713                         priv->oldduplex = phydev->duplex;
1714                 }
1715
1716                 if (phydev->speed != priv->oldspeed) {
1717                         new_state = 1;
1718                         switch (phydev->speed) {
1719                         case 1000:
1720                                 tempval =
1721                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1722                                 break;
1723                         case 100:
1724                         case 10:
1725                                 tempval =
1726                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1727
1728                                 /* Reduced mode distinguishes
1729                                  * between 10 and 100 */
1730                                 if (phydev->speed == SPEED_100)
1731                                         ecntrl |= ECNTRL_R100;
1732                                 else
1733                                         ecntrl &= ~(ECNTRL_R100);
1734                                 break;
1735                         default:
1736                                 if (netif_msg_link(priv))
1737                                         printk(KERN_WARNING
1738                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1739                                                 dev->name, phydev->speed);
1740                                 break;
1741                         }
1742
1743                         priv->oldspeed = phydev->speed;
1744                 }
1745
1746                 gfar_write(&regs->maccfg2, tempval);
1747                 gfar_write(&regs->ecntrl, ecntrl);
1748
1749                 if (!priv->oldlink) {
1750                         new_state = 1;
1751                         priv->oldlink = 1;
1752                         netif_schedule(dev);
1753                 }
1754         } else if (priv->oldlink) {
1755                 new_state = 1;
1756                 priv->oldlink = 0;
1757                 priv->oldspeed = 0;
1758                 priv->oldduplex = -1;
1759         }
1760
1761         if (new_state && netif_msg_link(priv))
1762                 phy_print_status(phydev);
1763
1764         spin_unlock_irqrestore(&priv->txlock, flags);
1765 }
1766
1767 /* Update the hash table based on the current list of multicast
1768  * addresses we subscribe to.  Also, change the promiscuity of
1769  * the device based on the flags (this function is called
1770  * whenever dev->flags is changed */
1771 static void gfar_set_multi(struct net_device *dev)
1772 {
1773         struct dev_mc_list *mc_ptr;
1774         struct gfar_private *priv = netdev_priv(dev);
1775         struct gfar __iomem *regs = priv->regs;
1776         u32 tempval;
1777
1778         if(dev->flags & IFF_PROMISC) {
1779                 /* Set RCTRL to PROM */
1780                 tempval = gfar_read(&regs->rctrl);
1781                 tempval |= RCTRL_PROM;
1782                 gfar_write(&regs->rctrl, tempval);
1783         } else {
1784                 /* Set RCTRL to not PROM */
1785                 tempval = gfar_read(&regs->rctrl);
1786                 tempval &= ~(RCTRL_PROM);
1787                 gfar_write(&regs->rctrl, tempval);
1788         }
1789
1790         if(dev->flags & IFF_ALLMULTI) {
1791                 /* Set the hash to rx all multicast frames */
1792                 gfar_write(&regs->igaddr0, 0xffffffff);
1793                 gfar_write(&regs->igaddr1, 0xffffffff);
1794                 gfar_write(&regs->igaddr2, 0xffffffff);
1795                 gfar_write(&regs->igaddr3, 0xffffffff);
1796                 gfar_write(&regs->igaddr4, 0xffffffff);
1797                 gfar_write(&regs->igaddr5, 0xffffffff);
1798                 gfar_write(&regs->igaddr6, 0xffffffff);
1799                 gfar_write(&regs->igaddr7, 0xffffffff);
1800                 gfar_write(&regs->gaddr0, 0xffffffff);
1801                 gfar_write(&regs->gaddr1, 0xffffffff);
1802                 gfar_write(&regs->gaddr2, 0xffffffff);
1803                 gfar_write(&regs->gaddr3, 0xffffffff);
1804                 gfar_write(&regs->gaddr4, 0xffffffff);
1805                 gfar_write(&regs->gaddr5, 0xffffffff);
1806                 gfar_write(&regs->gaddr6, 0xffffffff);
1807                 gfar_write(&regs->gaddr7, 0xffffffff);
1808         } else {
1809                 int em_num;
1810                 int idx;
1811
1812                 /* zero out the hash */
1813                 gfar_write(&regs->igaddr0, 0x0);
1814                 gfar_write(&regs->igaddr1, 0x0);
1815                 gfar_write(&regs->igaddr2, 0x0);
1816                 gfar_write(&regs->igaddr3, 0x0);
1817                 gfar_write(&regs->igaddr4, 0x0);
1818                 gfar_write(&regs->igaddr5, 0x0);
1819                 gfar_write(&regs->igaddr6, 0x0);
1820                 gfar_write(&regs->igaddr7, 0x0);
1821                 gfar_write(&regs->gaddr0, 0x0);
1822                 gfar_write(&regs->gaddr1, 0x0);
1823                 gfar_write(&regs->gaddr2, 0x0);
1824                 gfar_write(&regs->gaddr3, 0x0);
1825                 gfar_write(&regs->gaddr4, 0x0);
1826                 gfar_write(&regs->gaddr5, 0x0);
1827                 gfar_write(&regs->gaddr6, 0x0);
1828                 gfar_write(&regs->gaddr7, 0x0);
1829
1830                 /* If we have extended hash tables, we need to
1831                  * clear the exact match registers to prepare for
1832                  * setting them */
1833                 if (priv->extended_hash) {
1834                         em_num = GFAR_EM_NUM + 1;
1835                         gfar_clear_exact_match(dev);
1836                         idx = 1;
1837                 } else {
1838                         idx = 0;
1839                         em_num = 0;
1840                 }
1841
1842                 if(dev->mc_count == 0)
1843                         return;
1844
1845                 /* Parse the list, and set the appropriate bits */
1846                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1847                         if (idx < em_num) {
1848                                 gfar_set_mac_for_addr(dev, idx,
1849                                                 mc_ptr->dmi_addr);
1850                                 idx++;
1851                         } else
1852                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1853                 }
1854         }
1855
1856         return;
1857 }
1858
1859
1860 /* Clears each of the exact match registers to zero, so they
1861  * don't interfere with normal reception */
1862 static void gfar_clear_exact_match(struct net_device *dev)
1863 {
1864         int idx;
1865         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1866
1867         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1868                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1869 }
1870
1871 /* Set the appropriate hash bit for the given addr */
1872 /* The algorithm works like so:
1873  * 1) Take the Destination Address (ie the multicast address), and
1874  * do a CRC on it (little endian), and reverse the bits of the
1875  * result.
1876  * 2) Use the 8 most significant bits as a hash into a 256-entry
1877  * table.  The table is controlled through 8 32-bit registers:
1878  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1879  * gaddr7.  This means that the 3 most significant bits in the
1880  * hash index which gaddr register to use, and the 5 other bits
1881  * indicate which bit (assuming an IBM numbering scheme, which
1882  * for PowerPC (tm) is usually the case) in the register holds
1883  * the entry. */
1884 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1885 {
1886         u32 tempval;
1887         struct gfar_private *priv = netdev_priv(dev);
1888         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1889         int width = priv->hash_width;
1890         u8 whichbit = (result >> (32 - width)) & 0x1f;
1891         u8 whichreg = result >> (32 - width + 5);
1892         u32 value = (1 << (31-whichbit));
1893
1894         tempval = gfar_read(priv->hash_regs[whichreg]);
1895         tempval |= value;
1896         gfar_write(priv->hash_regs[whichreg], tempval);
1897
1898         return;
1899 }
1900
1901
1902 /* There are multiple MAC Address register pairs on some controllers
1903  * This function sets the numth pair to a given address
1904  */
1905 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1906 {
1907         struct gfar_private *priv = netdev_priv(dev);
1908         int idx;
1909         char tmpbuf[MAC_ADDR_LEN];
1910         u32 tempval;
1911         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1912
1913         macptr += num*2;
1914
1915         /* Now copy it into the mac registers backwards, cuz */
1916         /* little endian is silly */
1917         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1918                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1919
1920         gfar_write(macptr, *((u32 *) (tmpbuf)));
1921
1922         tempval = *((u32 *) (tmpbuf + 4));
1923
1924         gfar_write(macptr+1, tempval);
1925 }
1926
1927 /* GFAR error interrupt handler */
1928 static irqreturn_t gfar_error(int irq, void *dev_id)
1929 {
1930         struct net_device *dev = dev_id;
1931         struct gfar_private *priv = netdev_priv(dev);
1932
1933         /* Save ievent for future reference */
1934         u32 events = gfar_read(&priv->regs->ievent);
1935
1936         /* Clear IEVENT */
1937         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1938
1939         /* Hmm... */
1940         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1941                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1942                                 dev->name, events, gfar_read(&priv->regs->imask));
1943
1944         /* Update the error counters */
1945         if (events & IEVENT_TXE) {
1946                 priv->stats.tx_errors++;
1947
1948                 if (events & IEVENT_LC)
1949                         priv->stats.tx_window_errors++;
1950                 if (events & IEVENT_CRL)
1951                         priv->stats.tx_aborted_errors++;
1952                 if (events & IEVENT_XFUN) {
1953                         if (netif_msg_tx_err(priv))
1954                                 printk(KERN_DEBUG "%s: underrun.  packet dropped.\n",
1955                                                 dev->name);
1956                         priv->stats.tx_dropped++;
1957                         priv->extra_stats.tx_underrun++;
1958
1959                         /* Reactivate the Tx Queues */
1960                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1961                 }
1962                 if (netif_msg_tx_err(priv))
1963                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1964         }
1965         if (events & IEVENT_BSY) {
1966                 priv->stats.rx_errors++;
1967                 priv->extra_stats.rx_bsy++;
1968
1969                 gfar_receive(irq, dev_id);
1970
1971 #ifndef CONFIG_GFAR_NAPI
1972                 /* Clear the halt bit in RSTAT */
1973                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1974 #endif
1975
1976                 if (netif_msg_rx_err(priv))
1977                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1978                                         dev->name,
1979                                         gfar_read(&priv->regs->rstat));
1980         }
1981         if (events & IEVENT_BABR) {
1982                 priv->stats.rx_errors++;
1983                 priv->extra_stats.rx_babr++;
1984
1985                 if (netif_msg_rx_err(priv))
1986                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1987         }
1988         if (events & IEVENT_EBERR) {
1989                 priv->extra_stats.eberr++;
1990                 if (netif_msg_rx_err(priv))
1991                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1992         }
1993         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1994                 if (netif_msg_rx_status(priv))
1995                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1996
1997         if (events & IEVENT_BABT) {
1998                 priv->extra_stats.tx_babt++;
1999                 if (netif_msg_tx_err(priv))
2000                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
2001         }
2002         return IRQ_HANDLED;
2003 }
2004
2005 /* Structure for a device driver */
2006 static struct platform_driver gfar_driver = {
2007         .probe = gfar_probe,
2008         .remove = gfar_remove,
2009         .driver = {
2010                 .name = "fsl-gianfar",
2011         },
2012 };
2013
2014 static int __init gfar_init(void)
2015 {
2016         int err = gfar_mdio_init();
2017
2018         if (err)
2019                 return err;
2020
2021         err = platform_driver_register(&gfar_driver);
2022
2023         if (err)
2024                 gfar_mdio_exit();
2025
2026         return err;
2027 }
2028
2029 static void __exit gfar_exit(void)
2030 {
2031         platform_driver_unregister(&gfar_driver);
2032         gfar_mdio_exit();
2033 }
2034
2035 module_init(gfar_init);
2036 module_exit(gfar_exit);
2037