rndis_wlan: cleanup: rename and remove local pointers
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through platform_device.  Structures which
29  *  define the configuration needed by the board are defined in a
30  *  board structure in arch/ppc/platforms (though I do not
31  *  discount the possibility that other architectures could one
32  *  day be supported.
33  *
34  *  The Gianfar Ethernet Controller uses a ring of buffer
35  *  descriptors.  The beginning is indicated by a register
36  *  pointing to the physical address of the start of the ring.
37  *  The end is determined by a "wrap" bit being set in the
38  *  last descriptor of the ring.
39  *
40  *  When a packet is received, the RXF bit in the
41  *  IEVENT register is set, triggering an interrupt when the
42  *  corresponding bit in the IMASK register is also set (if
43  *  interrupt coalescing is active, then the interrupt may not
44  *  happen immediately, but will wait until either a set number
45  *  of frames or amount of time have passed).  In NAPI, the
46  *  interrupt handler will signal there is work to be done, and
47  *  exit.  Without NAPI, the packet(s) will be handled
48  *  immediately.  Both methods will start at the last known empty
49  *  descriptor, and process every subsequent descriptor until there
50  *  are none left with data (NAPI will stop after a set number of
51  *  packets to give time to other tasks, but will eventually
52  *  process all the packets).  The data arrives inside a
53  *  pre-allocated skb, and so after the skb is passed up to the
54  *  stack, a new skb must be allocated, and the address field in
55  *  the buffer descriptor must be updated to indicate this new
56  *  skb.
57  *
58  *  When the kernel requests that a packet be transmitted, the
59  *  driver starts where it left off last time, and points the
60  *  descriptor at the buffer which was passed in.  The driver
61  *  then informs the DMA engine that there are packets ready to
62  *  be transmitted.  Once the controller is finished transmitting
63  *  the packet, an interrupt may be triggered (under the same
64  *  conditions as for reception, but depending on the TXF bit).
65  *  The driver then cleans up the buffer.
66  */
67
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
81 #include <linux/mm.h>
82 #include <linux/platform_device.h>
83 #include <linux/ip.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
86 #include <linux/in.h>
87
88 #include <asm/io.h>
89 #include <asm/irq.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96
97 #include "gianfar.h"
98 #include "gianfar_mii.h"
99
100 #define TX_TIMEOUT      (1*HZ)
101 #undef BRIEF_GFAR_ERRORS
102 #undef VERBOSE_GFAR_ERRORS
103
104 #ifdef CONFIG_GFAR_NAPI
105 #define RECEIVE(x) netif_receive_skb(x)
106 #else
107 #define RECEIVE(x) netif_rx(x)
108 #endif
109
110 const char gfar_driver_name[] = "Gianfar Ethernet";
111 const char gfar_driver_version[] = "1.3";
112
113 static int gfar_enet_open(struct net_device *dev);
114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
115 static void gfar_timeout(struct net_device *dev);
116 static int gfar_close(struct net_device *dev);
117 struct sk_buff *gfar_new_skb(struct net_device *dev);
118 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
119                 struct sk_buff *skb);
120 static int gfar_set_mac_address(struct net_device *dev);
121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
122 static irqreturn_t gfar_error(int irq, void *dev_id);
123 static irqreturn_t gfar_transmit(int irq, void *dev_id);
124 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
125 static void adjust_link(struct net_device *dev);
126 static void init_registers(struct net_device *dev);
127 static int init_phy(struct net_device *dev);
128 static int gfar_probe(struct platform_device *pdev);
129 static int gfar_remove(struct platform_device *pdev);
130 static void free_skb_resources(struct gfar_private *priv);
131 static void gfar_set_multi(struct net_device *dev);
132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
133 static void gfar_configure_serdes(struct net_device *dev);
134 #ifdef CONFIG_GFAR_NAPI
135 static int gfar_poll(struct napi_struct *napi, int budget);
136 #endif
137 #ifdef CONFIG_NET_POLL_CONTROLLER
138 static void gfar_netpoll(struct net_device *dev);
139 #endif
140 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
141 static int gfar_clean_tx_ring(struct net_device *dev);
142 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
143 static void gfar_vlan_rx_register(struct net_device *netdev,
144                                 struct vlan_group *grp);
145 void gfar_halt(struct net_device *dev);
146 void gfar_start(struct net_device *dev);
147 static void gfar_clear_exact_match(struct net_device *dev);
148 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
149
150 extern const struct ethtool_ops gfar_ethtool_ops;
151
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
155
156 /* Returns 1 if incoming frames use an FCB */
157 static inline int gfar_uses_fcb(struct gfar_private *priv)
158 {
159         return (priv->vlan_enable || priv->rx_csum_enable);
160 }
161
162 /* Set up the ethernet device structure, private data,
163  * and anything else we need before we start */
164 static int gfar_probe(struct platform_device *pdev)
165 {
166         u32 tempval;
167         struct net_device *dev = NULL;
168         struct gfar_private *priv = NULL;
169         struct gianfar_platform_data *einfo;
170         struct resource *r;
171         int err = 0;
172         DECLARE_MAC_BUF(mac);
173
174         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
175
176         if (NULL == einfo) {
177                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
178                        pdev->id);
179
180                 return -ENODEV;
181         }
182
183         /* Create an ethernet device instance */
184         dev = alloc_etherdev(sizeof (*priv));
185
186         if (NULL == dev)
187                 return -ENOMEM;
188
189         priv = netdev_priv(dev);
190         priv->dev = dev;
191
192         /* Set the info in the priv to the current info */
193         priv->einfo = einfo;
194
195         /* fill out IRQ fields */
196         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
197                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
198                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
199                 priv->interruptError = platform_get_irq_byname(pdev, "error");
200                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
201                         goto regs_fail;
202         } else {
203                 priv->interruptTransmit = platform_get_irq(pdev, 0);
204                 if (priv->interruptTransmit < 0)
205                         goto regs_fail;
206         }
207
208         /* get a pointer to the register memory */
209         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
210         priv->regs = ioremap(r->start, sizeof (struct gfar));
211
212         if (NULL == priv->regs) {
213                 err = -ENOMEM;
214                 goto regs_fail;
215         }
216
217         spin_lock_init(&priv->txlock);
218         spin_lock_init(&priv->rxlock);
219
220         platform_set_drvdata(pdev, dev);
221
222         /* Stop the DMA engine now, in case it was running before */
223         /* (The firmware could have used it, and left it running). */
224         /* To do this, we write Graceful Receive Stop and Graceful */
225         /* Transmit Stop, and then wait until the corresponding bits */
226         /* in IEVENT indicate the stops have completed. */
227         tempval = gfar_read(&priv->regs->dmactrl);
228         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
229         gfar_write(&priv->regs->dmactrl, tempval);
230
231         tempval = gfar_read(&priv->regs->dmactrl);
232         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
233         gfar_write(&priv->regs->dmactrl, tempval);
234
235         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
236                 cpu_relax();
237
238         /* Reset MAC layer */
239         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
240
241         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
242         gfar_write(&priv->regs->maccfg1, tempval);
243
244         /* Initialize MACCFG2. */
245         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
246
247         /* Initialize ECNTRL */
248         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
249
250         /* Copy the station address into the dev structure, */
251         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
252
253         /* Set the dev->base_addr to the gfar reg region */
254         dev->base_addr = (unsigned long) (priv->regs);
255
256         SET_NETDEV_DEV(dev, &pdev->dev);
257
258         /* Fill in the dev structure */
259         dev->open = gfar_enet_open;
260         dev->hard_start_xmit = gfar_start_xmit;
261         dev->tx_timeout = gfar_timeout;
262         dev->watchdog_timeo = TX_TIMEOUT;
263 #ifdef CONFIG_GFAR_NAPI
264         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
265 #endif
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267         dev->poll_controller = gfar_netpoll;
268 #endif
269         dev->stop = gfar_close;
270         dev->change_mtu = gfar_change_mtu;
271         dev->mtu = 1500;
272         dev->set_multicast_list = gfar_set_multi;
273
274         dev->ethtool_ops = &gfar_ethtool_ops;
275
276         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
277                 priv->rx_csum_enable = 1;
278                 dev->features |= NETIF_F_IP_CSUM;
279         } else
280                 priv->rx_csum_enable = 0;
281
282         priv->vlgrp = NULL;
283
284         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
285                 dev->vlan_rx_register = gfar_vlan_rx_register;
286
287                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
288
289                 priv->vlan_enable = 1;
290         }
291
292         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
293                 priv->extended_hash = 1;
294                 priv->hash_width = 9;
295
296                 priv->hash_regs[0] = &priv->regs->igaddr0;
297                 priv->hash_regs[1] = &priv->regs->igaddr1;
298                 priv->hash_regs[2] = &priv->regs->igaddr2;
299                 priv->hash_regs[3] = &priv->regs->igaddr3;
300                 priv->hash_regs[4] = &priv->regs->igaddr4;
301                 priv->hash_regs[5] = &priv->regs->igaddr5;
302                 priv->hash_regs[6] = &priv->regs->igaddr6;
303                 priv->hash_regs[7] = &priv->regs->igaddr7;
304                 priv->hash_regs[8] = &priv->regs->gaddr0;
305                 priv->hash_regs[9] = &priv->regs->gaddr1;
306                 priv->hash_regs[10] = &priv->regs->gaddr2;
307                 priv->hash_regs[11] = &priv->regs->gaddr3;
308                 priv->hash_regs[12] = &priv->regs->gaddr4;
309                 priv->hash_regs[13] = &priv->regs->gaddr5;
310                 priv->hash_regs[14] = &priv->regs->gaddr6;
311                 priv->hash_regs[15] = &priv->regs->gaddr7;
312
313         } else {
314                 priv->extended_hash = 0;
315                 priv->hash_width = 8;
316
317                 priv->hash_regs[0] = &priv->regs->gaddr0;
318                 priv->hash_regs[1] = &priv->regs->gaddr1;
319                 priv->hash_regs[2] = &priv->regs->gaddr2;
320                 priv->hash_regs[3] = &priv->regs->gaddr3;
321                 priv->hash_regs[4] = &priv->regs->gaddr4;
322                 priv->hash_regs[5] = &priv->regs->gaddr5;
323                 priv->hash_regs[6] = &priv->regs->gaddr6;
324                 priv->hash_regs[7] = &priv->regs->gaddr7;
325         }
326
327         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
328                 priv->padding = DEFAULT_PADDING;
329         else
330                 priv->padding = 0;
331
332         if (dev->features & NETIF_F_IP_CSUM)
333                 dev->hard_header_len += GMAC_FCB_LEN;
334
335         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
336         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
337         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
338
339         priv->txcoalescing = DEFAULT_TX_COALESCE;
340         priv->txcount = DEFAULT_TXCOUNT;
341         priv->txtime = DEFAULT_TXTIME;
342         priv->rxcoalescing = DEFAULT_RX_COALESCE;
343         priv->rxcount = DEFAULT_RXCOUNT;
344         priv->rxtime = DEFAULT_RXTIME;
345
346         /* Enable most messages by default */
347         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
348
349         err = register_netdev(dev);
350
351         if (err) {
352                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
353                                 dev->name);
354                 goto register_fail;
355         }
356
357         /* Create all the sysfs files */
358         gfar_init_sysfs(dev);
359
360         /* Print out the device info */
361         printk(KERN_INFO DEVICE_NAME "%s\n",
362                dev->name, print_mac(mac, dev->dev_addr));
363
364         /* Even more device info helps when determining which kernel */
365         /* provided which set of benchmarks. */
366 #ifdef CONFIG_GFAR_NAPI
367         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
368 #else
369         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
370 #endif
371         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
372                dev->name, priv->rx_ring_size, priv->tx_ring_size);
373
374         return 0;
375
376 register_fail:
377         iounmap(priv->regs);
378 regs_fail:
379         free_netdev(dev);
380         return err;
381 }
382
383 static int gfar_remove(struct platform_device *pdev)
384 {
385         struct net_device *dev = platform_get_drvdata(pdev);
386         struct gfar_private *priv = netdev_priv(dev);
387
388         platform_set_drvdata(pdev, NULL);
389
390         iounmap(priv->regs);
391         free_netdev(dev);
392
393         return 0;
394 }
395
396
397 /* Reads the controller's registers to determine what interface
398  * connects it to the PHY.
399  */
400 static phy_interface_t gfar_get_interface(struct net_device *dev)
401 {
402         struct gfar_private *priv = netdev_priv(dev);
403         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
404
405         if (ecntrl & ECNTRL_SGMII_MODE)
406                 return PHY_INTERFACE_MODE_SGMII;
407
408         if (ecntrl & ECNTRL_TBI_MODE) {
409                 if (ecntrl & ECNTRL_REDUCED_MODE)
410                         return PHY_INTERFACE_MODE_RTBI;
411                 else
412                         return PHY_INTERFACE_MODE_TBI;
413         }
414
415         if (ecntrl & ECNTRL_REDUCED_MODE) {
416                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
417                         return PHY_INTERFACE_MODE_RMII;
418                 else {
419                         phy_interface_t interface = priv->einfo->interface;
420
421                         /*
422                          * This isn't autodetected right now, so it must
423                          * be set by the device tree or platform code.
424                          */
425                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
426                                 return PHY_INTERFACE_MODE_RGMII_ID;
427
428                         return PHY_INTERFACE_MODE_RGMII;
429                 }
430         }
431
432         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
433                 return PHY_INTERFACE_MODE_GMII;
434
435         return PHY_INTERFACE_MODE_MII;
436 }
437
438
439 /* Initializes driver's PHY state, and attaches to the PHY.
440  * Returns 0 on success.
441  */
442 static int init_phy(struct net_device *dev)
443 {
444         struct gfar_private *priv = netdev_priv(dev);
445         uint gigabit_support =
446                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
447                 SUPPORTED_1000baseT_Full : 0;
448         struct phy_device *phydev;
449         char phy_id[BUS_ID_SIZE];
450         phy_interface_t interface;
451
452         priv->oldlink = 0;
453         priv->oldspeed = 0;
454         priv->oldduplex = -1;
455
456         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
457
458         interface = gfar_get_interface(dev);
459
460         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
461
462         if (interface == PHY_INTERFACE_MODE_SGMII)
463                 gfar_configure_serdes(dev);
464
465         if (IS_ERR(phydev)) {
466                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
467                 return PTR_ERR(phydev);
468         }
469
470         /* Remove any features not supported by the controller */
471         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
472         phydev->advertising = phydev->supported;
473
474         priv->phydev = phydev;
475
476         return 0;
477 }
478
479 /*
480  * Initialize TBI PHY interface for communicating with the
481  * SERDES lynx PHY on the chip.  We communicate with this PHY
482  * through the MDIO bus on each controller, treating it as a
483  * "normal" PHY at the address found in the TBIPA register.  We assume
484  * that the TBIPA register is valid.  Either the MDIO bus code will set
485  * it to a value that doesn't conflict with other PHYs on the bus, or the
486  * value doesn't matter, as there are no other PHYs on the bus.
487  */
488 static void gfar_configure_serdes(struct net_device *dev)
489 {
490         struct gfar_private *priv = netdev_priv(dev);
491         struct gfar_mii __iomem *regs =
492                         (void __iomem *)&priv->regs->gfar_mii_regs;
493         int tbipa = gfar_read(&priv->regs->tbipa);
494
495         /* Single clk mode, mii mode off(for serdes communication) */
496         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
497
498         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
499                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
500                         ADVERTISE_1000XPSE_ASYM);
501
502         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
503                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
504 }
505
506 static void init_registers(struct net_device *dev)
507 {
508         struct gfar_private *priv = netdev_priv(dev);
509
510         /* Clear IEVENT */
511         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
512
513         /* Initialize IMASK */
514         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
515
516         /* Init hash registers to zero */
517         gfar_write(&priv->regs->igaddr0, 0);
518         gfar_write(&priv->regs->igaddr1, 0);
519         gfar_write(&priv->regs->igaddr2, 0);
520         gfar_write(&priv->regs->igaddr3, 0);
521         gfar_write(&priv->regs->igaddr4, 0);
522         gfar_write(&priv->regs->igaddr5, 0);
523         gfar_write(&priv->regs->igaddr6, 0);
524         gfar_write(&priv->regs->igaddr7, 0);
525
526         gfar_write(&priv->regs->gaddr0, 0);
527         gfar_write(&priv->regs->gaddr1, 0);
528         gfar_write(&priv->regs->gaddr2, 0);
529         gfar_write(&priv->regs->gaddr3, 0);
530         gfar_write(&priv->regs->gaddr4, 0);
531         gfar_write(&priv->regs->gaddr5, 0);
532         gfar_write(&priv->regs->gaddr6, 0);
533         gfar_write(&priv->regs->gaddr7, 0);
534
535         /* Zero out the rmon mib registers if it has them */
536         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
537                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
538
539                 /* Mask off the CAM interrupts */
540                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
541                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
542         }
543
544         /* Initialize the max receive buffer length */
545         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
546
547         /* Initialize the Minimum Frame Length Register */
548         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
549 }
550
551
552 /* Halt the receive and transmit queues */
553 void gfar_halt(struct net_device *dev)
554 {
555         struct gfar_private *priv = netdev_priv(dev);
556         struct gfar __iomem *regs = priv->regs;
557         u32 tempval;
558
559         /* Mask all interrupts */
560         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
561
562         /* Clear all interrupts */
563         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
564
565         /* Stop the DMA, and wait for it to stop */
566         tempval = gfar_read(&priv->regs->dmactrl);
567         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
568             != (DMACTRL_GRS | DMACTRL_GTS)) {
569                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
570                 gfar_write(&priv->regs->dmactrl, tempval);
571
572                 while (!(gfar_read(&priv->regs->ievent) &
573                          (IEVENT_GRSC | IEVENT_GTSC)))
574                         cpu_relax();
575         }
576
577         /* Disable Rx and Tx */
578         tempval = gfar_read(&regs->maccfg1);
579         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
580         gfar_write(&regs->maccfg1, tempval);
581 }
582
583 void stop_gfar(struct net_device *dev)
584 {
585         struct gfar_private *priv = netdev_priv(dev);
586         struct gfar __iomem *regs = priv->regs;
587         unsigned long flags;
588
589         phy_stop(priv->phydev);
590
591         /* Lock it down */
592         spin_lock_irqsave(&priv->txlock, flags);
593         spin_lock(&priv->rxlock);
594
595         gfar_halt(dev);
596
597         spin_unlock(&priv->rxlock);
598         spin_unlock_irqrestore(&priv->txlock, flags);
599
600         /* Free the IRQs */
601         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
602                 free_irq(priv->interruptError, dev);
603                 free_irq(priv->interruptTransmit, dev);
604                 free_irq(priv->interruptReceive, dev);
605         } else {
606                 free_irq(priv->interruptTransmit, dev);
607         }
608
609         free_skb_resources(priv);
610
611         dma_free_coherent(&dev->dev,
612                         sizeof(struct txbd8)*priv->tx_ring_size
613                         + sizeof(struct rxbd8)*priv->rx_ring_size,
614                         priv->tx_bd_base,
615                         gfar_read(&regs->tbase0));
616 }
617
618 /* If there are any tx skbs or rx skbs still around, free them.
619  * Then free tx_skbuff and rx_skbuff */
620 static void free_skb_resources(struct gfar_private *priv)
621 {
622         struct rxbd8 *rxbdp;
623         struct txbd8 *txbdp;
624         int i;
625
626         /* Go through all the buffer descriptors and free their data buffers */
627         txbdp = priv->tx_bd_base;
628
629         for (i = 0; i < priv->tx_ring_size; i++) {
630
631                 if (priv->tx_skbuff[i]) {
632                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
633                                         txbdp->length,
634                                         DMA_TO_DEVICE);
635                         dev_kfree_skb_any(priv->tx_skbuff[i]);
636                         priv->tx_skbuff[i] = NULL;
637                 }
638
639                 txbdp++;
640         }
641
642         kfree(priv->tx_skbuff);
643
644         rxbdp = priv->rx_bd_base;
645
646         /* rx_skbuff is not guaranteed to be allocated, so only
647          * free it and its contents if it is allocated */
648         if(priv->rx_skbuff != NULL) {
649                 for (i = 0; i < priv->rx_ring_size; i++) {
650                         if (priv->rx_skbuff[i]) {
651                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
652                                                 priv->rx_buffer_size,
653                                                 DMA_FROM_DEVICE);
654
655                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
656                                 priv->rx_skbuff[i] = NULL;
657                         }
658
659                         rxbdp->status = 0;
660                         rxbdp->length = 0;
661                         rxbdp->bufPtr = 0;
662
663                         rxbdp++;
664                 }
665
666                 kfree(priv->rx_skbuff);
667         }
668 }
669
670 void gfar_start(struct net_device *dev)
671 {
672         struct gfar_private *priv = netdev_priv(dev);
673         struct gfar __iomem *regs = priv->regs;
674         u32 tempval;
675
676         /* Enable Rx and Tx in MACCFG1 */
677         tempval = gfar_read(&regs->maccfg1);
678         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
679         gfar_write(&regs->maccfg1, tempval);
680
681         /* Initialize DMACTRL to have WWR and WOP */
682         tempval = gfar_read(&priv->regs->dmactrl);
683         tempval |= DMACTRL_INIT_SETTINGS;
684         gfar_write(&priv->regs->dmactrl, tempval);
685
686         /* Make sure we aren't stopped */
687         tempval = gfar_read(&priv->regs->dmactrl);
688         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
689         gfar_write(&priv->regs->dmactrl, tempval);
690
691         /* Clear THLT/RHLT, so that the DMA starts polling now */
692         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
693         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
694
695         /* Unmask the interrupts we look for */
696         gfar_write(&regs->imask, IMASK_DEFAULT);
697 }
698
699 /* Bring the controller up and running */
700 int startup_gfar(struct net_device *dev)
701 {
702         struct txbd8 *txbdp;
703         struct rxbd8 *rxbdp;
704         dma_addr_t addr = 0;
705         unsigned long vaddr;
706         int i;
707         struct gfar_private *priv = netdev_priv(dev);
708         struct gfar __iomem *regs = priv->regs;
709         int err = 0;
710         u32 rctrl = 0;
711         u32 attrs = 0;
712
713         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
714
715         /* Allocate memory for the buffer descriptors */
716         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
717                         sizeof (struct txbd8) * priv->tx_ring_size +
718                         sizeof (struct rxbd8) * priv->rx_ring_size,
719                         &addr, GFP_KERNEL);
720
721         if (vaddr == 0) {
722                 if (netif_msg_ifup(priv))
723                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
724                                         dev->name);
725                 return -ENOMEM;
726         }
727
728         priv->tx_bd_base = (struct txbd8 *) vaddr;
729
730         /* enet DMA only understands physical addresses */
731         gfar_write(&regs->tbase0, addr);
732
733         /* Start the rx descriptor ring where the tx ring leaves off */
734         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
735         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
736         priv->rx_bd_base = (struct rxbd8 *) vaddr;
737         gfar_write(&regs->rbase0, addr);
738
739         /* Setup the skbuff rings */
740         priv->tx_skbuff =
741             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
742                                         priv->tx_ring_size, GFP_KERNEL);
743
744         if (NULL == priv->tx_skbuff) {
745                 if (netif_msg_ifup(priv))
746                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
747                                         dev->name);
748                 err = -ENOMEM;
749                 goto tx_skb_fail;
750         }
751
752         for (i = 0; i < priv->tx_ring_size; i++)
753                 priv->tx_skbuff[i] = NULL;
754
755         priv->rx_skbuff =
756             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
757                                         priv->rx_ring_size, GFP_KERNEL);
758
759         if (NULL == priv->rx_skbuff) {
760                 if (netif_msg_ifup(priv))
761                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
762                                         dev->name);
763                 err = -ENOMEM;
764                 goto rx_skb_fail;
765         }
766
767         for (i = 0; i < priv->rx_ring_size; i++)
768                 priv->rx_skbuff[i] = NULL;
769
770         /* Initialize some variables in our dev structure */
771         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
772         priv->cur_rx = priv->rx_bd_base;
773         priv->skb_curtx = priv->skb_dirtytx = 0;
774         priv->skb_currx = 0;
775
776         /* Initialize Transmit Descriptor Ring */
777         txbdp = priv->tx_bd_base;
778         for (i = 0; i < priv->tx_ring_size; i++) {
779                 txbdp->status = 0;
780                 txbdp->length = 0;
781                 txbdp->bufPtr = 0;
782                 txbdp++;
783         }
784
785         /* Set the last descriptor in the ring to indicate wrap */
786         txbdp--;
787         txbdp->status |= TXBD_WRAP;
788
789         rxbdp = priv->rx_bd_base;
790         for (i = 0; i < priv->rx_ring_size; i++) {
791                 struct sk_buff *skb;
792
793                 skb = gfar_new_skb(dev);
794
795                 if (!skb) {
796                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
797                                         dev->name);
798
799                         goto err_rxalloc_fail;
800                 }
801
802                 priv->rx_skbuff[i] = skb;
803
804                 gfar_new_rxbdp(dev, rxbdp, skb);
805
806                 rxbdp++;
807         }
808
809         /* Set the last descriptor in the ring to wrap */
810         rxbdp--;
811         rxbdp->status |= RXBD_WRAP;
812
813         /* If the device has multiple interrupts, register for
814          * them.  Otherwise, only register for the one */
815         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
816                 /* Install our interrupt handlers for Error,
817                  * Transmit, and Receive */
818                 if (request_irq(priv->interruptError, gfar_error,
819                                 0, "enet_error", dev) < 0) {
820                         if (netif_msg_intr(priv))
821                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
822                                         dev->name, priv->interruptError);
823
824                         err = -1;
825                         goto err_irq_fail;
826                 }
827
828                 if (request_irq(priv->interruptTransmit, gfar_transmit,
829                                 0, "enet_tx", dev) < 0) {
830                         if (netif_msg_intr(priv))
831                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
832                                         dev->name, priv->interruptTransmit);
833
834                         err = -1;
835
836                         goto tx_irq_fail;
837                 }
838
839                 if (request_irq(priv->interruptReceive, gfar_receive,
840                                 0, "enet_rx", dev) < 0) {
841                         if (netif_msg_intr(priv))
842                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
843                                                 dev->name, priv->interruptReceive);
844
845                         err = -1;
846                         goto rx_irq_fail;
847                 }
848         } else {
849                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
850                                 0, "gfar_interrupt", dev) < 0) {
851                         if (netif_msg_intr(priv))
852                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
853                                         dev->name, priv->interruptError);
854
855                         err = -1;
856                         goto err_irq_fail;
857                 }
858         }
859
860         phy_start(priv->phydev);
861
862         /* Configure the coalescing support */
863         if (priv->txcoalescing)
864                 gfar_write(&regs->txic,
865                            mk_ic_value(priv->txcount, priv->txtime));
866         else
867                 gfar_write(&regs->txic, 0);
868
869         if (priv->rxcoalescing)
870                 gfar_write(&regs->rxic,
871                            mk_ic_value(priv->rxcount, priv->rxtime));
872         else
873                 gfar_write(&regs->rxic, 0);
874
875         if (priv->rx_csum_enable)
876                 rctrl |= RCTRL_CHECKSUMMING;
877
878         if (priv->extended_hash) {
879                 rctrl |= RCTRL_EXTHASH;
880
881                 gfar_clear_exact_match(dev);
882                 rctrl |= RCTRL_EMEN;
883         }
884
885         if (priv->vlan_enable)
886                 rctrl |= RCTRL_VLAN;
887
888         if (priv->padding) {
889                 rctrl &= ~RCTRL_PAL_MASK;
890                 rctrl |= RCTRL_PADDING(priv->padding);
891         }
892
893         /* Init rctrl based on our settings */
894         gfar_write(&priv->regs->rctrl, rctrl);
895
896         if (dev->features & NETIF_F_IP_CSUM)
897                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
898
899         /* Set the extraction length and index */
900         attrs = ATTRELI_EL(priv->rx_stash_size) |
901                 ATTRELI_EI(priv->rx_stash_index);
902
903         gfar_write(&priv->regs->attreli, attrs);
904
905         /* Start with defaults, and add stashing or locking
906          * depending on the approprate variables */
907         attrs = ATTR_INIT_SETTINGS;
908
909         if (priv->bd_stash_en)
910                 attrs |= ATTR_BDSTASH;
911
912         if (priv->rx_stash_size != 0)
913                 attrs |= ATTR_BUFSTASH;
914
915         gfar_write(&priv->regs->attr, attrs);
916
917         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
918         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
919         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
920
921         /* Start the controller */
922         gfar_start(dev);
923
924         return 0;
925
926 rx_irq_fail:
927         free_irq(priv->interruptTransmit, dev);
928 tx_irq_fail:
929         free_irq(priv->interruptError, dev);
930 err_irq_fail:
931 err_rxalloc_fail:
932 rx_skb_fail:
933         free_skb_resources(priv);
934 tx_skb_fail:
935         dma_free_coherent(&dev->dev,
936                         sizeof(struct txbd8)*priv->tx_ring_size
937                         + sizeof(struct rxbd8)*priv->rx_ring_size,
938                         priv->tx_bd_base,
939                         gfar_read(&regs->tbase0));
940
941         return err;
942 }
943
944 /* Called when something needs to use the ethernet device */
945 /* Returns 0 for success. */
946 static int gfar_enet_open(struct net_device *dev)
947 {
948 #ifdef CONFIG_GFAR_NAPI
949         struct gfar_private *priv = netdev_priv(dev);
950 #endif
951         int err;
952
953 #ifdef CONFIG_GFAR_NAPI
954         napi_enable(&priv->napi);
955 #endif
956
957         /* Initialize a bunch of registers */
958         init_registers(dev);
959
960         gfar_set_mac_address(dev);
961
962         err = init_phy(dev);
963
964         if(err) {
965 #ifdef CONFIG_GFAR_NAPI
966                 napi_disable(&priv->napi);
967 #endif
968                 return err;
969         }
970
971         err = startup_gfar(dev);
972         if (err) {
973 #ifdef CONFIG_GFAR_NAPI
974                 napi_disable(&priv->napi);
975 #endif
976                 return err;
977         }
978
979         netif_start_queue(dev);
980
981         return err;
982 }
983
984 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
985 {
986         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
987
988         memset(fcb, 0, GMAC_FCB_LEN);
989
990         return fcb;
991 }
992
993 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
994 {
995         u8 flags = 0;
996
997         /* If we're here, it's a IP packet with a TCP or UDP
998          * payload.  We set it to checksum, using a pseudo-header
999          * we provide
1000          */
1001         flags = TXFCB_DEFAULT;
1002
1003         /* Tell the controller what the protocol is */
1004         /* And provide the already calculated phcs */
1005         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1006                 flags |= TXFCB_UDP;
1007                 fcb->phcs = udp_hdr(skb)->check;
1008         } else
1009                 fcb->phcs = tcp_hdr(skb)->check;
1010
1011         /* l3os is the distance between the start of the
1012          * frame (skb->data) and the start of the IP hdr.
1013          * l4os is the distance between the start of the
1014          * l3 hdr and the l4 hdr */
1015         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1016         fcb->l4os = skb_network_header_len(skb);
1017
1018         fcb->flags = flags;
1019 }
1020
1021 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1022 {
1023         fcb->flags |= TXFCB_VLN;
1024         fcb->vlctl = vlan_tx_tag_get(skb);
1025 }
1026
1027 /* This is called by the kernel when a frame is ready for transmission. */
1028 /* It is pointed to by the dev->hard_start_xmit function pointer */
1029 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1030 {
1031         struct gfar_private *priv = netdev_priv(dev);
1032         struct txfcb *fcb = NULL;
1033         struct txbd8 *txbdp;
1034         u16 status;
1035         unsigned long flags;
1036
1037         /* Update transmit stats */
1038         dev->stats.tx_bytes += skb->len;
1039
1040         /* Lock priv now */
1041         spin_lock_irqsave(&priv->txlock, flags);
1042
1043         /* Point at the first free tx descriptor */
1044         txbdp = priv->cur_tx;
1045
1046         /* Clear all but the WRAP status flags */
1047         status = txbdp->status & TXBD_WRAP;
1048
1049         /* Set up checksumming */
1050         if (likely((dev->features & NETIF_F_IP_CSUM)
1051                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1052                 fcb = gfar_add_fcb(skb, txbdp);
1053                 status |= TXBD_TOE;
1054                 gfar_tx_checksum(skb, fcb);
1055         }
1056
1057         if (priv->vlan_enable &&
1058                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1059                 if (unlikely(NULL == fcb)) {
1060                         fcb = gfar_add_fcb(skb, txbdp);
1061                         status |= TXBD_TOE;
1062                 }
1063
1064                 gfar_tx_vlan(skb, fcb);
1065         }
1066
1067         /* Set buffer length and pointer */
1068         txbdp->length = skb->len;
1069         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1070                         skb->len, DMA_TO_DEVICE);
1071
1072         /* Save the skb pointer so we can free it later */
1073         priv->tx_skbuff[priv->skb_curtx] = skb;
1074
1075         /* Update the current skb pointer (wrapping if this was the last) */
1076         priv->skb_curtx =
1077             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1078
1079         /* Flag the BD as interrupt-causing */
1080         status |= TXBD_INTERRUPT;
1081
1082         /* Flag the BD as ready to go, last in frame, and  */
1083         /* in need of CRC */
1084         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1085
1086         dev->trans_start = jiffies;
1087
1088         /* The powerpc-specific eieio() is used, as wmb() has too strong
1089          * semantics (it requires synchronization between cacheable and
1090          * uncacheable mappings, which eieio doesn't provide and which we
1091          * don't need), thus requiring a more expensive sync instruction.  At
1092          * some point, the set of architecture-independent barrier functions
1093          * should be expanded to include weaker barriers.
1094          */
1095
1096         eieio();
1097         txbdp->status = status;
1098
1099         /* If this was the last BD in the ring, the next one */
1100         /* is at the beginning of the ring */
1101         if (txbdp->status & TXBD_WRAP)
1102                 txbdp = priv->tx_bd_base;
1103         else
1104                 txbdp++;
1105
1106         /* If the next BD still needs to be cleaned up, then the bds
1107            are full.  We need to tell the kernel to stop sending us stuff. */
1108         if (txbdp == priv->dirty_tx) {
1109                 netif_stop_queue(dev);
1110
1111                 dev->stats.tx_fifo_errors++;
1112         }
1113
1114         /* Update the current txbd to the next one */
1115         priv->cur_tx = txbdp;
1116
1117         /* Tell the DMA to go go go */
1118         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1119
1120         /* Unlock priv */
1121         spin_unlock_irqrestore(&priv->txlock, flags);
1122
1123         return 0;
1124 }
1125
1126 /* Stops the kernel queue, and halts the controller */
1127 static int gfar_close(struct net_device *dev)
1128 {
1129         struct gfar_private *priv = netdev_priv(dev);
1130
1131 #ifdef CONFIG_GFAR_NAPI
1132         napi_disable(&priv->napi);
1133 #endif
1134
1135         stop_gfar(dev);
1136
1137         /* Disconnect from the PHY */
1138         phy_disconnect(priv->phydev);
1139         priv->phydev = NULL;
1140
1141         netif_stop_queue(dev);
1142
1143         return 0;
1144 }
1145
1146 /* Changes the mac address if the controller is not running. */
1147 static int gfar_set_mac_address(struct net_device *dev)
1148 {
1149         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1150
1151         return 0;
1152 }
1153
1154
1155 /* Enables and disables VLAN insertion/extraction */
1156 static void gfar_vlan_rx_register(struct net_device *dev,
1157                 struct vlan_group *grp)
1158 {
1159         struct gfar_private *priv = netdev_priv(dev);
1160         unsigned long flags;
1161         u32 tempval;
1162
1163         spin_lock_irqsave(&priv->rxlock, flags);
1164
1165         priv->vlgrp = grp;
1166
1167         if (grp) {
1168                 /* Enable VLAN tag insertion */
1169                 tempval = gfar_read(&priv->regs->tctrl);
1170                 tempval |= TCTRL_VLINS;
1171
1172                 gfar_write(&priv->regs->tctrl, tempval);
1173
1174                 /* Enable VLAN tag extraction */
1175                 tempval = gfar_read(&priv->regs->rctrl);
1176                 tempval |= RCTRL_VLEX;
1177                 gfar_write(&priv->regs->rctrl, tempval);
1178         } else {
1179                 /* Disable VLAN tag insertion */
1180                 tempval = gfar_read(&priv->regs->tctrl);
1181                 tempval &= ~TCTRL_VLINS;
1182                 gfar_write(&priv->regs->tctrl, tempval);
1183
1184                 /* Disable VLAN tag extraction */
1185                 tempval = gfar_read(&priv->regs->rctrl);
1186                 tempval &= ~RCTRL_VLEX;
1187                 gfar_write(&priv->regs->rctrl, tempval);
1188         }
1189
1190         spin_unlock_irqrestore(&priv->rxlock, flags);
1191 }
1192
1193 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1194 {
1195         int tempsize, tempval;
1196         struct gfar_private *priv = netdev_priv(dev);
1197         int oldsize = priv->rx_buffer_size;
1198         int frame_size = new_mtu + ETH_HLEN;
1199
1200         if (priv->vlan_enable)
1201                 frame_size += VLAN_HLEN;
1202
1203         if (gfar_uses_fcb(priv))
1204                 frame_size += GMAC_FCB_LEN;
1205
1206         frame_size += priv->padding;
1207
1208         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1209                 if (netif_msg_drv(priv))
1210                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1211                                         dev->name);
1212                 return -EINVAL;
1213         }
1214
1215         tempsize =
1216             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1217             INCREMENTAL_BUFFER_SIZE;
1218
1219         /* Only stop and start the controller if it isn't already
1220          * stopped, and we changed something */
1221         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1222                 stop_gfar(dev);
1223
1224         priv->rx_buffer_size = tempsize;
1225
1226         dev->mtu = new_mtu;
1227
1228         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1229         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1230
1231         /* If the mtu is larger than the max size for standard
1232          * ethernet frames (ie, a jumbo frame), then set maccfg2
1233          * to allow huge frames, and to check the length */
1234         tempval = gfar_read(&priv->regs->maccfg2);
1235
1236         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1237                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1238         else
1239                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1240
1241         gfar_write(&priv->regs->maccfg2, tempval);
1242
1243         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1244                 startup_gfar(dev);
1245
1246         return 0;
1247 }
1248
1249 /* gfar_timeout gets called when a packet has not been
1250  * transmitted after a set amount of time.
1251  * For now, assume that clearing out all the structures, and
1252  * starting over will fix the problem. */
1253 static void gfar_timeout(struct net_device *dev)
1254 {
1255         dev->stats.tx_errors++;
1256
1257         if (dev->flags & IFF_UP) {
1258                 stop_gfar(dev);
1259                 startup_gfar(dev);
1260         }
1261
1262         netif_schedule(dev);
1263 }
1264
1265 /* Interrupt Handler for Transmit complete */
1266 static int gfar_clean_tx_ring(struct net_device *dev)
1267 {
1268         struct txbd8 *bdp;
1269         struct gfar_private *priv = netdev_priv(dev);
1270         int howmany = 0;
1271
1272         bdp = priv->dirty_tx;
1273         while ((bdp->status & TXBD_READY) == 0) {
1274                 /* If dirty_tx and cur_tx are the same, then either the */
1275                 /* ring is empty or full now (it could only be full in the beginning, */
1276                 /* obviously).  If it is empty, we are done. */
1277                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1278                         break;
1279
1280                 howmany++;
1281
1282                 /* Deferred means some collisions occurred during transmit, */
1283                 /* but we eventually sent the packet. */
1284                 if (bdp->status & TXBD_DEF)
1285                         dev->stats.collisions++;
1286
1287                 /* Free the sk buffer associated with this TxBD */
1288                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1289
1290                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1291                 priv->skb_dirtytx =
1292                     (priv->skb_dirtytx +
1293                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1294
1295                 /* Clean BD length for empty detection */
1296                 bdp->length = 0;
1297
1298                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1299                 if (bdp->status & TXBD_WRAP)
1300                         bdp = priv->tx_bd_base;
1301                 else
1302                         bdp++;
1303
1304                 /* Move dirty_tx to be the next bd */
1305                 priv->dirty_tx = bdp;
1306
1307                 /* We freed a buffer, so now we can restart transmission */
1308                 if (netif_queue_stopped(dev))
1309                         netif_wake_queue(dev);
1310         } /* while ((bdp->status & TXBD_READY) == 0) */
1311
1312         dev->stats.tx_packets += howmany;
1313
1314         return howmany;
1315 }
1316
1317 /* Interrupt Handler for Transmit complete */
1318 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1319 {
1320         struct net_device *dev = (struct net_device *) dev_id;
1321         struct gfar_private *priv = netdev_priv(dev);
1322
1323         /* Clear IEVENT */
1324         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1325
1326         /* Lock priv */
1327         spin_lock(&priv->txlock);
1328
1329         gfar_clean_tx_ring(dev);
1330
1331         /* If we are coalescing the interrupts, reset the timer */
1332         /* Otherwise, clear it */
1333         if (likely(priv->txcoalescing)) {
1334                 gfar_write(&priv->regs->txic, 0);
1335                 gfar_write(&priv->regs->txic,
1336                            mk_ic_value(priv->txcount, priv->txtime));
1337         }
1338
1339         spin_unlock(&priv->txlock);
1340
1341         return IRQ_HANDLED;
1342 }
1343
1344 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1345                 struct sk_buff *skb)
1346 {
1347         struct gfar_private *priv = netdev_priv(dev);
1348         u32 * status_len = (u32 *)bdp;
1349         u16 flags;
1350
1351         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1352                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1353
1354         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1355
1356         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1357                 flags |= RXBD_WRAP;
1358
1359         eieio();
1360
1361         *status_len = (u32)flags << 16;
1362 }
1363
1364
1365 struct sk_buff * gfar_new_skb(struct net_device *dev)
1366 {
1367         unsigned int alignamount;
1368         struct gfar_private *priv = netdev_priv(dev);
1369         struct sk_buff *skb = NULL;
1370
1371         /* We have to allocate the skb, so keep trying till we succeed */
1372         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1373
1374         if (!skb)
1375                 return NULL;
1376
1377         alignamount = RXBUF_ALIGNMENT -
1378                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1379
1380         /* We need the data buffer to be aligned properly.  We will reserve
1381          * as many bytes as needed to align the data properly
1382          */
1383         skb_reserve(skb, alignamount);
1384
1385         return skb;
1386 }
1387
1388 static inline void count_errors(unsigned short status, struct net_device *dev)
1389 {
1390         struct gfar_private *priv = netdev_priv(dev);
1391         struct net_device_stats *stats = &dev->stats;
1392         struct gfar_extra_stats *estats = &priv->extra_stats;
1393
1394         /* If the packet was truncated, none of the other errors
1395          * matter */
1396         if (status & RXBD_TRUNCATED) {
1397                 stats->rx_length_errors++;
1398
1399                 estats->rx_trunc++;
1400
1401                 return;
1402         }
1403         /* Count the errors, if there were any */
1404         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1405                 stats->rx_length_errors++;
1406
1407                 if (status & RXBD_LARGE)
1408                         estats->rx_large++;
1409                 else
1410                         estats->rx_short++;
1411         }
1412         if (status & RXBD_NONOCTET) {
1413                 stats->rx_frame_errors++;
1414                 estats->rx_nonoctet++;
1415         }
1416         if (status & RXBD_CRCERR) {
1417                 estats->rx_crcerr++;
1418                 stats->rx_crc_errors++;
1419         }
1420         if (status & RXBD_OVERRUN) {
1421                 estats->rx_overrun++;
1422                 stats->rx_crc_errors++;
1423         }
1424 }
1425
1426 irqreturn_t gfar_receive(int irq, void *dev_id)
1427 {
1428         struct net_device *dev = (struct net_device *) dev_id;
1429         struct gfar_private *priv = netdev_priv(dev);
1430 #ifdef CONFIG_GFAR_NAPI
1431         u32 tempval;
1432 #else
1433         unsigned long flags;
1434 #endif
1435
1436         /* support NAPI */
1437 #ifdef CONFIG_GFAR_NAPI
1438         /* Clear IEVENT, so interrupts aren't called again
1439          * because of the packets that have already arrived */
1440         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1441
1442         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1443                 tempval = gfar_read(&priv->regs->imask);
1444                 tempval &= IMASK_RTX_DISABLED;
1445                 gfar_write(&priv->regs->imask, tempval);
1446
1447                 __netif_rx_schedule(dev, &priv->napi);
1448         } else {
1449                 if (netif_msg_rx_err(priv))
1450                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1451                                 dev->name, gfar_read(&priv->regs->ievent),
1452                                 gfar_read(&priv->regs->imask));
1453         }
1454 #else
1455         /* Clear IEVENT, so rx interrupt isn't called again
1456          * because of this interrupt */
1457         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1458
1459         spin_lock_irqsave(&priv->rxlock, flags);
1460         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1461
1462         /* If we are coalescing interrupts, update the timer */
1463         /* Otherwise, clear it */
1464         if (likely(priv->rxcoalescing)) {
1465                 gfar_write(&priv->regs->rxic, 0);
1466                 gfar_write(&priv->regs->rxic,
1467                            mk_ic_value(priv->rxcount, priv->rxtime));
1468         }
1469
1470         spin_unlock_irqrestore(&priv->rxlock, flags);
1471 #endif
1472
1473         return IRQ_HANDLED;
1474 }
1475
1476 static inline int gfar_rx_vlan(struct sk_buff *skb,
1477                 struct vlan_group *vlgrp, unsigned short vlctl)
1478 {
1479 #ifdef CONFIG_GFAR_NAPI
1480         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1481 #else
1482         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1483 #endif
1484 }
1485
1486 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1487 {
1488         /* If valid headers were found, and valid sums
1489          * were verified, then we tell the kernel that no
1490          * checksumming is necessary.  Otherwise, it is */
1491         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1492                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1493         else
1494                 skb->ip_summed = CHECKSUM_NONE;
1495 }
1496
1497
1498 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1499 {
1500         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1501
1502         /* Remove the FCB from the skb */
1503         skb_pull(skb, GMAC_FCB_LEN);
1504
1505         return fcb;
1506 }
1507
1508 /* gfar_process_frame() -- handle one incoming packet if skb
1509  * isn't NULL.  */
1510 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1511                 int length)
1512 {
1513         struct gfar_private *priv = netdev_priv(dev);
1514         struct rxfcb *fcb = NULL;
1515
1516         if (NULL == skb) {
1517                 if (netif_msg_rx_err(priv))
1518                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1519                 dev->stats.rx_dropped++;
1520                 priv->extra_stats.rx_skbmissing++;
1521         } else {
1522                 int ret;
1523
1524                 /* Prep the skb for the packet */
1525                 skb_put(skb, length);
1526
1527                 /* Grab the FCB if there is one */
1528                 if (gfar_uses_fcb(priv))
1529                         fcb = gfar_get_fcb(skb);
1530
1531                 /* Remove the padded bytes, if there are any */
1532                 if (priv->padding)
1533                         skb_pull(skb, priv->padding);
1534
1535                 if (priv->rx_csum_enable)
1536                         gfar_rx_checksum(skb, fcb);
1537
1538                 /* Tell the skb what kind of packet this is */
1539                 skb->protocol = eth_type_trans(skb, dev);
1540
1541                 /* Send the packet up the stack */
1542                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1543                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1544                 else
1545                         ret = RECEIVE(skb);
1546
1547                 if (NET_RX_DROP == ret)
1548                         priv->extra_stats.kernel_dropped++;
1549         }
1550
1551         return 0;
1552 }
1553
1554 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1555  *   until the budget/quota has been reached. Returns the number
1556  *   of frames handled
1557  */
1558 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1559 {
1560         struct rxbd8 *bdp;
1561         struct sk_buff *skb;
1562         u16 pkt_len;
1563         int howmany = 0;
1564         struct gfar_private *priv = netdev_priv(dev);
1565
1566         /* Get the first full descriptor */
1567         bdp = priv->cur_rx;
1568
1569         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1570                 struct sk_buff *newskb;
1571                 rmb();
1572
1573                 /* Add another skb for the future */
1574                 newskb = gfar_new_skb(dev);
1575
1576                 skb = priv->rx_skbuff[priv->skb_currx];
1577
1578                 /* We drop the frame if we failed to allocate a new buffer */
1579                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1580                                  bdp->status & RXBD_ERR)) {
1581                         count_errors(bdp->status, dev);
1582
1583                         if (unlikely(!newskb))
1584                                 newskb = skb;
1585
1586                         if (skb) {
1587                                 dma_unmap_single(&priv->dev->dev,
1588                                                 bdp->bufPtr,
1589                                                 priv->rx_buffer_size,
1590                                                 DMA_FROM_DEVICE);
1591
1592                                 dev_kfree_skb_any(skb);
1593                         }
1594                 } else {
1595                         /* Increment the number of packets */
1596                         dev->stats.rx_packets++;
1597                         howmany++;
1598
1599                         /* Remove the FCS from the packet length */
1600                         pkt_len = bdp->length - 4;
1601
1602                         gfar_process_frame(dev, skb, pkt_len);
1603
1604                         dev->stats.rx_bytes += pkt_len;
1605                 }
1606
1607                 dev->last_rx = jiffies;
1608
1609                 priv->rx_skbuff[priv->skb_currx] = newskb;
1610
1611                 /* Setup the new bdp */
1612                 gfar_new_rxbdp(dev, bdp, newskb);
1613
1614                 /* Update to the next pointer */
1615                 if (bdp->status & RXBD_WRAP)
1616                         bdp = priv->rx_bd_base;
1617                 else
1618                         bdp++;
1619
1620                 /* update to point at the next skb */
1621                 priv->skb_currx =
1622                     (priv->skb_currx + 1) &
1623                     RX_RING_MOD_MASK(priv->rx_ring_size);
1624         }
1625
1626         /* Update the current rxbd pointer to be the next one */
1627         priv->cur_rx = bdp;
1628
1629         return howmany;
1630 }
1631
1632 #ifdef CONFIG_GFAR_NAPI
1633 static int gfar_poll(struct napi_struct *napi, int budget)
1634 {
1635         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1636         struct net_device *dev = priv->dev;
1637         int howmany;
1638         unsigned long flags;
1639
1640         /* If we fail to get the lock, don't bother with the TX BDs */
1641         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1642                 gfar_clean_tx_ring(dev);
1643                 spin_unlock_irqrestore(&priv->txlock, flags);
1644         }
1645
1646         howmany = gfar_clean_rx_ring(dev, budget);
1647
1648         if (howmany < budget) {
1649                 netif_rx_complete(dev, napi);
1650
1651                 /* Clear the halt bit in RSTAT */
1652                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1653
1654                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1655
1656                 /* If we are coalescing interrupts, update the timer */
1657                 /* Otherwise, clear it */
1658                 if (likely(priv->rxcoalescing)) {
1659                         gfar_write(&priv->regs->rxic, 0);
1660                         gfar_write(&priv->regs->rxic,
1661                                    mk_ic_value(priv->rxcount, priv->rxtime));
1662                 }
1663         }
1664
1665         return howmany;
1666 }
1667 #endif
1668
1669 #ifdef CONFIG_NET_POLL_CONTROLLER
1670 /*
1671  * Polling 'interrupt' - used by things like netconsole to send skbs
1672  * without having to re-enable interrupts. It's not called while
1673  * the interrupt routine is executing.
1674  */
1675 static void gfar_netpoll(struct net_device *dev)
1676 {
1677         struct gfar_private *priv = netdev_priv(dev);
1678
1679         /* If the device has multiple interrupts, run tx/rx */
1680         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1681                 disable_irq(priv->interruptTransmit);
1682                 disable_irq(priv->interruptReceive);
1683                 disable_irq(priv->interruptError);
1684                 gfar_interrupt(priv->interruptTransmit, dev);
1685                 enable_irq(priv->interruptError);
1686                 enable_irq(priv->interruptReceive);
1687                 enable_irq(priv->interruptTransmit);
1688         } else {
1689                 disable_irq(priv->interruptTransmit);
1690                 gfar_interrupt(priv->interruptTransmit, dev);
1691                 enable_irq(priv->interruptTransmit);
1692         }
1693 }
1694 #endif
1695
1696 /* The interrupt handler for devices with one interrupt */
1697 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1698 {
1699         struct net_device *dev = dev_id;
1700         struct gfar_private *priv = netdev_priv(dev);
1701
1702         /* Save ievent for future reference */
1703         u32 events = gfar_read(&priv->regs->ievent);
1704
1705         /* Check for reception */
1706         if (events & IEVENT_RX_MASK)
1707                 gfar_receive(irq, dev_id);
1708
1709         /* Check for transmit completion */
1710         if (events & IEVENT_TX_MASK)
1711                 gfar_transmit(irq, dev_id);
1712
1713         /* Check for errors */
1714         if (events & IEVENT_ERR_MASK)
1715                 gfar_error(irq, dev_id);
1716
1717         return IRQ_HANDLED;
1718 }
1719
1720 /* Called every time the controller might need to be made
1721  * aware of new link state.  The PHY code conveys this
1722  * information through variables in the phydev structure, and this
1723  * function converts those variables into the appropriate
1724  * register values, and can bring down the device if needed.
1725  */
1726 static void adjust_link(struct net_device *dev)
1727 {
1728         struct gfar_private *priv = netdev_priv(dev);
1729         struct gfar __iomem *regs = priv->regs;
1730         unsigned long flags;
1731         struct phy_device *phydev = priv->phydev;
1732         int new_state = 0;
1733
1734         spin_lock_irqsave(&priv->txlock, flags);
1735         if (phydev->link) {
1736                 u32 tempval = gfar_read(&regs->maccfg2);
1737                 u32 ecntrl = gfar_read(&regs->ecntrl);
1738
1739                 /* Now we make sure that we can be in full duplex mode.
1740                  * If not, we operate in half-duplex mode. */
1741                 if (phydev->duplex != priv->oldduplex) {
1742                         new_state = 1;
1743                         if (!(phydev->duplex))
1744                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1745                         else
1746                                 tempval |= MACCFG2_FULL_DUPLEX;
1747
1748                         priv->oldduplex = phydev->duplex;
1749                 }
1750
1751                 if (phydev->speed != priv->oldspeed) {
1752                         new_state = 1;
1753                         switch (phydev->speed) {
1754                         case 1000:
1755                                 tempval =
1756                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1757                                 break;
1758                         case 100:
1759                         case 10:
1760                                 tempval =
1761                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1762
1763                                 /* Reduced mode distinguishes
1764                                  * between 10 and 100 */
1765                                 if (phydev->speed == SPEED_100)
1766                                         ecntrl |= ECNTRL_R100;
1767                                 else
1768                                         ecntrl &= ~(ECNTRL_R100);
1769                                 break;
1770                         default:
1771                                 if (netif_msg_link(priv))
1772                                         printk(KERN_WARNING
1773                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1774                                                 dev->name, phydev->speed);
1775                                 break;
1776                         }
1777
1778                         priv->oldspeed = phydev->speed;
1779                 }
1780
1781                 gfar_write(&regs->maccfg2, tempval);
1782                 gfar_write(&regs->ecntrl, ecntrl);
1783
1784                 if (!priv->oldlink) {
1785                         new_state = 1;
1786                         priv->oldlink = 1;
1787                         netif_schedule(dev);
1788                 }
1789         } else if (priv->oldlink) {
1790                 new_state = 1;
1791                 priv->oldlink = 0;
1792                 priv->oldspeed = 0;
1793                 priv->oldduplex = -1;
1794         }
1795
1796         if (new_state && netif_msg_link(priv))
1797                 phy_print_status(phydev);
1798
1799         spin_unlock_irqrestore(&priv->txlock, flags);
1800 }
1801
1802 /* Update the hash table based on the current list of multicast
1803  * addresses we subscribe to.  Also, change the promiscuity of
1804  * the device based on the flags (this function is called
1805  * whenever dev->flags is changed */
1806 static void gfar_set_multi(struct net_device *dev)
1807 {
1808         struct dev_mc_list *mc_ptr;
1809         struct gfar_private *priv = netdev_priv(dev);
1810         struct gfar __iomem *regs = priv->regs;
1811         u32 tempval;
1812
1813         if(dev->flags & IFF_PROMISC) {
1814                 /* Set RCTRL to PROM */
1815                 tempval = gfar_read(&regs->rctrl);
1816                 tempval |= RCTRL_PROM;
1817                 gfar_write(&regs->rctrl, tempval);
1818         } else {
1819                 /* Set RCTRL to not PROM */
1820                 tempval = gfar_read(&regs->rctrl);
1821                 tempval &= ~(RCTRL_PROM);
1822                 gfar_write(&regs->rctrl, tempval);
1823         }
1824
1825         if(dev->flags & IFF_ALLMULTI) {
1826                 /* Set the hash to rx all multicast frames */
1827                 gfar_write(&regs->igaddr0, 0xffffffff);
1828                 gfar_write(&regs->igaddr1, 0xffffffff);
1829                 gfar_write(&regs->igaddr2, 0xffffffff);
1830                 gfar_write(&regs->igaddr3, 0xffffffff);
1831                 gfar_write(&regs->igaddr4, 0xffffffff);
1832                 gfar_write(&regs->igaddr5, 0xffffffff);
1833                 gfar_write(&regs->igaddr6, 0xffffffff);
1834                 gfar_write(&regs->igaddr7, 0xffffffff);
1835                 gfar_write(&regs->gaddr0, 0xffffffff);
1836                 gfar_write(&regs->gaddr1, 0xffffffff);
1837                 gfar_write(&regs->gaddr2, 0xffffffff);
1838                 gfar_write(&regs->gaddr3, 0xffffffff);
1839                 gfar_write(&regs->gaddr4, 0xffffffff);
1840                 gfar_write(&regs->gaddr5, 0xffffffff);
1841                 gfar_write(&regs->gaddr6, 0xffffffff);
1842                 gfar_write(&regs->gaddr7, 0xffffffff);
1843         } else {
1844                 int em_num;
1845                 int idx;
1846
1847                 /* zero out the hash */
1848                 gfar_write(&regs->igaddr0, 0x0);
1849                 gfar_write(&regs->igaddr1, 0x0);
1850                 gfar_write(&regs->igaddr2, 0x0);
1851                 gfar_write(&regs->igaddr3, 0x0);
1852                 gfar_write(&regs->igaddr4, 0x0);
1853                 gfar_write(&regs->igaddr5, 0x0);
1854                 gfar_write(&regs->igaddr6, 0x0);
1855                 gfar_write(&regs->igaddr7, 0x0);
1856                 gfar_write(&regs->gaddr0, 0x0);
1857                 gfar_write(&regs->gaddr1, 0x0);
1858                 gfar_write(&regs->gaddr2, 0x0);
1859                 gfar_write(&regs->gaddr3, 0x0);
1860                 gfar_write(&regs->gaddr4, 0x0);
1861                 gfar_write(&regs->gaddr5, 0x0);
1862                 gfar_write(&regs->gaddr6, 0x0);
1863                 gfar_write(&regs->gaddr7, 0x0);
1864
1865                 /* If we have extended hash tables, we need to
1866                  * clear the exact match registers to prepare for
1867                  * setting them */
1868                 if (priv->extended_hash) {
1869                         em_num = GFAR_EM_NUM + 1;
1870                         gfar_clear_exact_match(dev);
1871                         idx = 1;
1872                 } else {
1873                         idx = 0;
1874                         em_num = 0;
1875                 }
1876
1877                 if(dev->mc_count == 0)
1878                         return;
1879
1880                 /* Parse the list, and set the appropriate bits */
1881                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1882                         if (idx < em_num) {
1883                                 gfar_set_mac_for_addr(dev, idx,
1884                                                 mc_ptr->dmi_addr);
1885                                 idx++;
1886                         } else
1887                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1888                 }
1889         }
1890
1891         return;
1892 }
1893
1894
1895 /* Clears each of the exact match registers to zero, so they
1896  * don't interfere with normal reception */
1897 static void gfar_clear_exact_match(struct net_device *dev)
1898 {
1899         int idx;
1900         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1901
1902         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1903                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1904 }
1905
1906 /* Set the appropriate hash bit for the given addr */
1907 /* The algorithm works like so:
1908  * 1) Take the Destination Address (ie the multicast address), and
1909  * do a CRC on it (little endian), and reverse the bits of the
1910  * result.
1911  * 2) Use the 8 most significant bits as a hash into a 256-entry
1912  * table.  The table is controlled through 8 32-bit registers:
1913  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1914  * gaddr7.  This means that the 3 most significant bits in the
1915  * hash index which gaddr register to use, and the 5 other bits
1916  * indicate which bit (assuming an IBM numbering scheme, which
1917  * for PowerPC (tm) is usually the case) in the register holds
1918  * the entry. */
1919 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1920 {
1921         u32 tempval;
1922         struct gfar_private *priv = netdev_priv(dev);
1923         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1924         int width = priv->hash_width;
1925         u8 whichbit = (result >> (32 - width)) & 0x1f;
1926         u8 whichreg = result >> (32 - width + 5);
1927         u32 value = (1 << (31-whichbit));
1928
1929         tempval = gfar_read(priv->hash_regs[whichreg]);
1930         tempval |= value;
1931         gfar_write(priv->hash_regs[whichreg], tempval);
1932
1933         return;
1934 }
1935
1936
1937 /* There are multiple MAC Address register pairs on some controllers
1938  * This function sets the numth pair to a given address
1939  */
1940 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1941 {
1942         struct gfar_private *priv = netdev_priv(dev);
1943         int idx;
1944         char tmpbuf[MAC_ADDR_LEN];
1945         u32 tempval;
1946         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1947
1948         macptr += num*2;
1949
1950         /* Now copy it into the mac registers backwards, cuz */
1951         /* little endian is silly */
1952         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1953                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1954
1955         gfar_write(macptr, *((u32 *) (tmpbuf)));
1956
1957         tempval = *((u32 *) (tmpbuf + 4));
1958
1959         gfar_write(macptr+1, tempval);
1960 }
1961
1962 /* GFAR error interrupt handler */
1963 static irqreturn_t gfar_error(int irq, void *dev_id)
1964 {
1965         struct net_device *dev = dev_id;
1966         struct gfar_private *priv = netdev_priv(dev);
1967
1968         /* Save ievent for future reference */
1969         u32 events = gfar_read(&priv->regs->ievent);
1970
1971         /* Clear IEVENT */
1972         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1973
1974         /* Hmm... */
1975         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1976                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1977                        dev->name, events, gfar_read(&priv->regs->imask));
1978
1979         /* Update the error counters */
1980         if (events & IEVENT_TXE) {
1981                 dev->stats.tx_errors++;
1982
1983                 if (events & IEVENT_LC)
1984                         dev->stats.tx_window_errors++;
1985                 if (events & IEVENT_CRL)
1986                         dev->stats.tx_aborted_errors++;
1987                 if (events & IEVENT_XFUN) {
1988                         if (netif_msg_tx_err(priv))
1989                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1990                                        "packet dropped.\n", dev->name);
1991                         dev->stats.tx_dropped++;
1992                         priv->extra_stats.tx_underrun++;
1993
1994                         /* Reactivate the Tx Queues */
1995                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1996                 }
1997                 if (netif_msg_tx_err(priv))
1998                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1999         }
2000         if (events & IEVENT_BSY) {
2001                 dev->stats.rx_errors++;
2002                 priv->extra_stats.rx_bsy++;
2003
2004                 gfar_receive(irq, dev_id);
2005
2006 #ifndef CONFIG_GFAR_NAPI
2007                 /* Clear the halt bit in RSTAT */
2008                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
2009 #endif
2010
2011                 if (netif_msg_rx_err(priv))
2012                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2013                                dev->name, gfar_read(&priv->regs->rstat));
2014         }
2015         if (events & IEVENT_BABR) {
2016                 dev->stats.rx_errors++;
2017                 priv->extra_stats.rx_babr++;
2018
2019                 if (netif_msg_rx_err(priv))
2020                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2021         }
2022         if (events & IEVENT_EBERR) {
2023                 priv->extra_stats.eberr++;
2024                 if (netif_msg_rx_err(priv))
2025                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2026         }
2027         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2028                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2029
2030         if (events & IEVENT_BABT) {
2031                 priv->extra_stats.tx_babt++;
2032                 if (netif_msg_tx_err(priv))
2033                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2034         }
2035         return IRQ_HANDLED;
2036 }
2037
2038 /* work with hotplug and coldplug */
2039 MODULE_ALIAS("platform:fsl-gianfar");
2040
2041 /* Structure for a device driver */
2042 static struct platform_driver gfar_driver = {
2043         .probe = gfar_probe,
2044         .remove = gfar_remove,
2045         .driver = {
2046                 .name = "fsl-gianfar",
2047                 .owner = THIS_MODULE,
2048         },
2049 };
2050
2051 static int __init gfar_init(void)
2052 {
2053         int err = gfar_mdio_init();
2054
2055         if (err)
2056                 return err;
2057
2058         err = platform_driver_register(&gfar_driver);
2059
2060         if (err)
2061                 gfar_mdio_exit();
2062
2063         return err;
2064 }
2065
2066 static void __exit gfar_exit(void)
2067 {
2068         platform_driver_unregister(&gfar_driver);
2069         gfar_mdio_exit();
2070 }
2071
2072 module_init(gfar_init);
2073 module_exit(gfar_exit);
2074