[PATCH] gianfar: Fix sparse warnings
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
13  *
14  * This program is free software; you can redistribute  it and/or modify it
15  * under  the terms of  the GNU General  Public License as published by the
16  * Free Software Foundation;  either version 2 of the  License, or (at your
17  * option) any later version.
18  *
19  *  Gianfar:  AKA Lambda Draconis, "Dragon"
20  *  RA 11 31 24.2
21  *  Dec +69 19 52
22  *  V 3.84
23  *  B-V +1.62
24  *
25  *  Theory of operation
26  *
27  *  The driver is initialized through platform_device.  Structures which
28  *  define the configuration needed by the board are defined in a
29  *  board structure in arch/ppc/platforms (though I do not
30  *  discount the possibility that other architectures could one
31  *  day be supported.
32  *
33  *  The Gianfar Ethernet Controller uses a ring of buffer
34  *  descriptors.  The beginning is indicated by a register
35  *  pointing to the physical address of the start of the ring.
36  *  The end is determined by a "wrap" bit being set in the
37  *  last descriptor of the ring.
38  *
39  *  When a packet is received, the RXF bit in the
40  *  IEVENT register is set, triggering an interrupt when the
41  *  corresponding bit in the IMASK register is also set (if
42  *  interrupt coalescing is active, then the interrupt may not
43  *  happen immediately, but will wait until either a set number
44  *  of frames or amount of time have passed).  In NAPI, the
45  *  interrupt handler will signal there is work to be done, and
46  *  exit.  Without NAPI, the packet(s) will be handled
47  *  immediately.  Both methods will start at the last known empty
48  *  descriptor, and process every subsequent descriptor until there
49  *  are none left with data (NAPI will stop after a set number of
50  *  packets to give time to other tasks, but will eventually
51  *  process all the packets).  The data arrives inside a
52  *  pre-allocated skb, and so after the skb is passed up to the
53  *  stack, a new skb must be allocated, and the address field in
54  *  the buffer descriptor must be updated to indicate this new
55  *  skb.
56  *
57  *  When the kernel requests that a packet be transmitted, the
58  *  driver starts where it left off last time, and points the
59  *  descriptor at the buffer which was passed in.  The driver
60  *  then informs the DMA engine that there are packets ready to
61  *  be transmitted.  Once the controller is finished transmitting
62  *  the packet, an interrupt may be triggered (under the same
63  *  conditions as for reception, but depending on the TXF bit).
64  *  The driver then cleans up the buffer.
65  */
66
67 #include <linux/config.h>
68 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/string.h>
71 #include <linux/errno.h>
72 #include <linux/unistd.h>
73 #include <linux/slab.h>
74 #include <linux/interrupt.h>
75 #include <linux/init.h>
76 #include <linux/delay.h>
77 #include <linux/netdevice.h>
78 #include <linux/etherdevice.h>
79 #include <linux/skbuff.h>
80 #include <linux/if_vlan.h>
81 #include <linux/spinlock.h>
82 #include <linux/mm.h>
83 #include <linux/platform_device.h>
84 #include <linux/ip.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
87 #include <linux/in.h>
88
89 #include <asm/io.h>
90 #include <asm/irq.h>
91 #include <asm/uaccess.h>
92 #include <linux/module.h>
93 #include <linux/dma-mapping.h>
94 #include <linux/crc32.h>
95 #include <linux/mii.h>
96 #include <linux/phy.h>
97
98 #include "gianfar.h"
99 #include "gianfar_mii.h"
100
101 #define TX_TIMEOUT      (1*HZ)
102 #define SKB_ALLOC_TIMEOUT 1000000
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
105
106 #ifdef CONFIG_GFAR_NAPI
107 #define RECEIVE(x) netif_receive_skb(x)
108 #else
109 #define RECEIVE(x) netif_rx(x)
110 #endif
111
112 const char gfar_driver_name[] = "Gianfar Ethernet";
113 const char gfar_driver_version[] = "1.3";
114
115 static int gfar_enet_open(struct net_device *dev);
116 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
120 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
126 static void adjust_link(struct net_device *dev);
127 static void init_registers(struct net_device *dev);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *pdev);
130 static int gfar_remove(struct platform_device *pdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 #ifdef CONFIG_GFAR_NAPI
135 static int gfar_poll(struct net_device *dev, int *budget);
136 #endif
137 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
139 static void gfar_vlan_rx_register(struct net_device *netdev,
140                                 struct vlan_group *grp);
141 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
142 void gfar_halt(struct net_device *dev);
143 void gfar_start(struct net_device *dev);
144 static void gfar_clear_exact_match(struct net_device *dev);
145 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
146
147 extern struct ethtool_ops gfar_ethtool_ops;
148
149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151 MODULE_LICENSE("GPL");
152
153 /* Returns 1 if incoming frames use an FCB */
154 static inline int gfar_uses_fcb(struct gfar_private *priv)
155 {
156         return (priv->vlan_enable || priv->rx_csum_enable);
157 }
158
159 /* Set up the ethernet device structure, private data,
160  * and anything else we need before we start */
161 static int gfar_probe(struct platform_device *pdev)
162 {
163         u32 tempval;
164         struct net_device *dev = NULL;
165         struct gfar_private *priv = NULL;
166         struct gianfar_platform_data *einfo;
167         struct resource *r;
168         int idx;
169         int err = 0;
170
171         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
172
173         if (NULL == einfo) {
174                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
175                        pdev->id);
176
177                 return -ENODEV;
178         }
179
180         /* Create an ethernet device instance */
181         dev = alloc_etherdev(sizeof (*priv));
182
183         if (NULL == dev)
184                 return -ENOMEM;
185
186         priv = netdev_priv(dev);
187
188         /* Set the info in the priv to the current info */
189         priv->einfo = einfo;
190
191         /* fill out IRQ fields */
192         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
193                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
194                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
195                 priv->interruptError = platform_get_irq_byname(pdev, "error");
196         } else {
197                 priv->interruptTransmit = platform_get_irq(pdev, 0);
198         }
199
200         /* get a pointer to the register memory */
201         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202         priv->regs = ioremap(r->start, sizeof (struct gfar));
203
204         if (NULL == priv->regs) {
205                 err = -ENOMEM;
206                 goto regs_fail;
207         }
208
209         spin_lock_init(&priv->lock);
210
211         platform_set_drvdata(pdev, dev);
212
213         /* Stop the DMA engine now, in case it was running before */
214         /* (The firmware could have used it, and left it running). */
215         /* To do this, we write Graceful Receive Stop and Graceful */
216         /* Transmit Stop, and then wait until the corresponding bits */
217         /* in IEVENT indicate the stops have completed. */
218         tempval = gfar_read(&priv->regs->dmactrl);
219         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
220         gfar_write(&priv->regs->dmactrl, tempval);
221
222         tempval = gfar_read(&priv->regs->dmactrl);
223         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
224         gfar_write(&priv->regs->dmactrl, tempval);
225
226         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
227                 cpu_relax();
228
229         /* Reset MAC layer */
230         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
231
232         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
233         gfar_write(&priv->regs->maccfg1, tempval);
234
235         /* Initialize MACCFG2. */
236         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
237
238         /* Initialize ECNTRL */
239         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
240
241         /* Copy the station address into the dev structure, */
242         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
243
244         /* Set the dev->base_addr to the gfar reg region */
245         dev->base_addr = (unsigned long) (priv->regs);
246
247         SET_MODULE_OWNER(dev);
248         SET_NETDEV_DEV(dev, &pdev->dev);
249
250         /* Fill in the dev structure */
251         dev->open = gfar_enet_open;
252         dev->hard_start_xmit = gfar_start_xmit;
253         dev->tx_timeout = gfar_timeout;
254         dev->watchdog_timeo = TX_TIMEOUT;
255 #ifdef CONFIG_GFAR_NAPI
256         dev->poll = gfar_poll;
257         dev->weight = GFAR_DEV_WEIGHT;
258 #endif
259         dev->stop = gfar_close;
260         dev->get_stats = gfar_get_stats;
261         dev->change_mtu = gfar_change_mtu;
262         dev->mtu = 1500;
263         dev->set_multicast_list = gfar_set_multi;
264
265         dev->ethtool_ops = &gfar_ethtool_ops;
266
267         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
268                 priv->rx_csum_enable = 1;
269                 dev->features |= NETIF_F_IP_CSUM;
270         } else
271                 priv->rx_csum_enable = 0;
272
273         priv->vlgrp = NULL;
274
275         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
276                 dev->vlan_rx_register = gfar_vlan_rx_register;
277                 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
278
279                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
280
281                 priv->vlan_enable = 1;
282         }
283
284         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
285                 priv->extended_hash = 1;
286                 priv->hash_width = 9;
287
288                 priv->hash_regs[0] = &priv->regs->igaddr0;
289                 priv->hash_regs[1] = &priv->regs->igaddr1;
290                 priv->hash_regs[2] = &priv->regs->igaddr2;
291                 priv->hash_regs[3] = &priv->regs->igaddr3;
292                 priv->hash_regs[4] = &priv->regs->igaddr4;
293                 priv->hash_regs[5] = &priv->regs->igaddr5;
294                 priv->hash_regs[6] = &priv->regs->igaddr6;
295                 priv->hash_regs[7] = &priv->regs->igaddr7;
296                 priv->hash_regs[8] = &priv->regs->gaddr0;
297                 priv->hash_regs[9] = &priv->regs->gaddr1;
298                 priv->hash_regs[10] = &priv->regs->gaddr2;
299                 priv->hash_regs[11] = &priv->regs->gaddr3;
300                 priv->hash_regs[12] = &priv->regs->gaddr4;
301                 priv->hash_regs[13] = &priv->regs->gaddr5;
302                 priv->hash_regs[14] = &priv->regs->gaddr6;
303                 priv->hash_regs[15] = &priv->regs->gaddr7;
304
305         } else {
306                 priv->extended_hash = 0;
307                 priv->hash_width = 8;
308
309                 priv->hash_regs[0] = &priv->regs->gaddr0;
310                 priv->hash_regs[1] = &priv->regs->gaddr1;
311                 priv->hash_regs[2] = &priv->regs->gaddr2;
312                 priv->hash_regs[3] = &priv->regs->gaddr3;
313                 priv->hash_regs[4] = &priv->regs->gaddr4;
314                 priv->hash_regs[5] = &priv->regs->gaddr5;
315                 priv->hash_regs[6] = &priv->regs->gaddr6;
316                 priv->hash_regs[7] = &priv->regs->gaddr7;
317         }
318
319         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
320                 priv->padding = DEFAULT_PADDING;
321         else
322                 priv->padding = 0;
323
324         if (dev->features & NETIF_F_IP_CSUM)
325                 dev->hard_header_len += GMAC_FCB_LEN;
326
327         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
328         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
329         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
330
331         priv->txcoalescing = DEFAULT_TX_COALESCE;
332         priv->txcount = DEFAULT_TXCOUNT;
333         priv->txtime = DEFAULT_TXTIME;
334         priv->rxcoalescing = DEFAULT_RX_COALESCE;
335         priv->rxcount = DEFAULT_RXCOUNT;
336         priv->rxtime = DEFAULT_RXTIME;
337
338         /* Enable most messages by default */
339         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
340
341         err = register_netdev(dev);
342
343         if (err) {
344                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
345                                 dev->name);
346                 goto register_fail;
347         }
348
349         /* Create all the sysfs files */
350         gfar_init_sysfs(dev);
351
352         /* Print out the device info */
353         printk(KERN_INFO DEVICE_NAME, dev->name);
354         for (idx = 0; idx < 6; idx++)
355                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
356         printk("\n");
357
358         /* Even more device info helps when determining which kernel */
359         /* provided which set of benchmarks. */
360 #ifdef CONFIG_GFAR_NAPI
361         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
362 #else
363         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
364 #endif
365         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
366                dev->name, priv->rx_ring_size, priv->tx_ring_size);
367
368         return 0;
369
370 register_fail:
371         iounmap(priv->regs);
372 regs_fail:
373         free_netdev(dev);
374         return err;
375 }
376
377 static int gfar_remove(struct platform_device *pdev)
378 {
379         struct net_device *dev = platform_get_drvdata(pdev);
380         struct gfar_private *priv = netdev_priv(dev);
381
382         platform_set_drvdata(pdev, NULL);
383
384         iounmap(priv->regs);
385         free_netdev(dev);
386
387         return 0;
388 }
389
390
391 /* Initializes driver's PHY state, and attaches to the PHY.
392  * Returns 0 on success.
393  */
394 static int init_phy(struct net_device *dev)
395 {
396         struct gfar_private *priv = netdev_priv(dev);
397         uint gigabit_support =
398                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
399                 SUPPORTED_1000baseT_Full : 0;
400         struct phy_device *phydev;
401         char phy_id[BUS_ID_SIZE];
402
403         priv->oldlink = 0;
404         priv->oldspeed = 0;
405         priv->oldduplex = -1;
406
407         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
408
409         phydev = phy_connect(dev, phy_id, &adjust_link, 0);
410
411         if (IS_ERR(phydev)) {
412                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
413                 return PTR_ERR(phydev);
414         }
415
416         /* Remove any features not supported by the controller */
417         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
418         phydev->advertising = phydev->supported;
419
420         priv->phydev = phydev;
421
422         return 0;
423 }
424
425 static void init_registers(struct net_device *dev)
426 {
427         struct gfar_private *priv = netdev_priv(dev);
428
429         /* Clear IEVENT */
430         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
431
432         /* Initialize IMASK */
433         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
434
435         /* Init hash registers to zero */
436         gfar_write(&priv->regs->igaddr0, 0);
437         gfar_write(&priv->regs->igaddr1, 0);
438         gfar_write(&priv->regs->igaddr2, 0);
439         gfar_write(&priv->regs->igaddr3, 0);
440         gfar_write(&priv->regs->igaddr4, 0);
441         gfar_write(&priv->regs->igaddr5, 0);
442         gfar_write(&priv->regs->igaddr6, 0);
443         gfar_write(&priv->regs->igaddr7, 0);
444
445         gfar_write(&priv->regs->gaddr0, 0);
446         gfar_write(&priv->regs->gaddr1, 0);
447         gfar_write(&priv->regs->gaddr2, 0);
448         gfar_write(&priv->regs->gaddr3, 0);
449         gfar_write(&priv->regs->gaddr4, 0);
450         gfar_write(&priv->regs->gaddr5, 0);
451         gfar_write(&priv->regs->gaddr6, 0);
452         gfar_write(&priv->regs->gaddr7, 0);
453
454         /* Zero out the rmon mib registers if it has them */
455         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
456                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
457
458                 /* Mask off the CAM interrupts */
459                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
460                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
461         }
462
463         /* Initialize the max receive buffer length */
464         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
465
466         /* Initialize the Minimum Frame Length Register */
467         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
468
469         /* Assign the TBI an address which won't conflict with the PHYs */
470         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
471 }
472
473
474 /* Halt the receive and transmit queues */
475 void gfar_halt(struct net_device *dev)
476 {
477         struct gfar_private *priv = netdev_priv(dev);
478         struct gfar __iomem *regs = priv->regs;
479         u32 tempval;
480
481         /* Mask all interrupts */
482         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
483
484         /* Clear all interrupts */
485         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
486
487         /* Stop the DMA, and wait for it to stop */
488         tempval = gfar_read(&priv->regs->dmactrl);
489         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
490             != (DMACTRL_GRS | DMACTRL_GTS)) {
491                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
492                 gfar_write(&priv->regs->dmactrl, tempval);
493
494                 while (!(gfar_read(&priv->regs->ievent) &
495                          (IEVENT_GRSC | IEVENT_GTSC)))
496                         cpu_relax();
497         }
498
499         /* Disable Rx and Tx */
500         tempval = gfar_read(&regs->maccfg1);
501         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
502         gfar_write(&regs->maccfg1, tempval);
503 }
504
505 void stop_gfar(struct net_device *dev)
506 {
507         struct gfar_private *priv = netdev_priv(dev);
508         struct gfar __iomem *regs = priv->regs;
509         unsigned long flags;
510
511         phy_stop(priv->phydev);
512
513         /* Lock it down */
514         spin_lock_irqsave(&priv->lock, flags);
515
516         gfar_halt(dev);
517
518         spin_unlock_irqrestore(&priv->lock, flags);
519
520         /* Free the IRQs */
521         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
522                 free_irq(priv->interruptError, dev);
523                 free_irq(priv->interruptTransmit, dev);
524                 free_irq(priv->interruptReceive, dev);
525         } else {
526                 free_irq(priv->interruptTransmit, dev);
527         }
528
529         free_skb_resources(priv);
530
531         dma_free_coherent(NULL,
532                         sizeof(struct txbd8)*priv->tx_ring_size
533                         + sizeof(struct rxbd8)*priv->rx_ring_size,
534                         priv->tx_bd_base,
535                         gfar_read(&regs->tbase0));
536 }
537
538 /* If there are any tx skbs or rx skbs still around, free them.
539  * Then free tx_skbuff and rx_skbuff */
540 static void free_skb_resources(struct gfar_private *priv)
541 {
542         struct rxbd8 *rxbdp;
543         struct txbd8 *txbdp;
544         int i;
545
546         /* Go through all the buffer descriptors and free their data buffers */
547         txbdp = priv->tx_bd_base;
548
549         for (i = 0; i < priv->tx_ring_size; i++) {
550
551                 if (priv->tx_skbuff[i]) {
552                         dma_unmap_single(NULL, txbdp->bufPtr,
553                                         txbdp->length,
554                                         DMA_TO_DEVICE);
555                         dev_kfree_skb_any(priv->tx_skbuff[i]);
556                         priv->tx_skbuff[i] = NULL;
557                 }
558         }
559
560         kfree(priv->tx_skbuff);
561
562         rxbdp = priv->rx_bd_base;
563
564         /* rx_skbuff is not guaranteed to be allocated, so only
565          * free it and its contents if it is allocated */
566         if(priv->rx_skbuff != NULL) {
567                 for (i = 0; i < priv->rx_ring_size; i++) {
568                         if (priv->rx_skbuff[i]) {
569                                 dma_unmap_single(NULL, rxbdp->bufPtr,
570                                                 priv->rx_buffer_size,
571                                                 DMA_FROM_DEVICE);
572
573                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
574                                 priv->rx_skbuff[i] = NULL;
575                         }
576
577                         rxbdp->status = 0;
578                         rxbdp->length = 0;
579                         rxbdp->bufPtr = 0;
580
581                         rxbdp++;
582                 }
583
584                 kfree(priv->rx_skbuff);
585         }
586 }
587
588 void gfar_start(struct net_device *dev)
589 {
590         struct gfar_private *priv = netdev_priv(dev);
591         struct gfar __iomem *regs = priv->regs;
592         u32 tempval;
593
594         /* Enable Rx and Tx in MACCFG1 */
595         tempval = gfar_read(&regs->maccfg1);
596         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
597         gfar_write(&regs->maccfg1, tempval);
598
599         /* Initialize DMACTRL to have WWR and WOP */
600         tempval = gfar_read(&priv->regs->dmactrl);
601         tempval |= DMACTRL_INIT_SETTINGS;
602         gfar_write(&priv->regs->dmactrl, tempval);
603
604         /* Clear THLT, so that the DMA starts polling now */
605         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
606
607         /* Make sure we aren't stopped */
608         tempval = gfar_read(&priv->regs->dmactrl);
609         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
610         gfar_write(&priv->regs->dmactrl, tempval);
611
612         /* Unmask the interrupts we look for */
613         gfar_write(&regs->imask, IMASK_DEFAULT);
614 }
615
616 /* Bring the controller up and running */
617 int startup_gfar(struct net_device *dev)
618 {
619         struct txbd8 *txbdp;
620         struct rxbd8 *rxbdp;
621         dma_addr_t addr;
622         unsigned long vaddr;
623         int i;
624         struct gfar_private *priv = netdev_priv(dev);
625         struct gfar __iomem *regs = priv->regs;
626         int err = 0;
627         u32 rctrl = 0;
628         u32 attrs = 0;
629
630         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
631
632         /* Allocate memory for the buffer descriptors */
633         vaddr = (unsigned long) dma_alloc_coherent(NULL,
634                         sizeof (struct txbd8) * priv->tx_ring_size +
635                         sizeof (struct rxbd8) * priv->rx_ring_size,
636                         &addr, GFP_KERNEL);
637
638         if (vaddr == 0) {
639                 if (netif_msg_ifup(priv))
640                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
641                                         dev->name);
642                 return -ENOMEM;
643         }
644
645         priv->tx_bd_base = (struct txbd8 *) vaddr;
646
647         /* enet DMA only understands physical addresses */
648         gfar_write(&regs->tbase0, addr);
649
650         /* Start the rx descriptor ring where the tx ring leaves off */
651         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
652         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
653         priv->rx_bd_base = (struct rxbd8 *) vaddr;
654         gfar_write(&regs->rbase0, addr);
655
656         /* Setup the skbuff rings */
657         priv->tx_skbuff =
658             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
659                                         priv->tx_ring_size, GFP_KERNEL);
660
661         if (NULL == priv->tx_skbuff) {
662                 if (netif_msg_ifup(priv))
663                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
664                                         dev->name);
665                 err = -ENOMEM;
666                 goto tx_skb_fail;
667         }
668
669         for (i = 0; i < priv->tx_ring_size; i++)
670                 priv->tx_skbuff[i] = NULL;
671
672         priv->rx_skbuff =
673             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
674                                         priv->rx_ring_size, GFP_KERNEL);
675
676         if (NULL == priv->rx_skbuff) {
677                 if (netif_msg_ifup(priv))
678                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
679                                         dev->name);
680                 err = -ENOMEM;
681                 goto rx_skb_fail;
682         }
683
684         for (i = 0; i < priv->rx_ring_size; i++)
685                 priv->rx_skbuff[i] = NULL;
686
687         /* Initialize some variables in our dev structure */
688         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
689         priv->cur_rx = priv->rx_bd_base;
690         priv->skb_curtx = priv->skb_dirtytx = 0;
691         priv->skb_currx = 0;
692
693         /* Initialize Transmit Descriptor Ring */
694         txbdp = priv->tx_bd_base;
695         for (i = 0; i < priv->tx_ring_size; i++) {
696                 txbdp->status = 0;
697                 txbdp->length = 0;
698                 txbdp->bufPtr = 0;
699                 txbdp++;
700         }
701
702         /* Set the last descriptor in the ring to indicate wrap */
703         txbdp--;
704         txbdp->status |= TXBD_WRAP;
705
706         rxbdp = priv->rx_bd_base;
707         for (i = 0; i < priv->rx_ring_size; i++) {
708                 struct sk_buff *skb = NULL;
709
710                 rxbdp->status = 0;
711
712                 skb = gfar_new_skb(dev, rxbdp);
713
714                 priv->rx_skbuff[i] = skb;
715
716                 rxbdp++;
717         }
718
719         /* Set the last descriptor in the ring to wrap */
720         rxbdp--;
721         rxbdp->status |= RXBD_WRAP;
722
723         /* If the device has multiple interrupts, register for
724          * them.  Otherwise, only register for the one */
725         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
726                 /* Install our interrupt handlers for Error,
727                  * Transmit, and Receive */
728                 if (request_irq(priv->interruptError, gfar_error,
729                                 0, "enet_error", dev) < 0) {
730                         if (netif_msg_intr(priv))
731                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
732                                         dev->name, priv->interruptError);
733
734                         err = -1;
735                         goto err_irq_fail;
736                 }
737
738                 if (request_irq(priv->interruptTransmit, gfar_transmit,
739                                 0, "enet_tx", dev) < 0) {
740                         if (netif_msg_intr(priv))
741                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
742                                         dev->name, priv->interruptTransmit);
743
744                         err = -1;
745
746                         goto tx_irq_fail;
747                 }
748
749                 if (request_irq(priv->interruptReceive, gfar_receive,
750                                 0, "enet_rx", dev) < 0) {
751                         if (netif_msg_intr(priv))
752                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
753                                                 dev->name, priv->interruptReceive);
754
755                         err = -1;
756                         goto rx_irq_fail;
757                 }
758         } else {
759                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
760                                 0, "gfar_interrupt", dev) < 0) {
761                         if (netif_msg_intr(priv))
762                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
763                                         dev->name, priv->interruptError);
764
765                         err = -1;
766                         goto err_irq_fail;
767                 }
768         }
769
770         phy_start(priv->phydev);
771
772         /* Configure the coalescing support */
773         if (priv->txcoalescing)
774                 gfar_write(&regs->txic,
775                            mk_ic_value(priv->txcount, priv->txtime));
776         else
777                 gfar_write(&regs->txic, 0);
778
779         if (priv->rxcoalescing)
780                 gfar_write(&regs->rxic,
781                            mk_ic_value(priv->rxcount, priv->rxtime));
782         else
783                 gfar_write(&regs->rxic, 0);
784
785         if (priv->rx_csum_enable)
786                 rctrl |= RCTRL_CHECKSUMMING;
787
788         if (priv->extended_hash) {
789                 rctrl |= RCTRL_EXTHASH;
790
791                 gfar_clear_exact_match(dev);
792                 rctrl |= RCTRL_EMEN;
793         }
794
795         if (priv->vlan_enable)
796                 rctrl |= RCTRL_VLAN;
797
798         if (priv->padding) {
799                 rctrl &= ~RCTRL_PAL_MASK;
800                 rctrl |= RCTRL_PADDING(priv->padding);
801         }
802
803         /* Init rctrl based on our settings */
804         gfar_write(&priv->regs->rctrl, rctrl);
805
806         if (dev->features & NETIF_F_IP_CSUM)
807                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
808
809         /* Set the extraction length and index */
810         attrs = ATTRELI_EL(priv->rx_stash_size) |
811                 ATTRELI_EI(priv->rx_stash_index);
812
813         gfar_write(&priv->regs->attreli, attrs);
814
815         /* Start with defaults, and add stashing or locking
816          * depending on the approprate variables */
817         attrs = ATTR_INIT_SETTINGS;
818
819         if (priv->bd_stash_en)
820                 attrs |= ATTR_BDSTASH;
821
822         if (priv->rx_stash_size != 0)
823                 attrs |= ATTR_BUFSTASH;
824
825         gfar_write(&priv->regs->attr, attrs);
826
827         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
828         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
829         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
830
831         /* Start the controller */
832         gfar_start(dev);
833
834         return 0;
835
836 rx_irq_fail:
837         free_irq(priv->interruptTransmit, dev);
838 tx_irq_fail:
839         free_irq(priv->interruptError, dev);
840 err_irq_fail:
841 rx_skb_fail:
842         free_skb_resources(priv);
843 tx_skb_fail:
844         dma_free_coherent(NULL,
845                         sizeof(struct txbd8)*priv->tx_ring_size
846                         + sizeof(struct rxbd8)*priv->rx_ring_size,
847                         priv->tx_bd_base,
848                         gfar_read(&regs->tbase0));
849
850         return err;
851 }
852
853 /* Called when something needs to use the ethernet device */
854 /* Returns 0 for success. */
855 static int gfar_enet_open(struct net_device *dev)
856 {
857         int err;
858
859         /* Initialize a bunch of registers */
860         init_registers(dev);
861
862         gfar_set_mac_address(dev);
863
864         err = init_phy(dev);
865
866         if(err)
867                 return err;
868
869         err = startup_gfar(dev);
870
871         netif_start_queue(dev);
872
873         return err;
874 }
875
876 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
877 {
878         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
879
880         memset(fcb, 0, GMAC_FCB_LEN);
881
882         return fcb;
883 }
884
885 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
886 {
887         u8 flags = 0;
888
889         /* If we're here, it's a IP packet with a TCP or UDP
890          * payload.  We set it to checksum, using a pseudo-header
891          * we provide
892          */
893         flags = TXFCB_DEFAULT;
894
895         /* Tell the controller what the protocol is */
896         /* And provide the already calculated phcs */
897         if (skb->nh.iph->protocol == IPPROTO_UDP) {
898                 flags |= TXFCB_UDP;
899                 fcb->phcs = skb->h.uh->check;
900         } else
901                 fcb->phcs = skb->h.th->check;
902
903         /* l3os is the distance between the start of the
904          * frame (skb->data) and the start of the IP hdr.
905          * l4os is the distance between the start of the
906          * l3 hdr and the l4 hdr */
907         fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
908         fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
909
910         fcb->flags = flags;
911 }
912
913 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
914 {
915         fcb->flags |= TXFCB_VLN;
916         fcb->vlctl = vlan_tx_tag_get(skb);
917 }
918
919 /* This is called by the kernel when a frame is ready for transmission. */
920 /* It is pointed to by the dev->hard_start_xmit function pointer */
921 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
922 {
923         struct gfar_private *priv = netdev_priv(dev);
924         struct txfcb *fcb = NULL;
925         struct txbd8 *txbdp;
926         u16 status;
927
928         /* Update transmit stats */
929         priv->stats.tx_bytes += skb->len;
930
931         /* Lock priv now */
932         spin_lock_irq(&priv->lock);
933
934         /* Point at the first free tx descriptor */
935         txbdp = priv->cur_tx;
936
937         /* Clear all but the WRAP status flags */
938         status = txbdp->status & TXBD_WRAP;
939
940         /* Set up checksumming */
941         if (likely((dev->features & NETIF_F_IP_CSUM)
942                         && (CHECKSUM_HW == skb->ip_summed))) {
943                 fcb = gfar_add_fcb(skb, txbdp);
944                 status |= TXBD_TOE;
945                 gfar_tx_checksum(skb, fcb);
946         }
947
948         if (priv->vlan_enable &&
949                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
950                 if (unlikely(NULL == fcb)) {
951                         fcb = gfar_add_fcb(skb, txbdp);
952                         status |= TXBD_TOE;
953                 }
954
955                 gfar_tx_vlan(skb, fcb);
956         }
957
958         /* Set buffer length and pointer */
959         txbdp->length = skb->len;
960         txbdp->bufPtr = dma_map_single(NULL, skb->data,
961                         skb->len, DMA_TO_DEVICE);
962
963         /* Save the skb pointer so we can free it later */
964         priv->tx_skbuff[priv->skb_curtx] = skb;
965
966         /* Update the current skb pointer (wrapping if this was the last) */
967         priv->skb_curtx =
968             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
969
970         /* Flag the BD as interrupt-causing */
971         status |= TXBD_INTERRUPT;
972
973         /* Flag the BD as ready to go, last in frame, and  */
974         /* in need of CRC */
975         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
976
977         dev->trans_start = jiffies;
978
979         txbdp->status = status;
980
981         /* If this was the last BD in the ring, the next one */
982         /* is at the beginning of the ring */
983         if (txbdp->status & TXBD_WRAP)
984                 txbdp = priv->tx_bd_base;
985         else
986                 txbdp++;
987
988         /* If the next BD still needs to be cleaned up, then the bds
989            are full.  We need to tell the kernel to stop sending us stuff. */
990         if (txbdp == priv->dirty_tx) {
991                 netif_stop_queue(dev);
992
993                 priv->stats.tx_fifo_errors++;
994         }
995
996         /* Update the current txbd to the next one */
997         priv->cur_tx = txbdp;
998
999         /* Tell the DMA to go go go */
1000         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1001
1002         /* Unlock priv */
1003         spin_unlock_irq(&priv->lock);
1004
1005         return 0;
1006 }
1007
1008 /* Stops the kernel queue, and halts the controller */
1009 static int gfar_close(struct net_device *dev)
1010 {
1011         struct gfar_private *priv = netdev_priv(dev);
1012         stop_gfar(dev);
1013
1014         /* Disconnect from the PHY */
1015         phy_disconnect(priv->phydev);
1016         priv->phydev = NULL;
1017
1018         netif_stop_queue(dev);
1019
1020         return 0;
1021 }
1022
1023 /* returns a net_device_stats structure pointer */
1024 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1025 {
1026         struct gfar_private *priv = netdev_priv(dev);
1027
1028         return &(priv->stats);
1029 }
1030
1031 /* Changes the mac address if the controller is not running. */
1032 int gfar_set_mac_address(struct net_device *dev)
1033 {
1034         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1035
1036         return 0;
1037 }
1038
1039
1040 /* Enables and disables VLAN insertion/extraction */
1041 static void gfar_vlan_rx_register(struct net_device *dev,
1042                 struct vlan_group *grp)
1043 {
1044         struct gfar_private *priv = netdev_priv(dev);
1045         unsigned long flags;
1046         u32 tempval;
1047
1048         spin_lock_irqsave(&priv->lock, flags);
1049
1050         priv->vlgrp = grp;
1051
1052         if (grp) {
1053                 /* Enable VLAN tag insertion */
1054                 tempval = gfar_read(&priv->regs->tctrl);
1055                 tempval |= TCTRL_VLINS;
1056
1057                 gfar_write(&priv->regs->tctrl, tempval);
1058                 
1059                 /* Enable VLAN tag extraction */
1060                 tempval = gfar_read(&priv->regs->rctrl);
1061                 tempval |= RCTRL_VLEX;
1062                 gfar_write(&priv->regs->rctrl, tempval);
1063         } else {
1064                 /* Disable VLAN tag insertion */
1065                 tempval = gfar_read(&priv->regs->tctrl);
1066                 tempval &= ~TCTRL_VLINS;
1067                 gfar_write(&priv->regs->tctrl, tempval);
1068
1069                 /* Disable VLAN tag extraction */
1070                 tempval = gfar_read(&priv->regs->rctrl);
1071                 tempval &= ~RCTRL_VLEX;
1072                 gfar_write(&priv->regs->rctrl, tempval);
1073         }
1074
1075         spin_unlock_irqrestore(&priv->lock, flags);
1076 }
1077
1078
1079 static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1080 {
1081         struct gfar_private *priv = netdev_priv(dev);
1082         unsigned long flags;
1083
1084         spin_lock_irqsave(&priv->lock, flags);
1085
1086         if (priv->vlgrp)
1087                 priv->vlgrp->vlan_devices[vid] = NULL;
1088
1089         spin_unlock_irqrestore(&priv->lock, flags);
1090 }
1091
1092
1093 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1094 {
1095         int tempsize, tempval;
1096         struct gfar_private *priv = netdev_priv(dev);
1097         int oldsize = priv->rx_buffer_size;
1098         int frame_size = new_mtu + ETH_HLEN;
1099
1100         if (priv->vlan_enable)
1101                 frame_size += VLAN_ETH_HLEN;
1102
1103         if (gfar_uses_fcb(priv))
1104                 frame_size += GMAC_FCB_LEN;
1105
1106         frame_size += priv->padding;
1107
1108         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1109                 if (netif_msg_drv(priv))
1110                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1111                                         dev->name);
1112                 return -EINVAL;
1113         }
1114
1115         tempsize =
1116             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1117             INCREMENTAL_BUFFER_SIZE;
1118
1119         /* Only stop and start the controller if it isn't already
1120          * stopped, and we changed something */
1121         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1122                 stop_gfar(dev);
1123
1124         priv->rx_buffer_size = tempsize;
1125
1126         dev->mtu = new_mtu;
1127
1128         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1129         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1130
1131         /* If the mtu is larger than the max size for standard
1132          * ethernet frames (ie, a jumbo frame), then set maccfg2
1133          * to allow huge frames, and to check the length */
1134         tempval = gfar_read(&priv->regs->maccfg2);
1135
1136         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1137                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1138         else
1139                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1140
1141         gfar_write(&priv->regs->maccfg2, tempval);
1142
1143         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1144                 startup_gfar(dev);
1145
1146         return 0;
1147 }
1148
1149 /* gfar_timeout gets called when a packet has not been
1150  * transmitted after a set amount of time.
1151  * For now, assume that clearing out all the structures, and
1152  * starting over will fix the problem. */
1153 static void gfar_timeout(struct net_device *dev)
1154 {
1155         struct gfar_private *priv = netdev_priv(dev);
1156
1157         priv->stats.tx_errors++;
1158
1159         if (dev->flags & IFF_UP) {
1160                 stop_gfar(dev);
1161                 startup_gfar(dev);
1162         }
1163
1164         netif_schedule(dev);
1165 }
1166
1167 /* Interrupt Handler for Transmit complete */
1168 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs)
1169 {
1170         struct net_device *dev = (struct net_device *) dev_id;
1171         struct gfar_private *priv = netdev_priv(dev);
1172         struct txbd8 *bdp;
1173
1174         /* Clear IEVENT */
1175         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1176
1177         /* Lock priv */
1178         spin_lock(&priv->lock);
1179         bdp = priv->dirty_tx;
1180         while ((bdp->status & TXBD_READY) == 0) {
1181                 /* If dirty_tx and cur_tx are the same, then either the */
1182                 /* ring is empty or full now (it could only be full in the beginning, */
1183                 /* obviously).  If it is empty, we are done. */
1184                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1185                         break;
1186
1187                 priv->stats.tx_packets++;
1188
1189                 /* Deferred means some collisions occurred during transmit, */
1190                 /* but we eventually sent the packet. */
1191                 if (bdp->status & TXBD_DEF)
1192                         priv->stats.collisions++;
1193
1194                 /* Free the sk buffer associated with this TxBD */
1195                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1196                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1197                 priv->skb_dirtytx =
1198                     (priv->skb_dirtytx +
1199                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1200
1201                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1202                 if (bdp->status & TXBD_WRAP)
1203                         bdp = priv->tx_bd_base;
1204                 else
1205                         bdp++;
1206
1207                 /* Move dirty_tx to be the next bd */
1208                 priv->dirty_tx = bdp;
1209
1210                 /* We freed a buffer, so now we can restart transmission */
1211                 if (netif_queue_stopped(dev))
1212                         netif_wake_queue(dev);
1213         } /* while ((bdp->status & TXBD_READY) == 0) */
1214
1215         /* If we are coalescing the interrupts, reset the timer */
1216         /* Otherwise, clear it */
1217         if (priv->txcoalescing)
1218                 gfar_write(&priv->regs->txic,
1219                            mk_ic_value(priv->txcount, priv->txtime));
1220         else
1221                 gfar_write(&priv->regs->txic, 0);
1222
1223         spin_unlock(&priv->lock);
1224
1225         return IRQ_HANDLED;
1226 }
1227
1228 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1229 {
1230         unsigned int alignamount;
1231         struct gfar_private *priv = netdev_priv(dev);
1232         struct sk_buff *skb = NULL;
1233         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1234
1235         /* We have to allocate the skb, so keep trying till we succeed */
1236         while ((!skb) && timeout--)
1237                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1238
1239         if (NULL == skb)
1240                 return NULL;
1241
1242         alignamount = RXBUF_ALIGNMENT -
1243                 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1244
1245         /* We need the data buffer to be aligned properly.  We will reserve
1246          * as many bytes as needed to align the data properly
1247          */
1248         skb_reserve(skb, alignamount);
1249
1250         skb->dev = dev;
1251
1252         bdp->bufPtr = dma_map_single(NULL, skb->data,
1253                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1254
1255         bdp->length = 0;
1256
1257         /* Mark the buffer empty */
1258         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1259
1260         return skb;
1261 }
1262
1263 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1264 {
1265         struct net_device_stats *stats = &priv->stats;
1266         struct gfar_extra_stats *estats = &priv->extra_stats;
1267
1268         /* If the packet was truncated, none of the other errors
1269          * matter */
1270         if (status & RXBD_TRUNCATED) {
1271                 stats->rx_length_errors++;
1272
1273                 estats->rx_trunc++;
1274
1275                 return;
1276         }
1277         /* Count the errors, if there were any */
1278         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1279                 stats->rx_length_errors++;
1280
1281                 if (status & RXBD_LARGE)
1282                         estats->rx_large++;
1283                 else
1284                         estats->rx_short++;
1285         }
1286         if (status & RXBD_NONOCTET) {
1287                 stats->rx_frame_errors++;
1288                 estats->rx_nonoctet++;
1289         }
1290         if (status & RXBD_CRCERR) {
1291                 estats->rx_crcerr++;
1292                 stats->rx_crc_errors++;
1293         }
1294         if (status & RXBD_OVERRUN) {
1295                 estats->rx_overrun++;
1296                 stats->rx_crc_errors++;
1297         }
1298 }
1299
1300 irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1301 {
1302         struct net_device *dev = (struct net_device *) dev_id;
1303         struct gfar_private *priv = netdev_priv(dev);
1304
1305 #ifdef CONFIG_GFAR_NAPI
1306         u32 tempval;
1307 #endif
1308
1309         /* Clear IEVENT, so rx interrupt isn't called again
1310          * because of this interrupt */
1311         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1312
1313         /* support NAPI */
1314 #ifdef CONFIG_GFAR_NAPI
1315         if (netif_rx_schedule_prep(dev)) {
1316                 tempval = gfar_read(&priv->regs->imask);
1317                 tempval &= IMASK_RX_DISABLED;
1318                 gfar_write(&priv->regs->imask, tempval);
1319
1320                 __netif_rx_schedule(dev);
1321         } else {
1322                 if (netif_msg_rx_err(priv))
1323                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1324                                 dev->name, gfar_read(&priv->regs->ievent),
1325                                 gfar_read(&priv->regs->imask));
1326         }
1327 #else
1328
1329         spin_lock(&priv->lock);
1330         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1331
1332         /* If we are coalescing interrupts, update the timer */
1333         /* Otherwise, clear it */
1334         if (priv->rxcoalescing)
1335                 gfar_write(&priv->regs->rxic,
1336                            mk_ic_value(priv->rxcount, priv->rxtime));
1337         else
1338                 gfar_write(&priv->regs->rxic, 0);
1339
1340         spin_unlock(&priv->lock);
1341 #endif
1342
1343         return IRQ_HANDLED;
1344 }
1345
1346 static inline int gfar_rx_vlan(struct sk_buff *skb,
1347                 struct vlan_group *vlgrp, unsigned short vlctl)
1348 {
1349 #ifdef CONFIG_GFAR_NAPI
1350         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1351 #else
1352         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1353 #endif
1354 }
1355
1356 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1357 {
1358         /* If valid headers were found, and valid sums
1359          * were verified, then we tell the kernel that no
1360          * checksumming is necessary.  Otherwise, it is */
1361         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1362                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1363         else
1364                 skb->ip_summed = CHECKSUM_NONE;
1365 }
1366
1367
1368 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1369 {
1370         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1371
1372         /* Remove the FCB from the skb */
1373         skb_pull(skb, GMAC_FCB_LEN);
1374
1375         return fcb;
1376 }
1377
1378 /* gfar_process_frame() -- handle one incoming packet if skb
1379  * isn't NULL.  */
1380 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1381                 int length)
1382 {
1383         struct gfar_private *priv = netdev_priv(dev);
1384         struct rxfcb *fcb = NULL;
1385
1386         if (NULL == skb) {
1387                 if (netif_msg_rx_err(priv))
1388                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1389                 priv->stats.rx_dropped++;
1390                 priv->extra_stats.rx_skbmissing++;
1391         } else {
1392                 int ret;
1393
1394                 /* Prep the skb for the packet */
1395                 skb_put(skb, length);
1396
1397                 /* Grab the FCB if there is one */
1398                 if (gfar_uses_fcb(priv))
1399                         fcb = gfar_get_fcb(skb);
1400
1401                 /* Remove the padded bytes, if there are any */
1402                 if (priv->padding)
1403                         skb_pull(skb, priv->padding);
1404
1405                 if (priv->rx_csum_enable)
1406                         gfar_rx_checksum(skb, fcb);
1407
1408                 /* Tell the skb what kind of packet this is */
1409                 skb->protocol = eth_type_trans(skb, dev);
1410
1411                 /* Send the packet up the stack */
1412                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1413                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1414                 else
1415                         ret = RECEIVE(skb);
1416
1417                 if (NET_RX_DROP == ret)
1418                         priv->extra_stats.kernel_dropped++;
1419         }
1420
1421         return 0;
1422 }
1423
1424 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1425  *   until the budget/quota has been reached. Returns the number
1426  *   of frames handled
1427  */
1428 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1429 {
1430         struct rxbd8 *bdp;
1431         struct sk_buff *skb;
1432         u16 pkt_len;
1433         int howmany = 0;
1434         struct gfar_private *priv = netdev_priv(dev);
1435
1436         /* Get the first full descriptor */
1437         bdp = priv->cur_rx;
1438
1439         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1440                 skb = priv->rx_skbuff[priv->skb_currx];
1441
1442                 if (!(bdp->status &
1443                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1444                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1445                         /* Increment the number of packets */
1446                         priv->stats.rx_packets++;
1447                         howmany++;
1448
1449                         /* Remove the FCS from the packet length */
1450                         pkt_len = bdp->length - 4;
1451
1452                         gfar_process_frame(dev, skb, pkt_len);
1453
1454                         priv->stats.rx_bytes += pkt_len;
1455                 } else {
1456                         count_errors(bdp->status, priv);
1457
1458                         if (skb)
1459                                 dev_kfree_skb_any(skb);
1460
1461                         priv->rx_skbuff[priv->skb_currx] = NULL;
1462                 }
1463
1464                 dev->last_rx = jiffies;
1465
1466                 /* Clear the status flags for this buffer */
1467                 bdp->status &= ~RXBD_STATS;
1468
1469                 /* Add another skb for the future */
1470                 skb = gfar_new_skb(dev, bdp);
1471                 priv->rx_skbuff[priv->skb_currx] = skb;
1472
1473                 /* Update to the next pointer */
1474                 if (bdp->status & RXBD_WRAP)
1475                         bdp = priv->rx_bd_base;
1476                 else
1477                         bdp++;
1478
1479                 /* update to point at the next skb */
1480                 priv->skb_currx =
1481                     (priv->skb_currx +
1482                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1483
1484         }
1485
1486         /* Update the current rxbd pointer to be the next one */
1487         priv->cur_rx = bdp;
1488
1489         /* If no packets have arrived since the
1490          * last one we processed, clear the IEVENT RX and
1491          * BSY bits so that another interrupt won't be
1492          * generated when we set IMASK */
1493         if (bdp->status & RXBD_EMPTY)
1494                 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1495
1496         return howmany;
1497 }
1498
1499 #ifdef CONFIG_GFAR_NAPI
1500 static int gfar_poll(struct net_device *dev, int *budget)
1501 {
1502         int howmany;
1503         struct gfar_private *priv = netdev_priv(dev);
1504         int rx_work_limit = *budget;
1505
1506         if (rx_work_limit > dev->quota)
1507                 rx_work_limit = dev->quota;
1508
1509         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1510
1511         dev->quota -= howmany;
1512         rx_work_limit -= howmany;
1513         *budget -= howmany;
1514
1515         if (rx_work_limit >= 0) {
1516                 netif_rx_complete(dev);
1517
1518                 /* Clear the halt bit in RSTAT */
1519                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1520
1521                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1522
1523                 /* If we are coalescing interrupts, update the timer */
1524                 /* Otherwise, clear it */
1525                 if (priv->rxcoalescing)
1526                         gfar_write(&priv->regs->rxic,
1527                                    mk_ic_value(priv->rxcount, priv->rxtime));
1528                 else
1529                         gfar_write(&priv->regs->rxic, 0);
1530         }
1531
1532         return (rx_work_limit < 0) ? 1 : 0;
1533 }
1534 #endif
1535
1536 /* The interrupt handler for devices with one interrupt */
1537 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1538 {
1539         struct net_device *dev = dev_id;
1540         struct gfar_private *priv = netdev_priv(dev);
1541
1542         /* Save ievent for future reference */
1543         u32 events = gfar_read(&priv->regs->ievent);
1544
1545         /* Clear IEVENT */
1546         gfar_write(&priv->regs->ievent, events);
1547
1548         /* Check for reception */
1549         if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1550                 gfar_receive(irq, dev_id, regs);
1551
1552         /* Check for transmit completion */
1553         if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1554                 gfar_transmit(irq, dev_id, regs);
1555
1556         /* Update error statistics */
1557         if (events & IEVENT_TXE) {
1558                 priv->stats.tx_errors++;
1559
1560                 if (events & IEVENT_LC)
1561                         priv->stats.tx_window_errors++;
1562                 if (events & IEVENT_CRL)
1563                         priv->stats.tx_aborted_errors++;
1564                 if (events & IEVENT_XFUN) {
1565                         if (netif_msg_tx_err(priv))
1566                                 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1567                         priv->stats.tx_dropped++;
1568                         priv->extra_stats.tx_underrun++;
1569
1570                         /* Reactivate the Tx Queues */
1571                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1572                 }
1573         }
1574         if (events & IEVENT_BSY) {
1575                 priv->stats.rx_errors++;
1576                 priv->extra_stats.rx_bsy++;
1577
1578                 gfar_receive(irq, dev_id, regs);
1579
1580 #ifndef CONFIG_GFAR_NAPI
1581                 /* Clear the halt bit in RSTAT */
1582                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1583 #endif
1584
1585                 if (netif_msg_rx_err(priv))
1586                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1587                                         dev->name,
1588                                         gfar_read(&priv->regs->rstat));
1589         }
1590         if (events & IEVENT_BABR) {
1591                 priv->stats.rx_errors++;
1592                 priv->extra_stats.rx_babr++;
1593
1594                 if (netif_msg_rx_err(priv))
1595                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1596         }
1597         if (events & IEVENT_EBERR) {
1598                 priv->extra_stats.eberr++;
1599                 if (netif_msg_rx_err(priv))
1600                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1601         }
1602         if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1603                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1604
1605         if (events & IEVENT_BABT) {
1606                 priv->extra_stats.tx_babt++;
1607                 if (netif_msg_rx_err(priv))
1608                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1609         }
1610
1611         return IRQ_HANDLED;
1612 }
1613
1614 /* Called every time the controller might need to be made
1615  * aware of new link state.  The PHY code conveys this
1616  * information through variables in the phydev structure, and this
1617  * function converts those variables into the appropriate
1618  * register values, and can bring down the device if needed.
1619  */
1620 static void adjust_link(struct net_device *dev)
1621 {
1622         struct gfar_private *priv = netdev_priv(dev);
1623         struct gfar __iomem *regs = priv->regs;
1624         unsigned long flags;
1625         struct phy_device *phydev = priv->phydev;
1626         int new_state = 0;
1627
1628         spin_lock_irqsave(&priv->lock, flags);
1629         if (phydev->link) {
1630                 u32 tempval = gfar_read(&regs->maccfg2);
1631                 u32 ecntrl = gfar_read(&regs->ecntrl);
1632
1633                 /* Now we make sure that we can be in full duplex mode.
1634                  * If not, we operate in half-duplex mode. */
1635                 if (phydev->duplex != priv->oldduplex) {
1636                         new_state = 1;
1637                         if (!(phydev->duplex))
1638                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1639                         else
1640                                 tempval |= MACCFG2_FULL_DUPLEX;
1641
1642                         priv->oldduplex = phydev->duplex;
1643                 }
1644
1645                 if (phydev->speed != priv->oldspeed) {
1646                         new_state = 1;
1647                         switch (phydev->speed) {
1648                         case 1000:
1649                                 tempval =
1650                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1651                                 break;
1652                         case 100:
1653                         case 10:
1654                                 tempval =
1655                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1656
1657                                 /* Reduced mode distinguishes
1658                                  * between 10 and 100 */
1659                                 if (phydev->speed == SPEED_100)
1660                                         ecntrl |= ECNTRL_R100;
1661                                 else
1662                                         ecntrl &= ~(ECNTRL_R100);
1663                                 break;
1664                         default:
1665                                 if (netif_msg_link(priv))
1666                                         printk(KERN_WARNING
1667                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1668                                                 dev->name, phydev->speed);
1669                                 break;
1670                         }
1671
1672                         priv->oldspeed = phydev->speed;
1673                 }
1674
1675                 gfar_write(&regs->maccfg2, tempval);
1676                 gfar_write(&regs->ecntrl, ecntrl);
1677
1678                 if (!priv->oldlink) {
1679                         new_state = 1;
1680                         priv->oldlink = 1;
1681                         netif_schedule(dev);
1682                 }
1683         } else if (priv->oldlink) {
1684                 new_state = 1;
1685                 priv->oldlink = 0;
1686                 priv->oldspeed = 0;
1687                 priv->oldduplex = -1;
1688         }
1689
1690         if (new_state && netif_msg_link(priv))
1691                 phy_print_status(phydev);
1692
1693         spin_unlock_irqrestore(&priv->lock, flags);
1694 }
1695
1696 /* Update the hash table based on the current list of multicast
1697  * addresses we subscribe to.  Also, change the promiscuity of
1698  * the device based on the flags (this function is called
1699  * whenever dev->flags is changed */
1700 static void gfar_set_multi(struct net_device *dev)
1701 {
1702         struct dev_mc_list *mc_ptr;
1703         struct gfar_private *priv = netdev_priv(dev);
1704         struct gfar __iomem *regs = priv->regs;
1705         u32 tempval;
1706
1707         if(dev->flags & IFF_PROMISC) {
1708                 if (netif_msg_drv(priv))
1709                         printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1710                                         dev->name);
1711                 /* Set RCTRL to PROM */
1712                 tempval = gfar_read(&regs->rctrl);
1713                 tempval |= RCTRL_PROM;
1714                 gfar_write(&regs->rctrl, tempval);
1715         } else {
1716                 /* Set RCTRL to not PROM */
1717                 tempval = gfar_read(&regs->rctrl);
1718                 tempval &= ~(RCTRL_PROM);
1719                 gfar_write(&regs->rctrl, tempval);
1720         }
1721         
1722         if(dev->flags & IFF_ALLMULTI) {
1723                 /* Set the hash to rx all multicast frames */
1724                 gfar_write(&regs->igaddr0, 0xffffffff);
1725                 gfar_write(&regs->igaddr1, 0xffffffff);
1726                 gfar_write(&regs->igaddr2, 0xffffffff);
1727                 gfar_write(&regs->igaddr3, 0xffffffff);
1728                 gfar_write(&regs->igaddr4, 0xffffffff);
1729                 gfar_write(&regs->igaddr5, 0xffffffff);
1730                 gfar_write(&regs->igaddr6, 0xffffffff);
1731                 gfar_write(&regs->igaddr7, 0xffffffff);
1732                 gfar_write(&regs->gaddr0, 0xffffffff);
1733                 gfar_write(&regs->gaddr1, 0xffffffff);
1734                 gfar_write(&regs->gaddr2, 0xffffffff);
1735                 gfar_write(&regs->gaddr3, 0xffffffff);
1736                 gfar_write(&regs->gaddr4, 0xffffffff);
1737                 gfar_write(&regs->gaddr5, 0xffffffff);
1738                 gfar_write(&regs->gaddr6, 0xffffffff);
1739                 gfar_write(&regs->gaddr7, 0xffffffff);
1740         } else {
1741                 int em_num;
1742                 int idx;
1743
1744                 /* zero out the hash */
1745                 gfar_write(&regs->igaddr0, 0x0);
1746                 gfar_write(&regs->igaddr1, 0x0);
1747                 gfar_write(&regs->igaddr2, 0x0);
1748                 gfar_write(&regs->igaddr3, 0x0);
1749                 gfar_write(&regs->igaddr4, 0x0);
1750                 gfar_write(&regs->igaddr5, 0x0);
1751                 gfar_write(&regs->igaddr6, 0x0);
1752                 gfar_write(&regs->igaddr7, 0x0);
1753                 gfar_write(&regs->gaddr0, 0x0);
1754                 gfar_write(&regs->gaddr1, 0x0);
1755                 gfar_write(&regs->gaddr2, 0x0);
1756                 gfar_write(&regs->gaddr3, 0x0);
1757                 gfar_write(&regs->gaddr4, 0x0);
1758                 gfar_write(&regs->gaddr5, 0x0);
1759                 gfar_write(&regs->gaddr6, 0x0);
1760                 gfar_write(&regs->gaddr7, 0x0);
1761
1762                 /* If we have extended hash tables, we need to
1763                  * clear the exact match registers to prepare for
1764                  * setting them */
1765                 if (priv->extended_hash) {
1766                         em_num = GFAR_EM_NUM + 1;
1767                         gfar_clear_exact_match(dev);
1768                         idx = 1;
1769                 } else {
1770                         idx = 0;
1771                         em_num = 0;
1772                 }
1773
1774                 if(dev->mc_count == 0)
1775                         return;
1776
1777                 /* Parse the list, and set the appropriate bits */
1778                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1779                         if (idx < em_num) {
1780                                 gfar_set_mac_for_addr(dev, idx,
1781                                                 mc_ptr->dmi_addr);
1782                                 idx++;
1783                         } else
1784                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1785                 }
1786         }
1787
1788         return;
1789 }
1790
1791
1792 /* Clears each of the exact match registers to zero, so they
1793  * don't interfere with normal reception */
1794 static void gfar_clear_exact_match(struct net_device *dev)
1795 {
1796         int idx;
1797         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1798
1799         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1800                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1801 }
1802
1803 /* Set the appropriate hash bit for the given addr */
1804 /* The algorithm works like so:
1805  * 1) Take the Destination Address (ie the multicast address), and
1806  * do a CRC on it (little endian), and reverse the bits of the
1807  * result.
1808  * 2) Use the 8 most significant bits as a hash into a 256-entry
1809  * table.  The table is controlled through 8 32-bit registers:
1810  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1811  * gaddr7.  This means that the 3 most significant bits in the
1812  * hash index which gaddr register to use, and the 5 other bits
1813  * indicate which bit (assuming an IBM numbering scheme, which
1814  * for PowerPC (tm) is usually the case) in the register holds
1815  * the entry. */
1816 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1817 {
1818         u32 tempval;
1819         struct gfar_private *priv = netdev_priv(dev);
1820         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1821         int width = priv->hash_width;
1822         u8 whichbit = (result >> (32 - width)) & 0x1f;
1823         u8 whichreg = result >> (32 - width + 5);
1824         u32 value = (1 << (31-whichbit));
1825
1826         tempval = gfar_read(priv->hash_regs[whichreg]);
1827         tempval |= value;
1828         gfar_write(priv->hash_regs[whichreg], tempval);
1829
1830         return;
1831 }
1832
1833
1834 /* There are multiple MAC Address register pairs on some controllers
1835  * This function sets the numth pair to a given address
1836  */
1837 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1838 {
1839         struct gfar_private *priv = netdev_priv(dev);
1840         int idx;
1841         char tmpbuf[MAC_ADDR_LEN];
1842         u32 tempval;
1843         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1844
1845         macptr += num*2;
1846
1847         /* Now copy it into the mac registers backwards, cuz */
1848         /* little endian is silly */
1849         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1850                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1851
1852         gfar_write(macptr, *((u32 *) (tmpbuf)));
1853
1854         tempval = *((u32 *) (tmpbuf + 4));
1855
1856         gfar_write(macptr+1, tempval);
1857 }
1858
1859 /* GFAR error interrupt handler */
1860 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1861 {
1862         struct net_device *dev = dev_id;
1863         struct gfar_private *priv = netdev_priv(dev);
1864
1865         /* Save ievent for future reference */
1866         u32 events = gfar_read(&priv->regs->ievent);
1867
1868         /* Clear IEVENT */
1869         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1870
1871         /* Hmm... */
1872         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1873                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1874                                 dev->name, events, gfar_read(&priv->regs->imask));
1875
1876         /* Update the error counters */
1877         if (events & IEVENT_TXE) {
1878                 priv->stats.tx_errors++;
1879
1880                 if (events & IEVENT_LC)
1881                         priv->stats.tx_window_errors++;
1882                 if (events & IEVENT_CRL)
1883                         priv->stats.tx_aborted_errors++;
1884                 if (events & IEVENT_XFUN) {
1885                         if (netif_msg_tx_err(priv))
1886                                 printk(KERN_DEBUG "%s: underrun.  packet dropped.\n",
1887                                                 dev->name);
1888                         priv->stats.tx_dropped++;
1889                         priv->extra_stats.tx_underrun++;
1890
1891                         /* Reactivate the Tx Queues */
1892                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1893                 }
1894                 if (netif_msg_tx_err(priv))
1895                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1896         }
1897         if (events & IEVENT_BSY) {
1898                 priv->stats.rx_errors++;
1899                 priv->extra_stats.rx_bsy++;
1900
1901                 gfar_receive(irq, dev_id, regs);
1902
1903 #ifndef CONFIG_GFAR_NAPI
1904                 /* Clear the halt bit in RSTAT */
1905                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1906 #endif
1907
1908                 if (netif_msg_rx_err(priv))
1909                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1910                                         dev->name,
1911                                         gfar_read(&priv->regs->rstat));
1912         }
1913         if (events & IEVENT_BABR) {
1914                 priv->stats.rx_errors++;
1915                 priv->extra_stats.rx_babr++;
1916
1917                 if (netif_msg_rx_err(priv))
1918                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1919         }
1920         if (events & IEVENT_EBERR) {
1921                 priv->extra_stats.eberr++;
1922                 if (netif_msg_rx_err(priv))
1923                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1924         }
1925         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1926                 if (netif_msg_rx_status(priv))
1927                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1928
1929         if (events & IEVENT_BABT) {
1930                 priv->extra_stats.tx_babt++;
1931                 if (netif_msg_tx_err(priv))
1932                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1933         }
1934         return IRQ_HANDLED;
1935 }
1936
1937 /* Structure for a device driver */
1938 static struct platform_driver gfar_driver = {
1939         .probe = gfar_probe,
1940         .remove = gfar_remove,
1941         .driver = {
1942                 .name = "fsl-gianfar",
1943         },
1944 };
1945
1946 static int __init gfar_init(void)
1947 {
1948         int err = gfar_mdio_init();
1949
1950         if (err)
1951                 return err;
1952
1953         err = platform_driver_register(&gfar_driver);
1954
1955         if (err)
1956                 gfar_mdio_exit();
1957         
1958         return err;
1959 }
1960
1961 static void __exit gfar_exit(void)
1962 {
1963         platform_driver_unregister(&gfar_driver);
1964         gfar_mdio_exit();
1965 }
1966
1967 module_init(gfar_init);
1968 module_exit(gfar_exit);
1969