forcedeth: tx collision fix
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Changelog:
33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35  *                         Check all PCI BARs for the register window.
36  *                         udelay added to mii_rw.
37  *      0.03: 06 Oct 2003: Initialize dev->irq.
38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41  *                         irq mask updated
42  *      0.07: 14 Oct 2003: Further irq mask updates.
43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44  *                         added into irq handler, NULL check for drain_ring.
45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46  *                         requested interrupt sources.
47  *      0.10: 20 Oct 2003: First cleanup for release.
48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49  *                         MAC Address init fix, set_multicast cleanup.
50  *      0.12: 23 Oct 2003: Cleanups for release.
51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52  *                         Set link speed correctly. start rx before starting
53  *                         tx (nv_start_rx sets the link speed).
54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56  *                         open.
57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58  *                         increased to 1628 bytes.
59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60  *                         the tx length.
61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63  *                         addresses, really stop rx if already running
64  *                         in nv_start_rx, clean up a bit.
65  *      0.20: 07 Dec 2003: alloc fixes
66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68  *                         on close.
69  *      0.23: 26 Jan 2004: various small cleanups
70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71  *      0.25: 09 Mar 2004: wol support
72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74  *                         added CK804/MCP04 device IDs, code fixes
75  *                         for registers, link status and other minor fixes.
76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79  *                         into nv_close, otherwise reenabling for wol can
80  *                         cause DMA to kfree'd memory.
81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
82  *                         capabilities.
83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
84  *      0.33: 16 May 2005: Support for MCP51 added.
85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86  *      0.35: 26 Jun 2005: Support for MCP55 added.
87  *      0.36: 28 Jun 2005: Add jumbo frame support.
88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90  *                         per-packet flags.
91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
92  *      0.40: 19 Jul 2005: Add support for mac address change.
93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94  *                         of nv_remove
95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
96  *                         in the second (and later) nv_open call
97  *      0.43: 10 Aug 2005: Add support for tx checksum.
98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100  *      0.46: 20 Oct 2005: Add irq optimization modes.
101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
113  *      0.59: 30 Oct 2006: Added support for recoverable error.
114  *      0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
115  *
116  * Known bugs:
117  * We suspect that on some hardware no TX done interrupts are generated.
118  * This means recovery from netif_stop_queue only happens if the hw timer
119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
121  * If your hardware reliably generates tx done interrupts, then you can remove
122  * DEV_NEED_TIMERIRQ from the driver_data flags.
123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
124  * superfluous timer interrupts from the nic.
125  */
126 #ifdef CONFIG_FORCEDETH_NAPI
127 #define DRIVERNAPI "-NAPI"
128 #else
129 #define DRIVERNAPI
130 #endif
131 #define FORCEDETH_VERSION               "0.61"
132 #define DRV_NAME                        "forcedeth"
133
134 #include <linux/module.h>
135 #include <linux/types.h>
136 #include <linux/pci.h>
137 #include <linux/interrupt.h>
138 #include <linux/netdevice.h>
139 #include <linux/etherdevice.h>
140 #include <linux/delay.h>
141 #include <linux/spinlock.h>
142 #include <linux/ethtool.h>
143 #include <linux/timer.h>
144 #include <linux/skbuff.h>
145 #include <linux/mii.h>
146 #include <linux/random.h>
147 #include <linux/init.h>
148 #include <linux/if_vlan.h>
149 #include <linux/dma-mapping.h>
150
151 #include <asm/irq.h>
152 #include <asm/io.h>
153 #include <asm/uaccess.h>
154 #include <asm/system.h>
155
156 #if 0
157 #define dprintk                 printk
158 #else
159 #define dprintk(x...)           do { } while (0)
160 #endif
161
162 #define TX_WORK_PER_LOOP  64
163 #define RX_WORK_PER_LOOP  64
164
165 /*
166  * Hardware access:
167  */
168
169 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
170 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
171 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
172 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
173 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
174 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
175 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
176 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
177 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
178 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
179 #define DEV_HAS_STATISTICS_V1   0x0400  /* device supports hw statistics version 1 */
180 #define DEV_HAS_STATISTICS_V2   0x0800  /* device supports hw statistics version 2 */
181 #define DEV_HAS_TEST_EXTENDED   0x1000  /* device supports extended diagnostic test */
182 #define DEV_HAS_MGMT_UNIT       0x2000  /* device supports management unit */
183 #define DEV_HAS_CORRECT_MACADDR 0x4000  /* device supports correct mac address order */
184 #define DEV_HAS_COLLISION_FIX   0x8000  /* device supports tx collision fix */
185
186 enum {
187         NvRegIrqStatus = 0x000,
188 #define NVREG_IRQSTAT_MIIEVENT  0x040
189 #define NVREG_IRQSTAT_MASK              0x81ff
190         NvRegIrqMask = 0x004,
191 #define NVREG_IRQ_RX_ERROR              0x0001
192 #define NVREG_IRQ_RX                    0x0002
193 #define NVREG_IRQ_RX_NOBUF              0x0004
194 #define NVREG_IRQ_TX_ERR                0x0008
195 #define NVREG_IRQ_TX_OK                 0x0010
196 #define NVREG_IRQ_TIMER                 0x0020
197 #define NVREG_IRQ_LINK                  0x0040
198 #define NVREG_IRQ_RX_FORCED             0x0080
199 #define NVREG_IRQ_TX_FORCED             0x0100
200 #define NVREG_IRQ_RECOVER_ERROR         0x8000
201 #define NVREG_IRQMASK_THROUGHPUT        0x00df
202 #define NVREG_IRQMASK_CPU               0x0060
203 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
204 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
205 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
206
207 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
208                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
209                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
210
211         NvRegUnknownSetupReg6 = 0x008,
212 #define NVREG_UNKSETUP6_VAL             3
213
214 /*
215  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
216  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
217  */
218         NvRegPollingInterval = 0x00c,
219 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
220 #define NVREG_POLL_DEFAULT_CPU  13
221         NvRegMSIMap0 = 0x020,
222         NvRegMSIMap1 = 0x024,
223         NvRegMSIIrqMask = 0x030,
224 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
225         NvRegMisc1 = 0x080,
226 #define NVREG_MISC1_PAUSE_TX    0x01
227 #define NVREG_MISC1_HD          0x02
228 #define NVREG_MISC1_FORCE       0x3b0f3c
229
230         NvRegMacReset = 0x34,
231 #define NVREG_MAC_RESET_ASSERT  0x0F3
232         NvRegTransmitterControl = 0x084,
233 #define NVREG_XMITCTL_START     0x01
234 #define NVREG_XMITCTL_MGMT_ST   0x40000000
235 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
236 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
237 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
238 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
239 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
240 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
241 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
242 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
243 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
244         NvRegTransmitterStatus = 0x088,
245 #define NVREG_XMITSTAT_BUSY     0x01
246
247         NvRegPacketFilterFlags = 0x8c,
248 #define NVREG_PFF_PAUSE_RX      0x08
249 #define NVREG_PFF_ALWAYS        0x7F0000
250 #define NVREG_PFF_PROMISC       0x80
251 #define NVREG_PFF_MYADDR        0x20
252 #define NVREG_PFF_LOOPBACK      0x10
253
254         NvRegOffloadConfig = 0x90,
255 #define NVREG_OFFLOAD_HOMEPHY   0x601
256 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
257         NvRegReceiverControl = 0x094,
258 #define NVREG_RCVCTL_START      0x01
259 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
260         NvRegReceiverStatus = 0x98,
261 #define NVREG_RCVSTAT_BUSY      0x01
262
263         NvRegRandomSeed = 0x9c,
264 #define NVREG_RNDSEED_MASK      0x00ff
265 #define NVREG_RNDSEED_FORCE     0x7f00
266 #define NVREG_RNDSEED_FORCE2    0x2d00
267 #define NVREG_RNDSEED_FORCE3    0x7400
268
269         NvRegTxDeferral = 0xA0,
270 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
271 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
272 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
273 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
274 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
275 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
276         NvRegRxDeferral = 0xA4,
277 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
278         NvRegMacAddrA = 0xA8,
279         NvRegMacAddrB = 0xAC,
280         NvRegMulticastAddrA = 0xB0,
281 #define NVREG_MCASTADDRA_FORCE  0x01
282         NvRegMulticastAddrB = 0xB4,
283         NvRegMulticastMaskA = 0xB8,
284 #define NVREG_MCASTMASKA_NONE           0xffffffff
285         NvRegMulticastMaskB = 0xBC,
286 #define NVREG_MCASTMASKB_NONE           0xffff
287
288         NvRegPhyInterface = 0xC0,
289 #define PHY_RGMII               0x10000000
290
291         NvRegTxRingPhysAddr = 0x100,
292         NvRegRxRingPhysAddr = 0x104,
293         NvRegRingSizes = 0x108,
294 #define NVREG_RINGSZ_TXSHIFT 0
295 #define NVREG_RINGSZ_RXSHIFT 16
296         NvRegTransmitPoll = 0x10c,
297 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
298         NvRegLinkSpeed = 0x110,
299 #define NVREG_LINKSPEED_FORCE 0x10000
300 #define NVREG_LINKSPEED_10      1000
301 #define NVREG_LINKSPEED_100     100
302 #define NVREG_LINKSPEED_1000    50
303 #define NVREG_LINKSPEED_MASK    (0xFFF)
304         NvRegUnknownSetupReg5 = 0x130,
305 #define NVREG_UNKSETUP5_BIT31   (1<<31)
306         NvRegTxWatermark = 0x13c,
307 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
308 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
309 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
310         NvRegTxRxControl = 0x144,
311 #define NVREG_TXRXCTL_KICK      0x0001
312 #define NVREG_TXRXCTL_BIT1      0x0002
313 #define NVREG_TXRXCTL_BIT2      0x0004
314 #define NVREG_TXRXCTL_IDLE      0x0008
315 #define NVREG_TXRXCTL_RESET     0x0010
316 #define NVREG_TXRXCTL_RXCHECK   0x0400
317 #define NVREG_TXRXCTL_DESC_1    0
318 #define NVREG_TXRXCTL_DESC_2    0x002100
319 #define NVREG_TXRXCTL_DESC_3    0xc02200
320 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
321 #define NVREG_TXRXCTL_VLANINS   0x00080
322         NvRegTxRingPhysAddrHigh = 0x148,
323         NvRegRxRingPhysAddrHigh = 0x14C,
324         NvRegTxPauseFrame = 0x170,
325 #define NVREG_TX_PAUSEFRAME_DISABLE     0x01ff0080
326 #define NVREG_TX_PAUSEFRAME_ENABLE      0x01800010
327         NvRegMIIStatus = 0x180,
328 #define NVREG_MIISTAT_ERROR             0x0001
329 #define NVREG_MIISTAT_LINKCHANGE        0x0008
330 #define NVREG_MIISTAT_MASK_RW           0x0007
331 #define NVREG_MIISTAT_MASK_ALL          0x000f
332         NvRegMIIMask = 0x184,
333 #define NVREG_MII_LINKCHANGE            0x0008
334
335         NvRegAdapterControl = 0x188,
336 #define NVREG_ADAPTCTL_START    0x02
337 #define NVREG_ADAPTCTL_LINKUP   0x04
338 #define NVREG_ADAPTCTL_PHYVALID 0x40000
339 #define NVREG_ADAPTCTL_RUNNING  0x100000
340 #define NVREG_ADAPTCTL_PHYSHIFT 24
341         NvRegMIISpeed = 0x18c,
342 #define NVREG_MIISPEED_BIT8     (1<<8)
343 #define NVREG_MIIDELAY  5
344         NvRegMIIControl = 0x190,
345 #define NVREG_MIICTL_INUSE      0x08000
346 #define NVREG_MIICTL_WRITE      0x00400
347 #define NVREG_MIICTL_ADDRSHIFT  5
348         NvRegMIIData = 0x194,
349         NvRegWakeUpFlags = 0x200,
350 #define NVREG_WAKEUPFLAGS_VAL           0x7770
351 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
352 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
353 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
354 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
355 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
356 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
357 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
358 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
359 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
360 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
361
362         NvRegPatternCRC = 0x204,
363         NvRegPatternMask = 0x208,
364         NvRegPowerCap = 0x268,
365 #define NVREG_POWERCAP_D3SUPP   (1<<30)
366 #define NVREG_POWERCAP_D2SUPP   (1<<26)
367 #define NVREG_POWERCAP_D1SUPP   (1<<25)
368         NvRegPowerState = 0x26c,
369 #define NVREG_POWERSTATE_POWEREDUP      0x8000
370 #define NVREG_POWERSTATE_VALID          0x0100
371 #define NVREG_POWERSTATE_MASK           0x0003
372 #define NVREG_POWERSTATE_D0             0x0000
373 #define NVREG_POWERSTATE_D1             0x0001
374 #define NVREG_POWERSTATE_D2             0x0002
375 #define NVREG_POWERSTATE_D3             0x0003
376         NvRegTxCnt = 0x280,
377         NvRegTxZeroReXmt = 0x284,
378         NvRegTxOneReXmt = 0x288,
379         NvRegTxManyReXmt = 0x28c,
380         NvRegTxLateCol = 0x290,
381         NvRegTxUnderflow = 0x294,
382         NvRegTxLossCarrier = 0x298,
383         NvRegTxExcessDef = 0x29c,
384         NvRegTxRetryErr = 0x2a0,
385         NvRegRxFrameErr = 0x2a4,
386         NvRegRxExtraByte = 0x2a8,
387         NvRegRxLateCol = 0x2ac,
388         NvRegRxRunt = 0x2b0,
389         NvRegRxFrameTooLong = 0x2b4,
390         NvRegRxOverflow = 0x2b8,
391         NvRegRxFCSErr = 0x2bc,
392         NvRegRxFrameAlignErr = 0x2c0,
393         NvRegRxLenErr = 0x2c4,
394         NvRegRxUnicast = 0x2c8,
395         NvRegRxMulticast = 0x2cc,
396         NvRegRxBroadcast = 0x2d0,
397         NvRegTxDef = 0x2d4,
398         NvRegTxFrame = 0x2d8,
399         NvRegRxCnt = 0x2dc,
400         NvRegTxPause = 0x2e0,
401         NvRegRxPause = 0x2e4,
402         NvRegRxDropFrame = 0x2e8,
403         NvRegVlanControl = 0x300,
404 #define NVREG_VLANCONTROL_ENABLE        0x2000
405         NvRegMSIXMap0 = 0x3e0,
406         NvRegMSIXMap1 = 0x3e4,
407         NvRegMSIXIrqStatus = 0x3f0,
408
409         NvRegPowerState2 = 0x600,
410 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
411 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
412 };
413
414 /* Big endian: should work, but is untested */
415 struct ring_desc {
416         __le32 buf;
417         __le32 flaglen;
418 };
419
420 struct ring_desc_ex {
421         __le32 bufhigh;
422         __le32 buflow;
423         __le32 txvlan;
424         __le32 flaglen;
425 };
426
427 union ring_type {
428         struct ring_desc* orig;
429         struct ring_desc_ex* ex;
430 };
431
432 #define FLAG_MASK_V1 0xffff0000
433 #define FLAG_MASK_V2 0xffffc000
434 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
435 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
436
437 #define NV_TX_LASTPACKET        (1<<16)
438 #define NV_TX_RETRYERROR        (1<<19)
439 #define NV_TX_FORCED_INTERRUPT  (1<<24)
440 #define NV_TX_DEFERRED          (1<<26)
441 #define NV_TX_CARRIERLOST       (1<<27)
442 #define NV_TX_LATECOLLISION     (1<<28)
443 #define NV_TX_UNDERFLOW         (1<<29)
444 #define NV_TX_ERROR             (1<<30)
445 #define NV_TX_VALID             (1<<31)
446
447 #define NV_TX2_LASTPACKET       (1<<29)
448 #define NV_TX2_RETRYERROR       (1<<18)
449 #define NV_TX2_FORCED_INTERRUPT (1<<30)
450 #define NV_TX2_DEFERRED         (1<<25)
451 #define NV_TX2_CARRIERLOST      (1<<26)
452 #define NV_TX2_LATECOLLISION    (1<<27)
453 #define NV_TX2_UNDERFLOW        (1<<28)
454 /* error and valid are the same for both */
455 #define NV_TX2_ERROR            (1<<30)
456 #define NV_TX2_VALID            (1<<31)
457 #define NV_TX2_TSO              (1<<28)
458 #define NV_TX2_TSO_SHIFT        14
459 #define NV_TX2_TSO_MAX_SHIFT    14
460 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
461 #define NV_TX2_CHECKSUM_L3      (1<<27)
462 #define NV_TX2_CHECKSUM_L4      (1<<26)
463
464 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
465
466 #define NV_RX_DESCRIPTORVALID   (1<<16)
467 #define NV_RX_MISSEDFRAME       (1<<17)
468 #define NV_RX_SUBSTRACT1        (1<<18)
469 #define NV_RX_ERROR1            (1<<23)
470 #define NV_RX_ERROR2            (1<<24)
471 #define NV_RX_ERROR3            (1<<25)
472 #define NV_RX_ERROR4            (1<<26)
473 #define NV_RX_CRCERR            (1<<27)
474 #define NV_RX_OVERFLOW          (1<<28)
475 #define NV_RX_FRAMINGERR        (1<<29)
476 #define NV_RX_ERROR             (1<<30)
477 #define NV_RX_AVAIL             (1<<31)
478
479 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
480 #define NV_RX2_CHECKSUM_IP      (0x10000000)
481 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
482 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
483 #define NV_RX2_DESCRIPTORVALID  (1<<29)
484 #define NV_RX2_SUBSTRACT1       (1<<25)
485 #define NV_RX2_ERROR1           (1<<18)
486 #define NV_RX2_ERROR2           (1<<19)
487 #define NV_RX2_ERROR3           (1<<20)
488 #define NV_RX2_ERROR4           (1<<21)
489 #define NV_RX2_CRCERR           (1<<22)
490 #define NV_RX2_OVERFLOW         (1<<23)
491 #define NV_RX2_FRAMINGERR       (1<<24)
492 /* error and avail are the same for both */
493 #define NV_RX2_ERROR            (1<<30)
494 #define NV_RX2_AVAIL            (1<<31)
495
496 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
497 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
498
499 /* Miscelaneous hardware related defines: */
500 #define NV_PCI_REGSZ_VER1       0x270
501 #define NV_PCI_REGSZ_VER2       0x2d4
502 #define NV_PCI_REGSZ_VER3       0x604
503
504 /* various timeout delays: all in usec */
505 #define NV_TXRX_RESET_DELAY     4
506 #define NV_TXSTOP_DELAY1        10
507 #define NV_TXSTOP_DELAY1MAX     500000
508 #define NV_TXSTOP_DELAY2        100
509 #define NV_RXSTOP_DELAY1        10
510 #define NV_RXSTOP_DELAY1MAX     500000
511 #define NV_RXSTOP_DELAY2        100
512 #define NV_SETUP5_DELAY         5
513 #define NV_SETUP5_DELAYMAX      50000
514 #define NV_POWERUP_DELAY        5
515 #define NV_POWERUP_DELAYMAX     5000
516 #define NV_MIIBUSY_DELAY        50
517 #define NV_MIIPHY_DELAY 10
518 #define NV_MIIPHY_DELAYMAX      10000
519 #define NV_MAC_RESET_DELAY      64
520
521 #define NV_WAKEUPPATTERNS       5
522 #define NV_WAKEUPMASKENTRIES    4
523
524 /* General driver defaults */
525 #define NV_WATCHDOG_TIMEO       (5*HZ)
526
527 #define RX_RING_DEFAULT         128
528 #define TX_RING_DEFAULT         256
529 #define RX_RING_MIN             128
530 #define TX_RING_MIN             64
531 #define RING_MAX_DESC_VER_1     1024
532 #define RING_MAX_DESC_VER_2_3   16384
533
534 /* rx/tx mac addr + type + vlan + align + slack*/
535 #define NV_RX_HEADERS           (64)
536 /* even more slack. */
537 #define NV_RX_ALLOC_PAD         (64)
538
539 /* maximum mtu size */
540 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
541 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
542
543 #define OOM_REFILL      (1+HZ/20)
544 #define POLL_WAIT       (1+HZ/100)
545 #define LINK_TIMEOUT    (3*HZ)
546 #define STATS_INTERVAL  (10*HZ)
547
548 /*
549  * desc_ver values:
550  * The nic supports three different descriptor types:
551  * - DESC_VER_1: Original
552  * - DESC_VER_2: support for jumbo frames.
553  * - DESC_VER_3: 64-bit format.
554  */
555 #define DESC_VER_1      1
556 #define DESC_VER_2      2
557 #define DESC_VER_3      3
558
559 /* PHY defines */
560 #define PHY_OUI_MARVELL 0x5043
561 #define PHY_OUI_CICADA  0x03f1
562 #define PHY_OUI_VITESSE 0x01c1
563 #define PHY_OUI_REALTEK 0x0732
564 #define PHYID1_OUI_MASK 0x03ff
565 #define PHYID1_OUI_SHFT 6
566 #define PHYID2_OUI_MASK 0xfc00
567 #define PHYID2_OUI_SHFT 10
568 #define PHYID2_MODEL_MASK               0x03f0
569 #define PHY_MODEL_MARVELL_E3016         0x220
570 #define PHY_MARVELL_E3016_INITMASK      0x0300
571 #define PHY_CICADA_INIT1        0x0f000
572 #define PHY_CICADA_INIT2        0x0e00
573 #define PHY_CICADA_INIT3        0x01000
574 #define PHY_CICADA_INIT4        0x0200
575 #define PHY_CICADA_INIT5        0x0004
576 #define PHY_CICADA_INIT6        0x02000
577 #define PHY_VITESSE_INIT_REG1   0x1f
578 #define PHY_VITESSE_INIT_REG2   0x10
579 #define PHY_VITESSE_INIT_REG3   0x11
580 #define PHY_VITESSE_INIT_REG4   0x12
581 #define PHY_VITESSE_INIT_MSK1   0xc
582 #define PHY_VITESSE_INIT_MSK2   0x0180
583 #define PHY_VITESSE_INIT1       0x52b5
584 #define PHY_VITESSE_INIT2       0xaf8a
585 #define PHY_VITESSE_INIT3       0x8
586 #define PHY_VITESSE_INIT4       0x8f8a
587 #define PHY_VITESSE_INIT5       0xaf86
588 #define PHY_VITESSE_INIT6       0x8f86
589 #define PHY_VITESSE_INIT7       0xaf82
590 #define PHY_VITESSE_INIT8       0x0100
591 #define PHY_VITESSE_INIT9       0x8f82
592 #define PHY_VITESSE_INIT10      0x0
593 #define PHY_REALTEK_INIT_REG1   0x1f
594 #define PHY_REALTEK_INIT_REG2   0x19
595 #define PHY_REALTEK_INIT_REG3   0x13
596 #define PHY_REALTEK_INIT1       0x0000
597 #define PHY_REALTEK_INIT2       0x8e00
598 #define PHY_REALTEK_INIT3       0x0001
599 #define PHY_REALTEK_INIT4       0xad17
600
601 #define PHY_GIGABIT     0x0100
602
603 #define PHY_TIMEOUT     0x1
604 #define PHY_ERROR       0x2
605
606 #define PHY_100 0x1
607 #define PHY_1000        0x2
608 #define PHY_HALF        0x100
609
610 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
611 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
612 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
613 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
614 #define NV_PAUSEFRAME_RX_REQ     0x0010
615 #define NV_PAUSEFRAME_TX_REQ     0x0020
616 #define NV_PAUSEFRAME_AUTONEG    0x0040
617
618 /* MSI/MSI-X defines */
619 #define NV_MSI_X_MAX_VECTORS  8
620 #define NV_MSI_X_VECTORS_MASK 0x000f
621 #define NV_MSI_CAPABLE        0x0010
622 #define NV_MSI_X_CAPABLE      0x0020
623 #define NV_MSI_ENABLED        0x0040
624 #define NV_MSI_X_ENABLED      0x0080
625
626 #define NV_MSI_X_VECTOR_ALL   0x0
627 #define NV_MSI_X_VECTOR_RX    0x0
628 #define NV_MSI_X_VECTOR_TX    0x1
629 #define NV_MSI_X_VECTOR_OTHER 0x2
630
631 #define NV_RESTART_TX         0x1
632 #define NV_RESTART_RX         0x2
633
634 /* statistics */
635 struct nv_ethtool_str {
636         char name[ETH_GSTRING_LEN];
637 };
638
639 static const struct nv_ethtool_str nv_estats_str[] = {
640         { "tx_bytes" },
641         { "tx_zero_rexmt" },
642         { "tx_one_rexmt" },
643         { "tx_many_rexmt" },
644         { "tx_late_collision" },
645         { "tx_fifo_errors" },
646         { "tx_carrier_errors" },
647         { "tx_excess_deferral" },
648         { "tx_retry_error" },
649         { "rx_frame_error" },
650         { "rx_extra_byte" },
651         { "rx_late_collision" },
652         { "rx_runt" },
653         { "rx_frame_too_long" },
654         { "rx_over_errors" },
655         { "rx_crc_errors" },
656         { "rx_frame_align_error" },
657         { "rx_length_error" },
658         { "rx_unicast" },
659         { "rx_multicast" },
660         { "rx_broadcast" },
661         { "rx_packets" },
662         { "rx_errors_total" },
663         { "tx_errors_total" },
664
665         /* version 2 stats */
666         { "tx_deferral" },
667         { "tx_packets" },
668         { "rx_bytes" },
669         { "tx_pause" },
670         { "rx_pause" },
671         { "rx_drop_frame" }
672 };
673
674 struct nv_ethtool_stats {
675         u64 tx_bytes;
676         u64 tx_zero_rexmt;
677         u64 tx_one_rexmt;
678         u64 tx_many_rexmt;
679         u64 tx_late_collision;
680         u64 tx_fifo_errors;
681         u64 tx_carrier_errors;
682         u64 tx_excess_deferral;
683         u64 tx_retry_error;
684         u64 rx_frame_error;
685         u64 rx_extra_byte;
686         u64 rx_late_collision;
687         u64 rx_runt;
688         u64 rx_frame_too_long;
689         u64 rx_over_errors;
690         u64 rx_crc_errors;
691         u64 rx_frame_align_error;
692         u64 rx_length_error;
693         u64 rx_unicast;
694         u64 rx_multicast;
695         u64 rx_broadcast;
696         u64 rx_packets;
697         u64 rx_errors_total;
698         u64 tx_errors_total;
699
700         /* version 2 stats */
701         u64 tx_deferral;
702         u64 tx_packets;
703         u64 rx_bytes;
704         u64 tx_pause;
705         u64 rx_pause;
706         u64 rx_drop_frame;
707 };
708
709 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
710 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
711
712 /* diagnostics */
713 #define NV_TEST_COUNT_BASE 3
714 #define NV_TEST_COUNT_EXTENDED 4
715
716 static const struct nv_ethtool_str nv_etests_str[] = {
717         { "link      (online/offline)" },
718         { "register  (offline)       " },
719         { "interrupt (offline)       " },
720         { "loopback  (offline)       " }
721 };
722
723 struct register_test {
724         __u32 reg;
725         __u32 mask;
726 };
727
728 static const struct register_test nv_registers_test[] = {
729         { NvRegUnknownSetupReg6, 0x01 },
730         { NvRegMisc1, 0x03c },
731         { NvRegOffloadConfig, 0x03ff },
732         { NvRegMulticastAddrA, 0xffffffff },
733         { NvRegTxWatermark, 0x0ff },
734         { NvRegWakeUpFlags, 0x07777 },
735         { 0,0 }
736 };
737
738 struct nv_skb_map {
739         struct sk_buff *skb;
740         dma_addr_t dma;
741         unsigned int dma_len;
742 };
743
744 /*
745  * SMP locking:
746  * All hardware access under dev->priv->lock, except the performance
747  * critical parts:
748  * - rx is (pseudo-) lockless: it relies on the single-threading provided
749  *      by the arch code for interrupts.
750  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
751  *      needs dev->priv->lock :-(
752  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
753  */
754
755 /* in dev: base, irq */
756 struct fe_priv {
757         spinlock_t lock;
758
759         struct net_device *dev;
760         struct napi_struct napi;
761
762         /* General data:
763          * Locking: spin_lock(&np->lock); */
764         struct nv_ethtool_stats estats;
765         int in_shutdown;
766         u32 linkspeed;
767         int duplex;
768         int autoneg;
769         int fixed_mode;
770         int phyaddr;
771         int wolenabled;
772         unsigned int phy_oui;
773         unsigned int phy_model;
774         u16 gigabit;
775         int intr_test;
776         int recover_error;
777
778         /* General data: RO fields */
779         dma_addr_t ring_addr;
780         struct pci_dev *pci_dev;
781         u32 orig_mac[2];
782         u32 irqmask;
783         u32 desc_ver;
784         u32 txrxctl_bits;
785         u32 vlanctl_bits;
786         u32 driver_data;
787         u32 register_size;
788         int rx_csum;
789         u32 mac_in_use;
790
791         void __iomem *base;
792
793         /* rx specific fields.
794          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
795          */
796         union ring_type get_rx, put_rx, first_rx, last_rx;
797         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
798         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
799         struct nv_skb_map *rx_skb;
800
801         union ring_type rx_ring;
802         unsigned int rx_buf_sz;
803         unsigned int pkt_limit;
804         struct timer_list oom_kick;
805         struct timer_list nic_poll;
806         struct timer_list stats_poll;
807         u32 nic_poll_irq;
808         int rx_ring_size;
809
810         /* media detection workaround.
811          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
812          */
813         int need_linktimer;
814         unsigned long link_timeout;
815         /*
816          * tx specific fields.
817          */
818         union ring_type get_tx, put_tx, first_tx, last_tx;
819         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
820         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
821         struct nv_skb_map *tx_skb;
822
823         union ring_type tx_ring;
824         u32 tx_flags;
825         int tx_ring_size;
826         int tx_stop;
827
828         /* vlan fields */
829         struct vlan_group *vlangrp;
830
831         /* msi/msi-x fields */
832         u32 msi_flags;
833         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
834
835         /* flow control */
836         u32 pause_flags;
837 };
838
839 /*
840  * Maximum number of loops until we assume that a bit in the irq mask
841  * is stuck. Overridable with module param.
842  */
843 static int max_interrupt_work = 5;
844
845 /*
846  * Optimization can be either throuput mode or cpu mode
847  *
848  * Throughput Mode: Every tx and rx packet will generate an interrupt.
849  * CPU Mode: Interrupts are controlled by a timer.
850  */
851 enum {
852         NV_OPTIMIZATION_MODE_THROUGHPUT,
853         NV_OPTIMIZATION_MODE_CPU
854 };
855 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
856
857 /*
858  * Poll interval for timer irq
859  *
860  * This interval determines how frequent an interrupt is generated.
861  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
862  * Min = 0, and Max = 65535
863  */
864 static int poll_interval = -1;
865
866 /*
867  * MSI interrupts
868  */
869 enum {
870         NV_MSI_INT_DISABLED,
871         NV_MSI_INT_ENABLED
872 };
873 static int msi = NV_MSI_INT_ENABLED;
874
875 /*
876  * MSIX interrupts
877  */
878 enum {
879         NV_MSIX_INT_DISABLED,
880         NV_MSIX_INT_ENABLED
881 };
882 static int msix = NV_MSIX_INT_DISABLED;
883
884 /*
885  * DMA 64bit
886  */
887 enum {
888         NV_DMA_64BIT_DISABLED,
889         NV_DMA_64BIT_ENABLED
890 };
891 static int dma_64bit = NV_DMA_64BIT_ENABLED;
892
893 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
894 {
895         return netdev_priv(dev);
896 }
897
898 static inline u8 __iomem *get_hwbase(struct net_device *dev)
899 {
900         return ((struct fe_priv *)netdev_priv(dev))->base;
901 }
902
903 static inline void pci_push(u8 __iomem *base)
904 {
905         /* force out pending posted writes */
906         readl(base);
907 }
908
909 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
910 {
911         return le32_to_cpu(prd->flaglen)
912                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
913 }
914
915 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
916 {
917         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
918 }
919
920 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
921                                 int delay, int delaymax, const char *msg)
922 {
923         u8 __iomem *base = get_hwbase(dev);
924
925         pci_push(base);
926         do {
927                 udelay(delay);
928                 delaymax -= delay;
929                 if (delaymax < 0) {
930                         if (msg)
931                                 printk(msg);
932                         return 1;
933                 }
934         } while ((readl(base + offset) & mask) != target);
935         return 0;
936 }
937
938 #define NV_SETUP_RX_RING 0x01
939 #define NV_SETUP_TX_RING 0x02
940
941 static inline u32 dma_low(dma_addr_t addr)
942 {
943         return addr;
944 }
945
946 static inline u32 dma_high(dma_addr_t addr)
947 {
948         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
949 }
950
951 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
952 {
953         struct fe_priv *np = get_nvpriv(dev);
954         u8 __iomem *base = get_hwbase(dev);
955
956         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
957                 if (rxtx_flags & NV_SETUP_RX_RING) {
958                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
959                 }
960                 if (rxtx_flags & NV_SETUP_TX_RING) {
961                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
962                 }
963         } else {
964                 if (rxtx_flags & NV_SETUP_RX_RING) {
965                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
966                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
967                 }
968                 if (rxtx_flags & NV_SETUP_TX_RING) {
969                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
970                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
971                 }
972         }
973 }
974
975 static void free_rings(struct net_device *dev)
976 {
977         struct fe_priv *np = get_nvpriv(dev);
978
979         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
980                 if (np->rx_ring.orig)
981                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
982                                             np->rx_ring.orig, np->ring_addr);
983         } else {
984                 if (np->rx_ring.ex)
985                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
986                                             np->rx_ring.ex, np->ring_addr);
987         }
988         if (np->rx_skb)
989                 kfree(np->rx_skb);
990         if (np->tx_skb)
991                 kfree(np->tx_skb);
992 }
993
994 static int using_multi_irqs(struct net_device *dev)
995 {
996         struct fe_priv *np = get_nvpriv(dev);
997
998         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
999             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1000              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1001                 return 0;
1002         else
1003                 return 1;
1004 }
1005
1006 static void nv_enable_irq(struct net_device *dev)
1007 {
1008         struct fe_priv *np = get_nvpriv(dev);
1009
1010         if (!using_multi_irqs(dev)) {
1011                 if (np->msi_flags & NV_MSI_X_ENABLED)
1012                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1013                 else
1014                         enable_irq(np->pci_dev->irq);
1015         } else {
1016                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1017                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1018                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1019         }
1020 }
1021
1022 static void nv_disable_irq(struct net_device *dev)
1023 {
1024         struct fe_priv *np = get_nvpriv(dev);
1025
1026         if (!using_multi_irqs(dev)) {
1027                 if (np->msi_flags & NV_MSI_X_ENABLED)
1028                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1029                 else
1030                         disable_irq(np->pci_dev->irq);
1031         } else {
1032                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1033                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1034                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1035         }
1036 }
1037
1038 /* In MSIX mode, a write to irqmask behaves as XOR */
1039 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1040 {
1041         u8 __iomem *base = get_hwbase(dev);
1042
1043         writel(mask, base + NvRegIrqMask);
1044 }
1045
1046 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1047 {
1048         struct fe_priv *np = get_nvpriv(dev);
1049         u8 __iomem *base = get_hwbase(dev);
1050
1051         if (np->msi_flags & NV_MSI_X_ENABLED) {
1052                 writel(mask, base + NvRegIrqMask);
1053         } else {
1054                 if (np->msi_flags & NV_MSI_ENABLED)
1055                         writel(0, base + NvRegMSIIrqMask);
1056                 writel(0, base + NvRegIrqMask);
1057         }
1058 }
1059
1060 #define MII_READ        (-1)
1061 /* mii_rw: read/write a register on the PHY.
1062  *
1063  * Caller must guarantee serialization
1064  */
1065 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1066 {
1067         u8 __iomem *base = get_hwbase(dev);
1068         u32 reg;
1069         int retval;
1070
1071         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1072
1073         reg = readl(base + NvRegMIIControl);
1074         if (reg & NVREG_MIICTL_INUSE) {
1075                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1076                 udelay(NV_MIIBUSY_DELAY);
1077         }
1078
1079         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1080         if (value != MII_READ) {
1081                 writel(value, base + NvRegMIIData);
1082                 reg |= NVREG_MIICTL_WRITE;
1083         }
1084         writel(reg, base + NvRegMIIControl);
1085
1086         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1087                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1088                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1089                                 dev->name, miireg, addr);
1090                 retval = -1;
1091         } else if (value != MII_READ) {
1092                 /* it was a write operation - fewer failures are detectable */
1093                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1094                                 dev->name, value, miireg, addr);
1095                 retval = 0;
1096         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1097                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1098                                 dev->name, miireg, addr);
1099                 retval = -1;
1100         } else {
1101                 retval = readl(base + NvRegMIIData);
1102                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1103                                 dev->name, miireg, addr, retval);
1104         }
1105
1106         return retval;
1107 }
1108
1109 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1110 {
1111         struct fe_priv *np = netdev_priv(dev);
1112         u32 miicontrol;
1113         unsigned int tries = 0;
1114
1115         miicontrol = BMCR_RESET | bmcr_setup;
1116         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1117                 return -1;
1118         }
1119
1120         /* wait for 500ms */
1121         msleep(500);
1122
1123         /* must wait till reset is deasserted */
1124         while (miicontrol & BMCR_RESET) {
1125                 msleep(10);
1126                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1127                 /* FIXME: 100 tries seem excessive */
1128                 if (tries++ > 100)
1129                         return -1;
1130         }
1131         return 0;
1132 }
1133
1134 static int phy_init(struct net_device *dev)
1135 {
1136         struct fe_priv *np = get_nvpriv(dev);
1137         u8 __iomem *base = get_hwbase(dev);
1138         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1139
1140         /* phy errata for E3016 phy */
1141         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1142                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1143                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1144                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1145                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1146                         return PHY_ERROR;
1147                 }
1148         }
1149         if (np->phy_oui == PHY_OUI_REALTEK) {
1150                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1151                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1152                         return PHY_ERROR;
1153                 }
1154                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1155                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1156                         return PHY_ERROR;
1157                 }
1158                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1159                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1160                         return PHY_ERROR;
1161                 }
1162                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1163                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1164                         return PHY_ERROR;
1165                 }
1166                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1167                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1168                         return PHY_ERROR;
1169                 }
1170         }
1171
1172         /* set advertise register */
1173         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1174         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1175         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1176                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1177                 return PHY_ERROR;
1178         }
1179
1180         /* get phy interface type */
1181         phyinterface = readl(base + NvRegPhyInterface);
1182
1183         /* see if gigabit phy */
1184         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1185         if (mii_status & PHY_GIGABIT) {
1186                 np->gigabit = PHY_GIGABIT;
1187                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1188                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1189                 if (phyinterface & PHY_RGMII)
1190                         mii_control_1000 |= ADVERTISE_1000FULL;
1191                 else
1192                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1193
1194                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1195                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1196                         return PHY_ERROR;
1197                 }
1198         }
1199         else
1200                 np->gigabit = 0;
1201
1202         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1203         mii_control |= BMCR_ANENABLE;
1204
1205         /* reset the phy
1206          * (certain phys need bmcr to be setup with reset)
1207          */
1208         if (phy_reset(dev, mii_control)) {
1209                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1210                 return PHY_ERROR;
1211         }
1212
1213         /* phy vendor specific configuration */
1214         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1215                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1216                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1217                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1218                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1219                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1220                         return PHY_ERROR;
1221                 }
1222                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1223                 phy_reserved |= PHY_CICADA_INIT5;
1224                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1225                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1226                         return PHY_ERROR;
1227                 }
1228         }
1229         if (np->phy_oui == PHY_OUI_CICADA) {
1230                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1231                 phy_reserved |= PHY_CICADA_INIT6;
1232                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1233                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1234                         return PHY_ERROR;
1235                 }
1236         }
1237         if (np->phy_oui == PHY_OUI_VITESSE) {
1238                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1239                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1240                         return PHY_ERROR;
1241                 }
1242                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1243                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1244                         return PHY_ERROR;
1245                 }
1246                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1247                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1248                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1249                         return PHY_ERROR;
1250                 }
1251                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1252                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1253                 phy_reserved |= PHY_VITESSE_INIT3;
1254                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1255                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1256                         return PHY_ERROR;
1257                 }
1258                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1259                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1260                         return PHY_ERROR;
1261                 }
1262                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1263                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1264                         return PHY_ERROR;
1265                 }
1266                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1267                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1268                 phy_reserved |= PHY_VITESSE_INIT3;
1269                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1270                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1271                         return PHY_ERROR;
1272                 }
1273                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1274                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1275                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1276                         return PHY_ERROR;
1277                 }
1278                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1279                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1280                         return PHY_ERROR;
1281                 }
1282                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1283                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284                         return PHY_ERROR;
1285                 }
1286                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1287                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1288                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1289                         return PHY_ERROR;
1290                 }
1291                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1292                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1293                 phy_reserved |= PHY_VITESSE_INIT8;
1294                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1295                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1296                         return PHY_ERROR;
1297                 }
1298                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1299                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1300                         return PHY_ERROR;
1301                 }
1302                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1303                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1304                         return PHY_ERROR;
1305                 }
1306         }
1307         if (np->phy_oui == PHY_OUI_REALTEK) {
1308                 /* reset could have cleared these out, set them back */
1309                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1310                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1311                         return PHY_ERROR;
1312                 }
1313                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1314                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1315                         return PHY_ERROR;
1316                 }
1317                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1318                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1319                         return PHY_ERROR;
1320                 }
1321                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1322                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1323                         return PHY_ERROR;
1324                 }
1325                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1326                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1327                         return PHY_ERROR;
1328                 }
1329         }
1330
1331         /* some phys clear out pause advertisment on reset, set it back */
1332         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1333
1334         /* restart auto negotiation */
1335         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1336         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1337         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1338                 return PHY_ERROR;
1339         }
1340
1341         return 0;
1342 }
1343
1344 static void nv_start_rx(struct net_device *dev)
1345 {
1346         struct fe_priv *np = netdev_priv(dev);
1347         u8 __iomem *base = get_hwbase(dev);
1348         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1349
1350         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1351         /* Already running? Stop it. */
1352         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1353                 rx_ctrl &= ~NVREG_RCVCTL_START;
1354                 writel(rx_ctrl, base + NvRegReceiverControl);
1355                 pci_push(base);
1356         }
1357         writel(np->linkspeed, base + NvRegLinkSpeed);
1358         pci_push(base);
1359         rx_ctrl |= NVREG_RCVCTL_START;
1360         if (np->mac_in_use)
1361                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1362         writel(rx_ctrl, base + NvRegReceiverControl);
1363         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1364                                 dev->name, np->duplex, np->linkspeed);
1365         pci_push(base);
1366 }
1367
1368 static void nv_stop_rx(struct net_device *dev)
1369 {
1370         struct fe_priv *np = netdev_priv(dev);
1371         u8 __iomem *base = get_hwbase(dev);
1372         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1373
1374         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1375         if (!np->mac_in_use)
1376                 rx_ctrl &= ~NVREG_RCVCTL_START;
1377         else
1378                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1379         writel(rx_ctrl, base + NvRegReceiverControl);
1380         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1381                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1382                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1383
1384         udelay(NV_RXSTOP_DELAY2);
1385         if (!np->mac_in_use)
1386                 writel(0, base + NvRegLinkSpeed);
1387 }
1388
1389 static void nv_start_tx(struct net_device *dev)
1390 {
1391         struct fe_priv *np = netdev_priv(dev);
1392         u8 __iomem *base = get_hwbase(dev);
1393         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1394
1395         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1396         tx_ctrl |= NVREG_XMITCTL_START;
1397         if (np->mac_in_use)
1398                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1399         writel(tx_ctrl, base + NvRegTransmitterControl);
1400         pci_push(base);
1401 }
1402
1403 static void nv_stop_tx(struct net_device *dev)
1404 {
1405         struct fe_priv *np = netdev_priv(dev);
1406         u8 __iomem *base = get_hwbase(dev);
1407         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1408
1409         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1410         if (!np->mac_in_use)
1411                 tx_ctrl &= ~NVREG_XMITCTL_START;
1412         else
1413                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1414         writel(tx_ctrl, base + NvRegTransmitterControl);
1415         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1416                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1417                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1418
1419         udelay(NV_TXSTOP_DELAY2);
1420         if (!np->mac_in_use)
1421                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1422                        base + NvRegTransmitPoll);
1423 }
1424
1425 static void nv_txrx_reset(struct net_device *dev)
1426 {
1427         struct fe_priv *np = netdev_priv(dev);
1428         u8 __iomem *base = get_hwbase(dev);
1429
1430         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1431         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1432         pci_push(base);
1433         udelay(NV_TXRX_RESET_DELAY);
1434         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1435         pci_push(base);
1436 }
1437
1438 static void nv_mac_reset(struct net_device *dev)
1439 {
1440         struct fe_priv *np = netdev_priv(dev);
1441         u8 __iomem *base = get_hwbase(dev);
1442         u32 temp1, temp2, temp3;
1443
1444         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1445
1446         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1447         pci_push(base);
1448
1449         /* save registers since they will be cleared on reset */
1450         temp1 = readl(base + NvRegMacAddrA);
1451         temp2 = readl(base + NvRegMacAddrB);
1452         temp3 = readl(base + NvRegTransmitPoll);
1453
1454         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1455         pci_push(base);
1456         udelay(NV_MAC_RESET_DELAY);
1457         writel(0, base + NvRegMacReset);
1458         pci_push(base);
1459         udelay(NV_MAC_RESET_DELAY);
1460
1461         /* restore saved registers */
1462         writel(temp1, base + NvRegMacAddrA);
1463         writel(temp2, base + NvRegMacAddrB);
1464         writel(temp3, base + NvRegTransmitPoll);
1465
1466         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1467         pci_push(base);
1468 }
1469
1470 static void nv_get_hw_stats(struct net_device *dev)
1471 {
1472         struct fe_priv *np = netdev_priv(dev);
1473         u8 __iomem *base = get_hwbase(dev);
1474
1475         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1476         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1477         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1478         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1479         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1480         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1481         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1482         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1483         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1484         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1485         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1486         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1487         np->estats.rx_runt += readl(base + NvRegRxRunt);
1488         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1489         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1490         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1491         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1492         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1493         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1494         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1495         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1496         np->estats.rx_packets =
1497                 np->estats.rx_unicast +
1498                 np->estats.rx_multicast +
1499                 np->estats.rx_broadcast;
1500         np->estats.rx_errors_total =
1501                 np->estats.rx_crc_errors +
1502                 np->estats.rx_over_errors +
1503                 np->estats.rx_frame_error +
1504                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1505                 np->estats.rx_late_collision +
1506                 np->estats.rx_runt +
1507                 np->estats.rx_frame_too_long;
1508         np->estats.tx_errors_total =
1509                 np->estats.tx_late_collision +
1510                 np->estats.tx_fifo_errors +
1511                 np->estats.tx_carrier_errors +
1512                 np->estats.tx_excess_deferral +
1513                 np->estats.tx_retry_error;
1514
1515         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1516                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1517                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1518                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1519                 np->estats.tx_pause += readl(base + NvRegTxPause);
1520                 np->estats.rx_pause += readl(base + NvRegRxPause);
1521                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1522         }
1523 }
1524
1525 /*
1526  * nv_get_stats: dev->get_stats function
1527  * Get latest stats value from the nic.
1528  * Called with read_lock(&dev_base_lock) held for read -
1529  * only synchronized against unregister_netdevice.
1530  */
1531 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1532 {
1533         struct fe_priv *np = netdev_priv(dev);
1534
1535         /* If the nic supports hw counters then retrieve latest values */
1536         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1537                 nv_get_hw_stats(dev);
1538
1539                 /* copy to net_device stats */
1540                 dev->stats.tx_bytes = np->estats.tx_bytes;
1541                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1542                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1543                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1544                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1545                 dev->stats.rx_errors = np->estats.rx_errors_total;
1546                 dev->stats.tx_errors = np->estats.tx_errors_total;
1547         }
1548
1549         return &dev->stats;
1550 }
1551
1552 /*
1553  * nv_alloc_rx: fill rx ring entries.
1554  * Return 1 if the allocations for the skbs failed and the
1555  * rx engine is without Available descriptors
1556  */
1557 static int nv_alloc_rx(struct net_device *dev)
1558 {
1559         struct fe_priv *np = netdev_priv(dev);
1560         struct ring_desc* less_rx;
1561
1562         less_rx = np->get_rx.orig;
1563         if (less_rx-- == np->first_rx.orig)
1564                 less_rx = np->last_rx.orig;
1565
1566         while (np->put_rx.orig != less_rx) {
1567                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1568                 if (skb) {
1569                         np->put_rx_ctx->skb = skb;
1570                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1571                                                              skb->data,
1572                                                              skb_tailroom(skb),
1573                                                              PCI_DMA_FROMDEVICE);
1574                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1575                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1576                         wmb();
1577                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1578                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1579                                 np->put_rx.orig = np->first_rx.orig;
1580                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1581                                 np->put_rx_ctx = np->first_rx_ctx;
1582                 } else {
1583                         return 1;
1584                 }
1585         }
1586         return 0;
1587 }
1588
1589 static int nv_alloc_rx_optimized(struct net_device *dev)
1590 {
1591         struct fe_priv *np = netdev_priv(dev);
1592         struct ring_desc_ex* less_rx;
1593
1594         less_rx = np->get_rx.ex;
1595         if (less_rx-- == np->first_rx.ex)
1596                 less_rx = np->last_rx.ex;
1597
1598         while (np->put_rx.ex != less_rx) {
1599                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1600                 if (skb) {
1601                         np->put_rx_ctx->skb = skb;
1602                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1603                                                              skb->data,
1604                                                              skb_tailroom(skb),
1605                                                              PCI_DMA_FROMDEVICE);
1606                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1607                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1608                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1609                         wmb();
1610                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1611                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1612                                 np->put_rx.ex = np->first_rx.ex;
1613                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1614                                 np->put_rx_ctx = np->first_rx_ctx;
1615                 } else {
1616                         return 1;
1617                 }
1618         }
1619         return 0;
1620 }
1621
1622 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1623 #ifdef CONFIG_FORCEDETH_NAPI
1624 static void nv_do_rx_refill(unsigned long data)
1625 {
1626         struct net_device *dev = (struct net_device *) data;
1627         struct fe_priv *np = netdev_priv(dev);
1628
1629         /* Just reschedule NAPI rx processing */
1630         netif_rx_schedule(dev, &np->napi);
1631 }
1632 #else
1633 static void nv_do_rx_refill(unsigned long data)
1634 {
1635         struct net_device *dev = (struct net_device *) data;
1636         struct fe_priv *np = netdev_priv(dev);
1637         int retcode;
1638
1639         if (!using_multi_irqs(dev)) {
1640                 if (np->msi_flags & NV_MSI_X_ENABLED)
1641                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1642                 else
1643                         disable_irq(np->pci_dev->irq);
1644         } else {
1645                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1646         }
1647         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1648                 retcode = nv_alloc_rx(dev);
1649         else
1650                 retcode = nv_alloc_rx_optimized(dev);
1651         if (retcode) {
1652                 spin_lock_irq(&np->lock);
1653                 if (!np->in_shutdown)
1654                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1655                 spin_unlock_irq(&np->lock);
1656         }
1657         if (!using_multi_irqs(dev)) {
1658                 if (np->msi_flags & NV_MSI_X_ENABLED)
1659                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1660                 else
1661                         enable_irq(np->pci_dev->irq);
1662         } else {
1663                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1664         }
1665 }
1666 #endif
1667
1668 static void nv_init_rx(struct net_device *dev)
1669 {
1670         struct fe_priv *np = netdev_priv(dev);
1671         int i;
1672         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1673         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1674                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1675         else
1676                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1677         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1678         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1679
1680         for (i = 0; i < np->rx_ring_size; i++) {
1681                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1682                         np->rx_ring.orig[i].flaglen = 0;
1683                         np->rx_ring.orig[i].buf = 0;
1684                 } else {
1685                         np->rx_ring.ex[i].flaglen = 0;
1686                         np->rx_ring.ex[i].txvlan = 0;
1687                         np->rx_ring.ex[i].bufhigh = 0;
1688                         np->rx_ring.ex[i].buflow = 0;
1689                 }
1690                 np->rx_skb[i].skb = NULL;
1691                 np->rx_skb[i].dma = 0;
1692         }
1693 }
1694
1695 static void nv_init_tx(struct net_device *dev)
1696 {
1697         struct fe_priv *np = netdev_priv(dev);
1698         int i;
1699         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1700         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1701                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1702         else
1703                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1704         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1705         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1706
1707         for (i = 0; i < np->tx_ring_size; i++) {
1708                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1709                         np->tx_ring.orig[i].flaglen = 0;
1710                         np->tx_ring.orig[i].buf = 0;
1711                 } else {
1712                         np->tx_ring.ex[i].flaglen = 0;
1713                         np->tx_ring.ex[i].txvlan = 0;
1714                         np->tx_ring.ex[i].bufhigh = 0;
1715                         np->tx_ring.ex[i].buflow = 0;
1716                 }
1717                 np->tx_skb[i].skb = NULL;
1718                 np->tx_skb[i].dma = 0;
1719         }
1720 }
1721
1722 static int nv_init_ring(struct net_device *dev)
1723 {
1724         struct fe_priv *np = netdev_priv(dev);
1725
1726         nv_init_tx(dev);
1727         nv_init_rx(dev);
1728         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1729                 return nv_alloc_rx(dev);
1730         else
1731                 return nv_alloc_rx_optimized(dev);
1732 }
1733
1734 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1735 {
1736         struct fe_priv *np = netdev_priv(dev);
1737
1738         if (tx_skb->dma) {
1739                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1740                                tx_skb->dma_len,
1741                                PCI_DMA_TODEVICE);
1742                 tx_skb->dma = 0;
1743         }
1744         if (tx_skb->skb) {
1745                 dev_kfree_skb_any(tx_skb->skb);
1746                 tx_skb->skb = NULL;
1747                 return 1;
1748         } else {
1749                 return 0;
1750         }
1751 }
1752
1753 static void nv_drain_tx(struct net_device *dev)
1754 {
1755         struct fe_priv *np = netdev_priv(dev);
1756         unsigned int i;
1757
1758         for (i = 0; i < np->tx_ring_size; i++) {
1759                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1760                         np->tx_ring.orig[i].flaglen = 0;
1761                         np->tx_ring.orig[i].buf = 0;
1762                 } else {
1763                         np->tx_ring.ex[i].flaglen = 0;
1764                         np->tx_ring.ex[i].txvlan = 0;
1765                         np->tx_ring.ex[i].bufhigh = 0;
1766                         np->tx_ring.ex[i].buflow = 0;
1767                 }
1768                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1769                         dev->stats.tx_dropped++;
1770         }
1771 }
1772
1773 static void nv_drain_rx(struct net_device *dev)
1774 {
1775         struct fe_priv *np = netdev_priv(dev);
1776         int i;
1777
1778         for (i = 0; i < np->rx_ring_size; i++) {
1779                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1780                         np->rx_ring.orig[i].flaglen = 0;
1781                         np->rx_ring.orig[i].buf = 0;
1782                 } else {
1783                         np->rx_ring.ex[i].flaglen = 0;
1784                         np->rx_ring.ex[i].txvlan = 0;
1785                         np->rx_ring.ex[i].bufhigh = 0;
1786                         np->rx_ring.ex[i].buflow = 0;
1787                 }
1788                 wmb();
1789                 if (np->rx_skb[i].skb) {
1790                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1791                                          (skb_end_pointer(np->rx_skb[i].skb) -
1792                                           np->rx_skb[i].skb->data),
1793                                          PCI_DMA_FROMDEVICE);
1794                         dev_kfree_skb(np->rx_skb[i].skb);
1795                         np->rx_skb[i].skb = NULL;
1796                 }
1797         }
1798 }
1799
1800 static void drain_ring(struct net_device *dev)
1801 {
1802         nv_drain_tx(dev);
1803         nv_drain_rx(dev);
1804 }
1805
1806 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1807 {
1808         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1809 }
1810
1811 /*
1812  * nv_start_xmit: dev->hard_start_xmit function
1813  * Called with netif_tx_lock held.
1814  */
1815 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1816 {
1817         struct fe_priv *np = netdev_priv(dev);
1818         u32 tx_flags = 0;
1819         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1820         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1821         unsigned int i;
1822         u32 offset = 0;
1823         u32 bcnt;
1824         u32 size = skb->len-skb->data_len;
1825         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1826         u32 empty_slots;
1827         struct ring_desc* put_tx;
1828         struct ring_desc* start_tx;
1829         struct ring_desc* prev_tx;
1830         struct nv_skb_map* prev_tx_ctx;
1831
1832         /* add fragments to entries count */
1833         for (i = 0; i < fragments; i++) {
1834                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1835                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1836         }
1837
1838         empty_slots = nv_get_empty_tx_slots(np);
1839         if (unlikely(empty_slots <= entries)) {
1840                 spin_lock_irq(&np->lock);
1841                 netif_stop_queue(dev);
1842                 np->tx_stop = 1;
1843                 spin_unlock_irq(&np->lock);
1844                 return NETDEV_TX_BUSY;
1845         }
1846
1847         start_tx = put_tx = np->put_tx.orig;
1848
1849         /* setup the header buffer */
1850         do {
1851                 prev_tx = put_tx;
1852                 prev_tx_ctx = np->put_tx_ctx;
1853                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1854                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1855                                                 PCI_DMA_TODEVICE);
1856                 np->put_tx_ctx->dma_len = bcnt;
1857                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1858                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1859
1860                 tx_flags = np->tx_flags;
1861                 offset += bcnt;
1862                 size -= bcnt;
1863                 if (unlikely(put_tx++ == np->last_tx.orig))
1864                         put_tx = np->first_tx.orig;
1865                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1866                         np->put_tx_ctx = np->first_tx_ctx;
1867         } while (size);
1868
1869         /* setup the fragments */
1870         for (i = 0; i < fragments; i++) {
1871                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1872                 u32 size = frag->size;
1873                 offset = 0;
1874
1875                 do {
1876                         prev_tx = put_tx;
1877                         prev_tx_ctx = np->put_tx_ctx;
1878                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1879                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1880                                                            PCI_DMA_TODEVICE);
1881                         np->put_tx_ctx->dma_len = bcnt;
1882                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1883                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1884
1885                         offset += bcnt;
1886                         size -= bcnt;
1887                         if (unlikely(put_tx++ == np->last_tx.orig))
1888                                 put_tx = np->first_tx.orig;
1889                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1890                                 np->put_tx_ctx = np->first_tx_ctx;
1891                 } while (size);
1892         }
1893
1894         /* set last fragment flag  */
1895         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1896
1897         /* save skb in this slot's context area */
1898         prev_tx_ctx->skb = skb;
1899
1900         if (skb_is_gso(skb))
1901                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1902         else
1903                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1904                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1905
1906         spin_lock_irq(&np->lock);
1907
1908         /* set tx flags */
1909         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1910         np->put_tx.orig = put_tx;
1911
1912         spin_unlock_irq(&np->lock);
1913
1914         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1915                 dev->name, entries, tx_flags_extra);
1916         {
1917                 int j;
1918                 for (j=0; j<64; j++) {
1919                         if ((j%16) == 0)
1920                                 dprintk("\n%03x:", j);
1921                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1922                 }
1923                 dprintk("\n");
1924         }
1925
1926         dev->trans_start = jiffies;
1927         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1928         return NETDEV_TX_OK;
1929 }
1930
1931 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1932 {
1933         struct fe_priv *np = netdev_priv(dev);
1934         u32 tx_flags = 0;
1935         u32 tx_flags_extra;
1936         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1937         unsigned int i;
1938         u32 offset = 0;
1939         u32 bcnt;
1940         u32 size = skb->len-skb->data_len;
1941         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1942         u32 empty_slots;
1943         struct ring_desc_ex* put_tx;
1944         struct ring_desc_ex* start_tx;
1945         struct ring_desc_ex* prev_tx;
1946         struct nv_skb_map* prev_tx_ctx;
1947
1948         /* add fragments to entries count */
1949         for (i = 0; i < fragments; i++) {
1950                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1951                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1952         }
1953
1954         empty_slots = nv_get_empty_tx_slots(np);
1955         if (unlikely(empty_slots <= entries)) {
1956                 spin_lock_irq(&np->lock);
1957                 netif_stop_queue(dev);
1958                 np->tx_stop = 1;
1959                 spin_unlock_irq(&np->lock);
1960                 return NETDEV_TX_BUSY;
1961         }
1962
1963         start_tx = put_tx = np->put_tx.ex;
1964
1965         /* setup the header buffer */
1966         do {
1967                 prev_tx = put_tx;
1968                 prev_tx_ctx = np->put_tx_ctx;
1969                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1970                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1971                                                 PCI_DMA_TODEVICE);
1972                 np->put_tx_ctx->dma_len = bcnt;
1973                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
1974                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
1975                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1976
1977                 tx_flags = NV_TX2_VALID;
1978                 offset += bcnt;
1979                 size -= bcnt;
1980                 if (unlikely(put_tx++ == np->last_tx.ex))
1981                         put_tx = np->first_tx.ex;
1982                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1983                         np->put_tx_ctx = np->first_tx_ctx;
1984         } while (size);
1985
1986         /* setup the fragments */
1987         for (i = 0; i < fragments; i++) {
1988                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1989                 u32 size = frag->size;
1990                 offset = 0;
1991
1992                 do {
1993                         prev_tx = put_tx;
1994                         prev_tx_ctx = np->put_tx_ctx;
1995                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1996                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1997                                                            PCI_DMA_TODEVICE);
1998                         np->put_tx_ctx->dma_len = bcnt;
1999                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2000                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2001                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2002
2003                         offset += bcnt;
2004                         size -= bcnt;
2005                         if (unlikely(put_tx++ == np->last_tx.ex))
2006                                 put_tx = np->first_tx.ex;
2007                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2008                                 np->put_tx_ctx = np->first_tx_ctx;
2009                 } while (size);
2010         }
2011
2012         /* set last fragment flag  */
2013         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2014
2015         /* save skb in this slot's context area */
2016         prev_tx_ctx->skb = skb;
2017
2018         if (skb_is_gso(skb))
2019                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2020         else
2021                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2022                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2023
2024         /* vlan tag */
2025         if (likely(!np->vlangrp)) {
2026                 start_tx->txvlan = 0;
2027         } else {
2028                 if (vlan_tx_tag_present(skb))
2029                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2030                 else
2031                         start_tx->txvlan = 0;
2032         }
2033
2034         spin_lock_irq(&np->lock);
2035
2036         /* set tx flags */
2037         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2038         np->put_tx.ex = put_tx;
2039
2040         spin_unlock_irq(&np->lock);
2041
2042         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2043                 dev->name, entries, tx_flags_extra);
2044         {
2045                 int j;
2046                 for (j=0; j<64; j++) {
2047                         if ((j%16) == 0)
2048                                 dprintk("\n%03x:", j);
2049                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2050                 }
2051                 dprintk("\n");
2052         }
2053
2054         dev->trans_start = jiffies;
2055         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2056         return NETDEV_TX_OK;
2057 }
2058
2059 /*
2060  * nv_tx_done: check for completed packets, release the skbs.
2061  *
2062  * Caller must own np->lock.
2063  */
2064 static void nv_tx_done(struct net_device *dev)
2065 {
2066         struct fe_priv *np = netdev_priv(dev);
2067         u32 flags;
2068         struct ring_desc* orig_get_tx = np->get_tx.orig;
2069
2070         while ((np->get_tx.orig != np->put_tx.orig) &&
2071                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2072
2073                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2074                                         dev->name, flags);
2075
2076                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2077                                np->get_tx_ctx->dma_len,
2078                                PCI_DMA_TODEVICE);
2079                 np->get_tx_ctx->dma = 0;
2080
2081                 if (np->desc_ver == DESC_VER_1) {
2082                         if (flags & NV_TX_LASTPACKET) {
2083                                 if (flags & NV_TX_ERROR) {
2084                                         if (flags & NV_TX_UNDERFLOW)
2085                                                 dev->stats.tx_fifo_errors++;
2086                                         if (flags & NV_TX_CARRIERLOST)
2087                                                 dev->stats.tx_carrier_errors++;
2088                                         dev->stats.tx_errors++;
2089                                 } else {
2090                                         dev->stats.tx_packets++;
2091                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2092                                 }
2093                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2094                                 np->get_tx_ctx->skb = NULL;
2095                         }
2096                 } else {
2097                         if (flags & NV_TX2_LASTPACKET) {
2098                                 if (flags & NV_TX2_ERROR) {
2099                                         if (flags & NV_TX2_UNDERFLOW)
2100                                                 dev->stats.tx_fifo_errors++;
2101                                         if (flags & NV_TX2_CARRIERLOST)
2102                                                 dev->stats.tx_carrier_errors++;
2103                                         dev->stats.tx_errors++;
2104                                 } else {
2105                                         dev->stats.tx_packets++;
2106                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2107                                 }
2108                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2109                                 np->get_tx_ctx->skb = NULL;
2110                         }
2111                 }
2112                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2113                         np->get_tx.orig = np->first_tx.orig;
2114                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2115                         np->get_tx_ctx = np->first_tx_ctx;
2116         }
2117         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2118                 np->tx_stop = 0;
2119                 netif_wake_queue(dev);
2120         }
2121 }
2122
2123 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2124 {
2125         struct fe_priv *np = netdev_priv(dev);
2126         u32 flags;
2127         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2128
2129         while ((np->get_tx.ex != np->put_tx.ex) &&
2130                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2131                (limit-- > 0)) {
2132
2133                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2134                                         dev->name, flags);
2135
2136                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2137                                np->get_tx_ctx->dma_len,
2138                                PCI_DMA_TODEVICE);
2139                 np->get_tx_ctx->dma = 0;
2140
2141                 if (flags & NV_TX2_LASTPACKET) {
2142                         if (!(flags & NV_TX2_ERROR))
2143                                 dev->stats.tx_packets++;
2144                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2145                         np->get_tx_ctx->skb = NULL;
2146                 }
2147                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2148                         np->get_tx.ex = np->first_tx.ex;
2149                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2150                         np->get_tx_ctx = np->first_tx_ctx;
2151         }
2152         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2153                 np->tx_stop = 0;
2154                 netif_wake_queue(dev);
2155         }
2156 }
2157
2158 /*
2159  * nv_tx_timeout: dev->tx_timeout function
2160  * Called with netif_tx_lock held.
2161  */
2162 static void nv_tx_timeout(struct net_device *dev)
2163 {
2164         struct fe_priv *np = netdev_priv(dev);
2165         u8 __iomem *base = get_hwbase(dev);
2166         u32 status;
2167
2168         if (np->msi_flags & NV_MSI_X_ENABLED)
2169                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2170         else
2171                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2172
2173         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2174
2175         {
2176                 int i;
2177
2178                 printk(KERN_INFO "%s: Ring at %lx\n",
2179                        dev->name, (unsigned long)np->ring_addr);
2180                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2181                 for (i=0;i<=np->register_size;i+= 32) {
2182                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2183                                         i,
2184                                         readl(base + i + 0), readl(base + i + 4),
2185                                         readl(base + i + 8), readl(base + i + 12),
2186                                         readl(base + i + 16), readl(base + i + 20),
2187                                         readl(base + i + 24), readl(base + i + 28));
2188                 }
2189                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2190                 for (i=0;i<np->tx_ring_size;i+= 4) {
2191                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2192                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2193                                        i,
2194                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2195                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2196                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2197                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2198                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2199                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2200                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2201                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2202                         } else {
2203                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2204                                        i,
2205                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2206                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2207                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2208                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2209                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2210                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2211                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2212                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2213                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2214                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2215                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2216                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2217                         }
2218                 }
2219         }
2220
2221         spin_lock_irq(&np->lock);
2222
2223         /* 1) stop tx engine */
2224         nv_stop_tx(dev);
2225
2226         /* 2) check that the packets were not sent already: */
2227         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2228                 nv_tx_done(dev);
2229         else
2230                 nv_tx_done_optimized(dev, np->tx_ring_size);
2231
2232         /* 3) if there are dead entries: clear everything */
2233         if (np->get_tx_ctx != np->put_tx_ctx) {
2234                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2235                 nv_drain_tx(dev);
2236                 nv_init_tx(dev);
2237                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2238         }
2239
2240         netif_wake_queue(dev);
2241
2242         /* 4) restart tx engine */
2243         nv_start_tx(dev);
2244         spin_unlock_irq(&np->lock);
2245 }
2246
2247 /*
2248  * Called when the nic notices a mismatch between the actual data len on the
2249  * wire and the len indicated in the 802 header
2250  */
2251 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2252 {
2253         int hdrlen;     /* length of the 802 header */
2254         int protolen;   /* length as stored in the proto field */
2255
2256         /* 1) calculate len according to header */
2257         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2258                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2259                 hdrlen = VLAN_HLEN;
2260         } else {
2261                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2262                 hdrlen = ETH_HLEN;
2263         }
2264         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2265                                 dev->name, datalen, protolen, hdrlen);
2266         if (protolen > ETH_DATA_LEN)
2267                 return datalen; /* Value in proto field not a len, no checks possible */
2268
2269         protolen += hdrlen;
2270         /* consistency checks: */
2271         if (datalen > ETH_ZLEN) {
2272                 if (datalen >= protolen) {
2273                         /* more data on wire than in 802 header, trim of
2274                          * additional data.
2275                          */
2276                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2277                                         dev->name, protolen);
2278                         return protolen;
2279                 } else {
2280                         /* less data on wire than mentioned in header.
2281                          * Discard the packet.
2282                          */
2283                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2284                                         dev->name);
2285                         return -1;
2286                 }
2287         } else {
2288                 /* short packet. Accept only if 802 values are also short */
2289                 if (protolen > ETH_ZLEN) {
2290                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2291                                         dev->name);
2292                         return -1;
2293                 }
2294                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2295                                 dev->name, datalen);
2296                 return datalen;
2297         }
2298 }
2299
2300 static int nv_rx_process(struct net_device *dev, int limit)
2301 {
2302         struct fe_priv *np = netdev_priv(dev);
2303         u32 flags;
2304         int rx_work = 0;
2305         struct sk_buff *skb;
2306         int len;
2307
2308         while((np->get_rx.orig != np->put_rx.orig) &&
2309               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2310                 (rx_work < limit)) {
2311
2312                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2313                                         dev->name, flags);
2314
2315                 /*
2316                  * the packet is for us - immediately tear down the pci mapping.
2317                  * TODO: check if a prefetch of the first cacheline improves
2318                  * the performance.
2319                  */
2320                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2321                                 np->get_rx_ctx->dma_len,
2322                                 PCI_DMA_FROMDEVICE);
2323                 skb = np->get_rx_ctx->skb;
2324                 np->get_rx_ctx->skb = NULL;
2325
2326                 {
2327                         int j;
2328                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2329                         for (j=0; j<64; j++) {
2330                                 if ((j%16) == 0)
2331                                         dprintk("\n%03x:", j);
2332                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2333                         }
2334                         dprintk("\n");
2335                 }
2336                 /* look at what we actually got: */
2337                 if (np->desc_ver == DESC_VER_1) {
2338                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2339                                 len = flags & LEN_MASK_V1;
2340                                 if (unlikely(flags & NV_RX_ERROR)) {
2341                                         if (flags & NV_RX_ERROR4) {
2342                                                 len = nv_getlen(dev, skb->data, len);
2343                                                 if (len < 0) {
2344                                                         dev->stats.rx_errors++;
2345                                                         dev_kfree_skb(skb);
2346                                                         goto next_pkt;
2347                                                 }
2348                                         }
2349                                         /* framing errors are soft errors */
2350                                         else if (flags & NV_RX_FRAMINGERR) {
2351                                                 if (flags & NV_RX_SUBSTRACT1) {
2352                                                         len--;
2353                                                 }
2354                                         }
2355                                         /* the rest are hard errors */
2356                                         else {
2357                                                 if (flags & NV_RX_MISSEDFRAME)
2358                                                         dev->stats.rx_missed_errors++;
2359                                                 if (flags & NV_RX_CRCERR)
2360                                                         dev->stats.rx_crc_errors++;
2361                                                 if (flags & NV_RX_OVERFLOW)
2362                                                         dev->stats.rx_over_errors++;
2363                                                 dev->stats.rx_errors++;
2364                                                 dev_kfree_skb(skb);
2365                                                 goto next_pkt;
2366                                         }
2367                                 }
2368                         } else {
2369                                 dev_kfree_skb(skb);
2370                                 goto next_pkt;
2371                         }
2372                 } else {
2373                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2374                                 len = flags & LEN_MASK_V2;
2375                                 if (unlikely(flags & NV_RX2_ERROR)) {
2376                                         if (flags & NV_RX2_ERROR4) {
2377                                                 len = nv_getlen(dev, skb->data, len);
2378                                                 if (len < 0) {
2379                                                         dev->stats.rx_errors++;
2380                                                         dev_kfree_skb(skb);
2381                                                         goto next_pkt;
2382                                                 }
2383                                         }
2384                                         /* framing errors are soft errors */
2385                                         else if (flags & NV_RX2_FRAMINGERR) {
2386                                                 if (flags & NV_RX2_SUBSTRACT1) {
2387                                                         len--;
2388                                                 }
2389                                         }
2390                                         /* the rest are hard errors */
2391                                         else {
2392                                                 if (flags & NV_RX2_CRCERR)
2393                                                         dev->stats.rx_crc_errors++;
2394                                                 if (flags & NV_RX2_OVERFLOW)
2395                                                         dev->stats.rx_over_errors++;
2396                                                 dev->stats.rx_errors++;
2397                                                 dev_kfree_skb(skb);
2398                                                 goto next_pkt;
2399                                         }
2400                                 }
2401                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2402                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2403                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2404                         } else {
2405                                 dev_kfree_skb(skb);
2406                                 goto next_pkt;
2407                         }
2408                 }
2409                 /* got a valid packet - forward it to the network core */
2410                 skb_put(skb, len);
2411                 skb->protocol = eth_type_trans(skb, dev);
2412                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2413                                         dev->name, len, skb->protocol);
2414 #ifdef CONFIG_FORCEDETH_NAPI
2415                 netif_receive_skb(skb);
2416 #else
2417                 netif_rx(skb);
2418 #endif
2419                 dev->last_rx = jiffies;
2420                 dev->stats.rx_packets++;
2421                 dev->stats.rx_bytes += len;
2422 next_pkt:
2423                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2424                         np->get_rx.orig = np->first_rx.orig;
2425                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2426                         np->get_rx_ctx = np->first_rx_ctx;
2427
2428                 rx_work++;
2429         }
2430
2431         return rx_work;
2432 }
2433
2434 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2435 {
2436         struct fe_priv *np = netdev_priv(dev);
2437         u32 flags;
2438         u32 vlanflags = 0;
2439         int rx_work = 0;
2440         struct sk_buff *skb;
2441         int len;
2442
2443         while((np->get_rx.ex != np->put_rx.ex) &&
2444               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2445               (rx_work < limit)) {
2446
2447                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2448                                         dev->name, flags);
2449
2450                 /*
2451                  * the packet is for us - immediately tear down the pci mapping.
2452                  * TODO: check if a prefetch of the first cacheline improves
2453                  * the performance.
2454                  */
2455                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2456                                 np->get_rx_ctx->dma_len,
2457                                 PCI_DMA_FROMDEVICE);
2458                 skb = np->get_rx_ctx->skb;
2459                 np->get_rx_ctx->skb = NULL;
2460
2461                 {
2462                         int j;
2463                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2464                         for (j=0; j<64; j++) {
2465                                 if ((j%16) == 0)
2466                                         dprintk("\n%03x:", j);
2467                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2468                         }
2469                         dprintk("\n");
2470                 }
2471                 /* look at what we actually got: */
2472                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2473                         len = flags & LEN_MASK_V2;
2474                         if (unlikely(flags & NV_RX2_ERROR)) {
2475                                 if (flags & NV_RX2_ERROR4) {
2476                                         len = nv_getlen(dev, skb->data, len);
2477                                         if (len < 0) {
2478                                                 dev_kfree_skb(skb);
2479                                                 goto next_pkt;
2480                                         }
2481                                 }
2482                                 /* framing errors are soft errors */
2483                                 else if (flags & NV_RX2_FRAMINGERR) {
2484                                         if (flags & NV_RX2_SUBSTRACT1) {
2485                                                 len--;
2486                                         }
2487                                 }
2488                                 /* the rest are hard errors */
2489                                 else {
2490                                         dev_kfree_skb(skb);
2491                                         goto next_pkt;
2492                                 }
2493                         }
2494
2495                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2496                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2497                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2498
2499                         /* got a valid packet - forward it to the network core */
2500                         skb_put(skb, len);
2501                         skb->protocol = eth_type_trans(skb, dev);
2502                         prefetch(skb->data);
2503
2504                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2505                                 dev->name, len, skb->protocol);
2506
2507                         if (likely(!np->vlangrp)) {
2508 #ifdef CONFIG_FORCEDETH_NAPI
2509                                 netif_receive_skb(skb);
2510 #else
2511                                 netif_rx(skb);
2512 #endif
2513                         } else {
2514                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2515                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2516 #ifdef CONFIG_FORCEDETH_NAPI
2517                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2518                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2519 #else
2520                                         vlan_hwaccel_rx(skb, np->vlangrp,
2521                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2522 #endif
2523                                 } else {
2524 #ifdef CONFIG_FORCEDETH_NAPI
2525                                         netif_receive_skb(skb);
2526 #else
2527                                         netif_rx(skb);
2528 #endif
2529                                 }
2530                         }
2531
2532                         dev->last_rx = jiffies;
2533                         dev->stats.rx_packets++;
2534                         dev->stats.rx_bytes += len;
2535                 } else {
2536                         dev_kfree_skb(skb);
2537                 }
2538 next_pkt:
2539                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2540                         np->get_rx.ex = np->first_rx.ex;
2541                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2542                         np->get_rx_ctx = np->first_rx_ctx;
2543
2544                 rx_work++;
2545         }
2546
2547         return rx_work;
2548 }
2549
2550 static void set_bufsize(struct net_device *dev)
2551 {
2552         struct fe_priv *np = netdev_priv(dev);
2553
2554         if (dev->mtu <= ETH_DATA_LEN)
2555                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2556         else
2557                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2558 }
2559
2560 /*
2561  * nv_change_mtu: dev->change_mtu function
2562  * Called with dev_base_lock held for read.
2563  */
2564 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2565 {
2566         struct fe_priv *np = netdev_priv(dev);
2567         int old_mtu;
2568
2569         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2570                 return -EINVAL;
2571
2572         old_mtu = dev->mtu;
2573         dev->mtu = new_mtu;
2574
2575         /* return early if the buffer sizes will not change */
2576         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2577                 return 0;
2578         if (old_mtu == new_mtu)
2579                 return 0;
2580
2581         /* synchronized against open : rtnl_lock() held by caller */
2582         if (netif_running(dev)) {
2583                 u8 __iomem *base = get_hwbase(dev);
2584                 /*
2585                  * It seems that the nic preloads valid ring entries into an
2586                  * internal buffer. The procedure for flushing everything is
2587                  * guessed, there is probably a simpler approach.
2588                  * Changing the MTU is a rare event, it shouldn't matter.
2589                  */
2590                 nv_disable_irq(dev);
2591                 netif_tx_lock_bh(dev);
2592                 spin_lock(&np->lock);
2593                 /* stop engines */
2594                 nv_stop_rx(dev);
2595                 nv_stop_tx(dev);
2596                 nv_txrx_reset(dev);
2597                 /* drain rx queue */
2598                 nv_drain_rx(dev);
2599                 nv_drain_tx(dev);
2600                 /* reinit driver view of the rx queue */
2601                 set_bufsize(dev);
2602                 if (nv_init_ring(dev)) {
2603                         if (!np->in_shutdown)
2604                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2605                 }
2606                 /* reinit nic view of the rx queue */
2607                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2608                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2609                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2610                         base + NvRegRingSizes);
2611                 pci_push(base);
2612                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2613                 pci_push(base);
2614
2615                 /* restart rx engine */
2616                 nv_start_rx(dev);
2617                 nv_start_tx(dev);
2618                 spin_unlock(&np->lock);
2619                 netif_tx_unlock_bh(dev);
2620                 nv_enable_irq(dev);
2621         }
2622         return 0;
2623 }
2624
2625 static void nv_copy_mac_to_hw(struct net_device *dev)
2626 {
2627         u8 __iomem *base = get_hwbase(dev);
2628         u32 mac[2];
2629
2630         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2631                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2632         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2633
2634         writel(mac[0], base + NvRegMacAddrA);
2635         writel(mac[1], base + NvRegMacAddrB);
2636 }
2637
2638 /*
2639  * nv_set_mac_address: dev->set_mac_address function
2640  * Called with rtnl_lock() held.
2641  */
2642 static int nv_set_mac_address(struct net_device *dev, void *addr)
2643 {
2644         struct fe_priv *np = netdev_priv(dev);
2645         struct sockaddr *macaddr = (struct sockaddr*)addr;
2646
2647         if (!is_valid_ether_addr(macaddr->sa_data))
2648                 return -EADDRNOTAVAIL;
2649
2650         /* synchronized against open : rtnl_lock() held by caller */
2651         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2652
2653         if (netif_running(dev)) {
2654                 netif_tx_lock_bh(dev);
2655                 spin_lock_irq(&np->lock);
2656
2657                 /* stop rx engine */
2658                 nv_stop_rx(dev);
2659
2660                 /* set mac address */
2661                 nv_copy_mac_to_hw(dev);
2662
2663                 /* restart rx engine */
2664                 nv_start_rx(dev);
2665                 spin_unlock_irq(&np->lock);
2666                 netif_tx_unlock_bh(dev);
2667         } else {
2668                 nv_copy_mac_to_hw(dev);
2669         }
2670         return 0;
2671 }
2672
2673 /*
2674  * nv_set_multicast: dev->set_multicast function
2675  * Called with netif_tx_lock held.
2676  */
2677 static void nv_set_multicast(struct net_device *dev)
2678 {
2679         struct fe_priv *np = netdev_priv(dev);
2680         u8 __iomem *base = get_hwbase(dev);
2681         u32 addr[2];
2682         u32 mask[2];
2683         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2684
2685         memset(addr, 0, sizeof(addr));
2686         memset(mask, 0, sizeof(mask));
2687
2688         if (dev->flags & IFF_PROMISC) {
2689                 pff |= NVREG_PFF_PROMISC;
2690         } else {
2691                 pff |= NVREG_PFF_MYADDR;
2692
2693                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2694                         u32 alwaysOff[2];
2695                         u32 alwaysOn[2];
2696
2697                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2698                         if (dev->flags & IFF_ALLMULTI) {
2699                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2700                         } else {
2701                                 struct dev_mc_list *walk;
2702
2703                                 walk = dev->mc_list;
2704                                 while (walk != NULL) {
2705                                         u32 a, b;
2706                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2707                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2708                                         alwaysOn[0] &= a;
2709                                         alwaysOff[0] &= ~a;
2710                                         alwaysOn[1] &= b;
2711                                         alwaysOff[1] &= ~b;
2712                                         walk = walk->next;
2713                                 }
2714                         }
2715                         addr[0] = alwaysOn[0];
2716                         addr[1] = alwaysOn[1];
2717                         mask[0] = alwaysOn[0] | alwaysOff[0];
2718                         mask[1] = alwaysOn[1] | alwaysOff[1];
2719                 } else {
2720                         mask[0] = NVREG_MCASTMASKA_NONE;
2721                         mask[1] = NVREG_MCASTMASKB_NONE;
2722                 }
2723         }
2724         addr[0] |= NVREG_MCASTADDRA_FORCE;
2725         pff |= NVREG_PFF_ALWAYS;
2726         spin_lock_irq(&np->lock);
2727         nv_stop_rx(dev);
2728         writel(addr[0], base + NvRegMulticastAddrA);
2729         writel(addr[1], base + NvRegMulticastAddrB);
2730         writel(mask[0], base + NvRegMulticastMaskA);
2731         writel(mask[1], base + NvRegMulticastMaskB);
2732         writel(pff, base + NvRegPacketFilterFlags);
2733         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2734                 dev->name);
2735         nv_start_rx(dev);
2736         spin_unlock_irq(&np->lock);
2737 }
2738
2739 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2740 {
2741         struct fe_priv *np = netdev_priv(dev);
2742         u8 __iomem *base = get_hwbase(dev);
2743
2744         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2745
2746         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2747                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2748                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2749                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2750                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2751                 } else {
2752                         writel(pff, base + NvRegPacketFilterFlags);
2753                 }
2754         }
2755         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2756                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2757                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2758                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2759                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2760                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2761                 } else {
2762                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2763                         writel(regmisc, base + NvRegMisc1);
2764                 }
2765         }
2766 }
2767
2768 /**
2769  * nv_update_linkspeed: Setup the MAC according to the link partner
2770  * @dev: Network device to be configured
2771  *
2772  * The function queries the PHY and checks if there is a link partner.
2773  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2774  * set to 10 MBit HD.
2775  *
2776  * The function returns 0 if there is no link partner and 1 if there is
2777  * a good link partner.
2778  */
2779 static int nv_update_linkspeed(struct net_device *dev)
2780 {
2781         struct fe_priv *np = netdev_priv(dev);
2782         u8 __iomem *base = get_hwbase(dev);
2783         int adv = 0;
2784         int lpa = 0;
2785         int adv_lpa, adv_pause, lpa_pause;
2786         int newls = np->linkspeed;
2787         int newdup = np->duplex;
2788         int mii_status;
2789         int retval = 0;
2790         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2791         u32 txrxFlags = 0;
2792         u32 phy_exp;
2793
2794         /* BMSR_LSTATUS is latched, read it twice:
2795          * we want the current value.
2796          */
2797         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2798         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2799
2800         if (!(mii_status & BMSR_LSTATUS)) {
2801                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2802                                 dev->name);
2803                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2804                 newdup = 0;
2805                 retval = 0;
2806                 goto set_speed;
2807         }
2808
2809         if (np->autoneg == 0) {
2810                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2811                                 dev->name, np->fixed_mode);
2812                 if (np->fixed_mode & LPA_100FULL) {
2813                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2814                         newdup = 1;
2815                 } else if (np->fixed_mode & LPA_100HALF) {
2816                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2817                         newdup = 0;
2818                 } else if (np->fixed_mode & LPA_10FULL) {
2819                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2820                         newdup = 1;
2821                 } else {
2822                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2823                         newdup = 0;
2824                 }
2825                 retval = 1;
2826                 goto set_speed;
2827         }
2828         /* check auto negotiation is complete */
2829         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2830                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2831                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2832                 newdup = 0;
2833                 retval = 0;
2834                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2835                 goto set_speed;
2836         }
2837
2838         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2839         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2840         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2841                                 dev->name, adv, lpa);
2842
2843         retval = 1;
2844         if (np->gigabit == PHY_GIGABIT) {
2845                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2846                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2847
2848                 if ((control_1000 & ADVERTISE_1000FULL) &&
2849                         (status_1000 & LPA_1000FULL)) {
2850                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2851                                 dev->name);
2852                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2853                         newdup = 1;
2854                         goto set_speed;
2855                 }
2856         }
2857
2858         /* FIXME: handle parallel detection properly */
2859         adv_lpa = lpa & adv;
2860         if (adv_lpa & LPA_100FULL) {
2861                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2862                 newdup = 1;
2863         } else if (adv_lpa & LPA_100HALF) {
2864                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2865                 newdup = 0;
2866         } else if (adv_lpa & LPA_10FULL) {
2867                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2868                 newdup = 1;
2869         } else if (adv_lpa & LPA_10HALF) {
2870                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2871                 newdup = 0;
2872         } else {
2873                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2874                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2875                 newdup = 0;
2876         }
2877
2878 set_speed:
2879         if (np->duplex == newdup && np->linkspeed == newls)
2880                 return retval;
2881
2882         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2883                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2884
2885         np->duplex = newdup;
2886         np->linkspeed = newls;
2887
2888         /* The transmitter and receiver must be restarted for safe update */
2889         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
2890                 txrxFlags |= NV_RESTART_TX;
2891                 nv_stop_tx(dev);
2892         }
2893         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
2894                 txrxFlags |= NV_RESTART_RX;
2895                 nv_stop_rx(dev);
2896         }
2897
2898         if (np->gigabit == PHY_GIGABIT) {
2899                 phyreg = readl(base + NvRegRandomSeed);
2900                 phyreg &= ~(0x3FF00);
2901                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2902                         phyreg |= NVREG_RNDSEED_FORCE3;
2903                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2904                         phyreg |= NVREG_RNDSEED_FORCE2;
2905                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2906                         phyreg |= NVREG_RNDSEED_FORCE;
2907                 writel(phyreg, base + NvRegRandomSeed);
2908         }
2909
2910         phyreg = readl(base + NvRegPhyInterface);
2911         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2912         if (np->duplex == 0)
2913                 phyreg |= PHY_HALF;
2914         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2915                 phyreg |= PHY_100;
2916         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2917                 phyreg |= PHY_1000;
2918         writel(phyreg, base + NvRegPhyInterface);
2919
2920         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
2921         if (phyreg & PHY_RGMII) {
2922                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
2923                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2924                 } else {
2925                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
2926                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
2927                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
2928                                 else
2929                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
2930                         } else {
2931                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2932                         }
2933                 }
2934         } else {
2935                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
2936                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
2937                 else
2938                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
2939         }
2940         writel(txreg, base + NvRegTxDeferral);
2941
2942         if (np->desc_ver == DESC_VER_1) {
2943                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2944         } else {
2945                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2946                         txreg = NVREG_TX_WM_DESC2_3_1000;
2947                 else
2948                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2949         }
2950         writel(txreg, base + NvRegTxWatermark);
2951
2952         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2953                 base + NvRegMisc1);
2954         pci_push(base);
2955         writel(np->linkspeed, base + NvRegLinkSpeed);
2956         pci_push(base);
2957
2958         pause_flags = 0;
2959         /* setup pause frame */
2960         if (np->duplex != 0) {
2961                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2962                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2963                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2964
2965                         switch (adv_pause) {
2966                         case ADVERTISE_PAUSE_CAP:
2967                                 if (lpa_pause & LPA_PAUSE_CAP) {
2968                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2969                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2970                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2971                                 }
2972                                 break;
2973                         case ADVERTISE_PAUSE_ASYM:
2974                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2975                                 {
2976                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2977                                 }
2978                                 break;
2979                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2980                                 if (lpa_pause & LPA_PAUSE_CAP)
2981                                 {
2982                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2983                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2984                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2985                                 }
2986                                 if (lpa_pause == LPA_PAUSE_ASYM)
2987                                 {
2988                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2989                                 }
2990                                 break;
2991                         }
2992                 } else {
2993                         pause_flags = np->pause_flags;
2994                 }
2995         }
2996         nv_update_pause(dev, pause_flags);
2997
2998         if (txrxFlags & NV_RESTART_TX)
2999                 nv_start_tx(dev);
3000         if (txrxFlags & NV_RESTART_RX)
3001                 nv_start_rx(dev);
3002
3003         return retval;
3004 }
3005
3006 static void nv_linkchange(struct net_device *dev)
3007 {
3008         if (nv_update_linkspeed(dev)) {
3009                 if (!netif_carrier_ok(dev)) {
3010                         netif_carrier_on(dev);
3011                         printk(KERN_INFO "%s: link up.\n", dev->name);
3012                         nv_start_rx(dev);
3013                 }
3014         } else {
3015                 if (netif_carrier_ok(dev)) {
3016                         netif_carrier_off(dev);
3017                         printk(KERN_INFO "%s: link down.\n", dev->name);
3018                         nv_stop_rx(dev);
3019                 }
3020         }
3021 }
3022
3023 static void nv_link_irq(struct net_device *dev)
3024 {
3025         u8 __iomem *base = get_hwbase(dev);
3026         u32 miistat;
3027
3028         miistat = readl(base + NvRegMIIStatus);
3029         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3030         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3031
3032         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3033                 nv_linkchange(dev);
3034         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3035 }
3036
3037 static irqreturn_t nv_nic_irq(int foo, void *data)
3038 {
3039         struct net_device *dev = (struct net_device *) data;
3040         struct fe_priv *np = netdev_priv(dev);
3041         u8 __iomem *base = get_hwbase(dev);
3042         u32 events;
3043         int i;
3044
3045         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3046
3047         for (i=0; ; i++) {
3048                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3049                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3050                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3051                 } else {
3052                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3053                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3054                 }
3055                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3056                 if (!(events & np->irqmask))
3057                         break;
3058
3059                 spin_lock(&np->lock);
3060                 nv_tx_done(dev);
3061                 spin_unlock(&np->lock);
3062
3063 #ifdef CONFIG_FORCEDETH_NAPI
3064                 if (events & NVREG_IRQ_RX_ALL) {
3065                         netif_rx_schedule(dev, &np->napi);
3066
3067                         /* Disable furthur receive irq's */
3068                         spin_lock(&np->lock);
3069                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3070
3071                         if (np->msi_flags & NV_MSI_X_ENABLED)
3072                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3073                         else
3074                                 writel(np->irqmask, base + NvRegIrqMask);
3075                         spin_unlock(&np->lock);
3076                 }
3077 #else
3078                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3079                         if (unlikely(nv_alloc_rx(dev))) {
3080                                 spin_lock(&np->lock);
3081                                 if (!np->in_shutdown)
3082                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3083                                 spin_unlock(&np->lock);
3084                         }
3085                 }
3086 #endif
3087                 if (unlikely(events & NVREG_IRQ_LINK)) {
3088                         spin_lock(&np->lock);
3089                         nv_link_irq(dev);
3090                         spin_unlock(&np->lock);
3091                 }
3092                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3093                         spin_lock(&np->lock);
3094                         nv_linkchange(dev);
3095                         spin_unlock(&np->lock);
3096                         np->link_timeout = jiffies + LINK_TIMEOUT;
3097                 }
3098                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3099                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3100                                                 dev->name, events);
3101                 }
3102                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3103                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3104                                                 dev->name, events);
3105                 }
3106                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3107                         spin_lock(&np->lock);
3108                         /* disable interrupts on the nic */
3109                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3110                                 writel(0, base + NvRegIrqMask);
3111                         else
3112                                 writel(np->irqmask, base + NvRegIrqMask);
3113                         pci_push(base);
3114
3115                         if (!np->in_shutdown) {
3116                                 np->nic_poll_irq = np->irqmask;
3117                                 np->recover_error = 1;
3118                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3119                         }
3120                         spin_unlock(&np->lock);
3121                         break;
3122                 }
3123                 if (unlikely(i > max_interrupt_work)) {
3124                         spin_lock(&np->lock);
3125                         /* disable interrupts on the nic */
3126                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3127                                 writel(0, base + NvRegIrqMask);
3128                         else
3129                                 writel(np->irqmask, base + NvRegIrqMask);
3130                         pci_push(base);
3131
3132                         if (!np->in_shutdown) {
3133                                 np->nic_poll_irq = np->irqmask;
3134                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3135                         }
3136                         spin_unlock(&np->lock);
3137                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3138                         break;
3139                 }
3140
3141         }
3142         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3143
3144         return IRQ_RETVAL(i);
3145 }
3146
3147 /**
3148  * All _optimized functions are used to help increase performance
3149  * (reduce CPU and increase throughput). They use descripter version 3,
3150  * compiler directives, and reduce memory accesses.
3151  */
3152 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3153 {
3154         struct net_device *dev = (struct net_device *) data;
3155         struct fe_priv *np = netdev_priv(dev);
3156         u8 __iomem *base = get_hwbase(dev);
3157         u32 events;
3158         int i;
3159
3160         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3161
3162         for (i=0; ; i++) {
3163                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3164                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3165                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3166                 } else {
3167                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3168                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3169                 }
3170                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3171                 if (!(events & np->irqmask))
3172                         break;
3173
3174                 spin_lock(&np->lock);
3175                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3176                 spin_unlock(&np->lock);
3177
3178 #ifdef CONFIG_FORCEDETH_NAPI
3179                 if (events & NVREG_IRQ_RX_ALL) {
3180                         netif_rx_schedule(dev, &np->napi);
3181
3182                         /* Disable furthur receive irq's */
3183                         spin_lock(&np->lock);
3184                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3185
3186                         if (np->msi_flags & NV_MSI_X_ENABLED)
3187                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3188                         else
3189                                 writel(np->irqmask, base + NvRegIrqMask);
3190                         spin_unlock(&np->lock);
3191                 }
3192 #else
3193                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3194                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3195                                 spin_lock(&np->lock);
3196                                 if (!np->in_shutdown)
3197                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3198                                 spin_unlock(&np->lock);
3199                         }
3200                 }
3201 #endif
3202                 if (unlikely(events & NVREG_IRQ_LINK)) {
3203                         spin_lock(&np->lock);
3204                         nv_link_irq(dev);
3205                         spin_unlock(&np->lock);
3206                 }
3207                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3208                         spin_lock(&np->lock);
3209                         nv_linkchange(dev);
3210                         spin_unlock(&np->lock);
3211                         np->link_timeout = jiffies + LINK_TIMEOUT;
3212                 }
3213                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3214                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3215                                                 dev->name, events);
3216                 }
3217                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3218                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3219                                                 dev->name, events);
3220                 }
3221                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3222                         spin_lock(&np->lock);
3223                         /* disable interrupts on the nic */
3224                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3225                                 writel(0, base + NvRegIrqMask);
3226                         else
3227                                 writel(np->irqmask, base + NvRegIrqMask);
3228                         pci_push(base);
3229
3230                         if (!np->in_shutdown) {
3231                                 np->nic_poll_irq = np->irqmask;
3232                                 np->recover_error = 1;
3233                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3234                         }
3235                         spin_unlock(&np->lock);
3236                         break;
3237                 }
3238
3239                 if (unlikely(i > max_interrupt_work)) {
3240                         spin_lock(&np->lock);
3241                         /* disable interrupts on the nic */
3242                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3243                                 writel(0, base + NvRegIrqMask);
3244                         else
3245                                 writel(np->irqmask, base + NvRegIrqMask);
3246                         pci_push(base);
3247
3248                         if (!np->in_shutdown) {
3249                                 np->nic_poll_irq = np->irqmask;
3250                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3251                         }
3252                         spin_unlock(&np->lock);
3253                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3254                         break;
3255                 }
3256
3257         }
3258         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3259
3260         return IRQ_RETVAL(i);
3261 }
3262
3263 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3264 {
3265         struct net_device *dev = (struct net_device *) data;
3266         struct fe_priv *np = netdev_priv(dev);
3267         u8 __iomem *base = get_hwbase(dev);
3268         u32 events;
3269         int i;
3270         unsigned long flags;
3271
3272         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3273
3274         for (i=0; ; i++) {
3275                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3276                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3277                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3278                 if (!(events & np->irqmask))
3279                         break;
3280
3281                 spin_lock_irqsave(&np->lock, flags);
3282                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3283                 spin_unlock_irqrestore(&np->lock, flags);
3284
3285                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3286                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3287                                                 dev->name, events);
3288                 }
3289                 if (unlikely(i > max_interrupt_work)) {
3290                         spin_lock_irqsave(&np->lock, flags);
3291                         /* disable interrupts on the nic */
3292                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3293                         pci_push(base);
3294
3295                         if (!np->in_shutdown) {
3296                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3297                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3298                         }
3299                         spin_unlock_irqrestore(&np->lock, flags);
3300                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3301                         break;
3302                 }
3303
3304         }
3305         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3306
3307         return IRQ_RETVAL(i);
3308 }
3309
3310 #ifdef CONFIG_FORCEDETH_NAPI
3311 static int nv_napi_poll(struct napi_struct *napi, int budget)
3312 {
3313         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3314         struct net_device *dev = np->dev;
3315         u8 __iomem *base = get_hwbase(dev);
3316         unsigned long flags;
3317         int pkts, retcode;
3318
3319         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3320                 pkts = nv_rx_process(dev, budget);
3321                 retcode = nv_alloc_rx(dev);
3322         } else {
3323                 pkts = nv_rx_process_optimized(dev, budget);
3324                 retcode = nv_alloc_rx_optimized(dev);
3325         }
3326
3327         if (retcode) {
3328                 spin_lock_irqsave(&np->lock, flags);
3329                 if (!np->in_shutdown)
3330                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3331                 spin_unlock_irqrestore(&np->lock, flags);
3332         }
3333
3334         if (pkts < budget) {
3335                 /* re-enable receive interrupts */
3336                 spin_lock_irqsave(&np->lock, flags);
3337
3338                 __netif_rx_complete(dev, napi);
3339
3340                 np->irqmask |= NVREG_IRQ_RX_ALL;
3341                 if (np->msi_flags & NV_MSI_X_ENABLED)
3342                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3343                 else
3344                         writel(np->irqmask, base + NvRegIrqMask);
3345
3346                 spin_unlock_irqrestore(&np->lock, flags);
3347         }
3348         return pkts;
3349 }
3350 #endif
3351
3352 #ifdef CONFIG_FORCEDETH_NAPI
3353 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3354 {
3355         struct net_device *dev = (struct net_device *) data;
3356         struct fe_priv *np = netdev_priv(dev);
3357         u8 __iomem *base = get_hwbase(dev);
3358         u32 events;
3359
3360         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3361         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3362
3363         if (events) {
3364                 netif_rx_schedule(dev, &np->napi);
3365                 /* disable receive interrupts on the nic */
3366                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3367                 pci_push(base);
3368         }
3369         return IRQ_HANDLED;
3370 }
3371 #else
3372 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3373 {
3374         struct net_device *dev = (struct net_device *) data;
3375         struct fe_priv *np = netdev_priv(dev);
3376         u8 __iomem *base = get_hwbase(dev);
3377         u32 events;
3378         int i;
3379         unsigned long flags;
3380
3381         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3382
3383         for (i=0; ; i++) {
3384                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3385                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3386                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3387                 if (!(events & np->irqmask))
3388                         break;
3389
3390                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3391                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3392                                 spin_lock_irqsave(&np->lock, flags);
3393                                 if (!np->in_shutdown)
3394                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3395                                 spin_unlock_irqrestore(&np->lock, flags);
3396                         }
3397                 }
3398
3399                 if (unlikely(i > max_interrupt_work)) {
3400                         spin_lock_irqsave(&np->lock, flags);
3401                         /* disable interrupts on the nic */
3402                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3403                         pci_push(base);
3404
3405                         if (!np->in_shutdown) {
3406                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3407                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3408                         }
3409                         spin_unlock_irqrestore(&np->lock, flags);
3410                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3411                         break;
3412                 }
3413         }
3414         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3415
3416         return IRQ_RETVAL(i);
3417 }
3418 #endif
3419
3420 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3421 {
3422         struct net_device *dev = (struct net_device *) data;
3423         struct fe_priv *np = netdev_priv(dev);
3424         u8 __iomem *base = get_hwbase(dev);
3425         u32 events;
3426         int i;
3427         unsigned long flags;
3428
3429         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3430
3431         for (i=0; ; i++) {
3432                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3433                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3434                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3435                 if (!(events & np->irqmask))
3436                         break;
3437
3438                 /* check tx in case we reached max loop limit in tx isr */
3439                 spin_lock_irqsave(&np->lock, flags);
3440                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3441                 spin_unlock_irqrestore(&np->lock, flags);
3442
3443                 if (events & NVREG_IRQ_LINK) {
3444                         spin_lock_irqsave(&np->lock, flags);
3445                         nv_link_irq(dev);
3446                         spin_unlock_irqrestore(&np->lock, flags);
3447                 }
3448                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3449                         spin_lock_irqsave(&np->lock, flags);
3450                         nv_linkchange(dev);
3451                         spin_unlock_irqrestore(&np->lock, flags);
3452                         np->link_timeout = jiffies + LINK_TIMEOUT;
3453                 }
3454                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3455                         spin_lock_irq(&np->lock);
3456                         /* disable interrupts on the nic */
3457                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3458                         pci_push(base);
3459
3460                         if (!np->in_shutdown) {
3461                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3462                                 np->recover_error = 1;
3463                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3464                         }
3465                         spin_unlock_irq(&np->lock);
3466                         break;
3467                 }
3468                 if (events & (NVREG_IRQ_UNKNOWN)) {
3469                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3470                                                 dev->name, events);
3471                 }
3472                 if (unlikely(i > max_interrupt_work)) {
3473                         spin_lock_irqsave(&np->lock, flags);
3474                         /* disable interrupts on the nic */
3475                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3476                         pci_push(base);
3477
3478                         if (!np->in_shutdown) {
3479                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3480                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3481                         }
3482                         spin_unlock_irqrestore(&np->lock, flags);
3483                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3484                         break;
3485                 }
3486
3487         }
3488         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3489
3490         return IRQ_RETVAL(i);
3491 }
3492
3493 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3494 {
3495         struct net_device *dev = (struct net_device *) data;
3496         struct fe_priv *np = netdev_priv(dev);
3497         u8 __iomem *base = get_hwbase(dev);
3498         u32 events;
3499
3500         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3501
3502         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3503                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3504                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3505         } else {
3506                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3507                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3508         }
3509         pci_push(base);
3510         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3511         if (!(events & NVREG_IRQ_TIMER))
3512                 return IRQ_RETVAL(0);
3513
3514         spin_lock(&np->lock);
3515         np->intr_test = 1;
3516         spin_unlock(&np->lock);
3517
3518         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3519
3520         return IRQ_RETVAL(1);
3521 }
3522
3523 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3524 {
3525         u8 __iomem *base = get_hwbase(dev);
3526         int i;
3527         u32 msixmap = 0;
3528
3529         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3530          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3531          * the remaining 8 interrupts.
3532          */
3533         for (i = 0; i < 8; i++) {
3534                 if ((irqmask >> i) & 0x1) {
3535                         msixmap |= vector << (i << 2);
3536                 }
3537         }
3538         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3539
3540         msixmap = 0;
3541         for (i = 0; i < 8; i++) {
3542                 if ((irqmask >> (i + 8)) & 0x1) {
3543                         msixmap |= vector << (i << 2);
3544                 }
3545         }
3546         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3547 }
3548
3549 static int nv_request_irq(struct net_device *dev, int intr_test)
3550 {
3551         struct fe_priv *np = get_nvpriv(dev);
3552         u8 __iomem *base = get_hwbase(dev);
3553         int ret = 1;
3554         int i;
3555         irqreturn_t (*handler)(int foo, void *data);
3556
3557         if (intr_test) {
3558                 handler = nv_nic_irq_test;
3559         } else {
3560                 if (np->desc_ver == DESC_VER_3)
3561                         handler = nv_nic_irq_optimized;
3562                 else
3563                         handler = nv_nic_irq;
3564         }
3565
3566         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3567                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3568                         np->msi_x_entry[i].entry = i;
3569                 }
3570                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3571                         np->msi_flags |= NV_MSI_X_ENABLED;
3572                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3573                                 /* Request irq for rx handling */
3574                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3575                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3576                                         pci_disable_msix(np->pci_dev);
3577                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3578                                         goto out_err;
3579                                 }
3580                                 /* Request irq for tx handling */
3581                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3582                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3583                                         pci_disable_msix(np->pci_dev);
3584                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3585                                         goto out_free_rx;
3586                                 }
3587                                 /* Request irq for link and timer handling */
3588                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3589                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3590                                         pci_disable_msix(np->pci_dev);
3591                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3592                                         goto out_free_tx;
3593                                 }
3594                                 /* map interrupts to their respective vector */
3595                                 writel(0, base + NvRegMSIXMap0);
3596                                 writel(0, base + NvRegMSIXMap1);
3597                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3598                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3599                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3600                         } else {
3601                                 /* Request irq for all interrupts */
3602                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3603                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3604                                         pci_disable_msix(np->pci_dev);
3605                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3606                                         goto out_err;
3607                                 }
3608
3609                                 /* map interrupts to vector 0 */
3610                                 writel(0, base + NvRegMSIXMap0);
3611                                 writel(0, base + NvRegMSIXMap1);
3612                         }
3613                 }
3614         }
3615         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3616                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3617                         np->msi_flags |= NV_MSI_ENABLED;
3618                         dev->irq = np->pci_dev->irq;
3619                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3620                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3621                                 pci_disable_msi(np->pci_dev);
3622                                 np->msi_flags &= ~NV_MSI_ENABLED;
3623                                 dev->irq = np->pci_dev->irq;
3624                                 goto out_err;
3625                         }
3626
3627                         /* map interrupts to vector 0 */
3628                         writel(0, base + NvRegMSIMap0);
3629                         writel(0, base + NvRegMSIMap1);
3630                         /* enable msi vector 0 */
3631                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3632                 }
3633         }
3634         if (ret != 0) {
3635                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3636                         goto out_err;
3637
3638         }
3639
3640         return 0;
3641 out_free_tx:
3642         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3643 out_free_rx:
3644         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3645 out_err:
3646         return 1;
3647 }
3648
3649 static void nv_free_irq(struct net_device *dev)
3650 {
3651         struct fe_priv *np = get_nvpriv(dev);
3652         int i;
3653
3654         if (np->msi_flags & NV_MSI_X_ENABLED) {
3655                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3656                         free_irq(np->msi_x_entry[i].vector, dev);
3657                 }
3658                 pci_disable_msix(np->pci_dev);
3659                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3660         } else {
3661                 free_irq(np->pci_dev->irq, dev);
3662                 if (np->msi_flags & NV_MSI_ENABLED) {
3663                         pci_disable_msi(np->pci_dev);
3664                         np->msi_flags &= ~NV_MSI_ENABLED;
3665                 }
3666         }
3667 }
3668
3669 static void nv_do_nic_poll(unsigned long data)
3670 {
3671         struct net_device *dev = (struct net_device *) data;
3672         struct fe_priv *np = netdev_priv(dev);
3673         u8 __iomem *base = get_hwbase(dev);
3674         u32 mask = 0;
3675
3676         /*
3677          * First disable irq(s) and then
3678          * reenable interrupts on the nic, we have to do this before calling
3679          * nv_nic_irq because that may decide to do otherwise
3680          */
3681
3682         if (!using_multi_irqs(dev)) {
3683                 if (np->msi_flags & NV_MSI_X_ENABLED)
3684                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3685                 else
3686                         disable_irq_lockdep(np->pci_dev->irq);
3687                 mask = np->irqmask;
3688         } else {
3689                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3690                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3691                         mask |= NVREG_IRQ_RX_ALL;
3692                 }
3693                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3694                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3695                         mask |= NVREG_IRQ_TX_ALL;
3696                 }
3697                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3698                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3699                         mask |= NVREG_IRQ_OTHER;
3700                 }
3701         }
3702         np->nic_poll_irq = 0;
3703
3704         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3705
3706         if (np->recover_error) {
3707                 np->recover_error = 0;
3708                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3709                 if (netif_running(dev)) {
3710                         netif_tx_lock_bh(dev);
3711                         spin_lock(&np->lock);
3712                         /* stop engines */
3713                         nv_stop_rx(dev);
3714                         nv_stop_tx(dev);
3715                         nv_txrx_reset(dev);
3716                         /* drain rx queue */
3717                         nv_drain_rx(dev);
3718                         nv_drain_tx(dev);
3719                         /* reinit driver view of the rx queue */
3720                         set_bufsize(dev);
3721                         if (nv_init_ring(dev)) {
3722                                 if (!np->in_shutdown)
3723                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3724                         }
3725                         /* reinit nic view of the rx queue */
3726                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3727                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3728                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3729                                 base + NvRegRingSizes);
3730                         pci_push(base);
3731                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3732                         pci_push(base);
3733
3734                         /* restart rx engine */
3735                         nv_start_rx(dev);
3736                         nv_start_tx(dev);
3737                         spin_unlock(&np->lock);
3738                         netif_tx_unlock_bh(dev);
3739                 }
3740         }
3741
3742
3743         writel(mask, base + NvRegIrqMask);
3744         pci_push(base);
3745
3746         if (!using_multi_irqs(dev)) {
3747                 if (np->desc_ver == DESC_VER_3)
3748                         nv_nic_irq_optimized(0, dev);
3749                 else
3750                         nv_nic_irq(0, dev);
3751                 if (np->msi_flags & NV_MSI_X_ENABLED)
3752                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3753                 else
3754                         enable_irq_lockdep(np->pci_dev->irq);
3755         } else {
3756                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3757                         nv_nic_irq_rx(0, dev);
3758                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3759                 }
3760                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3761                         nv_nic_irq_tx(0, dev);
3762                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3763                 }
3764                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3765                         nv_nic_irq_other(0, dev);
3766                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3767                 }
3768         }
3769 }
3770
3771 #ifdef CONFIG_NET_POLL_CONTROLLER
3772 static void nv_poll_controller(struct net_device *dev)
3773 {
3774         nv_do_nic_poll((unsigned long) dev);
3775 }
3776 #endif
3777
3778 static void nv_do_stats_poll(unsigned long data)
3779 {
3780         struct net_device *dev = (struct net_device *) data;
3781         struct fe_priv *np = netdev_priv(dev);
3782
3783         nv_get_hw_stats(dev);
3784
3785         if (!np->in_shutdown)
3786                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3787 }
3788
3789 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3790 {
3791         struct fe_priv *np = netdev_priv(dev);
3792         strcpy(info->driver, DRV_NAME);
3793         strcpy(info->version, FORCEDETH_VERSION);
3794         strcpy(info->bus_info, pci_name(np->pci_dev));
3795 }
3796
3797 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3798 {
3799         struct fe_priv *np = netdev_priv(dev);
3800         wolinfo->supported = WAKE_MAGIC;
3801
3802         spin_lock_irq(&np->lock);
3803         if (np->wolenabled)
3804                 wolinfo->wolopts = WAKE_MAGIC;
3805         spin_unlock_irq(&np->lock);
3806 }
3807
3808 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3809 {
3810         struct fe_priv *np = netdev_priv(dev);
3811         u8 __iomem *base = get_hwbase(dev);
3812         u32 flags = 0;
3813
3814         if (wolinfo->wolopts == 0) {
3815                 np->wolenabled = 0;
3816         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3817                 np->wolenabled = 1;
3818                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3819         }
3820         if (netif_running(dev)) {
3821                 spin_lock_irq(&np->lock);
3822                 writel(flags, base + NvRegWakeUpFlags);
3823                 spin_unlock_irq(&np->lock);
3824         }
3825         return 0;
3826 }
3827
3828 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3829 {
3830         struct fe_priv *np = netdev_priv(dev);
3831         int adv;
3832
3833         spin_lock_irq(&np->lock);
3834         ecmd->port = PORT_MII;
3835         if (!netif_running(dev)) {
3836                 /* We do not track link speed / duplex setting if the
3837                  * interface is disabled. Force a link check */
3838                 if (nv_update_linkspeed(dev)) {
3839                         if (!netif_carrier_ok(dev))
3840                                 netif_carrier_on(dev);
3841                 } else {
3842                         if (netif_carrier_ok(dev))
3843                                 netif_carrier_off(dev);
3844                 }
3845         }
3846
3847         if (netif_carrier_ok(dev)) {
3848                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3849                 case NVREG_LINKSPEED_10:
3850                         ecmd->speed = SPEED_10;
3851                         break;
3852                 case NVREG_LINKSPEED_100:
3853                         ecmd->speed = SPEED_100;
3854                         break;
3855                 case NVREG_LINKSPEED_1000:
3856                         ecmd->speed = SPEED_1000;
3857                         break;
3858                 }
3859                 ecmd->duplex = DUPLEX_HALF;
3860                 if (np->duplex)
3861                         ecmd->duplex = DUPLEX_FULL;
3862         } else {
3863                 ecmd->speed = -1;
3864                 ecmd->duplex = -1;
3865         }
3866
3867         ecmd->autoneg = np->autoneg;
3868
3869         ecmd->advertising = ADVERTISED_MII;
3870         if (np->autoneg) {
3871                 ecmd->advertising |= ADVERTISED_Autoneg;
3872                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3873                 if (adv & ADVERTISE_10HALF)
3874                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3875                 if (adv & ADVERTISE_10FULL)
3876                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3877                 if (adv & ADVERTISE_100HALF)
3878                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3879                 if (adv & ADVERTISE_100FULL)
3880                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3881                 if (np->gigabit == PHY_GIGABIT) {
3882                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3883                         if (adv & ADVERTISE_1000FULL)
3884                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3885                 }
3886         }
3887         ecmd->supported = (SUPPORTED_Autoneg |
3888                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3889                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3890                 SUPPORTED_MII);
3891         if (np->gigabit == PHY_GIGABIT)
3892                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3893
3894         ecmd->phy_address = np->phyaddr;
3895         ecmd->transceiver = XCVR_EXTERNAL;
3896
3897         /* ignore maxtxpkt, maxrxpkt for now */
3898         spin_unlock_irq(&np->lock);
3899         return 0;
3900 }
3901
3902 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3903 {
3904         struct fe_priv *np = netdev_priv(dev);
3905
3906         if (ecmd->port != PORT_MII)
3907                 return -EINVAL;
3908         if (ecmd->transceiver != XCVR_EXTERNAL)
3909                 return -EINVAL;
3910         if (ecmd->phy_address != np->phyaddr) {
3911                 /* TODO: support switching between multiple phys. Should be
3912                  * trivial, but not enabled due to lack of test hardware. */
3913                 return -EINVAL;
3914         }
3915         if (ecmd->autoneg == AUTONEG_ENABLE) {
3916                 u32 mask;
3917
3918                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3919                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3920                 if (np->gigabit == PHY_GIGABIT)
3921                         mask |= ADVERTISED_1000baseT_Full;
3922
3923                 if ((ecmd->advertising & mask) == 0)
3924                         return -EINVAL;
3925
3926         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3927                 /* Note: autonegotiation disable, speed 1000 intentionally
3928                  * forbidden - noone should need that. */
3929
3930                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3931                         return -EINVAL;
3932                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3933                         return -EINVAL;
3934         } else {
3935                 return -EINVAL;
3936         }
3937
3938         netif_carrier_off(dev);
3939         if (netif_running(dev)) {
3940                 nv_disable_irq(dev);
3941                 netif_tx_lock_bh(dev);
3942                 spin_lock(&np->lock);
3943                 /* stop engines */
3944                 nv_stop_rx(dev);
3945                 nv_stop_tx(dev);
3946                 spin_unlock(&np->lock);
3947                 netif_tx_unlock_bh(dev);
3948         }
3949
3950         if (ecmd->autoneg == AUTONEG_ENABLE) {
3951                 int adv, bmcr;
3952
3953                 np->autoneg = 1;
3954
3955                 /* advertise only what has been requested */
3956                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3957                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3958                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3959                         adv |= ADVERTISE_10HALF;
3960                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3961                         adv |= ADVERTISE_10FULL;
3962                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3963                         adv |= ADVERTISE_100HALF;
3964                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3965                         adv |= ADVERTISE_100FULL;
3966                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3967                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3968                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3969                         adv |=  ADVERTISE_PAUSE_ASYM;
3970                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3971
3972                 if (np->gigabit == PHY_GIGABIT) {
3973                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3974                         adv &= ~ADVERTISE_1000FULL;
3975                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3976                                 adv |= ADVERTISE_1000FULL;
3977                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3978                 }
3979
3980                 if (netif_running(dev))
3981                         printk(KERN_INFO "%s: link down.\n", dev->name);
3982                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3983                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3984                         bmcr |= BMCR_ANENABLE;
3985                         /* reset the phy in order for settings to stick,
3986                          * and cause autoneg to start */
3987                         if (phy_reset(dev, bmcr)) {
3988                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3989                                 return -EINVAL;
3990                         }
3991                 } else {
3992                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3993                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3994                 }
3995         } else {
3996                 int adv, bmcr;
3997
3998                 np->autoneg = 0;
3999
4000                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4001                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4002                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4003                         adv |= ADVERTISE_10HALF;
4004                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4005                         adv |= ADVERTISE_10FULL;
4006                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4007                         adv |= ADVERTISE_100HALF;
4008                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4009                         adv |= ADVERTISE_100FULL;
4010                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4011                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4012                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4013                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4014                 }
4015                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4016                         adv |=  ADVERTISE_PAUSE_ASYM;
4017                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4018                 }
4019                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4020                 np->fixed_mode = adv;
4021
4022                 if (np->gigabit == PHY_GIGABIT) {
4023                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4024                         adv &= ~ADVERTISE_1000FULL;
4025                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4026                 }
4027
4028                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4029                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4030                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4031                         bmcr |= BMCR_FULLDPLX;
4032                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4033                         bmcr |= BMCR_SPEED100;
4034                 if (np->phy_oui == PHY_OUI_MARVELL) {
4035                         /* reset the phy in order for forced mode settings to stick */
4036                         if (phy_reset(dev, bmcr)) {
4037                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4038                                 return -EINVAL;
4039                         }
4040                 } else {
4041                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4042                         if (netif_running(dev)) {
4043                                 /* Wait a bit and then reconfigure the nic. */
4044                                 udelay(10);
4045                                 nv_linkchange(dev);
4046                         }
4047                 }
4048         }
4049
4050         if (netif_running(dev)) {
4051                 nv_start_rx(dev);
4052                 nv_start_tx(dev);
4053                 nv_enable_irq(dev);
4054         }
4055
4056         return 0;
4057 }
4058
4059 #define FORCEDETH_REGS_VER      1
4060
4061 static int nv_get_regs_len(struct net_device *dev)
4062 {
4063         struct fe_priv *np = netdev_priv(dev);
4064         return np->register_size;
4065 }
4066
4067 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4068 {
4069         struct fe_priv *np = netdev_priv(dev);
4070         u8 __iomem *base = get_hwbase(dev);
4071         u32 *rbuf = buf;
4072         int i;
4073
4074         regs->version = FORCEDETH_REGS_VER;
4075         spin_lock_irq(&np->lock);
4076         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4077                 rbuf[i] = readl(base + i*sizeof(u32));
4078         spin_unlock_irq(&np->lock);
4079 }
4080
4081 static int nv_nway_reset(struct net_device *dev)
4082 {
4083         struct fe_priv *np = netdev_priv(dev);
4084         int ret;
4085
4086         if (np->autoneg) {
4087                 int bmcr;
4088
4089                 netif_carrier_off(dev);
4090                 if (netif_running(dev)) {
4091                         nv_disable_irq(dev);
4092                         netif_tx_lock_bh(dev);
4093                         spin_lock(&np->lock);
4094                         /* stop engines */
4095                         nv_stop_rx(dev);
4096                         nv_stop_tx(dev);
4097                         spin_unlock(&np->lock);
4098                         netif_tx_unlock_bh(dev);
4099                         printk(KERN_INFO "%s: link down.\n", dev->name);
4100                 }
4101
4102                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4103                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4104                         bmcr |= BMCR_ANENABLE;
4105                         /* reset the phy in order for settings to stick*/
4106                         if (phy_reset(dev, bmcr)) {
4107                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4108                                 return -EINVAL;
4109                         }
4110                 } else {
4111                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4112                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4113                 }
4114
4115                 if (netif_running(dev)) {
4116                         nv_start_rx(dev);
4117                         nv_start_tx(dev);
4118                         nv_enable_irq(dev);
4119                 }
4120                 ret = 0;
4121         } else {
4122                 ret = -EINVAL;
4123         }
4124
4125         return ret;
4126 }
4127
4128 static int nv_set_tso(struct net_device *dev, u32 value)
4129 {
4130         struct fe_priv *np = netdev_priv(dev);
4131
4132         if ((np->driver_data & DEV_HAS_CHECKSUM))
4133                 return ethtool_op_set_tso(dev, value);
4134         else
4135                 return -EOPNOTSUPP;
4136 }
4137
4138 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4139 {
4140         struct fe_priv *np = netdev_priv(dev);
4141
4142         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4143         ring->rx_mini_max_pending = 0;
4144         ring->rx_jumbo_max_pending = 0;
4145         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4146
4147         ring->rx_pending = np->rx_ring_size;
4148         ring->rx_mini_pending = 0;
4149         ring->rx_jumbo_pending = 0;
4150         ring->tx_pending = np->tx_ring_size;
4151 }
4152
4153 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4154 {
4155         struct fe_priv *np = netdev_priv(dev);
4156         u8 __iomem *base = get_hwbase(dev);
4157         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4158         dma_addr_t ring_addr;
4159
4160         if (ring->rx_pending < RX_RING_MIN ||
4161             ring->tx_pending < TX_RING_MIN ||
4162             ring->rx_mini_pending != 0 ||
4163             ring->rx_jumbo_pending != 0 ||
4164             (np->desc_ver == DESC_VER_1 &&
4165              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4166               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4167             (np->desc_ver != DESC_VER_1 &&
4168              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4169               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4170                 return -EINVAL;
4171         }
4172
4173         /* allocate new rings */
4174         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4175                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4176                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4177                                             &ring_addr);
4178         } else {
4179                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4180                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4181                                             &ring_addr);
4182         }
4183         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4184         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4185         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4186                 /* fall back to old rings */
4187                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4188                         if (rxtx_ring)
4189                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4190                                                     rxtx_ring, ring_addr);
4191                 } else {
4192                         if (rxtx_ring)
4193                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4194                                                     rxtx_ring, ring_addr);
4195                 }
4196                 if (rx_skbuff)
4197                         kfree(rx_skbuff);
4198                 if (tx_skbuff)
4199                         kfree(tx_skbuff);
4200                 goto exit;
4201         }
4202
4203         if (netif_running(dev)) {
4204                 nv_disable_irq(dev);
4205                 netif_tx_lock_bh(dev);
4206                 spin_lock(&np->lock);
4207                 /* stop engines */
4208                 nv_stop_rx(dev);
4209                 nv_stop_tx(dev);
4210                 nv_txrx_reset(dev);
4211                 /* drain queues */
4212                 nv_drain_rx(dev);
4213                 nv_drain_tx(dev);
4214                 /* delete queues */
4215                 free_rings(dev);
4216         }
4217
4218         /* set new values */
4219         np->rx_ring_size = ring->rx_pending;
4220         np->tx_ring_size = ring->tx_pending;
4221         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4222                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4223                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4224         } else {
4225                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4226                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4227         }
4228         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4229         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4230         np->ring_addr = ring_addr;
4231
4232         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4233         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4234
4235         if (netif_running(dev)) {
4236                 /* reinit driver view of the queues */
4237                 set_bufsize(dev);
4238                 if (nv_init_ring(dev)) {
4239                         if (!np->in_shutdown)
4240                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4241                 }
4242
4243                 /* reinit nic view of the queues */
4244                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4245                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4246                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4247                         base + NvRegRingSizes);
4248                 pci_push(base);
4249                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4250                 pci_push(base);
4251
4252                 /* restart engines */
4253                 nv_start_rx(dev);
4254                 nv_start_tx(dev);
4255                 spin_unlock(&np->lock);
4256                 netif_tx_unlock_bh(dev);
4257                 nv_enable_irq(dev);
4258         }
4259         return 0;
4260 exit:
4261         return -ENOMEM;
4262 }
4263
4264 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4265 {
4266         struct fe_priv *np = netdev_priv(dev);
4267
4268         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4269         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4270         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4271 }
4272
4273 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4274 {
4275         struct fe_priv *np = netdev_priv(dev);
4276         int adv, bmcr;
4277
4278         if ((!np->autoneg && np->duplex == 0) ||
4279             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4280                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4281                        dev->name);
4282                 return -EINVAL;
4283         }
4284         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4285                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4286                 return -EINVAL;
4287         }
4288
4289         netif_carrier_off(dev);
4290         if (netif_running(dev)) {
4291                 nv_disable_irq(dev);
4292                 netif_tx_lock_bh(dev);
4293                 spin_lock(&np->lock);
4294                 /* stop engines */
4295                 nv_stop_rx(dev);
4296                 nv_stop_tx(dev);
4297                 spin_unlock(&np->lock);
4298                 netif_tx_unlock_bh(dev);
4299         }
4300
4301         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4302         if (pause->rx_pause)
4303                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4304         if (pause->tx_pause)
4305                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4306
4307         if (np->autoneg && pause->autoneg) {
4308                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4309
4310                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4311                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4312                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4313                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4314                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4315                         adv |=  ADVERTISE_PAUSE_ASYM;
4316                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4317
4318                 if (netif_running(dev))
4319                         printk(KERN_INFO "%s: link down.\n", dev->name);
4320                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4321                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4322                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4323         } else {
4324                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4325                 if (pause->rx_pause)
4326                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4327                 if (pause->tx_pause)
4328                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4329
4330                 if (!netif_running(dev))
4331                         nv_update_linkspeed(dev);
4332                 else
4333                         nv_update_pause(dev, np->pause_flags);
4334         }
4335
4336         if (netif_running(dev)) {
4337                 nv_start_rx(dev);
4338                 nv_start_tx(dev);
4339                 nv_enable_irq(dev);
4340         }
4341         return 0;
4342 }
4343
4344 static u32 nv_get_rx_csum(struct net_device *dev)
4345 {
4346         struct fe_priv *np = netdev_priv(dev);
4347         return (np->rx_csum) != 0;
4348 }
4349
4350 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4351 {
4352         struct fe_priv *np = netdev_priv(dev);
4353         u8 __iomem *base = get_hwbase(dev);
4354         int retcode = 0;
4355
4356         if (np->driver_data & DEV_HAS_CHECKSUM) {
4357                 if (data) {
4358                         np->rx_csum = 1;
4359                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4360                 } else {
4361                         np->rx_csum = 0;
4362                         /* vlan is dependent on rx checksum offload */
4363                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4364                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4365                 }
4366                 if (netif_running(dev)) {
4367                         spin_lock_irq(&np->lock);
4368                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4369                         spin_unlock_irq(&np->lock);
4370                 }
4371         } else {
4372                 return -EINVAL;
4373         }
4374
4375         return retcode;
4376 }
4377
4378 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4379 {
4380         struct fe_priv *np = netdev_priv(dev);
4381
4382         if (np->driver_data & DEV_HAS_CHECKSUM)
4383                 return ethtool_op_set_tx_hw_csum(dev, data);
4384         else
4385                 return -EOPNOTSUPP;
4386 }
4387
4388 static int nv_set_sg(struct net_device *dev, u32 data)
4389 {
4390         struct fe_priv *np = netdev_priv(dev);
4391
4392         if (np->driver_data & DEV_HAS_CHECKSUM)
4393                 return ethtool_op_set_sg(dev, data);
4394         else
4395                 return -EOPNOTSUPP;
4396 }
4397
4398 static int nv_get_sset_count(struct net_device *dev, int sset)
4399 {
4400         struct fe_priv *np = netdev_priv(dev);
4401
4402         switch (sset) {
4403         case ETH_SS_TEST:
4404                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4405                         return NV_TEST_COUNT_EXTENDED;
4406                 else
4407                         return NV_TEST_COUNT_BASE;
4408         case ETH_SS_STATS:
4409                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4410                         return NV_DEV_STATISTICS_V1_COUNT;
4411                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4412                         return NV_DEV_STATISTICS_V2_COUNT;
4413                 else
4414                         return 0;
4415         default:
4416                 return -EOPNOTSUPP;
4417         }
4418 }
4419
4420 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4421 {
4422         struct fe_priv *np = netdev_priv(dev);
4423
4424         /* update stats */
4425         nv_do_stats_poll((unsigned long)dev);
4426
4427         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4428 }
4429
4430 static int nv_link_test(struct net_device *dev)
4431 {
4432         struct fe_priv *np = netdev_priv(dev);
4433         int mii_status;
4434
4435         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4436         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4437
4438         /* check phy link status */
4439         if (!(mii_status & BMSR_LSTATUS))
4440                 return 0;
4441         else
4442                 return 1;
4443 }
4444
4445 static int nv_register_test(struct net_device *dev)
4446 {
4447         u8 __iomem *base = get_hwbase(dev);
4448         int i = 0;
4449         u32 orig_read, new_read;
4450
4451         do {
4452                 orig_read = readl(base + nv_registers_test[i].reg);
4453
4454                 /* xor with mask to toggle bits */
4455                 orig_read ^= nv_registers_test[i].mask;
4456
4457                 writel(orig_read, base + nv_registers_test[i].reg);
4458
4459                 new_read = readl(base + nv_registers_test[i].reg);
4460
4461                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4462                         return 0;
4463
4464                 /* restore original value */
4465                 orig_read ^= nv_registers_test[i].mask;
4466                 writel(orig_read, base + nv_registers_test[i].reg);
4467
4468         } while (nv_registers_test[++i].reg != 0);
4469
4470         return 1;
4471 }
4472
4473 static int nv_interrupt_test(struct net_device *dev)
4474 {
4475         struct fe_priv *np = netdev_priv(dev);
4476         u8 __iomem *base = get_hwbase(dev);
4477         int ret = 1;
4478         int testcnt;
4479         u32 save_msi_flags, save_poll_interval = 0;
4480
4481         if (netif_running(dev)) {
4482                 /* free current irq */
4483                 nv_free_irq(dev);
4484                 save_poll_interval = readl(base+NvRegPollingInterval);
4485         }
4486
4487         /* flag to test interrupt handler */
4488         np->intr_test = 0;
4489
4490         /* setup test irq */
4491         save_msi_flags = np->msi_flags;
4492         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4493         np->msi_flags |= 0x001; /* setup 1 vector */
4494         if (nv_request_irq(dev, 1))
4495                 return 0;
4496
4497         /* setup timer interrupt */
4498         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4499         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4500
4501         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4502
4503         /* wait for at least one interrupt */
4504         msleep(100);
4505
4506         spin_lock_irq(&np->lock);
4507
4508         /* flag should be set within ISR */
4509         testcnt = np->intr_test;
4510         if (!testcnt)
4511                 ret = 2;
4512
4513         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4514         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4515                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4516         else
4517                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4518
4519         spin_unlock_irq(&np->lock);
4520
4521         nv_free_irq(dev);
4522
4523         np->msi_flags = save_msi_flags;
4524
4525         if (netif_running(dev)) {
4526                 writel(save_poll_interval, base + NvRegPollingInterval);
4527                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4528                 /* restore original irq */
4529                 if (nv_request_irq(dev, 0))
4530                         return 0;
4531         }
4532
4533         return ret;
4534 }
4535
4536 static int nv_loopback_test(struct net_device *dev)
4537 {
4538         struct fe_priv *np = netdev_priv(dev);
4539         u8 __iomem *base = get_hwbase(dev);
4540         struct sk_buff *tx_skb, *rx_skb;
4541         dma_addr_t test_dma_addr;
4542         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4543         u32 flags;
4544         int len, i, pkt_len;
4545         u8 *pkt_data;
4546         u32 filter_flags = 0;
4547         u32 misc1_flags = 0;
4548         int ret = 1;
4549
4550         if (netif_running(dev)) {
4551                 nv_disable_irq(dev);
4552                 filter_flags = readl(base + NvRegPacketFilterFlags);
4553                 misc1_flags = readl(base + NvRegMisc1);
4554         } else {
4555                 nv_txrx_reset(dev);
4556         }
4557
4558         /* reinit driver view of the rx queue */
4559         set_bufsize(dev);
4560         nv_init_ring(dev);
4561
4562         /* setup hardware for loopback */
4563         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4564         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4565
4566         /* reinit nic view of the rx queue */
4567         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4568         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4569         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4570                 base + NvRegRingSizes);
4571         pci_push(base);
4572
4573         /* restart rx engine */
4574         nv_start_rx(dev);
4575         nv_start_tx(dev);
4576
4577         /* setup packet for tx */
4578         pkt_len = ETH_DATA_LEN;
4579         tx_skb = dev_alloc_skb(pkt_len);
4580         if (!tx_skb) {
4581                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4582                          " of %s\n", dev->name);
4583                 ret = 0;
4584                 goto out;
4585         }
4586         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4587                                        skb_tailroom(tx_skb),
4588                                        PCI_DMA_FROMDEVICE);
4589         pkt_data = skb_put(tx_skb, pkt_len);
4590         for (i = 0; i < pkt_len; i++)
4591                 pkt_data[i] = (u8)(i & 0xff);
4592
4593         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4594                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4595                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4596         } else {
4597                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4598                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4599                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4600         }
4601         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4602         pci_push(get_hwbase(dev));
4603
4604         msleep(500);
4605
4606         /* check for rx of the packet */
4607         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4608                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4609                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4610
4611         } else {
4612                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4613                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4614         }
4615
4616         if (flags & NV_RX_AVAIL) {
4617                 ret = 0;
4618         } else if (np->desc_ver == DESC_VER_1) {
4619                 if (flags & NV_RX_ERROR)
4620                         ret = 0;
4621         } else {
4622                 if (flags & NV_RX2_ERROR) {
4623                         ret = 0;
4624                 }
4625         }
4626
4627         if (ret) {
4628                 if (len != pkt_len) {
4629                         ret = 0;
4630                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4631                                 dev->name, len, pkt_len);
4632                 } else {
4633                         rx_skb = np->rx_skb[0].skb;
4634                         for (i = 0; i < pkt_len; i++) {
4635                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4636                                         ret = 0;
4637                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4638                                                 dev->name, i);
4639                                         break;
4640                                 }
4641                         }
4642                 }
4643         } else {
4644                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4645         }
4646
4647         pci_unmap_page(np->pci_dev, test_dma_addr,
4648                        (skb_end_pointer(tx_skb) - tx_skb->data),
4649                        PCI_DMA_TODEVICE);
4650         dev_kfree_skb_any(tx_skb);
4651  out:
4652         /* stop engines */
4653         nv_stop_rx(dev);
4654         nv_stop_tx(dev);
4655         nv_txrx_reset(dev);
4656         /* drain rx queue */
4657         nv_drain_rx(dev);
4658         nv_drain_tx(dev);
4659
4660         if (netif_running(dev)) {
4661                 writel(misc1_flags, base + NvRegMisc1);
4662                 writel(filter_flags, base + NvRegPacketFilterFlags);
4663                 nv_enable_irq(dev);
4664         }
4665
4666         return ret;
4667 }
4668
4669 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4670 {
4671         struct fe_priv *np = netdev_priv(dev);
4672         u8 __iomem *base = get_hwbase(dev);
4673         int result;
4674         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4675
4676         if (!nv_link_test(dev)) {
4677                 test->flags |= ETH_TEST_FL_FAILED;
4678                 buffer[0] = 1;
4679         }
4680
4681         if (test->flags & ETH_TEST_FL_OFFLINE) {
4682                 if (netif_running(dev)) {
4683                         netif_stop_queue(dev);
4684 #ifdef CONFIG_FORCEDETH_NAPI
4685                         napi_disable(&np->napi);
4686 #endif
4687                         netif_tx_lock_bh(dev);
4688                         spin_lock_irq(&np->lock);
4689                         nv_disable_hw_interrupts(dev, np->irqmask);
4690                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4691                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4692                         } else {
4693                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4694                         }
4695                         /* stop engines */
4696                         nv_stop_rx(dev);
4697                         nv_stop_tx(dev);
4698                         nv_txrx_reset(dev);
4699                         /* drain rx queue */
4700                         nv_drain_rx(dev);
4701                         nv_drain_tx(dev);
4702                         spin_unlock_irq(&np->lock);
4703                         netif_tx_unlock_bh(dev);
4704                 }
4705
4706                 if (!nv_register_test(dev)) {
4707                         test->flags |= ETH_TEST_FL_FAILED;
4708                         buffer[1] = 1;
4709                 }
4710
4711                 result = nv_interrupt_test(dev);
4712                 if (result != 1) {
4713                         test->flags |= ETH_TEST_FL_FAILED;
4714                         buffer[2] = 1;
4715                 }
4716                 if (result == 0) {
4717                         /* bail out */
4718                         return;
4719                 }
4720
4721                 if (!nv_loopback_test(dev)) {
4722                         test->flags |= ETH_TEST_FL_FAILED;
4723                         buffer[3] = 1;
4724                 }
4725
4726                 if (netif_running(dev)) {
4727                         /* reinit driver view of the rx queue */
4728                         set_bufsize(dev);
4729                         if (nv_init_ring(dev)) {
4730                                 if (!np->in_shutdown)
4731                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4732                         }
4733                         /* reinit nic view of the rx queue */
4734                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4735                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4736                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4737                                 base + NvRegRingSizes);
4738                         pci_push(base);
4739                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4740                         pci_push(base);
4741                         /* restart rx engine */
4742                         nv_start_rx(dev);
4743                         nv_start_tx(dev);
4744                         netif_start_queue(dev);
4745 #ifdef CONFIG_FORCEDETH_NAPI
4746                         napi_enable(&np->napi);
4747 #endif
4748                         nv_enable_hw_interrupts(dev, np->irqmask);
4749                 }
4750         }
4751 }
4752
4753 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4754 {
4755         switch (stringset) {
4756         case ETH_SS_STATS:
4757                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4758                 break;
4759         case ETH_SS_TEST:
4760                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4761                 break;
4762         }
4763 }
4764
4765 static const struct ethtool_ops ops = {
4766         .get_drvinfo = nv_get_drvinfo,
4767         .get_link = ethtool_op_get_link,
4768         .get_wol = nv_get_wol,
4769         .set_wol = nv_set_wol,
4770         .get_settings = nv_get_settings,
4771         .set_settings = nv_set_settings,
4772         .get_regs_len = nv_get_regs_len,
4773         .get_regs = nv_get_regs,
4774         .nway_reset = nv_nway_reset,
4775         .set_tso = nv_set_tso,
4776         .get_ringparam = nv_get_ringparam,
4777         .set_ringparam = nv_set_ringparam,
4778         .get_pauseparam = nv_get_pauseparam,
4779         .set_pauseparam = nv_set_pauseparam,
4780         .get_rx_csum = nv_get_rx_csum,
4781         .set_rx_csum = nv_set_rx_csum,
4782         .set_tx_csum = nv_set_tx_csum,
4783         .set_sg = nv_set_sg,
4784         .get_strings = nv_get_strings,
4785         .get_ethtool_stats = nv_get_ethtool_stats,
4786         .get_sset_count = nv_get_sset_count,
4787         .self_test = nv_self_test,
4788 };
4789
4790 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4791 {
4792         struct fe_priv *np = get_nvpriv(dev);
4793
4794         spin_lock_irq(&np->lock);
4795
4796         /* save vlan group */
4797         np->vlangrp = grp;
4798
4799         if (grp) {
4800                 /* enable vlan on MAC */
4801                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4802         } else {
4803                 /* disable vlan on MAC */
4804                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4805                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4806         }
4807
4808         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4809
4810         spin_unlock_irq(&np->lock);
4811 }
4812
4813 /* The mgmt unit and driver use a semaphore to access the phy during init */
4814 static int nv_mgmt_acquire_sema(struct net_device *dev)
4815 {
4816         u8 __iomem *base = get_hwbase(dev);
4817         int i;
4818         u32 tx_ctrl, mgmt_sema;
4819
4820         for (i = 0; i < 10; i++) {
4821                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4822                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4823                         break;
4824                 msleep(500);
4825         }
4826
4827         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4828                 return 0;
4829
4830         for (i = 0; i < 2; i++) {
4831                 tx_ctrl = readl(base + NvRegTransmitterControl);
4832                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4833                 writel(tx_ctrl, base + NvRegTransmitterControl);
4834
4835                 /* verify that semaphore was acquired */
4836                 tx_ctrl = readl(base + NvRegTransmitterControl);
4837                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4838                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4839                         return 1;
4840                 else
4841                         udelay(50);
4842         }
4843
4844         return 0;
4845 }
4846
4847 static int nv_open(struct net_device *dev)
4848 {
4849         struct fe_priv *np = netdev_priv(dev);
4850         u8 __iomem *base = get_hwbase(dev);
4851         int ret = 1;
4852         int oom, i;
4853
4854         dprintk(KERN_DEBUG "nv_open: begin\n");
4855
4856         /* erase previous misconfiguration */
4857         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4858                 nv_mac_reset(dev);
4859         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4860         writel(0, base + NvRegMulticastAddrB);
4861         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4862         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4863         writel(0, base + NvRegPacketFilterFlags);
4864
4865         writel(0, base + NvRegTransmitterControl);
4866         writel(0, base + NvRegReceiverControl);
4867
4868         writel(0, base + NvRegAdapterControl);
4869
4870         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4871                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4872
4873         /* initialize descriptor rings */
4874         set_bufsize(dev);
4875         oom = nv_init_ring(dev);
4876
4877         writel(0, base + NvRegLinkSpeed);
4878         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4879         nv_txrx_reset(dev);
4880         writel(0, base + NvRegUnknownSetupReg6);
4881
4882         np->in_shutdown = 0;
4883
4884         /* give hw rings */
4885         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4886         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4887                 base + NvRegRingSizes);
4888
4889         writel(np->linkspeed, base + NvRegLinkSpeed);
4890         if (np->desc_ver == DESC_VER_1)
4891                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4892         else
4893                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4894         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4895         writel(np->vlanctl_bits, base + NvRegVlanControl);
4896         pci_push(base);
4897         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4898         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4899                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4900                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4901
4902         writel(0, base + NvRegMIIMask);
4903         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4904         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4905
4906         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4907         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4908         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4909         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4910
4911         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4912         get_random_bytes(&i, sizeof(i));
4913         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4914         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4915         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4916         if (poll_interval == -1) {
4917                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4918                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4919                 else
4920                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4921         }
4922         else
4923                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4924         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4925         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4926                         base + NvRegAdapterControl);
4927         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4928         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4929         if (np->wolenabled)
4930                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4931
4932         i = readl(base + NvRegPowerState);
4933         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4934                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4935
4936         pci_push(base);
4937         udelay(10);
4938         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4939
4940         nv_disable_hw_interrupts(dev, np->irqmask);
4941         pci_push(base);
4942         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4943         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4944         pci_push(base);
4945
4946         if (nv_request_irq(dev, 0)) {
4947                 goto out_drain;
4948         }
4949
4950         /* ask for interrupts */
4951         nv_enable_hw_interrupts(dev, np->irqmask);
4952
4953         spin_lock_irq(&np->lock);
4954         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4955         writel(0, base + NvRegMulticastAddrB);
4956         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4957         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4958         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4959         /* One manual link speed update: Interrupts are enabled, future link
4960          * speed changes cause interrupts and are handled by nv_link_irq().
4961          */
4962         {
4963                 u32 miistat;
4964                 miistat = readl(base + NvRegMIIStatus);
4965                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4966                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4967         }
4968         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4969          * to init hw */
4970         np->linkspeed = 0;
4971         ret = nv_update_linkspeed(dev);
4972         nv_start_rx(dev);
4973         nv_start_tx(dev);
4974         netif_start_queue(dev);
4975 #ifdef CONFIG_FORCEDETH_NAPI
4976         napi_enable(&np->napi);
4977 #endif
4978
4979         if (ret) {
4980                 netif_carrier_on(dev);
4981         } else {
4982                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
4983                 netif_carrier_off(dev);
4984         }
4985         if (oom)
4986                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4987
4988         /* start statistics timer */
4989         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4990                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4991
4992         spin_unlock_irq(&np->lock);
4993
4994         return 0;
4995 out_drain:
4996         drain_ring(dev);
4997         return ret;
4998 }
4999
5000 static int nv_close(struct net_device *dev)
5001 {
5002         struct fe_priv *np = netdev_priv(dev);
5003         u8 __iomem *base;
5004
5005         spin_lock_irq(&np->lock);
5006         np->in_shutdown = 1;
5007         spin_unlock_irq(&np->lock);
5008 #ifdef CONFIG_FORCEDETH_NAPI
5009         napi_disable(&np->napi);
5010 #endif
5011         synchronize_irq(np->pci_dev->irq);
5012
5013         del_timer_sync(&np->oom_kick);
5014         del_timer_sync(&np->nic_poll);
5015         del_timer_sync(&np->stats_poll);
5016
5017         netif_stop_queue(dev);
5018         spin_lock_irq(&np->lock);
5019         nv_stop_tx(dev);
5020         nv_stop_rx(dev);
5021         nv_txrx_reset(dev);
5022
5023         /* disable interrupts on the nic or we will lock up */
5024         base = get_hwbase(dev);
5025         nv_disable_hw_interrupts(dev, np->irqmask);
5026         pci_push(base);
5027         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5028
5029         spin_unlock_irq(&np->lock);
5030
5031         nv_free_irq(dev);
5032
5033         drain_ring(dev);
5034
5035         if (np->wolenabled) {
5036                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5037                 nv_start_rx(dev);
5038         }
5039
5040         /* FIXME: power down nic */
5041
5042         return 0;
5043 }
5044
5045 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5046 {
5047         struct net_device *dev;
5048         struct fe_priv *np;
5049         unsigned long addr;
5050         u8 __iomem *base;
5051         int err, i;
5052         u32 powerstate, txreg;
5053         u32 phystate_orig = 0, phystate;
5054         int phyinitialized = 0;
5055         DECLARE_MAC_BUF(mac);
5056         static int printed_version;
5057
5058         if (!printed_version++)
5059                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5060                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5061
5062         dev = alloc_etherdev(sizeof(struct fe_priv));
5063         err = -ENOMEM;
5064         if (!dev)
5065                 goto out;
5066
5067         np = netdev_priv(dev);
5068         np->dev = dev;
5069         np->pci_dev = pci_dev;
5070         spin_lock_init(&np->lock);
5071         SET_NETDEV_DEV(dev, &pci_dev->dev);
5072
5073         init_timer(&np->oom_kick);
5074         np->oom_kick.data = (unsigned long) dev;
5075         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5076         init_timer(&np->nic_poll);
5077         np->nic_poll.data = (unsigned long) dev;
5078         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5079         init_timer(&np->stats_poll);
5080         np->stats_poll.data = (unsigned long) dev;
5081         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5082
5083         err = pci_enable_device(pci_dev);
5084         if (err)
5085                 goto out_free;
5086
5087         pci_set_master(pci_dev);
5088
5089         err = pci_request_regions(pci_dev, DRV_NAME);
5090         if (err < 0)
5091                 goto out_disable;
5092
5093         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5094                 np->register_size = NV_PCI_REGSZ_VER3;
5095         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5096                 np->register_size = NV_PCI_REGSZ_VER2;
5097         else
5098                 np->register_size = NV_PCI_REGSZ_VER1;
5099
5100         err = -EINVAL;
5101         addr = 0;
5102         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5103                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5104                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5105                                 pci_resource_len(pci_dev, i),
5106                                 pci_resource_flags(pci_dev, i));
5107                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5108                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5109                         addr = pci_resource_start(pci_dev, i);
5110                         break;
5111                 }
5112         }
5113         if (i == DEVICE_COUNT_RESOURCE) {
5114                 dev_printk(KERN_INFO, &pci_dev->dev,
5115                            "Couldn't find register window\n");
5116                 goto out_relreg;
5117         }
5118
5119         /* copy of driver data */
5120         np->driver_data = id->driver_data;
5121
5122         /* handle different descriptor versions */
5123         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5124                 /* packet format 3: supports 40-bit addressing */
5125                 np->desc_ver = DESC_VER_3;
5126                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5127                 if (dma_64bit) {
5128                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5129                                 dev_printk(KERN_INFO, &pci_dev->dev,
5130                                         "64-bit DMA failed, using 32-bit addressing\n");
5131                         else
5132                                 dev->features |= NETIF_F_HIGHDMA;
5133                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5134                                 dev_printk(KERN_INFO, &pci_dev->dev,
5135                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5136                         }
5137                 }
5138         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5139                 /* packet format 2: supports jumbo frames */
5140                 np->desc_ver = DESC_VER_2;
5141                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5142         } else {
5143                 /* original packet format */
5144                 np->desc_ver = DESC_VER_1;
5145                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5146         }
5147
5148         np->pkt_limit = NV_PKTLIMIT_1;
5149         if (id->driver_data & DEV_HAS_LARGEDESC)
5150                 np->pkt_limit = NV_PKTLIMIT_2;
5151
5152         if (id->driver_data & DEV_HAS_CHECKSUM) {
5153                 np->rx_csum = 1;
5154                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5155                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5156                 dev->features |= NETIF_F_TSO;
5157         }
5158
5159         np->vlanctl_bits = 0;
5160         if (id->driver_data & DEV_HAS_VLAN) {
5161                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5162                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5163                 dev->vlan_rx_register = nv_vlan_rx_register;
5164         }
5165
5166         np->msi_flags = 0;
5167         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5168                 np->msi_flags |= NV_MSI_CAPABLE;
5169         }
5170         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5171                 np->msi_flags |= NV_MSI_X_CAPABLE;
5172         }
5173
5174         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5175         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
5176                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5177         }
5178
5179
5180         err = -ENOMEM;
5181         np->base = ioremap(addr, np->register_size);
5182         if (!np->base)
5183                 goto out_relreg;
5184         dev->base_addr = (unsigned long)np->base;
5185
5186         dev->irq = pci_dev->irq;
5187
5188         np->rx_ring_size = RX_RING_DEFAULT;
5189         np->tx_ring_size = TX_RING_DEFAULT;
5190
5191         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5192                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5193                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5194                                         &np->ring_addr);
5195                 if (!np->rx_ring.orig)
5196                         goto out_unmap;
5197                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5198         } else {
5199                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5200                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5201                                         &np->ring_addr);
5202                 if (!np->rx_ring.ex)
5203                         goto out_unmap;
5204                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5205         }
5206         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5207         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5208         if (!np->rx_skb || !np->tx_skb)
5209                 goto out_freering;
5210
5211         dev->open = nv_open;
5212         dev->stop = nv_close;
5213         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5214                 dev->hard_start_xmit = nv_start_xmit;
5215         else
5216                 dev->hard_start_xmit = nv_start_xmit_optimized;
5217         dev->get_stats = nv_get_stats;
5218         dev->change_mtu = nv_change_mtu;
5219         dev->set_mac_address = nv_set_mac_address;
5220         dev->set_multicast_list = nv_set_multicast;
5221 #ifdef CONFIG_NET_POLL_CONTROLLER
5222         dev->poll_controller = nv_poll_controller;
5223 #endif
5224 #ifdef CONFIG_FORCEDETH_NAPI
5225         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5226 #endif
5227         SET_ETHTOOL_OPS(dev, &ops);
5228         dev->tx_timeout = nv_tx_timeout;
5229         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5230
5231         pci_set_drvdata(pci_dev, dev);
5232
5233         /* read the mac address */
5234         base = get_hwbase(dev);
5235         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5236         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5237
5238         /* check the workaround bit for correct mac address order */
5239         txreg = readl(base + NvRegTransmitPoll);
5240         if ((txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) ||
5241             (id->driver_data & DEV_HAS_CORRECT_MACADDR)) {
5242                 /* mac address is already in correct order */
5243                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5244                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5245                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5246                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5247                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5248                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5249         } else {
5250                 /* need to reverse mac address to correct order */
5251                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5252                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5253                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5254                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5255                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5256                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5257                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5258         }
5259         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5260
5261         if (!is_valid_ether_addr(dev->perm_addr)) {
5262                 /*
5263                  * Bad mac address. At least one bios sets the mac address
5264                  * to 01:23:45:67:89:ab
5265                  */
5266                 dev_printk(KERN_ERR, &pci_dev->dev,
5267                         "Invalid Mac address detected: %s\n",
5268                         print_mac(mac, dev->dev_addr));
5269                 dev_printk(KERN_ERR, &pci_dev->dev,
5270                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5271                 dev->dev_addr[0] = 0x00;
5272                 dev->dev_addr[1] = 0x00;
5273                 dev->dev_addr[2] = 0x6c;
5274                 get_random_bytes(&dev->dev_addr[3], 3);
5275         }
5276
5277         dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5278                 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5279
5280         /* set mac address */
5281         nv_copy_mac_to_hw(dev);
5282
5283         /* disable WOL */
5284         writel(0, base + NvRegWakeUpFlags);
5285         np->wolenabled = 0;
5286
5287         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5288
5289                 /* take phy and nic out of low power mode */
5290                 powerstate = readl(base + NvRegPowerState2);
5291                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5292                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5293                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5294                     pci_dev->revision >= 0xA3)
5295                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5296                 writel(powerstate, base + NvRegPowerState2);
5297         }
5298
5299         if (np->desc_ver == DESC_VER_1) {
5300                 np->tx_flags = NV_TX_VALID;
5301         } else {
5302                 np->tx_flags = NV_TX2_VALID;
5303         }
5304         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5305                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5306                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5307                         np->msi_flags |= 0x0003;
5308         } else {
5309                 np->irqmask = NVREG_IRQMASK_CPU;
5310                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5311                         np->msi_flags |= 0x0001;
5312         }
5313
5314         if (id->driver_data & DEV_NEED_TIMERIRQ)
5315                 np->irqmask |= NVREG_IRQ_TIMER;
5316         if (id->driver_data & DEV_NEED_LINKTIMER) {
5317                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5318                 np->need_linktimer = 1;
5319                 np->link_timeout = jiffies + LINK_TIMEOUT;
5320         } else {
5321                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5322                 np->need_linktimer = 0;
5323         }
5324
5325         /* clear phy state and temporarily halt phy interrupts */
5326         writel(0, base + NvRegMIIMask);
5327         phystate = readl(base + NvRegAdapterControl);
5328         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5329                 phystate_orig = 1;
5330                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5331                 writel(phystate, base + NvRegAdapterControl);
5332         }
5333         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5334
5335         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5336                 /* management unit running on the mac? */
5337                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5338                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5339                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5340                         if (nv_mgmt_acquire_sema(dev)) {
5341                                 /* management unit setup the phy already? */
5342                                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5343                                     NVREG_XMITCTL_SYNC_PHY_INIT) {
5344                                         /* phy is inited by mgmt unit */
5345                                         phyinitialized = 1;
5346                                         dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5347                                 } else {
5348                                         /* we need to init the phy */
5349                                 }
5350                         }
5351                 }
5352         }
5353
5354         /* find a suitable phy */
5355         for (i = 1; i <= 32; i++) {
5356                 int id1, id2;
5357                 int phyaddr = i & 0x1F;
5358
5359                 spin_lock_irq(&np->lock);
5360                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5361                 spin_unlock_irq(&np->lock);
5362                 if (id1 < 0 || id1 == 0xffff)
5363                         continue;
5364                 spin_lock_irq(&np->lock);
5365                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5366                 spin_unlock_irq(&np->lock);
5367                 if (id2 < 0 || id2 == 0xffff)
5368                         continue;
5369
5370                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5371                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5372                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5373                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5374                         pci_name(pci_dev), id1, id2, phyaddr);
5375                 np->phyaddr = phyaddr;
5376                 np->phy_oui = id1 | id2;
5377                 break;
5378         }
5379         if (i == 33) {
5380                 dev_printk(KERN_INFO, &pci_dev->dev,
5381                         "open: Could not find a valid PHY.\n");
5382                 goto out_error;
5383         }
5384
5385         if (!phyinitialized) {
5386                 /* reset it */
5387                 phy_init(dev);
5388         } else {
5389                 /* see if it is a gigabit phy */
5390                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5391                 if (mii_status & PHY_GIGABIT) {
5392                         np->gigabit = PHY_GIGABIT;
5393                 }
5394         }
5395
5396         /* set default link speed settings */
5397         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5398         np->duplex = 0;
5399         np->autoneg = 1;
5400
5401         err = register_netdev(dev);
5402         if (err) {
5403                 dev_printk(KERN_INFO, &pci_dev->dev,
5404                            "unable to register netdev: %d\n", err);
5405                 goto out_error;
5406         }
5407
5408         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5409                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5410                    dev->name,
5411                    np->phy_oui,
5412                    np->phyaddr,
5413                    dev->dev_addr[0],
5414                    dev->dev_addr[1],
5415                    dev->dev_addr[2],
5416                    dev->dev_addr[3],
5417                    dev->dev_addr[4],
5418                    dev->dev_addr[5]);
5419
5420         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5421                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5422                    dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5423                         "csum " : "",
5424                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5425                         "vlan " : "",
5426                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5427                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5428                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5429                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5430                    np->need_linktimer ? "lnktim " : "",
5431                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5432                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5433                    np->desc_ver);
5434
5435         return 0;
5436
5437 out_error:
5438         if (phystate_orig)
5439                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5440         pci_set_drvdata(pci_dev, NULL);
5441 out_freering:
5442         free_rings(dev);
5443 out_unmap:
5444         iounmap(get_hwbase(dev));
5445 out_relreg:
5446         pci_release_regions(pci_dev);
5447 out_disable:
5448         pci_disable_device(pci_dev);
5449 out_free:
5450         free_netdev(dev);
5451 out:
5452         return err;
5453 }
5454
5455 static void __devexit nv_remove(struct pci_dev *pci_dev)
5456 {
5457         struct net_device *dev = pci_get_drvdata(pci_dev);
5458         struct fe_priv *np = netdev_priv(dev);
5459         u8 __iomem *base = get_hwbase(dev);
5460
5461         unregister_netdev(dev);
5462
5463         /* special op: write back the misordered MAC address - otherwise
5464          * the next nv_probe would see a wrong address.
5465          */
5466         writel(np->orig_mac[0], base + NvRegMacAddrA);
5467         writel(np->orig_mac[1], base + NvRegMacAddrB);
5468         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5469                base + NvRegTransmitPoll);
5470
5471         /* free all structures */
5472         free_rings(dev);
5473         iounmap(get_hwbase(dev));
5474         pci_release_regions(pci_dev);
5475         pci_disable_device(pci_dev);
5476         free_netdev(dev);
5477         pci_set_drvdata(pci_dev, NULL);
5478 }
5479
5480 #ifdef CONFIG_PM
5481 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5482 {
5483         struct net_device *dev = pci_get_drvdata(pdev);
5484         struct fe_priv *np = netdev_priv(dev);
5485
5486         if (!netif_running(dev))
5487                 goto out;
5488
5489         netif_device_detach(dev);
5490
5491         // Gross.
5492         nv_close(dev);
5493
5494         pci_save_state(pdev);
5495         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5496         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5497 out:
5498         return 0;
5499 }
5500
5501 static int nv_resume(struct pci_dev *pdev)
5502 {
5503         struct net_device *dev = pci_get_drvdata(pdev);
5504         int rc = 0;
5505
5506         if (!netif_running(dev))
5507                 goto out;
5508
5509         netif_device_attach(dev);
5510
5511         pci_set_power_state(pdev, PCI_D0);
5512         pci_restore_state(pdev);
5513         pci_enable_wake(pdev, PCI_D0, 0);
5514
5515         rc = nv_open(dev);
5516 out:
5517         return rc;
5518 }
5519 #else
5520 #define nv_suspend NULL
5521 #define nv_resume NULL
5522 #endif /* CONFIG_PM */
5523
5524 static struct pci_device_id pci_tbl[] = {
5525         {       /* nForce Ethernet Controller */
5526                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5527                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5528         },
5529         {       /* nForce2 Ethernet Controller */
5530                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5531                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5532         },
5533         {       /* nForce3 Ethernet Controller */
5534                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5535                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5536         },
5537         {       /* nForce3 Ethernet Controller */
5538                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5539                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5540         },
5541         {       /* nForce3 Ethernet Controller */
5542              &n