forcedeth: remove isr processing loop
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.63"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk                 printk
69 #else
70 #define dprintk(x...)           do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP  64
74 #define RX_WORK_PER_LOOP  64
75
76 /*
77  * Hardware access:
78  */
79
80 #define DEV_NEED_TIMERIRQ          0x000001  /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER         0x000002  /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC          0x000004  /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA           0x000008  /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM           0x000010  /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN               0x000020  /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI                0x000040  /* device supports MSI */
87 #define DEV_HAS_MSI_X              0x000080  /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL        0x000100  /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1      0x000200  /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2      0x000600  /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3      0x000e00  /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED      0x001000  /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT          0x002000  /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR    0x004000  /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX      0x008000  /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x010000  /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x020000  /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x040000  /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT          0x080000  /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE          0x100000  /* device supports gear mode */
101
102 enum {
103         NvRegIrqStatus = 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT  0x040
105 #define NVREG_IRQSTAT_MASK              0x83ff
106         NvRegIrqMask = 0x004,
107 #define NVREG_IRQ_RX_ERROR              0x0001
108 #define NVREG_IRQ_RX                    0x0002
109 #define NVREG_IRQ_RX_NOBUF              0x0004
110 #define NVREG_IRQ_TX_ERR                0x0008
111 #define NVREG_IRQ_TX_OK                 0x0010
112 #define NVREG_IRQ_TIMER                 0x0020
113 #define NVREG_IRQ_LINK                  0x0040
114 #define NVREG_IRQ_RX_FORCED             0x0080
115 #define NVREG_IRQ_TX_FORCED             0x0100
116 #define NVREG_IRQ_RECOVER_ERROR         0x8200
117 #define NVREG_IRQMASK_THROUGHPUT        0x00df
118 #define NVREG_IRQMASK_CPU               0x0060
119 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122
123         NvRegUnknownSetupReg6 = 0x008,
124 #define NVREG_UNKSETUP6_VAL             3
125
126 /*
127  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
128  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
129  */
130         NvRegPollingInterval = 0x00c,
131 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
132 #define NVREG_POLL_DEFAULT_CPU  13
133         NvRegMSIMap0 = 0x020,
134         NvRegMSIMap1 = 0x024,
135         NvRegMSIIrqMask = 0x030,
136 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
137         NvRegMisc1 = 0x080,
138 #define NVREG_MISC1_PAUSE_TX    0x01
139 #define NVREG_MISC1_HD          0x02
140 #define NVREG_MISC1_FORCE       0x3b0f3c
141
142         NvRegMacReset = 0x34,
143 #define NVREG_MAC_RESET_ASSERT  0x0F3
144         NvRegTransmitterControl = 0x084,
145 #define NVREG_XMITCTL_START     0x01
146 #define NVREG_XMITCTL_MGMT_ST   0x40000000
147 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
148 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
149 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
150 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
151 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
152 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
153 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
154 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
155 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
156 #define NVREG_XMITCTL_DATA_START        0x00100000
157 #define NVREG_XMITCTL_DATA_READY        0x00010000
158 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
159         NvRegTransmitterStatus = 0x088,
160 #define NVREG_XMITSTAT_BUSY     0x01
161
162         NvRegPacketFilterFlags = 0x8c,
163 #define NVREG_PFF_PAUSE_RX      0x08
164 #define NVREG_PFF_ALWAYS        0x7F0000
165 #define NVREG_PFF_PROMISC       0x80
166 #define NVREG_PFF_MYADDR        0x20
167 #define NVREG_PFF_LOOPBACK      0x10
168
169         NvRegOffloadConfig = 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY   0x601
171 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
172         NvRegReceiverControl = 0x094,
173 #define NVREG_RCVCTL_START      0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175         NvRegReceiverStatus = 0x98,
176 #define NVREG_RCVSTAT_BUSY      0x01
177
178         NvRegSlotTime = 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
182 #define NVREG_SLOTTIME_HALF             0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
184 #define NVREG_SLOTTIME_MASK             0x000000ff
185
186         NvRegTxDeferral = 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
193         NvRegRxDeferral = 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
195         NvRegMacAddrA = 0xA8,
196         NvRegMacAddrB = 0xAC,
197         NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE  0x01
199         NvRegMulticastAddrB = 0xB4,
200         NvRegMulticastMaskA = 0xB8,
201 #define NVREG_MCASTMASKA_NONE           0xffffffff
202         NvRegMulticastMaskB = 0xBC,
203 #define NVREG_MCASTMASKB_NONE           0xffff
204
205         NvRegPhyInterface = 0xC0,
206 #define PHY_RGMII               0x10000000
207         NvRegBackOffControl = 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT                  24
211 #define NVREG_BKOFFCTRL_GEAR                    12
212
213         NvRegTxRingPhysAddr = 0x100,
214         NvRegRxRingPhysAddr = 0x104,
215         NvRegRingSizes = 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218         NvRegTransmitPoll = 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220         NvRegLinkSpeed = 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10      1000
223 #define NVREG_LINKSPEED_100     100
224 #define NVREG_LINKSPEED_1000    50
225 #define NVREG_LINKSPEED_MASK    (0xFFF)
226         NvRegUnknownSetupReg5 = 0x130,
227 #define NVREG_UNKSETUP5_BIT31   (1<<31)
228         NvRegTxWatermark = 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
232         NvRegTxRxControl = 0x144,
233 #define NVREG_TXRXCTL_KICK      0x0001
234 #define NVREG_TXRXCTL_BIT1      0x0002
235 #define NVREG_TXRXCTL_BIT2      0x0004
236 #define NVREG_TXRXCTL_IDLE      0x0008
237 #define NVREG_TXRXCTL_RESET     0x0010
238 #define NVREG_TXRXCTL_RXCHECK   0x0400
239 #define NVREG_TXRXCTL_DESC_1    0
240 #define NVREG_TXRXCTL_DESC_2    0x002100
241 #define NVREG_TXRXCTL_DESC_3    0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS   0x00080
244         NvRegTxRingPhysAddrHigh = 0x148,
245         NvRegRxRingPhysAddrHigh = 0x14C,
246         NvRegTxPauseFrame = 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
251         NvRegTxPauseFrameLimit = 0x174,
252 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
253         NvRegMIIStatus = 0x180,
254 #define NVREG_MIISTAT_ERROR             0x0001
255 #define NVREG_MIISTAT_LINKCHANGE        0x0008
256 #define NVREG_MIISTAT_MASK_RW           0x0007
257 #define NVREG_MIISTAT_MASK_ALL          0x000f
258         NvRegMIIMask = 0x184,
259 #define NVREG_MII_LINKCHANGE            0x0008
260
261         NvRegAdapterControl = 0x188,
262 #define NVREG_ADAPTCTL_START    0x02
263 #define NVREG_ADAPTCTL_LINKUP   0x04
264 #define NVREG_ADAPTCTL_PHYVALID 0x40000
265 #define NVREG_ADAPTCTL_RUNNING  0x100000
266 #define NVREG_ADAPTCTL_PHYSHIFT 24
267         NvRegMIISpeed = 0x18c,
268 #define NVREG_MIISPEED_BIT8     (1<<8)
269 #define NVREG_MIIDELAY  5
270         NvRegMIIControl = 0x190,
271 #define NVREG_MIICTL_INUSE      0x08000
272 #define NVREG_MIICTL_WRITE      0x00400
273 #define NVREG_MIICTL_ADDRSHIFT  5
274         NvRegMIIData = 0x194,
275         NvRegTxUnicast = 0x1a0,
276         NvRegTxMulticast = 0x1a4,
277         NvRegTxBroadcast = 0x1a8,
278         NvRegWakeUpFlags = 0x200,
279 #define NVREG_WAKEUPFLAGS_VAL           0x7770
280 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
281 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
282 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
283 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
284 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
285 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
286 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
287 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
288 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
289 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
290
291         NvRegMgmtUnitGetVersion = 0x204,
292 #define NVREG_MGMTUNITGETVERSION        0x01
293         NvRegMgmtUnitVersion = 0x208,
294 #define NVREG_MGMTUNITVERSION           0x08
295         NvRegPowerCap = 0x268,
296 #define NVREG_POWERCAP_D3SUPP   (1<<30)
297 #define NVREG_POWERCAP_D2SUPP   (1<<26)
298 #define NVREG_POWERCAP_D1SUPP   (1<<25)
299         NvRegPowerState = 0x26c,
300 #define NVREG_POWERSTATE_POWEREDUP      0x8000
301 #define NVREG_POWERSTATE_VALID          0x0100
302 #define NVREG_POWERSTATE_MASK           0x0003
303 #define NVREG_POWERSTATE_D0             0x0000
304 #define NVREG_POWERSTATE_D1             0x0001
305 #define NVREG_POWERSTATE_D2             0x0002
306 #define NVREG_POWERSTATE_D3             0x0003
307         NvRegMgmtUnitControl = 0x278,
308 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
309         NvRegTxCnt = 0x280,
310         NvRegTxZeroReXmt = 0x284,
311         NvRegTxOneReXmt = 0x288,
312         NvRegTxManyReXmt = 0x28c,
313         NvRegTxLateCol = 0x290,
314         NvRegTxUnderflow = 0x294,
315         NvRegTxLossCarrier = 0x298,
316         NvRegTxExcessDef = 0x29c,
317         NvRegTxRetryErr = 0x2a0,
318         NvRegRxFrameErr = 0x2a4,
319         NvRegRxExtraByte = 0x2a8,
320         NvRegRxLateCol = 0x2ac,
321         NvRegRxRunt = 0x2b0,
322         NvRegRxFrameTooLong = 0x2b4,
323         NvRegRxOverflow = 0x2b8,
324         NvRegRxFCSErr = 0x2bc,
325         NvRegRxFrameAlignErr = 0x2c0,
326         NvRegRxLenErr = 0x2c4,
327         NvRegRxUnicast = 0x2c8,
328         NvRegRxMulticast = 0x2cc,
329         NvRegRxBroadcast = 0x2d0,
330         NvRegTxDef = 0x2d4,
331         NvRegTxFrame = 0x2d8,
332         NvRegRxCnt = 0x2dc,
333         NvRegTxPause = 0x2e0,
334         NvRegRxPause = 0x2e4,
335         NvRegRxDropFrame = 0x2e8,
336         NvRegVlanControl = 0x300,
337 #define NVREG_VLANCONTROL_ENABLE        0x2000
338         NvRegMSIXMap0 = 0x3e0,
339         NvRegMSIXMap1 = 0x3e4,
340         NvRegMSIXIrqStatus = 0x3f0,
341
342         NvRegPowerState2 = 0x600,
343 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
344 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
345 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
346 };
347
348 /* Big endian: should work, but is untested */
349 struct ring_desc {
350         __le32 buf;
351         __le32 flaglen;
352 };
353
354 struct ring_desc_ex {
355         __le32 bufhigh;
356         __le32 buflow;
357         __le32 txvlan;
358         __le32 flaglen;
359 };
360
361 union ring_type {
362         struct ring_desc* orig;
363         struct ring_desc_ex* ex;
364 };
365
366 #define FLAG_MASK_V1 0xffff0000
367 #define FLAG_MASK_V2 0xffffc000
368 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
369 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
370
371 #define NV_TX_LASTPACKET        (1<<16)
372 #define NV_TX_RETRYERROR        (1<<19)
373 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
374 #define NV_TX_FORCED_INTERRUPT  (1<<24)
375 #define NV_TX_DEFERRED          (1<<26)
376 #define NV_TX_CARRIERLOST       (1<<27)
377 #define NV_TX_LATECOLLISION     (1<<28)
378 #define NV_TX_UNDERFLOW         (1<<29)
379 #define NV_TX_ERROR             (1<<30)
380 #define NV_TX_VALID             (1<<31)
381
382 #define NV_TX2_LASTPACKET       (1<<29)
383 #define NV_TX2_RETRYERROR       (1<<18)
384 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
385 #define NV_TX2_FORCED_INTERRUPT (1<<30)
386 #define NV_TX2_DEFERRED         (1<<25)
387 #define NV_TX2_CARRIERLOST      (1<<26)
388 #define NV_TX2_LATECOLLISION    (1<<27)
389 #define NV_TX2_UNDERFLOW        (1<<28)
390 /* error and valid are the same for both */
391 #define NV_TX2_ERROR            (1<<30)
392 #define NV_TX2_VALID            (1<<31)
393 #define NV_TX2_TSO              (1<<28)
394 #define NV_TX2_TSO_SHIFT        14
395 #define NV_TX2_TSO_MAX_SHIFT    14
396 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
397 #define NV_TX2_CHECKSUM_L3      (1<<27)
398 #define NV_TX2_CHECKSUM_L4      (1<<26)
399
400 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
401
402 #define NV_RX_DESCRIPTORVALID   (1<<16)
403 #define NV_RX_MISSEDFRAME       (1<<17)
404 #define NV_RX_SUBSTRACT1        (1<<18)
405 #define NV_RX_ERROR1            (1<<23)
406 #define NV_RX_ERROR2            (1<<24)
407 #define NV_RX_ERROR3            (1<<25)
408 #define NV_RX_ERROR4            (1<<26)
409 #define NV_RX_CRCERR            (1<<27)
410 #define NV_RX_OVERFLOW          (1<<28)
411 #define NV_RX_FRAMINGERR        (1<<29)
412 #define NV_RX_ERROR             (1<<30)
413 #define NV_RX_AVAIL             (1<<31)
414 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
415
416 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
417 #define NV_RX2_CHECKSUM_IP      (0x10000000)
418 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
419 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
420 #define NV_RX2_DESCRIPTORVALID  (1<<29)
421 #define NV_RX2_SUBSTRACT1       (1<<25)
422 #define NV_RX2_ERROR1           (1<<18)
423 #define NV_RX2_ERROR2           (1<<19)
424 #define NV_RX2_ERROR3           (1<<20)
425 #define NV_RX2_ERROR4           (1<<21)
426 #define NV_RX2_CRCERR           (1<<22)
427 #define NV_RX2_OVERFLOW         (1<<23)
428 #define NV_RX2_FRAMINGERR       (1<<24)
429 /* error and avail are the same for both */
430 #define NV_RX2_ERROR            (1<<30)
431 #define NV_RX2_AVAIL            (1<<31)
432 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
433
434 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
435 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
436
437 /* Miscelaneous hardware related defines: */
438 #define NV_PCI_REGSZ_VER1       0x270
439 #define NV_PCI_REGSZ_VER2       0x2d4
440 #define NV_PCI_REGSZ_VER3       0x604
441 #define NV_PCI_REGSZ_MAX        0x604
442
443 /* various timeout delays: all in usec */
444 #define NV_TXRX_RESET_DELAY     4
445 #define NV_TXSTOP_DELAY1        10
446 #define NV_TXSTOP_DELAY1MAX     500000
447 #define NV_TXSTOP_DELAY2        100
448 #define NV_RXSTOP_DELAY1        10
449 #define NV_RXSTOP_DELAY1MAX     500000
450 #define NV_RXSTOP_DELAY2        100
451 #define NV_SETUP5_DELAY         5
452 #define NV_SETUP5_DELAYMAX      50000
453 #define NV_POWERUP_DELAY        5
454 #define NV_POWERUP_DELAYMAX     5000
455 #define NV_MIIBUSY_DELAY        50
456 #define NV_MIIPHY_DELAY 10
457 #define NV_MIIPHY_DELAYMAX      10000
458 #define NV_MAC_RESET_DELAY      64
459
460 #define NV_WAKEUPPATTERNS       5
461 #define NV_WAKEUPMASKENTRIES    4
462
463 /* General driver defaults */
464 #define NV_WATCHDOG_TIMEO       (5*HZ)
465
466 #define RX_RING_DEFAULT         128
467 #define TX_RING_DEFAULT         256
468 #define RX_RING_MIN             128
469 #define TX_RING_MIN             64
470 #define RING_MAX_DESC_VER_1     1024
471 #define RING_MAX_DESC_VER_2_3   16384
472
473 /* rx/tx mac addr + type + vlan + align + slack*/
474 #define NV_RX_HEADERS           (64)
475 /* even more slack. */
476 #define NV_RX_ALLOC_PAD         (64)
477
478 /* maximum mtu size */
479 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
480 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
481
482 #define OOM_REFILL      (1+HZ/20)
483 #define POLL_WAIT       (1+HZ/100)
484 #define LINK_TIMEOUT    (3*HZ)
485 #define STATS_INTERVAL  (10*HZ)
486
487 /*
488  * desc_ver values:
489  * The nic supports three different descriptor types:
490  * - DESC_VER_1: Original
491  * - DESC_VER_2: support for jumbo frames.
492  * - DESC_VER_3: 64-bit format.
493  */
494 #define DESC_VER_1      1
495 #define DESC_VER_2      2
496 #define DESC_VER_3      3
497
498 /* PHY defines */
499 #define PHY_OUI_MARVELL         0x5043
500 #define PHY_OUI_CICADA          0x03f1
501 #define PHY_OUI_VITESSE         0x01c1
502 #define PHY_OUI_REALTEK         0x0732
503 #define PHY_OUI_REALTEK2        0x0020
504 #define PHYID1_OUI_MASK 0x03ff
505 #define PHYID1_OUI_SHFT 6
506 #define PHYID2_OUI_MASK 0xfc00
507 #define PHYID2_OUI_SHFT 10
508 #define PHYID2_MODEL_MASK               0x03f0
509 #define PHY_MODEL_REALTEK_8211          0x0110
510 #define PHY_REV_MASK                    0x0001
511 #define PHY_REV_REALTEK_8211B           0x0000
512 #define PHY_REV_REALTEK_8211C           0x0001
513 #define PHY_MODEL_REALTEK_8201          0x0200
514 #define PHY_MODEL_MARVELL_E3016         0x0220
515 #define PHY_MARVELL_E3016_INITMASK      0x0300
516 #define PHY_CICADA_INIT1        0x0f000
517 #define PHY_CICADA_INIT2        0x0e00
518 #define PHY_CICADA_INIT3        0x01000
519 #define PHY_CICADA_INIT4        0x0200
520 #define PHY_CICADA_INIT5        0x0004
521 #define PHY_CICADA_INIT6        0x02000
522 #define PHY_VITESSE_INIT_REG1   0x1f
523 #define PHY_VITESSE_INIT_REG2   0x10
524 #define PHY_VITESSE_INIT_REG3   0x11
525 #define PHY_VITESSE_INIT_REG4   0x12
526 #define PHY_VITESSE_INIT_MSK1   0xc
527 #define PHY_VITESSE_INIT_MSK2   0x0180
528 #define PHY_VITESSE_INIT1       0x52b5
529 #define PHY_VITESSE_INIT2       0xaf8a
530 #define PHY_VITESSE_INIT3       0x8
531 #define PHY_VITESSE_INIT4       0x8f8a
532 #define PHY_VITESSE_INIT5       0xaf86
533 #define PHY_VITESSE_INIT6       0x8f86
534 #define PHY_VITESSE_INIT7       0xaf82
535 #define PHY_VITESSE_INIT8       0x0100
536 #define PHY_VITESSE_INIT9       0x8f82
537 #define PHY_VITESSE_INIT10      0x0
538 #define PHY_REALTEK_INIT_REG1   0x1f
539 #define PHY_REALTEK_INIT_REG2   0x19
540 #define PHY_REALTEK_INIT_REG3   0x13
541 #define PHY_REALTEK_INIT_REG4   0x14
542 #define PHY_REALTEK_INIT_REG5   0x18
543 #define PHY_REALTEK_INIT_REG6   0x11
544 #define PHY_REALTEK_INIT_REG7   0x01
545 #define PHY_REALTEK_INIT1       0x0000
546 #define PHY_REALTEK_INIT2       0x8e00
547 #define PHY_REALTEK_INIT3       0x0001
548 #define PHY_REALTEK_INIT4       0xad17
549 #define PHY_REALTEK_INIT5       0xfb54
550 #define PHY_REALTEK_INIT6       0xf5c7
551 #define PHY_REALTEK_INIT7       0x1000
552 #define PHY_REALTEK_INIT8       0x0003
553 #define PHY_REALTEK_INIT9       0x0008
554 #define PHY_REALTEK_INIT10      0x0005
555 #define PHY_REALTEK_INIT11      0x0200
556 #define PHY_REALTEK_INIT_MSK1   0x0003
557
558 #define PHY_GIGABIT     0x0100
559
560 #define PHY_TIMEOUT     0x1
561 #define PHY_ERROR       0x2
562
563 #define PHY_100 0x1
564 #define PHY_1000        0x2
565 #define PHY_HALF        0x100
566
567 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
568 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
569 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
570 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
571 #define NV_PAUSEFRAME_RX_REQ     0x0010
572 #define NV_PAUSEFRAME_TX_REQ     0x0020
573 #define NV_PAUSEFRAME_AUTONEG    0x0040
574
575 /* MSI/MSI-X defines */
576 #define NV_MSI_X_MAX_VECTORS  8
577 #define NV_MSI_X_VECTORS_MASK 0x000f
578 #define NV_MSI_CAPABLE        0x0010
579 #define NV_MSI_X_CAPABLE      0x0020
580 #define NV_MSI_ENABLED        0x0040
581 #define NV_MSI_X_ENABLED      0x0080
582
583 #define NV_MSI_X_VECTOR_ALL   0x0
584 #define NV_MSI_X_VECTOR_RX    0x0
585 #define NV_MSI_X_VECTOR_TX    0x1
586 #define NV_MSI_X_VECTOR_OTHER 0x2
587
588 #define NV_MSI_PRIV_OFFSET 0x68
589 #define NV_MSI_PRIV_VALUE  0xffffffff
590
591 #define NV_RESTART_TX         0x1
592 #define NV_RESTART_RX         0x2
593
594 #define NV_TX_LIMIT_COUNT     16
595
596 /* statistics */
597 struct nv_ethtool_str {
598         char name[ETH_GSTRING_LEN];
599 };
600
601 static const struct nv_ethtool_str nv_estats_str[] = {
602         { "tx_bytes" },
603         { "tx_zero_rexmt" },
604         { "tx_one_rexmt" },
605         { "tx_many_rexmt" },
606         { "tx_late_collision" },
607         { "tx_fifo_errors" },
608         { "tx_carrier_errors" },
609         { "tx_excess_deferral" },
610         { "tx_retry_error" },
611         { "rx_frame_error" },
612         { "rx_extra_byte" },
613         { "rx_late_collision" },
614         { "rx_runt" },
615         { "rx_frame_too_long" },
616         { "rx_over_errors" },
617         { "rx_crc_errors" },
618         { "rx_frame_align_error" },
619         { "rx_length_error" },
620         { "rx_unicast" },
621         { "rx_multicast" },
622         { "rx_broadcast" },
623         { "rx_packets" },
624         { "rx_errors_total" },
625         { "tx_errors_total" },
626
627         /* version 2 stats */
628         { "tx_deferral" },
629         { "tx_packets" },
630         { "rx_bytes" },
631         { "tx_pause" },
632         { "rx_pause" },
633         { "rx_drop_frame" },
634
635         /* version 3 stats */
636         { "tx_unicast" },
637         { "tx_multicast" },
638         { "tx_broadcast" }
639 };
640
641 struct nv_ethtool_stats {
642         u64 tx_bytes;
643         u64 tx_zero_rexmt;
644         u64 tx_one_rexmt;
645         u64 tx_many_rexmt;
646         u64 tx_late_collision;
647         u64 tx_fifo_errors;
648         u64 tx_carrier_errors;
649         u64 tx_excess_deferral;
650         u64 tx_retry_error;
651         u64 rx_frame_error;
652         u64 rx_extra_byte;
653         u64 rx_late_collision;
654         u64 rx_runt;
655         u64 rx_frame_too_long;
656         u64 rx_over_errors;
657         u64 rx_crc_errors;
658         u64 rx_frame_align_error;
659         u64 rx_length_error;
660         u64 rx_unicast;
661         u64 rx_multicast;
662         u64 rx_broadcast;
663         u64 rx_packets;
664         u64 rx_errors_total;
665         u64 tx_errors_total;
666
667         /* version 2 stats */
668         u64 tx_deferral;
669         u64 tx_packets;
670         u64 rx_bytes;
671         u64 tx_pause;
672         u64 rx_pause;
673         u64 rx_drop_frame;
674
675         /* version 3 stats */
676         u64 tx_unicast;
677         u64 tx_multicast;
678         u64 tx_broadcast;
679 };
680
681 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
682 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
683 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
684
685 /* diagnostics */
686 #define NV_TEST_COUNT_BASE 3
687 #define NV_TEST_COUNT_EXTENDED 4
688
689 static const struct nv_ethtool_str nv_etests_str[] = {
690         { "link      (online/offline)" },
691         { "register  (offline)       " },
692         { "interrupt (offline)       " },
693         { "loopback  (offline)       " }
694 };
695
696 struct register_test {
697         __u32 reg;
698         __u32 mask;
699 };
700
701 static const struct register_test nv_registers_test[] = {
702         { NvRegUnknownSetupReg6, 0x01 },
703         { NvRegMisc1, 0x03c },
704         { NvRegOffloadConfig, 0x03ff },
705         { NvRegMulticastAddrA, 0xffffffff },
706         { NvRegTxWatermark, 0x0ff },
707         { NvRegWakeUpFlags, 0x07777 },
708         { 0,0 }
709 };
710
711 struct nv_skb_map {
712         struct sk_buff *skb;
713         dma_addr_t dma;
714         unsigned int dma_len;
715         struct ring_desc_ex *first_tx_desc;
716         struct nv_skb_map *next_tx_ctx;
717 };
718
719 /*
720  * SMP locking:
721  * All hardware access under netdev_priv(dev)->lock, except the performance
722  * critical parts:
723  * - rx is (pseudo-) lockless: it relies on the single-threading provided
724  *      by the arch code for interrupts.
725  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
726  *      needs netdev_priv(dev)->lock :-(
727  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
728  */
729
730 /* in dev: base, irq */
731 struct fe_priv {
732         spinlock_t lock;
733
734         struct net_device *dev;
735         struct napi_struct napi;
736
737         /* General data:
738          * Locking: spin_lock(&np->lock); */
739         struct nv_ethtool_stats estats;
740         int in_shutdown;
741         u32 linkspeed;
742         int duplex;
743         int autoneg;
744         int fixed_mode;
745         int phyaddr;
746         int wolenabled;
747         unsigned int phy_oui;
748         unsigned int phy_model;
749         unsigned int phy_rev;
750         u16 gigabit;
751         int intr_test;
752         int recover_error;
753
754         /* General data: RO fields */
755         dma_addr_t ring_addr;
756         struct pci_dev *pci_dev;
757         u32 orig_mac[2];
758         u32 events;
759         u32 irqmask;
760         u32 desc_ver;
761         u32 txrxctl_bits;
762         u32 vlanctl_bits;
763         u32 driver_data;
764         u32 device_id;
765         u32 register_size;
766         int rx_csum;
767         u32 mac_in_use;
768         int mgmt_version;
769         int mgmt_sema;
770
771         void __iomem *base;
772
773         /* rx specific fields.
774          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
775          */
776         union ring_type get_rx, put_rx, first_rx, last_rx;
777         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
778         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
779         struct nv_skb_map *rx_skb;
780
781         union ring_type rx_ring;
782         unsigned int rx_buf_sz;
783         unsigned int pkt_limit;
784         struct timer_list oom_kick;
785         struct timer_list nic_poll;
786         struct timer_list stats_poll;
787         u32 nic_poll_irq;
788         int rx_ring_size;
789
790         /* media detection workaround.
791          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
792          */
793         int need_linktimer;
794         unsigned long link_timeout;
795         /*
796          * tx specific fields.
797          */
798         union ring_type get_tx, put_tx, first_tx, last_tx;
799         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
800         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
801         struct nv_skb_map *tx_skb;
802
803         union ring_type tx_ring;
804         u32 tx_flags;
805         int tx_ring_size;
806         int tx_limit;
807         u32 tx_pkts_in_progress;
808         struct nv_skb_map *tx_change_owner;
809         struct nv_skb_map *tx_end_flip;
810         int tx_stop;
811
812         /* vlan fields */
813         struct vlan_group *vlangrp;
814
815         /* msi/msi-x fields */
816         u32 msi_flags;
817         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
818
819         /* flow control */
820         u32 pause_flags;
821
822         /* power saved state */
823         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
824
825         /* for different msi-x irq type */
826         char name_rx[IFNAMSIZ + 3];       /* -rx    */
827         char name_tx[IFNAMSIZ + 3];       /* -tx    */
828         char name_other[IFNAMSIZ + 6];    /* -other */
829 };
830
831 /*
832  * Maximum number of loops until we assume that a bit in the irq mask
833  * is stuck. Overridable with module param.
834  */
835 static int max_interrupt_work = 15;
836
837 /*
838  * Optimization can be either throuput mode or cpu mode
839  *
840  * Throughput Mode: Every tx and rx packet will generate an interrupt.
841  * CPU Mode: Interrupts are controlled by a timer.
842  */
843 enum {
844         NV_OPTIMIZATION_MODE_THROUGHPUT,
845         NV_OPTIMIZATION_MODE_CPU,
846         NV_OPTIMIZATION_MODE_DYNAMIC
847 };
848 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
849
850 /*
851  * Poll interval for timer irq
852  *
853  * This interval determines how frequent an interrupt is generated.
854  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
855  * Min = 0, and Max = 65535
856  */
857 static int poll_interval = -1;
858
859 /*
860  * MSI interrupts
861  */
862 enum {
863         NV_MSI_INT_DISABLED,
864         NV_MSI_INT_ENABLED
865 };
866 static int msi = NV_MSI_INT_ENABLED;
867
868 /*
869  * MSIX interrupts
870  */
871 enum {
872         NV_MSIX_INT_DISABLED,
873         NV_MSIX_INT_ENABLED
874 };
875 static int msix = NV_MSIX_INT_ENABLED;
876
877 /*
878  * DMA 64bit
879  */
880 enum {
881         NV_DMA_64BIT_DISABLED,
882         NV_DMA_64BIT_ENABLED
883 };
884 static int dma_64bit = NV_DMA_64BIT_ENABLED;
885
886 /*
887  * Crossover Detection
888  * Realtek 8201 phy + some OEM boards do not work properly.
889  */
890 enum {
891         NV_CROSSOVER_DETECTION_DISABLED,
892         NV_CROSSOVER_DETECTION_ENABLED
893 };
894 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
895
896 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
897 {
898         return netdev_priv(dev);
899 }
900
901 static inline u8 __iomem *get_hwbase(struct net_device *dev)
902 {
903         return ((struct fe_priv *)netdev_priv(dev))->base;
904 }
905
906 static inline void pci_push(u8 __iomem *base)
907 {
908         /* force out pending posted writes */
909         readl(base);
910 }
911
912 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
913 {
914         return le32_to_cpu(prd->flaglen)
915                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
916 }
917
918 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
919 {
920         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
921 }
922
923 static bool nv_optimized(struct fe_priv *np)
924 {
925         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
926                 return false;
927         return true;
928 }
929
930 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
931                                 int delay, int delaymax, const char *msg)
932 {
933         u8 __iomem *base = get_hwbase(dev);
934
935         pci_push(base);
936         do {
937                 udelay(delay);
938                 delaymax -= delay;
939                 if (delaymax < 0) {
940                         if (msg)
941                                 printk("%s", msg);
942                         return 1;
943                 }
944         } while ((readl(base + offset) & mask) != target);
945         return 0;
946 }
947
948 #define NV_SETUP_RX_RING 0x01
949 #define NV_SETUP_TX_RING 0x02
950
951 static inline u32 dma_low(dma_addr_t addr)
952 {
953         return addr;
954 }
955
956 static inline u32 dma_high(dma_addr_t addr)
957 {
958         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
959 }
960
961 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
962 {
963         struct fe_priv *np = get_nvpriv(dev);
964         u8 __iomem *base = get_hwbase(dev);
965
966         if (!nv_optimized(np)) {
967                 if (rxtx_flags & NV_SETUP_RX_RING) {
968                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
969                 }
970                 if (rxtx_flags & NV_SETUP_TX_RING) {
971                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
972                 }
973         } else {
974                 if (rxtx_flags & NV_SETUP_RX_RING) {
975                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
976                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
977                 }
978                 if (rxtx_flags & NV_SETUP_TX_RING) {
979                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
980                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
981                 }
982         }
983 }
984
985 static void free_rings(struct net_device *dev)
986 {
987         struct fe_priv *np = get_nvpriv(dev);
988
989         if (!nv_optimized(np)) {
990                 if (np->rx_ring.orig)
991                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
992                                             np->rx_ring.orig, np->ring_addr);
993         } else {
994                 if (np->rx_ring.ex)
995                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
996                                             np->rx_ring.ex, np->ring_addr);
997         }
998         if (np->rx_skb)
999                 kfree(np->rx_skb);
1000         if (np->tx_skb)
1001                 kfree(np->tx_skb);
1002 }
1003
1004 static int using_multi_irqs(struct net_device *dev)
1005 {
1006         struct fe_priv *np = get_nvpriv(dev);
1007
1008         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1009             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1010              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1011                 return 0;
1012         else
1013                 return 1;
1014 }
1015
1016 static void nv_enable_irq(struct net_device *dev)
1017 {
1018         struct fe_priv *np = get_nvpriv(dev);
1019
1020         if (!using_multi_irqs(dev)) {
1021                 if (np->msi_flags & NV_MSI_X_ENABLED)
1022                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1023                 else
1024                         enable_irq(np->pci_dev->irq);
1025         } else {
1026                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1027                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1028                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1029         }
1030 }
1031
1032 static void nv_disable_irq(struct net_device *dev)
1033 {
1034         struct fe_priv *np = get_nvpriv(dev);
1035
1036         if (!using_multi_irqs(dev)) {
1037                 if (np->msi_flags & NV_MSI_X_ENABLED)
1038                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1039                 else
1040                         disable_irq(np->pci_dev->irq);
1041         } else {
1042                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1043                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1044                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1045         }
1046 }
1047
1048 /* In MSIX mode, a write to irqmask behaves as XOR */
1049 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1050 {
1051         u8 __iomem *base = get_hwbase(dev);
1052
1053         writel(mask, base + NvRegIrqMask);
1054 }
1055
1056 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1057 {
1058         struct fe_priv *np = get_nvpriv(dev);
1059         u8 __iomem *base = get_hwbase(dev);
1060
1061         if (np->msi_flags & NV_MSI_X_ENABLED) {
1062                 writel(mask, base + NvRegIrqMask);
1063         } else {
1064                 if (np->msi_flags & NV_MSI_ENABLED)
1065                         writel(0, base + NvRegMSIIrqMask);
1066                 writel(0, base + NvRegIrqMask);
1067         }
1068 }
1069
1070 static void nv_napi_enable(struct net_device *dev)
1071 {
1072 #ifdef CONFIG_FORCEDETH_NAPI
1073         struct fe_priv *np = get_nvpriv(dev);
1074
1075         napi_enable(&np->napi);
1076 #endif
1077 }
1078
1079 static void nv_napi_disable(struct net_device *dev)
1080 {
1081 #ifdef CONFIG_FORCEDETH_NAPI
1082         struct fe_priv *np = get_nvpriv(dev);
1083
1084         napi_disable(&np->napi);
1085 #endif
1086 }
1087
1088 #define MII_READ        (-1)
1089 /* mii_rw: read/write a register on the PHY.
1090  *
1091  * Caller must guarantee serialization
1092  */
1093 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1094 {
1095         u8 __iomem *base = get_hwbase(dev);
1096         u32 reg;
1097         int retval;
1098
1099         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1100
1101         reg = readl(base + NvRegMIIControl);
1102         if (reg & NVREG_MIICTL_INUSE) {
1103                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1104                 udelay(NV_MIIBUSY_DELAY);
1105         }
1106
1107         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1108         if (value != MII_READ) {
1109                 writel(value, base + NvRegMIIData);
1110                 reg |= NVREG_MIICTL_WRITE;
1111         }
1112         writel(reg, base + NvRegMIIControl);
1113
1114         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1115                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1116                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1117                                 dev->name, miireg, addr);
1118                 retval = -1;
1119         } else if (value != MII_READ) {
1120                 /* it was a write operation - fewer failures are detectable */
1121                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1122                                 dev->name, value, miireg, addr);
1123                 retval = 0;
1124         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1125                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1126                                 dev->name, miireg, addr);
1127                 retval = -1;
1128         } else {
1129                 retval = readl(base + NvRegMIIData);
1130                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1131                                 dev->name, miireg, addr, retval);
1132         }
1133
1134         return retval;
1135 }
1136
1137 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1138 {
1139         struct fe_priv *np = netdev_priv(dev);
1140         u32 miicontrol;
1141         unsigned int tries = 0;
1142
1143         miicontrol = BMCR_RESET | bmcr_setup;
1144         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1145                 return -1;
1146         }
1147
1148         /* wait for 500ms */
1149         msleep(500);
1150
1151         /* must wait till reset is deasserted */
1152         while (miicontrol & BMCR_RESET) {
1153                 msleep(10);
1154                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1155                 /* FIXME: 100 tries seem excessive */
1156                 if (tries++ > 100)
1157                         return -1;
1158         }
1159         return 0;
1160 }
1161
1162 static int phy_init(struct net_device *dev)
1163 {
1164         struct fe_priv *np = get_nvpriv(dev);
1165         u8 __iomem *base = get_hwbase(dev);
1166         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1167
1168         /* phy errata for E3016 phy */
1169         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1170                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1171                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1172                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1173                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1174                         return PHY_ERROR;
1175                 }
1176         }
1177         if (np->phy_oui == PHY_OUI_REALTEK) {
1178                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1179                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1180                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1181                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1182                                 return PHY_ERROR;
1183                         }
1184                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1185                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1186                                 return PHY_ERROR;
1187                         }
1188                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1189                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1190                                 return PHY_ERROR;
1191                         }
1192                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1193                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1194                                 return PHY_ERROR;
1195                         }
1196                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1197                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1198                                 return PHY_ERROR;
1199                         }
1200                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1201                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1202                                 return PHY_ERROR;
1203                         }
1204                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1205                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1206                                 return PHY_ERROR;
1207                         }
1208                 }
1209                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1210                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1211                         u32 powerstate = readl(base + NvRegPowerState2);
1212
1213                         /* need to perform hw phy reset */
1214                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1215                         writel(powerstate, base + NvRegPowerState2);
1216                         msleep(25);
1217
1218                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1219                         writel(powerstate, base + NvRegPowerState2);
1220                         msleep(25);
1221
1222                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1223                         reg |= PHY_REALTEK_INIT9;
1224                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1225                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1226                                 return PHY_ERROR;
1227                         }
1228                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1229                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230                                 return PHY_ERROR;
1231                         }
1232                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1233                         if (!(reg & PHY_REALTEK_INIT11)) {
1234                                 reg |= PHY_REALTEK_INIT11;
1235                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1236                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1237                                         return PHY_ERROR;
1238                                 }
1239                         }
1240                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1241                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1242                                 return PHY_ERROR;
1243                         }
1244                 }
1245                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1246                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1247                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1248                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1249                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1250                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1251                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1252                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1253                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1254                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1255                                 phy_reserved |= PHY_REALTEK_INIT7;
1256                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1257                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1258                                         return PHY_ERROR;
1259                                 }
1260                         }
1261                 }
1262         }
1263
1264         /* set advertise register */
1265         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1266         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1267         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1268                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1269                 return PHY_ERROR;
1270         }
1271
1272         /* get phy interface type */
1273         phyinterface = readl(base + NvRegPhyInterface);
1274
1275         /* see if gigabit phy */
1276         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1277         if (mii_status & PHY_GIGABIT) {
1278                 np->gigabit = PHY_GIGABIT;
1279                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1280                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1281                 if (phyinterface & PHY_RGMII)
1282                         mii_control_1000 |= ADVERTISE_1000FULL;
1283                 else
1284                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1285
1286                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1287                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1288                         return PHY_ERROR;
1289                 }
1290         }
1291         else
1292                 np->gigabit = 0;
1293
1294         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1295         mii_control |= BMCR_ANENABLE;
1296
1297         if (np->phy_oui == PHY_OUI_REALTEK &&
1298             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1299             np->phy_rev == PHY_REV_REALTEK_8211C) {
1300                 /* start autoneg since we already performed hw reset above */
1301                 mii_control |= BMCR_ANRESTART;
1302                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1303                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1304                         return PHY_ERROR;
1305                 }
1306         } else {
1307                 /* reset the phy
1308                  * (certain phys need bmcr to be setup with reset)
1309                  */
1310                 if (phy_reset(dev, mii_control)) {
1311                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1312                         return PHY_ERROR;
1313                 }
1314         }
1315
1316         /* phy vendor specific configuration */
1317         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1318                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1319                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1320                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1321                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1322                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1323                         return PHY_ERROR;
1324                 }
1325                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1326                 phy_reserved |= PHY_CICADA_INIT5;
1327                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1328                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1329                         return PHY_ERROR;
1330                 }
1331         }
1332         if (np->phy_oui == PHY_OUI_CICADA) {
1333                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1334                 phy_reserved |= PHY_CICADA_INIT6;
1335                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1336                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1337                         return PHY_ERROR;
1338                 }
1339         }
1340         if (np->phy_oui == PHY_OUI_VITESSE) {
1341                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1342                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1343                         return PHY_ERROR;
1344                 }
1345                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1346                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1347                         return PHY_ERROR;
1348                 }
1349                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1350                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1351                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1352                         return PHY_ERROR;
1353                 }
1354                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1355                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1356                 phy_reserved |= PHY_VITESSE_INIT3;
1357                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1358                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1359                         return PHY_ERROR;
1360                 }
1361                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1362                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1363                         return PHY_ERROR;
1364                 }
1365                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1366                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1367                         return PHY_ERROR;
1368                 }
1369                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1370                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1371                 phy_reserved |= PHY_VITESSE_INIT3;
1372                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1373                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1374                         return PHY_ERROR;
1375                 }
1376                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1377                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1378                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1379                         return PHY_ERROR;
1380                 }
1381                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1382                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1383                         return PHY_ERROR;
1384                 }
1385                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1386                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387                         return PHY_ERROR;
1388                 }
1389                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1390                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1391                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1392                         return PHY_ERROR;
1393                 }
1394                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1395                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1396                 phy_reserved |= PHY_VITESSE_INIT8;
1397                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1398                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1399                         return PHY_ERROR;
1400                 }
1401                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1402                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1403                         return PHY_ERROR;
1404                 }
1405                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1406                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407                         return PHY_ERROR;
1408                 }
1409         }
1410         if (np->phy_oui == PHY_OUI_REALTEK) {
1411                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1412                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1413                         /* reset could have cleared these out, set them back */
1414                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1415                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1416                                 return PHY_ERROR;
1417                         }
1418                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1419                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1420                                 return PHY_ERROR;
1421                         }
1422                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1423                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1424                                 return PHY_ERROR;
1425                         }
1426                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1427                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1428                                 return PHY_ERROR;
1429                         }
1430                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1431                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1432                                 return PHY_ERROR;
1433                         }
1434                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1435                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1436                                 return PHY_ERROR;
1437                         }
1438                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1439                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1440                                 return PHY_ERROR;
1441                         }
1442                 }
1443                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1444                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1445                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1446                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1447                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1448                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1449                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1450                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1451                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1452                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1453                                 phy_reserved |= PHY_REALTEK_INIT7;
1454                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1455                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1456                                         return PHY_ERROR;
1457                                 }
1458                         }
1459                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1460                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1461                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1462                                         return PHY_ERROR;
1463                                 }
1464                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1465                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1466                                 phy_reserved |= PHY_REALTEK_INIT3;
1467                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1468                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1469                                         return PHY_ERROR;
1470                                 }
1471                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1472                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1473                                         return PHY_ERROR;
1474                                 }
1475                         }
1476                 }
1477         }
1478
1479         /* some phys clear out pause advertisment on reset, set it back */
1480         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1481
1482         /* restart auto negotiation, power down phy */
1483         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1484         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1485         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1486                 return PHY_ERROR;
1487         }
1488
1489         return 0;
1490 }
1491
1492 static void nv_start_rx(struct net_device *dev)
1493 {
1494         struct fe_priv *np = netdev_priv(dev);
1495         u8 __iomem *base = get_hwbase(dev);
1496         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1497
1498         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1499         /* Already running? Stop it. */
1500         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1501                 rx_ctrl &= ~NVREG_RCVCTL_START;
1502                 writel(rx_ctrl, base + NvRegReceiverControl);
1503                 pci_push(base);
1504         }
1505         writel(np->linkspeed, base + NvRegLinkSpeed);
1506         pci_push(base);
1507         rx_ctrl |= NVREG_RCVCTL_START;
1508         if (np->mac_in_use)
1509                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1510         writel(rx_ctrl, base + NvRegReceiverControl);
1511         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1512                                 dev->name, np->duplex, np->linkspeed);
1513         pci_push(base);
1514 }
1515
1516 static void nv_stop_rx(struct net_device *dev)
1517 {
1518         struct fe_priv *np = netdev_priv(dev);
1519         u8 __iomem *base = get_hwbase(dev);
1520         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1521
1522         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1523         if (!np->mac_in_use)
1524                 rx_ctrl &= ~NVREG_RCVCTL_START;
1525         else
1526                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1527         writel(rx_ctrl, base + NvRegReceiverControl);
1528         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1529                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1530                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1531
1532         udelay(NV_RXSTOP_DELAY2);
1533         if (!np->mac_in_use)
1534                 writel(0, base + NvRegLinkSpeed);
1535 }
1536
1537 static void nv_start_tx(struct net_device *dev)
1538 {
1539         struct fe_priv *np = netdev_priv(dev);
1540         u8 __iomem *base = get_hwbase(dev);
1541         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1542
1543         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1544         tx_ctrl |= NVREG_XMITCTL_START;
1545         if (np->mac_in_use)
1546                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1547         writel(tx_ctrl, base + NvRegTransmitterControl);
1548         pci_push(base);
1549 }
1550
1551 static void nv_stop_tx(struct net_device *dev)
1552 {
1553         struct fe_priv *np = netdev_priv(dev);
1554         u8 __iomem *base = get_hwbase(dev);
1555         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1556
1557         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1558         if (!np->mac_in_use)
1559                 tx_ctrl &= ~NVREG_XMITCTL_START;
1560         else
1561                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1562         writel(tx_ctrl, base + NvRegTransmitterControl);
1563         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1564                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1565                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1566
1567         udelay(NV_TXSTOP_DELAY2);
1568         if (!np->mac_in_use)
1569                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1570                        base + NvRegTransmitPoll);
1571 }
1572
1573 static void nv_start_rxtx(struct net_device *dev)
1574 {
1575         nv_start_rx(dev);
1576         nv_start_tx(dev);
1577 }
1578
1579 static void nv_stop_rxtx(struct net_device *dev)
1580 {
1581         nv_stop_rx(dev);
1582         nv_stop_tx(dev);
1583 }
1584
1585 static void nv_txrx_reset(struct net_device *dev)
1586 {
1587         struct fe_priv *np = netdev_priv(dev);
1588         u8 __iomem *base = get_hwbase(dev);
1589
1590         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1591         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1592         pci_push(base);
1593         udelay(NV_TXRX_RESET_DELAY);
1594         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1595         pci_push(base);
1596 }
1597
1598 static void nv_mac_reset(struct net_device *dev)
1599 {
1600         struct fe_priv *np = netdev_priv(dev);
1601         u8 __iomem *base = get_hwbase(dev);
1602         u32 temp1, temp2, temp3;
1603
1604         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1605
1606         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1607         pci_push(base);
1608
1609         /* save registers since they will be cleared on reset */
1610         temp1 = readl(base + NvRegMacAddrA);
1611         temp2 = readl(base + NvRegMacAddrB);
1612         temp3 = readl(base + NvRegTransmitPoll);
1613
1614         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1615         pci_push(base);
1616         udelay(NV_MAC_RESET_DELAY);
1617         writel(0, base + NvRegMacReset);
1618         pci_push(base);
1619         udelay(NV_MAC_RESET_DELAY);
1620
1621         /* restore saved registers */
1622         writel(temp1, base + NvRegMacAddrA);
1623         writel(temp2, base + NvRegMacAddrB);
1624         writel(temp3, base + NvRegTransmitPoll);
1625
1626         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1627         pci_push(base);
1628 }
1629
1630 static void nv_get_hw_stats(struct net_device *dev)
1631 {
1632         struct fe_priv *np = netdev_priv(dev);
1633         u8 __iomem *base = get_hwbase(dev);
1634
1635         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1636         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1637         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1638         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1639         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1640         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1641         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1642         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1643         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1644         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1645         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1646         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1647         np->estats.rx_runt += readl(base + NvRegRxRunt);
1648         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1649         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1650         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1651         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1652         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1653         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1654         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1655         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1656         np->estats.rx_packets =
1657                 np->estats.rx_unicast +
1658                 np->estats.rx_multicast +
1659                 np->estats.rx_broadcast;
1660         np->estats.rx_errors_total =
1661                 np->estats.rx_crc_errors +
1662                 np->estats.rx_over_errors +
1663                 np->estats.rx_frame_error +
1664                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1665                 np->estats.rx_late_collision +
1666                 np->estats.rx_runt +
1667                 np->estats.rx_frame_too_long;
1668         np->estats.tx_errors_total =
1669                 np->estats.tx_late_collision +
1670                 np->estats.tx_fifo_errors +
1671                 np->estats.tx_carrier_errors +
1672                 np->estats.tx_excess_deferral +
1673                 np->estats.tx_retry_error;
1674
1675         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1676                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1677                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1678                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1679                 np->estats.tx_pause += readl(base + NvRegTxPause);
1680                 np->estats.rx_pause += readl(base + NvRegRxPause);
1681                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1682         }
1683
1684         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1685                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1686                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1687                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1688         }
1689 }
1690
1691 /*
1692  * nv_get_stats: dev->get_stats function
1693  * Get latest stats value from the nic.
1694  * Called with read_lock(&dev_base_lock) held for read -
1695  * only synchronized against unregister_netdevice.
1696  */
1697 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1698 {
1699         struct fe_priv *np = netdev_priv(dev);
1700
1701         /* If the nic supports hw counters then retrieve latest values */
1702         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1703                 nv_get_hw_stats(dev);
1704
1705                 /* copy to net_device stats */
1706                 dev->stats.tx_bytes = np->estats.tx_bytes;
1707                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1708                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1709                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1710                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1711                 dev->stats.rx_errors = np->estats.rx_errors_total;
1712                 dev->stats.tx_errors = np->estats.tx_errors_total;
1713         }
1714
1715         return &dev->stats;
1716 }
1717
1718 /*
1719  * nv_alloc_rx: fill rx ring entries.
1720  * Return 1 if the allocations for the skbs failed and the
1721  * rx engine is without Available descriptors
1722  */
1723 static int nv_alloc_rx(struct net_device *dev)
1724 {
1725         struct fe_priv *np = netdev_priv(dev);
1726         struct ring_desc* less_rx;
1727
1728         less_rx = np->get_rx.orig;
1729         if (less_rx-- == np->first_rx.orig)
1730                 less_rx = np->last_rx.orig;
1731
1732         while (np->put_rx.orig != less_rx) {
1733                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1734                 if (skb) {
1735                         np->put_rx_ctx->skb = skb;
1736                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1737                                                              skb->data,
1738                                                              skb_tailroom(skb),
1739                                                              PCI_DMA_FROMDEVICE);
1740                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1741                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1742                         wmb();
1743                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1744                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1745                                 np->put_rx.orig = np->first_rx.orig;
1746                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1747                                 np->put_rx_ctx = np->first_rx_ctx;
1748                 } else {
1749                         return 1;
1750                 }
1751         }
1752         return 0;
1753 }
1754
1755 static int nv_alloc_rx_optimized(struct net_device *dev)
1756 {
1757         struct fe_priv *np = netdev_priv(dev);
1758         struct ring_desc_ex* less_rx;
1759
1760         less_rx = np->get_rx.ex;
1761         if (less_rx-- == np->first_rx.ex)
1762                 less_rx = np->last_rx.ex;
1763
1764         while (np->put_rx.ex != less_rx) {
1765                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1766                 if (skb) {
1767                         np->put_rx_ctx->skb = skb;
1768                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1769                                                              skb->data,
1770                                                              skb_tailroom(skb),
1771                                                              PCI_DMA_FROMDEVICE);
1772                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1773                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1774                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1775                         wmb();
1776                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1777                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1778                                 np->put_rx.ex = np->first_rx.ex;
1779                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1780                                 np->put_rx_ctx = np->first_rx_ctx;
1781                 } else {
1782                         return 1;
1783                 }
1784         }
1785         return 0;
1786 }
1787
1788 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1789 #ifdef CONFIG_FORCEDETH_NAPI
1790 static void nv_do_rx_refill(unsigned long data)
1791 {
1792         struct net_device *dev = (struct net_device *) data;
1793         struct fe_priv *np = netdev_priv(dev);
1794
1795         /* Just reschedule NAPI rx processing */
1796         napi_schedule(&np->napi);
1797 }
1798 #else
1799 static void nv_do_rx_refill(unsigned long data)
1800 {
1801         struct net_device *dev = (struct net_device *) data;
1802         struct fe_priv *np = netdev_priv(dev);
1803         int retcode;
1804
1805         if (!using_multi_irqs(dev)) {
1806                 if (np->msi_flags & NV_MSI_X_ENABLED)
1807                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1808                 else
1809                         disable_irq(np->pci_dev->irq);
1810         } else {
1811                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1812         }
1813         if (!nv_optimized(np))
1814                 retcode = nv_alloc_rx(dev);
1815         else
1816                 retcode = nv_alloc_rx_optimized(dev);
1817         if (retcode) {
1818                 spin_lock_irq(&np->lock);
1819                 if (!np->in_shutdown)
1820                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1821                 spin_unlock_irq(&np->lock);
1822         }
1823         if (!using_multi_irqs(dev)) {
1824                 if (np->msi_flags & NV_MSI_X_ENABLED)
1825                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1826                 else
1827                         enable_irq(np->pci_dev->irq);
1828         } else {
1829                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1830         }
1831 }
1832 #endif
1833
1834 static void nv_init_rx(struct net_device *dev)
1835 {
1836         struct fe_priv *np = netdev_priv(dev);
1837         int i;
1838
1839         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1840
1841         if (!nv_optimized(np))
1842                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1843         else
1844                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1845         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1846         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1847
1848         for (i = 0; i < np->rx_ring_size; i++) {
1849                 if (!nv_optimized(np)) {
1850                         np->rx_ring.orig[i].flaglen = 0;
1851                         np->rx_ring.orig[i].buf = 0;
1852                 } else {
1853                         np->rx_ring.ex[i].flaglen = 0;
1854                         np->rx_ring.ex[i].txvlan = 0;
1855                         np->rx_ring.ex[i].bufhigh = 0;
1856                         np->rx_ring.ex[i].buflow = 0;
1857                 }
1858                 np->rx_skb[i].skb = NULL;
1859                 np->rx_skb[i].dma = 0;
1860         }
1861 }
1862
1863 static void nv_init_tx(struct net_device *dev)
1864 {
1865         struct fe_priv *np = netdev_priv(dev);
1866         int i;
1867
1868         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1869
1870         if (!nv_optimized(np))
1871                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1872         else
1873                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1874         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1875         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1876         np->tx_pkts_in_progress = 0;
1877         np->tx_change_owner = NULL;
1878         np->tx_end_flip = NULL;
1879
1880         for (i = 0; i < np->tx_ring_size; i++) {
1881                 if (!nv_optimized(np)) {
1882                         np->tx_ring.orig[i].flaglen = 0;
1883                         np->tx_ring.orig[i].buf = 0;
1884                 } else {
1885                         np->tx_ring.ex[i].flaglen = 0;
1886                         np->tx_ring.ex[i].txvlan = 0;
1887                         np->tx_ring.ex[i].bufhigh = 0;
1888                         np->tx_ring.ex[i].buflow = 0;
1889                 }
1890                 np->tx_skb[i].skb = NULL;
1891                 np->tx_skb[i].dma = 0;
1892                 np->tx_skb[i].dma_len = 0;
1893                 np->tx_skb[i].first_tx_desc = NULL;
1894                 np->tx_skb[i].next_tx_ctx = NULL;
1895         }
1896 }
1897
1898 static int nv_init_ring(struct net_device *dev)
1899 {
1900         struct fe_priv *np = netdev_priv(dev);
1901
1902         nv_init_tx(dev);
1903         nv_init_rx(dev);
1904
1905         if (!nv_optimized(np))
1906                 return nv_alloc_rx(dev);
1907         else
1908                 return nv_alloc_rx_optimized(dev);
1909 }
1910
1911 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1912 {
1913         struct fe_priv *np = netdev_priv(dev);
1914
1915         if (tx_skb->dma) {
1916                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1917                                tx_skb->dma_len,
1918                                PCI_DMA_TODEVICE);
1919                 tx_skb->dma = 0;
1920         }
1921         if (tx_skb->skb) {
1922                 dev_kfree_skb_any(tx_skb->skb);
1923                 tx_skb->skb = NULL;
1924                 return 1;
1925         } else {
1926                 return 0;
1927         }
1928 }
1929
1930 static void nv_drain_tx(struct net_device *dev)
1931 {
1932         struct fe_priv *np = netdev_priv(dev);
1933         unsigned int i;
1934
1935         for (i = 0; i < np->tx_ring_size; i++) {
1936                 if (!nv_optimized(np)) {
1937                         np->tx_ring.orig[i].flaglen = 0;
1938                         np->tx_ring.orig[i].buf = 0;
1939                 } else {
1940                         np->tx_ring.ex[i].flaglen = 0;
1941                         np->tx_ring.ex[i].txvlan = 0;
1942                         np->tx_ring.ex[i].bufhigh = 0;
1943                         np->tx_ring.ex[i].buflow = 0;
1944                 }
1945                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1946                         dev->stats.tx_dropped++;
1947                 np->tx_skb[i].dma = 0;
1948                 np->tx_skb[i].dma_len = 0;
1949                 np->tx_skb[i].first_tx_desc = NULL;
1950                 np->tx_skb[i].next_tx_ctx = NULL;
1951         }
1952         np->tx_pkts_in_progress = 0;
1953         np->tx_change_owner = NULL;
1954         np->tx_end_flip = NULL;
1955 }
1956
1957 static void nv_drain_rx(struct net_device *dev)
1958 {
1959         struct fe_priv *np = netdev_priv(dev);
1960         int i;
1961
1962         for (i = 0; i < np->rx_ring_size; i++) {
1963                 if (!nv_optimized(np)) {
1964                         np->rx_ring.orig[i].flaglen = 0;
1965                         np->rx_ring.orig[i].buf = 0;
1966                 } else {
1967                         np->rx_ring.ex[i].flaglen = 0;
1968                         np->rx_ring.ex[i].txvlan = 0;
1969                         np->rx_ring.ex[i].bufhigh = 0;
1970                         np->rx_ring.ex[i].buflow = 0;
1971                 }
1972                 wmb();
1973                 if (np->rx_skb[i].skb) {
1974                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1975                                          (skb_end_pointer(np->rx_skb[i].skb) -
1976                                           np->rx_skb[i].skb->data),
1977                                          PCI_DMA_FROMDEVICE);
1978                         dev_kfree_skb(np->rx_skb[i].skb);
1979                         np->rx_skb[i].skb = NULL;
1980                 }
1981         }
1982 }
1983
1984 static void nv_drain_rxtx(struct net_device *dev)
1985 {
1986         nv_drain_tx(dev);
1987         nv_drain_rx(dev);
1988 }
1989
1990 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1991 {
1992         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1993 }
1994
1995 static void nv_legacybackoff_reseed(struct net_device *dev)
1996 {
1997         u8 __iomem *base = get_hwbase(dev);
1998         u32 reg;
1999         u32 low;
2000         int tx_status = 0;
2001
2002         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2003         get_random_bytes(&low, sizeof(low));
2004         reg |= low & NVREG_SLOTTIME_MASK;
2005
2006         /* Need to stop tx before change takes effect.
2007          * Caller has already gained np->lock.
2008          */
2009         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2010         if (tx_status)
2011                 nv_stop_tx(dev);
2012         nv_stop_rx(dev);
2013         writel(reg, base + NvRegSlotTime);
2014         if (tx_status)
2015                 nv_start_tx(dev);
2016         nv_start_rx(dev);
2017 }
2018
2019 /* Gear Backoff Seeds */
2020 #define BACKOFF_SEEDSET_ROWS    8
2021 #define BACKOFF_SEEDSET_LFSRS   15
2022
2023 /* Known Good seed sets */
2024 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2025     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2026     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2027     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2028     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2029     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2030     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2031     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2032     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2033
2034 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2035     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2036     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2037     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2038     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2039     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2040     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2041     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2042     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2043
2044 static void nv_gear_backoff_reseed(struct net_device *dev)
2045 {
2046         u8 __iomem *base = get_hwbase(dev);
2047         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2048         u32 temp, seedset, combinedSeed;
2049         int i;
2050
2051         /* Setup seed for free running LFSR */
2052         /* We are going to read the time stamp counter 3 times
2053            and swizzle bits around to increase randomness */
2054         get_random_bytes(&miniseed1, sizeof(miniseed1));
2055         miniseed1 &= 0x0fff;
2056         if (miniseed1 == 0)
2057                 miniseed1 = 0xabc;
2058
2059         get_random_bytes(&miniseed2, sizeof(miniseed2));
2060         miniseed2 &= 0x0fff;
2061         if (miniseed2 == 0)
2062                 miniseed2 = 0xabc;
2063         miniseed2_reversed =
2064                 ((miniseed2 & 0xF00) >> 8) |
2065                  (miniseed2 & 0x0F0) |
2066                  ((miniseed2 & 0x00F) << 8);
2067
2068         get_random_bytes(&miniseed3, sizeof(miniseed3));
2069         miniseed3 &= 0x0fff;
2070         if (miniseed3 == 0)
2071                 miniseed3 = 0xabc;
2072         miniseed3_reversed =
2073                 ((miniseed3 & 0xF00) >> 8) |
2074                  (miniseed3 & 0x0F0) |
2075                  ((miniseed3 & 0x00F) << 8);
2076
2077         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2078                        (miniseed2 ^ miniseed3_reversed);
2079
2080         /* Seeds can not be zero */
2081         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2082                 combinedSeed |= 0x08;
2083         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2084                 combinedSeed |= 0x8000;
2085
2086         /* No need to disable tx here */
2087         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2088         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2089         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2090         writel(temp,base + NvRegBackOffControl);
2091
2092         /* Setup seeds for all gear LFSRs. */
2093         get_random_bytes(&seedset, sizeof(seedset));
2094         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2095         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2096         {
2097                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2098                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2099                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2100                 writel(temp, base + NvRegBackOffControl);
2101         }
2102 }
2103
2104 /*
2105  * nv_start_xmit: dev->hard_start_xmit function
2106  * Called with netif_tx_lock held.
2107  */
2108 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2109 {
2110         struct fe_priv *np = netdev_priv(dev);
2111         u32 tx_flags = 0;
2112         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2113         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2114         unsigned int i;
2115         u32 offset = 0;
2116         u32 bcnt;
2117         u32 size = skb->len-skb->data_len;
2118         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2119         u32 empty_slots;
2120         struct ring_desc* put_tx;
2121         struct ring_desc* start_tx;
2122         struct ring_desc* prev_tx;
2123         struct nv_skb_map* prev_tx_ctx;
2124         unsigned long flags;
2125
2126         /* add fragments to entries count */
2127         for (i = 0; i < fragments; i++) {
2128                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2129                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2130         }
2131
2132         spin_lock_irqsave(&np->lock, flags);
2133         empty_slots = nv_get_empty_tx_slots(np);
2134         if (unlikely(empty_slots <= entries)) {
2135                 netif_stop_queue(dev);
2136                 np->tx_stop = 1;
2137                 spin_unlock_irqrestore(&np->lock, flags);
2138                 return NETDEV_TX_BUSY;
2139         }
2140         spin_unlock_irqrestore(&np->lock, flags);
2141
2142         start_tx = put_tx = np->put_tx.orig;
2143
2144         /* setup the header buffer */
2145         do {
2146                 prev_tx = put_tx;
2147                 prev_tx_ctx = np->put_tx_ctx;
2148                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2149                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2150                                                 PCI_DMA_TODEVICE);
2151                 np->put_tx_ctx->dma_len = bcnt;
2152                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2153                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2154
2155                 tx_flags = np->tx_flags;
2156                 offset += bcnt;
2157                 size -= bcnt;
2158                 if (unlikely(put_tx++ == np->last_tx.orig))
2159                         put_tx = np->first_tx.orig;
2160                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2161                         np->put_tx_ctx = np->first_tx_ctx;
2162         } while (size);
2163
2164         /* setup the fragments */
2165         for (i = 0; i < fragments; i++) {
2166                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2167                 u32 size = frag->size;
2168                 offset = 0;
2169
2170                 do {
2171                         prev_tx = put_tx;
2172                         prev_tx_ctx = np->put_tx_ctx;
2173                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2174                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2175                                                            PCI_DMA_TODEVICE);
2176                         np->put_tx_ctx->dma_len = bcnt;
2177                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2178                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2179
2180                         offset += bcnt;
2181                         size -= bcnt;
2182                         if (unlikely(put_tx++ == np->last_tx.orig))
2183                                 put_tx = np->first_tx.orig;
2184                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2185                                 np->put_tx_ctx = np->first_tx_ctx;
2186                 } while (size);
2187         }
2188
2189         /* set last fragment flag  */
2190         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2191
2192         /* save skb in this slot's context area */
2193         prev_tx_ctx->skb = skb;
2194
2195         if (skb_is_gso(skb))
2196                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2197         else
2198                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2199                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2200
2201         spin_lock_irqsave(&np->lock, flags);
2202
2203         /* set tx flags */
2204         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2205         np->put_tx.orig = put_tx;
2206
2207         spin_unlock_irqrestore(&np->lock, flags);
2208
2209         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2210                 dev->name, entries, tx_flags_extra);
2211         {
2212                 int j;
2213                 for (j=0; j<64; j++) {
2214                         if ((j%16) == 0)
2215                                 dprintk("\n%03x:", j);
2216                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2217                 }
2218                 dprintk("\n");
2219         }
2220
2221         dev->trans_start = jiffies;
2222         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2223         return NETDEV_TX_OK;
2224 }
2225
2226 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2227 {
2228         struct fe_priv *np = netdev_priv(dev);
2229         u32 tx_flags = 0;
2230         u32 tx_flags_extra;
2231         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2232         unsigned int i;
2233         u32 offset = 0;
2234         u32 bcnt;
2235         u32 size = skb->len-skb->data_len;
2236         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2237         u32 empty_slots;
2238         struct ring_desc_ex* put_tx;
2239         struct ring_desc_ex* start_tx;
2240         struct ring_desc_ex* prev_tx;
2241         struct nv_skb_map* prev_tx_ctx;
2242         struct nv_skb_map* start_tx_ctx;
2243         unsigned long flags;
2244
2245         /* add fragments to entries count */
2246         for (i = 0; i < fragments; i++) {
2247                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2248                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2249         }
2250
2251         spin_lock_irqsave(&np->lock, flags);
2252         empty_slots = nv_get_empty_tx_slots(np);
2253         if (unlikely(empty_slots <= entries)) {
2254                 netif_stop_queue(dev);
2255                 np->tx_stop = 1;
2256                 spin_unlock_irqrestore(&np->lock, flags);
2257                 return NETDEV_TX_BUSY;
2258         }
2259         spin_unlock_irqrestore(&np->lock, flags);
2260
2261         start_tx = put_tx = np->put_tx.ex;
2262         start_tx_ctx = np->put_tx_ctx;
2263
2264         /* setup the header buffer */
2265         do {
2266                 prev_tx = put_tx;
2267                 prev_tx_ctx = np->put_tx_ctx;
2268                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2269                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2270                                                 PCI_DMA_TODEVICE);
2271                 np->put_tx_ctx->dma_len = bcnt;
2272                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2273                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2274                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2275
2276                 tx_flags = NV_TX2_VALID;
2277                 offset += bcnt;
2278                 size -= bcnt;
2279                 if (unlikely(put_tx++ == np->last_tx.ex))
2280                         put_tx = np->first_tx.ex;
2281                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2282                         np->put_tx_ctx = np->first_tx_ctx;
2283         } while (size);
2284
2285         /* setup the fragments */
2286         for (i = 0; i < fragments; i++) {
2287                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2288                 u32 size = frag->size;
2289                 offset = 0;
2290
2291                 do {
2292                         prev_tx = put_tx;
2293                         prev_tx_ctx = np->put_tx_ctx;
2294                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2295                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2296                                                            PCI_DMA_TODEVICE);
2297                         np->put_tx_ctx->dma_len = bcnt;
2298                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2299                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2300                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2301
2302                         offset += bcnt;
2303                         size -= bcnt;
2304                         if (unlikely(put_tx++ == np->last_tx.ex))
2305                                 put_tx = np->first_tx.ex;
2306                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2307                                 np->put_tx_ctx = np->first_tx_ctx;
2308                 } while (size);
2309         }
2310
2311         /* set last fragment flag  */
2312         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2313
2314         /* save skb in this slot's context area */
2315         prev_tx_ctx->skb = skb;
2316
2317         if (skb_is_gso(skb))
2318                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2319         else
2320                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2321                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2322
2323         /* vlan tag */
2324         if (likely(!np->vlangrp)) {
2325                 start_tx->txvlan = 0;
2326         } else {
2327                 if (vlan_tx_tag_present(skb))
2328                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2329                 else
2330                         start_tx->txvlan = 0;
2331         }
2332
2333         spin_lock_irqsave(&np->lock, flags);
2334
2335         if (np->tx_limit) {
2336                 /* Limit the number of outstanding tx. Setup all fragments, but
2337                  * do not set the VALID bit on the first descriptor. Save a pointer
2338                  * to that descriptor and also for next skb_map element.
2339                  */
2340
2341                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2342                         if (!np->tx_change_owner)
2343                                 np->tx_change_owner = start_tx_ctx;
2344
2345                         /* remove VALID bit */
2346                         tx_flags &= ~NV_TX2_VALID;
2347                         start_tx_ctx->first_tx_desc = start_tx;
2348                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2349                         np->tx_end_flip = np->put_tx_ctx;
2350                 } else {
2351                         np->tx_pkts_in_progress++;
2352                 }
2353         }
2354
2355         /* set tx flags */
2356         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2357         np->put_tx.ex = put_tx;
2358
2359         spin_unlock_irqrestore(&np->lock, flags);
2360
2361         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2362                 dev->name, entries, tx_flags_extra);
2363         {
2364                 int j;
2365                 for (j=0; j<64; j++) {
2366                         if ((j%16) == 0)
2367                                 dprintk("\n%03x:", j);
2368                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2369                 }
2370                 dprintk("\n");
2371         }
2372
2373         dev->trans_start = jiffies;
2374         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2375         return NETDEV_TX_OK;
2376 }
2377
2378 static inline void nv_tx_flip_ownership(struct net_device *dev)
2379 {
2380         struct fe_priv *np = netdev_priv(dev);
2381
2382         np->tx_pkts_in_progress--;
2383         if (np->tx_change_owner) {
2384                 np->tx_change_owner->first_tx_desc->flaglen |=
2385                         cpu_to_le32(NV_TX2_VALID);
2386                 np->tx_pkts_in_progress++;
2387
2388                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2389                 if (np->tx_change_owner == np->tx_end_flip)
2390                         np->tx_change_owner = NULL;
2391
2392                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2393         }
2394 }
2395
2396 /*
2397  * nv_tx_done: check for completed packets, release the skbs.
2398  *
2399  * Caller must own np->lock.
2400  */
2401 static int nv_tx_done(struct net_device *dev, int limit)
2402 {
2403         struct fe_priv *np = netdev_priv(dev);
2404         u32 flags;
2405         int tx_work = 0;
2406         struct ring_desc* orig_get_tx = np->get_tx.orig;
2407
2408         while ((np->get_tx.orig != np->put_tx.orig) &&
2409                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2410                (tx_work < limit)) {
2411
2412                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2413                                         dev->name, flags);
2414
2415                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2416                                np->get_tx_ctx->dma_len,
2417                                PCI_DMA_TODEVICE);
2418                 np->get_tx_ctx->dma = 0;
2419
2420                 if (np->desc_ver == DESC_VER_1) {
2421                         if (flags & NV_TX_LASTPACKET) {
2422                                 if (flags & NV_TX_ERROR) {
2423                                         if (flags & NV_TX_UNDERFLOW)
2424                                                 dev->stats.tx_fifo_errors++;
2425                                         if (flags & NV_TX_CARRIERLOST)
2426                                                 dev->stats.tx_carrier_errors++;
2427                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2428                                                 nv_legacybackoff_reseed(dev);
2429                                         dev->stats.tx_errors++;
2430                                 } else {
2431                                         dev->stats.tx_packets++;
2432                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2433                                 }
2434                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2435                                 np->get_tx_ctx->skb = NULL;
2436                                 tx_work++;
2437                         }
2438                 } else {
2439                         if (flags & NV_TX2_LASTPACKET) {
2440                                 if (flags & NV_TX2_ERROR) {
2441                                         if (flags & NV_TX2_UNDERFLOW)
2442                                                 dev->stats.tx_fifo_errors++;
2443                                         if (flags & NV_TX2_CARRIERLOST)
2444                                                 dev->stats.tx_carrier_errors++;
2445                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2446                                                 nv_legacybackoff_reseed(dev);
2447                                         dev->stats.tx_errors++;
2448                                 } else {
2449                                         dev->stats.tx_packets++;
2450                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2451                                 }
2452                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2453                                 np->get_tx_ctx->skb = NULL;
2454                                 tx_work++;
2455                         }
2456                 }
2457                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2458                         np->get_tx.orig = np->first_tx.orig;
2459                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2460                         np->get_tx_ctx = np->first_tx_ctx;
2461         }
2462         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2463                 np->tx_stop = 0;
2464                 netif_wake_queue(dev);
2465         }
2466         return tx_work;
2467 }
2468
2469 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2470 {
2471         struct fe_priv *np = netdev_priv(dev);
2472         u32 flags;
2473         int tx_work = 0;
2474         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2475
2476         while ((np->get_tx.ex != np->put_tx.ex) &&
2477                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2478                (tx_work < limit)) {
2479
2480                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2481                                         dev->name, flags);
2482
2483                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2484                                np->get_tx_ctx->dma_len,
2485                                PCI_DMA_TODEVICE);
2486                 np->get_tx_ctx->dma = 0;
2487
2488                 if (flags & NV_TX2_LASTPACKET) {
2489                         if (!(flags & NV_TX2_ERROR))
2490                                 dev->stats.tx_packets++;
2491                         else {
2492                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2493                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2494                                                 nv_gear_backoff_reseed(dev);
2495                                         else
2496                                                 nv_legacybackoff_reseed(dev);
2497                                 }
2498                         }
2499
2500                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2501                         np->get_tx_ctx->skb = NULL;
2502                         tx_work++;
2503
2504                         if (np->tx_limit) {
2505                                 nv_tx_flip_ownership(dev);
2506                         }
2507                 }
2508                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2509                         np->get_tx.ex = np->first_tx.ex;
2510                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2511                         np->get_tx_ctx = np->first_tx_ctx;
2512         }
2513         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2514                 np->tx_stop = 0;
2515                 netif_wake_queue(dev);
2516         }
2517         return tx_work;
2518 }
2519
2520 /*
2521  * nv_tx_timeout: dev->tx_timeout function
2522  * Called with netif_tx_lock held.
2523  */
2524 static void nv_tx_timeout(struct net_device *dev)
2525 {
2526         struct fe_priv *np = netdev_priv(dev);
2527         u8 __iomem *base = get_hwbase(dev);
2528         u32 status;
2529
2530         if (np->msi_flags & NV_MSI_X_ENABLED)
2531                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2532         else
2533                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2534
2535         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2536
2537         {
2538                 int i;
2539
2540                 printk(KERN_INFO "%s: Ring at %lx\n",
2541                        dev->name, (unsigned long)np->ring_addr);
2542                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2543                 for (i=0;i<=np->register_size;i+= 32) {
2544                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2545                                         i,
2546                                         readl(base + i + 0), readl(base + i + 4),
2547                                         readl(base + i + 8), readl(base + i + 12),
2548                                         readl(base + i + 16), readl(base + i + 20),
2549                                         readl(base + i + 24), readl(base + i + 28));
2550                 }
2551                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2552                 for (i=0;i<np->tx_ring_size;i+= 4) {
2553                         if (!nv_optimized(np)) {
2554                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2555                                        i,
2556                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2557                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2558                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2559                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2560                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2561                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2562                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2563                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2564                         } else {
2565                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2566                                        i,
2567                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2568                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2569                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2570                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2571                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2572                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2573                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2574                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2575                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2576                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2577                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2578                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2579                         }
2580                 }
2581         }
2582
2583         spin_lock_irq(&np->lock);
2584
2585         /* 1) stop tx engine */
2586         nv_stop_tx(dev);
2587
2588         /* 2) check that the packets were not sent already: */
2589         if (!nv_optimized(np))
2590                 nv_tx_done(dev, np->tx_ring_size);
2591         else
2592                 nv_tx_done_optimized(dev, np->tx_ring_size);
2593
2594         /* 3) if there are dead entries: clear everything */
2595         if (np->get_tx_ctx != np->put_tx_ctx) {
2596                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2597                 nv_drain_tx(dev);
2598                 nv_init_tx(dev);
2599                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2600         }
2601
2602         netif_wake_queue(dev);
2603
2604         /* 4) restart tx engine */
2605         nv_start_tx(dev);
2606         spin_unlock_irq(&np->lock);
2607 }
2608
2609 /*
2610  * Called when the nic notices a mismatch between the actual data len on the
2611  * wire and the len indicated in the 802 header
2612  */
2613 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2614 {
2615         int hdrlen;     /* length of the 802 header */
2616         int protolen;   /* length as stored in the proto field */
2617
2618         /* 1) calculate len according to header */
2619         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2620                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2621                 hdrlen = VLAN_HLEN;
2622         } else {
2623                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2624                 hdrlen = ETH_HLEN;
2625         }
2626         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2627                                 dev->name, datalen, protolen, hdrlen);
2628         if (protolen > ETH_DATA_LEN)
2629                 return datalen; /* Value in proto field not a len, no checks possible */
2630
2631         protolen += hdrlen;
2632         /* consistency checks: */
2633         if (datalen > ETH_ZLEN) {
2634                 if (datalen >= protolen) {
2635                         /* more data on wire than in 802 header, trim of
2636                          * additional data.
2637                          */
2638                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2639                                         dev->name, protolen);
2640                         return protolen;
2641                 } else {
2642                         /* less data on wire than mentioned in header.
2643                          * Discard the packet.
2644                          */
2645                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2646                                         dev->name);
2647                         return -1;
2648                 }
2649         } else {
2650                 /* short packet. Accept only if 802 values are also short */
2651                 if (protolen > ETH_ZLEN) {
2652                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2653                                         dev->name);
2654                         return -1;
2655                 }
2656                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2657                                 dev->name, datalen);
2658                 return datalen;
2659         }
2660 }
2661
2662 static int nv_rx_process(struct net_device *dev, int limit)
2663 {
2664         struct fe_priv *np = netdev_priv(dev);
2665         u32 flags;
2666         int rx_work = 0;
2667         struct sk_buff *skb;
2668         int len;
2669
2670         while((np->get_rx.orig != np->put_rx.orig) &&
2671               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2672                 (rx_work < limit)) {
2673
2674                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2675                                         dev->name, flags);
2676
2677                 /*
2678                  * the packet is for us - immediately tear down the pci mapping.
2679                  * TODO: check if a prefetch of the first cacheline improves
2680                  * the performance.
2681                  */
2682                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2683                                 np->get_rx_ctx->dma_len,
2684                                 PCI_DMA_FROMDEVICE);
2685                 skb = np->get_rx_ctx->skb;
2686                 np->get_rx_ctx->skb = NULL;
2687
2688                 {
2689                         int j;
2690                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2691                         for (j=0; j<64; j++) {
2692                                 if ((j%16) == 0)
2693                                         dprintk("\n%03x:", j);
2694                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2695                         }
2696                         dprintk("\n");
2697                 }
2698                 /* look at what we actually got: */
2699                 if (np->desc_ver == DESC_VER_1) {
2700                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2701                                 len = flags & LEN_MASK_V1;
2702                                 if (unlikely(flags & NV_RX_ERROR)) {
2703                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2704                                                 len = nv_getlen(dev, skb->data, len);
2705                                                 if (len < 0) {
2706                                                         dev->stats.rx_errors++;
2707                                                         dev_kfree_skb(skb);
2708                                                         goto next_pkt;
2709                                                 }
2710                                         }
2711                                         /* framing errors are soft errors */
2712                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2713                                                 if (flags & NV_RX_SUBSTRACT1) {
2714                                                         len--;
2715                                                 }
2716                                         }
2717                                         /* the rest are hard errors */
2718                                         else {
2719                                                 if (flags & NV_RX_MISSEDFRAME)
2720                                                         dev->stats.rx_missed_errors++;
2721                                                 if (flags & NV_RX_CRCERR)
2722                                                         dev->stats.rx_crc_errors++;
2723                                                 if (flags & NV_RX_OVERFLOW)
2724                                                         dev->stats.rx_over_errors++;
2725                                                 dev->stats.rx_errors++;
2726                                                 dev_kfree_skb(skb);
2727                                                 goto next_pkt;
2728                                         }
2729                                 }
2730                         } else {
2731                                 dev_kfree_skb(skb);
2732                                 goto next_pkt;
2733                         }
2734                 } else {
2735                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2736                                 len = flags & LEN_MASK_V2;
2737                                 if (unlikely(flags & NV_RX2_ERROR)) {
2738                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2739                                                 len = nv_getlen(dev, skb->data, len);
2740                                                 if (len < 0) {
2741                                                         dev->stats.rx_errors++;
2742                                                         dev_kfree_skb(skb);
2743                                                         goto next_pkt;
2744                                                 }
2745                                         }
2746                                         /* framing errors are soft errors */
2747                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2748                                                 if (flags & NV_RX2_SUBSTRACT1) {
2749                                                         len--;
2750                                                 }
2751                                         }
2752                                         /* the rest are hard errors */
2753                                         else {
2754                                                 if (flags & NV_RX2_CRCERR)
2755                                                         dev->stats.rx_crc_errors++;
2756                                                 if (flags & NV_RX2_OVERFLOW)
2757                                                         dev->stats.rx_over_errors++;
2758                                                 dev->stats.rx_errors++;
2759                                                 dev_kfree_skb(skb);
2760                                                 goto next_pkt;
2761                                         }
2762                                 }
2763                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2764                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2765                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2766                         } else {
2767                                 dev_kfree_skb(skb);
2768                                 goto next_pkt;
2769                         }
2770                 }
2771                 /* got a valid packet - forward it to the network core */
2772                 skb_put(skb, len);
2773                 skb->protocol = eth_type_trans(skb, dev);
2774                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2775                                         dev->name, len, skb->protocol);
2776 #ifdef CONFIG_FORCEDETH_NAPI
2777                 netif_receive_skb(skb);
2778 #else
2779                 netif_rx(skb);
2780 #endif
2781                 dev->stats.rx_packets++;
2782                 dev->stats.rx_bytes += len;
2783 next_pkt:
2784                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2785                         np->get_rx.orig = np->first_rx.orig;
2786                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2787                         np->get_rx_ctx = np->first_rx_ctx;
2788
2789                 rx_work++;
2790         }
2791
2792         return rx_work;
2793 }
2794
2795 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2796 {
2797         struct fe_priv *np = netdev_priv(dev);
2798         u32 flags;
2799         u32 vlanflags = 0;
2800         int rx_work = 0;
2801         struct sk_buff *skb;
2802         int len;
2803
2804         while((np->get_rx.ex != np->put_rx.ex) &&
2805               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2806               (rx_work < limit)) {
2807
2808                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2809                                         dev->name, flags);
2810
2811                 /*
2812                  * the packet is for us - immediately tear down the pci mapping.
2813                  * TODO: check if a prefetch of the first cacheline improves
2814                  * the performance.
2815                  */
2816                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2817                                 np->get_rx_ctx->dma_len,
2818                                 PCI_DMA_FROMDEVICE);
2819                 skb = np->get_rx_ctx->skb;
2820                 np->get_rx_ctx->skb = NULL;
2821
2822                 {
2823                         int j;
2824                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2825                         for (j=0; j<64; j++) {
2826                                 if ((j%16) == 0)
2827                                         dprintk("\n%03x:", j);
2828                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2829                         }
2830                         dprintk("\n");
2831                 }
2832                 /* look at what we actually got: */
2833                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2834                         len = flags & LEN_MASK_V2;
2835                         if (unlikely(flags & NV_RX2_ERROR)) {
2836                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2837                                         len = nv_getlen(dev, skb->data, len);
2838                                         if (len < 0) {
2839                                                 dev_kfree_skb(skb);
2840                                                 goto next_pkt;
2841                                         }
2842                                 }
2843                                 /* framing errors are soft errors */
2844                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2845                                         if (flags & NV_RX2_SUBSTRACT1) {
2846                                                 len--;
2847                                         }
2848                                 }
2849                                 /* the rest are hard errors */
2850                                 else {
2851                                         dev_kfree_skb(skb);
2852                                         goto next_pkt;
2853                                 }
2854                         }
2855
2856                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2857                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2858                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2859
2860                         /* got a valid packet - forward it to the network core */
2861                         skb_put(skb, len);
2862                         skb->protocol = eth_type_trans(skb, dev);
2863                         prefetch(skb->data);
2864
2865                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2866                                 dev->name, len, skb->protocol);
2867
2868                         if (likely(!np->vlangrp)) {
2869 #ifdef CONFIG_FORCEDETH_NAPI
2870                                 netif_receive_skb(skb);
2871 #else
2872                                 netif_rx(skb);
2873 #endif
2874                         } else {
2875                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2876                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2877 #ifdef CONFIG_FORCEDETH_NAPI
2878                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2879                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2880 #else
2881                                         vlan_hwaccel_rx(skb, np->vlangrp,
2882                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2883 #endif
2884                                 } else {
2885 #ifdef CONFIG_FORCEDETH_NAPI
2886                                         netif_receive_skb(skb);
2887 #else
2888                                         netif_rx(skb);
2889 #endif
2890                                 }
2891                         }
2892
2893                         dev->stats.rx_packets++;
2894                         dev->stats.rx_bytes += len;
2895                 } else {
2896                         dev_kfree_skb(skb);
2897                 }
2898 next_pkt:
2899                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2900                         np->get_rx.ex = np->first_rx.ex;
2901                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2902                         np->get_rx_ctx = np->first_rx_ctx;
2903
2904                 rx_work++;
2905         }
2906
2907         return rx_work;
2908 }
2909
2910 static void set_bufsize(struct net_device *dev)
2911 {
2912         struct fe_priv *np = netdev_priv(dev);
2913
2914         if (dev->mtu <= ETH_DATA_LEN)
2915                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2916         else
2917                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2918 }
2919
2920 /*
2921  * nv_change_mtu: dev->change_mtu function
2922  * Called with dev_base_lock held for read.
2923  */
2924 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2925 {
2926         struct fe_priv *np = netdev_priv(dev);
2927         int old_mtu;
2928
2929         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2930                 return -EINVAL;
2931
2932         old_mtu = dev->mtu;
2933         dev->mtu = new_mtu;
2934
2935         /* return early if the buffer sizes will not change */
2936         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2937                 return 0;
2938         if (old_mtu == new_mtu)
2939                 return 0;
2940
2941         /* synchronized against open : rtnl_lock() held by caller */
2942         if (netif_running(dev)) {
2943                 u8 __iomem *base = get_hwbase(dev);
2944                 /*
2945                  * It seems that the nic preloads valid ring entries into an
2946                  * internal buffer. The procedure for flushing everything is
2947                  * guessed, there is probably a simpler approach.
2948                  * Changing the MTU is a rare event, it shouldn't matter.
2949                  */
2950                 nv_disable_irq(dev);
2951                 nv_napi_disable(dev);
2952                 netif_tx_lock_bh(dev);
2953                 netif_addr_lock(dev);
2954                 spin_lock(&np->lock);
2955                 /* stop engines */
2956                 nv_stop_rxtx(dev);
2957                 nv_txrx_reset(dev);
2958                 /* drain rx queue */
2959                 nv_drain_rxtx(dev);
2960                 /* reinit driver view of the rx queue */
2961                 set_bufsize(dev);
2962                 if (nv_init_ring(dev)) {
2963                         if (!np->in_shutdown)
2964                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2965                 }
2966                 /* reinit nic view of the rx queue */
2967                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2968                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2969                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2970                         base + NvRegRingSizes);
2971                 pci_push(base);
2972                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2973                 pci_push(base);
2974
2975                 /* restart rx engine */
2976                 nv_start_rxtx(dev);
2977                 spin_unlock(&np->lock);
2978                 netif_addr_unlock(dev);
2979                 netif_tx_unlock_bh(dev);
2980                 nv_napi_enable(dev);
2981                 nv_enable_irq(dev);
2982         }
2983         return 0;
2984 }
2985
2986 static void nv_copy_mac_to_hw(struct net_device *dev)
2987 {
2988         u8 __iomem *base = get_hwbase(dev);
2989         u32 mac[2];
2990
2991         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2992                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2993         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2994
2995         writel(mac[0], base + NvRegMacAddrA);
2996         writel(mac[1], base + NvRegMacAddrB);
2997 }
2998
2999 /*
3000  * nv_set_mac_address: dev->set_mac_address function
3001  * Called with rtnl_lock() held.
3002  */
3003 static int nv_set_mac_address(struct net_device *dev, void *addr)
3004 {
3005         struct fe_priv *np = netdev_priv(dev);
3006         struct sockaddr *macaddr = (struct sockaddr*)addr;
3007
3008         if (!is_valid_ether_addr(macaddr->sa_data))
3009                 return -EADDRNOTAVAIL;
3010
3011         /* synchronized against open : rtnl_lock() held by caller */
3012         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3013
3014         if (netif_running(dev)) {
3015                 netif_tx_lock_bh(dev);
3016                 netif_addr_lock(dev);
3017                 spin_lock_irq(&np->lock);
3018
3019                 /* stop rx engine */
3020                 nv_stop_rx(dev);
3021
3022                 /* set mac address */
3023                 nv_copy_mac_to_hw(dev);
3024
3025                 /* restart rx engine */
3026                 nv_start_rx(dev);
3027                 spin_unlock_irq(&np->lock);
3028                 netif_addr_unlock(dev);
3029                 netif_tx_unlock_bh(dev);
3030         } else {
3031                 nv_copy_mac_to_hw(dev);
3032         }
3033         return 0;
3034 }
3035
3036 /*
3037  * nv_set_multicast: dev->set_multicast function
3038  * Called with netif_tx_lock held.
3039  */
3040 static void nv_set_multicast(struct net_device *dev)
3041 {
3042         struct fe_priv *np = netdev_priv(dev);
3043         u8 __iomem *base = get_hwbase(dev);
3044         u32 addr[2];
3045         u32 mask[2];
3046         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3047
3048         memset(addr, 0, sizeof(addr));
3049         memset(mask, 0, sizeof(mask));
3050
3051         if (dev->flags & IFF_PROMISC) {
3052                 pff |= NVREG_PFF_PROMISC;
3053         } else {
3054                 pff |= NVREG_PFF_MYADDR;
3055
3056                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3057                         u32 alwaysOff[2];
3058                         u32 alwaysOn[2];
3059
3060                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3061                         if (dev->flags & IFF_ALLMULTI) {
3062                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3063                         } else {
3064                                 struct dev_mc_list *walk;
3065
3066                                 walk = dev->mc_list;
3067                                 while (walk != NULL) {
3068                                         u32 a, b;
3069                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3070                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3071                                         alwaysOn[0] &= a;
3072                                         alwaysOff[0] &= ~a;
3073                                         alwaysOn[1] &= b;
3074                                         alwaysOff[1] &= ~b;
3075                                         walk = walk->next;
3076                                 }
3077                         }
3078                         addr[0] = alwaysOn[0];
3079                         addr[1] = alwaysOn[1];
3080                         mask[0] = alwaysOn[0] | alwaysOff[0];
3081                         mask[1] = alwaysOn[1] | alwaysOff[1];
3082                 } else {
3083                         mask[0] = NVREG_MCASTMASKA_NONE;
3084                         mask[1] = NVREG_MCASTMASKB_NONE;
3085                 }
3086         }
3087         addr[0] |= NVREG_MCASTADDRA_FORCE;
3088         pff |= NVREG_PFF_ALWAYS;
3089         spin_lock_irq(&np->lock);
3090         nv_stop_rx(dev);
3091         writel(addr[0], base + NvRegMulticastAddrA);
3092         writel(addr[1], base + NvRegMulticastAddrB);
3093         writel(mask[0], base + NvRegMulticastMaskA);
3094         writel(mask[1], base + NvRegMulticastMaskB);
3095         writel(pff, base + NvRegPacketFilterFlags);
3096         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3097                 dev->name);
3098         nv_start_rx(dev);
3099         spin_unlock_irq(&np->lock);
3100 }
3101
3102 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3103 {
3104         struct fe_priv *np = netdev_priv(dev);
3105         u8 __iomem *base = get_hwbase(dev);
3106
3107         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3108
3109         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3110                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3111                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3112                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3113                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3114                 } else {
3115                         writel(pff, base + NvRegPacketFilterFlags);
3116                 }
3117         }
3118         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3119                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3120                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3121                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3122                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3123                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3124                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3125                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3126                                 /* limit the number of tx pause frames to a default of 8 */
3127                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3128                         }
3129                         writel(pause_enable,  base + NvRegTxPauseFrame);
3130                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3131                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3132                 } else {
3133                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3134                         writel(regmisc, base + NvRegMisc1);
3135                 }
3136         }
3137 }
3138
3139 /**
3140  * nv_update_linkspeed: Setup the MAC according to the link partner
3141  * @dev: Network device to be configured
3142  *
3143  * The function queries the PHY and checks if there is a link partner.
3144  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3145  * set to 10 MBit HD.
3146  *
3147  * The function returns 0 if there is no link partner and 1 if there is
3148  * a good link partner.
3149  */
3150 static int nv_update_linkspeed(struct net_device *dev)
3151 {
3152         struct fe_priv *np = netdev_priv(dev);
3153         u8 __iomem *base = get_hwbase(dev);
3154         int adv = 0;
3155         int lpa = 0;
3156         int adv_lpa, adv_pause, lpa_pause;
3157         int newls = np->linkspeed;
3158         int newdup = np->duplex;
3159         int mii_status;
3160         int retval = 0;
3161         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3162         u32 txrxFlags = 0;
3163         u32 phy_exp;
3164
3165         /* BMSR_LSTATUS is latched, read it twice:
3166          * we want the current value.
3167          */
3168         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3169         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3170
3171         if (!(mii_status & BMSR_LSTATUS)) {
3172                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3173                                 dev->name);
3174                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3175                 newdup = 0;
3176                 retval = 0;
3177                 goto set_speed;
3178         }
3179
3180         if (np->autoneg == 0) {
3181                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3182                                 dev->name, np->fixed_mode);
3183                 if (np->fixed_mode & LPA_100FULL) {
3184                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3185                         newdup = 1;
3186                 } else if (np->fixed_mode & LPA_100HALF) {
3187                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3188                         newdup = 0;
3189                 } else if (np->fixed_mode & LPA_10FULL) {
3190                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3191                         newdup = 1;
3192                 } else {
3193                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3194                         newdup = 0;
3195                 }
3196                 retval = 1;
3197                 goto set_speed;
3198         }
3199         /* check auto negotiation is complete */
3200         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3201                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3202                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3203                 newdup = 0;
3204                 retval = 0;
3205                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3206                 goto set_speed;
3207         }
3208
3209         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3210         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3211         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3212                                 dev->name, adv, lpa);
3213
3214         retval = 1;
3215         if (np->gigabit == PHY_GIGABIT) {
3216                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3217                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3218
3219                 if ((control_1000 & ADVERTISE_1000FULL) &&
3220                         (status_1000 & LPA_1000FULL)) {
3221                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3222                                 dev->name);
3223                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3224                         newdup = 1;
3225                         goto set_speed;
3226                 }
3227         }
3228
3229         /* FIXME: handle parallel detection properly */
3230         adv_lpa = lpa & adv;
3231         if (adv_lpa & LPA_100FULL) {
3232                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3233                 newdup = 1;
3234         } else if (adv_lpa & LPA_100HALF) {
3235                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3236                 newdup = 0;
3237         } else if (adv_lpa & LPA_10FULL) {
3238                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3239                 newdup = 1;
3240         } else if (adv_lpa & LPA_10HALF) {
3241                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3242                 newdup = 0;
3243         } else {
3244                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3245                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3246                 newdup = 0;
3247         }
3248
3249 set_speed:
3250         if (np->duplex == newdup && np->linkspeed == newls)
3251                 return retval;
3252
3253         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3254                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3255
3256         np->duplex = newdup;
3257         np->linkspeed = newls;
3258
3259         /* The transmitter and receiver must be restarted for safe update */
3260         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3261                 txrxFlags |= NV_RESTART_TX;
3262                 nv_stop_tx(dev);
3263         }
3264         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3265                 txrxFlags |= NV_RESTART_RX;
3266                 nv_stop_rx(dev);
3267         }
3268
3269         if (np->gigabit == PHY_GIGABIT) {
3270                 phyreg = readl(base + NvRegSlotTime);
3271                 phyreg &= ~(0x3FF00);
3272                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3273                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3274                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3275                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3276                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3277                 writel(phyreg, base + NvRegSlotTime);
3278         }
3279
3280         phyreg = readl(base + NvRegPhyInterface);
3281         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3282         if (np->duplex == 0)
3283                 phyreg |= PHY_HALF;
3284         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3285                 phyreg |= PHY_100;
3286         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3287                 phyreg |= PHY_1000;
3288         writel(phyreg, base + NvRegPhyInterface);
3289
3290         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3291         if (phyreg & PHY_RGMII) {
3292                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3293                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3294                 } else {
3295                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3296                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3297                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3298                                 else
3299                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3300                         } else {
3301                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3302                         }
3303                 }
3304         } else {
3305                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3306                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3307                 else
3308                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3309         }
3310         writel(txreg, base + NvRegTxDeferral);
3311
3312         if (np->desc_ver == DESC_VER_1) {
3313                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3314         } else {
3315                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3316                         txreg = NVREG_TX_WM_DESC2_3_1000;
3317                 else
3318                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3319         }
3320         writel(txreg, base + NvRegTxWatermark);
3321
3322         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3323                 base + NvRegMisc1);
3324         pci_push(base);
3325         writel(np->linkspeed, base + NvRegLinkSpeed);
3326         pci_push(base);
3327
3328         pause_flags = 0;
3329         /* setup pause frame */
3330         if (np->duplex != 0) {
3331                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3332                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3333                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3334
3335                         switch (adv_pause) {
3336                         case ADVERTISE_PAUSE_CAP:
3337                                 if (lpa_pause & LPA_PAUSE_CAP) {
3338                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3339                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3340                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3341                                 }
3342                                 break;
3343                         case ADVERTISE_PAUSE_ASYM:
3344                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3345                                 {
3346                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3347                                 }
3348                                 break;
3349                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3350                                 if (lpa_pause & LPA_PAUSE_CAP)
3351                                 {
3352                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3353                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3354                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3355                                 }
3356                                 if (lpa_pause == LPA_PAUSE_ASYM)
3357                                 {
3358                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3359                                 }
3360                                 break;
3361                         }
3362                 } else {
3363                         pause_flags = np->pause_flags;
3364                 }
3365         }
3366         nv_update_pause(dev, pause_flags);
3367
3368         if (txrxFlags & NV_RESTART_TX)
3369                 nv_start_tx(dev);
3370         if (txrxFlags & NV_RESTART_RX)
3371                 nv_start_rx(dev);
3372
3373         return retval;
3374 }
3375
3376 static void nv_linkchange(struct net_device *dev)
3377 {
3378         if (nv_update_linkspeed(dev)) {
3379                 if (!netif_carrier_ok(dev)) {
3380                         netif_carrier_on(dev);
3381                         printk(KERN_INFO "%s: link up.\n", dev->name);
3382                         nv_start_rx(dev);
3383                 }
3384         } else {
3385                 if (netif_carrier_ok(dev)) {
3386                         netif_carrier_off(dev);
3387                         printk(KERN_INFO "%s: link down.\n", dev->name);
3388                         nv_stop_rx(dev);
3389                 }
3390         }
3391 }
3392
3393 static void nv_link_irq(struct net_device *dev)
3394 {
3395         u8 __iomem *base = get_hwbase(dev);
3396         u32 miistat;
3397
3398         miistat = readl(base + NvRegMIIStatus);
3399         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3400         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3401
3402         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3403                 nv_linkchange(dev);
3404         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3405 }
3406
3407 static void nv_msi_workaround(struct fe_priv *np)
3408 {
3409
3410         /* Need to toggle the msi irq mask within the ethernet device,
3411          * otherwise, future interrupts will not be detected.
3412          */
3413         if (np->msi_flags & NV_MSI_ENABLED) {
3414                 u8 __iomem *base = np->base;
3415
3416                 writel(0, base + NvRegMSIIrqMask);
3417                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3418         }
3419 }
3420
3421 static irqreturn_t nv_nic_irq(int foo, void *data)
3422 {
3423         struct net_device *dev = (struct net_device *) data;
3424         struct fe_priv *np = netdev_priv(dev);
3425         u8 __iomem *base = get_hwbase(dev);
3426
3427         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3428
3429         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3430                 np->events = readl(base + NvRegIrqStatus);
3431                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3432         } else {
3433                 np->events = readl(base + NvRegMSIXIrqStatus);
3434                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3435         }
3436         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3437         if (!(np->events & np->irqmask))
3438                 return IRQ_NONE;
3439
3440         nv_msi_workaround(np);
3441
3442 #ifdef CONFIG_FORCEDETH_NAPI
3443         spin_lock(&np->lock);
3444         napi_schedule(&np->napi);
3445
3446         /* Disable furthur irq's
3447            (msix not enabled with napi) */
3448         writel(0, base + NvRegIrqMask);
3449
3450         spin_unlock(&np->lock);
3451
3452         return IRQ_HANDLED;
3453 #else
3454         spin_lock(&np->lock);
3455         nv_tx_done(dev, np->tx_ring_size);
3456         spin_unlock(&np->lock);
3457
3458         if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3459                 if (unlikely(nv_alloc_rx(dev))) {
3460                         spin_lock(&np->lock);
3461                         if (!np->in_shutdown)
3462                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3463                         spin_unlock(&np->lock);
3464                 }
3465         }
3466
3467         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3468                 spin_lock(&np->lock);
3469                 nv_link_irq(dev);
3470                 spin_unlock(&np->lock);
3471         }
3472         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3473                 spin_lock(&np->lock);
3474                 nv_linkchange(dev);
3475                 spin_unlock(&np->lock);
3476                 np->link_timeout = jiffies + LINK_TIMEOUT;
3477         }
3478         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3479                 spin_lock(&np->lock);
3480                 /* disable interrupts on the nic */
3481                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3482                         writel(0, base + NvRegIrqMask);
3483                 else
3484                         writel(np->irqmask, base + NvRegIrqMask);
3485                 pci_push(base);
3486
3487                 if (!np->in_shutdown) {
3488                         np->nic_poll_irq = np->irqmask;
3489                         np->recover_error = 1;
3490                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3491                 }
3492                 spin_unlock(&np->lock);
3493         }
3494 #endif
3495         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3496
3497         return IRQ_HANDLED;
3498 }
3499
3500 /**
3501  * All _optimized functions are used to help increase performance
3502  * (reduce CPU and increase throughput). They use descripter version 3,
3503  * compiler directives, and reduce memory accesses.
3504  */
3505 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3506 {
3507         struct net_device *dev = (struct net_device *) data;
3508         struct fe_priv *np = netdev_priv(dev);
3509         u8 __iomem *base = get_hwbase(dev);
3510
3511         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3512
3513         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3514                 np->events = readl(base + NvRegIrqStatus);
3515                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3516         } else {
3517                 np->events = readl(base + NvRegMSIXIrqStatus);
3518                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3519         }
3520         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3521         if (!(np->events & np->irqmask))
3522                 return IRQ_NONE;
3523
3524         nv_msi_workaround(np);
3525
3526 #ifdef CONFIG_FORCEDETH_NAPI
3527         spin_lock(&np->lock);
3528         napi_schedule(&np->napi);
3529
3530         /* Disable furthur irq's
3531            (msix not enabled with napi) */
3532         writel(0, base + NvRegIrqMask);
3533
3534         spin_unlock(&np->lock);
3535
3536         return IRQ_HANDLED;
3537 #else
3538         spin_lock(&np->lock);
3539         nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3540         spin_unlock(&np->lock);
3541
3542         if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3543                 if (unlikely(nv_alloc_rx_optimized(dev))) {
3544                         spin_lock(&np->lock);
3545                         if (!np->in_shutdown)
3546                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3547                         spin_unlock(&np->lock);
3548                 }
3549         }
3550
3551         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3552                 spin_lock(&np->lock);
3553                 nv_link_irq(dev);
3554                 spin_unlock(&np->lock);
3555         }
3556         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3557                 spin_lock(&np->lock);
3558                 nv_linkchange(dev);
3559                 spin_unlock(&np->lock);
3560                 np->link_timeout = jiffies + LINK_TIMEOUT;
3561         }
3562         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3563                 spin_lock(&np->lock);
3564                 /* disable interrupts on the nic */
3565                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3566                         writel(0, base + NvRegIrqMask);
3567                 else
3568                         writel(np->irqmask, base + NvRegIrqMask);
3569                 pci_push(base);
3570
3571                 if (!np->in_shutdown) {
3572                         np->nic_poll_irq = np->irqmask;
3573                         np->recover_error = 1;
3574                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3575                 }
3576                 spin_unlock(&np->lock);
3577         }
3578
3579 #endif
3580         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3581
3582         return IRQ_HANDLED;
3583 }
3584
3585 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3586 {
3587         struct net_device *dev = (struct net_device *) data;
3588         struct fe_priv *np = netdev_priv(dev);
3589         u8 __iomem *base = get_hwbase(dev);
3590         u32 events;
3591         int i;
3592         unsigned long flags;
3593
3594         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3595
3596         for (i=0; ; i++) {
3597                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3598                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3599                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3600                 if (!(events & np->irqmask))
3601                         break;
3602
3603                 spin_lock_irqsave(&np->lock, flags);
3604                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3605                 spin_unlock_irqrestore(&np->lock, flags);
3606
3607                 if (unlikely(i > max_interrupt_work)) {
3608                         spin_lock_irqsave(&np->lock, flags);
3609                         /* disable interrupts on the nic */
3610                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3611                         pci_push(base);
3612
3613                         if (!np->in_shutdown) {
3614                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3615                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3616                         }
3617                         spin_unlock_irqrestore(&np->lock, flags);
3618                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3619                         break;
3620                 }
3621
3622         }
3623         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3624
3625         return IRQ_RETVAL(i);
3626 }
3627
3628 #ifdef CONFIG_FORCEDETH_NAPI
3629 static int nv_napi_poll(struct napi_struct *napi, int budget)
3630 {
3631         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3632         struct net_device *dev = np->dev;
3633         u8 __iomem *base = get_hwbase(dev);
3634         unsigned long flags;
3635         int pkts, retcode;
3636
3637         if (!nv_optimized(np)) {
3638                 spin_lock_irqsave(&np->lock, flags);
3639                 nv_tx_done(dev, np->tx_ring_size);
3640                 spin_unlock_irqrestore(&np->lock, flags);
3641
3642                 pkts = nv_rx_process(dev, budget);
3643                 retcode = nv_alloc_rx(dev);
3644         } else {
3645                 spin_lock_irqsave(&np->lock, flags);
3646                 nv_tx_done_optimized(dev, np->tx_ring_size);
3647                 spin_unlock_irqrestore(&np->lock, flags);
3648
3649                 pkts = nv_rx_process_optimized(dev, budget);
3650                 retcode = nv_alloc_rx_optimized(dev);
3651         }
3652
3653         if (retcode) {
3654                 spin_lock_irqsave(&np->lock, flags);
3655                 if (!np->in_shutdown)
3656                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3657                 spin_unlock_irqrestore(&np->lock, flags);
3658         }
3659
3660         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3661                 spin_lock_irqsave(&np->lock, flags);
3662                 nv_link_irq(dev);
3663                 spin_unlock_irqrestore(&np->lock, flags);
3664         }
3665         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3666                 spin_lock_irqsave(&np->lock, flags);
3667                 nv_linkchange(dev);
3668                 spin_unlock_irqrestore(&np->lock, flags);
3669                 np->link_timeout = jiffies + LINK_TIMEOUT;
3670         }
3671         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3672                 spin_lock_irqsave(&np->lock, flags);
3673                 if (!np->in_shutdown) {
3674                         np->nic_poll_irq = np->irqmask;
3675                         np->recover_error = 1;
3676                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3677                 }
3678                 spin_unlock_irqrestore(&np->lock, flags);
3679                 __napi_complete(napi);
3680                 return pkts;
3681         }
3682
3683         if (pkts < budget) {
3684                 /* re-enable interrupts
3685                    (msix not enabled in napi) */
3686                 spin_lock_irqsave(&np->lock, flags);
3687
3688                 __napi_complete(napi);
3689
3690                 writel(np->irqmask, base + NvRegIrqMask);
3691
3692                 spin_unlock_irqrestore(&np->lock, flags);
3693         }
3694         return pkts;
3695 }
3696 #endif
3697
3698 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3699 {
3700         struct net_device *dev = (struct net_device *) data;
3701         struct fe_priv *np = netdev_priv(dev);
3702         u8 __iomem *base = get_hwbase(dev);
3703         u32 events;
3704         int i;
3705         unsigned long flags;
3706
3707         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3708
3709         for (i=0; ; i++) {
3710                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3711                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3712                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3713                 if (!(events & np->irqmask))
3714                         break;
3715
3716                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3717                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3718                                 spin_lock_irqsave(&np->lock, flags);
3719                                 if (!np->in_shutdown)
3720                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3721                                 spin_unlock_irqrestore(&np->lock, flags);
3722                         }
3723                 }
3724
3725                 if (unlikely(i > max_interrupt_work)) {
3726                         spin_lock_irqsave(&np->lock, flags);
3727                         /* disable interrupts on the nic */
3728                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3729                         pci_push(base);
3730
3731                         if (!np->in_shutdown) {
3732                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3733                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3734                         }
3735                         spin_unlock_irqrestore(&np->lock, flags);
3736                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3737                         break;
3738                 }
3739         }
3740         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3741
3742         return IRQ_RETVAL(i);
3743 }
3744
3745 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3746 {
3747         struct net_device *dev = (struct net_device *) data;
3748         struct fe_priv *np = netdev_priv(dev);
3749         u8 __iomem *base = get_hwbase(dev);
3750         u32 events;
3751         int i;
3752         unsigned long flags;
3753
3754         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3755
3756         for (i=0; ; i++) {
3757                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3758                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3759                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3760                 if (!(events & np->irqmask))
3761                         break;
3762
3763                 /* check tx in case we reached max loop limit in tx isr */
3764                 spin_lock_irqsave(&np->lock, flags);
3765                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3766                 spin_unlock_irqrestore(&np->lock, flags);
3767
3768                 if (events & NVREG_IRQ_LINK) {
3769                         spin_lock_irqsave(&np->lock, flags);
3770                         nv_link_irq(dev);
3771                         spin_unlock_irqrestore(&np->lock, flags);
3772                 }
3773                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3774                         spin_lock_irqsave(&np->lock, flags);
3775                         nv_linkchange(dev);
3776                         spin_unlock_irqrestore(&np->lock, flags);
3777                         np->link_timeout = jiffies + LINK_TIMEOUT;
3778                 }
3779                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3780                         spin_lock_irq(&np->lock);
3781                         /* disable interrupts on the nic */
3782                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3783                         pci_push(base);
3784
3785                         if (!np->in_shutdown) {
3786                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3787                                 np->recover_error = 1;
3788                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3789                         }
3790                         spin_unlock_irq(&np->lock);
3791                         break;
3792                 }
3793                 if (unlikely(i > max_interrupt_work)) {
3794                         spin_lock_irqsave(&np->lock, flags);
3795                         /* disable interrupts on the nic */
3796                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3797                         pci_push(base);
3798
3799                         if (!np->in_shutdown) {
3800                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3801                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3802                         }
3803                         spin_unlock_irqrestore(&np->lock, flags);
3804                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3805                         break;
3806                 }
3807
3808         }
3809         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3810
3811         return IRQ_RETVAL(i);
3812 }
3813
3814 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3815 {
3816         struct net_device *dev = (struct net_device *) data;
3817         struct fe_priv *np = netdev_priv(dev);
3818         u8 __iomem *base = get_hwbase(dev);
3819         u32 events;
3820
3821         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3822
3823         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3824                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3825                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3826         } else {
3827                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3828                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3829         }
3830         pci_push(base);
3831         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3832         if (!(events & NVREG_IRQ_TIMER))
3833                 return IRQ_RETVAL(0);
3834
3835         nv_msi_workaround(np);
3836
3837         spin_lock(&np->lock);
3838         np->intr_test = 1;
3839         spin_unlock(&np->lock);
3840
3841         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3842
3843         return IRQ_RETVAL(1);
3844 }
3845
3846 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3847 {
3848         u8 __iomem *base = get_hwbase(dev);
3849         int i;
3850         u32 msixmap = 0;
3851
3852         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3853          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3854          * the remaining 8 interrupts.
3855          */
3856         for (i = 0; i < 8; i++) {
3857                 if ((irqmask >> i) & 0x1) {
3858                         msixmap |= vector << (i << 2);
3859                 }
3860         }
3861         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3862
3863         msixmap = 0;
3864         for (i = 0; i < 8; i++) {
3865                 if ((irqmask >> (i + 8)) & 0x1) {
3866                         msixmap |= vector << (i << 2);
3867                 }
3868         }
3869         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3870 }
3871
3872 static int nv_request_irq(struct net_device *dev, int intr_test)
3873 {
3874         struct fe_priv *np = get_nvpriv(dev);
3875         u8 __iomem *base = get_hwbase(dev);
3876         int ret = 1;
3877         int i;
3878         irqreturn_t (*handler)(int foo, void *data);
3879
3880         if (intr_test) {
3881                 handler = nv_nic_irq_test;
3882         } else {
3883                 if (nv_optimized(np))
3884                         handler = nv_nic_irq_optimized;
3885                 else
3886                         handler = nv_nic_irq;
3887         }
3888
3889         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3890                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3891                         np->msi_x_entry[i].entry = i;
3892                 }
3893                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3894                         np->msi_flags |= NV_MSI_X_ENABLED;
3895                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3896                                 /* Request irq for rx handling */
3897                                 sprintf(np->name_rx, "%s-rx", dev->name);
3898                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3899                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3900                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3901                                         pci_disable_msix(np->pci_dev);
3902                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3903                                         goto out_err;
3904                                 }
3905                                 /* Request irq for tx handling */
3906                                 sprintf(np->name_tx, "%s-tx", dev->name);
3907                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3908                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3909                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3910                                         pci_disable_msix(np->pci_dev);
3911                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3912                                         goto out_free_rx;
3913                                 }
3914                                 /* Request irq for link and timer handling */
3915                                 sprintf(np->name_other, "%s-other", dev->name);
3916                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3917                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3918                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3919                                         pci_disable_msix(np->pci_dev);
3920                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3921                                         goto out_free_tx;
3922                                 }
3923                                 /* map interrupts to their respective vector */
3924                                 writel(0, base + NvRegMSIXMap0);
3925                                 writel(0, base + NvRegMSIXMap1);
3926                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3927                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3928                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3929                         } else {
3930                                 /* Request irq for all interrupts */
3931                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3932                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3933                                         pci_disable_msix(np->pci_dev);
3934                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3935                                         goto out_err;
3936                                 }
3937
3938                                 /* map interrupts to vector 0 */
3939                                 writel(0, base + NvRegMSIXMap0);
3940                                 writel(0, base + NvRegMSIXMap1);
3941                         }
3942                 }
3943         }
3944         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3945                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3946                         np->msi_flags |= NV_MSI_ENABLED;
3947                         dev->irq = np->pci_dev->irq;
3948                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3949                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3950                                 pci_disable_msi(np->pci_dev);
3951                                 np->msi_flags &= ~NV_MSI_ENABLED;
3952                                 dev->irq = np->pci_dev->irq;
3953                                 goto out_err;
3954                         }
3955
3956                         /* map interrupts to vector 0 */
3957                         writel(0, base + NvRegMSIMap0);
3958                         writel(0, base + NvRegMSIMap1);
3959                         /* enable msi vector 0 */
3960                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3961                 }
3962         }
3963         if (ret != 0) {
3964                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3965                         goto out_err;
3966
3967         }
3968
3969         return 0;
3970 out_free_tx:
3971         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3972 out_free_rx:
3973         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3974 out_err:
3975         return 1;
3976 }
3977
3978 static void nv_free_irq(struct net_device *dev)
3979 {
3980         struct fe_priv *np = get_nvpriv(dev);
3981         int i;
3982
3983         if (np->msi_flags & NV_MSI_X_ENABLED) {
3984                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3985                         free_irq(np->msi_x_entry[i].vector, dev);
3986                 }
3987                 pci_disable_msix(np->pci_dev);
3988                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3989         } else {
3990                 free_irq(np->pci_dev->irq, dev);
3991                 if (np->msi_flags & NV_MSI_ENABLED) {
3992                         pci_disable_msi(np->pci_dev);
3993                         np->msi_flags &= ~NV_MSI_ENABLED;
3994                 }
3995         }
3996 }
3997
3998 static void nv_do_nic_poll(unsigned long data)
3999 {
4000         struct net_device *dev = (struct net_device *) data;
4001         struct fe_priv *np = netdev_priv(dev);
4002         u8 __iomem *base = get_hwbase(dev);
4003         u32 mask = 0;
4004
4005         /*
4006          * First disable irq(s) and then
4007          * reenable interrupts on the nic, we have to do this before calling
4008          * nv_nic_irq because that may decide to do otherwise
4009          */
4010
4011         if (!using_multi_irqs(dev)) {
4012                 if (np->msi_flags & NV_MSI_X_ENABLED)
4013                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4014                 else
4015                         disable_irq_lockdep(np->pci_dev->irq);
4016                 mask = np->irqmask;
4017         } else {
4018                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4019                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4020                         mask |= NVREG_IRQ_RX_ALL;
4021                 }
4022                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4023                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4024                         mask |= NVREG_IRQ_TX_ALL;
4025                 }
4026                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4027                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4028                         mask |= NVREG_IRQ_OTHER;
4029                 }
4030         }
4031         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4032
4033         if (np->recover_error) {
4034                 np->recover_error = 0;
4035                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4036                 if (netif_running(dev)) {
4037                         netif_tx_lock_bh(dev);
4038                         netif_addr_lock(dev);
4039                         spin_lock(&np->lock);
4040                         /* stop engines */
4041                         nv_stop_rxtx(dev);
4042                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4043                                 nv_mac_reset(dev);
4044                         nv_txrx_reset(dev);
4045                         /* drain rx queue */
4046                         nv_drain_rxtx(dev);
4047                         /* reinit driver view of the rx queue */
4048                         set_bufsize(dev);
4049                         if (nv_init_ring(dev)) {
4050                                 if (!np->in_shutdown)
4051                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4052                         }
4053                         /* reinit nic view of the rx queue */
4054                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4055                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4056                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4057                                 base + NvRegRingSizes);
4058                         pci_push(base);
4059                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4060                         pci_push(base);
4061                         /* clear interrupts */
4062                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4063                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4064                         else
4065                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4066
4067                         /* restart rx engine */
4068                         nv_start_rxtx(dev);
4069                         spin_unlock(&np->lock);
4070                         netif_addr_unlock(dev);
4071                         netif_tx_unlock_bh(dev);
4072                 }
4073         }
4074
4075         writel(mask, base + NvRegIrqMask);
4076         pci_push(base);
4077
4078         if (!using_multi_irqs(dev)) {
4079                 np->nic_poll_irq = 0;
4080                 if (nv_optimized(np))
4081                         nv_nic_irq_optimized(0, dev);
4082                 else
4083                         nv_nic_irq(0, dev);
4084                 if (np->msi_flags & NV_MSI_X_ENABLED)
4085                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4086                 else
4087                         enable_irq_lockdep(np->pci_dev->irq);
4088         } else {
4089                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4090                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4091                         nv_nic_irq_rx(0, dev);
4092                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4093                 }
4094                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4095                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4096                         nv_nic_irq_tx(0, dev);
4097                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4098                 }
4099                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4100                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4101                         nv_nic_irq_other(0, dev);
4102                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4103                 }
4104         }
4105
4106 }
4107
4108 #ifdef CONFIG_NET_POLL_CONTROLLER
4109 static void nv_poll_controller(struct net_device *dev)
4110 {
4111         nv_do_nic_poll((unsigned long) dev);
4112 }
4113 #endif
4114
4115 static void nv_do_stats_poll(unsigned long data)
4116 {
4117         struct net_device *dev = (struct net_device *) data;
4118         struct fe_priv *np = netdev_priv(dev);
4119
4120         nv_get_hw_stats(dev);
4121
4122         if (!np->in_shutdown)
4123                 mod_timer(&np->stats_poll,
4124                         round_jiffies(jiffies + STATS_INTERVAL));
4125 }
4126
4127 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4128 {
4129         struct fe_priv *np = netdev_priv(dev);
4130         strcpy(info->driver, DRV_NAME);
4131         strcpy(info->version, FORCEDETH_VERSION);
4132         strcpy(info->bus_info, pci_name(np->pci_dev));
4133 }
4134
4135 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4136 {
4137         struct fe_priv *np = netdev_priv(dev);
4138         wolinfo->supported = WAKE_MAGIC;
4139
4140         spin_lock_irq(&np->lock);
4141         if (np->wolenabled)
4142                 wolinfo->wolopts = WAKE_MAGIC;
4143         spin_unlock_irq(&np->lock);
4144 }
4145
4146 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4147 {
4148         struct fe_priv *np = netdev_priv(dev);
4149         u8 __iomem *base = get_hwbase(dev);
4150         u32 flags = 0;
4151
4152         if (wolinfo->wolopts == 0) {
4153                 np->wolenabled = 0;
4154         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4155                 np->wolenabled = 1;
4156                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4157         }
4158         if (netif_running(dev)) {
4159                 spin_lock_irq(&np->lock);
4160                 writel(flags, base + NvRegWakeUpFlags);
4161                 spin_unlock_irq(&np->lock);
4162         }
4163         return 0;
4164 }
4165
4166 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4167 {
4168         struct fe_priv *np = netdev_priv(dev);
4169         int adv;
4170
4171         spin_lock_irq(&np->lock);
4172         ecmd->port = PORT_MII;
4173         if (!netif_running(dev)) {
4174                 /* We do not track link speed / duplex setting if the
4175                  * interface is disabled. Force a link check */
4176                 if (nv_update_linkspeed(dev)) {
4177                         if (!netif_carrier_ok(dev))
4178                                 netif_carrier_on(dev);
4179                 } else {
4180                         if (netif_carrier_ok(dev))
4181                                 netif_carrier_off(dev);
4182                 }
4183         }
4184
4185         if (netif_carrier_ok(dev)) {
4186                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4187                 case NVREG_LINKSPEED_10:
4188                         ecmd->speed = SPEED_10;
4189                         break;
4190                 case NVREG_LINKSPEED_100:
4191                         ecmd->speed = SPEED_100;
4192                         break;
4193                 case NVREG_LINKSPEED_1000:
4194                         ecmd->speed = SPEED_1000;
4195                         break;
4196                 }
4197                 ecmd->duplex = DUPLEX_HALF;
4198                 if (np->duplex)
4199                         ecmd->duplex = DUPLEX_FULL;
4200         } else {
4201                 ecmd->speed = -1;
4202                 ecmd->duplex = -1;
4203         }
4204
4205         ecmd->autoneg = np->autoneg;
4206
4207         ecmd->advertising = ADVERTISED_MII;
4208         if (np->autoneg) {
4209                 ecmd->advertising |= ADVERTISED_Autoneg;
4210                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4211                 if (adv & ADVERTISE_10HALF)
4212                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4213                 if (adv & ADVERTISE_10FULL)
4214                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4215                 if (adv & ADVERTISE_100HALF)
4216                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4217                 if (adv & ADVERTISE_100FULL)
4218                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4219                 if (np->gigabit == PHY_GIGABIT) {
4220                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4221                         if (adv & ADVERTISE_1000FULL)
4222                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4223                 }
4224         }
4225         ecmd->supported = (SUPPORTED_Autoneg |
4226                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4227                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4228                 SUPPORTED_MII);
4229         if (np->gigabit == PHY_GIGABIT)
4230                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4231
4232         ecmd->phy_address = np->phyaddr;
4233         ecmd->transceiver = XCVR_EXTERNAL;
4234
4235         /* ignore maxtxpkt, maxrxpkt for now */
4236         spin_unlock_irq(&np->lock);
4237         return 0;
4238 }
4239
4240 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4241 {
4242         struct fe_priv *np = netdev_priv(dev);
4243
4244         if (ecmd->port != PORT_MII)
4245                 return -EINVAL;
4246         if (ecmd->transceiver != XCVR_EXTERNAL)
4247                 return -EINVAL;
4248         if (ecmd->phy_address != np->phyaddr) {
4249                 /* TODO: support switching between multiple phys. Should be
4250                  * trivial, but not enabled due to lack of test hardware. */
4251                 return -EINVAL;
4252         }
4253         if (ecmd->autoneg == AUTONEG_ENABLE) {
4254                 u32 mask;
4255
4256                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4257                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4258                 if (np->gigabit == PHY_GIGABIT)
4259                         mask |= ADVERTISED_1000baseT_Full;
4260
4261                 if ((ecmd->advertising & mask) == 0)
4262                         return -EINVAL;
4263
4264         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4265                 /* Note: autonegotiation disable, speed 1000 intentionally
4266                  * forbidden - noone should need that. */
4267
4268                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4269                         return -EINVAL;
4270                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4271                         return -EINVAL;
4272         } else {
4273                 return -EINVAL;
4274         }
4275
4276         netif_carrier_off(dev);
4277         if (netif_running(dev)) {
4278                 unsigned long flags;
4279
4280                 nv_disable_irq(dev);
4281                 netif_tx_lock_bh(dev);
4282                 netif_addr_lock(dev);
4283                 /* with plain spinlock lockdep complains */
4284                 spin_lock_irqsave(&np->lock, flags);
4285                 /* stop engines */
4286                 /* FIXME:
4287                  * this can take some time, and interrupts are disabled
4288                  * due to spin_lock_irqsave, but let's hope no daemon
4289                  * is going to change the settings very often...
4290                  * Worst case:
4291                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4292                  * + some minor delays, which is up to a second approximately
4293                  */
4294                 nv_stop_rxtx(dev);
4295                 spin_unlock_irqrestore(&np->lock, flags);
4296                 netif_addr_unlock(dev);
4297                 netif_tx_unlock_bh(dev);
4298         }
4299
4300         if (ecmd->autoneg == AUTONEG_ENABLE) {
4301                 int adv, bmcr;
4302
4303                 np->autoneg = 1;
4304
4305                 /* advertise only what has been requested */
4306                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4307                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4308                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4309                         adv |= ADVERTISE_10HALF;
4310                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4311                         adv |= ADVERTISE_10FULL;
4312                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4313                         adv |= ADVERTISE_100HALF;
4314                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4315                         adv |= ADVERTISE_100FULL;
4316                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4317                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4318                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4319                         adv |=  ADVERTISE_PAUSE_ASYM;
4320                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4321
4322                 if (np->gigabit == PHY_GIGABIT) {
4323                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4324                         adv &= ~ADVERTISE_1000FULL;
4325                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4326                                 adv |= ADVERTISE_1000FULL;
4327                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4328                 }
4329
4330                 if (netif_running(dev))
4331                         printk(KERN_INFO "%s: link down.\n", dev->name);
4332                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4333                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4334                         bmcr |= BMCR_ANENABLE;
4335                         /* reset the phy in order for settings to stick,
4336                          * and cause autoneg to start */
4337                         if (phy_reset(dev, bmcr)) {
4338                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4339                                 return -EINVAL;
4340                         }
4341                 } else {
4342                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4343                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4344                 }
4345         } else {
4346                 int adv, bmcr;
4347
4348                 np->autoneg = 0;
4349
4350                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4351                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4352                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4353                         adv |= ADVERTISE_10HALF;
4354                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4355                         adv |= ADVERTISE_10FULL;
4356                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4357                         adv |= ADVERTISE_100HALF;
4358                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4359                         adv |= ADVERTISE_100FULL;
4360                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4361                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4362                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4363                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4364                 }
4365                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4366                         adv |=  ADVERTISE_PAUSE_ASYM;
4367                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4368                 }
4369                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4370                 np->fixed_mode = adv;
4371
4372                 if (np->gigabit == PHY_GIGABIT) {
4373                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4374                         adv &= ~ADVERTISE_1000FULL;
4375                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4376                 }
4377
4378                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4379                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4380                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4381                         bmcr |= BMCR_FULLDPLX;
4382                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4383                         bmcr |= BMCR_SPEED100;
4384                 if (np->phy_oui == PHY_OUI_MARVELL) {
4385                         /* reset the phy in order for forced mode settings to stick */
4386                         if (phy_reset(dev, bmcr)) {
4387                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4388                                 return -EINVAL;
4389                         }
4390                 } else {
4391                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4392                         if (netif_running(dev)) {
4393                                 /* Wait a bit and then reconfigure the nic. */
4394                                 udelay(10);
4395                                 nv_linkchange(dev);
4396                         }
4397                 }
4398         }
4399
4400         if (netif_running(dev)) {
4401                 nv_start_rxtx(dev);
4402                 nv_enable_irq(dev);
4403         }
4404
4405         return 0;
4406 }
4407
4408 #define FORCEDETH_REGS_VER      1
4409
4410 static int nv_get_regs_len(struct net_device *dev)
4411 {
4412         struct fe_priv *np = netdev_priv(dev);
4413         return np->register_size;
4414 }
4415
4416 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4417 {
4418         struct fe_priv *np = netdev_priv(dev);
4419         u8 __iomem *base = get_hwbase(dev);
4420         u32 *rbuf = buf;
4421         int i;
4422
4423         regs->version = FORCEDETH_REGS_VER;
4424         spin_lock_irq(&np->lock);
4425         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4426                 rbuf[i] = readl(base + i*sizeof(u32));
4427         spin_unlock_irq(&np->lock);
4428 }
4429
4430 static int nv_nway_reset(struct net_device *dev)
4431 {
4432         struct fe_priv *np = netdev_priv(dev);
4433         int ret;
4434
4435         if (np->autoneg) {
4436                 int bmcr;
4437
4438                 netif_carrier_off(dev);
4439                 if (netif_running(dev)) {
4440                         nv_disable_irq(dev);
4441                         netif_tx_lock_bh(dev);
4442                         netif_addr_lock(dev);
4443                         spin_lock(&np->lock);
4444                         /* stop engines */
4445                         nv_stop_rxtx(dev);
4446                         spin_unlock(&np->lock);
4447                         netif_addr_unlock(dev);
4448                         netif_tx_unlock_bh(dev);
4449                         printk(KERN_INFO "%s: link down.\n", dev->name);
4450                 }
4451
4452                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4453                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4454                         bmcr |= BMCR_ANENABLE;
4455                         /* reset the phy in order for settings to stick*/
4456                         if (phy_reset(dev, bmcr)) {
4457                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4458                                 return -EINVAL;
4459                         }
4460                 } else {
4461                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4462                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4463                 }
4464
4465                 if (netif_running(dev)) {
4466                         nv_start_rxtx(dev);
4467                         nv_enable_irq(dev);
4468                 }
4469                 ret = 0;
4470         } else {
4471                 ret = -EINVAL;
4472         }
4473
4474         return ret;
4475 }
4476
4477 static int nv_set_tso(struct net_device *dev, u32 value)
4478 {
4479         struct fe_priv *np = netdev_priv(dev);
4480
4481         if ((np->driver_data & DEV_HAS_CHECKSUM))
4482                 return ethtool_op_set_tso(dev, value);
4483         else
4484                 return -EOPNOTSUPP;
4485 }
4486
4487 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4488 {
4489         struct fe_priv *np = netdev_priv(dev);
4490
4491         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4492         ring->rx_mini_max_pending = 0;
4493         ring->rx_jumbo_max_pending = 0;
4494         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4495
4496         ring->rx_pending = np->rx_ring_size;
4497         ring->rx_mini_pending = 0;
4498         ring->rx_jumbo_pending = 0;
4499         ring->tx_pending = np->tx_ring_size;
4500 }
4501
4502 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4503 {
4504         struct fe_priv *np = netdev_priv(dev);
4505         u8 __iomem *base = get_hwbase(dev);
4506         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4507         dma_addr_t ring_addr;
4508
4509         if (ring->rx_pending < RX_RING_MIN ||
4510             ring->tx_pending < TX_RING_MIN ||
4511             ring->rx_mini_pending != 0 ||
4512             ring->rx_jumbo_pending != 0 ||
4513             (np->desc_ver == DESC_VER_1 &&
4514              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4515               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4516             (np->desc_ver != DESC_VER_1 &&
4517              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4518               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4519                 return -EINVAL;
4520         }
4521
4522         /* allocate new rings */
4523         if (!nv_optimized(np)) {
4524                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4525                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4526                                             &ring_addr);
4527         } else {
4528                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4529                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4530                                             &ring_addr);
4531         }
4532         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4533         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4534         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4535                 /* fall back to old rings */
4536                 if (!nv_optimized(np)) {
4537                         if (rxtx_ring)
4538                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4539                                                     rxtx_ring, ring_addr);
4540                 } else {
4541                         if (rxtx_ring)
4542                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4543                                                     rxtx_ring, ring_addr);
4544                 }
4545                 if (rx_skbuff)
4546                         kfree(rx_skbuff);
4547                 if (tx_skbuff)
4548                         kfree(tx_skbuff);
4549                 goto exit;
4550         }
4551
4552         if (netif_running(dev)) {
4553                 nv_disable_irq(dev);
4554                 nv_napi_disable(dev);
4555                 netif_tx_lock_bh(dev);
4556                 netif_addr_lock(dev);
4557                 spin_lock(&np->lock);
4558                 /* stop engines */
4559                 nv_stop_rxtx(dev);
4560                 nv_txrx_reset(dev);
4561                 /* drain queues */
4562                 nv_drain_rxtx(dev);
4563                 /* delete queues */
4564                 free_rings(dev);
4565         }
4566
4567         /* set new values */
4568         np->rx_ring_size = ring->rx_pending;
4569         np->tx_ring_size = ring->tx_pending;
4570
4571         if (!nv_optimized(np)) {
4572                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4573                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4574         } else {
4575                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4576                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4577         }
4578         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4579         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4580         np->ring_addr = ring_addr;
4581
4582         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4583         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4584
4585         if (netif_running(dev)) {
4586                 /* reinit driver view of the queues */
4587                 set_bufsize(dev);
4588                 if (nv_init_ring(dev)) {
4589                         if (!np->in_shutdown)
4590                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4591                 }
4592
4593                 /* reinit nic view of the queues */
4594                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4595                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4596                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4597                         base + NvRegRingSizes);
4598                 pci_push(base);
4599                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4600                 pci_push(base);
4601
4602                 /* restart engines */
4603                 nv_start_rxtx(dev);
4604                 spin_unlock(&np->lock);
4605                 netif_addr_unlock(dev);
4606                 netif_tx_unlock_bh(dev);
4607                 nv_napi_enable(dev);
4608                 nv_enable_irq(dev);
4609         }
4610         return 0;
4611 exit:
4612         return -ENOMEM;
4613 }
4614
4615 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4616 {
4617         struct fe_priv *np = netdev_priv(dev);
4618
4619         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4620         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4621         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4622 }
4623
4624 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4625 {
4626         struct fe_priv *np = netdev_priv(dev);
4627         int adv, bmcr;
4628
4629         if ((!np->autoneg && np->duplex == 0) ||
4630             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4631                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4632                        dev->name);
4633                 return -EINVAL;
4634         }
4635         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4636                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4637                 return -EINVAL;
4638         }
4639
4640         netif_carrier_off(dev);
4641         if (netif_running(dev)) {
4642                 nv_disable_irq(dev);
4643                 netif_tx_lock_bh(dev);
4644                 netif_addr_lock(dev);
4645                 spin_lock(&np->lock);
4646                 /* stop engines */
4647                 nv_stop_rxtx(dev);
4648                 spin_unlock(&np->lock);
4649                 netif_addr_unlock(dev);
4650                 netif_tx_unlock_bh(dev);
4651         }
4652
4653         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4654         if (pause->rx_pause)
4655                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4656         if (pause->tx_pause)
4657                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4658
4659         if (np->autoneg && pause->autoneg) {
4660                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4661
4662                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4663                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4664                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4665                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4666                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4667                         adv |=  ADVERTISE_PAUSE_ASYM;
4668                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4669
4670                 if (netif_running(dev))
4671                         printk(KERN_INFO "%s: link down.\n", dev->name);
4672                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4673                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4674                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4675         } else {
4676                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4677                 if (pause->rx_pause)
4678                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4679                 if (pause->tx_pause)
4680                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4681
4682                 if (!netif_running(dev))
4683                         nv_update_linkspeed(dev);
4684                 else
4685                         nv_update_pause(dev, np->pause_flags);
4686         }
4687
4688         if (netif_running(dev)) {
4689                 nv_start_rxtx(dev);
4690                 nv_enable_irq(dev);
4691         }
4692         return 0;
4693 }
4694
4695 static u32 nv_get_rx_csum(struct net_device *dev)
4696 {
4697         struct fe_priv *np = netdev_priv(dev);
4698         return (np->rx_csum) != 0;
4699 }
4700
4701 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4702 {
4703         struct fe_priv *np = netdev_priv(dev);
4704         u8 __iomem *base = get_hwbase(dev);
4705         int retcode = 0;
4706
4707         if (np->driver_data & DEV_HAS_CHECKSUM) {
4708                 if (data) {
4709                         np->rx_csum = 1;
4710                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4711                 } else {
4712                         np->rx_csum = 0;
4713                         /* vlan is dependent on rx checksum offload */
4714                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4715                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4716                 }
4717                 if (netif_running(dev)) {
4718                         spin_lock_irq(&np->lock);
4719                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4720                         spin_unlock_irq(&np->lock);
4721                 }
4722         } else {
4723                 return -EINVAL;
4724         }
4725
4726         return retcode;
4727 }
4728
4729 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4730 {
4731         struct fe_priv *np = netdev_priv(dev);
4732
4733         if (np->driver_data & DEV_HAS_CHECKSUM)
4734                 return ethtool_op_set_tx_csum(dev, data);
4735         else
4736                 return -EOPNOTSUPP;
4737 }
4738
4739 static int nv_set_sg(struct net_device *dev, u32 data)
4740 {
4741         struct fe_priv *np = netdev_priv(dev);
4742
4743         if (np->driver_data & DEV_HAS_CHECKSUM)
4744                 return ethtool_op_set_sg(dev, data);
4745         else
4746                 return -EOPNOTSUPP;
4747 }
4748
4749 static int nv_get_sset_count(struct net_device *dev, int sset)
4750 {
4751         struct fe_priv *np = netdev_priv(dev);
4752
4753         switch (sset) {
4754         case ETH_SS_TEST:
4755                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4756                         return NV_TEST_COUNT_EXTENDED;
4757                 else
4758                         return NV_TEST_COUNT_BASE;
4759         case ETH_SS_STATS:
4760                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4761                         return NV_DEV_STATISTICS_V3_COUNT;
4762                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4763                         return NV_DEV_STATISTICS_V2_COUNT;
4764                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4765                         return NV_DEV_STATISTICS_V1_COUNT;
4766                 else
4767                         return 0;
4768         default:
4769                 return -EOPNOTSUPP;
4770         }
4771 }
4772
4773 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4774 {
4775         struct fe_priv *np = netdev_priv(dev);
4776
4777         /* update stats */
4778         nv_do_stats_poll((unsigned long)dev);
4779
4780         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4781 }
4782
4783 static int nv_link_test(struct net_device *dev)
4784 {
4785         struct fe_priv *np = netdev_priv(dev);
4786         int mii_status;
4787
4788         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4789         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4790
4791         /* check phy link status */
4792         if (!(mii_status & BMSR_LSTATUS))
4793                 return 0;
4794         else
4795                 return 1;
4796 }
4797
4798 static int nv_register_test(struct net_device *dev)
4799 {
4800         u8 __iomem *base = get_hwbase(dev);
4801         int i = 0;
4802         u32 orig_read, new_read;
4803
4804         do {
4805                 orig_read = readl(base + nv_registers_test[i].reg);
4806
4807                 /* xor with mask to toggle bits */
4808                 orig_read ^= nv_registers_test[i].mask;
4809
4810                 writel(orig_read, base + nv_registers_test[i].reg);
4811
4812                 new_read = readl(base + nv_registers_test[i].reg);
4813
4814                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4815                         return 0;
4816
4817                 /* restore original value */
4818                 orig_read ^= nv_registers_test[i].mask;
4819                 writel(orig_read, base + nv_registers_test[i].reg);
4820
4821         } while (nv_registers_test[++i].reg != 0);
4822
4823         return 1;
4824 }
4825
4826 static int nv_interrupt_test(struct net_device *dev)
4827 {
4828         struct fe_priv *np = netdev_priv(dev);
4829         u8 __iomem *base = get_hwbase(dev);
4830         int ret = 1;
4831         int testcnt;
4832         u32 save_msi_flags, save_poll_interval = 0;
4833
4834         if (netif_running(dev)) {
4835                 /* free current irq */
4836                 nv_free_irq(dev);
4837                 save_poll_interval = readl(base+NvRegPollingInterval);
4838         }
4839
4840         /* flag to test interrupt handler */
4841         np->intr_test = 0;
4842
4843         /* setup test irq */
4844         save_msi_flags = np->msi_flags;
4845         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4846         np->msi_flags |= 0x001; /* setup 1 vector */
4847         if (nv_request_irq(dev, 1))
4848                 return 0;
4849
4850         /* setup timer interrupt */
4851         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4852         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4853
4854         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4855
4856         /* wait for at least one interrupt */
4857         msleep(100);
4858
4859         spin_lock_irq(&np->lock);
4860
4861         /* flag should be set within ISR */
4862         testcnt = np->intr_test;
4863         if (!testcnt)
4864                 ret = 2;
4865
4866         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4867         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4868                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4869         else
4870                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4871
4872         spin_unlock_irq(&np->lock);
4873
4874         nv_free_irq(dev);
4875
4876         np->msi_flags = save_msi_flags;
4877
4878         if (netif_running(dev)) {
4879                 writel(save_poll_interval, base + NvRegPollingInterval);
4880                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4881                 /* restore original irq */
4882                 if (nv_request_irq(dev, 0))
4883                         return 0;
4884         }
4885
4886         return ret;
4887 }
4888
4889 static int nv_loopback_test(struct net_device *dev)
4890 {
4891         struct fe_priv *np = netdev_priv(dev);
4892         u8 __iomem *base = get_hwbase(dev);
4893         struct sk_buff *tx_skb, *rx_skb;
4894         dma_addr_t test_dma_addr;
4895         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4896         u32 flags;
4897         int len, i, pkt_len;
4898         u8 *pkt_data;
4899         u32 filter_flags = 0;
4900         u32 misc1_flags = 0;
4901         int ret = 1;
4902
4903         if (netif_running(dev)) {
4904                 nv_disable_irq(dev);
4905                 filter_flags = readl(base + NvRegPacketFilterFlags);
4906                 misc1_flags = readl(base + NvRegMisc1);
4907         } else {
4908                 nv_txrx_reset(dev);
4909         }
4910
4911         /* reinit driver view of the rx queue */
4912         set_bufsize(dev);
4913         nv_init_ring(dev);
4914
4915         /* setup hardware for loopback */
4916         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4917         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4918
4919         /* reinit nic view of the rx queue */
4920         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4921         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4922         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4923                 base + NvRegRingSizes);
4924         pci_push(base);
4925
4926         /* restart rx engine */
4927         nv_start_rxtx(dev);
4928
4929         /* setup packet for tx */
4930         pkt_len = ETH_DATA_LEN;
4931         tx_skb = dev_alloc_skb(pkt_len);
4932         if (!tx_skb) {
4933                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4934                          " of %s\n", dev->name);
4935                 ret = 0;
4936                 goto out;
4937         }
4938         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4939                                        skb_tailroom(tx_skb),
4940                                        PCI_DMA_FROMDEVICE);
4941         pkt_data = skb_put(tx_skb, pkt_len);
4942         for (i = 0; i < pkt_len; i++)
4943                 pkt_data[i] = (u8)(i & 0xff);
4944
4945         if (!nv_optimized(np)) {
4946                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4947                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4948         } else {
4949                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4950                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4951                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4952         }
4953         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4954         pci_push(get_hwbase(dev));
4955
4956         msleep(500);
4957
4958         /* check for rx of the packet */
4959         if (!nv_optimized(np)) {
4960                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4961                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4962
4963         } else {
4964                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4965                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4966         }
4967
4968         if (flags & NV_RX_AVAIL) {
4969                 ret = 0;
4970         } else if (np->desc_ver == DESC_VER_1) {
4971                 if (flags & NV_RX_ERROR)
4972                         ret = 0;
4973         } else {
4974                 if (flags & NV_RX2_ERROR) {
4975                         ret = 0;
4976                 }
4977         }
4978
4979         if (ret) {
4980                 if (len != pkt_len) {
4981                         ret = 0;
4982                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4983                                 dev->name, len, pkt_len);
4984                 } else {
4985                         rx_skb = np->rx_skb[0].skb;
4986                         for (i = 0; i < pkt_len; i++) {
4987                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4988                                         ret = 0;
4989                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4990                                                 dev->name, i);
4991                                         break;
4992                                 }
4993                         }
4994                 }
4995         } else {
4996                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4997         }
4998
4999         pci_unmap_page(np->pci_dev, test_dma_addr,
5000                        (skb_end_pointer(tx_skb) - tx_skb->data),
5001                        PCI_DMA_TODEVICE);
5002         dev_kfree_skb_any(tx_skb);
5003  out:
5004         /* stop engines */
5005         nv_stop_rxtx(dev);
5006         nv_txrx_reset(dev);
5007         /* drain rx queue */
5008         nv_drain_rxtx(dev);
5009
5010         if (netif_running(dev)) {
5011                 writel(misc1_flags, base + NvRegMisc1);
5012                 writel(filter_flags, base + NvRegPacketFilterFlags);
5013                 nv_enable_irq(dev);
5014         }
5015
5016         return ret;
5017 }
5018
5019 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5020 {
5021         struct fe_priv *np = netdev_priv(dev);
5022         u8 __iomem *base = get_hwbase(dev);
5023         int result;
5024         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5025
5026         if (!nv_link_test(dev)) {
5027                 test->flags |= ETH_TEST_FL_FAILED;
5028                 buffer[0] = 1;
5029         }
5030
5031         if (test->flags & ETH_TEST_FL_OFFLINE) {
5032                 if (netif_running(dev)) {
5033                         netif_stop_queue(dev);
5034                         nv_napi_disable(dev);
5035                         netif_tx_lock_bh(dev);
5036                         netif_addr_lock(dev);
5037                         spin_lock_irq(&np->lock);
5038                         nv_disable_hw_interrupts(dev, np->irqmask);
5039                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5040                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5041                         } else {
5042                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5043                         }
5044                         /* stop engines */
5045                         nv_stop_rxtx(dev);
5046                         nv_txrx_reset(dev);
5047                         /* drain rx queue */
5048                         nv_drain_rxtx(dev);
5049                         spin_unlock_irq(&np->lock);
5050                         netif_addr_unlock(dev);
5051                         netif_tx_unlock_bh(dev);
5052                 }
5053
5054                 if (!nv_register_test(dev)) {
5055                         test->flags |= ETH_TEST_FL_FAILED;
5056                         buffer[1] = 1;
5057                 }
5058
5059                 result = nv_interrupt_test(dev);
5060                 if (result != 1) {
5061                         test->flags |= ETH_TEST_FL_FAILED;
5062                         buffer[2] = 1;
5063                 }
5064                 if (result == 0) {
5065                         /* bail out */
5066                         return;
5067                 }
5068
5069                 if (!nv_loopback_test(dev)) {
5070                         test->flags |= ETH_TEST_FL_FAILED;
5071                         buffer[3] = 1;
5072                 }
5073
5074                 if (netif_running(dev)) {
5075                         /* reinit driver view of the rx queue */
5076                         set_bufsize(dev);
5077                         if (nv_init_ring(dev)) {
5078                                 if (!np->in_shutdown)
5079                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5080                         }
5081                         /* reinit nic view of the rx queue */
5082                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5083                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5084                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5085                                 base + NvRegRingSizes);
5086                         pci_push(base);
5087                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5088                         pci_push(base);
5089                         /* restart rx engine */
5090                         nv_start_rxtx(dev);
5091                         netif_start_queue(dev);
5092                         nv_napi_enable(dev);
5093                         nv_enable_hw_interrupts(dev, np->irqmask);
5094                 }
5095         }
5096 }
5097
5098 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5099 {
5100         switch (stringset) {
5101         case ETH_SS_STATS:
5102                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5103                 break;
5104         case ETH_SS_TEST:
5105                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5106                 break;
5107         }
5108 }
5109
5110 static const struct ethtool_ops ops = {
5111         .get_drvinfo = nv_get_drvinfo,
5112         .get_link = ethtool_op_get_link,
5113         .get_wol = nv_get_wol,
5114         .set_wol = nv_set_wol,
5115         .get_settings = nv_get_settings,
5116         .set_settings = nv_set_settings,
5117         .get_regs_len = nv_get_regs_len,
5118         .get_regs = nv_get_regs,
5119         .nway_reset = nv_nway_reset,
5120         .set_tso = nv_set_tso,
5121         .get_ringparam = nv_get_ringparam,
5122         .set_ringparam = nv_set_ringparam,
5123         .get_pauseparam = nv_get_pauseparam,
5124         .set_pauseparam = nv_set_pauseparam,
5125         .get_rx_csum = nv_get_rx_csum,
5126         .set_rx_csum = nv_set_rx_csum,
5127         .set_tx_csum = nv_set_tx_csum,
5128         .set_sg = nv_set_sg,
5129         .get_strings = nv_get_strings,
5130         .get_ethtool_stats = nv_get_ethtool_stats,
5131         .get_sset_count = nv_get_sset_count,
5132         .self_test = nv_self_test,
5133 };
5134
5135 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5136 {
5137         struct fe_priv *np = get_nvpriv(dev);
5138
5139         spin_lock_irq(&np->lock);
5140
5141         /* save vlan group */
5142         np->vlangrp = grp;
5143
5144         if (grp) {
5145                 /* enable vlan on MAC */
5146                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5147         } else {
5148                 /* disable vlan on MAC */
5149                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5150                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5151         }
5152
5153         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5154
5155         spin_unlock_irq(&np->lock);
5156 }
5157
5158 /* The mgmt unit and driver use a semaphore to access the phy during init */
5159 static int nv_mgmt_acquire_sema(struct net_device *dev)
5160 {
5161         struct fe_priv *np = netdev_priv(dev);
5162         u8 __iomem *base = get_hwbase(dev);
5163         int i;
5164         u32 tx_ctrl, mgmt_sema;
5165
5166         for (i = 0; i < 10; i++) {
5167                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5168                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5169                         break;
5170                 msleep(500);
5171         }
5172
5173         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5174                 return 0;
5175
5176         for (i = 0; i < 2; i++) {
5177                 tx_ctrl = readl(base + NvRegTransmitterControl);
5178                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5179                 writel(tx_ctrl, base + NvRegTransmitterControl);
5180
5181                 /* verify that semaphore was acquired */
5182                 tx_ctrl = readl(base + NvRegTransmitterControl);
5183                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5184                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5185                         np->mgmt_sema = 1;
5186                         return 1;
5187                 }
5188                 else
5189                         udelay(50);
5190         }
5191
5192         return 0;
5193 }
5194
5195 static void nv_mgmt_release_sema(struct net_device *dev)
5196 {
5197         struct fe_priv *np = netdev_priv(dev);
5198         u8 __iomem *base = get_hwbase(dev);
5199         u32 tx_ctrl;
5200
5201         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5202                 if (np->mgmt_sema) {
5203                         tx_ctrl = readl(base + NvRegTransmitterControl);
5204                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5205                         writel(tx_ctrl, base + NvRegTransmitterControl);
5206                 }
5207         }
5208 }
5209
5210
5211 static int nv_mgmt_get_version(struct net_device *dev)
5212 {
5213         struct fe_priv *np = netdev_priv(dev);
5214         u8 __iomem *base = get_hwbase(dev);
5215         u32 data_ready = readl(base + NvRegTransmitterControl);
5216         u32 data_ready2 = 0;
5217         unsigned long start;
5218         int ready = 0;
5219
5220         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5221         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5222         start = jiffies;
5223         while (time_before(jiffies, start + 5*HZ)) {
5224                 data_ready2 = readl(base + NvRegTransmitterControl);
5225                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5226                         ready = 1;
5227                         break;
5228                 }
5229                 schedule_timeout_uninterruptible(1);
5230         }
5231
5232         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5233                 return 0;
5234
5235         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5236
5237         return 1;
5238 }
5239
5240 static int nv_open(struct net_device *dev)
5241 {
5242         struct fe_priv *np = netdev_priv(dev);
5243         u8 __iomem *base = get_hwbase(dev);
5244         int ret = 1;
5245         int oom, i;
5246         u32 low;
5247
5248         dprintk(KERN_DEBUG "nv_open: begin\n");
5249
5250         /* power up phy */
5251         mii_rw(dev, np->phyaddr, MII_BMCR,
5252                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5253
5254         /* erase previous misconfiguration */
5255         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5256                 nv_mac_reset(dev);
5257         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5258         writel(0, base + NvRegMulticastAddrB);
5259         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5260         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5261         writel(0, base + NvRegPacketFilterFlags);
5262
5263         writel(0, base + NvRegTransmitterControl);
5264         writel(0, base + NvRegReceiverControl);
5265
5266         writel(0, base + NvRegAdapterControl);
5267
5268         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5269                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5270
5271         /* initialize descriptor rings */
5272         set_bufsize(dev);
5273         oom = nv_init_ring(dev);
5274
5275         writel(0, base + NvRegLinkSpeed);
5276         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5277         nv_txrx_reset(dev);
5278         writel(0, base + NvRegUnknownSetupReg6);
5279
5280         np->in_shutdown = 0;
5281
5282         /* give hw rings */
5283         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5284         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5285                 base + NvRegRingSizes);
5286
5287         writel(np->linkspeed, base + NvRegLinkSpeed);
5288         if (np->desc_ver == DESC_VER_1)
5289                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5290         else
5291                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5292         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5293         writel(np->vlanctl_bits, base + NvRegVlanControl);
5294         pci_push(base);
5295         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5296         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5297                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5298                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5299
5300         writel(0, base + NvRegMIIMask);
5301         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5302         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5303
5304         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5305         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5306         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5307         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5308
5309         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5310
5311         get_random_bytes(&low, sizeof(low));
5312         low &= NVREG_SLOTTIME_MASK;
5313         if (np->desc_ver == DESC_VER_1) {
5314                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5315         } else {
5316                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5317                         /* setup legacy backoff */
5318                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5319                 } else {
5320                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5321                         nv_gear_backoff_reseed(dev);
5322                 }
5323         }
5324         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5325         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5326         if (poll_interval == -1) {
5327                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5328                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5329                 else
5330                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5331         }
5332         else
5333                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5334         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5335         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5336                         base + NvRegAdapterControl);
5337         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5338         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5339         if (np->wolenabled)
5340                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5341
5342         i = readl(base + NvRegPowerState);
5343         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5344                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5345
5346         pci_push(base);
5347         udelay(10);
5348         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5349
5350         nv_disable_hw_interrupts(dev, np->irqmask);
5351         pci_push(base);
5352         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5353         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5354         pci_push(base);
5355
5356         if (nv_request_irq(dev, 0)) {
5357                 goto out_drain;
5358         }
5359
5360         /* ask for interrupts */
5361         nv_enable_hw_interrupts(dev, np->irqmask);
5362
5363         spin_lock_irq(&np->lock);
5364         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5365         writel(0, base + NvRegMulticastAddrB);
5366         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5367         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5368         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5369         /* One manual link speed update: Interrupts are enabled, future link
5370          * speed changes cause interrupts and are handled by nv_link_irq().
5371          */
5372         {
5373                 u32 miistat;
5374                 miistat = readl(base + NvRegMIIStatus);
5375                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5376                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5377         }
5378         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5379          * to init hw */
5380         np->linkspeed = 0;
5381         ret = nv_update_linkspeed(dev);
5382         nv_start_rxtx(dev);
5383         netif_start_queue(dev);
5384         nv_napi_enable(dev);
5385
5386         if (ret) {
5387                 netif_carrier_on(dev);
5388         } else {
5389                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5390                 netif_carrier_off(dev);
5391         }
5392         if (oom)
5393                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5394
5395         /* start statistics timer */
5396         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5397                 mod_timer(&np->stats_poll,
5398                         round_jiffies(jiffies + STATS_INTERVAL));
5399
5400         spin_unlock_irq(&np->lock);
5401
5402         return 0;
5403 out_drain:
5404         nv_drain_rxtx(dev);
5405         return ret;
5406 }
5407
5408 static int nv_close(struct net_device *dev)
5409 {
5410         struct fe_priv *np = netdev_priv(dev);
5411         u8 __iomem *base;
5412
5413         spin_lock_irq(&np->lock);
5414         np->in_shutdown = 1;
5415         spin_unlock_irq(&np->lock);
5416         nv_napi_disable(dev);
5417         synchronize_irq(np->pci_dev->irq);
5418
5419         del_timer_sync(&np->oom_kick);
5420         del_timer_sync(&np->nic_poll);
5421         del_timer_sync(&np->stats_poll);
5422
5423         netif_stop_queue(dev);
5424         spin_lock_irq(&np->lock);
5425         nv_stop_rxtx(dev);
5426         nv_txrx_reset(dev);
5427
5428         /* disable interrupts on the nic or we will lock up */
5429         base = get_hwbase(dev);
5430         nv_disable_hw_interrupts(dev, np->irqmask);
5431         pci_push(base);
5432         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5433
5434         spin_unlock_irq(&np->lock);
5435
5436         nv_free_irq(dev);
5437
5438         nv_drain_rxtx(dev);
5439
5440         if (np->wolenabled) {
5441                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5442                 nv_start_rx(dev);
5443         } else {
5444                 /* power down phy */
5445                 mii_rw(dev, np->phyaddr, MII_BMCR,
5446                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5447         }
5448
5449         /* FIXME: power down nic */
5450
5451         return 0;
5452 }
5453
5454 static const struct net_device_ops nv_netdev_ops = {
5455         .ndo_open               = nv_open,
5456         .ndo_stop               = nv_close,
5457         .ndo_get_stats          = nv_get_stats,
5458         .ndo_start_xmit         = nv_start_xmit,
5459         .ndo_tx_timeout         = nv_tx_timeout,
5460         .ndo_change_mtu         = nv_change_mtu,
5461         .ndo_validate_addr      = eth_validate_addr,
5462         .ndo_set_mac_address    = nv_set_mac_address,
5463         .ndo_set_multicast_list = nv_set_multicast,
5464         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5465 #ifdef CONFIG_NET_POLL_CONTROLLER
5466         .ndo_poll_controller    = nv_poll_controller,
5467 #endif
5468 };
5469
5470 static const struct net_device_ops nv_netdev_ops_optimized = {
5471         .ndo_open               = nv_open,
5472         .ndo_stop               = nv_close,
5473         .ndo_get_stats          = nv_get_stats,
5474         .ndo_start_xmit         = nv_start_xmit_optimized,
5475         .ndo_tx_timeout         = nv_tx_timeout,
5476         .ndo_change_mtu         = nv_change_mtu,
5477         .ndo_validate_addr      = eth_validate_addr,
5478         .ndo_set_mac_address    = nv_set_mac_address,
5479         .ndo_set_multicast_list = nv_set_multicast,
5480         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5481 #ifdef CONFIG_NET_POLL_CONTROLLER
5482         .ndo_poll_controller    = nv_poll_controller,
5483 #endif
5484 };
5485
5486 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5487 {
5488         struct net_device *dev;
5489         struct fe_priv *np;
5490         unsigned long addr;
5491         u8 __iomem *base;
5492         int err, i;
5493         u32 powerstate, txreg;
5494         u32 phystate_orig = 0, phystate;
5495         int phyinitialized = 0;
5496         static int printed_version;
5497
5498         if (!printed_version++)
5499                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5500                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5501
5502         dev = alloc_etherdev(sizeof(struct fe_priv));
5503         err = -ENOMEM;
5504         if (!dev)
5505                 goto out;
5506
5507         np = netdev_priv(dev);
5508         np->dev = dev;
5509         np->pci_dev = pci_dev;
5510         spin_lock_init(&np->lock);
5511         SET_NETDEV_DEV(dev, &pci_dev->dev);
5512
5513         init_timer(&np->oom_kick);
5514         np->oom_kick.data = (unsigned long) dev;
5515         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5516         init_timer(&np->nic_poll);
5517         np->nic_poll.data = (unsigned long) dev;
5518         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5519         init_timer(&np->stats_poll);
5520         np->stats_poll.data = (unsigned long) dev;
5521         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5522
5523         err = pci_enable_device(pci_dev);
5524         if (err)
5525                 goto out_free;
5526
5527         pci_set_master(pci_dev);
5528
5529         err = pci_request_regions(pci_dev, DRV_NAME);
5530         if (err < 0)
5531                 goto out_disable;
5532
5533         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5534                 np->register_size = NV_PCI_REGSZ_VER3;
5535         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5536                 np->register_size = NV_PCI_REGSZ_VER2;
5537         else
5538                 np->register_size = NV_PCI_REGSZ_VER1;
5539
5540         err = -EINVAL;
5541         addr = 0;
5542         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5543                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5544                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5545                                 pci_resource_len(pci_dev, i),
5546                                 pci_resource_flags(pci_dev, i));
5547                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5548                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5549                         addr = pci_resource_start(pci_dev, i);
5550                         break;
5551                 }
5552         }
5553         if (i == DEVICE_COUNT_RESOURCE) {
5554                 dev_printk(KERN_INFO, &pci_dev->dev,
5555                            "Couldn't find register window\n");
5556                 goto out_relreg;
5557         }
5558
5559         /* copy of driver data */
5560         np->driver_data = id->driver_data;
5561         /* copy o