Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.64"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/sched.h>
53 #include <linux/spinlock.h>
54 #include <linux/ethtool.h>
55 #include <linux/timer.h>
56 #include <linux/skbuff.h>
57 #include <linux/mii.h>
58 #include <linux/random.h>
59 #include <linux/init.h>
60 #include <linux/if_vlan.h>
61 #include <linux/dma-mapping.h>
62
63 #include <asm/irq.h>
64 #include <asm/io.h>
65 #include <asm/uaccess.h>
66 #include <asm/system.h>
67
68 #if 0
69 #define dprintk                 printk
70 #else
71 #define dprintk(x...)           do { } while (0)
72 #endif
73
74 #define TX_WORK_PER_LOOP  64
75 #define RX_WORK_PER_LOOP  64
76
77 /*
78  * Hardware access:
79  */
80
81 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
82 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
83 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
84 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
85 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
86 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
87 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
88 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
89 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
90 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
91 #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
92 #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
93 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
94 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
95 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
96 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
97 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
98 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
99 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
100 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
101 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
102 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
103 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
104 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
105 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
106
107 enum {
108         NvRegIrqStatus = 0x000,
109 #define NVREG_IRQSTAT_MIIEVENT  0x040
110 #define NVREG_IRQSTAT_MASK              0x83ff
111         NvRegIrqMask = 0x004,
112 #define NVREG_IRQ_RX_ERROR              0x0001
113 #define NVREG_IRQ_RX                    0x0002
114 #define NVREG_IRQ_RX_NOBUF              0x0004
115 #define NVREG_IRQ_TX_ERR                0x0008
116 #define NVREG_IRQ_TX_OK                 0x0010
117 #define NVREG_IRQ_TIMER                 0x0020
118 #define NVREG_IRQ_LINK                  0x0040
119 #define NVREG_IRQ_RX_FORCED             0x0080
120 #define NVREG_IRQ_TX_FORCED             0x0100
121 #define NVREG_IRQ_RECOVER_ERROR         0x8200
122 #define NVREG_IRQMASK_THROUGHPUT        0x00df
123 #define NVREG_IRQMASK_CPU               0x0060
124 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
125 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
126 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
127
128         NvRegUnknownSetupReg6 = 0x008,
129 #define NVREG_UNKSETUP6_VAL             3
130
131 /*
132  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
133  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
134  */
135         NvRegPollingInterval = 0x00c,
136 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
137 #define NVREG_POLL_DEFAULT_CPU  13
138         NvRegMSIMap0 = 0x020,
139         NvRegMSIMap1 = 0x024,
140         NvRegMSIIrqMask = 0x030,
141 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
142         NvRegMisc1 = 0x080,
143 #define NVREG_MISC1_PAUSE_TX    0x01
144 #define NVREG_MISC1_HD          0x02
145 #define NVREG_MISC1_FORCE       0x3b0f3c
146
147         NvRegMacReset = 0x34,
148 #define NVREG_MAC_RESET_ASSERT  0x0F3
149         NvRegTransmitterControl = 0x084,
150 #define NVREG_XMITCTL_START     0x01
151 #define NVREG_XMITCTL_MGMT_ST   0x40000000
152 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
153 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
154 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
155 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
156 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
157 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
158 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
159 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
160 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
161 #define NVREG_XMITCTL_DATA_START        0x00100000
162 #define NVREG_XMITCTL_DATA_READY        0x00010000
163 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
164         NvRegTransmitterStatus = 0x088,
165 #define NVREG_XMITSTAT_BUSY     0x01
166
167         NvRegPacketFilterFlags = 0x8c,
168 #define NVREG_PFF_PAUSE_RX      0x08
169 #define NVREG_PFF_ALWAYS        0x7F0000
170 #define NVREG_PFF_PROMISC       0x80
171 #define NVREG_PFF_MYADDR        0x20
172 #define NVREG_PFF_LOOPBACK      0x10
173
174         NvRegOffloadConfig = 0x90,
175 #define NVREG_OFFLOAD_HOMEPHY   0x601
176 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
177         NvRegReceiverControl = 0x094,
178 #define NVREG_RCVCTL_START      0x01
179 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
180         NvRegReceiverStatus = 0x98,
181 #define NVREG_RCVSTAT_BUSY      0x01
182
183         NvRegSlotTime = 0x9c,
184 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
185 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
186 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
187 #define NVREG_SLOTTIME_HALF             0x0000ff00
188 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
189 #define NVREG_SLOTTIME_MASK             0x000000ff
190
191         NvRegTxDeferral = 0xA0,
192 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
193 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
194 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
197 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
198         NvRegRxDeferral = 0xA4,
199 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
200         NvRegMacAddrA = 0xA8,
201         NvRegMacAddrB = 0xAC,
202         NvRegMulticastAddrA = 0xB0,
203 #define NVREG_MCASTADDRA_FORCE  0x01
204         NvRegMulticastAddrB = 0xB4,
205         NvRegMulticastMaskA = 0xB8,
206 #define NVREG_MCASTMASKA_NONE           0xffffffff
207         NvRegMulticastMaskB = 0xBC,
208 #define NVREG_MCASTMASKB_NONE           0xffff
209
210         NvRegPhyInterface = 0xC0,
211 #define PHY_RGMII               0x10000000
212         NvRegBackOffControl = 0xC4,
213 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
214 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
215 #define NVREG_BKOFFCTRL_SELECT                  24
216 #define NVREG_BKOFFCTRL_GEAR                    12
217
218         NvRegTxRingPhysAddr = 0x100,
219         NvRegRxRingPhysAddr = 0x104,
220         NvRegRingSizes = 0x108,
221 #define NVREG_RINGSZ_TXSHIFT 0
222 #define NVREG_RINGSZ_RXSHIFT 16
223         NvRegTransmitPoll = 0x10c,
224 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
225         NvRegLinkSpeed = 0x110,
226 #define NVREG_LINKSPEED_FORCE 0x10000
227 #define NVREG_LINKSPEED_10      1000
228 #define NVREG_LINKSPEED_100     100
229 #define NVREG_LINKSPEED_1000    50
230 #define NVREG_LINKSPEED_MASK    (0xFFF)
231         NvRegUnknownSetupReg5 = 0x130,
232 #define NVREG_UNKSETUP5_BIT31   (1<<31)
233         NvRegTxWatermark = 0x13c,
234 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
235 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
236 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
237         NvRegTxRxControl = 0x144,
238 #define NVREG_TXRXCTL_KICK      0x0001
239 #define NVREG_TXRXCTL_BIT1      0x0002
240 #define NVREG_TXRXCTL_BIT2      0x0004
241 #define NVREG_TXRXCTL_IDLE      0x0008
242 #define NVREG_TXRXCTL_RESET     0x0010
243 #define NVREG_TXRXCTL_RXCHECK   0x0400
244 #define NVREG_TXRXCTL_DESC_1    0
245 #define NVREG_TXRXCTL_DESC_2    0x002100
246 #define NVREG_TXRXCTL_DESC_3    0xc02200
247 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
248 #define NVREG_TXRXCTL_VLANINS   0x00080
249         NvRegTxRingPhysAddrHigh = 0x148,
250         NvRegRxRingPhysAddrHigh = 0x14C,
251         NvRegTxPauseFrame = 0x170,
252 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
253 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
256         NvRegTxPauseFrameLimit = 0x174,
257 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
258         NvRegMIIStatus = 0x180,
259 #define NVREG_MIISTAT_ERROR             0x0001
260 #define NVREG_MIISTAT_LINKCHANGE        0x0008
261 #define NVREG_MIISTAT_MASK_RW           0x0007
262 #define NVREG_MIISTAT_MASK_ALL          0x000f
263         NvRegMIIMask = 0x184,
264 #define NVREG_MII_LINKCHANGE            0x0008
265
266         NvRegAdapterControl = 0x188,
267 #define NVREG_ADAPTCTL_START    0x02
268 #define NVREG_ADAPTCTL_LINKUP   0x04
269 #define NVREG_ADAPTCTL_PHYVALID 0x40000
270 #define NVREG_ADAPTCTL_RUNNING  0x100000
271 #define NVREG_ADAPTCTL_PHYSHIFT 24
272         NvRegMIISpeed = 0x18c,
273 #define NVREG_MIISPEED_BIT8     (1<<8)
274 #define NVREG_MIIDELAY  5
275         NvRegMIIControl = 0x190,
276 #define NVREG_MIICTL_INUSE      0x08000
277 #define NVREG_MIICTL_WRITE      0x00400
278 #define NVREG_MIICTL_ADDRSHIFT  5
279         NvRegMIIData = 0x194,
280         NvRegTxUnicast = 0x1a0,
281         NvRegTxMulticast = 0x1a4,
282         NvRegTxBroadcast = 0x1a8,
283         NvRegWakeUpFlags = 0x200,
284 #define NVREG_WAKEUPFLAGS_VAL           0x7770
285 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
286 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
287 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
288 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
289 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
290 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
291 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
292 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
293 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
294 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
295
296         NvRegMgmtUnitGetVersion = 0x204,
297 #define NVREG_MGMTUNITGETVERSION        0x01
298         NvRegMgmtUnitVersion = 0x208,
299 #define NVREG_MGMTUNITVERSION           0x08
300         NvRegPowerCap = 0x268,
301 #define NVREG_POWERCAP_D3SUPP   (1<<30)
302 #define NVREG_POWERCAP_D2SUPP   (1<<26)
303 #define NVREG_POWERCAP_D1SUPP   (1<<25)
304         NvRegPowerState = 0x26c,
305 #define NVREG_POWERSTATE_POWEREDUP      0x8000
306 #define NVREG_POWERSTATE_VALID          0x0100
307 #define NVREG_POWERSTATE_MASK           0x0003
308 #define NVREG_POWERSTATE_D0             0x0000
309 #define NVREG_POWERSTATE_D1             0x0001
310 #define NVREG_POWERSTATE_D2             0x0002
311 #define NVREG_POWERSTATE_D3             0x0003
312         NvRegMgmtUnitControl = 0x278,
313 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
314         NvRegTxCnt = 0x280,
315         NvRegTxZeroReXmt = 0x284,
316         NvRegTxOneReXmt = 0x288,
317         NvRegTxManyReXmt = 0x28c,
318         NvRegTxLateCol = 0x290,
319         NvRegTxUnderflow = 0x294,
320         NvRegTxLossCarrier = 0x298,
321         NvRegTxExcessDef = 0x29c,
322         NvRegTxRetryErr = 0x2a0,
323         NvRegRxFrameErr = 0x2a4,
324         NvRegRxExtraByte = 0x2a8,
325         NvRegRxLateCol = 0x2ac,
326         NvRegRxRunt = 0x2b0,
327         NvRegRxFrameTooLong = 0x2b4,
328         NvRegRxOverflow = 0x2b8,
329         NvRegRxFCSErr = 0x2bc,
330         NvRegRxFrameAlignErr = 0x2c0,
331         NvRegRxLenErr = 0x2c4,
332         NvRegRxUnicast = 0x2c8,
333         NvRegRxMulticast = 0x2cc,
334         NvRegRxBroadcast = 0x2d0,
335         NvRegTxDef = 0x2d4,
336         NvRegTxFrame = 0x2d8,
337         NvRegRxCnt = 0x2dc,
338         NvRegTxPause = 0x2e0,
339         NvRegRxPause = 0x2e4,
340         NvRegRxDropFrame = 0x2e8,
341         NvRegVlanControl = 0x300,
342 #define NVREG_VLANCONTROL_ENABLE        0x2000
343         NvRegMSIXMap0 = 0x3e0,
344         NvRegMSIXMap1 = 0x3e4,
345         NvRegMSIXIrqStatus = 0x3f0,
346
347         NvRegPowerState2 = 0x600,
348 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
349 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
350 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
351 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
352 };
353
354 /* Big endian: should work, but is untested */
355 struct ring_desc {
356         __le32 buf;
357         __le32 flaglen;
358 };
359
360 struct ring_desc_ex {
361         __le32 bufhigh;
362         __le32 buflow;
363         __le32 txvlan;
364         __le32 flaglen;
365 };
366
367 union ring_type {
368         struct ring_desc* orig;
369         struct ring_desc_ex* ex;
370 };
371
372 #define FLAG_MASK_V1 0xffff0000
373 #define FLAG_MASK_V2 0xffffc000
374 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
375 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
376
377 #define NV_TX_LASTPACKET        (1<<16)
378 #define NV_TX_RETRYERROR        (1<<19)
379 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
380 #define NV_TX_FORCED_INTERRUPT  (1<<24)
381 #define NV_TX_DEFERRED          (1<<26)
382 #define NV_TX_CARRIERLOST       (1<<27)
383 #define NV_TX_LATECOLLISION     (1<<28)
384 #define NV_TX_UNDERFLOW         (1<<29)
385 #define NV_TX_ERROR             (1<<30)
386 #define NV_TX_VALID             (1<<31)
387
388 #define NV_TX2_LASTPACKET       (1<<29)
389 #define NV_TX2_RETRYERROR       (1<<18)
390 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
391 #define NV_TX2_FORCED_INTERRUPT (1<<30)
392 #define NV_TX2_DEFERRED         (1<<25)
393 #define NV_TX2_CARRIERLOST      (1<<26)
394 #define NV_TX2_LATECOLLISION    (1<<27)
395 #define NV_TX2_UNDERFLOW        (1<<28)
396 /* error and valid are the same for both */
397 #define NV_TX2_ERROR            (1<<30)
398 #define NV_TX2_VALID            (1<<31)
399 #define NV_TX2_TSO              (1<<28)
400 #define NV_TX2_TSO_SHIFT        14
401 #define NV_TX2_TSO_MAX_SHIFT    14
402 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
403 #define NV_TX2_CHECKSUM_L3      (1<<27)
404 #define NV_TX2_CHECKSUM_L4      (1<<26)
405
406 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
407
408 #define NV_RX_DESCRIPTORVALID   (1<<16)
409 #define NV_RX_MISSEDFRAME       (1<<17)
410 #define NV_RX_SUBSTRACT1        (1<<18)
411 #define NV_RX_ERROR1            (1<<23)
412 #define NV_RX_ERROR2            (1<<24)
413 #define NV_RX_ERROR3            (1<<25)
414 #define NV_RX_ERROR4            (1<<26)
415 #define NV_RX_CRCERR            (1<<27)
416 #define NV_RX_OVERFLOW          (1<<28)
417 #define NV_RX_FRAMINGERR        (1<<29)
418 #define NV_RX_ERROR             (1<<30)
419 #define NV_RX_AVAIL             (1<<31)
420 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
421
422 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
423 #define NV_RX2_CHECKSUM_IP      (0x10000000)
424 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
425 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
426 #define NV_RX2_DESCRIPTORVALID  (1<<29)
427 #define NV_RX2_SUBSTRACT1       (1<<25)
428 #define NV_RX2_ERROR1           (1<<18)
429 #define NV_RX2_ERROR2           (1<<19)
430 #define NV_RX2_ERROR3           (1<<20)
431 #define NV_RX2_ERROR4           (1<<21)
432 #define NV_RX2_CRCERR           (1<<22)
433 #define NV_RX2_OVERFLOW         (1<<23)
434 #define NV_RX2_FRAMINGERR       (1<<24)
435 /* error and avail are the same for both */
436 #define NV_RX2_ERROR            (1<<30)
437 #define NV_RX2_AVAIL            (1<<31)
438 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
439
440 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
441 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
442
443 /* Miscelaneous hardware related defines: */
444 #define NV_PCI_REGSZ_VER1       0x270
445 #define NV_PCI_REGSZ_VER2       0x2d4
446 #define NV_PCI_REGSZ_VER3       0x604
447 #define NV_PCI_REGSZ_MAX        0x604
448
449 /* various timeout delays: all in usec */
450 #define NV_TXRX_RESET_DELAY     4
451 #define NV_TXSTOP_DELAY1        10
452 #define NV_TXSTOP_DELAY1MAX     500000
453 #define NV_TXSTOP_DELAY2        100
454 #define NV_RXSTOP_DELAY1        10
455 #define NV_RXSTOP_DELAY1MAX     500000
456 #define NV_RXSTOP_DELAY2        100
457 #define NV_SETUP5_DELAY         5
458 #define NV_SETUP5_DELAYMAX      50000
459 #define NV_POWERUP_DELAY        5
460 #define NV_POWERUP_DELAYMAX     5000
461 #define NV_MIIBUSY_DELAY        50
462 #define NV_MIIPHY_DELAY 10
463 #define NV_MIIPHY_DELAYMAX      10000
464 #define NV_MAC_RESET_DELAY      64
465
466 #define NV_WAKEUPPATTERNS       5
467 #define NV_WAKEUPMASKENTRIES    4
468
469 /* General driver defaults */
470 #define NV_WATCHDOG_TIMEO       (5*HZ)
471
472 #define RX_RING_DEFAULT         512
473 #define TX_RING_DEFAULT         256
474 #define RX_RING_MIN             128
475 #define TX_RING_MIN             64
476 #define RING_MAX_DESC_VER_1     1024
477 #define RING_MAX_DESC_VER_2_3   16384
478
479 /* rx/tx mac addr + type + vlan + align + slack*/
480 #define NV_RX_HEADERS           (64)
481 /* even more slack. */
482 #define NV_RX_ALLOC_PAD         (64)
483
484 /* maximum mtu size */
485 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
486 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
487
488 #define OOM_REFILL      (1+HZ/20)
489 #define POLL_WAIT       (1+HZ/100)
490 #define LINK_TIMEOUT    (3*HZ)
491 #define STATS_INTERVAL  (10*HZ)
492
493 /*
494  * desc_ver values:
495  * The nic supports three different descriptor types:
496  * - DESC_VER_1: Original
497  * - DESC_VER_2: support for jumbo frames.
498  * - DESC_VER_3: 64-bit format.
499  */
500 #define DESC_VER_1      1
501 #define DESC_VER_2      2
502 #define DESC_VER_3      3
503
504 /* PHY defines */
505 #define PHY_OUI_MARVELL         0x5043
506 #define PHY_OUI_CICADA          0x03f1
507 #define PHY_OUI_VITESSE         0x01c1
508 #define PHY_OUI_REALTEK         0x0732
509 #define PHY_OUI_REALTEK2        0x0020
510 #define PHYID1_OUI_MASK 0x03ff
511 #define PHYID1_OUI_SHFT 6
512 #define PHYID2_OUI_MASK 0xfc00
513 #define PHYID2_OUI_SHFT 10
514 #define PHYID2_MODEL_MASK               0x03f0
515 #define PHY_MODEL_REALTEK_8211          0x0110
516 #define PHY_REV_MASK                    0x0001
517 #define PHY_REV_REALTEK_8211B           0x0000
518 #define PHY_REV_REALTEK_8211C           0x0001
519 #define PHY_MODEL_REALTEK_8201          0x0200
520 #define PHY_MODEL_MARVELL_E3016         0x0220
521 #define PHY_MARVELL_E3016_INITMASK      0x0300
522 #define PHY_CICADA_INIT1        0x0f000
523 #define PHY_CICADA_INIT2        0x0e00
524 #define PHY_CICADA_INIT3        0x01000
525 #define PHY_CICADA_INIT4        0x0200
526 #define PHY_CICADA_INIT5        0x0004
527 #define PHY_CICADA_INIT6        0x02000
528 #define PHY_VITESSE_INIT_REG1   0x1f
529 #define PHY_VITESSE_INIT_REG2   0x10
530 #define PHY_VITESSE_INIT_REG3   0x11
531 #define PHY_VITESSE_INIT_REG4   0x12
532 #define PHY_VITESSE_INIT_MSK1   0xc
533 #define PHY_VITESSE_INIT_MSK2   0x0180
534 #define PHY_VITESSE_INIT1       0x52b5
535 #define PHY_VITESSE_INIT2       0xaf8a
536 #define PHY_VITESSE_INIT3       0x8
537 #define PHY_VITESSE_INIT4       0x8f8a
538 #define PHY_VITESSE_INIT5       0xaf86
539 #define PHY_VITESSE_INIT6       0x8f86
540 #define PHY_VITESSE_INIT7       0xaf82
541 #define PHY_VITESSE_INIT8       0x0100
542 #define PHY_VITESSE_INIT9       0x8f82
543 #define PHY_VITESSE_INIT10      0x0
544 #define PHY_REALTEK_INIT_REG1   0x1f
545 #define PHY_REALTEK_INIT_REG2   0x19
546 #define PHY_REALTEK_INIT_REG3   0x13
547 #define PHY_REALTEK_INIT_REG4   0x14
548 #define PHY_REALTEK_INIT_REG5   0x18
549 #define PHY_REALTEK_INIT_REG6   0x11
550 #define PHY_REALTEK_INIT_REG7   0x01
551 #define PHY_REALTEK_INIT1       0x0000
552 #define PHY_REALTEK_INIT2       0x8e00
553 #define PHY_REALTEK_INIT3       0x0001
554 #define PHY_REALTEK_INIT4       0xad17
555 #define PHY_REALTEK_INIT5       0xfb54
556 #define PHY_REALTEK_INIT6       0xf5c7
557 #define PHY_REALTEK_INIT7       0x1000
558 #define PHY_REALTEK_INIT8       0x0003
559 #define PHY_REALTEK_INIT9       0x0008
560 #define PHY_REALTEK_INIT10      0x0005
561 #define PHY_REALTEK_INIT11      0x0200
562 #define PHY_REALTEK_INIT_MSK1   0x0003
563
564 #define PHY_GIGABIT     0x0100
565
566 #define PHY_TIMEOUT     0x1
567 #define PHY_ERROR       0x2
568
569 #define PHY_100 0x1
570 #define PHY_1000        0x2
571 #define PHY_HALF        0x100
572
573 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
574 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
575 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
576 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
577 #define NV_PAUSEFRAME_RX_REQ     0x0010
578 #define NV_PAUSEFRAME_TX_REQ     0x0020
579 #define NV_PAUSEFRAME_AUTONEG    0x0040
580
581 /* MSI/MSI-X defines */
582 #define NV_MSI_X_MAX_VECTORS  8
583 #define NV_MSI_X_VECTORS_MASK 0x000f
584 #define NV_MSI_CAPABLE        0x0010
585 #define NV_MSI_X_CAPABLE      0x0020
586 #define NV_MSI_ENABLED        0x0040
587 #define NV_MSI_X_ENABLED      0x0080
588
589 #define NV_MSI_X_VECTOR_ALL   0x0
590 #define NV_MSI_X_VECTOR_RX    0x0
591 #define NV_MSI_X_VECTOR_TX    0x1
592 #define NV_MSI_X_VECTOR_OTHER 0x2
593
594 #define NV_MSI_PRIV_OFFSET 0x68
595 #define NV_MSI_PRIV_VALUE  0xffffffff
596
597 #define NV_RESTART_TX         0x1
598 #define NV_RESTART_RX         0x2
599
600 #define NV_TX_LIMIT_COUNT     16
601
602 #define NV_DYNAMIC_THRESHOLD        4
603 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
604
605 /* statistics */
606 struct nv_ethtool_str {
607         char name[ETH_GSTRING_LEN];
608 };
609
610 static const struct nv_ethtool_str nv_estats_str[] = {
611         { "tx_bytes" },
612         { "tx_zero_rexmt" },
613         { "tx_one_rexmt" },
614         { "tx_many_rexmt" },
615         { "tx_late_collision" },
616         { "tx_fifo_errors" },
617         { "tx_carrier_errors" },
618         { "tx_excess_deferral" },
619         { "tx_retry_error" },
620         { "rx_frame_error" },
621         { "rx_extra_byte" },
622         { "rx_late_collision" },
623         { "rx_runt" },
624         { "rx_frame_too_long" },
625         { "rx_over_errors" },
626         { "rx_crc_errors" },
627         { "rx_frame_align_error" },
628         { "rx_length_error" },
629         { "rx_unicast" },
630         { "rx_multicast" },
631         { "rx_broadcast" },
632         { "rx_packets" },
633         { "rx_errors_total" },
634         { "tx_errors_total" },
635
636         /* version 2 stats */
637         { "tx_deferral" },
638         { "tx_packets" },
639         { "rx_bytes" },
640         { "tx_pause" },
641         { "rx_pause" },
642         { "rx_drop_frame" },
643
644         /* version 3 stats */
645         { "tx_unicast" },
646         { "tx_multicast" },
647         { "tx_broadcast" }
648 };
649
650 struct nv_ethtool_stats {
651         u64 tx_bytes;
652         u64 tx_zero_rexmt;
653         u64 tx_one_rexmt;
654         u64 tx_many_rexmt;
655         u64 tx_late_collision;
656         u64 tx_fifo_errors;
657         u64 tx_carrier_errors;
658         u64 tx_excess_deferral;
659         u64 tx_retry_error;
660         u64 rx_frame_error;
661         u64 rx_extra_byte;
662         u64 rx_late_collision;
663         u64 rx_runt;
664         u64 rx_frame_too_long;
665         u64 rx_over_errors;
666         u64 rx_crc_errors;
667         u64 rx_frame_align_error;
668         u64 rx_length_error;
669         u64 rx_unicast;
670         u64 rx_multicast;
671         u64 rx_broadcast;
672         u64 rx_packets;
673         u64 rx_errors_total;
674         u64 tx_errors_total;
675
676         /* version 2 stats */
677         u64 tx_deferral;
678         u64 tx_packets;
679         u64 rx_bytes;
680         u64 tx_pause;
681         u64 rx_pause;
682         u64 rx_drop_frame;
683
684         /* version 3 stats */
685         u64 tx_unicast;
686         u64 tx_multicast;
687         u64 tx_broadcast;
688 };
689
690 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
691 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
692 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
693
694 /* diagnostics */
695 #define NV_TEST_COUNT_BASE 3
696 #define NV_TEST_COUNT_EXTENDED 4
697
698 static const struct nv_ethtool_str nv_etests_str[] = {
699         { "link      (online/offline)" },
700         { "register  (offline)       " },
701         { "interrupt (offline)       " },
702         { "loopback  (offline)       " }
703 };
704
705 struct register_test {
706         __u32 reg;
707         __u32 mask;
708 };
709
710 static const struct register_test nv_registers_test[] = {
711         { NvRegUnknownSetupReg6, 0x01 },
712         { NvRegMisc1, 0x03c },
713         { NvRegOffloadConfig, 0x03ff },
714         { NvRegMulticastAddrA, 0xffffffff },
715         { NvRegTxWatermark, 0x0ff },
716         { NvRegWakeUpFlags, 0x07777 },
717         { 0,0 }
718 };
719
720 struct nv_skb_map {
721         struct sk_buff *skb;
722         dma_addr_t dma;
723         unsigned int dma_len:31;
724         unsigned int dma_single:1;
725         struct ring_desc_ex *first_tx_desc;
726         struct nv_skb_map *next_tx_ctx;
727 };
728
729 /*
730  * SMP locking:
731  * All hardware access under netdev_priv(dev)->lock, except the performance
732  * critical parts:
733  * - rx is (pseudo-) lockless: it relies on the single-threading provided
734  *      by the arch code for interrupts.
735  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
736  *      needs netdev_priv(dev)->lock :-(
737  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
738  */
739
740 /* in dev: base, irq */
741 struct fe_priv {
742         spinlock_t lock;
743
744         struct net_device *dev;
745         struct napi_struct napi;
746
747         /* General data:
748          * Locking: spin_lock(&np->lock); */
749         struct nv_ethtool_stats estats;
750         int in_shutdown;
751         u32 linkspeed;
752         int duplex;
753         int autoneg;
754         int fixed_mode;
755         int phyaddr;
756         int wolenabled;
757         unsigned int phy_oui;
758         unsigned int phy_model;
759         unsigned int phy_rev;
760         u16 gigabit;
761         int intr_test;
762         int recover_error;
763         int quiet_count;
764
765         /* General data: RO fields */
766         dma_addr_t ring_addr;
767         struct pci_dev *pci_dev;
768         u32 orig_mac[2];
769         u32 events;
770         u32 irqmask;
771         u32 desc_ver;
772         u32 txrxctl_bits;
773         u32 vlanctl_bits;
774         u32 driver_data;
775         u32 device_id;
776         u32 register_size;
777         int rx_csum;
778         u32 mac_in_use;
779         int mgmt_version;
780         int mgmt_sema;
781
782         void __iomem *base;
783
784         /* rx specific fields.
785          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
786          */
787         union ring_type get_rx, put_rx, first_rx, last_rx;
788         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
789         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
790         struct nv_skb_map *rx_skb;
791
792         union ring_type rx_ring;
793         unsigned int rx_buf_sz;
794         unsigned int pkt_limit;
795         struct timer_list oom_kick;
796         struct timer_list nic_poll;
797         struct timer_list stats_poll;
798         u32 nic_poll_irq;
799         int rx_ring_size;
800
801         /* media detection workaround.
802          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
803          */
804         int need_linktimer;
805         unsigned long link_timeout;
806         /*
807          * tx specific fields.
808          */
809         union ring_type get_tx, put_tx, first_tx, last_tx;
810         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
811         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
812         struct nv_skb_map *tx_skb;
813
814         union ring_type tx_ring;
815         u32 tx_flags;
816         int tx_ring_size;
817         int tx_limit;
818         u32 tx_pkts_in_progress;
819         struct nv_skb_map *tx_change_owner;
820         struct nv_skb_map *tx_end_flip;
821         int tx_stop;
822
823         /* vlan fields */
824         struct vlan_group *vlangrp;
825
826         /* msi/msi-x fields */
827         u32 msi_flags;
828         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
829
830         /* flow control */
831         u32 pause_flags;
832
833         /* power saved state */
834         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
835
836         /* for different msi-x irq type */
837         char name_rx[IFNAMSIZ + 3];       /* -rx    */
838         char name_tx[IFNAMSIZ + 3];       /* -tx    */
839         char name_other[IFNAMSIZ + 6];    /* -other */
840 };
841
842 /*
843  * Maximum number of loops until we assume that a bit in the irq mask
844  * is stuck. Overridable with module param.
845  */
846 static int max_interrupt_work = 4;
847
848 /*
849  * Optimization can be either throuput mode or cpu mode
850  *
851  * Throughput Mode: Every tx and rx packet will generate an interrupt.
852  * CPU Mode: Interrupts are controlled by a timer.
853  */
854 enum {
855         NV_OPTIMIZATION_MODE_THROUGHPUT,
856         NV_OPTIMIZATION_MODE_CPU,
857         NV_OPTIMIZATION_MODE_DYNAMIC
858 };
859 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
860
861 /*
862  * Poll interval for timer irq
863  *
864  * This interval determines how frequent an interrupt is generated.
865  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
866  * Min = 0, and Max = 65535
867  */
868 static int poll_interval = -1;
869
870 /*
871  * MSI interrupts
872  */
873 enum {
874         NV_MSI_INT_DISABLED,
875         NV_MSI_INT_ENABLED
876 };
877 static int msi = NV_MSI_INT_ENABLED;
878
879 /*
880  * MSIX interrupts
881  */
882 enum {
883         NV_MSIX_INT_DISABLED,
884         NV_MSIX_INT_ENABLED
885 };
886 static int msix = NV_MSIX_INT_ENABLED;
887
888 /*
889  * DMA 64bit
890  */
891 enum {
892         NV_DMA_64BIT_DISABLED,
893         NV_DMA_64BIT_ENABLED
894 };
895 static int dma_64bit = NV_DMA_64BIT_ENABLED;
896
897 /*
898  * Crossover Detection
899  * Realtek 8201 phy + some OEM boards do not work properly.
900  */
901 enum {
902         NV_CROSSOVER_DETECTION_DISABLED,
903         NV_CROSSOVER_DETECTION_ENABLED
904 };
905 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
906
907 /*
908  * Power down phy when interface is down (persists through reboot;
909  * older Linux and other OSes may not power it up again)
910  */
911 static int phy_power_down = 0;
912
913 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
914 {
915         return netdev_priv(dev);
916 }
917
918 static inline u8 __iomem *get_hwbase(struct net_device *dev)
919 {
920         return ((struct fe_priv *)netdev_priv(dev))->base;
921 }
922
923 static inline void pci_push(u8 __iomem *base)
924 {
925         /* force out pending posted writes */
926         readl(base);
927 }
928
929 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
930 {
931         return le32_to_cpu(prd->flaglen)
932                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
933 }
934
935 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
936 {
937         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
938 }
939
940 static bool nv_optimized(struct fe_priv *np)
941 {
942         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
943                 return false;
944         return true;
945 }
946
947 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
948                                 int delay, int delaymax, const char *msg)
949 {
950         u8 __iomem *base = get_hwbase(dev);
951
952         pci_push(base);
953         do {
954                 udelay(delay);
955                 delaymax -= delay;
956                 if (delaymax < 0) {
957                         if (msg)
958                                 printk("%s", msg);
959                         return 1;
960                 }
961         } while ((readl(base + offset) & mask) != target);
962         return 0;
963 }
964
965 #define NV_SETUP_RX_RING 0x01
966 #define NV_SETUP_TX_RING 0x02
967
968 static inline u32 dma_low(dma_addr_t addr)
969 {
970         return addr;
971 }
972
973 static inline u32 dma_high(dma_addr_t addr)
974 {
975         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
976 }
977
978 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
979 {
980         struct fe_priv *np = get_nvpriv(dev);
981         u8 __iomem *base = get_hwbase(dev);
982
983         if (!nv_optimized(np)) {
984                 if (rxtx_flags & NV_SETUP_RX_RING) {
985                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
986                 }
987                 if (rxtx_flags & NV_SETUP_TX_RING) {
988                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
989                 }
990         } else {
991                 if (rxtx_flags & NV_SETUP_RX_RING) {
992                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
993                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
994                 }
995                 if (rxtx_flags & NV_SETUP_TX_RING) {
996                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
997                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
998                 }
999         }
1000 }
1001
1002 static void free_rings(struct net_device *dev)
1003 {
1004         struct fe_priv *np = get_nvpriv(dev);
1005
1006         if (!nv_optimized(np)) {
1007                 if (np->rx_ring.orig)
1008                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1009                                             np->rx_ring.orig, np->ring_addr);
1010         } else {
1011                 if (np->rx_ring.ex)
1012                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1013                                             np->rx_ring.ex, np->ring_addr);
1014         }
1015         if (np->rx_skb)
1016                 kfree(np->rx_skb);
1017         if (np->tx_skb)
1018                 kfree(np->tx_skb);
1019 }
1020
1021 static int using_multi_irqs(struct net_device *dev)
1022 {
1023         struct fe_priv *np = get_nvpriv(dev);
1024
1025         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1026             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1027              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1028                 return 0;
1029         else
1030                 return 1;
1031 }
1032
1033 static void nv_txrx_gate(struct net_device *dev, bool gate)
1034 {
1035         struct fe_priv *np = get_nvpriv(dev);
1036         u8 __iomem *base = get_hwbase(dev);
1037         u32 powerstate;
1038
1039         if (!np->mac_in_use &&
1040             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1041                 powerstate = readl(base + NvRegPowerState2);
1042                 if (gate)
1043                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1044                 else
1045                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1046                 writel(powerstate, base + NvRegPowerState2);
1047         }
1048 }
1049
1050 static void nv_enable_irq(struct net_device *dev)
1051 {
1052         struct fe_priv *np = get_nvpriv(dev);
1053
1054         if (!using_multi_irqs(dev)) {
1055                 if (np->msi_flags & NV_MSI_X_ENABLED)
1056                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1057                 else
1058                         enable_irq(np->pci_dev->irq);
1059         } else {
1060                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1061                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1062                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1063         }
1064 }
1065
1066 static void nv_disable_irq(struct net_device *dev)
1067 {
1068         struct fe_priv *np = get_nvpriv(dev);
1069
1070         if (!using_multi_irqs(dev)) {
1071                 if (np->msi_flags & NV_MSI_X_ENABLED)
1072                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1073                 else
1074                         disable_irq(np->pci_dev->irq);
1075         } else {
1076                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1077                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1078                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1079         }
1080 }
1081
1082 /* In MSIX mode, a write to irqmask behaves as XOR */
1083 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1084 {
1085         u8 __iomem *base = get_hwbase(dev);
1086
1087         writel(mask, base + NvRegIrqMask);
1088 }
1089
1090 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1091 {
1092         struct fe_priv *np = get_nvpriv(dev);
1093         u8 __iomem *base = get_hwbase(dev);
1094
1095         if (np->msi_flags & NV_MSI_X_ENABLED) {
1096                 writel(mask, base + NvRegIrqMask);
1097         } else {
1098                 if (np->msi_flags & NV_MSI_ENABLED)
1099                         writel(0, base + NvRegMSIIrqMask);
1100                 writel(0, base + NvRegIrqMask);
1101         }
1102 }
1103
1104 static void nv_napi_enable(struct net_device *dev)
1105 {
1106 #ifdef CONFIG_FORCEDETH_NAPI
1107         struct fe_priv *np = get_nvpriv(dev);
1108
1109         napi_enable(&np->napi);
1110 #endif
1111 }
1112
1113 static void nv_napi_disable(struct net_device *dev)
1114 {
1115 #ifdef CONFIG_FORCEDETH_NAPI
1116         struct fe_priv *np = get_nvpriv(dev);
1117
1118         napi_disable(&np->napi);
1119 #endif
1120 }
1121
1122 #define MII_READ        (-1)
1123 /* mii_rw: read/write a register on the PHY.
1124  *
1125  * Caller must guarantee serialization
1126  */
1127 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1128 {
1129         u8 __iomem *base = get_hwbase(dev);
1130         u32 reg;
1131         int retval;
1132
1133         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1134
1135         reg = readl(base + NvRegMIIControl);
1136         if (reg & NVREG_MIICTL_INUSE) {
1137                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1138                 udelay(NV_MIIBUSY_DELAY);
1139         }
1140
1141         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1142         if (value != MII_READ) {
1143                 writel(value, base + NvRegMIIData);
1144                 reg |= NVREG_MIICTL_WRITE;
1145         }
1146         writel(reg, base + NvRegMIIControl);
1147
1148         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1149                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1150                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1151                                 dev->name, miireg, addr);
1152                 retval = -1;
1153         } else if (value != MII_READ) {
1154                 /* it was a write operation - fewer failures are detectable */
1155                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1156                                 dev->name, value, miireg, addr);
1157                 retval = 0;
1158         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1159                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1160                                 dev->name, miireg, addr);
1161                 retval = -1;
1162         } else {
1163                 retval = readl(base + NvRegMIIData);
1164                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1165                                 dev->name, miireg, addr, retval);
1166         }
1167
1168         return retval;
1169 }
1170
1171 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1172 {
1173         struct fe_priv *np = netdev_priv(dev);
1174         u32 miicontrol;
1175         unsigned int tries = 0;
1176
1177         miicontrol = BMCR_RESET | bmcr_setup;
1178         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1179                 return -1;
1180         }
1181
1182         /* wait for 500ms */
1183         msleep(500);
1184
1185         /* must wait till reset is deasserted */
1186         while (miicontrol & BMCR_RESET) {
1187                 msleep(10);
1188                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1189                 /* FIXME: 100 tries seem excessive */
1190                 if (tries++ > 100)
1191                         return -1;
1192         }
1193         return 0;
1194 }
1195
1196 static int phy_init(struct net_device *dev)
1197 {
1198         struct fe_priv *np = get_nvpriv(dev);
1199         u8 __iomem *base = get_hwbase(dev);
1200         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1201
1202         /* phy errata for E3016 phy */
1203         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1204                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1205                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1206                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1207                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1208                         return PHY_ERROR;
1209                 }
1210         }
1211         if (np->phy_oui == PHY_OUI_REALTEK) {
1212                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1213                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1214                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1215                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1216                                 return PHY_ERROR;
1217                         }
1218                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1219                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1220                                 return PHY_ERROR;
1221                         }
1222                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1223                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1224                                 return PHY_ERROR;
1225                         }
1226                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1227                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1228                                 return PHY_ERROR;
1229                         }
1230                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1231                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1232                                 return PHY_ERROR;
1233                         }
1234                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1235                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1236                                 return PHY_ERROR;
1237                         }
1238                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1239                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1240                                 return PHY_ERROR;
1241                         }
1242                 }
1243                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1244                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1245                         u32 powerstate = readl(base + NvRegPowerState2);
1246
1247                         /* need to perform hw phy reset */
1248                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1249                         writel(powerstate, base + NvRegPowerState2);
1250                         msleep(25);
1251
1252                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1253                         writel(powerstate, base + NvRegPowerState2);
1254                         msleep(25);
1255
1256                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1257                         reg |= PHY_REALTEK_INIT9;
1258                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1259                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1260                                 return PHY_ERROR;
1261                         }
1262                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1263                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1264                                 return PHY_ERROR;
1265                         }
1266                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1267                         if (!(reg & PHY_REALTEK_INIT11)) {
1268                                 reg |= PHY_REALTEK_INIT11;
1269                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1270                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1271                                         return PHY_ERROR;
1272                                 }
1273                         }
1274                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1275                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1276                                 return PHY_ERROR;
1277                         }
1278                 }
1279                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1280                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1281                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1282                                 phy_reserved |= PHY_REALTEK_INIT7;
1283                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1284                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1285                                         return PHY_ERROR;
1286                                 }
1287                         }
1288                 }
1289         }
1290
1291         /* set advertise register */
1292         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1293         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1294         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1295                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1296                 return PHY_ERROR;
1297         }
1298
1299         /* get phy interface type */
1300         phyinterface = readl(base + NvRegPhyInterface);
1301
1302         /* see if gigabit phy */
1303         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1304         if (mii_status & PHY_GIGABIT) {
1305                 np->gigabit = PHY_GIGABIT;
1306                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1307                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1308                 if (phyinterface & PHY_RGMII)
1309                         mii_control_1000 |= ADVERTISE_1000FULL;
1310                 else
1311                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1312
1313                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1314                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1315                         return PHY_ERROR;
1316                 }
1317         }
1318         else
1319                 np->gigabit = 0;
1320
1321         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1322         mii_control |= BMCR_ANENABLE;
1323
1324         if (np->phy_oui == PHY_OUI_REALTEK &&
1325             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1326             np->phy_rev == PHY_REV_REALTEK_8211C) {
1327                 /* start autoneg since we already performed hw reset above */
1328                 mii_control |= BMCR_ANRESTART;
1329                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1330                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1331                         return PHY_ERROR;
1332                 }
1333         } else {
1334                 /* reset the phy
1335                  * (certain phys need bmcr to be setup with reset)
1336                  */
1337                 if (phy_reset(dev, mii_control)) {
1338                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1339                         return PHY_ERROR;
1340                 }
1341         }
1342
1343         /* phy vendor specific configuration */
1344         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1345                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1346                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1347                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1348                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1349                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1350                         return PHY_ERROR;
1351                 }
1352                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1353                 phy_reserved |= PHY_CICADA_INIT5;
1354                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1355                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1356                         return PHY_ERROR;
1357                 }
1358         }
1359         if (np->phy_oui == PHY_OUI_CICADA) {
1360                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1361                 phy_reserved |= PHY_CICADA_INIT6;
1362                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1363                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1364                         return PHY_ERROR;
1365                 }
1366         }
1367         if (np->phy_oui == PHY_OUI_VITESSE) {
1368                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1369                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1370                         return PHY_ERROR;
1371                 }
1372                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1373                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1374                         return PHY_ERROR;
1375                 }
1376                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1377                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1378                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1379                         return PHY_ERROR;
1380                 }
1381                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1382                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1383                 phy_reserved |= PHY_VITESSE_INIT3;
1384                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1385                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1386                         return PHY_ERROR;
1387                 }
1388                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1389                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1390                         return PHY_ERROR;
1391                 }
1392                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1393                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1394                         return PHY_ERROR;
1395                 }
1396                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1397                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1398                 phy_reserved |= PHY_VITESSE_INIT3;
1399                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1400                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1401                         return PHY_ERROR;
1402                 }
1403                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1404                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1405                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1406                         return PHY_ERROR;
1407                 }
1408                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1409                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1410                         return PHY_ERROR;
1411                 }
1412                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1413                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1414                         return PHY_ERROR;
1415                 }
1416                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1417                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1418                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1419                         return PHY_ERROR;
1420                 }
1421                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1422                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1423                 phy_reserved |= PHY_VITESSE_INIT8;
1424                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1425                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1426                         return PHY_ERROR;
1427                 }
1428                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1429                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1430                         return PHY_ERROR;
1431                 }
1432                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1433                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1434                         return PHY_ERROR;
1435                 }
1436         }
1437         if (np->phy_oui == PHY_OUI_REALTEK) {
1438                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1439                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1440                         /* reset could have cleared these out, set them back */
1441                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1442                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1443                                 return PHY_ERROR;
1444                         }
1445                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1446                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1447                                 return PHY_ERROR;
1448                         }
1449                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1450                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1451                                 return PHY_ERROR;
1452                         }
1453                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1454                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1455                                 return PHY_ERROR;
1456                         }
1457                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1458                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1459                                 return PHY_ERROR;
1460                         }
1461                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1462                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1463                                 return PHY_ERROR;
1464                         }
1465                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1466                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1467                                 return PHY_ERROR;
1468                         }
1469                 }
1470                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1471                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1472                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1473                                 phy_reserved |= PHY_REALTEK_INIT7;
1474                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1475                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1476                                         return PHY_ERROR;
1477                                 }
1478                         }
1479                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1480                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1481                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1482                                         return PHY_ERROR;
1483                                 }
1484                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1485                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1486                                 phy_reserved |= PHY_REALTEK_INIT3;
1487                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1488                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1489                                         return PHY_ERROR;
1490                                 }
1491                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1492                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1493                                         return PHY_ERROR;
1494                                 }
1495                         }
1496                 }
1497         }
1498
1499         /* some phys clear out pause advertisment on reset, set it back */
1500         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1501
1502         /* restart auto negotiation, power down phy */
1503         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1504         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1505         if (phy_power_down) {
1506                 mii_control |= BMCR_PDOWN;
1507         }
1508         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1509                 return PHY_ERROR;
1510         }
1511
1512         return 0;
1513 }
1514
1515 static void nv_start_rx(struct net_device *dev)
1516 {
1517         struct fe_priv *np = netdev_priv(dev);
1518         u8 __iomem *base = get_hwbase(dev);
1519         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1520
1521         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1522         /* Already running? Stop it. */
1523         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1524                 rx_ctrl &= ~NVREG_RCVCTL_START;
1525                 writel(rx_ctrl, base + NvRegReceiverControl);
1526                 pci_push(base);
1527         }
1528         writel(np->linkspeed, base + NvRegLinkSpeed);
1529         pci_push(base);
1530         rx_ctrl |= NVREG_RCVCTL_START;
1531         if (np->mac_in_use)
1532                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1533         writel(rx_ctrl, base + NvRegReceiverControl);
1534         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1535                                 dev->name, np->duplex, np->linkspeed);
1536         pci_push(base);
1537 }
1538
1539 static void nv_stop_rx(struct net_device *dev)
1540 {
1541         struct fe_priv *np = netdev_priv(dev);
1542         u8 __iomem *base = get_hwbase(dev);
1543         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1544
1545         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1546         if (!np->mac_in_use)
1547                 rx_ctrl &= ~NVREG_RCVCTL_START;
1548         else
1549                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1550         writel(rx_ctrl, base + NvRegReceiverControl);
1551         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1552                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1553                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1554
1555         udelay(NV_RXSTOP_DELAY2);
1556         if (!np->mac_in_use)
1557                 writel(0, base + NvRegLinkSpeed);
1558 }
1559
1560 static void nv_start_tx(struct net_device *dev)
1561 {
1562         struct fe_priv *np = netdev_priv(dev);
1563         u8 __iomem *base = get_hwbase(dev);
1564         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1565
1566         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1567         tx_ctrl |= NVREG_XMITCTL_START;
1568         if (np->mac_in_use)
1569                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1570         writel(tx_ctrl, base + NvRegTransmitterControl);
1571         pci_push(base);
1572 }
1573
1574 static void nv_stop_tx(struct net_device *dev)
1575 {
1576         struct fe_priv *np = netdev_priv(dev);
1577         u8 __iomem *base = get_hwbase(dev);
1578         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579
1580         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1581         if (!np->mac_in_use)
1582                 tx_ctrl &= ~NVREG_XMITCTL_START;
1583         else
1584                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1585         writel(tx_ctrl, base + NvRegTransmitterControl);
1586         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1587                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1588                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1589
1590         udelay(NV_TXSTOP_DELAY2);
1591         if (!np->mac_in_use)
1592                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1593                        base + NvRegTransmitPoll);
1594 }
1595
1596 static void nv_start_rxtx(struct net_device *dev)
1597 {
1598         nv_start_rx(dev);
1599         nv_start_tx(dev);
1600 }
1601
1602 static void nv_stop_rxtx(struct net_device *dev)
1603 {
1604         nv_stop_rx(dev);
1605         nv_stop_tx(dev);
1606 }
1607
1608 static void nv_txrx_reset(struct net_device *dev)
1609 {
1610         struct fe_priv *np = netdev_priv(dev);
1611         u8 __iomem *base = get_hwbase(dev);
1612
1613         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1614         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1615         pci_push(base);
1616         udelay(NV_TXRX_RESET_DELAY);
1617         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1618         pci_push(base);
1619 }
1620
1621 static void nv_mac_reset(struct net_device *dev)
1622 {
1623         struct fe_priv *np = netdev_priv(dev);
1624         u8 __iomem *base = get_hwbase(dev);
1625         u32 temp1, temp2, temp3;
1626
1627         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1628
1629         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1630         pci_push(base);
1631
1632         /* save registers since they will be cleared on reset */
1633         temp1 = readl(base + NvRegMacAddrA);
1634         temp2 = readl(base + NvRegMacAddrB);
1635         temp3 = readl(base + NvRegTransmitPoll);
1636
1637         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1638         pci_push(base);
1639         udelay(NV_MAC_RESET_DELAY);
1640         writel(0, base + NvRegMacReset);
1641         pci_push(base);
1642         udelay(NV_MAC_RESET_DELAY);
1643
1644         /* restore saved registers */
1645         writel(temp1, base + NvRegMacAddrA);
1646         writel(temp2, base + NvRegMacAddrB);
1647         writel(temp3, base + NvRegTransmitPoll);
1648
1649         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1650         pci_push(base);
1651 }
1652
1653 static void nv_get_hw_stats(struct net_device *dev)
1654 {
1655         struct fe_priv *np = netdev_priv(dev);
1656         u8 __iomem *base = get_hwbase(dev);
1657
1658         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1659         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1660         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1661         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1662         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1663         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1664         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1665         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1666         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1667         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1668         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1669         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1670         np->estats.rx_runt += readl(base + NvRegRxRunt);
1671         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1672         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1673         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1674         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1675         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1676         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1677         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1678         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1679         np->estats.rx_packets =
1680                 np->estats.rx_unicast +
1681                 np->estats.rx_multicast +
1682                 np->estats.rx_broadcast;
1683         np->estats.rx_errors_total =
1684                 np->estats.rx_crc_errors +
1685                 np->estats.rx_over_errors +
1686                 np->estats.rx_frame_error +
1687                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1688                 np->estats.rx_late_collision +
1689                 np->estats.rx_runt +
1690                 np->estats.rx_frame_too_long;
1691         np->estats.tx_errors_total =
1692                 np->estats.tx_late_collision +
1693                 np->estats.tx_fifo_errors +
1694                 np->estats.tx_carrier_errors +
1695                 np->estats.tx_excess_deferral +
1696                 np->estats.tx_retry_error;
1697
1698         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1699                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1700                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1701                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1702                 np->estats.tx_pause += readl(base + NvRegTxPause);
1703                 np->estats.rx_pause += readl(base + NvRegRxPause);
1704                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1705         }
1706
1707         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1708                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1709                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1710                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1711         }
1712 }
1713
1714 /*
1715  * nv_get_stats: dev->get_stats function
1716  * Get latest stats value from the nic.
1717  * Called with read_lock(&dev_base_lock) held for read -
1718  * only synchronized against unregister_netdevice.
1719  */
1720 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1721 {
1722         struct fe_priv *np = netdev_priv(dev);
1723
1724         /* If the nic supports hw counters then retrieve latest values */
1725         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1726                 nv_get_hw_stats(dev);
1727
1728                 /* copy to net_device stats */
1729                 dev->stats.tx_bytes = np->estats.tx_bytes;
1730                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1731                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1732                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1733                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1734                 dev->stats.rx_errors = np->estats.rx_errors_total;
1735                 dev->stats.tx_errors = np->estats.tx_errors_total;
1736         }
1737
1738         return &dev->stats;
1739 }
1740
1741 /*
1742  * nv_alloc_rx: fill rx ring entries.
1743  * Return 1 if the allocations for the skbs failed and the
1744  * rx engine is without Available descriptors
1745  */
1746 static int nv_alloc_rx(struct net_device *dev)
1747 {
1748         struct fe_priv *np = netdev_priv(dev);
1749         struct ring_desc* less_rx;
1750
1751         less_rx = np->get_rx.orig;
1752         if (less_rx-- == np->first_rx.orig)
1753                 less_rx = np->last_rx.orig;
1754
1755         while (np->put_rx.orig != less_rx) {
1756                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1757                 if (skb) {
1758                         np->put_rx_ctx->skb = skb;
1759                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1760                                                              skb->data,
1761                                                              skb_tailroom(skb),
1762                                                              PCI_DMA_FROMDEVICE);
1763                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1764                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1765                         wmb();
1766                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1767                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1768                                 np->put_rx.orig = np->first_rx.orig;
1769                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1770                                 np->put_rx_ctx = np->first_rx_ctx;
1771                 } else {
1772                         return 1;
1773                 }
1774         }
1775         return 0;
1776 }
1777
1778 static int nv_alloc_rx_optimized(struct net_device *dev)
1779 {
1780         struct fe_priv *np = netdev_priv(dev);
1781         struct ring_desc_ex* less_rx;
1782
1783         less_rx = np->get_rx.ex;
1784         if (less_rx-- == np->first_rx.ex)
1785                 less_rx = np->last_rx.ex;
1786
1787         while (np->put_rx.ex != less_rx) {
1788                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1789                 if (skb) {
1790                         np->put_rx_ctx->skb = skb;
1791                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1792                                                              skb->data,
1793                                                              skb_tailroom(skb),
1794                                                              PCI_DMA_FROMDEVICE);
1795                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1796                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1797                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1798                         wmb();
1799                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1800                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1801                                 np->put_rx.ex = np->first_rx.ex;
1802                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1803                                 np->put_rx_ctx = np->first_rx_ctx;
1804                 } else {
1805                         return 1;
1806                 }
1807         }
1808         return 0;
1809 }
1810
1811 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1812 #ifdef CONFIG_FORCEDETH_NAPI
1813 static void nv_do_rx_refill(unsigned long data)
1814 {
1815         struct net_device *dev = (struct net_device *) data;
1816         struct fe_priv *np = netdev_priv(dev);
1817
1818         /* Just reschedule NAPI rx processing */
1819         napi_schedule(&np->napi);
1820 }
1821 #else
1822 static void nv_do_rx_refill(unsigned long data)
1823 {
1824         struct net_device *dev = (struct net_device *) data;
1825         struct fe_priv *np = netdev_priv(dev);
1826         int retcode;
1827
1828         if (!using_multi_irqs(dev)) {
1829                 if (np->msi_flags & NV_MSI_X_ENABLED)
1830                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1831                 else
1832                         disable_irq(np->pci_dev->irq);
1833         } else {
1834                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1835         }
1836         if (!nv_optimized(np))
1837                 retcode = nv_alloc_rx(dev);
1838         else
1839                 retcode = nv_alloc_rx_optimized(dev);
1840         if (retcode) {
1841                 spin_lock_irq(&np->lock);
1842                 if (!np->in_shutdown)
1843                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1844                 spin_unlock_irq(&np->lock);
1845         }
1846         if (!using_multi_irqs(dev)) {
1847                 if (np->msi_flags & NV_MSI_X_ENABLED)
1848                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1849                 else
1850                         enable_irq(np->pci_dev->irq);
1851         } else {
1852                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1853         }
1854 }
1855 #endif
1856
1857 static void nv_init_rx(struct net_device *dev)
1858 {
1859         struct fe_priv *np = netdev_priv(dev);
1860         int i;
1861
1862         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1863
1864         if (!nv_optimized(np))
1865                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1866         else
1867                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1868         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1869         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1870
1871         for (i = 0; i < np->rx_ring_size; i++) {
1872                 if (!nv_optimized(np)) {
1873                         np->rx_ring.orig[i].flaglen = 0;
1874                         np->rx_ring.orig[i].buf = 0;
1875                 } else {
1876                         np->rx_ring.ex[i].flaglen = 0;
1877                         np->rx_ring.ex[i].txvlan = 0;
1878                         np->rx_ring.ex[i].bufhigh = 0;
1879                         np->rx_ring.ex[i].buflow = 0;
1880                 }
1881                 np->rx_skb[i].skb = NULL;
1882                 np->rx_skb[i].dma = 0;
1883         }
1884 }
1885
1886 static void nv_init_tx(struct net_device *dev)
1887 {
1888         struct fe_priv *np = netdev_priv(dev);
1889         int i;
1890
1891         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1892
1893         if (!nv_optimized(np))
1894                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1895         else
1896                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1897         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1898         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1899         np->tx_pkts_in_progress = 0;
1900         np->tx_change_owner = NULL;
1901         np->tx_end_flip = NULL;
1902         np->tx_stop = 0;
1903
1904         for (i = 0; i < np->tx_ring_size; i++) {
1905                 if (!nv_optimized(np)) {
1906                         np->tx_ring.orig[i].flaglen = 0;
1907                         np->tx_ring.orig[i].buf = 0;
1908                 } else {
1909                         np->tx_ring.ex[i].flaglen = 0;
1910                         np->tx_ring.ex[i].txvlan = 0;
1911                         np->tx_ring.ex[i].bufhigh = 0;
1912                         np->tx_ring.ex[i].buflow = 0;
1913                 }
1914                 np->tx_skb[i].skb = NULL;
1915                 np->tx_skb[i].dma = 0;
1916                 np->tx_skb[i].dma_len = 0;
1917                 np->tx_skb[i].dma_single = 0;
1918                 np->tx_skb[i].first_tx_desc = NULL;
1919                 np->tx_skb[i].next_tx_ctx = NULL;
1920         }
1921 }
1922
1923 static int nv_init_ring(struct net_device *dev)
1924 {
1925         struct fe_priv *np = netdev_priv(dev);
1926
1927         nv_init_tx(dev);
1928         nv_init_rx(dev);
1929
1930         if (!nv_optimized(np))
1931                 return nv_alloc_rx(dev);
1932         else
1933                 return nv_alloc_rx_optimized(dev);
1934 }
1935
1936 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1937 {
1938         if (tx_skb->dma) {
1939                 if (tx_skb->dma_single)
1940                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1941                                          tx_skb->dma_len,
1942                                          PCI_DMA_TODEVICE);
1943                 else
1944                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1945                                        tx_skb->dma_len,
1946                                        PCI_DMA_TODEVICE);
1947                 tx_skb->dma = 0;
1948         }
1949 }
1950
1951 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1952 {
1953         nv_unmap_txskb(np, tx_skb);
1954         if (tx_skb->skb) {
1955                 dev_kfree_skb_any(tx_skb->skb);
1956                 tx_skb->skb = NULL;
1957                 return 1;
1958         }
1959         return 0;
1960 }
1961
1962 static void nv_drain_tx(struct net_device *dev)
1963 {
1964         struct fe_priv *np = netdev_priv(dev);
1965         unsigned int i;
1966
1967         for (i = 0; i < np->tx_ring_size; i++) {
1968                 if (!nv_optimized(np)) {
1969                         np->tx_ring.orig[i].flaglen = 0;
1970                         np->tx_ring.orig[i].buf = 0;
1971                 } else {
1972                         np->tx_ring.ex[i].flaglen = 0;
1973                         np->tx_ring.ex[i].txvlan = 0;
1974                         np->tx_ring.ex[i].bufhigh = 0;
1975                         np->tx_ring.ex[i].buflow = 0;
1976                 }
1977                 if (nv_release_txskb(np, &np->tx_skb[i]))
1978                         dev->stats.tx_dropped++;
1979                 np->tx_skb[i].dma = 0;
1980                 np->tx_skb[i].dma_len = 0;
1981                 np->tx_skb[i].dma_single = 0;
1982                 np->tx_skb[i].first_tx_desc = NULL;
1983                 np->tx_skb[i].next_tx_ctx = NULL;
1984         }
1985         np->tx_pkts_in_progress = 0;
1986         np->tx_change_owner = NULL;
1987         np->tx_end_flip = NULL;
1988 }
1989
1990 static void nv_drain_rx(struct net_device *dev)
1991 {
1992         struct fe_priv *np = netdev_priv(dev);
1993         int i;
1994
1995         for (i = 0; i < np->rx_ring_size; i++) {
1996                 if (!nv_optimized(np)) {
1997                         np->rx_ring.orig[i].flaglen = 0;
1998                         np->rx_ring.orig[i].buf = 0;
1999                 } else {
2000                         np->rx_ring.ex[i].flaglen = 0;
2001                         np->rx_ring.ex[i].txvlan = 0;
2002                         np->rx_ring.ex[i].bufhigh = 0;
2003                         np->rx_ring.ex[i].buflow = 0;
2004                 }
2005                 wmb();
2006                 if (np->rx_skb[i].skb) {
2007                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2008                                          (skb_end_pointer(np->rx_skb[i].skb) -
2009                                           np->rx_skb[i].skb->data),
2010                                          PCI_DMA_FROMDEVICE);
2011                         dev_kfree_skb(np->rx_skb[i].skb);
2012                         np->rx_skb[i].skb = NULL;
2013                 }
2014         }
2015 }
2016
2017 static void nv_drain_rxtx(struct net_device *dev)
2018 {
2019         nv_drain_tx(dev);
2020         nv_drain_rx(dev);
2021 }
2022
2023 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2024 {
2025         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2026 }
2027
2028 static void nv_legacybackoff_reseed(struct net_device *dev)
2029 {
2030         u8 __iomem *base = get_hwbase(dev);
2031         u32 reg;
2032         u32 low;
2033         int tx_status = 0;
2034
2035         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2036         get_random_bytes(&low, sizeof(low));
2037         reg |= low & NVREG_SLOTTIME_MASK;
2038
2039         /* Need to stop tx before change takes effect.
2040          * Caller has already gained np->lock.
2041          */
2042         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2043         if (tx_status)
2044                 nv_stop_tx(dev);
2045         nv_stop_rx(dev);
2046         writel(reg, base + NvRegSlotTime);
2047         if (tx_status)
2048                 nv_start_tx(dev);
2049         nv_start_rx(dev);
2050 }
2051
2052 /* Gear Backoff Seeds */
2053 #define BACKOFF_SEEDSET_ROWS    8
2054 #define BACKOFF_SEEDSET_LFSRS   15
2055
2056 /* Known Good seed sets */
2057 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2058     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2059     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2060     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2061     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2062     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2063     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2064     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2065     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2066
2067 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2068     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2069     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2070     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2071     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2072     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2073     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2074     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2075     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2076
2077 static void nv_gear_backoff_reseed(struct net_device *dev)
2078 {
2079         u8 __iomem *base = get_hwbase(dev);
2080         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2081         u32 temp, seedset, combinedSeed;
2082         int i;
2083
2084         /* Setup seed for free running LFSR */
2085         /* We are going to read the time stamp counter 3 times
2086            and swizzle bits around to increase randomness */
2087         get_random_bytes(&miniseed1, sizeof(miniseed1));
2088         miniseed1 &= 0x0fff;
2089         if (miniseed1 == 0)
2090                 miniseed1 = 0xabc;
2091
2092         get_random_bytes(&miniseed2, sizeof(miniseed2));
2093         miniseed2 &= 0x0fff;
2094         if (miniseed2 == 0)
2095                 miniseed2 = 0xabc;
2096         miniseed2_reversed =
2097                 ((miniseed2 & 0xF00) >> 8) |
2098                  (miniseed2 & 0x0F0) |
2099                  ((miniseed2 & 0x00F) << 8);
2100
2101         get_random_bytes(&miniseed3, sizeof(miniseed3));
2102         miniseed3 &= 0x0fff;
2103         if (miniseed3 == 0)
2104                 miniseed3 = 0xabc;
2105         miniseed3_reversed =
2106                 ((miniseed3 & 0xF00) >> 8) |
2107                  (miniseed3 & 0x0F0) |
2108                  ((miniseed3 & 0x00F) << 8);
2109
2110         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2111                        (miniseed2 ^ miniseed3_reversed);
2112
2113         /* Seeds can not be zero */
2114         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2115                 combinedSeed |= 0x08;
2116         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2117                 combinedSeed |= 0x8000;
2118
2119         /* No need to disable tx here */
2120         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2121         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2122         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2123         writel(temp,base + NvRegBackOffControl);
2124
2125         /* Setup seeds for all gear LFSRs. */
2126         get_random_bytes(&seedset, sizeof(seedset));
2127         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2128         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2129         {
2130                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2131                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2132                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2133                 writel(temp, base + NvRegBackOffControl);
2134         }
2135 }
2136
2137 /*
2138  * nv_start_xmit: dev->hard_start_xmit function
2139  * Called with netif_tx_lock held.
2140  */
2141 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2142 {
2143         struct fe_priv *np = netdev_priv(dev);
2144         u32 tx_flags = 0;
2145         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2146         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2147         unsigned int i;
2148         u32 offset = 0;
2149         u32 bcnt;
2150         u32 size = skb->len-skb->data_len;
2151         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2152         u32 empty_slots;
2153         struct ring_desc* put_tx;
2154         struct ring_desc* start_tx;
2155         struct ring_desc* prev_tx;
2156         struct nv_skb_map* prev_tx_ctx;
2157         unsigned long flags;
2158
2159         /* add fragments to entries count */
2160         for (i = 0; i < fragments; i++) {
2161                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2162                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2163         }
2164
2165         spin_lock_irqsave(&np->lock, flags);
2166         empty_slots = nv_get_empty_tx_slots(np);
2167         if (unlikely(empty_slots <= entries)) {
2168                 netif_stop_queue(dev);
2169                 np->tx_stop = 1;
2170                 spin_unlock_irqrestore(&np->lock, flags);
2171                 return NETDEV_TX_BUSY;
2172         }
2173         spin_unlock_irqrestore(&np->lock, flags);
2174
2175         start_tx = put_tx = np->put_tx.orig;
2176
2177         /* setup the header buffer */
2178         do {
2179                 prev_tx = put_tx;
2180                 prev_tx_ctx = np->put_tx_ctx;
2181                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2182                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2183                                                 PCI_DMA_TODEVICE);
2184                 np->put_tx_ctx->dma_len = bcnt;
2185                 np->put_tx_ctx->dma_single = 1;
2186                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2187                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2188
2189                 tx_flags = np->tx_flags;
2190                 offset += bcnt;
2191                 size -= bcnt;
2192                 if (unlikely(put_tx++ == np->last_tx.orig))
2193                         put_tx = np->first_tx.orig;
2194                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2195                         np->put_tx_ctx = np->first_tx_ctx;
2196         } while (size);
2197
2198         /* setup the fragments */
2199         for (i = 0; i < fragments; i++) {
2200                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2201                 u32 size = frag->size;
2202                 offset = 0;
2203
2204                 do {
2205                         prev_tx = put_tx;
2206                         prev_tx_ctx = np->put_tx_ctx;
2207                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2208                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2209                                                            PCI_DMA_TODEVICE);
2210                         np->put_tx_ctx->dma_len = bcnt;
2211                         np->put_tx_ctx->dma_single = 0;
2212                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2213                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2214
2215                         offset += bcnt;
2216                         size -= bcnt;
2217                         if (unlikely(put_tx++ == np->last_tx.orig))
2218                                 put_tx = np->first_tx.orig;
2219                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2220                                 np->put_tx_ctx = np->first_tx_ctx;
2221                 } while (size);
2222         }
2223
2224         /* set last fragment flag  */
2225         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2226
2227         /* save skb in this slot's context area */
2228         prev_tx_ctx->skb = skb;
2229
2230         if (skb_is_gso(skb))
2231                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2232         else
2233                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2234                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2235
2236         spin_lock_irqsave(&np->lock, flags);
2237
2238         /* set tx flags */
2239         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2240         np->put_tx.orig = put_tx;
2241
2242         spin_unlock_irqrestore(&np->lock, flags);
2243
2244         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2245                 dev->name, entries, tx_flags_extra);
2246         {
2247                 int j;
2248                 for (j=0; j<64; j++) {
2249                         if ((j%16) == 0)
2250                                 dprintk("\n%03x:", j);
2251                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2252                 }
2253                 dprintk("\n");
2254         }
2255
2256         dev->trans_start = jiffies;
2257         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2258         return NETDEV_TX_OK;
2259 }
2260
2261 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2262                                            struct net_device *dev)
2263 {
2264         struct fe_priv *np = netdev_priv(dev);
2265         u32 tx_flags = 0;
2266         u32 tx_flags_extra;
2267         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2268         unsigned int i;
2269         u32 offset = 0;
2270         u32 bcnt;
2271         u32 size = skb->len-skb->data_len;
2272         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2273         u32 empty_slots;
2274         struct ring_desc_ex* put_tx;
2275         struct ring_desc_ex* start_tx;
2276         struct ring_desc_ex* prev_tx;
2277         struct nv_skb_map* prev_tx_ctx;
2278         struct nv_skb_map* start_tx_ctx;
2279         unsigned long flags;
2280
2281         /* add fragments to entries count */
2282         for (i = 0; i < fragments; i++) {
2283                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2284                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2285         }
2286
2287         spin_lock_irqsave(&np->lock, flags);
2288         empty_slots = nv_get_empty_tx_slots(np);
2289         if (unlikely(empty_slots <= entries)) {
2290                 netif_stop_queue(dev);
2291                 np->tx_stop = 1;
2292                 spin_unlock_irqrestore(&np->lock, flags);
2293                 return NETDEV_TX_BUSY;
2294         }
2295         spin_unlock_irqrestore(&np->lock, flags);
2296
2297         start_tx = put_tx = np->put_tx.ex;
2298         start_tx_ctx = np->put_tx_ctx;
2299
2300         /* setup the header buffer */
2301         do {
2302                 prev_tx = put_tx;
2303                 prev_tx_ctx = np->put_tx_ctx;
2304                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2305                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2306                                                 PCI_DMA_TODEVICE);
2307                 np->put_tx_ctx->dma_len = bcnt;
2308                 np->put_tx_ctx->dma_single = 1;
2309                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2310                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2311                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2312
2313                 tx_flags = NV_TX2_VALID;
2314                 offset += bcnt;
2315                 size -= bcnt;
2316                 if (unlikely(put_tx++ == np->last_tx.ex))
2317                         put_tx = np->first_tx.ex;
2318                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2319                         np->put_tx_ctx = np->first_tx_ctx;
2320         } while (size);
2321
2322         /* setup the fragments */
2323         for (i = 0; i < fragments; i++) {
2324                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2325                 u32 size = frag->size;
2326                 offset = 0;
2327
2328                 do {
2329                         prev_tx = put_tx;
2330                         prev_tx_ctx = np->put_tx_ctx;
2331                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2332                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2333                                                            PCI_DMA_TODEVICE);
2334                         np->put_tx_ctx->dma_len = bcnt;
2335                         np->put_tx_ctx->dma_single = 0;
2336                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2337                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2338                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2339
2340                         offset += bcnt;
2341                         size -= bcnt;
2342                         if (unlikely(put_tx++ == np->last_tx.ex))
2343                                 put_tx = np->first_tx.ex;
2344                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2345                                 np->put_tx_ctx = np->first_tx_ctx;
2346                 } while (size);
2347         }
2348
2349         /* set last fragment flag  */
2350         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2351
2352         /* save skb in this slot's context area */
2353         prev_tx_ctx->skb = skb;
2354
2355         if (skb_is_gso(skb))
2356                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2357         else
2358                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2359                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2360
2361         /* vlan tag */
2362         if (likely(!np->vlangrp)) {
2363                 start_tx->txvlan = 0;
2364         } else {
2365                 if (vlan_tx_tag_present(skb))
2366                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2367                 else
2368                         start_tx->txvlan = 0;
2369         }
2370
2371         spin_lock_irqsave(&np->lock, flags);
2372
2373         if (np->tx_limit) {
2374                 /* Limit the number of outstanding tx. Setup all fragments, but
2375                  * do not set the VALID bit on the first descriptor. Save a pointer
2376                  * to that descriptor and also for next skb_map element.
2377                  */
2378
2379                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2380                         if (!np->tx_change_owner)
2381                                 np->tx_change_owner = start_tx_ctx;
2382
2383                         /* remove VALID bit */
2384                         tx_flags &= ~NV_TX2_VALID;
2385                         start_tx_ctx->first_tx_desc = start_tx;
2386                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2387                         np->tx_end_flip = np->put_tx_ctx;
2388                 } else {
2389                         np->tx_pkts_in_progress++;
2390                 }
2391         }
2392
2393         /* set tx flags */
2394         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2395         np->put_tx.ex = put_tx;
2396
2397         spin_unlock_irqrestore(&np->lock, flags);
2398
2399         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2400                 dev->name, entries, tx_flags_extra);
2401         {
2402                 int j;
2403                 for (j=0; j<64; j++) {
2404                         if ((j%16) == 0)
2405                                 dprintk("\n%03x:", j);
2406                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2407                 }
2408                 dprintk("\n");
2409         }
2410
2411         dev->trans_start = jiffies;
2412         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2413         return NETDEV_TX_OK;
2414 }
2415
2416 static inline void nv_tx_flip_ownership(struct net_device *dev)
2417 {
2418         struct fe_priv *np = netdev_priv(dev);
2419
2420         np->tx_pkts_in_progress--;
2421         if (np->tx_change_owner) {
2422                 np->tx_change_owner->first_tx_desc->flaglen |=
2423                         cpu_to_le32(NV_TX2_VALID);
2424                 np->tx_pkts_in_progress++;
2425
2426                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2427                 if (np->tx_change_owner == np->tx_end_flip)
2428                         np->tx_change_owner = NULL;
2429
2430                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2431         }
2432 }
2433
2434 /*
2435  * nv_tx_done: check for completed packets, release the skbs.
2436  *
2437  * Caller must own np->lock.
2438  */
2439 static int nv_tx_done(struct net_device *dev, int limit)
2440 {
2441         struct fe_priv *np = netdev_priv(dev);
2442         u32 flags;
2443         int tx_work = 0;
2444         struct ring_desc* orig_get_tx = np->get_tx.orig;
2445
2446         while ((np->get_tx.orig != np->put_tx.orig) &&
2447                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2448                (tx_work < limit)) {
2449
2450                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2451                                         dev->name, flags);
2452
2453                 nv_unmap_txskb(np, np->get_tx_ctx);
2454
2455                 if (np->desc_ver == DESC_VER_1) {
2456                         if (flags & NV_TX_LASTPACKET) {
2457                                 if (flags & NV_TX_ERROR) {
2458                                         if (flags & NV_TX_UNDERFLOW)
2459                                                 dev->stats.tx_fifo_errors++;
2460                                         if (flags & NV_TX_CARRIERLOST)
2461                                                 dev->stats.tx_carrier_errors++;
2462                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2463                                                 nv_legacybackoff_reseed(dev);
2464                                         dev->stats.tx_errors++;
2465                                 } else {
2466                                         dev->stats.tx_packets++;
2467                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2468                                 }
2469                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2470                                 np->get_tx_ctx->skb = NULL;
2471                                 tx_work++;
2472                         }
2473                 } else {
2474                         if (flags & NV_TX2_LASTPACKET) {
2475                                 if (flags & NV_TX2_ERROR) {
2476                                         if (flags & NV_TX2_UNDERFLOW)
2477                                                 dev->stats.tx_fifo_errors++;
2478                                         if (flags & NV_TX2_CARRIERLOST)
2479                                                 dev->stats.tx_carrier_errors++;
2480                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2481                                                 nv_legacybackoff_reseed(dev);
2482                                         dev->stats.tx_errors++;
2483                                 } else {
2484                                         dev->stats.tx_packets++;
2485                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2486                                 }
2487                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2488                                 np->get_tx_ctx->skb = NULL;
2489                                 tx_work++;
2490                         }
2491                 }
2492                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2493                         np->get_tx.orig = np->first_tx.orig;
2494                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2495                         np->get_tx_ctx = np->first_tx_ctx;
2496         }
2497         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2498                 np->tx_stop = 0;
2499                 netif_wake_queue(dev);
2500         }
2501         return tx_work;
2502 }
2503
2504 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2505 {
2506         struct fe_priv *np = netdev_priv(dev);
2507         u32 flags;
2508         int tx_work = 0;
2509         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2510
2511         while ((np->get_tx.ex != np->put_tx.ex) &&
2512                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2513                (tx_work < limit)) {
2514
2515                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2516                                         dev->name, flags);
2517
2518                 nv_unmap_txskb(np, np->get_tx_ctx);
2519
2520                 if (flags & NV_TX2_LASTPACKET) {
2521                         if (!(flags & NV_TX2_ERROR))
2522                                 dev->stats.tx_packets++;
2523                         else {
2524                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2525                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2526                                                 nv_gear_backoff_reseed(dev);
2527                                         else
2528                                                 nv_legacybackoff_reseed(dev);
2529                                 }
2530                         }
2531
2532                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2533                         np->get_tx_ctx->skb = NULL;
2534                         tx_work++;
2535
2536                         if (np->tx_limit) {
2537                                 nv_tx_flip_ownership(dev);
2538                         }
2539                 }
2540                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2541                         np->get_tx.ex = np->first_tx.ex;
2542                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2543                         np->get_tx_ctx = np->first_tx_ctx;
2544         }
2545         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2546                 np->tx_stop = 0;
2547                 netif_wake_queue(dev);
2548         }
2549         return tx_work;
2550 }
2551
2552 /*
2553  * nv_tx_timeout: dev->tx_timeout function
2554  * Called with netif_tx_lock held.
2555  */
2556 static void nv_tx_timeout(struct net_device *dev)
2557 {
2558         struct fe_priv *np = netdev_priv(dev);
2559         u8 __iomem *base = get_hwbase(dev);
2560         u32 status;
2561         union ring_type put_tx;
2562         int saved_tx_limit;
2563
2564         if (np->msi_flags & NV_MSI_X_ENABLED)
2565                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2566         else
2567                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2568
2569         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2570
2571         {
2572                 int i;
2573
2574                 printk(KERN_INFO "%s: Ring at %lx\n",
2575                        dev->name, (unsigned long)np->ring_addr);
2576                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2577                 for (i=0;i<=np->register_size;i+= 32) {
2578                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2579                                         i,
2580                                         readl(base + i + 0), readl(base + i + 4),
2581                                         readl(base + i + 8), readl(base + i + 12),
2582                                         readl(base + i + 16), readl(base + i + 20),
2583                                         readl(base + i + 24), readl(base + i + 28));
2584                 }
2585                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2586                 for (i=0;i<np->tx_ring_size;i+= 4) {
2587                         if (!nv_optimized(np)) {
2588                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2589                                        i,
2590                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2591                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2592                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2593                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2594                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2595                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2596                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2597                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2598                         } else {
2599                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2600                                        i,
2601                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2602                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2603                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2604                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2605                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2606                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2607                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2608                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2609                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2610                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2611                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2612                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2613                         }
2614                 }
2615         }
2616
2617         spin_lock_irq(&np->lock);
2618
2619         /* 1) stop tx engine */
2620         nv_stop_tx(dev);
2621
2622         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2623         saved_tx_limit = np->tx_limit;
2624         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2625         np->tx_stop = 0;  /* prevent waking tx queue */
2626         if (!nv_optimized(np))
2627                 nv_tx_done(dev, np->tx_ring_size);
2628         else
2629                 nv_tx_done_optimized(dev, np->tx_ring_size);
2630
2631         /* save current HW postion */
2632         if (np->tx_change_owner)
2633                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2634         else
2635                 put_tx = np->put_tx;
2636
2637         /* 3) clear all tx state */
2638         nv_drain_tx(dev);
2639         nv_init_tx(dev);
2640
2641         /* 4) restore state to current HW position */
2642         np->get_tx = np->put_tx = put_tx;
2643         np->tx_limit = saved_tx_limit;
2644
2645         /* 5) restart tx engine */
2646         nv_start_tx(dev);
2647         netif_wake_queue(dev);
2648         spin_unlock_irq(&np->lock);
2649 }
2650
2651 /*
2652  * Called when the nic notices a mismatch between the actual data len on the
2653  * wire and the len indicated in the 802 header
2654  */
2655 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2656 {
2657         int hdrlen;     /* length of the 802 header */
2658         int protolen;   /* length as stored in the proto field */
2659
2660         /* 1) calculate len according to header */
2661         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2662                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2663                 hdrlen = VLAN_HLEN;
2664         } else {
2665                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2666                 hdrlen = ETH_HLEN;
2667         }
2668         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2669                                 dev->name, datalen, protolen, hdrlen);
2670         if (protolen > ETH_DATA_LEN)
2671                 return datalen; /* Value in proto field not a len, no checks possible */
2672
2673         protolen += hdrlen;
2674         /* consistency checks: */
2675         if (datalen > ETH_ZLEN) {
2676                 if (datalen >= protolen) {
2677                         /* more data on wire than in 802 header, trim of
2678                          * additional data.
2679                          */
2680                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2681                                         dev->name, protolen);
2682                         return protolen;
2683                 } else {
2684                         /* less data on wire than mentioned in header.
2685                          * Discard the packet.
2686                          */
2687                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2688                                         dev->name);
2689                         return -1;
2690                 }
2691         } else {
2692                 /* short packet. Accept only if 802 values are also short */
2693                 if (protolen > ETH_ZLEN) {
2694                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2695                                         dev->name);
2696                         return -1;
2697                 }
2698                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2699                                 dev->name, datalen);
2700                 return datalen;
2701         }
2702 }
2703
2704 static int nv_rx_process(struct net_device *dev, int limit)
2705 {
2706         struct fe_priv *np = netdev_priv(dev);
2707         u32 flags;
2708         int rx_work = 0;
2709         struct sk_buff *skb;
2710         int len;
2711
2712         while((np->get_rx.orig != np->put_rx.orig) &&
2713               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2714                 (rx_work < limit)) {
2715
2716                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2717                                         dev->name, flags);
2718
2719                 /*
2720                  * the packet is for us - immediately tear down the pci mapping.
2721                  * TODO: check if a prefetch of the first cacheline improves
2722                  * the performance.
2723                  */
2724                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2725                                 np->get_rx_ctx->dma_len,
2726                                 PCI_DMA_FROMDEVICE);
2727                 skb = np->get_rx_ctx->skb;
2728                 np->get_rx_ctx->skb = NULL;
2729
2730                 {
2731                         int j;
2732                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2733                         for (j=0; j<64; j++) {
2734                                 if ((j%16) == 0)
2735                                         dprintk("\n%03x:", j);
2736                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2737                         }
2738                         dprintk("\n");
2739                 }
2740                 /* look at what we actually got: */
2741                 if (np->desc_ver == DESC_VER_1) {
2742                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2743                                 len = flags & LEN_MASK_V1;
2744                                 if (unlikely(flags & NV_RX_ERROR)) {
2745                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2746                                                 len = nv_getlen(dev, skb->data, len);
2747                                                 if (len < 0) {
2748                                                         dev->stats.rx_errors++;
2749                                                         dev_kfree_skb(skb);
2750                                                         goto next_pkt;
2751                                                 }
2752                                         }
2753                                         /* framing errors are soft errors */
2754                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2755                                                 if (flags & NV_RX_SUBSTRACT1) {
2756                                                         len--;
2757                                                 }
2758                                         }
2759                                         /* the rest are hard errors */
2760                                         else {
2761                                                 if (flags & NV_RX_MISSEDFRAME)
2762                                                         dev->stats.rx_missed_errors++;
2763                                                 if (flags & NV_RX_CRCERR)
2764                                                         dev->stats.rx_crc_errors++;
2765                                                 if (flags & NV_RX_OVERFLOW)
2766                                                         dev->stats.rx_over_errors++;
2767                                                 dev->stats.rx_errors++;
2768                                                 dev_kfree_skb(skb);
2769                                                 goto next_pkt;
2770                                         }
2771                                 }
2772                         } else {
2773                                 dev_kfree_skb(skb);
2774                                 goto next_pkt;
2775                         }
2776                 } else {
2777                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2778                                 len = flags & LEN_MASK_V2;
2779                                 if (unlikely(flags & NV_RX2_ERROR)) {
2780                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2781                                                 len = nv_getlen(dev, skb->data, len);
2782                                                 if (len < 0) {
2783                                                         dev->stats.rx_errors++;
2784                                                         dev_kfree_skb(skb);
2785                                                         goto next_pkt;
2786                                                 }
2787                                         }
2788                                         /* framing errors are soft errors */
2789                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2790                                                 if (flags & NV_RX2_SUBSTRACT1) {
2791                                                         len--;
2792                                                 }
2793                                         }
2794                                         /* the rest are hard errors */
2795                                         else {
2796                                                 if (flags & NV_RX2_CRCERR)
2797                                                         dev->stats.rx_crc_errors++;
2798                                                 if (flags & NV_RX2_OVERFLOW)
2799                                                         dev->stats.rx_over_errors++;
2800                                                 dev->stats.rx_errors++;
2801                                                 dev_kfree_skb(skb);
2802                                                 goto next_pkt;
2803                                         }
2804                                 }
2805                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2806                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2807                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2808                         } else {
2809                                 dev_kfree_skb(skb);
2810                                 goto next_pkt;
2811                         }
2812                 }
2813                 /* got a valid packet - forward it to the network core */
2814                 skb_put(skb, len);
2815                 skb->protocol = eth_type_trans(skb, dev);
2816                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2817                                         dev->name, len, skb->protocol);
2818 #ifdef CONFIG_FORCEDETH_NAPI
2819                 netif_receive_skb(skb);
2820 #else
2821                 netif_rx(skb);
2822 #endif
2823                 dev->stats.rx_packets++;
2824                 dev->stats.rx_bytes += len;
2825 next_pkt:
2826                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2827                         np->get_rx.orig = np->first_rx.orig;
2828                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2829                         np->get_rx_ctx = np->first_rx_ctx;
2830
2831                 rx_work++;
2832         }
2833
2834         return rx_work;
2835 }
2836
2837 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2838 {
2839         struct fe_priv *np = netdev_priv(dev);
2840         u32 flags;
2841         u32 vlanflags = 0;
2842         int rx_work = 0;
2843         struct sk_buff *skb;
2844         int len;
2845
2846         while((np->get_rx.ex != np->put_rx.ex) &&
2847               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2848               (rx_work < limit)) {
2849
2850                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2851                                         dev->name, flags);
2852
2853                 /*
2854                  * the packet is for us - immediately tear down the pci mapping.
2855                  * TODO: check if a prefetch of the first cacheline improves
2856                  * the performance.
2857                  */
2858                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2859                                 np->get_rx_ctx->dma_len,
2860                                 PCI_DMA_FROMDEVICE);
2861                 skb = np->get_rx_ctx->skb;
2862                 np->get_rx_ctx->skb = NULL;
2863
2864                 {
2865                         int j;
2866                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2867                         for (j=0; j<64; j++) {
2868                                 if ((j%16) == 0)
2869                                         dprintk("\n%03x:", j);
2870                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2871                         }
2872                         dprintk("\n");
2873                 }
2874                 /* look at what we actually got: */
2875                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2876                         len = flags & LEN_MASK_V2;
2877                         if (unlikely(flags & NV_RX2_ERROR)) {
2878                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2879                                         len = nv_getlen(dev, skb->data, len);
2880                                         if (len < 0) {
2881                                                 dev_kfree_skb(skb);
2882                                                 goto next_pkt;
2883                                         }
2884                                 }
2885                                 /* framing errors are soft errors */
2886                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2887                                         if (flags & NV_RX2_SUBSTRACT1) {
2888                                                 len--;
2889                                         }
2890                                 }
2891                                 /* the rest are hard errors */
2892                                 else {
2893                                         dev_kfree_skb(skb);
2894                                         goto next_pkt;
2895                                 }
2896                         }
2897
2898                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2899                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2900                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2901
2902                         /* got a valid packet - forward it to the network core */
2903                         skb_put(skb, len);
2904                         skb->protocol = eth_type_trans(skb, dev);
2905                         prefetch(skb->data);
2906
2907                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2908                                 dev->name, len, skb->protocol);
2909
2910                         if (likely(!np->vlangrp)) {
2911 #ifdef CONFIG_FORCEDETH_NAPI
2912                                 netif_receive_skb(skb);
2913 #else
2914                                 netif_rx(skb);
2915 #endif
2916                         } else {
2917                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2918                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2919 #ifdef CONFIG_FORCEDETH_NAPI
2920                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2921                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2922 #else
2923                                         vlan_hwaccel_rx(skb, np->vlangrp,
2924                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2925 #endif
2926                                 } else {
2927 #ifdef CONFIG_FORCEDETH_NAPI
2928                                         netif_receive_skb(skb);
2929 #else
2930                                         netif_rx(skb);
2931 #endif
2932                                 }
2933                         }
2934
2935                         dev->stats.rx_packets++;
2936                         dev->stats.rx_bytes += len;
2937                 } else {
2938                         dev_kfree_skb(skb);
2939                 }
2940 next_pkt:
2941                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2942                         np->get_rx.ex = np->first_rx.ex;
2943                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2944                         np->get_rx_ctx = np->first_rx_ctx;
2945
2946                 rx_work++;
2947         }
2948
2949         return rx_work;
2950 }
2951
2952 static void set_bufsize(struct net_device *dev)
2953 {
2954         struct fe_priv *np = netdev_priv(dev);
2955
2956         if (dev->mtu <= ETH_DATA_LEN)
2957                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2958         else
2959                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2960 }
2961
2962 /*
2963  * nv_change_mtu: dev->change_mtu function
2964  * Called with dev_base_lock held for read.
2965  */
2966 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2967 {
2968         struct fe_priv *np = netdev_priv(dev);
2969         int old_mtu;
2970
2971         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2972                 return -EINVAL;
2973
2974         old_mtu = dev->mtu;
2975         dev->mtu = new_mtu;
2976
2977         /* return early if the buffer sizes will not change */
2978         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2979                 return 0;
2980         if (old_mtu == new_mtu)
2981                 return 0;
2982
2983         /* synchronized against open : rtnl_lock() held by caller */
2984         if (netif_running(dev)) {
2985                 u8 __iomem *base = get_hwbase(dev);
2986                 /*
2987                  * It seems that the nic preloads valid ring entries into an
2988                  * internal buffer. The procedure for flushing everything is
2989                  * guessed, there is probably a simpler approach.
2990                  * Changing the MTU is a rare event, it shouldn't matter.
2991                  */
2992                 nv_disable_irq(dev);
2993                 nv_napi_disable(dev);
2994                 netif_tx_lock_bh(dev);
2995                 netif_addr_lock(dev);
2996                 spin_lock(&np->lock);
2997                 /* stop engines */
2998                 nv_stop_rxtx(dev);
2999                 nv_txrx_reset(dev);
3000                 /* drain rx queue */
3001                 nv_drain_rxtx(dev);
3002                 /* reinit driver view of the rx queue */
3003                 set_bufsize(dev);
3004                 if (nv_init_ring(dev)) {
3005                         if (!np->in_shutdown)
3006                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3007                 }
3008                 /* reinit nic view of the rx queue */
3009                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3010                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3011                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3012                         base + NvRegRingSizes);
3013                 pci_push(base);
3014                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3015                 pci_push(base);
3016
3017                 /* restart rx engine */
3018                 nv_start_rxtx(dev);
3019                 spin_unlock(&np->lock);
3020                 netif_addr_unlock(dev);
3021                 netif_tx_unlock_bh(dev);
3022                 nv_napi_enable(dev);
3023                 nv_enable_irq(dev);
3024         }
3025         return 0;
3026 }
3027
3028 static void nv_copy_mac_to_hw(struct net_device *dev)
3029 {
3030         u8 __iomem *base = get_hwbase(dev);
3031         u32 mac[2];
3032
3033         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3034                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3035         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3036
3037         writel(mac[0], base + NvRegMacAddrA);
3038         writel(mac[1], base + NvRegMacAddrB);
3039 }
3040
3041 /*
3042  * nv_set_mac_address: dev->set_mac_address function
3043  * Called with rtnl_lock() held.
3044  */
3045 static int nv_set_mac_address(struct net_device *dev, void *addr)
3046 {
3047         struct fe_priv *np = netdev_priv(dev);
3048         struct sockaddr *macaddr = (struct sockaddr*)addr;
3049
3050         if (!is_valid_ether_addr(macaddr->sa_data))
3051                 return -EADDRNOTAVAIL;
3052
3053         /* synchronized against open : rtnl_lock() held by caller */
3054         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3055
3056         if (netif_running(dev)) {
3057                 netif_tx_lock_bh(dev);
3058                 netif_addr_lock(dev);
3059                 spin_lock_irq(&np->lock);
3060
3061                 /* stop rx engine */
3062                 nv_stop_rx(dev);
3063
3064                 /* set mac address */
3065                 nv_copy_mac_to_hw(dev);
3066
3067                 /* restart rx engine */
3068                 nv_start_rx(dev);
3069                 spin_unlock_irq(&np->lock);
3070                 netif_addr_unlock(dev);
3071                 netif_tx_unlock_bh(dev);
3072         } else {
3073                 nv_copy_mac_to_hw(dev);
3074         }
3075         return 0;
3076 }
3077
3078 /*
3079  * nv_set_multicast: dev->set_multicast function
3080  * Called with netif_tx_lock held.
3081  */
3082 static void nv_set_multicast(struct net_device *dev)
3083 {
3084         struct fe_priv *np = netdev_priv(dev);
3085         u8 __iomem *base = get_hwbase(dev);
3086         u32 addr[2];
3087         u32 mask[2];
3088         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3089
3090         memset(addr, 0, sizeof(addr));
3091         memset(mask, 0, sizeof(mask));
3092
3093         if (dev->flags & IFF_PROMISC) {
3094                 pff |= NVREG_PFF_PROMISC;
3095         } else {
3096                 pff |= NVREG_PFF_MYADDR;
3097
3098                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3099                         u32 alwaysOff[2];
3100                         u32 alwaysOn[2];
3101
3102                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3103                         if (dev->flags & IFF_ALLMULTI) {
3104                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3105                         } else {
3106                                 struct dev_mc_list *walk;
3107
3108                                 netdev_for_each_mc_addr(walk, dev) {
3109                                         u32 a, b;
3110                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3111                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3112                                         alwaysOn[0] &= a;
3113                                         alwaysOff[0] &= ~a;
3114                                         alwaysOn[1] &= b;
3115                                         alwaysOff[1] &= ~b;
3116                                 }
3117                         }
3118                         addr[0] = alwaysOn[0];
3119                         addr[1] = alwaysOn[1];
3120                         mask[0] = alwaysOn[0] | alwaysOff[0];
3121                         mask[1] = alwaysOn[1] | alwaysOff[1];
3122                 } else {
3123                         mask[0] = NVREG_MCASTMASKA_NONE;
3124                         mask[1] = NVREG_MCASTMASKB_NONE;
3125                 }
3126         }
3127         addr[0] |= NVREG_MCASTADDRA_FORCE;
3128         pff |= NVREG_PFF_ALWAYS;
3129         spin_lock_irq(&np->lock);
3130         nv_stop_rx(dev);
3131         writel(addr[0], base + NvRegMulticastAddrA);
3132         writel(addr[1], base + NvRegMulticastAddrB);
3133         writel(mask[0], base + NvRegMulticastMaskA);
3134         writel(mask[1], base + NvRegMulticastMaskB);
3135         writel(pff, base + NvRegPacketFilterFlags);
3136         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3137                 dev->name);
3138         nv_start_rx(dev);
3139         spin_unlock_irq(&np->lock);
3140 }
3141
3142 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3143 {
3144         struct fe_priv *np = netdev_priv(dev);
3145         u8 __iomem *base = get_hwbase(dev);
3146
3147         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3148
3149         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3150                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3151                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3152                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3153                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3154                 } else {
3155                         writel(pff, base + NvRegPacketFilterFlags);
3156                 }
3157         }
3158         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3159                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3160                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3161                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3162                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3163                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3164                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3165                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3166                                 /* limit the number of tx pause frames to a default of 8 */
3167                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3168                         }
3169                         writel(pause_enable,  base + NvRegTxPauseFrame);
3170                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3171                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3172                 } else {
3173                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3174                         writel(regmisc, base + NvRegMisc1);
3175                 }
3176         }
3177 }
3178
3179 /**
3180  * nv_update_linkspeed: Setup the MAC according to the link partner
3181  * @dev: Network device to be configured
3182  *
3183  * The function queries the PHY and checks if there is a link partner.
3184  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3185  * set to 10 MBit HD.
3186  *
3187  * The function returns 0 if there is no link partner and 1 if there is
3188  * a good link partner.
3189  */
3190 static int nv_update_linkspeed(struct net_device *dev)
3191 {
3192         struct fe_priv *np = netdev_priv(dev);
3193         u8 __iomem *base = get_hwbase(dev);
3194         int adv = 0;
3195         int lpa = 0;
3196         int adv_lpa, adv_pause, lpa_pause;
3197         int newls = np->linkspeed;
3198         int newdup = np->duplex;
3199         int mii_status;
3200         int retval = 0;
3201         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3202         u32 txrxFlags = 0;
3203         u32 phy_exp;
3204
3205         /* BMSR_LSTATUS is latched, read it twice:
3206          * we want the current value.
3207          */
3208         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3209         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3210
3211         if (!(mii_status & BMSR_LSTATUS)) {
3212                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3213                                 dev->name);
3214                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3215                 newdup = 0;
3216                 retval = 0;
3217                 goto set_speed;
3218         }
3219
3220         if (np->autoneg == 0) {
3221                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3222                                 dev->name, np->fixed_mode);
3223                 if (np->fixed_mode & LPA_100FULL) {
3224                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3225                         newdup = 1;
3226                 } else if (np->fixed_mode & LPA_100HALF) {
3227                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3228                         newdup = 0;
3229                 } else if (np->fixed_mode & LPA_10FULL) {
3230                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3231                         newdup = 1;
3232                 } else {
3233                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3234                         newdup = 0;
3235                 }
3236                 retval = 1;
3237                 goto set_speed;
3238         }
3239         /* check auto negotiation is complete */
3240         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3241                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3242                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3243                 newdup = 0;
3244                 retval = 0;
3245                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3246                 goto set_speed;
3247         }
3248
3249         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3250         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3251         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3252                                 dev->name, adv, lpa);
3253
3254         retval = 1;
3255         if (np->gigabit == PHY_GIGABIT) {
3256                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3257                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3258
3259                 if ((control_1000 & ADVERTISE_1000FULL) &&
3260                         (status_1000 & LPA_1000FULL)) {
3261                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3262                                 dev->name);
3263                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3264                         newdup = 1;
3265                         goto set_speed;
3266                 }
3267         }
3268
3269         /* FIXME: handle parallel detection properly */
3270         adv_lpa = lpa & adv;
3271         if (adv_lpa & LPA_100FULL) {
3272                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3273                 newdup = 1;
3274         } else if (adv_lpa & LPA_100HALF) {
3275                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3276                 newdup = 0;
3277         } else if (adv_lpa & LPA_10FULL) {
3278                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3279                 newdup = 1;
3280         } else if (adv_lpa & LPA_10HALF) {
3281                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3282                 newdup = 0;
3283         } else {
3284                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3285                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3286                 newdup = 0;
3287         }
3288
3289 set_speed:
3290         if (np->duplex == newdup && np->linkspeed == newls)
3291                 return retval;
3292
3293         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3294                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3295
3296         np->duplex = newdup;
3297         np->linkspeed = newls;
3298
3299         /* The transmitter and receiver must be restarted for safe update */
3300         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3301                 txrxFlags |= NV_RESTART_TX;
3302                 nv_stop_tx(dev);
3303         }
3304         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3305                 txrxFlags |= NV_RESTART_RX;
3306                 nv_stop_rx(dev);
3307         }
3308
3309         if (np->gigabit == PHY_GIGABIT) {
3310                 phyreg = readl(base + NvRegSlotTime);
3311                 phyreg &= ~(0x3FF00);
3312                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3313                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3314                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3315                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3316                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3317                 writel(phyreg, base + NvRegSlotTime);
3318         }
3319
3320         phyreg = readl(base + NvRegPhyInterface);
3321         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3322         if (np->duplex == 0)
3323                 phyreg |= PHY_HALF;
3324         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3325                 phyreg |= PHY_100;
3326         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3327                 phyreg |= PHY_1000;
3328         writel(phyreg, base + NvRegPhyInterface);
3329
3330         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3331         if (phyreg & PHY_RGMII) {
3332                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3333                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3334                 } else {
3335                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3336                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3337                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3338                                 else
3339                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3340                         } else {
3341                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3342                         }
3343                 }
3344         } else {
3345                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3346                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3347                 else
3348                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3349         }
3350         writel(txreg, base + NvRegTxDeferral);
3351
3352         if (np->desc_ver == DESC_VER_1) {
3353                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3354         } else {
3355                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3356                         txreg = NVREG_TX_WM_DESC2_3_1000;
3357                 else
3358                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3359         }
3360         writel(txreg, base + NvRegTxWatermark);
3361
3362         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3363                 base + NvRegMisc1);
3364         pci_push(base);
3365         writel(np->linkspeed, base + NvRegLinkSpeed);
3366         pci_push(base);
3367
3368         pause_flags = 0;
3369         /* setup pause frame */
3370         if (np->duplex != 0) {
3371                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3372                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3373                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3374
3375                         switch (adv_pause) {
3376                         case ADVERTISE_PAUSE_CAP:
3377                                 if (lpa_pause & LPA_PAUSE_CAP) {
3378                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3379                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3380                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3381                                 }
3382                                 break;
3383                         case ADVERTISE_PAUSE_ASYM:
3384                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3385                                 {
3386                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3387                                 }
3388                                 break;
3389                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3390                                 if (lpa_pause & LPA_PAUSE_CAP)
3391                                 {
3392                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3393                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3394                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3395                                 }
3396                                 if (lpa_pause == LPA_PAUSE_ASYM)
3397                                 {
3398                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3399                                 }
3400                                 break;
3401                         }
3402                 } else {
3403                         pause_flags = np->pause_flags;
3404                 }
3405         }
3406         nv_update_pause(dev, pause_flags);
3407
3408         if (txrxFlags & NV_RESTART_TX)
3409                 nv_start_tx(dev);
3410         if (txrxFlags & NV_RESTART_RX)
3411                 nv_start_rx(dev);
3412
3413         return retval;
3414 }
3415
3416 static void nv_linkchange(struct net_device *dev)
3417 {
3418         if (nv_update_linkspeed(dev)) {
3419                 if (!netif_carrier_ok(dev)) {
3420                         netif_carrier_on(dev);
3421                         printk(KERN_INFO "%s: link up.\n", dev->name);
3422                         nv_txrx_gate(dev, false);
3423                         nv_start_rx(dev);
3424                 }
3425         } else {
3426                 if (netif_carrier_ok(dev)) {
3427                         netif_carrier_off(dev);
3428                         printk(KERN_INFO "%s: link down.\n", dev->name);
3429                         nv_txrx_gate(dev, true);
3430                         nv_stop_rx(dev);
3431                 }
3432         }
3433 }
3434
3435 static void nv_link_irq(struct net_device *dev)
3436 {
3437         u8 __iomem *base = get_hwbase(dev);
3438         u32 miistat;
3439
3440         miistat = readl(base + NvRegMIIStatus);
3441         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3442         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3443
3444         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3445                 nv_linkchange(dev);
3446         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3447 }
3448
3449 static void nv_msi_workaround(struct fe_priv *np)
3450 {
3451
3452         /* Need to toggle the msi irq mask within the ethernet device,
3453          * otherwise, future interrupts will not be detected.
3454          */
3455         if (np->msi_flags & NV_MSI_ENABLED) {
3456                 u8 __iomem *base = np->base;
3457
3458                 writel(0, base + NvRegMSIIrqMask);
3459                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3460         }
3461 }
3462
3463 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3464 {
3465         struct fe_priv *np = netdev_priv(dev);
3466
3467         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3468                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3469                         /* transition to poll based interrupts */
3470                         np->quiet_count = 0;
3471                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3472                                 np->irqmask = NVREG_IRQMASK_CPU;
3473                                 return 1;
3474                         }
3475                 } else {
3476                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3477                                 np->quiet_count++;
3478                         } else {
3479                                 /* reached a period of low activity, switch
3480                                    to per tx/rx packet interrupts */
3481                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3482                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3483                                         return 1;
3484                                 }
3485                         }
3486                 }
3487         }
3488         return 0;
3489 }
3490
3491 static irqreturn_t nv_nic_irq(int foo, void *data)
3492 {
3493         struct net_device *dev = (struct net_device *) data;
3494         struct fe_priv *np = netdev_priv(dev);
3495         u8 __iomem *base = get_hwbase(dev);
3496 #ifndef CONFIG_FORCEDETH_NAPI
3497         int total_work = 0;
3498         int loop_count = 0;
3499 #endif
3500
3501         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3502
3503         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3504                 np->events = readl(base + NvRegIrqStatus);
3505                 writel(np->events, base + NvRegIrqStatus);
3506         } else {
3507                 np->events = readl(base + NvRegMSIXIrqStatus);
3508                 writel(np->events, base + NvRegMSIXIrqStatus);
3509         }
3510         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3511         if (!(np->events & np->irqmask))
3512                 return IRQ_NONE;
3513
3514         nv_msi_workaround(np);
3515
3516 #ifdef CONFIG_FORCEDETH_NAPI
3517         if (napi_schedule_prep(&np->napi)) {
3518                 /*
3519                  * Disable further irq's (msix not enabled with napi)
3520                  */
3521                 writel(0, base + NvRegIrqMask);
3522                 __napi_schedule(&np->napi);
3523         }
3524
3525 #else
3526         do
3527         {
3528                 int work = 0;
3529                 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3530                         if (unlikely(nv_alloc_rx(dev))) {
3531                                 spin_lock(&np->lock);
3532                                 if (!np->in_shutdown)
3533                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3534                                 spin_unlock(&np->lock);
3535                         }
3536                 }
3537
3538                 spin_lock(&np->lock);
3539                 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3540                 spin_unlock(&np->lock);
3541
3542                 if (!work)
3543                         break;
3544
3545                 total_work += work;
3546
3547                 loop_count++;
3548         }
3549         while (loop_count < max_interrupt_work);
3550
3551         if (nv_change_interrupt_mode(dev, total_work)) {
3552                 /* setup new irq mask */
3553                 writel(np->irqmask, base + NvRegIrqMask);
3554         }
3555
3556         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3557                 spin_lock(&np->lock);
3558                 nv_link_irq(dev);
3559                 spin_unlock(&np->lock);
3560         }
3561         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3562                 spin_lock(&np->lock);
3563                 nv_linkchange(dev);
3564                 spin_unlock(&np->lock);
3565                 np->link_timeout = jiffies + LINK_TIMEOUT;
3566         }
3567         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3568                 spin_lock(&np->lock);
3569                 /* disable interrupts on the nic */
3570                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3571                         writel(0, base + NvRegIrqMask);
3572                 else
3573                         writel(np->irqmask, base + NvRegIrqMask);
3574                 pci_push(base);
3575
3576                 if (!np->in_shutdown) {
3577                         np->nic_poll_irq = np->irqmask;
3578                         np->recover_error = 1;
3579                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3580                 }
3581                 spin_unlock(&np->lock);
3582         }
3583 #endif
3584         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3585
3586         return IRQ_HANDLED;
3587 }
3588
3589 /**
3590  * All _optimized functions are used to help increase performance
3591  * (reduce CPU and increase throughput). They use descripter version 3,
3592  * compiler directives, and reduce memory accesses.
3593  */
3594 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3595 {
3596         struct net_device *dev = (struct net_device *) data;
3597         struct fe_priv *np = netdev_priv(dev);
3598         u8 __iomem *base = get_hwbase(dev);
3599 #ifndef CONFIG_FORCEDETH_NAPI
3600         int total_work = 0;
3601         int loop_count = 0;
3602 #endif
3603
3604         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3605
3606         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3607                 np->events = readl(base + NvRegIrqStatus);
3608                 writel(np->events, base + NvRegIrqStatus);
3609         } else {
3610                 np->events = readl(base + NvRegMSIXIrqStatus);
3611                 writel(np->events, base + NvRegMSIXIrqStatus);
3612         }
3613         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3614         if (!(np->events & np->irqmask))
3615                 return IRQ_NONE;
3616
3617         nv_msi_workaround(np);
3618
3619 #ifdef CONFIG_FORCEDETH_NAPI
3620         if (napi_schedule_prep(&np->napi)) {
3621                 /*
3622                  * Disable further irq's (msix not enabled with napi)
3623                  */
3624                 writel(0, base + NvRegIrqMask);
3625                 __napi_schedule(&np->napi);
3626         }
3627 #else
3628         do
3629         {
3630                 int work = 0;
3631                 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3632                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3633                                 spin_lock(&np->lock);
3634                                 if (!np->in_shutdown)
3635                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3636                                 spin_unlock(&np->lock);
3637                         }
3638                 }
3639
3640                 spin_lock(&np->lock);
3641                 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3642                 spin_unlock(&np->lock);
3643
3644                 if (!work)
3645                         break;
3646
3647                 total_work += work;
3648
3649                 loop_count++;
3650         }
3651         while (loop_count < max_interrupt_work);
3652
3653         if (nv_change_interrupt_mode(dev, total_work)) {
3654                 /* setup new irq mask */
3655                 writel(np->irqmask, base + NvRegIrqMask);
3656         }
3657
3658         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3659                 spin_lock(&np->lock);
3660                 nv_link_irq(dev);
3661                 spin_unlock(&np->lock);
3662         }
3663         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3664                 spin_lock(&np->lock);
3665                 nv_linkchange(dev);
3666                 spin_unlock(&np->lock);
3667                 np->link_timeout = jiffies + LINK_TIMEOUT;
3668         }
3669         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3670                 spin_lock(&np->lock);
3671                 /* disable interrupts on the nic */
3672                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3673                         writel(0, base + NvRegIrqMask);
3674                 else
3675                         writel(np->irqmask, base + NvRegIrqMask);
3676                 pci_push(base);
3677
3678                 if (!np->in_shutdown) {
3679                         np->nic_poll_irq = np->irqmask;
3680                         np->recover_error = 1;
3681                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3682                 }
3683                 spin_unlock(&np->lock);
3684         }
3685
3686 #endif
3687         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3688
3689         return IRQ_HANDLED;
3690 }
3691
3692 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3693 {
3694         struct net_device *dev = (struct net_device *) data;
3695         struct fe_priv *np = netdev_priv(dev);
3696         u8 __iomem *base = get_hwbase(dev);
3697         u32 events;
3698         int i;
3699         unsigned long flags;
3700
3701         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3702
3703         for (i=0; ; i++) {
3704                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3705                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3706                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3707                 if (!(events & np->irqmask))
3708                         break;
3709
3710                 spin_lock_irqsave(&np->lock, flags);
3711                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3712                 spin_unlock_irqrestore(&np->lock, flags);
3713
3714                 if (unlikely(i > max_interrupt_work)) {
3715                         spin_lock_irqsave(&np->lock, flags);
3716                         /* disable interrupts on the nic */
3717                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3718                         pci_push(base);
3719
3720                         if (!np->in_shutdown) {
3721                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3722                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3723                         }
3724                         spin_unlock_irqrestore(&np->lock, flags);
3725                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3726                         break;
3727                 }
3728
3729         }
3730         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3731
3732         return IRQ_RETVAL(i);
3733 }
3734
3735 #ifdef CONFIG_FORCEDETH_NAPI
3736 static int nv_napi_poll(struct napi_struct *napi, int budget)
3737 {
3738         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3739         struct net_device *dev = np->dev;
3740         u8 __iomem *base = get_hwbase(dev);
3741         unsigned long flags;
3742         int retcode;
3743         int tx_work, rx_work;
3744
3745         if (!nv_optimized(np)) {
3746                 spin_lock_irqsave(&np->lock, flags);
3747                 tx_work = nv_tx_done(dev, np->tx_ring_size);
3748                 spin_unlock_irqrestore(&np->lock, flags);
3749
3750                 rx_work = nv_rx_process(dev, budget);
3751                 retcode = nv_alloc_rx(dev);
3752         } else {
3753                 spin_lock_irqsave(&np->lock, flags);
3754                 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3755                 spin_unlock_irqrestore(&np->lock, flags);
3756
3757                 rx_work = nv_rx_process_optimized(dev, budget);
3758                 retcode = nv_alloc_rx_optimized(dev);
3759         }
3760
3761         if (retcode) {
3762                 spin_lock_irqsave(&np->lock, flags);
3763                 if (!np->in_shutdown)
3764                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3765                 spin_unlock_irqrestore(&np->lock, flags);
3766         }
3767
3768         nv_change_interrupt_mode(dev, tx_work + rx_work);
3769
3770         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3771                 spin_lock_irqsave(&np->lock, flags);
3772                 nv_link_irq(dev);
3773                 spin_unlock_irqrestore(&np->lock, flags);
3774         }
3775         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3776                 spin_lock_irqsave(&np->lock, flags);
3777                 nv_linkchange(dev);
3778                 spin_unlock_irqrestore(&np->lock, flags);
3779                 np->link_timeout = jiffies + LINK_TIMEOUT;
3780         }
3781         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3782                 spin_lock_irqsave(&np->lock, flags);
3783                 if (!np->in_shutdown) {
3784                         np->nic_poll_irq = np->irqmask;
3785                         np->recover_error = 1;
3786                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3787                 }
3788                 spin_unlock_irqrestore(&np->lock, flags);
3789                 napi_complete(napi);
3790                 return rx_work;
3791         }
3792
3793         if (rx_work < budget) {
3794                 /* re-enable interrupts
3795                    (msix not enabled in napi) */
3796                 napi_complete(napi);
3797
3798                 writel(np->irqmask, base + NvRegIrqMask);
3799         }
3800         return rx_work;
3801 }
3802 #endif
3803
3804 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3805 {
3806         struct net_device *dev = (struct net_device *) data;
3807         struct fe_priv *np = netdev_priv(dev);
3808         u8 __iomem *base = get_hwbase(dev);
3809         u32 events;
3810         int i;
3811         unsigned long flags;
3812
3813         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3814
3815         for (i=0; ; i++) {
3816                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3817                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3818                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3819                 if (!(events & np->irqmask))
3820                         break;
3821
3822                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3823                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3824                                 spin_lock_irqsave(&np->lock, flags);
3825                                 if (!np->in_shutdown)
3826                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3827                                 spin_unlock_irqrestore(&np->lock, flags);
3828                         }
3829                 }
3830
3831                 if (unlikely(i > max_interrupt_work)) {
3832                         spin_lock_irqsave(&np->lock, flags);
3833                         /* disable interrupts on the nic */
3834                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3835                         pci_push(base);
3836
3837                         if (!np->in_shutdown) {
3838                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3839                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3840                         }
3841                         spin_unlock_irqrestore(&np->lock, flags);
3842                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3843                         break;
3844                 }
3845         }
3846         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3847
3848         return IRQ_RETVAL(i);
3849 }
3850
3851 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3852 {
3853         struct net_device *dev = (struct net_device *) data;
3854         struct fe_priv *np = netdev_priv(dev);
3855         u8 __iomem *base = get_hwbase(dev);
3856         u32 events;
3857         int i;
3858         unsigned long flags;
3859
3860         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3861
3862         for (i=0; ; i++) {
3863                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3864                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3865                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3866                 if (!(events & np->irqmask))
3867                         break;
3868
3869                 /* check tx in case we reached max loop limit in tx isr */
3870                 spin_lock_irqsave(&np->lock, flags);
3871                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3872                 spin_unlock_irqrestore(&np->lock, flags);
3873
3874                 if (events & NVREG_IRQ_LINK) {
3875                         spin_lock_irqsave(&np->lock, flags);
3876                         nv_link_irq(dev);
3877                         spin_unlock_irqrestore(&np->lock, flags);
3878                 }
3879                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3880                         spin_lock_irqsave(&np->lock, flags);
3881                         nv_linkchange(dev);
3882                         spin_unlock_irqrestore(&np->lock, flags);
3883                         np->link_timeout = jiffies + LINK_TIMEOUT;
3884                 }
3885                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3886                         spin_lock_irq(&np->lock);
3887                         /* disable interrupts on the nic */
3888                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3889                         pci_push(base);
3890
3891                         if (!np->in_shutdown) {
3892                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3893                                 np->recover_error = 1;
3894                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3895                         }
3896                         spin_unlock_irq(&np->lock);
3897                         break;
3898                 }
3899                 if (unlikely(i > max_interrupt_work)) {
3900                         spin_lock_irqsave(&np->lock, flags);
3901                         /* disable interrupts on the nic */
3902                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3903                         pci_push(base);
3904
3905                         if (!np->in_shutdown) {
3906                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3907                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3908                         }
3909                         spin_unlock_irqrestore(&np->lock, flags);
3910                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3911                         break;
3912                 }
3913
3914         }
3915         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3916
3917         return IRQ_RETVAL(i);
3918 }
3919
3920 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3921 {
3922         struct net_device *dev = (struct net_device *) data;
3923         struct fe_priv *np = netdev_priv(dev);
3924         u8 __iomem *base = get_hwbase(dev);
3925         u32 events;
3926
3927         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3928
3929         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3930                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3931                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3932         } else {
3933                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3934                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3935         }
3936         pci_push(base);
3937         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3938         if (!(events & NVREG_IRQ_TIMER))
3939                 return IRQ_RETVAL(0);
3940
3941         nv_msi_workaround(np);
3942
3943         spin_lock(&np->lock);
3944         np->intr_test = 1;
3945         spin_unlock(&np->lock);
3946
3947         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3948
3949         return IRQ_RETVAL(1);
3950 }
3951
3952 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3953 {
3954         u8 __iomem *base = get_hwbase(dev);
3955         int i;
3956         u32 msixmap = 0;
3957
3958         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3959          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3960          * the remaining 8 interrupts.
3961          */
3962         for (i = 0; i < 8; i++) {
3963                 if ((irqmask >> i) & 0x1) {
3964                         msixmap |= vector << (i << 2);
3965                 }
3966         }
3967         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3968
3969         msixmap = 0;
3970         for (i = 0; i < 8; i++) {
3971                 if ((irqmask >> (i + 8)) & 0x1) {
3972                         msixmap |= vector << (i << 2);
3973                 }
3974         }
3975         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3976 }
3977
3978 static int nv_request_irq(struct net_device *dev, int intr_test)
3979 {
3980         struct fe_priv *np = get_nvpriv(dev);
3981         u8 __iomem *base = get_hwbase(dev);
3982         int ret = 1;
3983         int i;
3984         irqreturn_t (*handler)(int foo, void *data);
3985
3986         if (intr_test) {
3987                 handler = nv_nic_irq_test;
3988         } else {
3989                 if (nv_optimized(np))
3990                         handler = nv_nic_irq_optimized;
3991                 else
3992                         handler = nv_nic_irq;
3993         }
3994
3995         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3996                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3997                         np->msi_x_entry[i].entry = i;
3998                 }
3999                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
4000                         np->msi_flags |= NV_MSI_X_ENABLED;
4001                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
4002                                 /* Request irq for rx handling */
4003                                 sprintf(np->name_rx, "%s-rx", dev->name);
4004                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
4005                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
4006                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
4007                                         pci_disable_msix(np->pci_dev);
4008                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4009                                         goto out_err;
4010                                 }
4011                                 /* Request irq for tx handling */
4012                                 sprintf(np->name_tx, "%s-tx", dev->name);
4013                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4014                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
4015                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4016                                         pci_disable_msix(np->pci_dev);
4017                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4018                                         goto out_free_rx;
4019                                 }
4020                                 /* Request irq for link and timer handling */
4021                                 sprintf(np->name_other, "%s-other", dev->name);
4022                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4023                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4024                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4025                                         pci_disable_msix(np->pci_dev);
4026                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4027                                         goto out_free_tx;
4028                                 }
4029                                 /* map interrupts to their respective vector */
4030                                 writel(0, base + NvRegMSIXMap0);
4031                                 writel(0, base + NvRegMSIXMap1);
4032                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4033                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4034                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4035                         } else {
4036                                 /* Request irq for all interrupts */
4037                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4038                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4039                                         pci_disable_msix(np->pci_dev);
4040                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4041                                         goto out_err;
4042                                 }
4043
4044                                 /* map interrupts to vector 0 */
4045                                 writel(0, base + NvRegMSIXMap0);
4046                                 writel(0, base + NvRegMSIXMap1);
4047                         }
4048                 }
4049         }
4050         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4051                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4052                         np->msi_flags |= NV_MSI_ENABLED;
4053                         dev->irq = np->pci_dev->irq;
4054                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4055                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4056                                 pci_disable_msi(np->pci_dev);
4057                                 np->msi_flags &= ~NV_MSI_ENABLED;
4058                                 dev->irq = np->pci_dev->irq;
4059                                 goto out_err;
4060                         }
4061
4062                         /* map interrupts to vector 0 */
4063                         writel(0, base + NvRegMSIMap0);
4064                         writel(0, base + NvRegMSIMap1);
4065                         /* enable msi vector 0 */
4066                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4067                 }
4068         }
4069         if (ret != 0) {
4070                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4071                         goto out_err;
4072
4073         }
4074
4075         return 0;
4076 out_free_tx:
4077         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4078 out_free_rx:
4079         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4080 out_err:
4081         return 1;
4082 }
4083
4084 static void nv_free_irq(struct net_device *dev)
4085 {
4086         struct fe_priv *np = get_nvpriv(dev);
4087         int i;
4088
4089         if (np->msi_flags & NV_MSI_X_ENABLED) {
4090                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4091                         free_irq(np->msi_x_entry[i].vector, dev);
4092                 }
4093                 pci_disable_msix(np->pci_dev);
4094                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4095         } else {
4096                 free_irq(np->pci_dev->irq, dev);
4097                 if (np->msi_flags & NV_MSI_ENABLED) {
4098                         pci_disable_msi(np->pci_dev);
4099                         np->msi_flags &= ~NV_MSI_ENABLED;
4100                 }
4101         }
4102 }
4103
4104 static void nv_do_nic_poll(unsigned long data)
4105 {
4106         struct net_device *dev = (struct net_device *) data;
4107         struct fe_priv *np = netdev_priv(dev);
4108         u8 __iomem *base = get_hwbase(dev);
4109         u32 mask = 0;
4110
4111         /*
4112          * First disable irq(s) and then
4113          * reenable interrupts on the nic, we have to do this before calling
4114          * nv_nic_irq because that may decide to do otherwise
4115          */
4116
4117         if (!using_multi_irqs(dev)) {
4118                 if (np->msi_flags & NV_MSI_X_ENABLED)
4119                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4120                 else
4121                         disable_irq_lockdep(np->pci_dev->irq);
4122                 mask = np->irqmask;
4123         } else {
4124                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4125                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4126                         mask |= NVREG_IRQ_RX_ALL;
4127                 }
4128                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4129                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4130                         mask |= NVREG_IRQ_TX_ALL;
4131                 }
4132                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4133                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4134                         mask |= NVREG_IRQ_OTHER;
4135                 }
4136         }
4137         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4138
4139         if (np->recover_error) {
4140                 np->recover_error = 0;
4141                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4142                 if (netif_running(dev)) {
4143                         netif_tx_lock_bh(dev);
4144                         netif_addr_lock(dev);
4145                         spin_lock(&np->lock);
4146                         /* stop engines */
4147                         nv_stop_rxtx(dev);
4148                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4149                                 nv_mac_reset(dev);
4150                         nv_txrx_reset(dev);
4151                         /* drain rx queue */
4152                         nv_drain_rxtx(dev);
4153                         /* reinit driver view of the rx queue */
4154                         set_bufsize(dev);
4155                         if (nv_init_ring(dev)) {
4156                                 if (!np->in_shutdown)
4157                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4158                         }
4159                         /* reinit nic view of the rx queue */
4160                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4161                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4162                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4163                                 base + NvRegRingSizes);
4164                         pci_push(base);
4165                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4166                         pci_push(base);
4167                         /* clear interrupts */
4168                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4169                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4170                         else
4171                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4172
4173                         /* restart rx engine */
4174                         nv_start_rxtx(dev);
4175                         spin_unlock(&np->lock);
4176                         netif_addr_unlock(dev);
4177                         netif_tx_unlock_bh(dev);
4178                 }
4179         }
4180
4181         writel(mask, base + NvRegIrqMask);
4182         pci_push(base);
4183
4184         if (!using_multi_irqs(dev)) {
4185                 np->nic_poll_irq = 0;
4186                 if (nv_optimized(np))
4187                         nv_nic_irq_optimized(0, dev);
4188                 else
4189                         nv_nic_irq(0, dev);
4190                 if (np->msi_flags & NV_MSI_X_ENABLED)
4191                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4192                 else
4193                         enable_irq_lockdep(np->pci_dev->irq);
4194         } else {
4195                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4196                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4197                         nv_nic_irq_rx(0, dev);
4198                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4199                 }
4200                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4201                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4202                         nv_nic_irq_tx(0, dev);
4203                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4204                 }
4205                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4206                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4207                         nv_nic_irq_other(0, dev);
4208                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4209                 }
4210         }
4211
4212 }
4213
4214 #ifdef CONFIG_NET_POLL_CONTROLLER
4215 static void nv_poll_controller(struct net_device *dev)
4216 {
4217         nv_do_nic_poll((unsigned long) dev);
4218 }
4219 #endif
4220
4221 static void nv_do_stats_poll(unsigned long data)
4222 {
4223         struct net_device *dev = (struct net_device *) data;
4224         struct fe_priv *np = netdev_priv(dev);
4225
4226         nv_get_hw_stats(dev);
4227
4228         if (!np->in_shutdown)
4229                 mod_timer(&np->stats_poll,
4230                         round_jiffies(jiffies + STATS_INTERVAL));
4231 }
4232
4233 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4234 {
4235         struct fe_priv *np = netdev_priv(dev);
4236         strcpy(info->driver, DRV_NAME);
4237         strcpy(info->version, FORCEDETH_VERSION);
4238         strcpy(info->bus_info, pci_name(np->pci_dev));
4239 }
4240
4241 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4242 {
4243         struct fe_priv *np = netdev_priv(dev);
4244         wolinfo->supported = WAKE_MAGIC;
4245
4246         spin_lock_irq(&np->lock);
4247         if (np->wolenabled)
4248                 wolinfo->wolopts = WAKE_MAGIC;
4249         spin_unlock_irq(&np->lock);
4250 }
4251
4252 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4253 {
4254         struct fe_priv *np = netdev_priv(dev);
4255         u8 __iomem *base = get_hwbase(dev);
4256         u32 flags = 0;
4257
4258         if (wolinfo->wolopts == 0) {
4259                 np->wolenabled = 0;
4260         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4261                 np->wolenabled = 1;
4262                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4263         }
4264         if (netif_running(dev)) {
4265                 spin_lock_irq(&np->lock);
4266                 writel(flags, base + NvRegWakeUpFlags);
4267                 spin_unlock_irq(&np->lock);
4268         }
4269         return 0;
4270 }
4271
4272 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4273 {
4274         struct fe_priv *np = netdev_priv(dev);
4275         int adv;
4276
4277         spin_lock_irq(&np->lock);
4278         ecmd->port = PORT_MII;
4279         if (!netif_running(dev)) {
4280                 /* We do not track link speed / duplex setting if the
4281                  * interface is disabled. Force a link check */
4282                 if (nv_update_linkspeed(dev)) {
4283                         if (!netif_carrier_ok(dev))
4284                                 netif_carrier_on(dev);
4285                 } else {
4286                         if (netif_carrier_ok(dev))
4287                                 netif_carrier_off(dev);
4288                 }
4289         }
4290
4291         if (netif_carrier_ok(dev)) {
4292                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4293                 case NVREG_LINKSPEED_10:
4294                         ecmd->speed = SPEED_10;
4295                         break;
4296                 case NVREG_LINKSPEED_100:
4297                         ecmd->speed = SPEED_100;
4298                         break;
4299                 case NVREG_LINKSPEED_1000:
4300                         ecmd->speed = SPEED_1000;
4301                         break;
4302                 }
4303                 ecmd->duplex = DUPLEX_HALF;
4304                 if (np->duplex)
4305                         ecmd->duplex = DUPLEX_FULL;
4306         } else {
4307                 ecmd->speed = -1;
4308                 ecmd->duplex = -1;
4309         }
4310
4311         ecmd->autoneg = np->autoneg;
4312
4313         ecmd->advertising = ADVERTISED_MII;
4314         if (np->autoneg) {
4315                 ecmd->advertising |= ADVERTISED_Autoneg;
4316                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4317                 if (adv & ADVERTISE_10HALF)
4318                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4319                 if (adv & ADVERTISE_10FULL)
4320                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4321                 if (adv & ADVERTISE_100HALF)
4322                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4323                 if (adv & ADVERTISE_100FULL)
4324                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4325                 if (np->gigabit == PHY_GIGABIT) {
4326                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4327                         if (adv & ADVERTISE_1000FULL)
4328                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4329                 }
4330         }
4331         ecmd->supported = (SUPPORTED_Autoneg |
4332                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4333                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4334                 SUPPORTED_MII);
4335         if (np->gigabit == PHY_GIGABIT)
4336                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4337
4338         ecmd->phy_address = np->phyaddr;
4339         ecmd->transceiver = XCVR_EXTERNAL;
4340
4341         /* ignore maxtxpkt, maxrxpkt for now */
4342         spin_unlock_irq(&np->lock);
4343         return 0;
4344 }
4345
4346 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4347 {
4348         struct fe_priv *np = netdev_priv(dev);
4349
4350         if (ecmd->port != PORT_MII)
4351                 return -EINVAL;
4352         if (ecmd->transceiver != XCVR_EXTERNAL)
4353                 return -EINVAL;
4354         if (ecmd->phy_address != np->phyaddr) {
4355                 /* TODO: support switching between multiple phys. Should be
4356                  * trivial, but not enabled due to lack of test hardware. */
4357                 return -EINVAL;
4358         }
4359         if (ecmd->autoneg == AUTONEG_ENABLE) {
4360                 u32 mask;
4361
4362                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4363                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4364                 if (np->gigabit == PHY_GIGABIT)
4365                         mask |= ADVERTISED_1000baseT_Full;
4366
4367                 if ((ecmd->advertising & mask) == 0)
4368                         return -EINVAL;
4369
4370         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4371                 /* Note: autonegotiation disable, speed 1000 intentionally
4372                  * forbidden - noone should need that. */
4373
4374                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4375                         return -EINVAL;
4376                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4377                         return -EINVAL;
4378         } else {
4379                 return -EINVAL;
4380         }
4381
4382         netif_carrier_off(dev);
4383         if (netif_running(dev)) {
4384                 unsigned long flags;
4385
4386                 nv_disable_irq(dev);
4387                 netif_tx_lock_bh(dev);
4388                 netif_addr_lock(dev);
4389                 /* with plain spinlock lockdep complains */
4390                 spin_lock_irqsave(&np->lock, flags);
4391                 /* stop engines */
4392                 /* FIXME:
4393                  * this can take some time, and interrupts are disabled
4394                  * due to spin_lock_irqsave, but let's hope no daemon
4395                  * is going to change the settings very often...
4396                  * Worst case:
4397                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4398                  * + some minor delays, which is up to a second approximately
4399                  */
4400                 nv_stop_rxtx(dev);
4401                 spin_unlock_irqrestore(&np->lock, flags);
4402                 netif_addr_unlock(dev);
4403                 netif_tx_unlock_bh(dev);
4404         }
4405
4406         if (ecmd->autoneg == AUTONEG_ENABLE) {
4407                 int adv, bmcr;
4408
4409                 np->autoneg = 1;
4410
4411                 /* advertise only what has been requested */
4412                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4413                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4414                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4415                         adv |= ADVERTISE_10HALF;
4416                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4417                         adv |= ADVERTISE_10FULL;
4418                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4419                         adv |= ADVERTISE_100HALF;
4420                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4421                         adv |= ADVERTISE_100FULL;
4422                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4423                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4424                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4425                         adv |=  ADVERTISE_PAUSE_ASYM;
4426                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4427
4428                 if (np->gigabit == PHY_GIGABIT) {
4429                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4430                         adv &= ~ADVERTISE_1000FULL;
4431                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4432                                 adv |= ADVERTISE_1000FULL;
4433                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4434                 }
4435
4436                 if (netif_running(dev))
4437                         printk(KERN_INFO "%s: link down.\n", dev->name);
4438                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4439                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4440                         bmcr |= BMCR_ANENABLE;
4441                         /* reset the phy in order for settings to stick,
4442                          * and cause autoneg to start */
4443                         if (phy_reset(dev, bmcr)) {
4444                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4445                                 return -EINVAL;
4446                         }
4447                 } else {
4448                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4449                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4450                 }
4451         } else {
4452                 int adv, bmcr;
4453
4454                 np->autoneg = 0;
4455
4456                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4457                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4458                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4459                         adv |= ADVERTISE_10HALF;
4460                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4461                         adv |= ADVERTISE_10FULL;
4462                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4463                         adv |= ADVERTISE_100HALF;
4464                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4465                         adv |= ADVERTISE_100FULL;
4466                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4467                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4468                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4469                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4470                 }
4471                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4472                         adv |=  ADVERTISE_PAUSE_ASYM;
4473                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4474                 }
4475                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4476                 np->fixed_mode = adv;
4477
4478                 if (np->gigabit == PHY_GIGABIT) {
4479                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4480                         adv &= ~ADVERTISE_1000FULL;
4481                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4482                 }
4483
4484                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4485                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4486                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4487                         bmcr |= BMCR_FULLDPLX;
4488                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4489                         bmcr |= BMCR_SPEED100;
4490                 if (np->phy_oui == PHY_OUI_MARVELL) {
4491                         /* reset the phy in order for forced mode settings to stick */
4492                         if (phy_reset(dev, bmcr)) {
4493                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4494                                 return -EINVAL;
4495                         }
4496                 } else {
4497                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4498                         if (netif_running(dev)) {
4499                                 /* Wait a bit and then reconfigure the nic. */
4500                                 udelay(10);
4501                                 nv_linkchange(dev);
4502                         }
4503                 }
4504         }
4505
4506         if (netif_running(dev)) {
4507                 nv_start_rxtx(dev);
4508                 nv_enable_irq(dev);
4509         }
4510
4511         return 0;
4512 }
4513
4514 #define FORCEDETH_REGS_VER      1
4515
4516 static int nv_get_regs_len(struct net_device *dev)
4517 {
4518         struct fe_priv *np = netdev_priv(dev);
4519         return np->register_size;
4520 }
4521
4522 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4523 {
4524         struct fe_priv *np = netdev_priv(dev);
4525         u8 __iomem *base = get_hwbase(dev);
4526         u32 *rbuf = buf;
4527         int i;
4528
4529         regs->version = FORCEDETH_REGS_VER;
4530         spin_lock_irq(&np->lock);
4531         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4532                 rbuf[i] = readl(base + i*sizeof(u32));
4533         spin_unlock_irq(&np->lock);
4534 }
4535
4536 static int nv_nway_reset(struct net_device *dev)
4537 {
4538         struct fe_priv *np = netdev_priv(dev);
4539         int ret;
4540
4541         if (np->autoneg) {
4542                 int bmcr;
4543
4544                 netif_carrier_off(dev);
4545                 if (netif_running(dev)) {
4546                         nv_disable_irq(dev);
4547                         netif_tx_lock_bh(dev);
4548                         netif_addr_lock(dev);
4549                         spin_lock(&np->lock);
4550                         /* stop engines */
4551                         nv_stop_rxtx(dev);
4552                         spin_unlock(&np->lock);
4553                         netif_addr_unlock(dev);
4554                         netif_tx_unlock_bh(dev);
4555                         printk(KERN_INFO "%s: link down.\n", dev->name);
4556                 }
4557
4558                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4559                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4560                         bmcr |= BMCR_ANENABLE;
4561                         /* reset the phy in order for settings to stick*/
4562                         if (phy_reset(dev, bmcr)) {
4563                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4564                                 return -EINVAL;
4565                         }
4566                 } else {
4567                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4568                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4569                 }
4570
4571                 if (netif_running(dev)) {
4572                         nv_start_rxtx(dev);
4573                         nv_enable_irq(dev);
4574                 }
4575                 ret = 0;
4576         } else {
4577                 ret = -EINVAL;
4578         }
4579
4580         return ret;
4581 }
4582
4583 static int nv_set_tso(struct net_device *dev, u32 value)
4584 {
4585         struct fe_priv *np = netdev_priv(dev);
4586
4587         if ((np->driver_data & DEV_HAS_CHECKSUM))
4588                 return ethtool_op_set_tso(dev, value);
4589         else
4590                 return -EOPNOTSUPP;
4591 }
4592
4593 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4594 {
4595         struct fe_priv *np = netdev_priv(dev);
4596
4597         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4598         ring->rx_mini_max_pending = 0;
4599         ring->rx_jumbo_max_pending = 0;
4600         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4601
4602         ring->rx_pending = np->rx_ring_size;
4603         ring->rx_mini_pending = 0;
4604         ring->rx_jumbo_pending = 0;
4605         ring->tx_pending = np->tx_ring_size;
4606 }
4607
4608 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4609 {
4610         struct fe_priv *np = netdev_priv(dev);
4611         u8 __iomem *base = get_hwbase(dev);
4612         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4613         dma_addr_t ring_addr;
4614
4615         if (ring->rx_pending < RX_RING_MIN ||
4616             ring->tx_pending < TX_RING_MIN ||
4617             ring->rx_mini_pending != 0 ||
4618             ring->rx_jumbo_pending != 0 ||
4619             (np->desc_ver == DESC_VER_1 &&
4620              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4621               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4622             (np->desc_ver != DESC_VER_1 &&
4623              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4624               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4625                 return -EINVAL;
4626         }
4627
4628         /* allocate new rings */
4629         if (!nv_optimized(np)) {
4630                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4631                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4632                                             &ring_addr);
4633         } else {
4634                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4635                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4636                                             &ring_addr);
4637         }
4638         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4639         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4640         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4641                 /* fall back to old rings */
4642                 if (!nv_optimized(np)) {
4643                         if (rxtx_ring)
4644                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4645                                                     rxtx_ring, ring_addr);
4646                 } else {
4647                         if (rxtx_ring)
4648                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4649                                                     rxtx_ring, ring_addr);
4650                 }
4651                 if (rx_skbuff)
4652                         kfree(rx_skbuff);
4653                 if (tx_skbuff)
4654                         kfree(tx_skbuff);
4655                 goto exit;
4656         }
4657
4658         if (netif_running(dev)) {
4659                 nv_disable_irq(dev);
4660                 nv_napi_disable(dev);
4661                 netif_tx_lock_bh(dev);
4662                 netif_addr_lock(dev);
4663                 spin_lock(&np->lock);
4664                 /* stop engines */
4665                 nv_stop_rxtx(dev);
4666                 nv_txrx_reset(dev);
4667                 /* drain queues */
4668                 nv_drain_rxtx(dev);
4669                 /* delete queues */
4670                 free_rings(dev);
4671         }
4672
4673         /* set new values */
4674         np->rx_ring_size = ring->rx_pending;
4675         np->tx_ring_size = ring->tx_pending;
4676
4677         if (!nv_optimized(np)) {
4678                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4679                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4680         } else {
4681                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4682                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4683         }
4684         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4685         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4686         np->ring_addr = ring_addr;
4687
4688         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4689         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4690
4691         if (netif_running(dev)) {
4692                 /* reinit driver view of the queues */
4693                 set_bufsize(dev);
4694                 if (nv_init_ring(dev)) {
4695                         if (!np->in_shutdown)
4696                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4697                 }
4698
4699                 /* reinit nic view of the queues */
4700                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4701                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4702                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4703                         base + NvRegRingSizes);
4704                 pci_push(base);
4705                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4706                 pci_push(base);
4707
4708                 /* restart engines */
4709                 nv_start_rxtx(dev);
4710                 spin_unlock(&np->lock);
4711                 netif_addr_unlock(dev);
4712                 netif_tx_unlock_bh(dev);
4713                 nv_napi_enable(dev);
4714                 nv_enable_irq(dev);
4715         }
4716         return 0;
4717 exit:
4718         return -ENOMEM;
4719 }
4720
4721 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4722 {
4723         struct fe_priv *np = netdev_priv(dev);
4724
4725         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4726         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4727         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4728 }
4729
4730 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4731 {
4732         struct fe_priv *np = netdev_priv(dev);
4733         int adv, bmcr;
4734
4735         if ((!np->autoneg && np->duplex == 0) ||
4736             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4737                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4738                        dev->name);
4739                 return -EINVAL;
4740         }
4741         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4742                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4743                 return -EINVAL;
4744         }
4745
4746         netif_carrier_off(dev);
4747         if (netif_running(dev)) {
4748                 nv_disable_irq(dev);
4749                 netif_tx_lock_bh(dev);
4750                 netif_addr_lock(dev);
4751                 spin_lock(&np->lock);
4752                 /* stop engines */
4753                 nv_stop_rxtx(dev);
4754                 spin_unlock(&np->lock);
4755                 netif_addr_unlock(dev);
4756                 netif_tx_unlock_bh(dev);
4757         }
4758
4759         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4760         if (pause->rx_pause)
4761                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4762         if (pause->tx_pause)
4763                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4764
4765         if (np->autoneg && pause->autoneg) {
4766                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4767
4768                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4769                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4770                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4771                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4772                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4773                         adv |=  ADVERTISE_PAUSE_ASYM;
4774                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4775
4776                 if (netif_running(dev))
4777                         printk(KERN_INFO "%s: link down.\n", dev->name);
4778                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4779                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4780                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4781         } else {
4782                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4783                 if (pause->rx_pause)
4784                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4785                 if (pause->tx_pause)
4786                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4787
4788                 if (!netif_running(dev))
4789                         nv_update_linkspeed(dev);
4790                 else
4791                         nv_update_pause(dev, np->pause_flags);
4792         }
4793
4794         if (netif_running(dev)) {
4795                 nv_start_rxtx(dev);
4796                 nv_enable_irq(dev);
4797         }
4798         return 0;
4799 }
4800
4801 static u32 nv_get_rx_csum(struct net_device *dev)
4802 {
4803         struct fe_priv *np = netdev_priv(dev);
4804         return (np->rx_csum) != 0;
4805 }
4806
4807 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4808 {
4809         struct fe_priv *np = netdev_priv(dev);
4810         u8 __iomem *base = get_hwbase(dev);
4811         int retcode = 0;
4812
4813         if (np->driver_data & DEV_HAS_CHECKSUM) {
4814                 if (data) {
4815                         np->rx_csum = 1;
4816                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4817                 } else {
4818                         np->rx_csum = 0;
4819                         /* vlan is dependent on rx checksum offload */
4820                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4821                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4822                 }
4823                 if (netif_running(dev)) {
4824                         spin_lock_irq(&np->lock);
4825                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4826                         spin_unlock_irq(&np->lock);
4827                 }
4828         } else {
4829                 return -EINVAL;
4830         }
4831
4832         return retcode;
4833 }
4834
4835 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4836 {
4837         struct fe_priv *np = netdev_priv(dev);
4838
4839         if (np->driver_data & DEV_HAS_CHECKSUM)
4840                 return ethtool_op_set_tx_csum(dev, data);
4841         else
4842                 return -EOPNOTSUPP;
4843 }
4844
4845 static int nv_set_sg(struct net_device *dev, u32 data)
4846 {
4847         struct fe_priv *np = netdev_priv(dev);
4848
4849         if (np->driver_data & DEV_HAS_CHECKSUM)
4850                 return ethtool_op_set_sg(dev, data);
4851         else
4852                 return -EOPNOTSUPP;
4853 }
4854
4855 static int nv_get_sset_count(struct net_device *dev, int sset)
4856 {
4857         struct fe_priv *np = netdev_priv(dev);
4858
4859         switch (sset) {
4860         case ETH_SS_TEST:
4861                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4862                         return NV_TEST_COUNT_EXTENDED;
4863                 else
4864                         return NV_TEST_COUNT_BASE;
4865         case ETH_SS_STATS:
4866                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4867                         return NV_DEV_STATISTICS_V3_COUNT;
4868                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4869                         return NV_DEV_STATISTICS_V2_COUNT;
4870                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4871                         return NV_DEV_STATISTICS_V1_COUNT;
4872                 else
4873                         return 0;
4874         default:
4875                 return -EOPNOTSUPP;
4876         }
4877 }
4878
4879 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4880 {
4881         struct fe_priv *np = netdev_priv(dev);
4882
4883         /* update stats */
4884         nv_do_stats_poll((unsigned long)dev);
4885
4886         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4887 }
4888
4889 static int nv_link_test(struct net_device *dev)
4890 {
4891         struct fe_priv *np = netdev_priv(dev);
4892         int mii_status;
4893
4894         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4895         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4896
4897         /* check phy link status */
4898         if (!(mii_status & BMSR_LSTATUS))
4899                 return 0;
4900         else
4901                 return 1;
4902 }
4903
4904 static int nv_register_test(struct net_device *dev)
4905 {
4906         u8 __iomem *base = get_hwbase(dev);
4907         int i = 0;
4908         u32 orig_read, new_read;
4909
4910         do {
4911                 orig_read = readl(base + nv_registers_test[i].reg);
4912
4913                 /* xor with mask to toggle bits */
4914                 orig_read ^= nv_registers_test[i].mask;
4915
4916                 writel(orig_read, base + nv_registers_test[i].reg);
4917
4918                 new_read = readl(base + nv_registers_test[i].reg);
4919
4920                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4921                         return 0;
4922
4923                 /* restore original value */
4924                 orig_read ^= nv_registers_test[i].mask;
4925                 writel(orig_read, base + nv_registers_test[i].reg);
4926
4927         } while (nv_registers_test[++i].reg != 0);
4928
4929         return 1;
4930 }
4931
4932 static int nv_interrupt_test(struct net_device *dev)
4933 {
4934         struct fe_priv *np = netdev_priv(dev);
4935         u8 __iomem *base = get_hwbase(dev);
4936         int ret = 1;
4937         int testcnt;
4938         u32 save_msi_flags, save_poll_interval = 0;
4939
4940         if (netif_running(dev)) {
4941                 /* free current irq */
4942                 nv_free_irq(dev);
4943                 save_poll_interval = readl(base+NvRegPollingInterval);
4944         }
4945
4946         /* flag to test interrupt handler */
4947         np->intr_test = 0;
4948
4949         /* setup test irq */
4950         save_msi_flags = np->msi_flags;
4951         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4952         np->msi_flags |= 0x001; /* setup 1 vector */
4953         if (nv_request_irq(dev, 1))
4954                 return 0;
4955
4956         /* setup timer interrupt */
4957         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4958         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4959
4960         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4961
4962         /* wait for at least one interrupt */
4963         msleep(100);
4964
4965         spin_lock_irq(&np->lock);
4966
4967         /* flag should be set within ISR */
4968         testcnt = np->intr_test;
4969         if (!testcnt)
4970                 ret = 2;
4971
4972         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4973         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4974                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4975         else
4976                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4977
4978         spin_unlock_irq(&np->lock);
4979
4980         nv_free_irq(dev);
4981
4982         np->msi_flags = save_msi_flags;
4983
4984         if (netif_running(dev)) {
4985                 writel(save_poll_interval, base + NvRegPollingInterval);
4986                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4987                 /* restore original irq */
4988                 if (nv_request_irq(dev, 0))
4989                         return 0;
4990         }
4991
4992         return ret;
4993 }
4994
4995 static int nv_loopback_test(struct net_device *dev)
4996 {
4997         struct fe_priv *np = netdev_priv(dev);
4998         u8 __iomem *base = get_hwbase(dev);
4999         struct sk_buff *tx_skb, *rx_skb;
5000         dma_addr_t test_dma_addr;
5001         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5002         u32 flags;
5003         int len, i, pkt_len;
5004         u8 *pkt_data;
5005         u32 filter_flags = 0;
5006         u32 misc1_flags = 0;
5007         int ret = 1;
5008
5009         if (netif_running(dev)) {
5010                 nv_disable_irq(dev);
5011                 filter_flags = readl(base + NvRegPacketFilterFlags);
5012                 misc1_flags = readl(base + NvRegMisc1);
5013         } else {
5014                 nv_txrx_reset(dev);
5015         }
5016
5017         /* reinit driver view of the rx queue */
5018         set_bufsize(dev);
5019         nv_init_ring(dev);
5020
5021         /* setup hardware for loopback */
5022         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5023         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5024
5025         /* reinit nic view of the rx queue */
5026         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5027         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5028         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5029                 base + NvRegRingSizes);
5030         pci_push(base);
5031
5032         /* restart rx engine */
5033         nv_start_rxtx(dev);
5034
5035         /* setup packet for tx */
5036         pkt_len = ETH_DATA_LEN;
5037         tx_skb = dev_alloc_skb(pkt_len);
5038         if (!tx_skb) {
5039                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5040                          " of %s\n", dev->name);
5041                 ret = 0;
5042                 goto out;
5043         }
5044         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5045                                        skb_tailroom(tx_skb),
5046                                        PCI_DMA_FROMDEVICE);
5047         pkt_data = skb_put(tx_skb, pkt_len);
5048         for (i = 0; i < pkt_len; i++)
5049                 pkt_data[i] = (u8)(i & 0xff);
5050
5051         if (!nv_optimized(np)) {
5052                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5053                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5054         } else {
5055                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5056                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5057                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5058         }
5059         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5060         pci_push(get_hwbase(dev));
5061
5062         msleep(500);
5063
5064         /* check for rx of the packet */
5065         if (!nv_optimized(np)) {
5066                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5067                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5068
5069         } else {
5070                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5071                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5072         }
5073
5074         if (flags & NV_RX_AVAIL) {
5075                 ret = 0;
5076         } else if (np->desc_ver == DESC_VER_1) {
5077                 if (flags & NV_RX_ERROR)
5078                         ret = 0;
5079         } else {
5080                 if (flags & NV_RX2_ERROR) {
5081                         ret = 0;
5082                 }
5083         }
5084
5085         if (ret) {
5086                 if (len != pkt_len) {
5087                         ret = 0;
5088                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5089                                 dev->name, len, pkt_len);
5090                 } else {
5091                         rx_skb = np->rx_skb[0].skb;
5092                         for (i = 0; i < pkt_len; i++) {
5093                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5094                                         ret = 0;
5095                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5096                                                 dev->name, i);
5097                                         break;
5098                                 }
5099                         }
5100                 }
5101         } else {
5102                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5103         }
5104
5105         pci_unmap_single(np->pci_dev, test_dma_addr,
5106                        (skb_end_pointer(tx_skb) - tx_skb->data),
5107                        PCI_DMA_TODEVICE);
5108         dev_kfree_skb_any(tx_skb);
5109  out:
5110         /* stop engines */
5111         nv_stop_rxtx(dev);
5112         nv_txrx_reset(dev);
5113         /* drain rx queue */
5114         nv_drain_rxtx(dev);
5115
5116         if (netif_running(dev)) {
5117                 writel(misc1_flags, base + NvRegMisc1);
5118                 writel(filter_flags, base + NvRegPacketFilterFlags);
5119                 nv_enable_irq(dev);
5120         }
5121
5122         return ret;
5123 }
5124
5125 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5126 {
5127         struct fe_priv *np = netdev_priv(dev);
5128         u8 __iomem *base = get_hwbase(dev);
5129         int result;
5130         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5131
5132         if (!nv_link_test(dev)) {
5133                 test->flags |= ETH_TEST_FL_FAILED;
5134                 buffer[0] = 1;
5135         }
5136
5137         if (test->flags & ETH_TEST_FL_OFFLINE) {
5138                 if (netif_running(dev)) {
5139                         netif_stop_queue(dev);
5140                         nv_napi_disable(dev);
5141                         netif_tx_lock_bh(dev);
5142                         netif_addr_lock(dev);
5143                         spin_lock_irq(&np->lock);
5144                         nv_disable_hw_interrupts(dev, np->irqmask);
5145                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5146                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5147                         } else {
5148                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5149                         }
5150                         /* stop engines */
5151                         nv_stop_rxtx(dev);
5152                         nv_txrx_reset(dev);
5153                         /* drain rx queue */
5154                         nv_drain_rxtx(dev);
5155                         spin_unlock_irq(&np->lock);
5156                         netif_addr_unlock(dev);
5157                         netif_tx_unlock_bh(dev);
5158                 }
5159
5160                 if (!nv_register_test(dev)) {
5161                         test->flags |= ETH_TEST_FL_FAILED;
5162                         buffer[1] = 1;
5163                 }
5164
5165                 result = nv_interrupt_test(dev);
5166                 if (result != 1) {
5167                         test->flags |= ETH_TEST_FL_FAILED;
5168                         buffer[2] = 1;
5169                 }
5170                 if (result == 0) {
5171                         /* bail out */
5172                         return;
5173                 }
5174
5175                 if (!nv_loopback_test(dev)) {
5176                         test->flags |= ETH_TEST_FL_FAILED;
5177                         buffer[3] = 1;
5178                 }
5179
5180                 if (netif_running(dev)) {
5181                         /* reinit driver view of the rx queue */
5182                         set_bufsize(dev);
5183                         if (nv_init_ring(dev)) {
5184                                 if (!np->in_shutdown)
5185                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5186                         }
5187                         /* reinit nic view of the rx queue */
5188                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5189                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5190                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5191                                 base + NvRegRingSizes);
5192                         pci_push(base);
5193                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5194                         pci_push(base);
5195                         /* restart rx engine */
5196                         nv_start_rxtx(dev);
5197                         netif_start_queue(dev);
5198                         nv_napi_enable(dev);
5199                         nv_enable_hw_interrupts(dev, np->irqmask);
5200                 }
5201         }
5202 }
5203
5204 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5205 {
5206         switch (stringset) {
5207         case ETH_SS_STATS:
5208                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5209                 break;
5210         case ETH_SS_TEST:
5211                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5212                 break;
5213         }
5214 }
5215
5216 static const struct ethtool_ops ops = {
5217         .get_drvinfo = nv_get_drvinfo,
5218         .get_link = ethtool_op_get_link,
5219         .get_wol = nv_get_wol,
5220         .set_wol = nv_set_wol,
5221         .get_settings = nv_get_settings,
5222         .set_settings = nv_set_settings,
5223         .get_regs_len = nv_get_regs_len,
5224         .get_regs = nv_get_regs,
5225         .nway_reset = nv_nway_reset,
5226         .set_tso = nv_set_tso,
5227         .get_ringparam = nv_get_ringparam,
5228         .set_ringparam = nv_set_ringparam,
5229         .get_pauseparam = nv_get_pauseparam,
5230         .set_pauseparam = nv_set_pauseparam,
5231         .get_rx_csum = nv_get_rx_csum,
5232         .set_rx_csum = nv_set_rx_csum,
5233         .set_tx_csum = nv_set_tx_csum,
5234         .set_sg = nv_set_sg,
5235         .get_strings = nv_get_strings,
5236         .get_ethtool_stats = nv_get_ethtool_stats,
5237         .get_sset_count = nv_get_sset_count,
5238         .self_test = nv_self_test,
5239 };
5240
5241 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5242 {
5243         struct fe_priv *np = get_nvpriv(dev);
5244
5245         spin_lock_irq(&np->lock);
5246
5247         /* save vlan group */
5248         np->vlangrp = grp;
5249
5250         if (grp) {
5251                 /* enable vlan on MAC */
5252                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5253         } else {
5254                 /* disable vlan on MAC */
5255                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5256                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5257         }
5258
5259         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5260
5261         spin_unlock_irq(&np->lock);
5262 }
5263
5264 /* The mgmt unit and driver use a semaphore to access the phy during init */
5265 static int nv_mgmt_acquire_sema(struct net_device *dev)
5266 {
5267         struct fe_priv *np = netdev_priv(dev);
5268         u8 __iomem *base = get_hwbase(dev);
5269         int i;
5270         u32 tx_ctrl, mgmt_sema;
5271
5272         for (i = 0; i < 10; i++) {
5273                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5274                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5275                         break;
5276                 msleep(500);
5277         }
5278
5279         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5280                 return 0;
5281
5282         for (i = 0; i < 2; i++) {
5283                 tx_ctrl = readl(base + NvRegTransmitterControl);
5284                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5285                 writel(tx_ctrl, base + NvRegTransmitterControl);
5286
5287                 /* verify that semaphore was acquired */
5288                 tx_ctrl = readl(base + NvRegTransmitterControl);
5289                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5290                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5291                         np->mgmt_sema = 1;
5292                         return 1;
5293                 }
5294                 else
5295                         udelay(50);
5296         }
5297
5298         return 0;
5299 }
5300
5301 static void nv_mgmt_release_sema(struct net_device *dev)
5302 {
5303         struct fe_priv *np = netdev_priv(dev);
5304         u8 __iomem *base = get_hwbase(dev);
5305         u32 tx_ctrl;
5306
5307         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5308                 if (np->mgmt_sema) {
5309                         tx_ctrl = readl(base + NvRegTransmitterControl);
5310                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5311                         writel(tx_ctrl, base + NvRegTransmitterControl);
5312                 }
5313         }
5314 }
5315
5316
5317 static int nv_mgmt_get_version(struct net_device *dev)
5318 {
5319         struct fe_priv *np = netdev_priv(dev);
5320         u8 __iomem *base = get_hwbase(dev);
5321         u32 data_ready = readl(base + NvRegTransmitterControl);
5322         u32 data_ready2 = 0;
5323         unsigned long start;
5324         int ready = 0;
5325
5326         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5327         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5328         start = jiffies;
5329         while (time_before(jiffies, start + 5*HZ)) {
5330                 data_ready2 = readl(base + NvRegTransmitterControl);
5331                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5332                         ready = 1;
5333                         break;
5334                 }
5335                 schedule_timeout_uninterruptible(1);
5336         }
5337
5338         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5339                 return 0;
5340
5341         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5342
5343         return 1;
5344 }
5345
5346 static int nv_open(struct net_device *dev)
5347 {
5348         struct fe_priv *np = netdev_priv(dev);
5349         u8 __iomem *base = get_hwbase(dev);
5350         int ret = 1;
5351         int oom, i;
5352         u32 low;
5353
5354         dprintk(KERN_DEBUG "nv_open: begin\n");
5355
5356         /* power up phy */
5357         mii_rw(dev, np->phyaddr, MII_BMCR,
5358                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5359
5360         nv_txrx_gate(dev, false);
5361         /* erase previous misconfiguration */
5362         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5363                 nv_mac_reset(dev);
5364         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5365         writel(0, base + NvRegMulticastAddrB);
5366         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5367         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5368         writel(0, base + NvRegPacketFilterFlags);
5369
5370         writel(0, base + NvRegTransmitterControl);
5371         writel(0, base + NvRegReceiverControl);
5372
5373         writel(0, base + NvRegAdapterControl);
5374
5375         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5376                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5377
5378         /* initialize descriptor rings */
5379         set_bufsize(dev);
5380         oom = nv_init_ring(dev);
5381
5382         writel(0, base + NvRegLinkSpeed);
5383         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5384         nv_txrx_reset(dev);
5385         writel(0, base + NvRegUnknownSetupReg6);
5386
5387         np->in_shutdown = 0;
5388
5389         /* give hw rings */
5390         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5391         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5392                 base + NvRegRingSizes);
5393
5394         writel(np->linkspeed, base + NvRegLinkSpeed);
5395         if (np->desc_ver == DESC_VER_1)
5396                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5397         else
5398                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5399         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5400         writel(np->vlanctl_bits, base + NvRegVlanControl);
5401         pci_push(base);
5402         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5403         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5404                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5405                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5406
5407         writel(0, base + NvRegMIIMask);
5408         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5409         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5410
5411         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5412         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5413         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5414         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5415
5416         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5417
5418         get_random_bytes(&low, sizeof(low));
5419         low &= NVREG_SLOTTIME_MASK;
5420         if (np->desc_ver == DESC_VER_1) {
5421                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5422         } else {
5423                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5424                         /* setup legacy backoff */
5425                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5426                 } else {
5427                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5428                         nv_gear_backoff_reseed(dev);
5429                 }
5430         }
5431         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5432         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5433         if (poll_interval == -1) {
5434                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5435                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5436                 else
5437                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5438         }
5439         else
5440                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5441         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5442         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5443                         base + NvRegAdapterControl);
5444         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5445         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5446         if (np->wolenabled)
5447                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5448
5449         i = readl(base + NvRegPowerState);
5450         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5451                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5452
5453         pci_push(base);
5454         udelay(10);
5455         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5456
5457         nv_disable_hw_interrupts(dev, np->irqmask);
5458         pci_push(base);
5459         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5460         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5461         pci_push(base);
5462
5463         if (nv_request_irq(dev, 0)) {
5464                 goto out_drain;
5465         }
5466
5467         /* ask for interrupts */
5468         nv_enable_hw_interrupts(dev, np->irqmask);
5469
5470         spin_lock_irq(&np->lock);
5471         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5472         writel(0, base + NvRegMulticastAddrB);
5473         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5474         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5475         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5476         /* One manual link speed update: Interrupts are enabled, future link
5477          * speed changes cause interrupts and are handled by nv_link_irq().
5478          */
5479         {
5480                 u32 miistat;
5481                 miistat = readl(base + NvRegMIIStatus);
5482                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5483                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5484         }
5485         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5486          * to init hw */
5487         np->linkspeed = 0;
5488         ret = nv_update_linkspeed(dev);
5489         nv_start_rxtx(dev);
5490         netif_start_queue(dev);
5491         nv_napi_enable(dev);
5492
5493         if (ret) {
5494                 netif_carrier_on(dev);
5495         } else {
5496                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5497                 netif_carrier_off(dev);
5498         }
5499         if (oom)
5500                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5501
5502         /* start statistics timer */
5503         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5504                 mod_timer(&np->stats_poll,
5505                         round_jiffies(jiffies + STATS_INTERVAL));
5506
5507         spin_unlock_irq(&np->lock);
5508
5509         return 0;
5510 out_drain:
5511         nv_drain_rxtx(dev);
5512         return ret;
5513 }
5514
5515 static int nv_close(struct net_device *dev)
5516 {
5517         struct fe_priv *np = netdev_priv(dev);
5518         u8 __iomem *base;
5519
5520         spin_lock_irq(&np->lock);
5521         np->in_shutdown = 1;
5522         spin_unlock_irq(&np->lock);
5523         nv_napi_disable(dev);
5524         synchronize_irq(np->pci_dev->irq);
5525
5526         del_timer_sync(&np->oom_kick);
5527         del_timer_sync(&np->nic_poll);
5528         del_timer_sync(&np->stats_poll);
5529
5530         netif_stop_queue(dev);
5531         spin_lock_irq(&np->lock);
5532         nv_stop_rxtx(dev);
5533         nv_txrx_reset(dev);
5534
5535         /* disable interrupts on the nic or we will lock up */
5536         base = get_hwbase(dev);
5537         nv_disable_hw_interrupts(dev, np->irqmask);
5538         pci_push(base);
5539         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5540
5541         spin_unlock_irq(&np->lock);
5542
5543         nv_free_irq(dev);
5544
5545         nv_drain_rxtx(dev);
5546
5547         if (np->wolenabled || !phy_power_down) {
5548                 nv_txrx_gate(dev, false);
5549                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5550                 nv_start_rx(dev);
5551         } else {
5552                 /* power down phy */
5553                 mii_rw(dev, np->phyaddr, MII_BMCR,
5554                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5555                 nv_txrx_gate(dev, true);
5556         }
5557
5558         /* FIXME: power down nic */
5559
5560         return 0;
5561 }
5562
5563 static const struct net_device_ops nv_netdev_ops = {
5564         .ndo