forcedeth: realtek phy crossover detection
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.61"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk                 printk
69 #else
70 #define dprintk(x...)           do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP  64
74 #define RX_WORK_PER_LOOP  64
75
76 /*
77  * Hardware access:
78  */
79
80 #define DEV_NEED_TIMERIRQ          0x00001  /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER         0x00002  /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC          0x00004  /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA           0x00008  /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM           0x00010  /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN               0x00020  /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI                0x00040  /* device supports MSI */
87 #define DEV_HAS_MSI_X              0x00080  /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL        0x00100  /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1      0x00200  /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2      0x00400  /* device supports hw statistics version 2 */
91 #define DEV_HAS_TEST_EXTENDED      0x00800  /* device supports extended diagnostic test */
92 #define DEV_HAS_MGMT_UNIT          0x01000  /* device supports management unit */
93 #define DEV_HAS_CORRECT_MACADDR    0x02000  /* device supports correct mac address order */
94 #define DEV_HAS_COLLISION_FIX      0x04000  /* device supports tx collision fix */
95 #define DEV_HAS_PAUSEFRAME_TX_V1   0x08000  /* device supports tx pause frames version 1 */
96 #define DEV_HAS_PAUSEFRAME_TX_V2   0x10000  /* device supports tx pause frames version 2 */
97 #define DEV_HAS_PAUSEFRAME_TX_V3   0x20000  /* device supports tx pause frames version 3 */
98 #define DEV_NEED_TX_LIMIT          0x40000  /* device needs to limit tx */
99 #define DEV_HAS_GEAR_MODE          0x80000  /* device supports gear mode */
100
101 enum {
102         NvRegIrqStatus = 0x000,
103 #define NVREG_IRQSTAT_MIIEVENT  0x040
104 #define NVREG_IRQSTAT_MASK              0x81ff
105         NvRegIrqMask = 0x004,
106 #define NVREG_IRQ_RX_ERROR              0x0001
107 #define NVREG_IRQ_RX                    0x0002
108 #define NVREG_IRQ_RX_NOBUF              0x0004
109 #define NVREG_IRQ_TX_ERR                0x0008
110 #define NVREG_IRQ_TX_OK                 0x0010
111 #define NVREG_IRQ_TIMER                 0x0020
112 #define NVREG_IRQ_LINK                  0x0040
113 #define NVREG_IRQ_RX_FORCED             0x0080
114 #define NVREG_IRQ_TX_FORCED             0x0100
115 #define NVREG_IRQ_RECOVER_ERROR         0x8000
116 #define NVREG_IRQMASK_THROUGHPUT        0x00df
117 #define NVREG_IRQMASK_CPU               0x0060
118 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
119 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
120 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
121
122 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
123                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
124                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
125
126         NvRegUnknownSetupReg6 = 0x008,
127 #define NVREG_UNKSETUP6_VAL             3
128
129 /*
130  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
131  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
132  */
133         NvRegPollingInterval = 0x00c,
134 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
135 #define NVREG_POLL_DEFAULT_CPU  13
136         NvRegMSIMap0 = 0x020,
137         NvRegMSIMap1 = 0x024,
138         NvRegMSIIrqMask = 0x030,
139 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
140         NvRegMisc1 = 0x080,
141 #define NVREG_MISC1_PAUSE_TX    0x01
142 #define NVREG_MISC1_HD          0x02
143 #define NVREG_MISC1_FORCE       0x3b0f3c
144
145         NvRegMacReset = 0x34,
146 #define NVREG_MAC_RESET_ASSERT  0x0F3
147         NvRegTransmitterControl = 0x084,
148 #define NVREG_XMITCTL_START     0x01
149 #define NVREG_XMITCTL_MGMT_ST   0x40000000
150 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
151 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
152 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
153 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
154 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
155 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
156 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
157 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
158 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
159         NvRegTransmitterStatus = 0x088,
160 #define NVREG_XMITSTAT_BUSY     0x01
161
162         NvRegPacketFilterFlags = 0x8c,
163 #define NVREG_PFF_PAUSE_RX      0x08
164 #define NVREG_PFF_ALWAYS        0x7F0000
165 #define NVREG_PFF_PROMISC       0x80
166 #define NVREG_PFF_MYADDR        0x20
167 #define NVREG_PFF_LOOPBACK      0x10
168
169         NvRegOffloadConfig = 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY   0x601
171 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
172         NvRegReceiverControl = 0x094,
173 #define NVREG_RCVCTL_START      0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175         NvRegReceiverStatus = 0x98,
176 #define NVREG_RCVSTAT_BUSY      0x01
177
178         NvRegSlotTime = 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
182 #define NVREG_SLOTTIME_HALF             0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
184 #define NVREG_SLOTTIME_MASK             0x000000ff
185
186         NvRegTxDeferral = 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
193         NvRegRxDeferral = 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
195         NvRegMacAddrA = 0xA8,
196         NvRegMacAddrB = 0xAC,
197         NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE  0x01
199         NvRegMulticastAddrB = 0xB4,
200         NvRegMulticastMaskA = 0xB8,
201 #define NVREG_MCASTMASKA_NONE           0xffffffff
202         NvRegMulticastMaskB = 0xBC,
203 #define NVREG_MCASTMASKB_NONE           0xffff
204
205         NvRegPhyInterface = 0xC0,
206 #define PHY_RGMII               0x10000000
207         NvRegBackOffControl = 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT                  24
211 #define NVREG_BKOFFCTRL_GEAR                    12
212
213         NvRegTxRingPhysAddr = 0x100,
214         NvRegRxRingPhysAddr = 0x104,
215         NvRegRingSizes = 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218         NvRegTransmitPoll = 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220         NvRegLinkSpeed = 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10      1000
223 #define NVREG_LINKSPEED_100     100
224 #define NVREG_LINKSPEED_1000    50
225 #define NVREG_LINKSPEED_MASK    (0xFFF)
226         NvRegUnknownSetupReg5 = 0x130,
227 #define NVREG_UNKSETUP5_BIT31   (1<<31)
228         NvRegTxWatermark = 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
232         NvRegTxRxControl = 0x144,
233 #define NVREG_TXRXCTL_KICK      0x0001
234 #define NVREG_TXRXCTL_BIT1      0x0002
235 #define NVREG_TXRXCTL_BIT2      0x0004
236 #define NVREG_TXRXCTL_IDLE      0x0008
237 #define NVREG_TXRXCTL_RESET     0x0010
238 #define NVREG_TXRXCTL_RXCHECK   0x0400
239 #define NVREG_TXRXCTL_DESC_1    0
240 #define NVREG_TXRXCTL_DESC_2    0x002100
241 #define NVREG_TXRXCTL_DESC_3    0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS   0x00080
244         NvRegTxRingPhysAddrHigh = 0x148,
245         NvRegRxRingPhysAddrHigh = 0x14C,
246         NvRegTxPauseFrame = 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
251         NvRegMIIStatus = 0x180,
252 #define NVREG_MIISTAT_ERROR             0x0001
253 #define NVREG_MIISTAT_LINKCHANGE        0x0008
254 #define NVREG_MIISTAT_MASK_RW           0x0007
255 #define NVREG_MIISTAT_MASK_ALL          0x000f
256         NvRegMIIMask = 0x184,
257 #define NVREG_MII_LINKCHANGE            0x0008
258
259         NvRegAdapterControl = 0x188,
260 #define NVREG_ADAPTCTL_START    0x02
261 #define NVREG_ADAPTCTL_LINKUP   0x04
262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
263 #define NVREG_ADAPTCTL_RUNNING  0x100000
264 #define NVREG_ADAPTCTL_PHYSHIFT 24
265         NvRegMIISpeed = 0x18c,
266 #define NVREG_MIISPEED_BIT8     (1<<8)
267 #define NVREG_MIIDELAY  5
268         NvRegMIIControl = 0x190,
269 #define NVREG_MIICTL_INUSE      0x08000
270 #define NVREG_MIICTL_WRITE      0x00400
271 #define NVREG_MIICTL_ADDRSHIFT  5
272         NvRegMIIData = 0x194,
273         NvRegWakeUpFlags = 0x200,
274 #define NVREG_WAKEUPFLAGS_VAL           0x7770
275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
277 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
278 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
279 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
280 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
284 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
285
286         NvRegPatternCRC = 0x204,
287         NvRegPatternMask = 0x208,
288         NvRegPowerCap = 0x268,
289 #define NVREG_POWERCAP_D3SUPP   (1<<30)
290 #define NVREG_POWERCAP_D2SUPP   (1<<26)
291 #define NVREG_POWERCAP_D1SUPP   (1<<25)
292         NvRegPowerState = 0x26c,
293 #define NVREG_POWERSTATE_POWEREDUP      0x8000
294 #define NVREG_POWERSTATE_VALID          0x0100
295 #define NVREG_POWERSTATE_MASK           0x0003
296 #define NVREG_POWERSTATE_D0             0x0000
297 #define NVREG_POWERSTATE_D1             0x0001
298 #define NVREG_POWERSTATE_D2             0x0002
299 #define NVREG_POWERSTATE_D3             0x0003
300         NvRegTxCnt = 0x280,
301         NvRegTxZeroReXmt = 0x284,
302         NvRegTxOneReXmt = 0x288,
303         NvRegTxManyReXmt = 0x28c,
304         NvRegTxLateCol = 0x290,
305         NvRegTxUnderflow = 0x294,
306         NvRegTxLossCarrier = 0x298,
307         NvRegTxExcessDef = 0x29c,
308         NvRegTxRetryErr = 0x2a0,
309         NvRegRxFrameErr = 0x2a4,
310         NvRegRxExtraByte = 0x2a8,
311         NvRegRxLateCol = 0x2ac,
312         NvRegRxRunt = 0x2b0,
313         NvRegRxFrameTooLong = 0x2b4,
314         NvRegRxOverflow = 0x2b8,
315         NvRegRxFCSErr = 0x2bc,
316         NvRegRxFrameAlignErr = 0x2c0,
317         NvRegRxLenErr = 0x2c4,
318         NvRegRxUnicast = 0x2c8,
319         NvRegRxMulticast = 0x2cc,
320         NvRegRxBroadcast = 0x2d0,
321         NvRegTxDef = 0x2d4,
322         NvRegTxFrame = 0x2d8,
323         NvRegRxCnt = 0x2dc,
324         NvRegTxPause = 0x2e0,
325         NvRegRxPause = 0x2e4,
326         NvRegRxDropFrame = 0x2e8,
327         NvRegVlanControl = 0x300,
328 #define NVREG_VLANCONTROL_ENABLE        0x2000
329         NvRegMSIXMap0 = 0x3e0,
330         NvRegMSIXMap1 = 0x3e4,
331         NvRegMSIXIrqStatus = 0x3f0,
332
333         NvRegPowerState2 = 0x600,
334 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
335 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
336 };
337
338 /* Big endian: should work, but is untested */
339 struct ring_desc {
340         __le32 buf;
341         __le32 flaglen;
342 };
343
344 struct ring_desc_ex {
345         __le32 bufhigh;
346         __le32 buflow;
347         __le32 txvlan;
348         __le32 flaglen;
349 };
350
351 union ring_type {
352         struct ring_desc* orig;
353         struct ring_desc_ex* ex;
354 };
355
356 #define FLAG_MASK_V1 0xffff0000
357 #define FLAG_MASK_V2 0xffffc000
358 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
359 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
360
361 #define NV_TX_LASTPACKET        (1<<16)
362 #define NV_TX_RETRYERROR        (1<<19)
363 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
364 #define NV_TX_FORCED_INTERRUPT  (1<<24)
365 #define NV_TX_DEFERRED          (1<<26)
366 #define NV_TX_CARRIERLOST       (1<<27)
367 #define NV_TX_LATECOLLISION     (1<<28)
368 #define NV_TX_UNDERFLOW         (1<<29)
369 #define NV_TX_ERROR             (1<<30)
370 #define NV_TX_VALID             (1<<31)
371
372 #define NV_TX2_LASTPACKET       (1<<29)
373 #define NV_TX2_RETRYERROR       (1<<18)
374 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
375 #define NV_TX2_FORCED_INTERRUPT (1<<30)
376 #define NV_TX2_DEFERRED         (1<<25)
377 #define NV_TX2_CARRIERLOST      (1<<26)
378 #define NV_TX2_LATECOLLISION    (1<<27)
379 #define NV_TX2_UNDERFLOW        (1<<28)
380 /* error and valid are the same for both */
381 #define NV_TX2_ERROR            (1<<30)
382 #define NV_TX2_VALID            (1<<31)
383 #define NV_TX2_TSO              (1<<28)
384 #define NV_TX2_TSO_SHIFT        14
385 #define NV_TX2_TSO_MAX_SHIFT    14
386 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
387 #define NV_TX2_CHECKSUM_L3      (1<<27)
388 #define NV_TX2_CHECKSUM_L4      (1<<26)
389
390 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
391
392 #define NV_RX_DESCRIPTORVALID   (1<<16)
393 #define NV_RX_MISSEDFRAME       (1<<17)
394 #define NV_RX_SUBSTRACT1        (1<<18)
395 #define NV_RX_ERROR1            (1<<23)
396 #define NV_RX_ERROR2            (1<<24)
397 #define NV_RX_ERROR3            (1<<25)
398 #define NV_RX_ERROR4            (1<<26)
399 #define NV_RX_CRCERR            (1<<27)
400 #define NV_RX_OVERFLOW          (1<<28)
401 #define NV_RX_FRAMINGERR        (1<<29)
402 #define NV_RX_ERROR             (1<<30)
403 #define NV_RX_AVAIL             (1<<31)
404
405 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
406 #define NV_RX2_CHECKSUM_IP      (0x10000000)
407 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
408 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
409 #define NV_RX2_DESCRIPTORVALID  (1<<29)
410 #define NV_RX2_SUBSTRACT1       (1<<25)
411 #define NV_RX2_ERROR1           (1<<18)
412 #define NV_RX2_ERROR2           (1<<19)
413 #define NV_RX2_ERROR3           (1<<20)
414 #define NV_RX2_ERROR4           (1<<21)
415 #define NV_RX2_CRCERR           (1<<22)
416 #define NV_RX2_OVERFLOW         (1<<23)
417 #define NV_RX2_FRAMINGERR       (1<<24)
418 /* error and avail are the same for both */
419 #define NV_RX2_ERROR            (1<<30)
420 #define NV_RX2_AVAIL            (1<<31)
421
422 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
423 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
424
425 /* Miscelaneous hardware related defines: */
426 #define NV_PCI_REGSZ_VER1       0x270
427 #define NV_PCI_REGSZ_VER2       0x2d4
428 #define NV_PCI_REGSZ_VER3       0x604
429
430 /* various timeout delays: all in usec */
431 #define NV_TXRX_RESET_DELAY     4
432 #define NV_TXSTOP_DELAY1        10
433 #define NV_TXSTOP_DELAY1MAX     500000
434 #define NV_TXSTOP_DELAY2        100
435 #define NV_RXSTOP_DELAY1        10
436 #define NV_RXSTOP_DELAY1MAX     500000
437 #define NV_RXSTOP_DELAY2        100
438 #define NV_SETUP5_DELAY         5
439 #define NV_SETUP5_DELAYMAX      50000
440 #define NV_POWERUP_DELAY        5
441 #define NV_POWERUP_DELAYMAX     5000
442 #define NV_MIIBUSY_DELAY        50
443 #define NV_MIIPHY_DELAY 10
444 #define NV_MIIPHY_DELAYMAX      10000
445 #define NV_MAC_RESET_DELAY      64
446
447 #define NV_WAKEUPPATTERNS       5
448 #define NV_WAKEUPMASKENTRIES    4
449
450 /* General driver defaults */
451 #define NV_WATCHDOG_TIMEO       (5*HZ)
452
453 #define RX_RING_DEFAULT         128
454 #define TX_RING_DEFAULT         256
455 #define RX_RING_MIN             128
456 #define TX_RING_MIN             64
457 #define RING_MAX_DESC_VER_1     1024
458 #define RING_MAX_DESC_VER_2_3   16384
459
460 /* rx/tx mac addr + type + vlan + align + slack*/
461 #define NV_RX_HEADERS           (64)
462 /* even more slack. */
463 #define NV_RX_ALLOC_PAD         (64)
464
465 /* maximum mtu size */
466 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
467 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
468
469 #define OOM_REFILL      (1+HZ/20)
470 #define POLL_WAIT       (1+HZ/100)
471 #define LINK_TIMEOUT    (3*HZ)
472 #define STATS_INTERVAL  (10*HZ)
473
474 /*
475  * desc_ver values:
476  * The nic supports three different descriptor types:
477  * - DESC_VER_1: Original
478  * - DESC_VER_2: support for jumbo frames.
479  * - DESC_VER_3: 64-bit format.
480  */
481 #define DESC_VER_1      1
482 #define DESC_VER_2      2
483 #define DESC_VER_3      3
484
485 /* PHY defines */
486 #define PHY_OUI_MARVELL         0x5043
487 #define PHY_OUI_CICADA          0x03f1
488 #define PHY_OUI_VITESSE         0x01c1
489 #define PHY_OUI_REALTEK         0x0732
490 #define PHY_OUI_REALTEK2        0x0020
491 #define PHYID1_OUI_MASK 0x03ff
492 #define PHYID1_OUI_SHFT 6
493 #define PHYID2_OUI_MASK 0xfc00
494 #define PHYID2_OUI_SHFT 10
495 #define PHYID2_MODEL_MASK               0x03f0
496 #define PHY_MODEL_REALTEK_8211          0x0110
497 #define PHY_REV_MASK                    0x0001
498 #define PHY_REV_REALTEK_8211B           0x0000
499 #define PHY_REV_REALTEK_8211C           0x0001
500 #define PHY_MODEL_REALTEK_8201          0x0200
501 #define PHY_MODEL_MARVELL_E3016         0x0220
502 #define PHY_MARVELL_E3016_INITMASK      0x0300
503 #define PHY_CICADA_INIT1        0x0f000
504 #define PHY_CICADA_INIT2        0x0e00
505 #define PHY_CICADA_INIT3        0x01000
506 #define PHY_CICADA_INIT4        0x0200
507 #define PHY_CICADA_INIT5        0x0004
508 #define PHY_CICADA_INIT6        0x02000
509 #define PHY_VITESSE_INIT_REG1   0x1f
510 #define PHY_VITESSE_INIT_REG2   0x10
511 #define PHY_VITESSE_INIT_REG3   0x11
512 #define PHY_VITESSE_INIT_REG4   0x12
513 #define PHY_VITESSE_INIT_MSK1   0xc
514 #define PHY_VITESSE_INIT_MSK2   0x0180
515 #define PHY_VITESSE_INIT1       0x52b5
516 #define PHY_VITESSE_INIT2       0xaf8a
517 #define PHY_VITESSE_INIT3       0x8
518 #define PHY_VITESSE_INIT4       0x8f8a
519 #define PHY_VITESSE_INIT5       0xaf86
520 #define PHY_VITESSE_INIT6       0x8f86
521 #define PHY_VITESSE_INIT7       0xaf82
522 #define PHY_VITESSE_INIT8       0x0100
523 #define PHY_VITESSE_INIT9       0x8f82
524 #define PHY_VITESSE_INIT10      0x0
525 #define PHY_REALTEK_INIT_REG1   0x1f
526 #define PHY_REALTEK_INIT_REG2   0x19
527 #define PHY_REALTEK_INIT_REG3   0x13
528 #define PHY_REALTEK_INIT_REG4   0x14
529 #define PHY_REALTEK_INIT_REG5   0x18
530 #define PHY_REALTEK_INIT_REG6   0x11
531 #define PHY_REALTEK_INIT1       0x0000
532 #define PHY_REALTEK_INIT2       0x8e00
533 #define PHY_REALTEK_INIT3       0x0001
534 #define PHY_REALTEK_INIT4       0xad17
535 #define PHY_REALTEK_INIT5       0xfb54
536 #define PHY_REALTEK_INIT6       0xf5c7
537 #define PHY_REALTEK_INIT7       0x1000
538 #define PHY_REALTEK_INIT8       0x0003
539 #define PHY_REALTEK_INIT_MSK1   0x0003
540
541 #define PHY_GIGABIT     0x0100
542
543 #define PHY_TIMEOUT     0x1
544 #define PHY_ERROR       0x2
545
546 #define PHY_100 0x1
547 #define PHY_1000        0x2
548 #define PHY_HALF        0x100
549
550 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
551 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
552 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
553 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
554 #define NV_PAUSEFRAME_RX_REQ     0x0010
555 #define NV_PAUSEFRAME_TX_REQ     0x0020
556 #define NV_PAUSEFRAME_AUTONEG    0x0040
557
558 /* MSI/MSI-X defines */
559 #define NV_MSI_X_MAX_VECTORS  8
560 #define NV_MSI_X_VECTORS_MASK 0x000f
561 #define NV_MSI_CAPABLE        0x0010
562 #define NV_MSI_X_CAPABLE      0x0020
563 #define NV_MSI_ENABLED        0x0040
564 #define NV_MSI_X_ENABLED      0x0080
565
566 #define NV_MSI_X_VECTOR_ALL   0x0
567 #define NV_MSI_X_VECTOR_RX    0x0
568 #define NV_MSI_X_VECTOR_TX    0x1
569 #define NV_MSI_X_VECTOR_OTHER 0x2
570
571 #define NV_RESTART_TX         0x1
572 #define NV_RESTART_RX         0x2
573
574 #define NV_TX_LIMIT_COUNT     16
575
576 /* statistics */
577 struct nv_ethtool_str {
578         char name[ETH_GSTRING_LEN];
579 };
580
581 static const struct nv_ethtool_str nv_estats_str[] = {
582         { "tx_bytes" },
583         { "tx_zero_rexmt" },
584         { "tx_one_rexmt" },
585         { "tx_many_rexmt" },
586         { "tx_late_collision" },
587         { "tx_fifo_errors" },
588         { "tx_carrier_errors" },
589         { "tx_excess_deferral" },
590         { "tx_retry_error" },
591         { "rx_frame_error" },
592         { "rx_extra_byte" },
593         { "rx_late_collision" },
594         { "rx_runt" },
595         { "rx_frame_too_long" },
596         { "rx_over_errors" },
597         { "rx_crc_errors" },
598         { "rx_frame_align_error" },
599         { "rx_length_error" },
600         { "rx_unicast" },
601         { "rx_multicast" },
602         { "rx_broadcast" },
603         { "rx_packets" },
604         { "rx_errors_total" },
605         { "tx_errors_total" },
606
607         /* version 2 stats */
608         { "tx_deferral" },
609         { "tx_packets" },
610         { "rx_bytes" },
611         { "tx_pause" },
612         { "rx_pause" },
613         { "rx_drop_frame" }
614 };
615
616 struct nv_ethtool_stats {
617         u64 tx_bytes;
618         u64 tx_zero_rexmt;
619         u64 tx_one_rexmt;
620         u64 tx_many_rexmt;
621         u64 tx_late_collision;
622         u64 tx_fifo_errors;
623         u64 tx_carrier_errors;
624         u64 tx_excess_deferral;
625         u64 tx_retry_error;
626         u64 rx_frame_error;
627         u64 rx_extra_byte;
628         u64 rx_late_collision;
629         u64 rx_runt;
630         u64 rx_frame_too_long;
631         u64 rx_over_errors;
632         u64 rx_crc_errors;
633         u64 rx_frame_align_error;
634         u64 rx_length_error;
635         u64 rx_unicast;
636         u64 rx_multicast;
637         u64 rx_broadcast;
638         u64 rx_packets;
639         u64 rx_errors_total;
640         u64 tx_errors_total;
641
642         /* version 2 stats */
643         u64 tx_deferral;
644         u64 tx_packets;
645         u64 rx_bytes;
646         u64 tx_pause;
647         u64 rx_pause;
648         u64 rx_drop_frame;
649 };
650
651 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
652 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
653
654 /* diagnostics */
655 #define NV_TEST_COUNT_BASE 3
656 #define NV_TEST_COUNT_EXTENDED 4
657
658 static const struct nv_ethtool_str nv_etests_str[] = {
659         { "link      (online/offline)" },
660         { "register  (offline)       " },
661         { "interrupt (offline)       " },
662         { "loopback  (offline)       " }
663 };
664
665 struct register_test {
666         __u32 reg;
667         __u32 mask;
668 };
669
670 static const struct register_test nv_registers_test[] = {
671         { NvRegUnknownSetupReg6, 0x01 },
672         { NvRegMisc1, 0x03c },
673         { NvRegOffloadConfig, 0x03ff },
674         { NvRegMulticastAddrA, 0xffffffff },
675         { NvRegTxWatermark, 0x0ff },
676         { NvRegWakeUpFlags, 0x07777 },
677         { 0,0 }
678 };
679
680 struct nv_skb_map {
681         struct sk_buff *skb;
682         dma_addr_t dma;
683         unsigned int dma_len;
684         struct ring_desc_ex *first_tx_desc;
685         struct nv_skb_map *next_tx_ctx;
686 };
687
688 /*
689  * SMP locking:
690  * All hardware access under dev->priv->lock, except the performance
691  * critical parts:
692  * - rx is (pseudo-) lockless: it relies on the single-threading provided
693  *      by the arch code for interrupts.
694  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
695  *      needs dev->priv->lock :-(
696  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
697  */
698
699 /* in dev: base, irq */
700 struct fe_priv {
701         spinlock_t lock;
702
703         struct net_device *dev;
704         struct napi_struct napi;
705
706         /* General data:
707          * Locking: spin_lock(&np->lock); */
708         struct nv_ethtool_stats estats;
709         int in_shutdown;
710         u32 linkspeed;
711         int duplex;
712         int autoneg;
713         int fixed_mode;
714         int phyaddr;
715         int wolenabled;
716         unsigned int phy_oui;
717         unsigned int phy_model;
718         unsigned int phy_rev;
719         u16 gigabit;
720         int intr_test;
721         int recover_error;
722
723         /* General data: RO fields */
724         dma_addr_t ring_addr;
725         struct pci_dev *pci_dev;
726         u32 orig_mac[2];
727         u32 irqmask;
728         u32 desc_ver;
729         u32 txrxctl_bits;
730         u32 vlanctl_bits;
731         u32 driver_data;
732         u32 device_id;
733         u32 register_size;
734         int rx_csum;
735         u32 mac_in_use;
736
737         void __iomem *base;
738
739         /* rx specific fields.
740          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
741          */
742         union ring_type get_rx, put_rx, first_rx, last_rx;
743         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
744         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
745         struct nv_skb_map *rx_skb;
746
747         union ring_type rx_ring;
748         unsigned int rx_buf_sz;
749         unsigned int pkt_limit;
750         struct timer_list oom_kick;
751         struct timer_list nic_poll;
752         struct timer_list stats_poll;
753         u32 nic_poll_irq;
754         int rx_ring_size;
755
756         /* media detection workaround.
757          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
758          */
759         int need_linktimer;
760         unsigned long link_timeout;
761         /*
762          * tx specific fields.
763          */
764         union ring_type get_tx, put_tx, first_tx, last_tx;
765         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
766         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
767         struct nv_skb_map *tx_skb;
768
769         union ring_type tx_ring;
770         u32 tx_flags;
771         int tx_ring_size;
772         int tx_limit;
773         u32 tx_pkts_in_progress;
774         struct nv_skb_map *tx_change_owner;
775         struct nv_skb_map *tx_end_flip;
776         int tx_stop;
777
778         /* vlan fields */
779         struct vlan_group *vlangrp;
780
781         /* msi/msi-x fields */
782         u32 msi_flags;
783         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
784
785         /* flow control */
786         u32 pause_flags;
787 };
788
789 /*
790  * Maximum number of loops until we assume that a bit in the irq mask
791  * is stuck. Overridable with module param.
792  */
793 static int max_interrupt_work = 5;
794
795 /*
796  * Optimization can be either throuput mode or cpu mode
797  *
798  * Throughput Mode: Every tx and rx packet will generate an interrupt.
799  * CPU Mode: Interrupts are controlled by a timer.
800  */
801 enum {
802         NV_OPTIMIZATION_MODE_THROUGHPUT,
803         NV_OPTIMIZATION_MODE_CPU
804 };
805 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
806
807 /*
808  * Poll interval for timer irq
809  *
810  * This interval determines how frequent an interrupt is generated.
811  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
812  * Min = 0, and Max = 65535
813  */
814 static int poll_interval = -1;
815
816 /*
817  * MSI interrupts
818  */
819 enum {
820         NV_MSI_INT_DISABLED,
821         NV_MSI_INT_ENABLED
822 };
823 static int msi = NV_MSI_INT_ENABLED;
824
825 /*
826  * MSIX interrupts
827  */
828 enum {
829         NV_MSIX_INT_DISABLED,
830         NV_MSIX_INT_ENABLED
831 };
832 static int msix = NV_MSIX_INT_DISABLED;
833
834 /*
835  * DMA 64bit
836  */
837 enum {
838         NV_DMA_64BIT_DISABLED,
839         NV_DMA_64BIT_ENABLED
840 };
841 static int dma_64bit = NV_DMA_64BIT_ENABLED;
842
843 /*
844  * Crossover Detection
845  * Realtek 8201 phy + some OEM boards do not work properly.
846  */
847 enum {
848         NV_CROSSOVER_DETECTION_DISABLED,
849         NV_CROSSOVER_DETECTION_ENABLED
850 };
851 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
852
853 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
854 {
855         return netdev_priv(dev);
856 }
857
858 static inline u8 __iomem *get_hwbase(struct net_device *dev)
859 {
860         return ((struct fe_priv *)netdev_priv(dev))->base;
861 }
862
863 static inline void pci_push(u8 __iomem *base)
864 {
865         /* force out pending posted writes */
866         readl(base);
867 }
868
869 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
870 {
871         return le32_to_cpu(prd->flaglen)
872                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
873 }
874
875 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
876 {
877         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
878 }
879
880 static bool nv_optimized(struct fe_priv *np)
881 {
882         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
883                 return false;
884         return true;
885 }
886
887 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
888                                 int delay, int delaymax, const char *msg)
889 {
890         u8 __iomem *base = get_hwbase(dev);
891
892         pci_push(base);
893         do {
894                 udelay(delay);
895                 delaymax -= delay;
896                 if (delaymax < 0) {
897                         if (msg)
898                                 printk(msg);
899                         return 1;
900                 }
901         } while ((readl(base + offset) & mask) != target);
902         return 0;
903 }
904
905 #define NV_SETUP_RX_RING 0x01
906 #define NV_SETUP_TX_RING 0x02
907
908 static inline u32 dma_low(dma_addr_t addr)
909 {
910         return addr;
911 }
912
913 static inline u32 dma_high(dma_addr_t addr)
914 {
915         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
916 }
917
918 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
919 {
920         struct fe_priv *np = get_nvpriv(dev);
921         u8 __iomem *base = get_hwbase(dev);
922
923         if (!nv_optimized(np)) {
924                 if (rxtx_flags & NV_SETUP_RX_RING) {
925                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
926                 }
927                 if (rxtx_flags & NV_SETUP_TX_RING) {
928                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
929                 }
930         } else {
931                 if (rxtx_flags & NV_SETUP_RX_RING) {
932                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
933                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
934                 }
935                 if (rxtx_flags & NV_SETUP_TX_RING) {
936                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
937                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
938                 }
939         }
940 }
941
942 static void free_rings(struct net_device *dev)
943 {
944         struct fe_priv *np = get_nvpriv(dev);
945
946         if (!nv_optimized(np)) {
947                 if (np->rx_ring.orig)
948                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
949                                             np->rx_ring.orig, np->ring_addr);
950         } else {
951                 if (np->rx_ring.ex)
952                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
953                                             np->rx_ring.ex, np->ring_addr);
954         }
955         if (np->rx_skb)
956                 kfree(np->rx_skb);
957         if (np->tx_skb)
958                 kfree(np->tx_skb);
959 }
960
961 static int using_multi_irqs(struct net_device *dev)
962 {
963         struct fe_priv *np = get_nvpriv(dev);
964
965         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
966             ((np->msi_flags & NV_MSI_X_ENABLED) &&
967              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
968                 return 0;
969         else
970                 return 1;
971 }
972
973 static void nv_enable_irq(struct net_device *dev)
974 {
975         struct fe_priv *np = get_nvpriv(dev);
976
977         if (!using_multi_irqs(dev)) {
978                 if (np->msi_flags & NV_MSI_X_ENABLED)
979                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
980                 else
981                         enable_irq(np->pci_dev->irq);
982         } else {
983                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
984                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
985                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
986         }
987 }
988
989 static void nv_disable_irq(struct net_device *dev)
990 {
991         struct fe_priv *np = get_nvpriv(dev);
992
993         if (!using_multi_irqs(dev)) {
994                 if (np->msi_flags & NV_MSI_X_ENABLED)
995                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
996                 else
997                         disable_irq(np->pci_dev->irq);
998         } else {
999                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1000                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1001                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1002         }
1003 }
1004
1005 /* In MSIX mode, a write to irqmask behaves as XOR */
1006 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1007 {
1008         u8 __iomem *base = get_hwbase(dev);
1009
1010         writel(mask, base + NvRegIrqMask);
1011 }
1012
1013 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1014 {
1015         struct fe_priv *np = get_nvpriv(dev);
1016         u8 __iomem *base = get_hwbase(dev);
1017
1018         if (np->msi_flags & NV_MSI_X_ENABLED) {
1019                 writel(mask, base + NvRegIrqMask);
1020         } else {
1021                 if (np->msi_flags & NV_MSI_ENABLED)
1022                         writel(0, base + NvRegMSIIrqMask);
1023                 writel(0, base + NvRegIrqMask);
1024         }
1025 }
1026
1027 #define MII_READ        (-1)
1028 /* mii_rw: read/write a register on the PHY.
1029  *
1030  * Caller must guarantee serialization
1031  */
1032 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1033 {
1034         u8 __iomem *base = get_hwbase(dev);
1035         u32 reg;
1036         int retval;
1037
1038         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1039
1040         reg = readl(base + NvRegMIIControl);
1041         if (reg & NVREG_MIICTL_INUSE) {
1042                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1043                 udelay(NV_MIIBUSY_DELAY);
1044         }
1045
1046         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1047         if (value != MII_READ) {
1048                 writel(value, base + NvRegMIIData);
1049                 reg |= NVREG_MIICTL_WRITE;
1050         }
1051         writel(reg, base + NvRegMIIControl);
1052
1053         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1054                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1055                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1056                                 dev->name, miireg, addr);
1057                 retval = -1;
1058         } else if (value != MII_READ) {
1059                 /* it was a write operation - fewer failures are detectable */
1060                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1061                                 dev->name, value, miireg, addr);
1062                 retval = 0;
1063         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1064                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1065                                 dev->name, miireg, addr);
1066                 retval = -1;
1067         } else {
1068                 retval = readl(base + NvRegMIIData);
1069                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1070                                 dev->name, miireg, addr, retval);
1071         }
1072
1073         return retval;
1074 }
1075
1076 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1077 {
1078         struct fe_priv *np = netdev_priv(dev);
1079         u32 miicontrol;
1080         unsigned int tries = 0;
1081
1082         miicontrol = BMCR_RESET | bmcr_setup;
1083         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1084                 return -1;
1085         }
1086
1087         /* wait for 500ms */
1088         msleep(500);
1089
1090         /* must wait till reset is deasserted */
1091         while (miicontrol & BMCR_RESET) {
1092                 msleep(10);
1093                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1094                 /* FIXME: 100 tries seem excessive */
1095                 if (tries++ > 100)
1096                         return -1;
1097         }
1098         return 0;
1099 }
1100
1101 static int phy_init(struct net_device *dev)
1102 {
1103         struct fe_priv *np = get_nvpriv(dev);
1104         u8 __iomem *base = get_hwbase(dev);
1105         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1106
1107         /* phy errata for E3016 phy */
1108         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1109                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1110                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1111                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1112                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1113                         return PHY_ERROR;
1114                 }
1115         }
1116         if (np->phy_oui == PHY_OUI_REALTEK) {
1117                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1118                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1119                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1120                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1121                                 return PHY_ERROR;
1122                         }
1123                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1124                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1125                                 return PHY_ERROR;
1126                         }
1127                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1128                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1129                                 return PHY_ERROR;
1130                         }
1131                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1132                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1133                                 return PHY_ERROR;
1134                         }
1135                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1136                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137                                 return PHY_ERROR;
1138                         }
1139                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1140                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1141                                 return PHY_ERROR;
1142                         }
1143                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1144                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145                                 return PHY_ERROR;
1146                         }
1147                 }
1148                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1149                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1150                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1151                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1152                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1153                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1154                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1155                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1156                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1157                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1158                                 phy_reserved |= PHY_REALTEK_INIT7;
1159                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1160                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1161                                         return PHY_ERROR;
1162                                 }
1163                         }
1164                 }
1165         }
1166
1167         /* set advertise register */
1168         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1169         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1170         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1171                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1172                 return PHY_ERROR;
1173         }
1174
1175         /* get phy interface type */
1176         phyinterface = readl(base + NvRegPhyInterface);
1177
1178         /* see if gigabit phy */
1179         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1180         if (mii_status & PHY_GIGABIT) {
1181                 np->gigabit = PHY_GIGABIT;
1182                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1183                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1184                 if (phyinterface & PHY_RGMII)
1185                         mii_control_1000 |= ADVERTISE_1000FULL;
1186                 else
1187                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1188
1189                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1190                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1191                         return PHY_ERROR;
1192                 }
1193         }
1194         else
1195                 np->gigabit = 0;
1196
1197         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1198         mii_control |= BMCR_ANENABLE;
1199
1200         /* reset the phy
1201          * (certain phys need bmcr to be setup with reset)
1202          */
1203         if (phy_reset(dev, mii_control)) {
1204                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1205                 return PHY_ERROR;
1206         }
1207
1208         /* phy vendor specific configuration */
1209         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1210                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1211                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1212                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1213                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1214                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1215                         return PHY_ERROR;
1216                 }
1217                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1218                 phy_reserved |= PHY_CICADA_INIT5;
1219                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1220                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1221                         return PHY_ERROR;
1222                 }
1223         }
1224         if (np->phy_oui == PHY_OUI_CICADA) {
1225                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1226                 phy_reserved |= PHY_CICADA_INIT6;
1227                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1228                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1229                         return PHY_ERROR;
1230                 }
1231         }
1232         if (np->phy_oui == PHY_OUI_VITESSE) {
1233                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1234                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1235                         return PHY_ERROR;
1236                 }
1237                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1238                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                         return PHY_ERROR;
1240                 }
1241                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1242                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1243                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1244                         return PHY_ERROR;
1245                 }
1246                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1247                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1248                 phy_reserved |= PHY_VITESSE_INIT3;
1249                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1250                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1251                         return PHY_ERROR;
1252                 }
1253                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1254                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255                         return PHY_ERROR;
1256                 }
1257                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1258                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259                         return PHY_ERROR;
1260                 }
1261                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1262                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1263                 phy_reserved |= PHY_VITESSE_INIT3;
1264                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1265                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1266                         return PHY_ERROR;
1267                 }
1268                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1269                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1270                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1271                         return PHY_ERROR;
1272                 }
1273                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1274                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275                         return PHY_ERROR;
1276                 }
1277                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1278                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1279                         return PHY_ERROR;
1280                 }
1281                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1282                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1283                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284                         return PHY_ERROR;
1285                 }
1286                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1287                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1288                 phy_reserved |= PHY_VITESSE_INIT8;
1289                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1290                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1291                         return PHY_ERROR;
1292                 }
1293                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1294                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1295                         return PHY_ERROR;
1296                 }
1297                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1298                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1299                         return PHY_ERROR;
1300                 }
1301         }
1302         if (np->phy_oui == PHY_OUI_REALTEK) {
1303                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1304                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1305                         /* reset could have cleared these out, set them back */
1306                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1307                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1308                                 return PHY_ERROR;
1309                         }
1310                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1311                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1312                                 return PHY_ERROR;
1313                         }
1314                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1315                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1316                                 return PHY_ERROR;
1317                         }
1318                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1319                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1320                                 return PHY_ERROR;
1321                         }
1322                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1323                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324                                 return PHY_ERROR;
1325                         }
1326                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1327                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328                                 return PHY_ERROR;
1329                         }
1330                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1331                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332                                 return PHY_ERROR;
1333                         }
1334                 }
1335                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1336                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1337                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1338                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1339                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1340                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1341                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1342                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1343                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1344                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1345                                 phy_reserved |= PHY_REALTEK_INIT7;
1346                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1347                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1348                                         return PHY_ERROR;
1349                                 }
1350                         }
1351                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1352                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1353                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354                                         return PHY_ERROR;
1355                                 }
1356                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1357                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1358                                 phy_reserved |= PHY_REALTEK_INIT3;
1359                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1360                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1361                                         return PHY_ERROR;
1362                                 }
1363                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1364                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365                                         return PHY_ERROR;
1366                                 }
1367                         }
1368                 }
1369         }
1370
1371         /* some phys clear out pause advertisment on reset, set it back */
1372         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1373
1374         /* restart auto negotiation */
1375         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1376         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1377         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1378                 return PHY_ERROR;
1379         }
1380
1381         return 0;
1382 }
1383
1384 static void nv_start_rx(struct net_device *dev)
1385 {
1386         struct fe_priv *np = netdev_priv(dev);
1387         u8 __iomem *base = get_hwbase(dev);
1388         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1389
1390         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1391         /* Already running? Stop it. */
1392         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1393                 rx_ctrl &= ~NVREG_RCVCTL_START;
1394                 writel(rx_ctrl, base + NvRegReceiverControl);
1395                 pci_push(base);
1396         }
1397         writel(np->linkspeed, base + NvRegLinkSpeed);
1398         pci_push(base);
1399         rx_ctrl |= NVREG_RCVCTL_START;
1400         if (np->mac_in_use)
1401                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1402         writel(rx_ctrl, base + NvRegReceiverControl);
1403         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1404                                 dev->name, np->duplex, np->linkspeed);
1405         pci_push(base);
1406 }
1407
1408 static void nv_stop_rx(struct net_device *dev)
1409 {
1410         struct fe_priv *np = netdev_priv(dev);
1411         u8 __iomem *base = get_hwbase(dev);
1412         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1413
1414         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1415         if (!np->mac_in_use)
1416                 rx_ctrl &= ~NVREG_RCVCTL_START;
1417         else
1418                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1419         writel(rx_ctrl, base + NvRegReceiverControl);
1420         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1421                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1422                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1423
1424         udelay(NV_RXSTOP_DELAY2);
1425         if (!np->mac_in_use)
1426                 writel(0, base + NvRegLinkSpeed);
1427 }
1428
1429 static void nv_start_tx(struct net_device *dev)
1430 {
1431         struct fe_priv *np = netdev_priv(dev);
1432         u8 __iomem *base = get_hwbase(dev);
1433         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1434
1435         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1436         tx_ctrl |= NVREG_XMITCTL_START;
1437         if (np->mac_in_use)
1438                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1439         writel(tx_ctrl, base + NvRegTransmitterControl);
1440         pci_push(base);
1441 }
1442
1443 static void nv_stop_tx(struct net_device *dev)
1444 {
1445         struct fe_priv *np = netdev_priv(dev);
1446         u8 __iomem *base = get_hwbase(dev);
1447         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1448
1449         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1450         if (!np->mac_in_use)
1451                 tx_ctrl &= ~NVREG_XMITCTL_START;
1452         else
1453                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1454         writel(tx_ctrl, base + NvRegTransmitterControl);
1455         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1456                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1457                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1458
1459         udelay(NV_TXSTOP_DELAY2);
1460         if (!np->mac_in_use)
1461                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1462                        base + NvRegTransmitPoll);
1463 }
1464
1465 static void nv_start_rxtx(struct net_device *dev)
1466 {
1467         nv_start_rx(dev);
1468         nv_start_tx(dev);
1469 }
1470
1471 static void nv_stop_rxtx(struct net_device *dev)
1472 {
1473         nv_stop_rx(dev);
1474         nv_stop_tx(dev);
1475 }
1476
1477 static void nv_txrx_reset(struct net_device *dev)
1478 {
1479         struct fe_priv *np = netdev_priv(dev);
1480         u8 __iomem *base = get_hwbase(dev);
1481
1482         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1483         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1484         pci_push(base);
1485         udelay(NV_TXRX_RESET_DELAY);
1486         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1487         pci_push(base);
1488 }
1489
1490 static void nv_mac_reset(struct net_device *dev)
1491 {
1492         struct fe_priv *np = netdev_priv(dev);
1493         u8 __iomem *base = get_hwbase(dev);
1494         u32 temp1, temp2, temp3;
1495
1496         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1497
1498         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1499         pci_push(base);
1500
1501         /* save registers since they will be cleared on reset */
1502         temp1 = readl(base + NvRegMacAddrA);
1503         temp2 = readl(base + NvRegMacAddrB);
1504         temp3 = readl(base + NvRegTransmitPoll);
1505
1506         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1507         pci_push(base);
1508         udelay(NV_MAC_RESET_DELAY);
1509         writel(0, base + NvRegMacReset);
1510         pci_push(base);
1511         udelay(NV_MAC_RESET_DELAY);
1512
1513         /* restore saved registers */
1514         writel(temp1, base + NvRegMacAddrA);
1515         writel(temp2, base + NvRegMacAddrB);
1516         writel(temp3, base + NvRegTransmitPoll);
1517
1518         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1519         pci_push(base);
1520 }
1521
1522 static void nv_get_hw_stats(struct net_device *dev)
1523 {
1524         struct fe_priv *np = netdev_priv(dev);
1525         u8 __iomem *base = get_hwbase(dev);
1526
1527         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1528         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1529         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1530         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1531         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1532         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1533         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1534         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1535         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1536         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1537         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1538         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1539         np->estats.rx_runt += readl(base + NvRegRxRunt);
1540         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1541         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1542         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1543         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1544         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1545         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1546         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1547         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1548         np->estats.rx_packets =
1549                 np->estats.rx_unicast +
1550                 np->estats.rx_multicast +
1551                 np->estats.rx_broadcast;
1552         np->estats.rx_errors_total =
1553                 np->estats.rx_crc_errors +
1554                 np->estats.rx_over_errors +
1555                 np->estats.rx_frame_error +
1556                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1557                 np->estats.rx_late_collision +
1558                 np->estats.rx_runt +
1559                 np->estats.rx_frame_too_long;
1560         np->estats.tx_errors_total =
1561                 np->estats.tx_late_collision +
1562                 np->estats.tx_fifo_errors +
1563                 np->estats.tx_carrier_errors +
1564                 np->estats.tx_excess_deferral +
1565                 np->estats.tx_retry_error;
1566
1567         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1568                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1569                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1570                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1571                 np->estats.tx_pause += readl(base + NvRegTxPause);
1572                 np->estats.rx_pause += readl(base + NvRegRxPause);
1573                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1574         }
1575 }
1576
1577 /*
1578  * nv_get_stats: dev->get_stats function
1579  * Get latest stats value from the nic.
1580  * Called with read_lock(&dev_base_lock) held for read -
1581  * only synchronized against unregister_netdevice.
1582  */
1583 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1584 {
1585         struct fe_priv *np = netdev_priv(dev);
1586
1587         /* If the nic supports hw counters then retrieve latest values */
1588         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1589                 nv_get_hw_stats(dev);
1590
1591                 /* copy to net_device stats */
1592                 dev->stats.tx_bytes = np->estats.tx_bytes;
1593                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1594                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1595                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1596                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1597                 dev->stats.rx_errors = np->estats.rx_errors_total;
1598                 dev->stats.tx_errors = np->estats.tx_errors_total;
1599         }
1600
1601         return &dev->stats;
1602 }
1603
1604 /*
1605  * nv_alloc_rx: fill rx ring entries.
1606  * Return 1 if the allocations for the skbs failed and the
1607  * rx engine is without Available descriptors
1608  */
1609 static int nv_alloc_rx(struct net_device *dev)
1610 {
1611         struct fe_priv *np = netdev_priv(dev);
1612         struct ring_desc* less_rx;
1613
1614         less_rx = np->get_rx.orig;
1615         if (less_rx-- == np->first_rx.orig)
1616                 less_rx = np->last_rx.orig;
1617
1618         while (np->put_rx.orig != less_rx) {
1619                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1620                 if (skb) {
1621                         np->put_rx_ctx->skb = skb;
1622                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1623                                                              skb->data,
1624                                                              skb_tailroom(skb),
1625                                                              PCI_DMA_FROMDEVICE);
1626                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1627                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1628                         wmb();
1629                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1630                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1631                                 np->put_rx.orig = np->first_rx.orig;
1632                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1633                                 np->put_rx_ctx = np->first_rx_ctx;
1634                 } else {
1635                         return 1;
1636                 }
1637         }
1638         return 0;
1639 }
1640
1641 static int nv_alloc_rx_optimized(struct net_device *dev)
1642 {
1643         struct fe_priv *np = netdev_priv(dev);
1644         struct ring_desc_ex* less_rx;
1645
1646         less_rx = np->get_rx.ex;
1647         if (less_rx-- == np->first_rx.ex)
1648                 less_rx = np->last_rx.ex;
1649
1650         while (np->put_rx.ex != less_rx) {
1651                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1652                 if (skb) {
1653                         np->put_rx_ctx->skb = skb;
1654                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1655                                                              skb->data,
1656                                                              skb_tailroom(skb),
1657                                                              PCI_DMA_FROMDEVICE);
1658                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1659                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1660                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1661                         wmb();
1662                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1663                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1664                                 np->put_rx.ex = np->first_rx.ex;
1665                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1666                                 np->put_rx_ctx = np->first_rx_ctx;
1667                 } else {
1668                         return 1;
1669                 }
1670         }
1671         return 0;
1672 }
1673
1674 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1675 #ifdef CONFIG_FORCEDETH_NAPI
1676 static void nv_do_rx_refill(unsigned long data)
1677 {
1678         struct net_device *dev = (struct net_device *) data;
1679         struct fe_priv *np = netdev_priv(dev);
1680
1681         /* Just reschedule NAPI rx processing */
1682         netif_rx_schedule(dev, &np->napi);
1683 }
1684 #else
1685 static void nv_do_rx_refill(unsigned long data)
1686 {
1687         struct net_device *dev = (struct net_device *) data;
1688         struct fe_priv *np = netdev_priv(dev);
1689         int retcode;
1690
1691         if (!using_multi_irqs(dev)) {
1692                 if (np->msi_flags & NV_MSI_X_ENABLED)
1693                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1694                 else
1695                         disable_irq(np->pci_dev->irq);
1696         } else {
1697                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1698         }
1699         if (!nv_optimized(np))
1700                 retcode = nv_alloc_rx(dev);
1701         else
1702                 retcode = nv_alloc_rx_optimized(dev);
1703         if (retcode) {
1704                 spin_lock_irq(&np->lock);
1705                 if (!np->in_shutdown)
1706                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1707                 spin_unlock_irq(&np->lock);
1708         }
1709         if (!using_multi_irqs(dev)) {
1710                 if (np->msi_flags & NV_MSI_X_ENABLED)
1711                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1712                 else
1713                         enable_irq(np->pci_dev->irq);
1714         } else {
1715                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1716         }
1717 }
1718 #endif
1719
1720 static void nv_init_rx(struct net_device *dev)
1721 {
1722         struct fe_priv *np = netdev_priv(dev);
1723         int i;
1724
1725         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1726
1727         if (!nv_optimized(np))
1728                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1729         else
1730                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1731         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1732         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1733
1734         for (i = 0; i < np->rx_ring_size; i++) {
1735                 if (!nv_optimized(np)) {
1736                         np->rx_ring.orig[i].flaglen = 0;
1737                         np->rx_ring.orig[i].buf = 0;
1738                 } else {
1739                         np->rx_ring.ex[i].flaglen = 0;
1740                         np->rx_ring.ex[i].txvlan = 0;
1741                         np->rx_ring.ex[i].bufhigh = 0;
1742                         np->rx_ring.ex[i].buflow = 0;
1743                 }
1744                 np->rx_skb[i].skb = NULL;
1745                 np->rx_skb[i].dma = 0;
1746         }
1747 }
1748
1749 static void nv_init_tx(struct net_device *dev)
1750 {
1751         struct fe_priv *np = netdev_priv(dev);
1752         int i;
1753
1754         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1755
1756         if (!nv_optimized(np))
1757                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1758         else
1759                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1760         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1761         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1762         np->tx_pkts_in_progress = 0;
1763         np->tx_change_owner = NULL;
1764         np->tx_end_flip = NULL;
1765
1766         for (i = 0; i < np->tx_ring_size; i++) {
1767                 if (!nv_optimized(np)) {
1768                         np->tx_ring.orig[i].flaglen = 0;
1769                         np->tx_ring.orig[i].buf = 0;
1770                 } else {
1771                         np->tx_ring.ex[i].flaglen = 0;
1772                         np->tx_ring.ex[i].txvlan = 0;
1773                         np->tx_ring.ex[i].bufhigh = 0;
1774                         np->tx_ring.ex[i].buflow = 0;
1775                 }
1776                 np->tx_skb[i].skb = NULL;
1777                 np->tx_skb[i].dma = 0;
1778                 np->tx_skb[i].dma_len = 0;
1779                 np->tx_skb[i].first_tx_desc = NULL;
1780                 np->tx_skb[i].next_tx_ctx = NULL;
1781         }
1782 }
1783
1784 static int nv_init_ring(struct net_device *dev)
1785 {
1786         struct fe_priv *np = netdev_priv(dev);
1787
1788         nv_init_tx(dev);
1789         nv_init_rx(dev);
1790
1791         if (!nv_optimized(np))
1792                 return nv_alloc_rx(dev);
1793         else
1794                 return nv_alloc_rx_optimized(dev);
1795 }
1796
1797 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1798 {
1799         struct fe_priv *np = netdev_priv(dev);
1800
1801         if (tx_skb->dma) {
1802                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1803                                tx_skb->dma_len,
1804                                PCI_DMA_TODEVICE);
1805                 tx_skb->dma = 0;
1806         }
1807         if (tx_skb->skb) {
1808                 dev_kfree_skb_any(tx_skb->skb);
1809                 tx_skb->skb = NULL;
1810                 return 1;
1811         } else {
1812                 return 0;
1813         }
1814 }
1815
1816 static void nv_drain_tx(struct net_device *dev)
1817 {
1818         struct fe_priv *np = netdev_priv(dev);
1819         unsigned int i;
1820
1821         for (i = 0; i < np->tx_ring_size; i++) {
1822                 if (!nv_optimized(np)) {
1823                         np->tx_ring.orig[i].flaglen = 0;
1824                         np->tx_ring.orig[i].buf = 0;
1825                 } else {
1826                         np->tx_ring.ex[i].flaglen = 0;
1827                         np->tx_ring.ex[i].txvlan = 0;
1828                         np->tx_ring.ex[i].bufhigh = 0;
1829                         np->tx_ring.ex[i].buflow = 0;
1830                 }
1831                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1832                         dev->stats.tx_dropped++;
1833                 np->tx_skb[i].dma = 0;
1834                 np->tx_skb[i].dma_len = 0;
1835                 np->tx_skb[i].first_tx_desc = NULL;
1836                 np->tx_skb[i].next_tx_ctx = NULL;
1837         }
1838         np->tx_pkts_in_progress = 0;
1839         np->tx_change_owner = NULL;
1840         np->tx_end_flip = NULL;
1841 }
1842
1843 static void nv_drain_rx(struct net_device *dev)
1844 {
1845         struct fe_priv *np = netdev_priv(dev);
1846         int i;
1847
1848         for (i = 0; i < np->rx_ring_size; i++) {
1849                 if (!nv_optimized(np)) {
1850                         np->rx_ring.orig[i].flaglen = 0;
1851                         np->rx_ring.orig[i].buf = 0;
1852                 } else {
1853                         np->rx_ring.ex[i].flaglen = 0;
1854                         np->rx_ring.ex[i].txvlan = 0;
1855                         np->rx_ring.ex[i].bufhigh = 0;
1856                         np->rx_ring.ex[i].buflow = 0;
1857                 }
1858                 wmb();
1859                 if (np->rx_skb[i].skb) {
1860                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1861                                          (skb_end_pointer(np->rx_skb[i].skb) -
1862                                           np->rx_skb[i].skb->data),
1863                                          PCI_DMA_FROMDEVICE);
1864                         dev_kfree_skb(np->rx_skb[i].skb);
1865                         np->rx_skb[i].skb = NULL;
1866                 }
1867         }
1868 }
1869
1870 static void nv_drain_rxtx(struct net_device *dev)
1871 {
1872         nv_drain_tx(dev);
1873         nv_drain_rx(dev);
1874 }
1875
1876 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1877 {
1878         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1879 }
1880
1881 static void nv_legacybackoff_reseed(struct net_device *dev)
1882 {
1883         u8 __iomem *base = get_hwbase(dev);
1884         u32 reg;
1885         u32 low;
1886         int tx_status = 0;
1887
1888         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1889         get_random_bytes(&low, sizeof(low));
1890         reg |= low & NVREG_SLOTTIME_MASK;
1891
1892         /* Need to stop tx before change takes effect.
1893          * Caller has already gained np->lock.
1894          */
1895         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1896         if (tx_status)
1897                 nv_stop_tx(dev);
1898         nv_stop_rx(dev);
1899         writel(reg, base + NvRegSlotTime);
1900         if (tx_status)
1901                 nv_start_tx(dev);
1902         nv_start_rx(dev);
1903 }
1904
1905 /* Gear Backoff Seeds */
1906 #define BACKOFF_SEEDSET_ROWS    8
1907 #define BACKOFF_SEEDSET_LFSRS   15
1908
1909 /* Known Good seed sets */
1910 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1911     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1912     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1913     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1914     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1915     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1916     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1917     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
1918     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1919
1920 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1921     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1922     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1923     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1924     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1925     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1926     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1928     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1929
1930 static void nv_gear_backoff_reseed(struct net_device *dev)
1931 {
1932         u8 __iomem *base = get_hwbase(dev);
1933         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
1934         u32 temp, seedset, combinedSeed;
1935         int i;
1936
1937         /* Setup seed for free running LFSR */
1938         /* We are going to read the time stamp counter 3 times
1939            and swizzle bits around to increase randomness */
1940         get_random_bytes(&miniseed1, sizeof(miniseed1));
1941         miniseed1 &= 0x0fff;
1942         if (miniseed1 == 0)
1943                 miniseed1 = 0xabc;
1944
1945         get_random_bytes(&miniseed2, sizeof(miniseed2));
1946         miniseed2 &= 0x0fff;
1947         if (miniseed2 == 0)
1948                 miniseed2 = 0xabc;
1949         miniseed2_reversed =
1950                 ((miniseed2 & 0xF00) >> 8) |
1951                  (miniseed2 & 0x0F0) |
1952                  ((miniseed2 & 0x00F) << 8);
1953
1954         get_random_bytes(&miniseed3, sizeof(miniseed3));
1955         miniseed3 &= 0x0fff;
1956         if (miniseed3 == 0)
1957                 miniseed3 = 0xabc;
1958         miniseed3_reversed =
1959                 ((miniseed3 & 0xF00) >> 8) |
1960                  (miniseed3 & 0x0F0) |
1961                  ((miniseed3 & 0x00F) << 8);
1962
1963         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
1964                        (miniseed2 ^ miniseed3_reversed);
1965
1966         /* Seeds can not be zero */
1967         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
1968                 combinedSeed |= 0x08;
1969         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
1970                 combinedSeed |= 0x8000;
1971
1972         /* No need to disable tx here */
1973         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
1974         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
1975         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
1976         writel(temp,base + NvRegBackOffControl);
1977
1978         /* Setup seeds for all gear LFSRs. */
1979         get_random_bytes(&seedset, sizeof(seedset));
1980         seedset = seedset % BACKOFF_SEEDSET_ROWS;
1981         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
1982         {
1983                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
1984                 temp |= main_seedset[seedset][i-1] & 0x3ff;
1985                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
1986                 writel(temp, base + NvRegBackOffControl);
1987         }
1988 }
1989
1990 /*
1991  * nv_start_xmit: dev->hard_start_xmit function
1992  * Called with netif_tx_lock held.
1993  */
1994 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1995 {
1996         struct fe_priv *np = netdev_priv(dev);
1997         u32 tx_flags = 0;
1998         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1999         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2000         unsigned int i;
2001         u32 offset = 0;
2002         u32 bcnt;
2003         u32 size = skb->len-skb->data_len;
2004         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2005         u32 empty_slots;
2006         struct ring_desc* put_tx;
2007         struct ring_desc* start_tx;
2008         struct ring_desc* prev_tx;
2009         struct nv_skb_map* prev_tx_ctx;
2010         unsigned long flags;
2011
2012         /* add fragments to entries count */
2013         for (i = 0; i < fragments; i++) {
2014                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2015                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2016         }
2017
2018         empty_slots = nv_get_empty_tx_slots(np);
2019         if (unlikely(empty_slots <= entries)) {
2020                 spin_lock_irqsave(&np->lock, flags);
2021                 netif_stop_queue(dev);
2022                 np->tx_stop = 1;
2023                 spin_unlock_irqrestore(&np->lock, flags);
2024                 return NETDEV_TX_BUSY;
2025         }
2026
2027         start_tx = put_tx = np->put_tx.orig;
2028
2029         /* setup the header buffer */
2030         do {
2031                 prev_tx = put_tx;
2032                 prev_tx_ctx = np->put_tx_ctx;
2033                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2034                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2035                                                 PCI_DMA_TODEVICE);
2036                 np->put_tx_ctx->dma_len = bcnt;
2037                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2038                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2039
2040                 tx_flags = np->tx_flags;
2041                 offset += bcnt;
2042                 size -= bcnt;
2043                 if (unlikely(put_tx++ == np->last_tx.orig))
2044                         put_tx = np->first_tx.orig;
2045                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2046                         np->put_tx_ctx = np->first_tx_ctx;
2047         } while (size);
2048
2049         /* setup the fragments */
2050         for (i = 0; i < fragments; i++) {
2051                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2052                 u32 size = frag->size;
2053                 offset = 0;
2054
2055                 do {
2056                         prev_tx = put_tx;
2057                         prev_tx_ctx = np->put_tx_ctx;
2058                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2059                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2060                                                            PCI_DMA_TODEVICE);
2061                         np->put_tx_ctx->dma_len = bcnt;
2062                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2063                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2064
2065                         offset += bcnt;
2066                         size -= bcnt;
2067                         if (unlikely(put_tx++ == np->last_tx.orig))
2068                                 put_tx = np->first_tx.orig;
2069                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2070                                 np->put_tx_ctx = np->first_tx_ctx;
2071                 } while (size);
2072         }
2073
2074         /* set last fragment flag  */
2075         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2076
2077         /* save skb in this slot's context area */
2078         prev_tx_ctx->skb = skb;
2079
2080         if (skb_is_gso(skb))
2081                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2082         else
2083                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2084                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2085
2086         spin_lock_irqsave(&np->lock, flags);
2087
2088         /* set tx flags */
2089         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2090         np->put_tx.orig = put_tx;
2091
2092         spin_unlock_irqrestore(&np->lock, flags);
2093
2094         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2095                 dev->name, entries, tx_flags_extra);
2096         {
2097                 int j;
2098                 for (j=0; j<64; j++) {
2099                         if ((j%16) == 0)
2100                                 dprintk("\n%03x:", j);
2101                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2102                 }
2103                 dprintk("\n");
2104         }
2105
2106         dev->trans_start = jiffies;
2107         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2108         return NETDEV_TX_OK;
2109 }
2110
2111 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2112 {
2113         struct fe_priv *np = netdev_priv(dev);
2114         u32 tx_flags = 0;
2115         u32 tx_flags_extra;
2116         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2117         unsigned int i;
2118         u32 offset = 0;
2119         u32 bcnt;
2120         u32 size = skb->len-skb->data_len;
2121         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2122         u32 empty_slots;
2123         struct ring_desc_ex* put_tx;
2124         struct ring_desc_ex* start_tx;
2125         struct ring_desc_ex* prev_tx;
2126         struct nv_skb_map* prev_tx_ctx;
2127         struct nv_skb_map* start_tx_ctx;
2128         unsigned long flags;
2129
2130         /* add fragments to entries count */
2131         for (i = 0; i < fragments; i++) {
2132                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2133                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2134         }
2135
2136         empty_slots = nv_get_empty_tx_slots(np);
2137         if (unlikely(empty_slots <= entries)) {
2138                 spin_lock_irqsave(&np->lock, flags);
2139                 netif_stop_queue(dev);
2140                 np->tx_stop = 1;
2141                 spin_unlock_irqrestore(&np->lock, flags);
2142                 return NETDEV_TX_BUSY;
2143         }
2144
2145         start_tx = put_tx = np->put_tx.ex;
2146         start_tx_ctx = np->put_tx_ctx;
2147
2148         /* setup the header buffer */
2149         do {
2150                 prev_tx = put_tx;
2151                 prev_tx_ctx = np->put_tx_ctx;
2152                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2153                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2154                                                 PCI_DMA_TODEVICE);
2155                 np->put_tx_ctx->dma_len = bcnt;
2156                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2157                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2158                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2159
2160                 tx_flags = NV_TX2_VALID;
2161                 offset += bcnt;
2162                 size -= bcnt;
2163                 if (unlikely(put_tx++ == np->last_tx.ex))
2164                         put_tx = np->first_tx.ex;
2165                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2166                         np->put_tx_ctx = np->first_tx_ctx;
2167         } while (size);
2168
2169         /* setup the fragments */
2170         for (i = 0; i < fragments; i++) {
2171                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2172                 u32 size = frag->size;
2173                 offset = 0;
2174
2175                 do {
2176                         prev_tx = put_tx;
2177                         prev_tx_ctx = np->put_tx_ctx;
2178                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2179                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2180                                                            PCI_DMA_TODEVICE);
2181                         np->put_tx_ctx->dma_len = bcnt;
2182                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2183                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2184                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2185
2186                         offset += bcnt;
2187                         size -= bcnt;
2188                         if (unlikely(put_tx++ == np->last_tx.ex))
2189                                 put_tx = np->first_tx.ex;
2190                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2191                                 np->put_tx_ctx = np->first_tx_ctx;
2192                 } while (size);
2193         }
2194
2195         /* set last fragment flag  */
2196         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2197
2198         /* save skb in this slot's context area */
2199         prev_tx_ctx->skb = skb;
2200
2201         if (skb_is_gso(skb))
2202                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2203         else
2204                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2205                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2206
2207         /* vlan tag */
2208         if (likely(!np->vlangrp)) {
2209                 start_tx->txvlan = 0;
2210         } else {
2211                 if (vlan_tx_tag_present(skb))
2212                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2213                 else
2214                         start_tx->txvlan = 0;
2215         }
2216
2217         spin_lock_irqsave(&np->lock, flags);
2218
2219         if (np->tx_limit) {
2220                 /* Limit the number of outstanding tx. Setup all fragments, but
2221                  * do not set the VALID bit on the first descriptor. Save a pointer
2222                  * to that descriptor and also for next skb_map element.
2223                  */
2224
2225                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2226                         if (!np->tx_change_owner)
2227                                 np->tx_change_owner = start_tx_ctx;
2228
2229                         /* remove VALID bit */
2230                         tx_flags &= ~NV_TX2_VALID;
2231                         start_tx_ctx->first_tx_desc = start_tx;
2232                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2233                         np->tx_end_flip = np->put_tx_ctx;
2234                 } else {
2235                         np->tx_pkts_in_progress++;
2236                 }
2237         }
2238
2239         /* set tx flags */
2240         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2241         np->put_tx.ex = put_tx;
2242
2243         spin_unlock_irqrestore(&np->lock, flags);
2244
2245         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2246                 dev->name, entries, tx_flags_extra);
2247         {
2248                 int j;
2249                 for (j=0; j<64; j++) {
2250                         if ((j%16) == 0)
2251                                 dprintk("\n%03x:", j);
2252                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2253                 }
2254                 dprintk("\n");
2255         }
2256
2257         dev->trans_start = jiffies;
2258         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2259         return NETDEV_TX_OK;
2260 }
2261
2262 static inline void nv_tx_flip_ownership(struct net_device *dev)
2263 {
2264         struct fe_priv *np = netdev_priv(dev);
2265
2266         np->tx_pkts_in_progress--;
2267         if (np->tx_change_owner) {
2268                 np->tx_change_owner->first_tx_desc->flaglen |=
2269                         cpu_to_le32(NV_TX2_VALID);
2270                 np->tx_pkts_in_progress++;
2271
2272                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2273                 if (np->tx_change_owner == np->tx_end_flip)
2274                         np->tx_change_owner = NULL;
2275
2276                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2277         }
2278 }
2279
2280 /*
2281  * nv_tx_done: check for completed packets, release the skbs.
2282  *
2283  * Caller must own np->lock.
2284  */
2285 static void nv_tx_done(struct net_device *dev)
2286 {
2287         struct fe_priv *np = netdev_priv(dev);
2288         u32 flags;
2289         struct ring_desc* orig_get_tx = np->get_tx.orig;
2290
2291         while ((np->get_tx.orig != np->put_tx.orig) &&
2292                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2293
2294                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2295                                         dev->name, flags);
2296
2297                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2298                                np->get_tx_ctx->dma_len,
2299                                PCI_DMA_TODEVICE);
2300                 np->get_tx_ctx->dma = 0;
2301
2302                 if (np->desc_ver == DESC_VER_1) {
2303                         if (flags & NV_TX_LASTPACKET) {
2304                                 if (flags & NV_TX_ERROR) {
2305                                         if (flags & NV_TX_UNDERFLOW)
2306                                                 dev->stats.tx_fifo_errors++;
2307                                         if (flags & NV_TX_CARRIERLOST)
2308                                                 dev->stats.tx_carrier_errors++;
2309                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2310                                                 nv_legacybackoff_reseed(dev);
2311                                         dev->stats.tx_errors++;
2312                                 } else {
2313                                         dev->stats.tx_packets++;
2314                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2315                                 }
2316                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2317                                 np->get_tx_ctx->skb = NULL;
2318                         }
2319                 } else {
2320                         if (flags & NV_TX2_LASTPACKET) {
2321                                 if (flags & NV_TX2_ERROR) {
2322                                         if (flags & NV_TX2_UNDERFLOW)
2323                                                 dev->stats.tx_fifo_errors++;
2324                                         if (flags & NV_TX2_CARRIERLOST)
2325                                                 dev->stats.tx_carrier_errors++;
2326                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2327                                                 nv_legacybackoff_reseed(dev);
2328                                         dev->stats.tx_errors++;
2329                                 } else {
2330                                         dev->stats.tx_packets++;
2331                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2332                                 }
2333                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2334                                 np->get_tx_ctx->skb = NULL;
2335                         }
2336                 }
2337                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2338                         np->get_tx.orig = np->first_tx.orig;
2339                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2340                         np->get_tx_ctx = np->first_tx_ctx;
2341         }
2342         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2343                 np->tx_stop = 0;
2344                 netif_wake_queue(dev);
2345         }
2346 }
2347
2348 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2349 {
2350         struct fe_priv *np = netdev_priv(dev);
2351         u32 flags;
2352         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2353
2354         while ((np->get_tx.ex != np->put_tx.ex) &&
2355                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2356                (limit-- > 0)) {
2357
2358                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2359                                         dev->name, flags);
2360
2361                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2362                                np->get_tx_ctx->dma_len,
2363                                PCI_DMA_TODEVICE);
2364                 np->get_tx_ctx->dma = 0;
2365
2366                 if (flags & NV_TX2_LASTPACKET) {
2367                         if (!(flags & NV_TX2_ERROR))
2368                                 dev->stats.tx_packets++;
2369                         else {
2370                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2371                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2372                                                 nv_gear_backoff_reseed(dev);
2373                                         else
2374                                                 nv_legacybackoff_reseed(dev);
2375                                 }
2376                         }
2377
2378                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2379                         np->get_tx_ctx->skb = NULL;
2380
2381                         if (np->tx_limit) {
2382                                 nv_tx_flip_ownership(dev);
2383                         }
2384                 }
2385                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2386                         np->get_tx.ex = np->first_tx.ex;
2387                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2388                         np->get_tx_ctx = np->first_tx_ctx;
2389         }
2390         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2391                 np->tx_stop = 0;
2392                 netif_wake_queue(dev);
2393         }
2394 }
2395
2396 /*
2397  * nv_tx_timeout: dev->tx_timeout function
2398  * Called with netif_tx_lock held.
2399  */
2400 static void nv_tx_timeout(struct net_device *dev)
2401 {
2402         struct fe_priv *np = netdev_priv(dev);
2403         u8 __iomem *base = get_hwbase(dev);
2404         u32 status;
2405
2406         if (np->msi_flags & NV_MSI_X_ENABLED)
2407                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2408         else
2409                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2410
2411         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2412
2413         {
2414                 int i;
2415
2416                 printk(KERN_INFO "%s: Ring at %lx\n",
2417                        dev->name, (unsigned long)np->ring_addr);
2418                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2419                 for (i=0;i<=np->register_size;i+= 32) {
2420                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2421                                         i,
2422                                         readl(base + i + 0), readl(base + i + 4),
2423                                         readl(base + i + 8), readl(base + i + 12),
2424                                         readl(base + i + 16), readl(base + i + 20),
2425                                         readl(base + i + 24), readl(base + i + 28));
2426                 }
2427                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2428                 for (i=0;i<np->tx_ring_size;i+= 4) {
2429                         if (!nv_optimized(np)) {
2430                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2431                                        i,
2432                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2433                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2434                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2435                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2436                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2437                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2438                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2439                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2440                         } else {
2441                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2442                                        i,
2443                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2444                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2445                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2446                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2447                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2448                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2449                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2450                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2451                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2452                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2453                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2454                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2455                         }
2456                 }
2457         }
2458
2459         spin_lock_irq(&np->lock);
2460
2461         /* 1) stop tx engine */
2462         nv_stop_tx(dev);
2463
2464         /* 2) check that the packets were not sent already: */
2465         if (!nv_optimized(np))
2466                 nv_tx_done(dev);
2467         else
2468                 nv_tx_done_optimized(dev, np->tx_ring_size);
2469
2470         /* 3) if there are dead entries: clear everything */
2471         if (np->get_tx_ctx != np->put_tx_ctx) {
2472                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2473                 nv_drain_tx(dev);
2474                 nv_init_tx(dev);
2475                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2476         }
2477
2478         netif_wake_queue(dev);
2479
2480         /* 4) restart tx engine */
2481         nv_start_tx(dev);
2482         spin_unlock_irq(&np->lock);
2483 }
2484
2485 /*
2486  * Called when the nic notices a mismatch between the actual data len on the
2487  * wire and the len indicated in the 802 header
2488  */
2489 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2490 {
2491         int hdrlen;     /* length of the 802 header */
2492         int protolen;   /* length as stored in the proto field */
2493
2494         /* 1) calculate len according to header */
2495         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2496                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2497                 hdrlen = VLAN_HLEN;
2498         } else {
2499                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2500                 hdrlen = ETH_HLEN;
2501         }
2502         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2503                                 dev->name, datalen, protolen, hdrlen);
2504         if (protolen > ETH_DATA_LEN)
2505                 return datalen; /* Value in proto field not a len, no checks possible */
2506
2507         protolen += hdrlen;
2508         /* consistency checks: */
2509         if (datalen > ETH_ZLEN) {
2510                 if (datalen >= protolen) {
2511                         /* more data on wire than in 802 header, trim of
2512                          * additional data.
2513                          */
2514                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2515                                         dev->name, protolen);
2516                         return protolen;
2517                 } else {
2518                         /* less data on wire than mentioned in header.
2519                          * Discard the packet.
2520                          */
2521                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2522                                         dev->name);
2523                         return -1;
2524                 }
2525         } else {
2526                 /* short packet. Accept only if 802 values are also short */
2527                 if (protolen > ETH_ZLEN) {
2528                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2529                                         dev->name);
2530                         return -1;
2531                 }
2532                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2533                                 dev->name, datalen);
2534                 return datalen;
2535         }
2536 }
2537
2538 static int nv_rx_process(struct net_device *dev, int limit)
2539 {
2540         struct fe_priv *np = netdev_priv(dev);
2541         u32 flags;
2542         int rx_work = 0;
2543         struct sk_buff *skb;
2544         int len;
2545
2546         while((np->get_rx.orig != np->put_rx.orig) &&
2547               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2548                 (rx_work < limit)) {
2549
2550                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2551                                         dev->name, flags);
2552
2553                 /*
2554                  * the packet is for us - immediately tear down the pci mapping.
2555                  * TODO: check if a prefetch of the first cacheline improves
2556                  * the performance.
2557                  */
2558                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2559                                 np->get_rx_ctx->dma_len,
2560                                 PCI_DMA_FROMDEVICE);
2561                 skb = np->get_rx_ctx->skb;
2562                 np->get_rx_ctx->skb = NULL;
2563
2564                 {
2565                         int j;
2566                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2567                         for (j=0; j<64; j++) {
2568                                 if ((j%16) == 0)
2569                                         dprintk("\n%03x:", j);
2570                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2571                         }
2572                         dprintk("\n");
2573                 }
2574                 /* look at what we actually got: */
2575                 if (np->desc_ver == DESC_VER_1) {
2576                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2577                                 len = flags & LEN_MASK_V1;
2578                                 if (unlikely(flags & NV_RX_ERROR)) {
2579                                         if (flags & NV_RX_ERROR4) {
2580                                                 len = nv_getlen(dev, skb->data, len);
2581                                                 if (len < 0) {
2582                                                         dev->stats.rx_errors++;
2583                                                         dev_kfree_skb(skb);
2584                                                         goto next_pkt;
2585                                                 }
2586                                         }
2587                                         /* framing errors are soft errors */
2588                                         else if (flags & NV_RX_FRAMINGERR) {
2589                                                 if (flags & NV_RX_SUBSTRACT1) {
2590                                                         len--;
2591                                                 }
2592                                         }
2593                                         /* the rest are hard errors */
2594                                         else {
2595                                                 if (flags & NV_RX_MISSEDFRAME)
2596                                                         dev->stats.rx_missed_errors++;
2597                                                 if (flags & NV_RX_CRCERR)
2598                                                         dev->stats.rx_crc_errors++;
2599                                                 if (flags & NV_RX_OVERFLOW)
2600                                                         dev->stats.rx_over_errors++;
2601                                                 dev->stats.rx_errors++;
2602                                                 dev_kfree_skb(skb);
2603                                                 goto next_pkt;
2604                                         }
2605                                 }
2606                         } else {
2607                                 dev_kfree_skb(skb);
2608                                 goto next_pkt;
2609                         }
2610                 } else {
2611                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2612                                 len = flags & LEN_MASK_V2;
2613                                 if (unlikely(flags & NV_RX2_ERROR)) {
2614                                         if (flags & NV_RX2_ERROR4) {
2615                                                 len = nv_getlen(dev, skb->data, len);
2616                                                 if (len < 0) {
2617                                                         dev->stats.rx_errors++;
2618                                                         dev_kfree_skb(skb);
2619                                                         goto next_pkt;
2620                                                 }
2621                                         }
2622                                         /* framing errors are soft errors */
2623                                         else if (flags & NV_RX2_FRAMINGERR) {
2624                                                 if (flags & NV_RX2_SUBSTRACT1) {
2625                                                         len--;
2626                                                 }
2627                                         }
2628                                         /* the rest are hard errors */
2629                                         else {
2630                                                 if (flags & NV_RX2_CRCERR)
2631                                                         dev->stats.rx_crc_errors++;
2632                                                 if (flags & NV_RX2_OVERFLOW)
2633                                                         dev->stats.rx_over_errors++;
2634                                                 dev->stats.rx_errors++;
2635                                                 dev_kfree_skb(skb);
2636                                                 goto next_pkt;
2637                                         }
2638                                 }
2639                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2640                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2641                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2642                         } else {
2643                                 dev_kfree_skb(skb);
2644                                 goto next_pkt;
2645                         }
2646                 }
2647                 /* got a valid packet - forward it to the network core */
2648                 skb_put(skb, len);
2649                 skb->protocol = eth_type_trans(skb, dev);
2650                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2651                                         dev->name, len, skb->protocol);
2652 #ifdef CONFIG_FORCEDETH_NAPI
2653                 netif_receive_skb(skb);
2654 #else
2655                 netif_rx(skb);
2656 #endif
2657                 dev->last_rx = jiffies;
2658                 dev->stats.rx_packets++;
2659                 dev->stats.rx_bytes += len;
2660 next_pkt:
2661                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2662                         np->get_rx.orig = np->first_rx.orig;
2663                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2664                         np->get_rx_ctx = np->first_rx_ctx;
2665
2666                 rx_work++;
2667         }
2668
2669         return rx_work;
2670 }
2671
2672 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2673 {
2674         struct fe_priv *np = netdev_priv(dev);
2675         u32 flags;
2676         u32 vlanflags = 0;
2677         int rx_work = 0;
2678         struct sk_buff *skb;
2679         int len;
2680
2681         while((np->get_rx.ex != np->put_rx.ex) &&
2682               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2683               (rx_work < limit)) {
2684
2685                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2686                                         dev->name, flags);
2687
2688                 /*
2689                  * the packet is for us - immediately tear down the pci mapping.
2690                  * TODO: check if a prefetch of the first cacheline improves
2691                  * the performance.
2692                  */
2693                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2694                                 np->get_rx_ctx->dma_len,
2695                                 PCI_DMA_FROMDEVICE);
2696                 skb = np->get_rx_ctx->skb;
2697                 np->get_rx_ctx->skb = NULL;
2698
2699                 {
2700                         int j;
2701                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2702                         for (j=0; j<64; j++) {
2703                                 if ((j%16) == 0)
2704                                         dprintk("\n%03x:", j);
2705                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2706                         }
2707                         dprintk("\n");
2708                 }
2709                 /* look at what we actually got: */
2710                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2711                         len = flags & LEN_MASK_V2;
2712                         if (unlikely(flags & NV_RX2_ERROR)) {
2713                                 if (flags & NV_RX2_ERROR4) {
2714                                         len = nv_getlen(dev, skb->data, len);
2715                                         if (len < 0) {
2716                                                 dev_kfree_skb(skb);
2717                                                 goto next_pkt;
2718                                         }
2719                                 }
2720                                 /* framing errors are soft errors */
2721                                 else if (flags & NV_RX2_FRAMINGERR) {
2722                                         if (flags & NV_RX2_SUBSTRACT1) {
2723                                                 len--;
2724                                         }
2725                                 }
2726                                 /* the rest are hard errors */
2727                                 else {
2728                                         dev_kfree_skb(skb);
2729                                         goto next_pkt;
2730                                 }
2731                         }
2732
2733                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2734                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2735                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2736
2737                         /* got a valid packet - forward it to the network core */
2738                         skb_put(skb, len);
2739                         skb->protocol = eth_type_trans(skb, dev);
2740                         prefetch(skb->data);
2741
2742                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2743                                 dev->name, len, skb->protocol);
2744
2745                         if (likely(!np->vlangrp)) {
2746 #ifdef CONFIG_FORCEDETH_NAPI
2747                                 netif_receive_skb(skb);
2748 #else
2749                                 netif_rx(skb);
2750 #endif
2751                         } else {
2752                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2753                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2754 #ifdef CONFIG_FORCEDETH_NAPI
2755                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2756                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2757 #else
2758                                         vlan_hwaccel_rx(skb, np->vlangrp,
2759                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2760 #endif
2761                                 } else {
2762 #ifdef CONFIG_FORCEDETH_NAPI
2763                                         netif_receive_skb(skb);
2764 #else
2765                                         netif_rx(skb);
2766 #endif
2767                                 }
2768                         }
2769
2770                         dev->last_rx = jiffies;
2771                         dev->stats.rx_packets++;
2772                         dev->stats.rx_bytes += len;
2773                 } else {
2774                         dev_kfree_skb(skb);
2775                 }
2776 next_pkt:
2777                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2778                         np->get_rx.ex = np->first_rx.ex;
2779                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2780                         np->get_rx_ctx = np->first_rx_ctx;
2781
2782                 rx_work++;
2783         }
2784
2785         return rx_work;
2786 }
2787
2788 static void set_bufsize(struct net_device *dev)
2789 {
2790         struct fe_priv *np = netdev_priv(dev);
2791
2792         if (dev->mtu <= ETH_DATA_LEN)
2793                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2794         else
2795                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2796 }
2797
2798 /*
2799  * nv_change_mtu: dev->change_mtu function
2800  * Called with dev_base_lock held for read.
2801  */
2802 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2803 {
2804         struct fe_priv *np = netdev_priv(dev);
2805         int old_mtu;
2806
2807         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2808                 return -EINVAL;
2809
2810         old_mtu = dev->mtu;
2811         dev->mtu = new_mtu;
2812
2813         /* return early if the buffer sizes will not change */
2814         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2815                 return 0;
2816         if (old_mtu == new_mtu)
2817                 return 0;
2818
2819         /* synchronized against open : rtnl_lock() held by caller */
2820         if (netif_running(dev)) {
2821                 u8 __iomem *base = get_hwbase(dev);
2822                 /*
2823                  * It seems that the nic preloads valid ring entries into an
2824                  * internal buffer. The procedure for flushing everything is
2825                  * guessed, there is probably a simpler approach.
2826                  * Changing the MTU is a rare event, it shouldn't matter.
2827                  */
2828                 nv_disable_irq(dev);
2829                 netif_tx_lock_bh(dev);
2830                 spin_lock(&np->lock);
2831                 /* stop engines */
2832                 nv_stop_rxtx(dev);
2833                 nv_txrx_reset(dev);
2834                 /* drain rx queue */
2835                 nv_drain_rxtx(dev);
2836                 /* reinit driver view of the rx queue */
2837                 set_bufsize(dev);
2838                 if (nv_init_ring(dev)) {
2839                         if (!np->in_shutdown)
2840                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2841                 }
2842                 /* reinit nic view of the rx queue */
2843                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2844                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2845                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2846                         base + NvRegRingSizes);
2847                 pci_push(base);
2848                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2849                 pci_push(base);
2850
2851                 /* restart rx engine */
2852                 nv_start_rxtx(dev);
2853                 spin_unlock(&np->lock);
2854                 netif_tx_unlock_bh(dev);
2855                 nv_enable_irq(dev);
2856         }
2857         return 0;
2858 }
2859
2860 static void nv_copy_mac_to_hw(struct net_device *dev)
2861 {
2862         u8 __iomem *base = get_hwbase(dev);
2863         u32 mac[2];
2864
2865         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2866                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2867         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2868
2869         writel(mac[0], base + NvRegMacAddrA);
2870         writel(mac[1], base + NvRegMacAddrB);
2871 }
2872
2873 /*
2874  * nv_set_mac_address: dev->set_mac_address function
2875  * Called with rtnl_lock() held.
2876  */
2877 static int nv_set_mac_address(struct net_device *dev, void *addr)
2878 {
2879         struct fe_priv *np = netdev_priv(dev);
2880         struct sockaddr *macaddr = (struct sockaddr*)addr;
2881
2882         if (!is_valid_ether_addr(macaddr->sa_data))
2883                 return -EADDRNOTAVAIL;
2884
2885         /* synchronized against open : rtnl_lock() held by caller */
2886         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2887
2888         if (netif_running(dev)) {
2889                 netif_tx_lock_bh(dev);
2890                 spin_lock_irq(&np->lock);
2891
2892                 /* stop rx engine */
2893                 nv_stop_rx(dev);
2894
2895                 /* set mac address */
2896                 nv_copy_mac_to_hw(dev);
2897
2898                 /* restart rx engine */
2899                 nv_start_rx(dev);
2900                 spin_unlock_irq(&np->lock);
2901                 netif_tx_unlock_bh(dev);
2902         } else {
2903                 nv_copy_mac_to_hw(dev);
2904         }
2905         return 0;
2906 }
2907
2908 /*
2909  * nv_set_multicast: dev->set_multicast function
2910  * Called with netif_tx_lock held.
2911  */
2912 static void nv_set_multicast(struct net_device *dev)
2913 {
2914         struct fe_priv *np = netdev_priv(dev);
2915         u8 __iomem *base = get_hwbase(dev);
2916         u32 addr[2];
2917         u32 mask[2];
2918         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2919
2920         memset(addr, 0, sizeof(addr));
2921         memset(mask, 0, sizeof(mask));
2922
2923         if (dev->flags & IFF_PROMISC) {
2924                 pff |= NVREG_PFF_PROMISC;
2925         } else {
2926                 pff |= NVREG_PFF_MYADDR;
2927
2928                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2929                         u32 alwaysOff[2];
2930                         u32 alwaysOn[2];
2931
2932                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2933                         if (dev->flags & IFF_ALLMULTI) {
2934                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2935                         } else {
2936                                 struct dev_mc_list *walk;
2937
2938                                 walk = dev->mc_list;
2939                                 while (walk != NULL) {
2940                                         u32 a, b;
2941                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2942                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2943                                         alwaysOn[0] &= a;
2944                                         alwaysOff[0] &= ~a;
2945                                         alwaysOn[1] &= b;
2946                                         alwaysOff[1] &= ~b;
2947                                         walk = walk->next;
2948                                 }
2949                         }
2950                         addr[0] = alwaysOn[0];
2951                         addr[1] = alwaysOn[1];
2952                         mask[0] = alwaysOn[0] | alwaysOff[0];
2953                         mask[1] = alwaysOn[1] | alwaysOff[1];
2954                 } else {
2955                         mask[0] = NVREG_MCASTMASKA_NONE;
2956                         mask[1] = NVREG_MCASTMASKB_NONE;
2957                 }
2958         }
2959         addr[0] |= NVREG_MCASTADDRA_FORCE;
2960         pff |= NVREG_PFF_ALWAYS;
2961         spin_lock_irq(&np->lock);
2962         nv_stop_rx(dev);
2963         writel(addr[0], base + NvRegMulticastAddrA);
2964         writel(addr[1], base + NvRegMulticastAddrB);
2965         writel(mask[0], base + NvRegMulticastMaskA);
2966         writel(mask[1], base + NvRegMulticastMaskB);
2967         writel(pff, base + NvRegPacketFilterFlags);
2968         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2969                 dev->name);
2970         nv_start_rx(dev);
2971         spin_unlock_irq(&np->lock);
2972 }
2973
2974 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2975 {
2976         struct fe_priv *np = netdev_priv(dev);
2977         u8 __iomem *base = get_hwbase(dev);
2978
2979         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2980
2981         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2982                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2983                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2984                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2985                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2986                 } else {
2987                         writel(pff, base + NvRegPacketFilterFlags);
2988                 }
2989         }
2990         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2991                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2992                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2993                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2994                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2995                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
2996                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
2997                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
2998                         writel(pause_enable,  base + NvRegTxPauseFrame);
2999                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3000                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3001                 } else {
3002                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3003                         writel(regmisc, base + NvRegMisc1);
3004                 }
3005         }
3006 }
3007
3008 /**
3009  * nv_update_linkspeed: Setup the MAC according to the link partner
3010  * @dev: Network device to be configured
3011  *
3012  * The function queries the PHY and checks if there is a link partner.
3013  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3014  * set to 10 MBit HD.
3015  *
3016  * The function returns 0 if there is no link partner and 1 if there is
3017  * a good link partner.
3018  */
3019 static int nv_update_linkspeed(struct net_device *dev)
3020 {
3021         struct fe_priv *np = netdev_priv(dev);
3022         u8 __iomem *base = get_hwbase(dev);
3023         int adv = 0;
3024         int lpa = 0;
3025         int adv_lpa, adv_pause, lpa_pause;
3026         int newls = np->linkspeed;
3027         int newdup = np->duplex;
3028         int mii_status;
3029         int retval = 0;
3030         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3031         u32 txrxFlags = 0;
3032         u32 phy_exp;
3033
3034         /* BMSR_LSTATUS is latched, read it twice:
3035          * we want the current value.
3036          */
3037         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3038         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3039
3040         if (!(mii_status & BMSR_LSTATUS)) {
3041                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3042                                 dev->name);
3043                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3044                 newdup = 0;
3045                 retval = 0;
3046                 goto set_speed;
3047         }
3048
3049         if (np->autoneg == 0) {
3050                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3051                                 dev->name, np->fixed_mode);
3052                 if (np->fixed_mode & LPA_100FULL) {
3053                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3054                         newdup = 1;
3055                 } else if (np->fixed_mode & LPA_100HALF) {
3056                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3057                         newdup = 0;
3058                 } else if (np->fixed_mode & LPA_10FULL) {
3059                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3060                         newdup = 1;
3061                 } else {
3062                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3063                         newdup = 0;
3064                 }
3065                 retval = 1;
3066                 goto set_speed;
3067         }
3068         /* check auto negotiation is complete */
3069         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3070                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3071                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3072                 newdup = 0;
3073                 retval = 0;
3074                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3075                 goto set_speed;
3076         }
3077
3078         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3079         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3080         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3081                                 dev->name, adv, lpa);
3082
3083         retval = 1;
3084         if (np->gigabit == PHY_GIGABIT) {
3085                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3086                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3087
3088                 if ((control_1000 & ADVERTISE_1000FULL) &&
3089                         (status_1000 & LPA_1000FULL)) {
3090                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3091                                 dev->name);
3092                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3093                         newdup = 1;
3094                         goto set_speed;
3095                 }
3096         }
3097
3098         /* FIXME: handle parallel detection properly */
3099         adv_lpa = lpa & adv;
3100         if (adv_lpa & LPA_100FULL) {
3101                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3102                 newdup = 1;
3103         } else if (adv_lpa & LPA_100HALF) {
3104                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3105                 newdup = 0;
3106         } else if (adv_lpa & LPA_10FULL) {
3107                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3108                 newdup = 1;
3109         } else if (adv_lpa & LPA_10HALF) {
3110                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3111                 newdup = 0;
3112         } else {
3113                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3114                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3115                 newdup = 0;
3116         }
3117
3118 set_speed:
3119         if (np->duplex == newdup && np->linkspeed == newls)
3120                 return retval;
3121
3122         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3123                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3124
3125         np->duplex = newdup;
3126         np->linkspeed = newls;
3127
3128         /* The transmitter and receiver must be restarted for safe update */
3129         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3130                 txrxFlags |= NV_RESTART_TX;
3131                 nv_stop_tx(dev);
3132         }
3133         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3134                 txrxFlags |= NV_RESTART_RX;
3135                 nv_stop_rx(dev);
3136         }
3137
3138         if (np->gigabit == PHY_GIGABIT) {
3139                 phyreg = readl(base + NvRegSlotTime);
3140                 phyreg &= ~(0x3FF00);
3141                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3142                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3143                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3144                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3145                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3146                 writel(phyreg, base + NvRegSlotTime);
3147         }
3148
3149         phyreg = readl(base + NvRegPhyInterface);
3150         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3151         if (np->duplex == 0)
3152                 phyreg |= PHY_HALF;
3153         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3154                 phyreg |= PHY_100;
3155         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3156                 phyreg |= PHY_1000;
3157         writel(phyreg, base + NvRegPhyInterface);
3158
3159         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3160         if (phyreg & PHY_RGMII) {
3161                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3162                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3163                 } else {
3164                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3165                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3166                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3167                                 else
3168                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3169                         } else {
3170                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3171                         }
3172                 }
3173         } else {
3174                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3175                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3176                 else
3177                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3178         }
3179         writel(txreg, base + NvRegTxDeferral);
3180
3181         if (np->desc_ver == DESC_VER_1) {
3182                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3183         } else {
3184                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3185                         txreg = NVREG_TX_WM_DESC2_3_1000;
3186                 else
3187                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3188         }
3189         writel(txreg, base + NvRegTxWatermark);
3190
3191         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3192                 base + NvRegMisc1);
3193         pci_push(base);
3194         writel(np->linkspeed, base + NvRegLinkSpeed);
3195         pci_push(base);
3196
3197         pause_flags = 0;
3198         /* setup pause frame */
3199         if (np->duplex != 0) {
3200                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3201                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3202                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3203
3204                         switch (adv_pause) {
3205                         case ADVERTISE_PAUSE_CAP:
3206                                 if (lpa_pause & LPA_PAUSE_CAP) {
3207                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3208                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3209                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3210                                 }
3211                                 break;
3212                         case ADVERTISE_PAUSE_ASYM:
3213                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3214                                 {
3215                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3216                                 }
3217                                 break;
3218                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3219                                 if (lpa_pause & LPA_PAUSE_CAP)
3220                                 {
3221                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3222                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3223                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3224                                 }
3225                                 if (lpa_pause == LPA_PAUSE_ASYM)
3226                                 {
3227                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3228                                 }
3229                                 break;
3230                         }
3231                 } else {
3232                         pause_flags = np->pause_flags;
3233                 }
3234         }
3235         nv_update_pause(dev, pause_flags);
3236
3237         if (txrxFlags & NV_RESTART_TX)
3238                 nv_start_tx(dev);
3239         if (txrxFlags & NV_RESTART_RX)
3240                 nv_start_rx(dev);
3241
3242         return retval;
3243 }
3244
3245 static void nv_linkchange(struct net_device *dev)
3246 {
3247         if (nv_update_linkspeed(dev)) {
3248                 if (!netif_carrier_ok(dev)) {
3249                         netif_carrier_on(dev);
3250                         printk(KERN_INFO "%s: link up.\n", dev->name);
3251                         nv_start_rx(dev);
3252                 }
3253         } else {
3254                 if (netif_carrier_ok(dev)) {
3255                         netif_carrier_off(dev);
3256                         printk(KERN_INFO "%s: link down.\n", dev->name);
3257                         nv_stop_rx(dev);
3258                 }
3259         }
3260 }
3261
3262 static void nv_link_irq(struct net_device *dev)
3263 {
3264         u8 __iomem *base = get_hwbase(dev);
3265         u32 miistat;
3266
3267         miistat = readl(base + NvRegMIIStatus);
3268         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3269         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3270
3271         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3272                 nv_linkchange(dev);
3273         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3274 }
3275
3276 static irqreturn_t nv_nic_irq(int foo, void *data)
3277 {
3278         struct net_device *dev = (struct net_device *) data;
3279         struct fe_priv *np = netdev_priv(dev);
3280         u8 __iomem *base = get_hwbase(dev);
3281         u32 events;
3282         int i;
3283
3284         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3285
3286         for (i=0; ; i++) {
3287                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3288                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3289                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3290                 } else {
3291                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3292                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3293                 }
3294                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3295                 if (!(events & np->irqmask))
3296                         break;
3297
3298                 spin_lock(&np->lock);
3299                 nv_tx_done(dev);
3300                 spin_unlock(&np->lock);
3301
3302 #ifdef CONFIG_FORCEDETH_NAPI
3303                 if (events & NVREG_IRQ_RX_ALL) {
3304                         netif_rx_schedule(dev, &np->napi);
3305
3306                         /* Disable furthur receive irq's */
3307                         spin_lock(&np->lock);
3308                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3309
3310                         if (np->msi_flags & NV_MSI_X_ENABLED)
3311                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3312                         else
3313                                 writel(np->irqmask, base + NvRegIrqMask);
3314                         spin_unlock(&np->lock);
3315                 }
3316 #else
3317                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3318                         if (unlikely(nv_alloc_rx(dev))) {
3319                                 spin_lock(&np->lock);
3320                                 if (!np->in_shutdown)
3321                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3322                                 spin_unlock(&np->lock);
3323                         }
3324                 }
3325 #endif
3326                 if (unlikely(events & NVREG_IRQ_LINK)) {
3327                         spin_lock(&np->lock);
3328                         nv_link_irq(dev);
3329                         spin_unlock(&np->lock);
3330                 }
3331                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3332                         spin_lock(&np->lock);
3333                         nv_linkchange(dev);
3334                         spin_unlock(&np->lock);
3335                         np->link_timeout = jiffies + LINK_TIMEOUT;
3336                 }
3337                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3338                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3339                                                 dev->name, events);
3340                 }
3341                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3342                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3343                                                 dev->name, events);
3344                 }
3345                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3346                         spin_lock(&np->lock);
3347                         /* disable interrupts on the nic */
3348                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3349                                 writel(0, base + NvRegIrqMask);
3350                         else
3351                                 writel(np->irqmask, base + NvRegIrqMask);
3352                         pci_push(base);
3353
3354                         if (!np->in_shutdown) {
3355                                 np->nic_poll_irq = np->irqmask;
3356                                 np->recover_error = 1;
3357                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3358                         }
3359                         spin_unlock(&np->lock);
3360                         break;
3361                 }
3362                 if (unlikely(i > max_interrupt_work)) {
3363                         spin_lock(&np->lock);
3364                         /* disable interrupts on the nic */
3365                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3366                                 writel(0, base + NvRegIrqMask);
3367                         else
3368                                 writel(np->irqmask, base + NvRegIrqMask);
3369                         pci_push(base);
3370
3371                         if (!np->in_shutdown) {
3372                                 np->nic_poll_irq = np->irqmask;
3373                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3374                         }
3375                         spin_unlock(&np->lock);
3376                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3377                         break;
3378                 }
3379
3380         }
3381         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3382
3383         return IRQ_RETVAL(i);
3384 }
3385
3386 /**
3387  * All _optimized functions are used to help increase performance
3388  * (reduce CPU and increase throughput). They use descripter version 3,
3389  * compiler directives, and reduce memory accesses.
3390  */
3391 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3392 {
3393         struct net_device *dev = (struct net_device *) data;
3394         struct fe_priv *np = netdev_priv(dev);
3395         u8 __iomem *base = get_hwbase(dev);
3396         u32 events;
3397         int i;
3398
3399         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3400
3401         for (i=0; ; i++) {
3402                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3403                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3404                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3405                 } else {
3406                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3407                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3408                 }
3409                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3410                 if (!(events & np->irqmask))
3411                         break;
3412
3413                 spin_lock(&np->lock);
3414                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3415                 spin_unlock(&np->lock);
3416
3417 #ifdef CONFIG_FORCEDETH_NAPI
3418                 if (events & NVREG_IRQ_RX_ALL) {
3419                         netif_rx_schedule(dev, &np->napi);
3420
3421                         /* Disable furthur receive irq's */
3422                         spin_lock(&np->lock);
3423                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3424
3425                         if (np->msi_flags & NV_MSI_X_ENABLED)
3426                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3427                         else
3428                                 writel(np->irqmask, base + NvRegIrqMask);
3429                         spin_unlock(&np->lock);
3430                 }
3431 #else
3432                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3433                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3434                                 spin_lock(&np->lock);
3435                                 if (!np->in_shutdown)
3436                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3437                                 spin_unlock(&np->lock);
3438                         }
3439                 }
3440 #endif
3441                 if (unlikely(events & NVREG_IRQ_LINK)) {
3442                         spin_lock(&np->lock);
3443                         nv_link_irq(dev);
3444                         spin_unlock(&np->lock);
3445                 }
3446                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3447                         spin_lock(&np->lock);
3448                         nv_linkchange(dev);
3449                         spin_unlock(&np->lock);
3450                         np->link_timeout = jiffies + LINK_TIMEOUT;
3451                 }
3452                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3453                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3454                                                 dev->name, events);
3455                 }
3456                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3457                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3458                                                 dev->name, events);
3459                 }
3460                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3461                         spin_lock(&np->lock);
3462                         /* disable interrupts on the nic */
3463                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3464                                 writel(0, base + NvRegIrqMask);
3465                         else
3466                                 writel(np->irqmask, base + NvRegIrqMask);
3467                         pci_push(base);
3468
3469                         if (!np->in_shutdown) {
3470                                 np->nic_poll_irq = np->irqmask;
3471                                 np->recover_error = 1;
3472                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3473                         }
3474                         spin_unlock(&np->lock);
3475                         break;
3476                 }
3477
3478                 if (unlikely(i > max_interrupt_work)) {
3479                         spin_lock(&np->lock);
3480                         /* disable interrupts on the nic */
3481                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3482                                 writel(0, base + NvRegIrqMask);
3483                         else
3484                                 writel(np->irqmask, base + NvRegIrqMask);
3485                         pci_push(base);
3486
3487                         if (!np->in_shutdown) {
3488                                 np->nic_poll_irq = np->irqmask;
3489                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3490                         }
3491                         spin_unlock(&np->lock);
3492                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3493                         break;
3494                 }
3495
3496         }
3497         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3498
3499         return IRQ_RETVAL(i);
3500 }
3501
3502 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3503 {
3504         struct net_device *dev = (struct net_device *) data;
3505         struct fe_priv *np = netdev_priv(dev);
3506         u8 __iomem *base = get_hwbase(dev);
3507         u32 events;
3508         int i;
3509         unsigned long flags;
3510
3511         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3512
3513         for (i=0; ; i++) {
3514                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3515                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3516                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3517                 if (!(events & np->irqmask))
3518                         break;
3519
3520                 spin_lock_irqsave(&np->lock, flags);
3521                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3522                 spin_unlock_irqrestore(&np->lock, flags);
3523
3524                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3525                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3526                                                 dev->name, events);
3527                 }
3528                 if (unlikely(i > max_interrupt_work)) {
3529                         spin_lock_irqsave(&np->lock, flags);
3530                         /* disable interrupts on the nic */
3531                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3532                         pci_push(base);
3533
3534                         if (!np->in_shutdown) {
3535                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3536                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3537                         }
3538                         spin_unlock_irqrestore(&np->lock, flags);
3539                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3540                         break;
3541                 }
3542
3543         }
3544         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3545
3546         return IRQ_RETVAL(i);
3547 }
3548
3549 #ifdef CONFIG_FORCEDETH_NAPI
3550 static int nv_napi_poll(struct napi_struct *napi, int budget)
3551 {
3552         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3553         struct net_device *dev = np->dev;
3554         u8 __iomem *base = get_hwbase(dev);
3555         unsigned long flags;
3556         int pkts, retcode;
3557
3558         if (!nv_optimized(np)) {
3559                 pkts = nv_rx_process(dev, budget);
3560                 retcode = nv_alloc_rx(dev);
3561         } else {
3562                 pkts = nv_rx_process_optimized(dev, budget);
3563                 retcode = nv_alloc_rx_optimized(dev);
3564         }
3565
3566         if (retcode) {
3567                 spin_lock_irqsave(&np->lock, flags);
3568                 if (!np->in_shutdown)
3569                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3570                 spin_unlock_irqrestore(&np->lock, flags);
3571         }
3572
3573         if (pkts < budget) {
3574                 /* re-enable receive interrupts */
3575                 spin_lock_irqsave(&np->lock, flags);
3576
3577                 __netif_rx_complete(dev, napi);
3578
3579                 np->irqmask |= NVREG_IRQ_RX_ALL;
3580                 if (np->msi_flags & NV_MSI_X_ENABLED)
3581                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3582                 else
3583                         writel(np->irqmask, base + NvRegIrqMask);
3584
3585                 spin_unlock_irqrestore(&np->lock, flags);
3586         }
3587         return pkts;
3588 }
3589 #endif
3590
3591 #ifdef CONFIG_FORCEDETH_NAPI
3592 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3593 {
3594         struct net_device *dev = (struct net_device *) data;
3595         struct fe_priv *np = netdev_priv(dev);
3596         u8 __iomem *base = get_hwbase(dev);
3597         u32 events;
3598
3599         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3600         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3601
3602         if (events) {
3603                 netif_rx_schedule(dev, &np->napi);
3604                 /* disable receive interrupts on the nic */
3605                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3606                 pci_push(base);
3607         }
3608         return IRQ_HANDLED;
3609 }
3610 #else
3611 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3612 {
3613         struct net_device *dev = (struct net_device *) data;
3614         struct fe_priv *np = netdev_priv(dev);
3615         u8 __iomem *base = get_hwbase(dev);
3616         u32 events;
3617         int i;
3618         unsigned long flags;
3619
3620         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3621
3622         for (i=0; ; i++) {
3623                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3624                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3625                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3626                 if (!(events & np->irqmask))
3627                         break;
3628
3629                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3630                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3631                                 spin_lock_irqsave(&np->lock, flags);
3632                                 if (!np->in_shutdown)
3633                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3634                                 spin_unlock_irqrestore(&np->lock, flags);
3635                         }
3636                 }
3637
3638                 if (unlikely(i > max_interrupt_work)) {
3639                         spin_lock_irqsave(&np->lock, flags);
3640                         /* disable interrupts on the nic */
3641                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3642                         pci_push(base);
3643
3644                         if (!np->in_shutdown) {
3645                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3646                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3647                         }
3648                         spin_unlock_irqrestore(&np->lock, flags);
3649                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3650                         break;
3651                 }
3652         }
3653         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3654
3655         return IRQ_RETVAL(i);
3656 }
3657 #endif
3658
3659 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3660 {
3661         struct net_device *dev = (struct net_device *) data;
3662         struct fe_priv *np = netdev_priv(dev);
3663         u8 __iomem *base = get_hwbase(dev);
3664         u32 events;
3665         int i;
3666         unsigned long flags;
3667
3668         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3669
3670         for (i=0; ; i++) {
3671                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3672                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3673                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3674                 if (!(events & np->irqmask))
3675                         break;
3676
3677                 /* check tx in case we reached max loop limit in tx isr */
3678                 spin_lock_irqsave(&np->lock, flags);
3679                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3680                 spin_unlock_irqrestore(&np->lock, flags);
3681
3682                 if (events & NVREG_IRQ_LINK) {
3683                         spin_lock_irqsave(&np->lock, flags);
3684                         nv_link_irq(dev);
3685                         spin_unlock_irqrestore(&np->lock, flags);
3686                 }
3687                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3688                         spin_lock_irqsave(&np->lock, flags);
3689                         nv_linkchange(dev);
3690                         spin_unlock_irqrestore(&np->lock, flags);
3691                         np->link_timeout = jiffies + LINK_TIMEOUT;
3692                 }
3693                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3694                         spin_lock_irq(&np->lock);
3695                         /* disable interrupts on the nic */
3696                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3697                         pci_push(base);
3698
3699                         if (!np->in_shutdown) {
3700                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3701                                 np->recover_error = 1;
3702                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3703                         }
3704                         spin_unlock_irq(&np->lock);
3705                         break;
3706                 }
3707                 if (events & (NVREG_IRQ_UNKNOWN)) {
3708                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3709                                                 dev->name, events);
3710                 }
3711                 if (unlikely(i > max_interrupt_work)) {
3712                         spin_lock_irqsave(&np->lock, flags);
3713                         /* disable interrupts on the nic */
3714                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3715                         pci_push(base);
3716
3717                         if (!np->in_shutdown) {
3718                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3719                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3720                         }
3721                         spin_unlock_irqrestore(&np->lock, flags);
3722                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3723                         break;
3724                 }
3725
3726         }
3727         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3728
3729         return IRQ_RETVAL(i);
3730 }
3731
3732 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3733 {
3734         struct net_device *dev = (struct net_device *) data;
3735         struct fe_priv *np = netdev_priv(dev);
3736         u8 __iomem *base = get_hwbase(dev);
3737         u32 events;
3738
3739         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3740
3741         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3742                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3743                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3744         } else {
3745                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3746                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3747         }
3748         pci_push(base);
3749         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3750         if (!(events & NVREG_IRQ_TIMER))
3751                 return IRQ_RETVAL(0);
3752
3753         spin_lock(&np->lock);
3754         np->intr_test = 1;
3755         spin_unlock(&np->lock);
3756
3757         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3758
3759         return IRQ_RETVAL(1);
3760 }
3761
3762 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3763 {
3764         u8 __iomem *base = get_hwbase(dev);
3765         int i;
3766         u32 msixmap = 0;
3767
3768         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3769          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3770          * the remaining 8 interrupts.
3771          */
3772         for (i = 0; i < 8; i++) {
3773                 if ((irqmask >> i) & 0x1) {
3774                         msixmap |= vector << (i << 2);
3775                 }
3776         }
3777         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3778
3779         msixmap = 0;
3780         for (i = 0; i < 8; i++) {
3781                 if ((irqmask >> (i + 8)) & 0x1) {
3782                         msixmap |= vector << (i << 2);
3783                 }
3784         }
3785         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3786 }
3787
3788 static int nv_request_irq(struct net_device *dev, int intr_test)
3789 {
3790         struct fe_priv *np = get_nvpriv(dev);
3791         u8 __iomem *base = get_hwbase(dev);
3792         int ret = 1;
3793         int i;
3794         irqreturn_t (*handler)(int foo, void *data);
3795
3796         if (intr_test) {
3797                 handler = nv_nic_irq_test;
3798         } else {
3799                 if (nv_optimized(np))
3800                         handler = nv_nic_irq_optimized;
3801                 else
3802                         handler = nv_nic_irq;
3803         }
3804
3805         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3806                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3807                         np->msi_x_entry[i].entry = i;
3808                 }
3809                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3810                         np->msi_flags |= NV_MSI_X_ENABLED;
3811                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3812                                 /* Request irq for rx handling */
3813                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3814                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3815                                         pci_disable_msix(np->pci_dev);
3816                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3817                                         goto out_err;
3818                                 }
3819                                 /* Request irq for tx handling */
3820                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3821                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3822                                         pci_disable_msix(np->pci_dev);
3823                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3824                                         goto out_free_rx;
3825                                 }
3826                                 /* Request irq for link and timer handling */
3827                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3828                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3829                                         pci_disable_msix(np->pci_dev);
3830                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3831                                         goto out_free_tx;
3832                                 }
3833                                 /* map interrupts to their respective vector */
3834                                 writel(0, base + NvRegMSIXMap0);
3835                                 writel(0, base + NvRegMSIXMap1);
3836                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3837                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3838                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3839                         } else {
3840                                 /* Request irq for all interrupts */
3841                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3842                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3843                                         pci_disable_msix(np->pci_dev);
3844                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3845                                         goto out_err;
3846                                 }
3847
3848                                 /* map interrupts to vector 0 */
3849                                 writel(0, base + NvRegMSIXMap0);
3850                                 writel(0, base + NvRegMSIXMap1);
3851                         }
3852                 }
3853         }
3854         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3855                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3856                         np->msi_flags |= NV_MSI_ENABLED;
3857                         dev->irq = np->pci_dev->irq;
3858                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3859                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3860                                 pci_disable_msi(np->pci_dev);
3861                                 np->msi_flags &= ~NV_MSI_ENABLED;
3862                                 dev->irq = np->pci_dev->irq;
3863                                 goto out_err;
3864                         }
3865
3866                         /* map interrupts to vector 0 */
3867                         writel(0, base + NvRegMSIMap0);
3868                         writel(0, base + NvRegMSIMap1);
3869                         /* enable msi vector 0 */
3870                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3871                 }
3872         }
3873         if (ret != 0) {
3874                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3875                         goto out_err;
3876
3877         }
3878
3879         return 0;
3880 out_free_tx:
3881         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3882 out_free_rx:
3883         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3884 out_err:
3885         return 1;
3886 }
3887
3888 static void nv_free_irq(struct net_device *dev)
3889 {
3890         struct fe_priv *np = get_nvpriv(dev);
3891         int i;
3892
3893         if (np->msi_flags & NV_MSI_X_ENABLED) {
3894                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3895                         free_irq(np->msi_x_entry[i].vector, dev);
3896                 }
3897                 pci_disable_msix(np->pci_dev);
3898                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3899         } else {
3900                 free_irq(np->pci_dev->irq, dev);
3901                 if (np->msi_flags & NV_MSI_ENABLED) {
3902                         pci_disable_msi(np->pci_dev);
3903                         np->msi_flags &= ~NV_MSI_ENABLED;
3904                 }
3905         }
3906 }
3907
3908 static void nv_do_nic_poll(unsigned long data)
3909 {
3910         struct net_device *dev = (struct net_device *) data;
3911         struct fe_priv *np = netdev_priv(dev);
3912         u8 __iomem *base = get_hwbase(dev);
3913         u32 mask = 0;
3914
3915         /*
3916          * First disable irq(s) and then
3917          * reenable interrupts on the nic, we have to do this before calling
3918          * nv_nic_irq because that may decide to do otherwise
3919          */
3920
3921         if (!using_multi_irqs(dev)) {
3922                 if (np->msi_flags & NV_MSI_X_ENABLED)
3923                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3924                 else
3925                         disable_irq_lockdep(np->pci_dev->irq);
3926                 mask = np->irqmask;
3927         } else {
3928                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3929                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3930                         mask |= NVREG_IRQ_RX_ALL;
3931                 }
3932                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3933                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3934                         mask |= NVREG_IRQ_TX_ALL;
3935                 }
3936                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3937                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3938                         mask |= NVREG_IRQ_OTHER;
3939                 }
3940         }
3941         np->nic_poll_irq = 0;
3942
3943         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3944
3945         if (np->recover_error) {
3946                 np->recover_error = 0;
3947                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3948                 if (netif_running(dev)) {
3949                         netif_tx_lock_bh(dev);
3950                         spin_lock(&np->lock);
3951                         /* stop engines */
3952                         nv_stop_rxtx(dev);
3953                         nv_txrx_reset(dev);
3954                         /* drain rx queue */
3955                         nv_drain_rxtx(dev);
3956                         /* reinit driver view of the rx queue */
3957                         set_bufsize(dev);
3958                         if (nv_init_ring(dev)) {
3959                                 if (!np->in_shutdown)
3960                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3961                         }
3962                         /* reinit nic view of the rx queue */
3963                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3964                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3965                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3966                                 base + NvRegRingSizes);
3967                         pci_push(base);
3968                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3969                         pci_push(base);
3970
3971                         /* restart rx engine */
3972                         nv_start_rxtx(dev);
3973                         spin_unlock(&np->lock);
3974                         netif_tx_unlock_bh(dev);
3975                 }
3976         }
3977
3978
3979         writel(mask, base + NvRegIrqMask);
3980         pci_push(base);
3981
3982         if (!using_multi_irqs(dev)) {
3983                 if (nv_optimized(np))
3984                         nv_nic_irq_optimized(0, dev);
3985                 else
3986                         nv_nic_irq(0, dev);
3987                 if (np->msi_flags & NV_MSI_X_ENABLED)
3988                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3989                 else
3990                         enable_irq_lockdep(np->pci_dev->irq);
3991         } else {
3992                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3993                         nv_nic_irq_rx(0, dev);
3994                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3995                 }
3996                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3997                         nv_nic_irq_tx(0, dev);
3998                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3999                 }
4000                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4001                         nv_nic_irq_other(0, dev);
4002                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4003                 }
4004         }
4005 }
4006
4007 #ifdef CONFIG_NET_POLL_CONTROLLER
4008 static void nv_poll_controller(struct net_device *dev)
4009 {
4010         nv_do_nic_poll((unsigned long) dev);
4011 }
4012 #endif
4013
4014 static void nv_do_stats_poll(unsigned long data)
4015 {
4016         struct net_device *dev = (struct net_device *) data;
4017         struct fe_priv *np = netdev_priv(dev);
4018
4019         nv_get_hw_stats(dev);
4020
4021         if (!np->in_shutdown)
4022                 mod_timer(&np->stats_poll,
4023                         round_jiffies(jiffies + STATS_INTERVAL));
4024 }
4025
4026 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4027 {
4028         struct fe_priv *np = netdev_priv(dev);
4029         strcpy(info->driver, DRV_NAME);
4030         strcpy(info->version, FORCEDETH_VERSION);
4031         strcpy(info->bus_info, pci_name(np->pci_dev));
4032 }
4033
4034 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4035 {
4036         struct fe_priv *np = netdev_priv(dev);
4037         wolinfo->supported = WAKE_MAGIC;
4038
4039         spin_lock_irq(&np->lock);
4040         if (np->wolenabled)
4041                 wolinfo->wolopts = WAKE_MAGIC;
4042         spin_unlock_irq(&np->lock);
4043 }
4044
4045 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4046 {
4047         struct fe_priv *np = netdev_priv(dev);
4048         u8 __iomem *base = get_hwbase(dev);
4049         u32 flags = 0;
4050
4051         if (wolinfo->wolopts == 0) {
4052                 np->wolenabled = 0;
4053         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4054                 np->wolenabled = 1;
4055                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4056         }
4057         if (netif_running(dev)) {
4058                 spin_lock_irq(&np->lock);
4059                 writel(flags, base + NvRegWakeUpFlags);
4060                 spin_unlock_irq(&np->lock);
4061         }
4062         return 0;
4063 }
4064
4065 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4066 {
4067         struct fe_priv *np = netdev_priv(dev);
4068         int adv;
4069
4070         spin_lock_irq(&np->lock);
4071         ecmd->port = PORT_MII;
4072         if (!netif_running(dev)) {
4073                 /* We do not track link speed / duplex setting if the
4074                  * interface is disabled. Force a link check */
4075                 if (nv_update_linkspeed(dev)) {
4076                         if (!netif_carrier_ok(dev))
4077                                 netif_carrier_on(dev);
4078                 } else {
4079                         if (netif_carrier_ok(dev))
4080                                 netif_carrier_off(dev);
4081                 }
4082         }
4083
4084         if (netif_carrier_ok(dev)) {
4085                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4086                 case NVREG_LINKSPEED_10:
4087                         ecmd->speed = SPEED_10;
4088                         break;
4089                 case NVREG_LINKSPEED_100:
4090                         ecmd->speed = SPEED_100;
4091                         break;
4092                 case NVREG_LINKSPEED_1000:
4093                         ecmd->speed = SPEED_1000;
4094                         break;
4095                 }
4096                 ecmd->duplex = DUPLEX_HALF;
4097                 if (np->duplex)
4098                         ecmd->duplex = DUPLEX_FULL;
4099         } else {
4100                 ecmd->speed = -1;
4101                 ecmd->duplex = -1;
4102         }
4103
4104         ecmd->autoneg = np->autoneg;
4105
4106         ecmd->advertising = ADVERTISED_MII;
4107         if (np->autoneg) {
4108                 ecmd->advertising |= ADVERTISED_Autoneg;
4109                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4110                 if (adv & ADVERTISE_10HALF)
4111                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4112                 if (adv & ADVERTISE_10FULL)
4113                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4114                 if (adv & ADVERTISE_100HALF)
4115                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4116                 if (adv & ADVERTISE_100FULL)
4117                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4118                 if (np->gigabit == PHY_GIGABIT) {
4119                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4120                         if (adv & ADVERTISE_1000FULL)
4121                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4122                 }
4123         }
4124         ecmd->supported = (SUPPORTED_Autoneg |
4125                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4126                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4127                 SUPPORTED_MII);
4128         if (np->gigabit == PHY_GIGABIT)
4129                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4130
4131         ecmd->phy_address = np->phyaddr;
4132         ecmd->transceiver = XCVR_EXTERNAL;
4133
4134         /* ignore maxtxpkt, maxrxpkt for now */
4135         spin_unlock_irq(&np->lock);
4136         return 0;
4137 }
4138
4139 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4140 {
4141         struct fe_priv *np = netdev_priv(dev);
4142
4143         if (ecmd->port != PORT_MII)
4144                 return -EINVAL;
4145         if (ecmd->transceiver != XCVR_EXTERNAL)
4146                 return -EINVAL;
4147         if (ecmd->phy_address != np->phyaddr) {
4148                 /* TODO: support switching between multiple phys. Should be
4149                  * trivial, but not enabled due to lack of test hardware. */
4150                 return -EINVAL;
4151         }
4152         if (ecmd->autoneg == AUTONEG_ENABLE) {
4153                 u32 mask;
4154
4155                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4156                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4157                 if (np->gigabit == PHY_GIGABIT)
4158                         mask |= ADVERTISED_1000baseT_Full;
4159
4160                 if ((ecmd->advertising & mask) == 0)
4161                         return -EINVAL;
4162
4163         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4164                 /* Note: autonegotiation disable, speed 1000 intentionally
4165                  * forbidden - noone should need that. */
4166
4167                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4168                         return -EINVAL;
4169                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4170                         return -EINVAL;
4171         } else {
4172                 return -EINVAL;
4173         }
4174
4175         netif_carrier_off(dev);
4176         if (netif_running(dev)) {
4177                 nv_disable_irq(dev);
4178                 netif_tx_lock_bh(dev);
4179                 spin_lock(&np->lock);
4180                 /* stop engines */
4181                 nv_stop_rxtx(dev);
4182                 spin_unlock(&np->lock);
4183                 netif_tx_unlock_bh(dev);
4184         }
4185
4186         if (ecmd->autoneg == AUTONEG_ENABLE) {
4187                 int adv, bmcr;
4188
4189                 np->autoneg = 1;
4190
4191                 /* advertise only what has been requested */
4192                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4193                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4194                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4195                         adv |= ADVERTISE_10HALF;
4196                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4197                         adv |= ADVERTISE_10FULL;
4198                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4199                         adv |= ADVERTISE_100HALF;
4200                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4201                         adv |= ADVERTISE_100FULL;
4202                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4203                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4204                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4205                         adv |=  ADVERTISE_PAUSE_ASYM;
4206                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4207
4208                 if (np->gigabit == PHY_GIGABIT) {
4209                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4210                         adv &= ~ADVERTISE_1000FULL;
4211                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4212                                 adv |= ADVERTISE_1000FULL;
4213                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4214                 }
4215
4216                 if (netif_running(dev))
4217                         printk(KERN_INFO "%s: link down.\n", dev->name);
4218                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4219                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4220                         bmcr |= BMCR_ANENABLE;
4221                         /* reset the phy in order for settings to stick,
4222                          * and cause autoneg to start */
4223                         if (phy_reset(dev, bmcr)) {
4224                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4225                                 return -EINVAL;
4226                         }
4227                 } else {
4228                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4229                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4230                 }
4231         } else {
4232                 int adv, bmcr;
4233
4234                 np->autoneg = 0;
4235
4236                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4237                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4238                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4239                         adv |= ADVERTISE_10HALF;
4240                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4241                         adv |= ADVERTISE_10FULL;
4242                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4243                         adv |= ADVERTISE_100HALF;
4244                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4245                         adv |= ADVERTISE_100FULL;
4246                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4247                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4248                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4249                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4250                 }
4251                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4252                         adv |=  ADVERTISE_PAUSE_ASYM;
4253                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4254                 }
4255                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4256                 np->fixed_mode = adv;
4257
4258                 if (np->gigabit == PHY_GIGABIT) {
4259                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4260                         adv &= ~ADVERTISE_1000FULL;
4261                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4262                 }
4263
4264                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4265                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4266                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4267                         bmcr |= BMCR_FULLDPLX;
4268                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4269                         bmcr |= BMCR_SPEED100;
4270                 if (np->phy_oui == PHY_OUI_MARVELL) {
4271                         /* reset the phy in order for forced mode settings to stick */
4272                         if (phy_reset(dev, bmcr)) {
4273                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4274                                 return -EINVAL;
4275                         }
4276                 } else {
4277                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4278                         if (netif_running(dev)) {
4279                                 /* Wait a bit and then reconfigure the nic. */
4280                                 udelay(10);
4281                                 nv_linkchange(dev);
4282                         }
4283                 }
4284         }
4285
4286         if (netif_running(dev)) {
4287                 nv_start_rxtx(dev);
4288                 nv_enable_irq(dev);
4289         }
4290
4291         return 0;
4292 }
4293
4294 #define FORCEDETH_REGS_VER      1
4295
4296 static int nv_get_regs_len(struct net_device *dev)
4297 {
4298         struct fe_priv *np = netdev_priv(dev);
4299         return np->register_size;
4300 }
4301
4302 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4303 {
4304         struct fe_priv *np = netdev_priv(dev);
4305         u8 __iomem *base = get_hwbase(dev);
4306         u32 *rbuf = buf;
4307         int i;
4308
4309         regs->version = FORCEDETH_REGS_VER;
4310         spin_lock_irq(&np->lock);
4311         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4312                 rbuf[i] = readl(base + i*sizeof(u32));
4313         spin_unlock_irq(&np->lock);
4314 }
4315
4316 static int nv_nway_reset(struct net_device *dev)
4317 {
4318         struct fe_priv *np = netdev_priv(dev);
4319         int ret;
4320
4321         if (np->autoneg) {
4322                 int bmcr;
4323
4324                 netif_carrier_off(dev);
4325                 if (netif_running(dev)) {
4326                         nv_disable_irq(dev);
4327                         netif_tx_lock_bh(dev);
4328                         spin_lock(&np->lock);
4329                         /* stop engines */
4330                         nv_stop_rxtx(dev);
4331                         spin_unlock(&np->lock);
4332                         netif_tx_unlock_bh(dev);
4333                         printk(KERN_INFO "%s: link down.\n", dev->name);
4334                 }
4335
4336                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4337                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4338                         bmcr |= BMCR_ANENABLE;
4339                         /* reset the phy in order for settings to stick*/
4340                         if (phy_reset(dev, bmcr)) {
4341                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4342                                 return -EINVAL;
4343                         }
4344                 } else {
4345                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4346                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4347                 }
4348
4349                 if (netif_running(dev)) {
4350                         nv_start_rxtx(dev);
4351                         nv_enable_irq(dev);
4352                 }
4353                 ret = 0;
4354         } else {
4355                 ret = -EINVAL;
4356         }
4357
4358         return ret;
4359 }
4360
4361 static int nv_set_tso(struct net_device *dev, u32 value)
4362 {
4363         struct fe_priv *np = netdev_priv(dev);
4364
4365         if ((np->driver_data & DEV_HAS_CHECKSUM))
4366                 return ethtool_op_set_tso(dev, value);
4367         else
4368                 return -EOPNOTSUPP;
4369 }
4370
4371 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4372 {
4373         struct fe_priv *np = netdev_priv(dev);
4374
4375         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4376         ring->rx_mini_max_pending = 0;
4377         ring->rx_jumbo_max_pending = 0;
4378         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4379
4380         ring->rx_pending = np->rx_ring_size;
4381         ring->rx_mini_pending = 0;
4382         ring->rx_jumbo_pending = 0;
4383         ring->tx_pending = np->tx_ring_size;
4384 }
4385
4386 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4387 {
4388         struct fe_priv *np = netdev_priv(dev);
4389         u8 __iomem *base = get_hwbase(dev);
4390         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4391         dma_addr_t ring_addr;
4392
4393         if (ring->rx_pending < RX_RING_MIN ||
4394             ring->tx_pending < TX_RING_MIN ||
4395             ring->rx_mini_pending != 0 ||
4396             ring->rx_jumbo_pending != 0 ||
4397             (np->desc_ver == DESC_VER_1 &&
4398              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4399               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4400             (np->desc_ver != DESC_VER_1 &&
4401              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4402               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4403                 return -EINVAL;
4404         }
4405
4406         /* allocate new rings */
4407         if (!nv_optimized(np)) {
4408                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4409                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4410                                             &ring_addr);
4411         } else {
4412                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4413                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4414                                             &ring_addr);
4415         }
4416         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4417         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4418         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4419                 /* fall back to old rings */
4420                 if (!nv_optimized(np)) {
4421                         if (rxtx_ring)
4422                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4423                                                     rxtx_ring, ring_addr);
4424                 } else {
4425                         if (rxtx_ring)
4426                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4427                                                     rxtx_ring, ring_addr);
4428                 }
4429                 if (rx_skbuff)
4430                         kfree(rx_skbuff);
4431                 if (tx_skbuff)
4432                         kfree(tx_skbuff);
4433                 goto exit;
4434         }
4435
4436         if (netif_running(dev)) {
4437                 nv_disable_irq(dev);
4438                 netif_tx_lock_bh(dev);
4439                 spin_lock(&np->lock);
4440                 /* stop engines */
4441                 nv_stop_rxtx(dev);
4442                 nv_txrx_reset(dev);
4443                 /* drain queues */
4444                 nv_drain_rxtx(dev);
4445                 /* delete queues */
4446                 free_rings(dev);
4447         }
4448
4449         /* set new values */
4450         np->rx_ring_size = ring->rx_pending;
4451         np->tx_ring_size = ring->tx_pending;
4452
4453         if (!nv_optimized(np)) {
4454                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4455                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4456         } else {
4457                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4458                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4459         }
4460         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4461         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4462         np->ring_addr = ring_addr;
4463
4464         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4465         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4466
4467         if (netif_running(dev)) {
4468                 /* reinit driver view of the queues */
4469                 set_bufsize(dev);
4470                 if (nv_init_ring(dev)) {
4471                         if (!np->in_shutdown)
4472                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4473                 }
4474
4475                 /* reinit nic view of the queues */
4476                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4477                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4478                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4479                         base + NvRegRingSizes);
4480                 pci_push(base);
4481                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4482                 pci_push(base);
4483
4484                 /* restart engines */
4485                 nv_start_rxtx(dev);
4486                 spin_unlock(&np->lock);
4487                 netif_tx_unlock_bh(dev);
4488                 nv_enable_irq(dev);
4489         }
4490         return 0;
4491 exit:
4492         return -ENOMEM;
4493 }
4494
4495 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4496 {
4497         struct fe_priv *np = netdev_priv(dev);
4498
4499         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4500         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4501         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4502 }
4503
4504 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4505 {
4506         struct fe_priv *np = netdev_priv(dev);
4507         int adv, bmcr;
4508
4509         if ((!np->autoneg && np->duplex == 0) ||
4510             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4511                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4512                        dev->name);
4513                 return -EINVAL;
4514         }
4515         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4516                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4517                 return -EINVAL;
4518         }
4519
4520         netif_carrier_off(dev);
4521         if (netif_running(dev)) {
4522                 nv_disable_irq(dev);
4523                 netif_tx_lock_bh(dev);
4524                 spin_lock(&np->lock);
4525                 /* stop engines */
4526                 nv_stop_rxtx(dev);
4527                 spin_unlock(&np->lock);
4528                 netif_tx_unlock_bh(dev);
4529         }
4530
4531         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4532         if (pause->rx_pause)
4533                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4534         if (pause->tx_pause)
4535                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4536
4537         if (np->autoneg && pause->autoneg) {
4538                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4539
4540                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4541                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4542                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4543                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4544                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4545                         adv |=  ADVERTISE_PAUSE_ASYM;
4546                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4547
4548                 if (netif_running(dev))
4549                         printk(KERN_INFO "%s: link down.\n", dev->name);
4550                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4551                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4552                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4553         } else {
4554                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4555                 if (pause->rx_pause)
4556                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4557                 if (pause->tx_pause)
4558                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4559
4560                 if (!netif_running(dev))
4561                         nv_update_linkspeed(dev);
4562                 else
4563                         nv_update_pause(dev, np->pause_flags);
4564         }
4565
4566         if (netif_running(dev)) {
4567                 nv_start_rxtx(dev);
4568                 nv_enable_irq(dev);
4569         }
4570         return 0;
4571 }
4572
4573 static u32 nv_get_rx_csum(struct net_device *dev)
4574 {
4575         struct fe_priv *np = netdev_priv(dev);
4576         return (np->rx_csum) != 0;
4577 }
4578
4579 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4580 {
4581         struct fe_priv *np = netdev_priv(dev);
4582         u8 __iomem *base = get_hwbase(dev);
4583         int retcode = 0;
4584
4585         if (np->driver_data & DEV_HAS_CHECKSUM) {
4586                 if (data) {
4587                         np->rx_csum = 1;
4588                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4589                 } else {
4590                         np->rx_csum = 0;
4591                         /* vlan is dependent on rx checksum offload */
4592                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4593                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4594                 }
4595                 if (netif_running(dev)) {
4596                         spin_lock_irq(&np->lock);
4597                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4598                         spin_unlock_irq(&np->lock);
4599                 }
4600         } else {
4601                 return -EINVAL;
4602         }
4603
4604         return retcode;
4605 }
4606
4607 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4608 {
4609         struct fe_priv *np = netdev_priv(dev);
4610
4611         if (np->driver_data & DEV_HAS_CHECKSUM)
4612                 return ethtool_op_set_tx_hw_csum(dev, data);
4613         else
4614                 return -EOPNOTSUPP;
4615 }
4616
4617 static int nv_set_sg(struct net_device *dev, u32 data)
4618 {
4619         struct fe_priv *np = netdev_priv(dev);
4620
4621         if (np->driver_data & DEV_HAS_CHECKSUM)
4622                 return ethtool_op_set_sg(dev, data);
4623         else
4624                 return -EOPNOTSUPP;
4625 }
4626
4627 static int nv_get_sset_count(struct net_device *dev, int sset)
4628 {
4629         struct fe_priv *np = netdev_priv(dev);
4630
4631         switch (sset) {
4632         case ETH_SS_TEST:
4633                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4634                         return NV_TEST_COUNT_EXTENDED;
4635                 else
4636                         return NV_TEST_COUNT_BASE;
4637         case ETH_SS_STATS:
4638                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4639                         return NV_DEV_STATISTICS_V1_COUNT;
4640                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4641                         return NV_DEV_STATISTICS_V2_COUNT;
4642                 else
4643                         return 0;
4644         default:
4645                 return -EOPNOTSUPP;
4646         }
4647 }
4648
4649 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4650 {
4651         struct fe_priv *np = netdev_priv(dev);
4652
4653         /* update stats */
4654         nv_do_stats_poll((unsigned long)dev);
4655
4656         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4657 }
4658
4659 static int nv_link_test(struct net_device *dev)
4660 {
4661         struct fe_priv *np = netdev_priv(dev);
4662         int mii_status;
4663
4664         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4665         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4666
4667         /* check phy link status */
4668         if (!(mii_status & BMSR_LSTATUS))
4669                 return 0;
4670         else
4671                 return 1;
4672 }
4673
4674 static int nv_register_test(struct net_device *dev)
4675 {
4676         u8 __iomem *base = get_hwbase(dev);
4677         int i = 0;
4678         u32 orig_read, new_read;
4679
4680         do {
4681                 orig_read = readl(base + nv_registers_test[i].reg);
4682
4683                 /* xor with mask to toggle bits */
4684                 orig_read ^= nv_registers_test[i].mask;
4685
4686                 writel(orig_read, base + nv_registers_test[i].reg);
4687
4688                 new_read = readl(base + nv_registers_test[i].reg);
4689
4690                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4691                         return 0;
4692
4693                 /* restore original value */
4694                 orig_read ^= nv_registers_test[i].mask;
4695                 writel(orig_read, base + nv_registers_test[i].reg);
4696
4697         } while (nv_registers_test[++i].reg != 0);
4698
4699         return 1;
4700 }
4701
4702 static int nv_interrupt_test(struct net_device *dev)
4703 {
4704         struct fe_priv *np = netdev_priv(dev);
4705         u8 __iomem *base = get_hwbase(dev);
4706         int ret = 1;
4707         int testcnt;
4708         u32 save_msi_flags, save_poll_interval = 0;
4709
4710         if (netif_running(dev)) {
4711                 /* free current irq */
4712                 nv_free_irq(dev);
4713                 save_poll_interval = readl(base+NvRegPollingInterval);
4714         }
4715
4716         /* flag to test interrupt handler */
4717         np->intr_test = 0;
4718
4719         /* setup test irq */
4720         save_msi_flags = np->msi_flags;
4721         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4722         np->msi_flags |= 0x001; /* setup 1 vector */
4723         if (nv_request_irq(dev, 1))
4724                 return 0;
4725
4726         /* setup timer interrupt */
4727         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4728         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4729
4730         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4731
4732         /* wait for at least one interrupt */
4733         msleep(100);
4734
4735         spin_lock_irq(&np->lock);
4736
4737         /* flag should be set within ISR */
4738         testcnt = np->intr_test;
4739         if (!testcnt)
4740                 ret = 2;
4741
4742         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4743         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4744                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4745         else
4746                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4747
4748         spin_unlock_irq(&np->lock);
4749
4750         nv_free_irq(dev);
4751
4752         np->msi_flags = save_msi_flags;
4753
4754         if (netif_running(dev)) {
4755                 writel(save_poll_interval, base + NvRegPollingInterval);
4756                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4757                 /* restore original irq */
4758                 if (nv_request_irq(dev, 0))
4759                         return 0;
4760         }
4761
4762         return ret;
4763 }
4764
4765 static int nv_loopback_test(struct net_device *dev)
4766 {
4767         struct fe_priv *np = netdev_priv(dev);
4768         u8 __iomem *base = get_hwbase(dev);
4769         struct sk_buff *tx_skb, *rx_skb;
4770         dma_addr_t test_dma_addr;
4771         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4772         u32 flags;
4773         int len, i, pkt_len;
4774         u8 *pkt_data;
4775         u32 filter_flags = 0;
4776         u32 misc1_flags = 0;
4777         int ret = 1;
4778
4779         if (netif_running(dev)) {
4780                 nv_disable_irq(dev);
4781                 filter_flags = readl(base + NvRegPacketFilterFlags);
4782                 misc1_flags = readl(base + NvRegMisc1);
4783         } else {
4784                 nv_txrx_reset(dev);
4785         }
4786
4787         /* reinit driver view of the rx queue */
4788         set_bufsize(dev);
4789         nv_init_ring(dev);
4790
4791         /* setup hardware for loopback */
4792         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4793         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4794
4795         /* reinit nic view of the rx queue */
4796         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4797         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4798         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4799                 base + NvRegRingSizes);
4800         pci_push(base);
4801
4802         /* restart rx engine */
4803         nv_start_rxtx(dev);
4804
4805         /* setup packet for tx */
4806         pkt_len = ETH_DATA_LEN;
4807         tx_skb = dev_alloc_skb(pkt_len);
4808         if (!tx_skb) {
4809                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4810                          " of %s\n", dev->name);
4811                 ret = 0;
4812                 goto out;
4813         }
4814         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4815                                        skb_tailroom(tx_skb),
4816                                        PCI_DMA_FROMDEVICE);
4817         pkt_data = skb_put(tx_skb, pkt_len);
4818         for (i = 0; i < pkt_len; i++)
4819                 pkt_data[i] = (u8)(i & 0xff);
4820
4821         if (!nv_optimized(np)) {
4822                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4823                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4824         } else {
4825                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4826                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4827                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4828         }
4829         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4830         pci_push(get_hwbase(dev));
4831
4832         msleep(500);
4833
4834         /* check for rx of the packet */
4835         if (!nv_optimized(np)) {
4836                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4837                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4838
4839         } else {
4840                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4841                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4842         }
4843
4844         if (flags & NV_RX_AVAIL) {
4845                 ret = 0;
4846         } else if (np->desc_ver == DESC_VER_1) {
4847                 if (flags & NV_RX_ERROR)
4848                         ret = 0;
4849         } else {
4850                 if (flags & NV_RX2_ERROR) {
4851                         ret = 0;
4852                 }
4853         }
4854
4855         if (ret) {
4856                 if (len != pkt_len) {
4857                         ret = 0;
4858                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4859                                 dev->name, len, pkt_len);
4860                 } else {
4861                         rx_skb = np->rx_skb[0].skb;
4862                         for (i = 0; i < pkt_len; i++) {
4863                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4864                                         ret = 0;
4865                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4866                                                 dev->name, i);
4867                                         break;
4868                                 }
4869                         }
4870                 }
4871         } else {
4872                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4873         }
4874
4875         pci_unmap_page(np->pci_dev, test_dma_addr,
4876                        (skb_end_pointer(tx_skb) - tx_skb->data),
4877                        PCI_DMA_TODEVICE);
4878         dev_kfree_skb_any(tx_skb);
4879  out:
4880         /* stop engines */
4881         nv_stop_rxtx(dev);
4882         nv_txrx_reset(dev);
4883         /* drain rx queue */
4884         nv_drain_rxtx(dev);
4885
4886         if (netif_running(dev)) {
4887                 writel(misc1_flags, base + NvRegMisc1);
4888                 writel(filter_flags, base + NvRegPacketFilterFlags);
4889                 nv_enable_irq(dev);
4890         }
4891
4892         return ret;
4893 }
4894
4895 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4896 {
4897         struct fe_priv *np = netdev_priv(dev);
4898         u8 __iomem *base = get_hwbase(dev);
4899         int result;
4900         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4901
4902         if (!nv_link_test(dev)) {
4903                 test->flags |= ETH_TEST_FL_FAILED;
4904                 buffer[0] = 1;
4905         }
4906
4907         if (test->flags & ETH_TEST_FL_OFFLINE) {
4908                 if (netif_running(dev)) {
4909                         netif_stop_queue(dev);
4910 #ifdef CONFIG_FORCEDETH_NAPI
4911                         napi_disable(&np->napi);
4912 #endif
4913                         netif_tx_lock_bh(dev);
4914                         spin_lock_irq(&np->lock);
4915                         nv_disable_hw_interrupts(dev, np->irqmask);
4916                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4917                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4918                         } else {
4919                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4920                         }
4921                         /* stop engines */
4922                         nv_stop_rxtx(dev);
4923                         nv_txrx_reset(dev);
4924                         /* drain rx queue */
4925                         nv_drain_rxtx(dev);
4926                         spin_unlock_irq(&np->lock);
4927                         netif_tx_unlock_bh(dev);
4928                 }
4929
4930                 if (!nv_register_test(dev)) {
4931                         test->flags |= ETH_TEST_FL_FAILED;
4932                         buffer[1] = 1;
4933                 }
4934
4935                 result = nv_interrupt_test(dev);
4936                 if (result != 1) {
4937                         test->flags |= ETH_TEST_FL_FAILED;
4938                         buffer[2] = 1;
4939                 }
4940                 if (result == 0) {
4941                         /* bail out */
4942                         return;
4943                 }
4944
4945                 if (!nv_loopback_test(dev)) {
4946                         test->flags |= ETH_TEST_FL_FAILED;
4947                         buffer[3] = 1;
4948                 }
4949
4950                 if (netif_running(dev)) {
4951                         /* reinit driver view of the rx queue */
4952                         set_bufsize(dev);
4953                         if (nv_init_ring(dev)) {
4954                                 if (!np->in_shutdown)
4955                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4956                         }
4957                         /* reinit nic view of the rx queue */
4958                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4959                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4960                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4961                                 base + NvRegRingSizes);
4962                         pci_push(base);
4963                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4964                         pci_push(base);
4965                         /* restart rx engine */
4966                         nv_start_rxtx(dev);
4967                         netif_start_queue(dev);
4968 #ifdef CONFIG_FORCEDETH_NAPI
4969                         napi_enable(&np->napi);
4970 #endif
4971                         nv_enable_hw_interrupts(dev, np->irqmask);
4972                 }
4973         }
4974 }
4975
4976 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4977 {
4978         switch (stringset) {
4979         case ETH_SS_STATS:
4980                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4981                 break;
4982         case ETH_SS_TEST:
4983                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4984                 break;
4985         }
4986 }
4987
4988 static const struct ethtool_ops ops = {
4989         .get_drvinfo = nv_get_drvinfo,
4990         .get_link = ethtool_op_get_link,
4991         .get_wol = nv_get_wol,
4992         .set_wol = nv_set_wol,
4993         .get_settings = nv_get_settings,
4994         .set_settings = nv_set_settings,
4995         .get_regs_len = nv_get_regs_len,
4996         .get_regs = nv_get_regs,
4997         .nway_reset = nv_nway_reset,
4998         .set_tso = nv_set_tso,
4999         .get_ringparam = nv_get_ringparam,
5000         .set_ringparam = nv_set_ringparam,
5001         .get_pauseparam = nv_get_pauseparam,
5002         .set_pauseparam = nv_set_pauseparam,
5003         .get_rx_csum = nv_get_rx_csum,
5004         .set_rx_csum = nv_set_rx_csum,
5005         .set_tx_csum = nv_set_tx_csum,
5006         .set_sg = nv_set_sg,
5007         .get_strings = nv_get_strings,
5008         .get_ethtool_stats = nv_get_ethtool_stats,
5009         .get_sset_count = nv_get_sset_count,
5010         .self_test = nv_self_test,
5011 };
5012
5013 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5014 {
5015         struct fe_priv *np = get_nvpriv(dev);
5016
5017         spin_lock_irq(&np->lock);
5018
5019         /* save vlan group */
5020         np->vlangrp = grp;
5021
5022         if (grp) {
5023                 /* enable vlan on MAC */
5024                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5025         } else {
5026                 /* disable vlan on MAC */
5027                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5028                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5029         }
5030
5031         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5032
5033         spin_unlock_irq(&np->lock);
5034 }
5035
5036 /* The mgmt unit and driver use a semaphore to access the phy during init */
5037 static int nv_mgmt_acquire_sema(struct net_device *dev)
5038 {
5039         u8 __iomem *base = get_hwbase(dev);
5040         int i;
5041         u32 tx_ctrl, mgmt_sema;
5042
5043         for (i = 0; i < 10; i++) {
5044                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5045                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5046                         break;
5047                 msleep(500);
5048         }
5049
5050         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5051                 return 0;
5052
5053         for (i = 0; i < 2; i++) {
5054                 tx_ctrl = readl(base + NvRegTransmitterControl);
5055                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5056                 writel(tx_ctrl, base + NvRegTransmitterControl);
5057
5058                 /* verify that semaphore was acquired */
5059                 tx_ctrl = readl(base + NvRegTransmitterControl);
5060                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5061                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5062                         return 1;
5063                 else
5064                         udelay(50);
5065         }
5066
5067         return 0;
5068 }
5069
5070 static int nv_open(struct net_device *dev)
5071 {
5072         struct fe_priv *np = netdev_priv(dev);
5073         u8 __iomem *base = get_hwbase(dev);
5074         int ret = 1;
5075         int oom, i;
5076         u32 low;
5077
5078         dprintk(KERN_DEBUG "nv_open: begin\n");
5079
5080         /* erase previous misconfiguration */
5081         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5082                 nv_mac_reset(dev);
5083         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5084         writel(0, base + NvRegMulticastAddrB);
5085         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5086         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5087         writel(0, base + NvRegPacketFilterFlags);
5088
5089         writel(0, base + NvRegTransmitterControl);
5090         writel(0, base + NvRegReceiverControl);
5091
5092         writel(0, base + NvRegAdapterControl);
5093
5094         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5095                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5096
5097         /* initialize descriptor rings */
5098         set_bufsize(dev);
5099         oom = nv_init_ring(dev);
5100
5101         writel(0, base + NvRegLinkSpeed);
5102         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5103         nv_txrx_reset(dev);
5104         writel(0, base + NvRegUnknownSetupReg6);
5105
5106         np->in_shutdown = 0;
5107
5108         /* give hw rings */
5109         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5110         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5111                 base + NvRegRingSizes);
5112
5113         writel(np->linkspeed, base + NvRegLinkSpeed);
5114         if (np->desc_ver == DESC_VER_1)
5115                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5116         else
5117                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5118         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5119         writel(np->vlanctl_bits, base + NvRegVlanControl);
5120         pci_push(base);
5121         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5122         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5123                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5124                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5125
5126         writel(0, base + NvRegMIIMask);
5127         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5128         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5129
5130         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5131         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5132         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5133         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5134
5135         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5136
5137         get_random_bytes(&low, sizeof(low));
5138         low &= NVREG_SLOTTIME_MASK;
5139         if (np->desc_ver == DESC_VER_1) {
5140                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5141         } else {
5142                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5143                         /* setup legacy backoff */
5144                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5145                 } else {
5146                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5147                         nv_gear_backoff_reseed(dev);
5148                 }
5149         }
5150         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5151         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5152         if (poll_interval == -1) {
5153                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5154                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5155                 else
5156                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5157         }
5158         else
5159                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5160         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5161         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5162                         base + NvRegAdapterControl);
5163         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5164         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5165         if (np->wolenabled)
5166                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5167
5168         i = readl(base + NvRegPowerState);
5169         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5170                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5171
5172         pci_push(base);
5173         udelay(10);
5174         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5175
5176         nv_disable_hw_interrupts(dev, np->irqmask);
5177         pci_push(base);
5178         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5179         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5180         pci_push(base);
5181
5182         if (nv_request_irq(dev, 0)) {
5183                 goto out_drain;
5184         }
5185
5186         /* ask for interrupts */
5187         nv_enable_hw_interrupts(dev, np->irqmask);
5188
5189         spin_lock_irq(&np->lock);
5190         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5191         writel(0, base + NvRegMulticastAddrB);
5192         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5193         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5194         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5195         /* One manual link speed update: Interrupts are enabled, future link
5196          * speed changes cause interrupts and are handled by nv_link_irq().
5197          */
5198         {
5199                 u32 miistat;
5200                 miistat = readl(base + NvRegMIIStatus);
5201                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5202                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5203         }
5204         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5205          * to init hw */
5206         np->linkspeed = 0;
5207         ret = nv_update_linkspeed(dev);
5208         nv_start_rxtx(dev);
5209         netif_start_queue(dev);
5210 #ifdef CONFIG_FORCEDETH_NAPI
5211         napi_enable(&np->napi);
5212 #endif
5213
5214         if (ret) {
5215                 netif_carrier_on(dev);
5216         } else {
5217                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5218                 netif_carrier_off(dev);
5219         }
5220         if (oom)
5221                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5222
5223         /* start statistics timer */
5224         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
5225                 mod_timer(&np->stats_poll,
5226                         round_jiffies(jiffies + STATS_INTERVAL));
5227
5228         spin_unlock_irq(&np->lock);
5229
5230         return 0;
5231 out_drain:
5232         nv_drain_rxtx(dev);
5233         return ret;
5234 }
5235
5236 static int nv_close(struct net_device *dev)
5237 {
5238         struct fe_priv *np = netdev_priv(dev);
5239         u8 __iomem *base;
5240
5241         spin_lock_irq(&np->lock);
5242         np->in_shutdown = 1;
5243         spin_unlock_irq(&np->lock);
5244 #ifdef CONFIG_FORCEDETH_NAPI
5245         napi_disable(&np->napi);
5246 #endif
5247         synchronize_irq(np->pci_dev->irq);
5248
5249         del_timer_sync(&np->oom_kick);
5250         del_timer_sync(&np->nic_poll);
5251         del_timer_sync(&np->stats_poll);
5252
5253         netif_stop_queue(dev);
5254         spin_lock_irq(&np->lock);
5255         nv_stop_rxtx(dev);
5256         nv_txrx_reset(dev);
5257
5258         /* disable interrupts on the nic or we will lock up */
5259         base = get_hwbase(dev);
5260         nv_disable_hw_interrupts(dev, np->irqmask);
5261         pci_push(base);
5262         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5263
5264         spin_unlock_irq(&np->lock);
5265
5266         nv_free_irq(dev);
5267
5268         nv_drain_rxtx(dev);
5269
5270         if (np->wolenabled) {
5271                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5272                 nv_start_rx(dev);
5273         }
5274
5275         /* FIXME: power down nic */
5276
5277         return 0;
5278 }
5279
5280 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5281 {
5282         struct net_device *dev;
5283         struct fe_priv *np;
5284         unsigned long addr;
5285         u8 __iomem *base;
5286         int err, i;
5287         u32 powerstate, txreg;
5288         u32 phystate_orig = 0, phystate;
5289         int phyinitialized = 0;
5290         DECLARE_MAC_BUF(mac);
5291         static int printed_version;
5292
5293         if (!printed_version++)
5294                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5295                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5296
5297         dev = alloc_etherdev(sizeof(struct fe_priv));
5298         err = -ENOMEM;
5299         if (!dev)
5300                 goto out;
5301
5302         np = netdev_priv(dev);
5303         np->dev = dev;
5304         np->pci_dev = pci_dev;
5305         spin_lock_init(&np->lock);
5306         SET_NETDEV_DEV(dev, &pci_dev->dev);
5307
5308         init_timer(&np->oom_kick);
5309         np->oom_kick.data = (unsigned long) dev;
5310         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5311         init_timer(&np->nic_poll);
5312         np->nic_poll.data = (unsigned long) dev;
5313         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5314         init_timer(&np->stats_poll);
5315         np->stats_poll.data = (unsigned long) dev;
5316         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5317
5318         err = pci_enable_device(pci_dev);
5319         if (err)
5320                 goto out_free;
5321
5322         pci_set_master(pci_dev);
5323
5324         err = pci_request_regions(pci_dev, DRV_NAME);
5325         if (err < 0)
5326                 goto out_disable;
5327
5328         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5329                 np->register_size = NV_PCI_REGSZ_VER3;
5330         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5331                 np->register_size = NV_PCI_REGSZ_VER2;
5332         else
5333                 np->register_size = NV_PCI_REGSZ_VER1;
5334
5335         err = -EINVAL;
5336         addr = 0;
5337         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5338                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5339                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5340                                 pci_resource_len(pci_dev, i),
5341                                 pci_resource_flags(pci_dev, i));
5342                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5343                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5344                         addr = pci_resource_start(pci_dev, i);
5345                         break;
5346                 }
5347         }
5348         if (i == DEVICE_COUNT_RESOURCE) {
5349                 dev_printk(KERN_INFO, &pci_dev->dev,
5350                            "Couldn't find register window\n");
5351                 goto out_relreg;
5352         }
5353
5354         /* copy of driver data */
5355         np->driver_data = id->driver_data;
5356         /* copy of device id */
5357         np->device_id = id->device;
5358
5359         /* handle different descriptor versions */
5360         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5361                 /* packet format 3: supports 40-bit addressing */
5362                 np->desc_ver = DESC_VER_3;
5363                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5364                 if (dma_64bit) {
5365                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5366                                 dev_printk(KERN_INFO, &pci_dev->dev,
5367                                         "64-bit DMA failed, using 32-bit addressing\n");
5368                         else
5369                                 dev->features |= NETIF_F_HIGHDMA;
5370                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5371                                 dev_printk(KERN_INFO, &pci_dev->dev,
5372                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5373                         }
5374                 }
5375         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5376                 /* packet format 2: supports jumbo frames */
5377                 np->desc_ver = DESC_VER_2;
5378                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5379         } else {
5380                 /* original packet format */
5381                 np->desc_ver = DESC_VER_1;
5382                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5383         }
5384
5385         np->pkt_limit = NV_PKTLIMIT_1;
5386         if (id->driver_data & DEV_HAS_LARGEDESC)
5387                 np->pkt_limit = NV_PKTLIMIT_2;
5388
5389         if (id->driver_data & DEV_HAS_CHECKSUM) {
5390                 np->rx_csum = 1;
5391                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5392                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5393                 dev->features |= NETIF_F_TSO;
5394         }
5395
5396         np->vlanctl_bits = 0;
5397         if (id->driver_data & DEV_HAS_VLAN) {
5398                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5399                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5400                 dev->vlan_rx_register = nv_vlan_rx_register;
5401         }
5402
5403         np->msi_flags = 0;
5404         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5405                 np->msi_flags |= NV_MSI_CAPABLE;
5406         }
5407         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5408                 np->msi_flags |= NV_MSI_X_CAPABLE;
5409         }
5410
5411         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5412         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5413             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5414             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5415                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5416         }
5417
5418
5419         err = -ENOMEM;
5420         np->base = ioremap(addr, np->register_size);
5421         if (!np->base)
5422                 goto out_relreg;
5423         dev->base_addr = (unsigned long)np->base;
5424
5425         dev->irq = pci_dev->irq;
5426
5427         np->rx_ring_size = RX_RING_DEFAULT;
5428         np->tx_ring_size = TX_RING_DEFAULT;
5429
5430         if (!nv_optimized(np)) {
5431                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5432                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5433                                         &np->ring_addr);
5434                 if (!np->rx_ring.orig)
5435                         goto out_unmap;
5436                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5437         } else {
5438                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5439                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5440                                         &np->ring_addr);
5441                 if (!np->rx_ring.ex)
5442                         goto out_unmap;
5443                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5444         }
5445         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5446         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5447         if (!np->rx_skb || !np->tx_skb)
5448                 goto out_freering;
5449
5450         dev->open = nv_open;
5451         dev->stop = nv_close;
5452
5453         if (!nv_optimized(np))
5454                 dev->hard_start_xmit = nv_start_xmit;
5455         else
5456                 dev->hard_start_xmit = nv_start_xmit_optimized;
5457         dev->get_stats = nv_get_stats;
5458         dev->change_mtu = nv_change_mtu;
5459         dev->set_mac_address = nv_set_mac_address;
5460         dev->set_multicast_list = nv_set_multicast;
5461 #ifdef CONFIG_NET_POLL_CONTROLLER
5462         dev->poll_controller = nv_poll_controller;
5463 #endif
5464 #ifdef CONFIG_FORCEDETH_NAPI
5465         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5466 #endif
5467         SET_ETHTOOL_OPS(dev, &ops);
5468         dev->tx_timeout = nv_tx_timeout;
5469         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5470
5471         pci_set_drvdata(pci_dev, dev);
5472
5473         /* read the mac address */
5474         base = get_hwbase(dev);
5475         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5476         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5477
5478         /* check the workaround bit for correct mac address order */
5479         txreg = readl(base + NvRegTransmitPoll);
5480         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5481                 /* mac address is already in correct order */
5482                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5483                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5484                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5485                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5486                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5487                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5488         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5489                 /* mac address is already in correct order */
5490                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5491                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5492                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5493                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5494                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5495                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5496                 /*
5497                  * Set orig mac address back to the reversed version.
5498                  * This flag will be cleared during low power transition.
5499                  * Therefore, we should always put back the reversed address.
5500                  */
5501                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5502                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5503                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5504         } else {
5505                 /* need to reverse mac address to correct order */
5506                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5507                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5508                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5509               &nbs