forcedeth: add clock gating feature <resend>
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.64"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk                 printk
69 #else
70 #define dprintk(x...)           do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP  64
74 #define RX_WORK_PER_LOOP  64
75
76 /*
77  * Hardware access:
78  */
79
80 #define DEV_NEED_TIMERIRQ          0x000001  /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER         0x000002  /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC          0x000004  /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA           0x000008  /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM           0x000010  /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN               0x000020  /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI                0x000040  /* device supports MSI */
87 #define DEV_HAS_MSI_X              0x000080  /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL        0x000100  /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1      0x000200  /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2      0x000600  /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3      0x000e00  /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED      0x001000  /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT          0x002000  /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR    0x004000  /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX      0x008000  /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x010000  /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x020000  /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x040000  /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT          0x080000  /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE          0x100000  /* device supports gear mode */
101
102 enum {
103         NvRegIrqStatus = 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT  0x040
105 #define NVREG_IRQSTAT_MASK              0x83ff
106         NvRegIrqMask = 0x004,
107 #define NVREG_IRQ_RX_ERROR              0x0001
108 #define NVREG_IRQ_RX                    0x0002
109 #define NVREG_IRQ_RX_NOBUF              0x0004
110 #define NVREG_IRQ_TX_ERR                0x0008
111 #define NVREG_IRQ_TX_OK                 0x0010
112 #define NVREG_IRQ_TIMER                 0x0020
113 #define NVREG_IRQ_LINK                  0x0040
114 #define NVREG_IRQ_RX_FORCED             0x0080
115 #define NVREG_IRQ_TX_FORCED             0x0100
116 #define NVREG_IRQ_RECOVER_ERROR         0x8200
117 #define NVREG_IRQMASK_THROUGHPUT        0x00df
118 #define NVREG_IRQMASK_CPU               0x0060
119 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122
123         NvRegUnknownSetupReg6 = 0x008,
124 #define NVREG_UNKSETUP6_VAL             3
125
126 /*
127  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
128  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
129  */
130         NvRegPollingInterval = 0x00c,
131 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
132 #define NVREG_POLL_DEFAULT_CPU  13
133         NvRegMSIMap0 = 0x020,
134         NvRegMSIMap1 = 0x024,
135         NvRegMSIIrqMask = 0x030,
136 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
137         NvRegMisc1 = 0x080,
138 #define NVREG_MISC1_PAUSE_TX    0x01
139 #define NVREG_MISC1_HD          0x02
140 #define NVREG_MISC1_FORCE       0x3b0f3c
141
142         NvRegMacReset = 0x34,
143 #define NVREG_MAC_RESET_ASSERT  0x0F3
144         NvRegTransmitterControl = 0x084,
145 #define NVREG_XMITCTL_START     0x01
146 #define NVREG_XMITCTL_MGMT_ST   0x40000000
147 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
148 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
149 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
150 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
151 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
152 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
153 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
154 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
155 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
156 #define NVREG_XMITCTL_DATA_START        0x00100000
157 #define NVREG_XMITCTL_DATA_READY        0x00010000
158 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
159         NvRegTransmitterStatus = 0x088,
160 #define NVREG_XMITSTAT_BUSY     0x01
161
162         NvRegPacketFilterFlags = 0x8c,
163 #define NVREG_PFF_PAUSE_RX      0x08
164 #define NVREG_PFF_ALWAYS        0x7F0000
165 #define NVREG_PFF_PROMISC       0x80
166 #define NVREG_PFF_MYADDR        0x20
167 #define NVREG_PFF_LOOPBACK      0x10
168
169         NvRegOffloadConfig = 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY   0x601
171 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
172         NvRegReceiverControl = 0x094,
173 #define NVREG_RCVCTL_START      0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175         NvRegReceiverStatus = 0x98,
176 #define NVREG_RCVSTAT_BUSY      0x01
177
178         NvRegSlotTime = 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
182 #define NVREG_SLOTTIME_HALF             0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
184 #define NVREG_SLOTTIME_MASK             0x000000ff
185
186         NvRegTxDeferral = 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
193         NvRegRxDeferral = 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
195         NvRegMacAddrA = 0xA8,
196         NvRegMacAddrB = 0xAC,
197         NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE  0x01
199         NvRegMulticastAddrB = 0xB4,
200         NvRegMulticastMaskA = 0xB8,
201 #define NVREG_MCASTMASKA_NONE           0xffffffff
202         NvRegMulticastMaskB = 0xBC,
203 #define NVREG_MCASTMASKB_NONE           0xffff
204
205         NvRegPhyInterface = 0xC0,
206 #define PHY_RGMII               0x10000000
207         NvRegBackOffControl = 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT                  24
211 #define NVREG_BKOFFCTRL_GEAR                    12
212
213         NvRegTxRingPhysAddr = 0x100,
214         NvRegRxRingPhysAddr = 0x104,
215         NvRegRingSizes = 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218         NvRegTransmitPoll = 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220         NvRegLinkSpeed = 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10      1000
223 #define NVREG_LINKSPEED_100     100
224 #define NVREG_LINKSPEED_1000    50
225 #define NVREG_LINKSPEED_MASK    (0xFFF)
226         NvRegUnknownSetupReg5 = 0x130,
227 #define NVREG_UNKSETUP5_BIT31   (1<<31)
228         NvRegTxWatermark = 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
232         NvRegTxRxControl = 0x144,
233 #define NVREG_TXRXCTL_KICK      0x0001
234 #define NVREG_TXRXCTL_BIT1      0x0002
235 #define NVREG_TXRXCTL_BIT2      0x0004
236 #define NVREG_TXRXCTL_IDLE      0x0008
237 #define NVREG_TXRXCTL_RESET     0x0010
238 #define NVREG_TXRXCTL_RXCHECK   0x0400
239 #define NVREG_TXRXCTL_DESC_1    0
240 #define NVREG_TXRXCTL_DESC_2    0x002100
241 #define NVREG_TXRXCTL_DESC_3    0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS   0x00080
244         NvRegTxRingPhysAddrHigh = 0x148,
245         NvRegRxRingPhysAddrHigh = 0x14C,
246         NvRegTxPauseFrame = 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
251         NvRegTxPauseFrameLimit = 0x174,
252 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
253         NvRegMIIStatus = 0x180,
254 #define NVREG_MIISTAT_ERROR             0x0001
255 #define NVREG_MIISTAT_LINKCHANGE        0x0008
256 #define NVREG_MIISTAT_MASK_RW           0x0007
257 #define NVREG_MIISTAT_MASK_ALL          0x000f
258         NvRegMIIMask = 0x184,
259 #define NVREG_MII_LINKCHANGE            0x0008
260
261         NvRegAdapterControl = 0x188,
262 #define NVREG_ADAPTCTL_START    0x02
263 #define NVREG_ADAPTCTL_LINKUP   0x04
264 #define NVREG_ADAPTCTL_PHYVALID 0x40000
265 #define NVREG_ADAPTCTL_RUNNING  0x100000
266 #define NVREG_ADAPTCTL_PHYSHIFT 24
267         NvRegMIISpeed = 0x18c,
268 #define NVREG_MIISPEED_BIT8     (1<<8)
269 #define NVREG_MIIDELAY  5
270         NvRegMIIControl = 0x190,
271 #define NVREG_MIICTL_INUSE      0x08000
272 #define NVREG_MIICTL_WRITE      0x00400
273 #define NVREG_MIICTL_ADDRSHIFT  5
274         NvRegMIIData = 0x194,
275         NvRegTxUnicast = 0x1a0,
276         NvRegTxMulticast = 0x1a4,
277         NvRegTxBroadcast = 0x1a8,
278         NvRegWakeUpFlags = 0x200,
279 #define NVREG_WAKEUPFLAGS_VAL           0x7770
280 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
281 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
282 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
283 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
284 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
285 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
286 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
287 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
288 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
289 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
290
291         NvRegMgmtUnitGetVersion = 0x204,
292 #define NVREG_MGMTUNITGETVERSION        0x01
293         NvRegMgmtUnitVersion = 0x208,
294 #define NVREG_MGMTUNITVERSION           0x08
295         NvRegPowerCap = 0x268,
296 #define NVREG_POWERCAP_D3SUPP   (1<<30)
297 #define NVREG_POWERCAP_D2SUPP   (1<<26)
298 #define NVREG_POWERCAP_D1SUPP   (1<<25)
299         NvRegPowerState = 0x26c,
300 #define NVREG_POWERSTATE_POWEREDUP      0x8000
301 #define NVREG_POWERSTATE_VALID          0x0100
302 #define NVREG_POWERSTATE_MASK           0x0003
303 #define NVREG_POWERSTATE_D0             0x0000
304 #define NVREG_POWERSTATE_D1             0x0001
305 #define NVREG_POWERSTATE_D2             0x0002
306 #define NVREG_POWERSTATE_D3             0x0003
307         NvRegMgmtUnitControl = 0x278,
308 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
309         NvRegTxCnt = 0x280,
310         NvRegTxZeroReXmt = 0x284,
311         NvRegTxOneReXmt = 0x288,
312         NvRegTxManyReXmt = 0x28c,
313         NvRegTxLateCol = 0x290,
314         NvRegTxUnderflow = 0x294,
315         NvRegTxLossCarrier = 0x298,
316         NvRegTxExcessDef = 0x29c,
317         NvRegTxRetryErr = 0x2a0,
318         NvRegRxFrameErr = 0x2a4,
319         NvRegRxExtraByte = 0x2a8,
320         NvRegRxLateCol = 0x2ac,
321         NvRegRxRunt = 0x2b0,
322         NvRegRxFrameTooLong = 0x2b4,
323         NvRegRxOverflow = 0x2b8,
324         NvRegRxFCSErr = 0x2bc,
325         NvRegRxFrameAlignErr = 0x2c0,
326         NvRegRxLenErr = 0x2c4,
327         NvRegRxUnicast = 0x2c8,
328         NvRegRxMulticast = 0x2cc,
329         NvRegRxBroadcast = 0x2d0,
330         NvRegTxDef = 0x2d4,
331         NvRegTxFrame = 0x2d8,
332         NvRegRxCnt = 0x2dc,
333         NvRegTxPause = 0x2e0,
334         NvRegRxPause = 0x2e4,
335         NvRegRxDropFrame = 0x2e8,
336         NvRegVlanControl = 0x300,
337 #define NVREG_VLANCONTROL_ENABLE        0x2000
338         NvRegMSIXMap0 = 0x3e0,
339         NvRegMSIXMap1 = 0x3e4,
340         NvRegMSIXIrqStatus = 0x3f0,
341
342         NvRegPowerState2 = 0x600,
343 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
344 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
345 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
346 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
347 };
348
349 /* Big endian: should work, but is untested */
350 struct ring_desc {
351         __le32 buf;
352         __le32 flaglen;
353 };
354
355 struct ring_desc_ex {
356         __le32 bufhigh;
357         __le32 buflow;
358         __le32 txvlan;
359         __le32 flaglen;
360 };
361
362 union ring_type {
363         struct ring_desc* orig;
364         struct ring_desc_ex* ex;
365 };
366
367 #define FLAG_MASK_V1 0xffff0000
368 #define FLAG_MASK_V2 0xffffc000
369 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
370 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
371
372 #define NV_TX_LASTPACKET        (1<<16)
373 #define NV_TX_RETRYERROR        (1<<19)
374 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
375 #define NV_TX_FORCED_INTERRUPT  (1<<24)
376 #define NV_TX_DEFERRED          (1<<26)
377 #define NV_TX_CARRIERLOST       (1<<27)
378 #define NV_TX_LATECOLLISION     (1<<28)
379 #define NV_TX_UNDERFLOW         (1<<29)
380 #define NV_TX_ERROR             (1<<30)
381 #define NV_TX_VALID             (1<<31)
382
383 #define NV_TX2_LASTPACKET       (1<<29)
384 #define NV_TX2_RETRYERROR       (1<<18)
385 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
386 #define NV_TX2_FORCED_INTERRUPT (1<<30)
387 #define NV_TX2_DEFERRED         (1<<25)
388 #define NV_TX2_CARRIERLOST      (1<<26)
389 #define NV_TX2_LATECOLLISION    (1<<27)
390 #define NV_TX2_UNDERFLOW        (1<<28)
391 /* error and valid are the same for both */
392 #define NV_TX2_ERROR            (1<<30)
393 #define NV_TX2_VALID            (1<<31)
394 #define NV_TX2_TSO              (1<<28)
395 #define NV_TX2_TSO_SHIFT        14
396 #define NV_TX2_TSO_MAX_SHIFT    14
397 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
398 #define NV_TX2_CHECKSUM_L3      (1<<27)
399 #define NV_TX2_CHECKSUM_L4      (1<<26)
400
401 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
402
403 #define NV_RX_DESCRIPTORVALID   (1<<16)
404 #define NV_RX_MISSEDFRAME       (1<<17)
405 #define NV_RX_SUBSTRACT1        (1<<18)
406 #define NV_RX_ERROR1            (1<<23)
407 #define NV_RX_ERROR2            (1<<24)
408 #define NV_RX_ERROR3            (1<<25)
409 #define NV_RX_ERROR4            (1<<26)
410 #define NV_RX_CRCERR            (1<<27)
411 #define NV_RX_OVERFLOW          (1<<28)
412 #define NV_RX_FRAMINGERR        (1<<29)
413 #define NV_RX_ERROR             (1<<30)
414 #define NV_RX_AVAIL             (1<<31)
415 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
416
417 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
418 #define NV_RX2_CHECKSUM_IP      (0x10000000)
419 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
420 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
421 #define NV_RX2_DESCRIPTORVALID  (1<<29)
422 #define NV_RX2_SUBSTRACT1       (1<<25)
423 #define NV_RX2_ERROR1           (1<<18)
424 #define NV_RX2_ERROR2           (1<<19)
425 #define NV_RX2_ERROR3           (1<<20)
426 #define NV_RX2_ERROR4           (1<<21)
427 #define NV_RX2_CRCERR           (1<<22)
428 #define NV_RX2_OVERFLOW         (1<<23)
429 #define NV_RX2_FRAMINGERR       (1<<24)
430 /* error and avail are the same for both */
431 #define NV_RX2_ERROR            (1<<30)
432 #define NV_RX2_AVAIL            (1<<31)
433 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
434
435 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
436 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
437
438 /* Miscelaneous hardware related defines: */
439 #define NV_PCI_REGSZ_VER1       0x270
440 #define NV_PCI_REGSZ_VER2       0x2d4
441 #define NV_PCI_REGSZ_VER3       0x604
442 #define NV_PCI_REGSZ_MAX        0x604
443
444 /* various timeout delays: all in usec */
445 #define NV_TXRX_RESET_DELAY     4
446 #define NV_TXSTOP_DELAY1        10
447 #define NV_TXSTOP_DELAY1MAX     500000
448 #define NV_TXSTOP_DELAY2        100
449 #define NV_RXSTOP_DELAY1        10
450 #define NV_RXSTOP_DELAY1MAX     500000
451 #define NV_RXSTOP_DELAY2        100
452 #define NV_SETUP5_DELAY         5
453 #define NV_SETUP5_DELAYMAX      50000
454 #define NV_POWERUP_DELAY        5
455 #define NV_POWERUP_DELAYMAX     5000
456 #define NV_MIIBUSY_DELAY        50
457 #define NV_MIIPHY_DELAY 10
458 #define NV_MIIPHY_DELAYMAX      10000
459 #define NV_MAC_RESET_DELAY      64
460
461 #define NV_WAKEUPPATTERNS       5
462 #define NV_WAKEUPMASKENTRIES    4
463
464 /* General driver defaults */
465 #define NV_WATCHDOG_TIMEO       (5*HZ)
466
467 #define RX_RING_DEFAULT         512
468 #define TX_RING_DEFAULT         256
469 #define RX_RING_MIN             128
470 #define TX_RING_MIN             64
471 #define RING_MAX_DESC_VER_1     1024
472 #define RING_MAX_DESC_VER_2_3   16384
473
474 /* rx/tx mac addr + type + vlan + align + slack*/
475 #define NV_RX_HEADERS           (64)
476 /* even more slack. */
477 #define NV_RX_ALLOC_PAD         (64)
478
479 /* maximum mtu size */
480 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
481 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
482
483 #define OOM_REFILL      (1+HZ/20)
484 #define POLL_WAIT       (1+HZ/100)
485 #define LINK_TIMEOUT    (3*HZ)
486 #define STATS_INTERVAL  (10*HZ)
487
488 /*
489  * desc_ver values:
490  * The nic supports three different descriptor types:
491  * - DESC_VER_1: Original
492  * - DESC_VER_2: support for jumbo frames.
493  * - DESC_VER_3: 64-bit format.
494  */
495 #define DESC_VER_1      1
496 #define DESC_VER_2      2
497 #define DESC_VER_3      3
498
499 /* PHY defines */
500 #define PHY_OUI_MARVELL         0x5043
501 #define PHY_OUI_CICADA          0x03f1
502 #define PHY_OUI_VITESSE         0x01c1
503 #define PHY_OUI_REALTEK         0x0732
504 #define PHY_OUI_REALTEK2        0x0020
505 #define PHYID1_OUI_MASK 0x03ff
506 #define PHYID1_OUI_SHFT 6
507 #define PHYID2_OUI_MASK 0xfc00
508 #define PHYID2_OUI_SHFT 10
509 #define PHYID2_MODEL_MASK               0x03f0
510 #define PHY_MODEL_REALTEK_8211          0x0110
511 #define PHY_REV_MASK                    0x0001
512 #define PHY_REV_REALTEK_8211B           0x0000
513 #define PHY_REV_REALTEK_8211C           0x0001
514 #define PHY_MODEL_REALTEK_8201          0x0200
515 #define PHY_MODEL_MARVELL_E3016         0x0220
516 #define PHY_MARVELL_E3016_INITMASK      0x0300
517 #define PHY_CICADA_INIT1        0x0f000
518 #define PHY_CICADA_INIT2        0x0e00
519 #define PHY_CICADA_INIT3        0x01000
520 #define PHY_CICADA_INIT4        0x0200
521 #define PHY_CICADA_INIT5        0x0004
522 #define PHY_CICADA_INIT6        0x02000
523 #define PHY_VITESSE_INIT_REG1   0x1f
524 #define PHY_VITESSE_INIT_REG2   0x10
525 #define PHY_VITESSE_INIT_REG3   0x11
526 #define PHY_VITESSE_INIT_REG4   0x12
527 #define PHY_VITESSE_INIT_MSK1   0xc
528 #define PHY_VITESSE_INIT_MSK2   0x0180
529 #define PHY_VITESSE_INIT1       0x52b5
530 #define PHY_VITESSE_INIT2       0xaf8a
531 #define PHY_VITESSE_INIT3       0x8
532 #define PHY_VITESSE_INIT4       0x8f8a
533 #define PHY_VITESSE_INIT5       0xaf86
534 #define PHY_VITESSE_INIT6       0x8f86
535 #define PHY_VITESSE_INIT7       0xaf82
536 #define PHY_VITESSE_INIT8       0x0100
537 #define PHY_VITESSE_INIT9       0x8f82
538 #define PHY_VITESSE_INIT10      0x0
539 #define PHY_REALTEK_INIT_REG1   0x1f
540 #define PHY_REALTEK_INIT_REG2   0x19
541 #define PHY_REALTEK_INIT_REG3   0x13
542 #define PHY_REALTEK_INIT_REG4   0x14
543 #define PHY_REALTEK_INIT_REG5   0x18
544 #define PHY_REALTEK_INIT_REG6   0x11
545 #define PHY_REALTEK_INIT_REG7   0x01
546 #define PHY_REALTEK_INIT1       0x0000
547 #define PHY_REALTEK_INIT2       0x8e00
548 #define PHY_REALTEK_INIT3       0x0001
549 #define PHY_REALTEK_INIT4       0xad17
550 #define PHY_REALTEK_INIT5       0xfb54
551 #define PHY_REALTEK_INIT6       0xf5c7
552 #define PHY_REALTEK_INIT7       0x1000
553 #define PHY_REALTEK_INIT8       0x0003
554 #define PHY_REALTEK_INIT9       0x0008
555 #define PHY_REALTEK_INIT10      0x0005
556 #define PHY_REALTEK_INIT11      0x0200
557 #define PHY_REALTEK_INIT_MSK1   0x0003
558
559 #define PHY_GIGABIT     0x0100
560
561 #define PHY_TIMEOUT     0x1
562 #define PHY_ERROR       0x2
563
564 #define PHY_100 0x1
565 #define PHY_1000        0x2
566 #define PHY_HALF        0x100
567
568 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
569 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
570 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
571 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
572 #define NV_PAUSEFRAME_RX_REQ     0x0010
573 #define NV_PAUSEFRAME_TX_REQ     0x0020
574 #define NV_PAUSEFRAME_AUTONEG    0x0040
575
576 /* MSI/MSI-X defines */
577 #define NV_MSI_X_MAX_VECTORS  8
578 #define NV_MSI_X_VECTORS_MASK 0x000f
579 #define NV_MSI_CAPABLE        0x0010
580 #define NV_MSI_X_CAPABLE      0x0020
581 #define NV_MSI_ENABLED        0x0040
582 #define NV_MSI_X_ENABLED      0x0080
583
584 #define NV_MSI_X_VECTOR_ALL   0x0
585 #define NV_MSI_X_VECTOR_RX    0x0
586 #define NV_MSI_X_VECTOR_TX    0x1
587 #define NV_MSI_X_VECTOR_OTHER 0x2
588
589 #define NV_MSI_PRIV_OFFSET 0x68
590 #define NV_MSI_PRIV_VALUE  0xffffffff
591
592 #define NV_RESTART_TX         0x1
593 #define NV_RESTART_RX         0x2
594
595 #define NV_TX_LIMIT_COUNT     16
596
597 #define NV_DYNAMIC_THRESHOLD        4
598 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
599
600 /* statistics */
601 struct nv_ethtool_str {
602         char name[ETH_GSTRING_LEN];
603 };
604
605 static const struct nv_ethtool_str nv_estats_str[] = {
606         { "tx_bytes" },
607         { "tx_zero_rexmt" },
608         { "tx_one_rexmt" },
609         { "tx_many_rexmt" },
610         { "tx_late_collision" },
611         { "tx_fifo_errors" },
612         { "tx_carrier_errors" },
613         { "tx_excess_deferral" },
614         { "tx_retry_error" },
615         { "rx_frame_error" },
616         { "rx_extra_byte" },
617         { "rx_late_collision" },
618         { "rx_runt" },
619         { "rx_frame_too_long" },
620         { "rx_over_errors" },
621         { "rx_crc_errors" },
622         { "rx_frame_align_error" },
623         { "rx_length_error" },
624         { "rx_unicast" },
625         { "rx_multicast" },
626         { "rx_broadcast" },
627         { "rx_packets" },
628         { "rx_errors_total" },
629         { "tx_errors_total" },
630
631         /* version 2 stats */
632         { "tx_deferral" },
633         { "tx_packets" },
634         { "rx_bytes" },
635         { "tx_pause" },
636         { "rx_pause" },
637         { "rx_drop_frame" },
638
639         /* version 3 stats */
640         { "tx_unicast" },
641         { "tx_multicast" },
642         { "tx_broadcast" }
643 };
644
645 struct nv_ethtool_stats {
646         u64 tx_bytes;
647         u64 tx_zero_rexmt;
648         u64 tx_one_rexmt;
649         u64 tx_many_rexmt;
650         u64 tx_late_collision;
651         u64 tx_fifo_errors;
652         u64 tx_carrier_errors;
653         u64 tx_excess_deferral;
654         u64 tx_retry_error;
655         u64 rx_frame_error;
656         u64 rx_extra_byte;
657         u64 rx_late_collision;
658         u64 rx_runt;
659         u64 rx_frame_too_long;
660         u64 rx_over_errors;
661         u64 rx_crc_errors;
662         u64 rx_frame_align_error;
663         u64 rx_length_error;
664         u64 rx_unicast;
665         u64 rx_multicast;
666         u64 rx_broadcast;
667         u64 rx_packets;
668         u64 rx_errors_total;
669         u64 tx_errors_total;
670
671         /* version 2 stats */
672         u64 tx_deferral;
673         u64 tx_packets;
674         u64 rx_bytes;
675         u64 tx_pause;
676         u64 rx_pause;
677         u64 rx_drop_frame;
678
679         /* version 3 stats */
680         u64 tx_unicast;
681         u64 tx_multicast;
682         u64 tx_broadcast;
683 };
684
685 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
686 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
687 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
688
689 /* diagnostics */
690 #define NV_TEST_COUNT_BASE 3
691 #define NV_TEST_COUNT_EXTENDED 4
692
693 static const struct nv_ethtool_str nv_etests_str[] = {
694         { "link      (online/offline)" },
695         { "register  (offline)       " },
696         { "interrupt (offline)       " },
697         { "loopback  (offline)       " }
698 };
699
700 struct register_test {
701         __u32 reg;
702         __u32 mask;
703 };
704
705 static const struct register_test nv_registers_test[] = {
706         { NvRegUnknownSetupReg6, 0x01 },
707         { NvRegMisc1, 0x03c },
708         { NvRegOffloadConfig, 0x03ff },
709         { NvRegMulticastAddrA, 0xffffffff },
710         { NvRegTxWatermark, 0x0ff },
711         { NvRegWakeUpFlags, 0x07777 },
712         { 0,0 }
713 };
714
715 struct nv_skb_map {
716         struct sk_buff *skb;
717         dma_addr_t dma;
718         unsigned int dma_len;
719         struct ring_desc_ex *first_tx_desc;
720         struct nv_skb_map *next_tx_ctx;
721 };
722
723 /*
724  * SMP locking:
725  * All hardware access under netdev_priv(dev)->lock, except the performance
726  * critical parts:
727  * - rx is (pseudo-) lockless: it relies on the single-threading provided
728  *      by the arch code for interrupts.
729  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
730  *      needs netdev_priv(dev)->lock :-(
731  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
732  */
733
734 /* in dev: base, irq */
735 struct fe_priv {
736         spinlock_t lock;
737
738         struct net_device *dev;
739         struct napi_struct napi;
740
741         /* General data:
742          * Locking: spin_lock(&np->lock); */
743         struct nv_ethtool_stats estats;
744         int in_shutdown;
745         u32 linkspeed;
746         int duplex;
747         int autoneg;
748         int fixed_mode;
749         int phyaddr;
750         int wolenabled;
751         unsigned int phy_oui;
752         unsigned int phy_model;
753         unsigned int phy_rev;
754         u16 gigabit;
755         int intr_test;
756         int recover_error;
757         int quiet_count;
758
759         /* General data: RO fields */
760         dma_addr_t ring_addr;
761         struct pci_dev *pci_dev;
762         u32 orig_mac[2];
763         u32 events;
764         u32 irqmask;
765         u32 desc_ver;
766         u32 txrxctl_bits;
767         u32 vlanctl_bits;
768         u32 driver_data;
769         u32 device_id;
770         u32 register_size;
771         int rx_csum;
772         u32 mac_in_use;
773         int mgmt_version;
774         int mgmt_sema;
775
776         void __iomem *base;
777
778         /* rx specific fields.
779          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
780          */
781         union ring_type get_rx, put_rx, first_rx, last_rx;
782         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
783         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
784         struct nv_skb_map *rx_skb;
785
786         union ring_type rx_ring;
787         unsigned int rx_buf_sz;
788         unsigned int pkt_limit;
789         struct timer_list oom_kick;
790         struct timer_list nic_poll;
791         struct timer_list stats_poll;
792         u32 nic_poll_irq;
793         int rx_ring_size;
794
795         /* media detection workaround.
796          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
797          */
798         int need_linktimer;
799         unsigned long link_timeout;
800         /*
801          * tx specific fields.
802          */
803         union ring_type get_tx, put_tx, first_tx, last_tx;
804         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
805         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
806         struct nv_skb_map *tx_skb;
807
808         union ring_type tx_ring;
809         u32 tx_flags;
810         int tx_ring_size;
811         int tx_limit;
812         u32 tx_pkts_in_progress;
813         struct nv_skb_map *tx_change_owner;
814         struct nv_skb_map *tx_end_flip;
815         int tx_stop;
816
817         /* vlan fields */
818         struct vlan_group *vlangrp;
819
820         /* msi/msi-x fields */
821         u32 msi_flags;
822         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
823
824         /* flow control */
825         u32 pause_flags;
826
827         /* power saved state */
828         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
829
830         /* for different msi-x irq type */
831         char name_rx[IFNAMSIZ + 3];       /* -rx    */
832         char name_tx[IFNAMSIZ + 3];       /* -tx    */
833         char name_other[IFNAMSIZ + 6];    /* -other */
834 };
835
836 /*
837  * Maximum number of loops until we assume that a bit in the irq mask
838  * is stuck. Overridable with module param.
839  */
840 static int max_interrupt_work = 4;
841
842 /*
843  * Optimization can be either throuput mode or cpu mode
844  *
845  * Throughput Mode: Every tx and rx packet will generate an interrupt.
846  * CPU Mode: Interrupts are controlled by a timer.
847  */
848 enum {
849         NV_OPTIMIZATION_MODE_THROUGHPUT,
850         NV_OPTIMIZATION_MODE_CPU,
851         NV_OPTIMIZATION_MODE_DYNAMIC
852 };
853 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
854
855 /*
856  * Poll interval for timer irq
857  *
858  * This interval determines how frequent an interrupt is generated.
859  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
860  * Min = 0, and Max = 65535
861  */
862 static int poll_interval = -1;
863
864 /*
865  * MSI interrupts
866  */
867 enum {
868         NV_MSI_INT_DISABLED,
869         NV_MSI_INT_ENABLED
870 };
871 static int msi = NV_MSI_INT_ENABLED;
872
873 /*
874  * MSIX interrupts
875  */
876 enum {
877         NV_MSIX_INT_DISABLED,
878         NV_MSIX_INT_ENABLED
879 };
880 static int msix = NV_MSIX_INT_ENABLED;
881
882 /*
883  * DMA 64bit
884  */
885 enum {
886         NV_DMA_64BIT_DISABLED,
887         NV_DMA_64BIT_ENABLED
888 };
889 static int dma_64bit = NV_DMA_64BIT_ENABLED;
890
891 /*
892  * Crossover Detection
893  * Realtek 8201 phy + some OEM boards do not work properly.
894  */
895 enum {
896         NV_CROSSOVER_DETECTION_DISABLED,
897         NV_CROSSOVER_DETECTION_ENABLED
898 };
899 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
900
901 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
902 {
903         return netdev_priv(dev);
904 }
905
906 static inline u8 __iomem *get_hwbase(struct net_device *dev)
907 {
908         return ((struct fe_priv *)netdev_priv(dev))->base;
909 }
910
911 static inline void pci_push(u8 __iomem *base)
912 {
913         /* force out pending posted writes */
914         readl(base);
915 }
916
917 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
918 {
919         return le32_to_cpu(prd->flaglen)
920                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
921 }
922
923 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
924 {
925         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
926 }
927
928 static bool nv_optimized(struct fe_priv *np)
929 {
930         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
931                 return false;
932         return true;
933 }
934
935 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
936                                 int delay, int delaymax, const char *msg)
937 {
938         u8 __iomem *base = get_hwbase(dev);
939
940         pci_push(base);
941         do {
942                 udelay(delay);
943                 delaymax -= delay;
944                 if (delaymax < 0) {
945                         if (msg)
946                                 printk("%s", msg);
947                         return 1;
948                 }
949         } while ((readl(base + offset) & mask) != target);
950         return 0;
951 }
952
953 #define NV_SETUP_RX_RING 0x01
954 #define NV_SETUP_TX_RING 0x02
955
956 static inline u32 dma_low(dma_addr_t addr)
957 {
958         return addr;
959 }
960
961 static inline u32 dma_high(dma_addr_t addr)
962 {
963         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
964 }
965
966 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
967 {
968         struct fe_priv *np = get_nvpriv(dev);
969         u8 __iomem *base = get_hwbase(dev);
970
971         if (!nv_optimized(np)) {
972                 if (rxtx_flags & NV_SETUP_RX_RING) {
973                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
974                 }
975                 if (rxtx_flags & NV_SETUP_TX_RING) {
976                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
977                 }
978         } else {
979                 if (rxtx_flags & NV_SETUP_RX_RING) {
980                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
981                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
982                 }
983                 if (rxtx_flags & NV_SETUP_TX_RING) {
984                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
985                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
986                 }
987         }
988 }
989
990 static void free_rings(struct net_device *dev)
991 {
992         struct fe_priv *np = get_nvpriv(dev);
993
994         if (!nv_optimized(np)) {
995                 if (np->rx_ring.orig)
996                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
997                                             np->rx_ring.orig, np->ring_addr);
998         } else {
999                 if (np->rx_ring.ex)
1000                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1001                                             np->rx_ring.ex, np->ring_addr);
1002         }
1003         if (np->rx_skb)
1004                 kfree(np->rx_skb);
1005         if (np->tx_skb)
1006                 kfree(np->tx_skb);
1007 }
1008
1009 static int using_multi_irqs(struct net_device *dev)
1010 {
1011         struct fe_priv *np = get_nvpriv(dev);
1012
1013         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1014             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1015              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1016                 return 0;
1017         else
1018                 return 1;
1019 }
1020
1021 static void nv_txrx_gate(struct net_device *dev, bool gate)
1022 {
1023         struct fe_priv *np = get_nvpriv(dev);
1024         u8 __iomem *base = get_hwbase(dev);
1025         u32 powerstate;
1026
1027         if (!np->mac_in_use &&
1028             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1029                 powerstate = readl(base + NvRegPowerState2);
1030                 if (gate)
1031                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1032                 else
1033                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1034                 writel(powerstate, base + NvRegPowerState2);
1035         }
1036 }
1037
1038 static void nv_enable_irq(struct net_device *dev)
1039 {
1040         struct fe_priv *np = get_nvpriv(dev);
1041
1042         if (!using_multi_irqs(dev)) {
1043                 if (np->msi_flags & NV_MSI_X_ENABLED)
1044                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1045                 else
1046                         enable_irq(np->pci_dev->irq);
1047         } else {
1048                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1049                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1050                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1051         }
1052 }
1053
1054 static void nv_disable_irq(struct net_device *dev)
1055 {
1056         struct fe_priv *np = get_nvpriv(dev);
1057
1058         if (!using_multi_irqs(dev)) {
1059                 if (np->msi_flags & NV_MSI_X_ENABLED)
1060                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1061                 else
1062                         disable_irq(np->pci_dev->irq);
1063         } else {
1064                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1065                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1066                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1067         }
1068 }
1069
1070 /* In MSIX mode, a write to irqmask behaves as XOR */
1071 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1072 {
1073         u8 __iomem *base = get_hwbase(dev);
1074
1075         writel(mask, base + NvRegIrqMask);
1076 }
1077
1078 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1079 {
1080         struct fe_priv *np = get_nvpriv(dev);
1081         u8 __iomem *base = get_hwbase(dev);
1082
1083         if (np->msi_flags & NV_MSI_X_ENABLED) {
1084                 writel(mask, base + NvRegIrqMask);
1085         } else {
1086                 if (np->msi_flags & NV_MSI_ENABLED)
1087                         writel(0, base + NvRegMSIIrqMask);
1088                 writel(0, base + NvRegIrqMask);
1089         }
1090 }
1091
1092 static void nv_napi_enable(struct net_device *dev)
1093 {
1094 #ifdef CONFIG_FORCEDETH_NAPI
1095         struct fe_priv *np = get_nvpriv(dev);
1096
1097         napi_enable(&np->napi);
1098 #endif
1099 }
1100
1101 static void nv_napi_disable(struct net_device *dev)
1102 {
1103 #ifdef CONFIG_FORCEDETH_NAPI
1104         struct fe_priv *np = get_nvpriv(dev);
1105
1106         napi_disable(&np->napi);
1107 #endif
1108 }
1109
1110 #define MII_READ        (-1)
1111 /* mii_rw: read/write a register on the PHY.
1112  *
1113  * Caller must guarantee serialization
1114  */
1115 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1116 {
1117         u8 __iomem *base = get_hwbase(dev);
1118         u32 reg;
1119         int retval;
1120
1121         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1122
1123         reg = readl(base + NvRegMIIControl);
1124         if (reg & NVREG_MIICTL_INUSE) {
1125                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1126                 udelay(NV_MIIBUSY_DELAY);
1127         }
1128
1129         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1130         if (value != MII_READ) {
1131                 writel(value, base + NvRegMIIData);
1132                 reg |= NVREG_MIICTL_WRITE;
1133         }
1134         writel(reg, base + NvRegMIIControl);
1135
1136         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1137                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1138                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1139                                 dev->name, miireg, addr);
1140                 retval = -1;
1141         } else if (value != MII_READ) {
1142                 /* it was a write operation - fewer failures are detectable */
1143                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1144                                 dev->name, value, miireg, addr);
1145                 retval = 0;
1146         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1147                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1148                                 dev->name, miireg, addr);
1149                 retval = -1;
1150         } else {
1151                 retval = readl(base + NvRegMIIData);
1152                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1153                                 dev->name, miireg, addr, retval);
1154         }
1155
1156         return retval;
1157 }
1158
1159 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1160 {
1161         struct fe_priv *np = netdev_priv(dev);
1162         u32 miicontrol;
1163         unsigned int tries = 0;
1164
1165         miicontrol = BMCR_RESET | bmcr_setup;
1166         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1167                 return -1;
1168         }
1169
1170         /* wait for 500ms */
1171         msleep(500);
1172
1173         /* must wait till reset is deasserted */
1174         while (miicontrol & BMCR_RESET) {
1175                 msleep(10);
1176                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1177                 /* FIXME: 100 tries seem excessive */
1178                 if (tries++ > 100)
1179                         return -1;
1180         }
1181         return 0;
1182 }
1183
1184 static int phy_init(struct net_device *dev)
1185 {
1186         struct fe_priv *np = get_nvpriv(dev);
1187         u8 __iomem *base = get_hwbase(dev);
1188         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1189
1190         /* phy errata for E3016 phy */
1191         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1192                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1193                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1194                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1195                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1196                         return PHY_ERROR;
1197                 }
1198         }
1199         if (np->phy_oui == PHY_OUI_REALTEK) {
1200                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1201                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1202                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1203                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1204                                 return PHY_ERROR;
1205                         }
1206                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1207                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1208                                 return PHY_ERROR;
1209                         }
1210                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1211                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1212                                 return PHY_ERROR;
1213                         }
1214                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1215                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1216                                 return PHY_ERROR;
1217                         }
1218                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1219                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1220                                 return PHY_ERROR;
1221                         }
1222                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1223                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1224                                 return PHY_ERROR;
1225                         }
1226                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1227                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1228                                 return PHY_ERROR;
1229                         }
1230                 }
1231                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1232                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1233                         u32 powerstate = readl(base + NvRegPowerState2);
1234
1235                         /* need to perform hw phy reset */
1236                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1237                         writel(powerstate, base + NvRegPowerState2);
1238                         msleep(25);
1239
1240                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1241                         writel(powerstate, base + NvRegPowerState2);
1242                         msleep(25);
1243
1244                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1245                         reg |= PHY_REALTEK_INIT9;
1246                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1247                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1248                                 return PHY_ERROR;
1249                         }
1250                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1251                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1252                                 return PHY_ERROR;
1253                         }
1254                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1255                         if (!(reg & PHY_REALTEK_INIT11)) {
1256                                 reg |= PHY_REALTEK_INIT11;
1257                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1258                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259                                         return PHY_ERROR;
1260                                 }
1261                         }
1262                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1263                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1264                                 return PHY_ERROR;
1265                         }
1266                 }
1267                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1268                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1269                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1270                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1271                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1272                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1273                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1274                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1275                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1276                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1277                                 phy_reserved |= PHY_REALTEK_INIT7;
1278                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1279                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1280                                         return PHY_ERROR;
1281                                 }
1282                         }
1283                 }
1284         }
1285
1286         /* set advertise register */
1287         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1288         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1289         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1290                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1291                 return PHY_ERROR;
1292         }
1293
1294         /* get phy interface type */
1295         phyinterface = readl(base + NvRegPhyInterface);
1296
1297         /* see if gigabit phy */
1298         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1299         if (mii_status & PHY_GIGABIT) {
1300                 np->gigabit = PHY_GIGABIT;
1301                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1302                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1303                 if (phyinterface & PHY_RGMII)
1304                         mii_control_1000 |= ADVERTISE_1000FULL;
1305                 else
1306                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1307
1308                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1309                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1310                         return PHY_ERROR;
1311                 }
1312         }
1313         else
1314                 np->gigabit = 0;
1315
1316         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1317         mii_control |= BMCR_ANENABLE;
1318
1319         if (np->phy_oui == PHY_OUI_REALTEK &&
1320             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1321             np->phy_rev == PHY_REV_REALTEK_8211C) {
1322                 /* start autoneg since we already performed hw reset above */
1323                 mii_control |= BMCR_ANRESTART;
1324                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1325                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1326                         return PHY_ERROR;
1327                 }
1328         } else {
1329                 /* reset the phy
1330                  * (certain phys need bmcr to be setup with reset)
1331                  */
1332                 if (phy_reset(dev, mii_control)) {
1333                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1334                         return PHY_ERROR;
1335                 }
1336         }
1337
1338         /* phy vendor specific configuration */
1339         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1340                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1341                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1342                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1343                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1344                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1345                         return PHY_ERROR;
1346                 }
1347                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1348                 phy_reserved |= PHY_CICADA_INIT5;
1349                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1350                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1351                         return PHY_ERROR;
1352                 }
1353         }
1354         if (np->phy_oui == PHY_OUI_CICADA) {
1355                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1356                 phy_reserved |= PHY_CICADA_INIT6;
1357                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1358                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1359                         return PHY_ERROR;
1360                 }
1361         }
1362         if (np->phy_oui == PHY_OUI_VITESSE) {
1363                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1364                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365                         return PHY_ERROR;
1366                 }
1367                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1368                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369                         return PHY_ERROR;
1370                 }
1371                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1372                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1373                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1374                         return PHY_ERROR;
1375                 }
1376                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1377                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1378                 phy_reserved |= PHY_VITESSE_INIT3;
1379                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1380                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1381                         return PHY_ERROR;
1382                 }
1383                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1384                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1385                         return PHY_ERROR;
1386                 }
1387                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1388                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1389                         return PHY_ERROR;
1390                 }
1391                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1392                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1393                 phy_reserved |= PHY_VITESSE_INIT3;
1394                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1395                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1396                         return PHY_ERROR;
1397                 }
1398                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1399                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1400                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1401                         return PHY_ERROR;
1402                 }
1403                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1404                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1405                         return PHY_ERROR;
1406                 }
1407                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1408                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409                         return PHY_ERROR;
1410                 }
1411                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1412                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1413                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1414                         return PHY_ERROR;
1415                 }
1416                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1417                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1418                 phy_reserved |= PHY_VITESSE_INIT8;
1419                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1420                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1421                         return PHY_ERROR;
1422                 }
1423                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1424                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1425                         return PHY_ERROR;
1426                 }
1427                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1428                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1429                         return PHY_ERROR;
1430                 }
1431         }
1432         if (np->phy_oui == PHY_OUI_REALTEK) {
1433                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1434                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1435                         /* reset could have cleared these out, set them back */
1436                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1437                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1438                                 return PHY_ERROR;
1439                         }
1440                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1441                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1442                                 return PHY_ERROR;
1443                         }
1444                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1445                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1446                                 return PHY_ERROR;
1447                         }
1448                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1449                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1450                                 return PHY_ERROR;
1451                         }
1452                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1453                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1454                                 return PHY_ERROR;
1455                         }
1456                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1457                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1458                                 return PHY_ERROR;
1459                         }
1460                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1461                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1462                                 return PHY_ERROR;
1463                         }
1464                 }
1465                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1466                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1467                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1468                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1469                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1470                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1471                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1472                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1473                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1474                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1475                                 phy_reserved |= PHY_REALTEK_INIT7;
1476                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1477                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1478                                         return PHY_ERROR;
1479                                 }
1480                         }
1481                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1482                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1483                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1484                                         return PHY_ERROR;
1485                                 }
1486                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1487                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1488                                 phy_reserved |= PHY_REALTEK_INIT3;
1489                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1490                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1491                                         return PHY_ERROR;
1492                                 }
1493                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1494                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1495                                         return PHY_ERROR;
1496                                 }
1497                         }
1498                 }
1499         }
1500
1501         /* some phys clear out pause advertisment on reset, set it back */
1502         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1503
1504         /* restart auto negotiation, power down phy */
1505         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1506         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1507         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1508                 return PHY_ERROR;
1509         }
1510
1511         return 0;
1512 }
1513
1514 static void nv_start_rx(struct net_device *dev)
1515 {
1516         struct fe_priv *np = netdev_priv(dev);
1517         u8 __iomem *base = get_hwbase(dev);
1518         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1519
1520         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1521         /* Already running? Stop it. */
1522         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1523                 rx_ctrl &= ~NVREG_RCVCTL_START;
1524                 writel(rx_ctrl, base + NvRegReceiverControl);
1525                 pci_push(base);
1526         }
1527         writel(np->linkspeed, base + NvRegLinkSpeed);
1528         pci_push(base);
1529         rx_ctrl |= NVREG_RCVCTL_START;
1530         if (np->mac_in_use)
1531                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1532         writel(rx_ctrl, base + NvRegReceiverControl);
1533         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1534                                 dev->name, np->duplex, np->linkspeed);
1535         pci_push(base);
1536 }
1537
1538 static void nv_stop_rx(struct net_device *dev)
1539 {
1540         struct fe_priv *np = netdev_priv(dev);
1541         u8 __iomem *base = get_hwbase(dev);
1542         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1543
1544         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1545         if (!np->mac_in_use)
1546                 rx_ctrl &= ~NVREG_RCVCTL_START;
1547         else
1548                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1549         writel(rx_ctrl, base + NvRegReceiverControl);
1550         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1551                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1552                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1553
1554         udelay(NV_RXSTOP_DELAY2);
1555         if (!np->mac_in_use)
1556                 writel(0, base + NvRegLinkSpeed);
1557 }
1558
1559 static void nv_start_tx(struct net_device *dev)
1560 {
1561         struct fe_priv *np = netdev_priv(dev);
1562         u8 __iomem *base = get_hwbase(dev);
1563         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564
1565         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1566         tx_ctrl |= NVREG_XMITCTL_START;
1567         if (np->mac_in_use)
1568                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1569         writel(tx_ctrl, base + NvRegTransmitterControl);
1570         pci_push(base);
1571 }
1572
1573 static void nv_stop_tx(struct net_device *dev)
1574 {
1575         struct fe_priv *np = netdev_priv(dev);
1576         u8 __iomem *base = get_hwbase(dev);
1577         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578
1579         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1580         if (!np->mac_in_use)
1581                 tx_ctrl &= ~NVREG_XMITCTL_START;
1582         else
1583                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1584         writel(tx_ctrl, base + NvRegTransmitterControl);
1585         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1586                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1587                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1588
1589         udelay(NV_TXSTOP_DELAY2);
1590         if (!np->mac_in_use)
1591                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1592                        base + NvRegTransmitPoll);
1593 }
1594
1595 static void nv_start_rxtx(struct net_device *dev)
1596 {
1597         nv_start_rx(dev);
1598         nv_start_tx(dev);
1599 }
1600
1601 static void nv_stop_rxtx(struct net_device *dev)
1602 {
1603         nv_stop_rx(dev);
1604         nv_stop_tx(dev);
1605 }
1606
1607 static void nv_txrx_reset(struct net_device *dev)
1608 {
1609         struct fe_priv *np = netdev_priv(dev);
1610         u8 __iomem *base = get_hwbase(dev);
1611
1612         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1613         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1614         pci_push(base);
1615         udelay(NV_TXRX_RESET_DELAY);
1616         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1617         pci_push(base);
1618 }
1619
1620 static void nv_mac_reset(struct net_device *dev)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         u8 __iomem *base = get_hwbase(dev);
1624         u32 temp1, temp2, temp3;
1625
1626         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1627
1628         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1629         pci_push(base);
1630
1631         /* save registers since they will be cleared on reset */
1632         temp1 = readl(base + NvRegMacAddrA);
1633         temp2 = readl(base + NvRegMacAddrB);
1634         temp3 = readl(base + NvRegTransmitPoll);
1635
1636         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1637         pci_push(base);
1638         udelay(NV_MAC_RESET_DELAY);
1639         writel(0, base + NvRegMacReset);
1640         pci_push(base);
1641         udelay(NV_MAC_RESET_DELAY);
1642
1643         /* restore saved registers */
1644         writel(temp1, base + NvRegMacAddrA);
1645         writel(temp2, base + NvRegMacAddrB);
1646         writel(temp3, base + NvRegTransmitPoll);
1647
1648         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1649         pci_push(base);
1650 }
1651
1652 static void nv_get_hw_stats(struct net_device *dev)
1653 {
1654         struct fe_priv *np = netdev_priv(dev);
1655         u8 __iomem *base = get_hwbase(dev);
1656
1657         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1658         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1659         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1660         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1661         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1662         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1663         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1664         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1665         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1666         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1667         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1668         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1669         np->estats.rx_runt += readl(base + NvRegRxRunt);
1670         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1671         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1672         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1673         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1674         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1675         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1676         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1677         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1678         np->estats.rx_packets =
1679                 np->estats.rx_unicast +
1680                 np->estats.rx_multicast +
1681                 np->estats.rx_broadcast;
1682         np->estats.rx_errors_total =
1683                 np->estats.rx_crc_errors +
1684                 np->estats.rx_over_errors +
1685                 np->estats.rx_frame_error +
1686                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1687                 np->estats.rx_late_collision +
1688                 np->estats.rx_runt +
1689                 np->estats.rx_frame_too_long;
1690         np->estats.tx_errors_total =
1691                 np->estats.tx_late_collision +
1692                 np->estats.tx_fifo_errors +
1693                 np->estats.tx_carrier_errors +
1694                 np->estats.tx_excess_deferral +
1695                 np->estats.tx_retry_error;
1696
1697         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1698                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1699                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1700                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1701                 np->estats.tx_pause += readl(base + NvRegTxPause);
1702                 np->estats.rx_pause += readl(base + NvRegRxPause);
1703                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1704         }
1705
1706         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1707                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1708                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1709                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1710         }
1711 }
1712
1713 /*
1714  * nv_get_stats: dev->get_stats function
1715  * Get latest stats value from the nic.
1716  * Called with read_lock(&dev_base_lock) held for read -
1717  * only synchronized against unregister_netdevice.
1718  */
1719 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1720 {
1721         struct fe_priv *np = netdev_priv(dev);
1722
1723         /* If the nic supports hw counters then retrieve latest values */
1724         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1725                 nv_get_hw_stats(dev);
1726
1727                 /* copy to net_device stats */
1728                 dev->stats.tx_bytes = np->estats.tx_bytes;
1729                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1730                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1731                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1732                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1733                 dev->stats.rx_errors = np->estats.rx_errors_total;
1734                 dev->stats.tx_errors = np->estats.tx_errors_total;
1735         }
1736
1737         return &dev->stats;
1738 }
1739
1740 /*
1741  * nv_alloc_rx: fill rx ring entries.
1742  * Return 1 if the allocations for the skbs failed and the
1743  * rx engine is without Available descriptors
1744  */
1745 static int nv_alloc_rx(struct net_device *dev)
1746 {
1747         struct fe_priv *np = netdev_priv(dev);
1748         struct ring_desc* less_rx;
1749
1750         less_rx = np->get_rx.orig;
1751         if (less_rx-- == np->first_rx.orig)
1752                 less_rx = np->last_rx.orig;
1753
1754         while (np->put_rx.orig != less_rx) {
1755                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1756                 if (skb) {
1757                         np->put_rx_ctx->skb = skb;
1758                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1759                                                              skb->data,
1760                                                              skb_tailroom(skb),
1761                                                              PCI_DMA_FROMDEVICE);
1762                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1763                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1764                         wmb();
1765                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1766                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1767                                 np->put_rx.orig = np->first_rx.orig;
1768                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1769                                 np->put_rx_ctx = np->first_rx_ctx;
1770                 } else {
1771                         return 1;
1772                 }
1773         }
1774         return 0;
1775 }
1776
1777 static int nv_alloc_rx_optimized(struct net_device *dev)
1778 {
1779         struct fe_priv *np = netdev_priv(dev);
1780         struct ring_desc_ex* less_rx;
1781
1782         less_rx = np->get_rx.ex;
1783         if (less_rx-- == np->first_rx.ex)
1784                 less_rx = np->last_rx.ex;
1785
1786         while (np->put_rx.ex != less_rx) {
1787                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1788                 if (skb) {
1789                         np->put_rx_ctx->skb = skb;
1790                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1791                                                              skb->data,
1792                                                              skb_tailroom(skb),
1793                                                              PCI_DMA_FROMDEVICE);
1794                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1795                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1796                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1797                         wmb();
1798                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1799                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1800                                 np->put_rx.ex = np->first_rx.ex;
1801                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1802                                 np->put_rx_ctx = np->first_rx_ctx;
1803                 } else {
1804                         return 1;
1805                 }
1806         }
1807         return 0;
1808 }
1809
1810 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1811 #ifdef CONFIG_FORCEDETH_NAPI
1812 static void nv_do_rx_refill(unsigned long data)
1813 {
1814         struct net_device *dev = (struct net_device *) data;
1815         struct fe_priv *np = netdev_priv(dev);
1816
1817         /* Just reschedule NAPI rx processing */
1818         napi_schedule(&np->napi);
1819 }
1820 #else
1821 static void nv_do_rx_refill(unsigned long data)
1822 {
1823         struct net_device *dev = (struct net_device *) data;
1824         struct fe_priv *np = netdev_priv(dev);
1825         int retcode;
1826
1827         if (!using_multi_irqs(dev)) {
1828                 if (np->msi_flags & NV_MSI_X_ENABLED)
1829                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1830                 else
1831                         disable_irq(np->pci_dev->irq);
1832         } else {
1833                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1834         }
1835         if (!nv_optimized(np))
1836                 retcode = nv_alloc_rx(dev);
1837         else
1838                 retcode = nv_alloc_rx_optimized(dev);
1839         if (retcode) {
1840                 spin_lock_irq(&np->lock);
1841                 if (!np->in_shutdown)
1842                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1843                 spin_unlock_irq(&np->lock);
1844         }
1845         if (!using_multi_irqs(dev)) {
1846                 if (np->msi_flags & NV_MSI_X_ENABLED)
1847                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1848                 else
1849                         enable_irq(np->pci_dev->irq);
1850         } else {
1851                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1852         }
1853 }
1854 #endif
1855
1856 static void nv_init_rx(struct net_device *dev)
1857 {
1858         struct fe_priv *np = netdev_priv(dev);
1859         int i;
1860
1861         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1862
1863         if (!nv_optimized(np))
1864                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1865         else
1866                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1867         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1868         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1869
1870         for (i = 0; i < np->rx_ring_size; i++) {
1871                 if (!nv_optimized(np)) {
1872                         np->rx_ring.orig[i].flaglen = 0;
1873                         np->rx_ring.orig[i].buf = 0;
1874                 } else {
1875                         np->rx_ring.ex[i].flaglen = 0;
1876                         np->rx_ring.ex[i].txvlan = 0;
1877                         np->rx_ring.ex[i].bufhigh = 0;
1878                         np->rx_ring.ex[i].buflow = 0;
1879                 }
1880                 np->rx_skb[i].skb = NULL;
1881                 np->rx_skb[i].dma = 0;
1882         }
1883 }
1884
1885 static void nv_init_tx(struct net_device *dev)
1886 {
1887         struct fe_priv *np = netdev_priv(dev);
1888         int i;
1889
1890         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1891
1892         if (!nv_optimized(np))
1893                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1894         else
1895                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1896         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1897         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1898         np->tx_pkts_in_progress = 0;
1899         np->tx_change_owner = NULL;
1900         np->tx_end_flip = NULL;
1901         np->tx_stop = 0;
1902
1903         for (i = 0; i < np->tx_ring_size; i++) {
1904                 if (!nv_optimized(np)) {
1905                         np->tx_ring.orig[i].flaglen = 0;
1906                         np->tx_ring.orig[i].buf = 0;
1907                 } else {
1908                         np->tx_ring.ex[i].flaglen = 0;
1909                         np->tx_ring.ex[i].txvlan = 0;
1910                         np->tx_ring.ex[i].bufhigh = 0;
1911                         np->tx_ring.ex[i].buflow = 0;
1912                 }
1913                 np->tx_skb[i].skb = NULL;
1914                 np->tx_skb[i].dma = 0;
1915                 np->tx_skb[i].dma_len = 0;
1916                 np->tx_skb[i].first_tx_desc = NULL;
1917                 np->tx_skb[i].next_tx_ctx = NULL;
1918         }
1919 }
1920
1921 static int nv_init_ring(struct net_device *dev)
1922 {
1923         struct fe_priv *np = netdev_priv(dev);
1924
1925         nv_init_tx(dev);
1926         nv_init_rx(dev);
1927
1928         if (!nv_optimized(np))
1929                 return nv_alloc_rx(dev);
1930         else
1931                 return nv_alloc_rx_optimized(dev);
1932 }
1933
1934 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1935 {
1936         struct fe_priv *np = netdev_priv(dev);
1937
1938         if (tx_skb->dma) {
1939                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1940                                tx_skb->dma_len,
1941                                PCI_DMA_TODEVICE);
1942                 tx_skb->dma = 0;
1943         }
1944         if (tx_skb->skb) {
1945                 dev_kfree_skb_any(tx_skb->skb);
1946                 tx_skb->skb = NULL;
1947                 return 1;
1948         } else {
1949                 return 0;
1950         }
1951 }
1952
1953 static void nv_drain_tx(struct net_device *dev)
1954 {
1955         struct fe_priv *np = netdev_priv(dev);
1956         unsigned int i;
1957
1958         for (i = 0; i < np->tx_ring_size; i++) {
1959                 if (!nv_optimized(np)) {
1960                         np->tx_ring.orig[i].flaglen = 0;
1961                         np->tx_ring.orig[i].buf = 0;
1962                 } else {
1963                         np->tx_ring.ex[i].flaglen = 0;
1964                         np->tx_ring.ex[i].txvlan = 0;
1965                         np->tx_ring.ex[i].bufhigh = 0;
1966                         np->tx_ring.ex[i].buflow = 0;
1967                 }
1968                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1969                         dev->stats.tx_dropped++;
1970                 np->tx_skb[i].dma = 0;
1971                 np->tx_skb[i].dma_len = 0;
1972                 np->tx_skb[i].first_tx_desc = NULL;
1973                 np->tx_skb[i].next_tx_ctx = NULL;
1974         }
1975         np->tx_pkts_in_progress = 0;
1976         np->tx_change_owner = NULL;
1977         np->tx_end_flip = NULL;
1978 }
1979
1980 static void nv_drain_rx(struct net_device *dev)
1981 {
1982         struct fe_priv *np = netdev_priv(dev);
1983         int i;
1984
1985         for (i = 0; i < np->rx_ring_size; i++) {
1986                 if (!nv_optimized(np)) {
1987                         np->rx_ring.orig[i].flaglen = 0;
1988                         np->rx_ring.orig[i].buf = 0;
1989                 } else {
1990                         np->rx_ring.ex[i].flaglen = 0;
1991                         np->rx_ring.ex[i].txvlan = 0;
1992                         np->rx_ring.ex[i].bufhigh = 0;
1993                         np->rx_ring.ex[i].buflow = 0;
1994                 }
1995                 wmb();
1996                 if (np->rx_skb[i].skb) {
1997                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1998                                          (skb_end_pointer(np->rx_skb[i].skb) -
1999                                           np->rx_skb[i].skb->data),
2000                                          PCI_DMA_FROMDEVICE);
2001                         dev_kfree_skb(np->rx_skb[i].skb);
2002                         np->rx_skb[i].skb = NULL;
2003                 }
2004         }
2005 }
2006
2007 static void nv_drain_rxtx(struct net_device *dev)
2008 {
2009         nv_drain_tx(dev);
2010         nv_drain_rx(dev);
2011 }
2012
2013 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2014 {
2015         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2016 }
2017
2018 static void nv_legacybackoff_reseed(struct net_device *dev)
2019 {
2020         u8 __iomem *base = get_hwbase(dev);
2021         u32 reg;
2022         u32 low;
2023         int tx_status = 0;
2024
2025         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2026         get_random_bytes(&low, sizeof(low));
2027         reg |= low & NVREG_SLOTTIME_MASK;
2028
2029         /* Need to stop tx before change takes effect.
2030          * Caller has already gained np->lock.
2031          */
2032         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2033         if (tx_status)
2034                 nv_stop_tx(dev);
2035         nv_stop_rx(dev);
2036         writel(reg, base + NvRegSlotTime);
2037         if (tx_status)
2038                 nv_start_tx(dev);
2039         nv_start_rx(dev);
2040 }
2041
2042 /* Gear Backoff Seeds */
2043 #define BACKOFF_SEEDSET_ROWS    8
2044 #define BACKOFF_SEEDSET_LFSRS   15
2045
2046 /* Known Good seed sets */
2047 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2048     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2049     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2050     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2051     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2052     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2053     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2054     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2055     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2056
2057 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2058     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2059     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2060     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2061     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2062     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2063     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2064     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2065     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2066
2067 static void nv_gear_backoff_reseed(struct net_device *dev)
2068 {
2069         u8 __iomem *base = get_hwbase(dev);
2070         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2071         u32 temp, seedset, combinedSeed;
2072         int i;
2073
2074         /* Setup seed for free running LFSR */
2075         /* We are going to read the time stamp counter 3 times
2076            and swizzle bits around to increase randomness */
2077         get_random_bytes(&miniseed1, sizeof(miniseed1));
2078         miniseed1 &= 0x0fff;
2079         if (miniseed1 == 0)
2080                 miniseed1 = 0xabc;
2081
2082         get_random_bytes(&miniseed2, sizeof(miniseed2));
2083         miniseed2 &= 0x0fff;
2084         if (miniseed2 == 0)
2085                 miniseed2 = 0xabc;
2086         miniseed2_reversed =
2087                 ((miniseed2 & 0xF00) >> 8) |
2088                  (miniseed2 & 0x0F0) |
2089                  ((miniseed2 & 0x00F) << 8);
2090
2091         get_random_bytes(&miniseed3, sizeof(miniseed3));
2092         miniseed3 &= 0x0fff;
2093         if (miniseed3 == 0)
2094                 miniseed3 = 0xabc;
2095         miniseed3_reversed =
2096                 ((miniseed3 & 0xF00) >> 8) |
2097                  (miniseed3 & 0x0F0) |
2098                  ((miniseed3 & 0x00F) << 8);
2099
2100         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2101                        (miniseed2 ^ miniseed3_reversed);
2102
2103         /* Seeds can not be zero */
2104         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2105                 combinedSeed |= 0x08;
2106         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2107                 combinedSeed |= 0x8000;
2108
2109         /* No need to disable tx here */
2110         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2111         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2112         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2113         writel(temp,base + NvRegBackOffControl);
2114
2115         /* Setup seeds for all gear LFSRs. */
2116         get_random_bytes(&seedset, sizeof(seedset));
2117         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2118         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2119         {
2120                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2121                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2122                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2123                 writel(temp, base + NvRegBackOffControl);
2124         }
2125 }
2126
2127 /*
2128  * nv_start_xmit: dev->hard_start_xmit function
2129  * Called with netif_tx_lock held.
2130  */
2131 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2132 {
2133         struct fe_priv *np = netdev_priv(dev);
2134         u32 tx_flags = 0;
2135         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2136         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2137         unsigned int i;
2138         u32 offset = 0;
2139         u32 bcnt;
2140         u32 size = skb->len-skb->data_len;
2141         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2142         u32 empty_slots;
2143         struct ring_desc* put_tx;
2144         struct ring_desc* start_tx;
2145         struct ring_desc* prev_tx;
2146         struct nv_skb_map* prev_tx_ctx;
2147         unsigned long flags;
2148
2149         /* add fragments to entries count */
2150         for (i = 0; i < fragments; i++) {
2151                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2152                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2153         }
2154
2155         spin_lock_irqsave(&np->lock, flags);
2156         empty_slots = nv_get_empty_tx_slots(np);
2157         if (unlikely(empty_slots <= entries)) {
2158                 netif_stop_queue(dev);
2159                 np->tx_stop = 1;
2160                 spin_unlock_irqrestore(&np->lock, flags);
2161                 return NETDEV_TX_BUSY;
2162         }
2163         spin_unlock_irqrestore(&np->lock, flags);
2164
2165         start_tx = put_tx = np->put_tx.orig;
2166
2167         /* setup the header buffer */
2168         do {
2169                 prev_tx = put_tx;
2170                 prev_tx_ctx = np->put_tx_ctx;
2171                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2172                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2173                                                 PCI_DMA_TODEVICE);
2174                 np->put_tx_ctx->dma_len = bcnt;
2175                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2176                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2177
2178                 tx_flags = np->tx_flags;
2179                 offset += bcnt;
2180                 size -= bcnt;
2181                 if (unlikely(put_tx++ == np->last_tx.orig))
2182                         put_tx = np->first_tx.orig;
2183                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2184                         np->put_tx_ctx = np->first_tx_ctx;
2185         } while (size);
2186
2187         /* setup the fragments */
2188         for (i = 0; i < fragments; i++) {
2189                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2190                 u32 size = frag->size;
2191                 offset = 0;
2192
2193                 do {
2194                         prev_tx = put_tx;
2195                         prev_tx_ctx = np->put_tx_ctx;
2196                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2197                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2198                                                            PCI_DMA_TODEVICE);
2199                         np->put_tx_ctx->dma_len = bcnt;
2200                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2201                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2202
2203                         offset += bcnt;
2204                         size -= bcnt;
2205                         if (unlikely(put_tx++ == np->last_tx.orig))
2206                                 put_tx = np->first_tx.orig;
2207                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2208                                 np->put_tx_ctx = np->first_tx_ctx;
2209                 } while (size);
2210         }
2211
2212         /* set last fragment flag  */
2213         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2214
2215         /* save skb in this slot's context area */
2216         prev_tx_ctx->skb = skb;
2217
2218         if (skb_is_gso(skb))
2219                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2220         else
2221                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2222                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2223
2224         spin_lock_irqsave(&np->lock, flags);
2225
2226         /* set tx flags */
2227         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2228         np->put_tx.orig = put_tx;
2229
2230         spin_unlock_irqrestore(&np->lock, flags);
2231
2232         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2233                 dev->name, entries, tx_flags_extra);
2234         {
2235                 int j;
2236                 for (j=0; j<64; j++) {
2237                         if ((j%16) == 0)
2238                                 dprintk("\n%03x:", j);
2239                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2240                 }
2241                 dprintk("\n");
2242         }
2243
2244         dev->trans_start = jiffies;
2245         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2246         return NETDEV_TX_OK;
2247 }
2248
2249 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2250 {
2251         struct fe_priv *np = netdev_priv(dev);
2252         u32 tx_flags = 0;
2253         u32 tx_flags_extra;
2254         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2255         unsigned int i;
2256         u32 offset = 0;
2257         u32 bcnt;
2258         u32 size = skb->len-skb->data_len;
2259         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2260         u32 empty_slots;
2261         struct ring_desc_ex* put_tx;
2262         struct ring_desc_ex* start_tx;
2263         struct ring_desc_ex* prev_tx;
2264         struct nv_skb_map* prev_tx_ctx;
2265         struct nv_skb_map* start_tx_ctx;
2266         unsigned long flags;
2267
2268         /* add fragments to entries count */
2269         for (i = 0; i < fragments; i++) {
2270                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2271                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2272         }
2273
2274         spin_lock_irqsave(&np->lock, flags);
2275         empty_slots = nv_get_empty_tx_slots(np);
2276         if (unlikely(empty_slots <= entries)) {
2277                 netif_stop_queue(dev);
2278                 np->tx_stop = 1;
2279                 spin_unlock_irqrestore(&np->lock, flags);
2280                 return NETDEV_TX_BUSY;
2281         }
2282         spin_unlock_irqrestore(&np->lock, flags);
2283
2284         start_tx = put_tx = np->put_tx.ex;
2285         start_tx_ctx = np->put_tx_ctx;
2286
2287         /* setup the header buffer */
2288         do {
2289                 prev_tx = put_tx;
2290                 prev_tx_ctx = np->put_tx_ctx;
2291                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2292                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2293                                                 PCI_DMA_TODEVICE);
2294                 np->put_tx_ctx->dma_len = bcnt;
2295                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2296                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2297                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2298
2299                 tx_flags = NV_TX2_VALID;
2300                 offset += bcnt;
2301                 size -= bcnt;
2302                 if (unlikely(put_tx++ == np->last_tx.ex))
2303                         put_tx = np->first_tx.ex;
2304                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2305                         np->put_tx_ctx = np->first_tx_ctx;
2306         } while (size);
2307
2308         /* setup the fragments */
2309         for (i = 0; i < fragments; i++) {
2310                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2311                 u32 size = frag->size;
2312                 offset = 0;
2313
2314                 do {
2315                         prev_tx = put_tx;
2316                         prev_tx_ctx = np->put_tx_ctx;
2317                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2318                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2319                                                            PCI_DMA_TODEVICE);
2320                         np->put_tx_ctx->dma_len = bcnt;
2321                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2322                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2323                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2324
2325                         offset += bcnt;
2326                         size -= bcnt;
2327                         if (unlikely(put_tx++ == np->last_tx.ex))
2328                                 put_tx = np->first_tx.ex;
2329                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2330                                 np->put_tx_ctx = np->first_tx_ctx;
2331                 } while (size);
2332         }
2333
2334         /* set last fragment flag  */
2335         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2336
2337         /* save skb in this slot's context area */
2338         prev_tx_ctx->skb = skb;
2339
2340         if (skb_is_gso(skb))
2341                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2342         else
2343                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2344                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2345
2346         /* vlan tag */
2347         if (likely(!np->vlangrp)) {
2348                 start_tx->txvlan = 0;
2349         } else {
2350                 if (vlan_tx_tag_present(skb))
2351                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2352                 else
2353                         start_tx->txvlan = 0;
2354         }
2355
2356         spin_lock_irqsave(&np->lock, flags);
2357
2358         if (np->tx_limit) {
2359                 /* Limit the number of outstanding tx. Setup all fragments, but
2360                  * do not set the VALID bit on the first descriptor. Save a pointer
2361                  * to that descriptor and also for next skb_map element.
2362                  */
2363
2364                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2365                         if (!np->tx_change_owner)
2366                                 np->tx_change_owner = start_tx_ctx;
2367
2368                         /* remove VALID bit */
2369                         tx_flags &= ~NV_TX2_VALID;
2370                         start_tx_ctx->first_tx_desc = start_tx;
2371                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2372                         np->tx_end_flip = np->put_tx_ctx;
2373                 } else {
2374                         np->tx_pkts_in_progress++;
2375                 }
2376         }
2377
2378         /* set tx flags */
2379         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2380         np->put_tx.ex = put_tx;
2381
2382         spin_unlock_irqrestore(&np->lock, flags);
2383
2384         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2385                 dev->name, entries, tx_flags_extra);
2386         {
2387                 int j;
2388                 for (j=0; j<64; j++) {
2389                         if ((j%16) == 0)
2390                                 dprintk("\n%03x:", j);
2391                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2392                 }
2393                 dprintk("\n");
2394         }
2395
2396         dev->trans_start = jiffies;
2397         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2398         return NETDEV_TX_OK;
2399 }
2400
2401 static inline void nv_tx_flip_ownership(struct net_device *dev)
2402 {
2403         struct fe_priv *np = netdev_priv(dev);
2404
2405         np->tx_pkts_in_progress--;
2406         if (np->tx_change_owner) {
2407                 np->tx_change_owner->first_tx_desc->flaglen |=
2408                         cpu_to_le32(NV_TX2_VALID);
2409                 np->tx_pkts_in_progress++;
2410
2411                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2412                 if (np->tx_change_owner == np->tx_end_flip)
2413                         np->tx_change_owner = NULL;
2414
2415                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2416         }
2417 }
2418
2419 /*
2420  * nv_tx_done: check for completed packets, release the skbs.
2421  *
2422  * Caller must own np->lock.
2423  */
2424 static int nv_tx_done(struct net_device *dev, int limit)
2425 {
2426         struct fe_priv *np = netdev_priv(dev);
2427         u32 flags;
2428         int tx_work = 0;
2429         struct ring_desc* orig_get_tx = np->get_tx.orig;
2430
2431         while ((np->get_tx.orig != np->put_tx.orig) &&
2432                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2433                (tx_work < limit)) {
2434
2435                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2436                                         dev->name, flags);
2437
2438                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2439                                np->get_tx_ctx->dma_len,
2440                                PCI_DMA_TODEVICE);
2441                 np->get_tx_ctx->dma = 0;
2442
2443                 if (np->desc_ver == DESC_VER_1) {
2444                         if (flags & NV_TX_LASTPACKET) {
2445                                 if (flags & NV_TX_ERROR) {
2446                                         if (flags & NV_TX_UNDERFLOW)
2447                                                 dev->stats.tx_fifo_errors++;
2448                                         if (flags & NV_TX_CARRIERLOST)
2449                                                 dev->stats.tx_carrier_errors++;
2450                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2451                                                 nv_legacybackoff_reseed(dev);
2452                                         dev->stats.tx_errors++;
2453                                 } else {
2454                                         dev->stats.tx_packets++;
2455                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2456                                 }
2457                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2458                                 np->get_tx_ctx->skb = NULL;
2459                                 tx_work++;
2460                         }
2461                 } else {
2462                         if (flags & NV_TX2_LASTPACKET) {
2463                                 if (flags & NV_TX2_ERROR) {
2464                                         if (flags & NV_TX2_UNDERFLOW)
2465                                                 dev->stats.tx_fifo_errors++;
2466                                         if (flags & NV_TX2_CARRIERLOST)
2467                                                 dev->stats.tx_carrier_errors++;
2468                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2469                                                 nv_legacybackoff_reseed(dev);
2470                                         dev->stats.tx_errors++;
2471                                 } else {
2472                                         dev->stats.tx_packets++;
2473                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2474                                 }
2475                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2476                                 np->get_tx_ctx->skb = NULL;
2477                                 tx_work++;
2478                         }
2479                 }
2480                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2481                         np->get_tx.orig = np->first_tx.orig;
2482                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2483                         np->get_tx_ctx = np->first_tx_ctx;
2484         }
2485         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2486                 np->tx_stop = 0;
2487                 netif_wake_queue(dev);
2488         }
2489         return tx_work;
2490 }
2491
2492 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2493 {
2494         struct fe_priv *np = netdev_priv(dev);
2495         u32 flags;
2496         int tx_work = 0;
2497         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2498
2499         while ((np->get_tx.ex != np->put_tx.ex) &&
2500                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2501                (tx_work < limit)) {
2502
2503                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2504                                         dev->name, flags);
2505
2506                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2507                                np->get_tx_ctx->dma_len,
2508                                PCI_DMA_TODEVICE);
2509                 np->get_tx_ctx->dma = 0;
2510
2511                 if (flags & NV_TX2_LASTPACKET) {
2512                         if (!(flags & NV_TX2_ERROR))
2513                                 dev->stats.tx_packets++;
2514                         else {
2515                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2516                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2517                                                 nv_gear_backoff_reseed(dev);
2518                                         else
2519                                                 nv_legacybackoff_reseed(dev);
2520                                 }
2521                         }
2522
2523                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2524                         np->get_tx_ctx->skb = NULL;
2525                         tx_work++;
2526
2527                         if (np->tx_limit) {
2528                                 nv_tx_flip_ownership(dev);
2529                         }
2530                 }
2531                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2532                         np->get_tx.ex = np->first_tx.ex;
2533                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2534                         np->get_tx_ctx = np->first_tx_ctx;
2535         }
2536         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2537                 np->tx_stop = 0;
2538                 netif_wake_queue(dev);
2539         }
2540         return tx_work;
2541 }
2542
2543 /*
2544  * nv_tx_timeout: dev->tx_timeout function
2545  * Called with netif_tx_lock held.
2546  */
2547 static void nv_tx_timeout(struct net_device *dev)
2548 {
2549         struct fe_priv *np = netdev_priv(dev);
2550         u8 __iomem *base = get_hwbase(dev);
2551         u32 status;
2552         union ring_type put_tx;
2553         int saved_tx_limit;
2554
2555         if (np->msi_flags & NV_MSI_X_ENABLED)
2556                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2557         else
2558                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2559
2560         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2561
2562         {
2563                 int i;
2564
2565                 printk(KERN_INFO "%s: Ring at %lx\n",
2566                        dev->name, (unsigned long)np->ring_addr);
2567                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2568                 for (i=0;i<=np->register_size;i+= 32) {
2569                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2570                                         i,
2571                                         readl(base + i + 0), readl(base + i + 4),
2572                                         readl(base + i + 8), readl(base + i + 12),
2573                                         readl(base + i + 16), readl(base + i + 20),
2574                                         readl(base + i + 24), readl(base + i + 28));
2575                 }
2576                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2577                 for (i=0;i<np->tx_ring_size;i+= 4) {
2578                         if (!nv_optimized(np)) {
2579                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2580                                        i,
2581                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2582                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2583                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2584                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2585                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2586                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2587                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2588                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2589                         } else {
2590                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2591                                        i,
2592                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2593                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2594                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2595                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2596                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2597                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2598                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2599                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2600                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2601                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2602                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2603                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2604                         }
2605                 }
2606         }
2607
2608         spin_lock_irq(&np->lock);
2609
2610         /* 1) stop tx engine */
2611         nv_stop_tx(dev);
2612
2613         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2614         saved_tx_limit = np->tx_limit;
2615         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2616         np->tx_stop = 0;  /* prevent waking tx queue */
2617         if (!nv_optimized(np))
2618                 nv_tx_done(dev, np->tx_ring_size);
2619         else
2620                 nv_tx_done_optimized(dev, np->tx_ring_size);
2621
2622         /* save current HW postion */
2623         if (np->tx_change_owner)
2624                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2625         else
2626                 put_tx = np->put_tx;
2627
2628         /* 3) clear all tx state */
2629         nv_drain_tx(dev);
2630         nv_init_tx(dev);
2631
2632         /* 4) restore state to current HW position */
2633         np->get_tx = np->put_tx = put_tx;
2634         np->tx_limit = saved_tx_limit;
2635
2636         /* 5) restart tx engine */
2637         nv_start_tx(dev);
2638         netif_wake_queue(dev);
2639         spin_unlock_irq(&np->lock);
2640 }
2641
2642 /*
2643  * Called when the nic notices a mismatch between the actual data len on the
2644  * wire and the len indicated in the 802 header
2645  */
2646 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2647 {
2648         int hdrlen;     /* length of the 802 header */
2649         int protolen;   /* length as stored in the proto field */
2650
2651         /* 1) calculate len according to header */
2652         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2653                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2654                 hdrlen = VLAN_HLEN;
2655         } else {
2656                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2657                 hdrlen = ETH_HLEN;
2658         }
2659         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2660                                 dev->name, datalen, protolen, hdrlen);
2661         if (protolen > ETH_DATA_LEN)
2662                 return datalen; /* Value in proto field not a len, no checks possible */
2663
2664         protolen += hdrlen;
2665         /* consistency checks: */
2666         if (datalen > ETH_ZLEN) {
2667                 if (datalen >= protolen) {
2668                         /* more data on wire than in 802 header, trim of
2669                          * additional data.
2670                          */
2671                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2672                                         dev->name, protolen);
2673                         return protolen;
2674                 } else {
2675                         /* less data on wire than mentioned in header.
2676                          * Discard the packet.
2677                          */
2678                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2679                                         dev->name);
2680                         return -1;
2681                 }
2682         } else {
2683                 /* short packet. Accept only if 802 values are also short */
2684                 if (protolen > ETH_ZLEN) {
2685                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2686                                         dev->name);
2687                         return -1;
2688                 }
2689                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2690                                 dev->name, datalen);
2691                 return datalen;
2692         }
2693 }
2694
2695 static int nv_rx_process(struct net_device *dev, int limit)
2696 {
2697         struct fe_priv *np = netdev_priv(dev);
2698         u32 flags;
2699         int rx_work = 0;
2700         struct sk_buff *skb;
2701         int len;
2702
2703         while((np->get_rx.orig != np->put_rx.orig) &&
2704               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2705                 (rx_work < limit)) {
2706
2707                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2708                                         dev->name, flags);
2709
2710                 /*
2711                  * the packet is for us - immediately tear down the pci mapping.
2712                  * TODO: check if a prefetch of the first cacheline improves
2713                  * the performance.
2714                  */
2715                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2716                                 np->get_rx_ctx->dma_len,
2717                                 PCI_DMA_FROMDEVICE);
2718                 skb = np->get_rx_ctx->skb;
2719                 np->get_rx_ctx->skb = NULL;
2720
2721                 {
2722                         int j;
2723                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2724                         for (j=0; j<64; j++) {
2725                                 if ((j%16) == 0)
2726                                         dprintk("\n%03x:", j);
2727                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2728                         }
2729                         dprintk("\n");
2730                 }
2731                 /* look at what we actually got: */
2732                 if (np->desc_ver == DESC_VER_1) {
2733                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2734                                 len = flags & LEN_MASK_V1;
2735                                 if (unlikely(flags & NV_RX_ERROR)) {
2736                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2737                                                 len = nv_getlen(dev, skb->data, len);
2738                                                 if (len < 0) {
2739                                                         dev->stats.rx_errors++;
2740                                                         dev_kfree_skb(skb);
2741                                                         goto next_pkt;
2742                                                 }
2743                                         }
2744                                         /* framing errors are soft errors */
2745                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2746                                                 if (flags & NV_RX_SUBSTRACT1) {
2747                                                         len--;
2748                                                 }
2749                                         }
2750                                         /* the rest are hard errors */
2751                                         else {
2752                                                 if (flags & NV_RX_MISSEDFRAME)
2753                                                         dev->stats.rx_missed_errors++;
2754                                                 if (flags & NV_RX_CRCERR)
2755                                                         dev->stats.rx_crc_errors++;
2756                                                 if (flags & NV_RX_OVERFLOW)
2757                                                         dev->stats.rx_over_errors++;
2758                                                 dev->stats.rx_errors++;
2759                                                 dev_kfree_skb(skb);
2760                                                 goto next_pkt;
2761                                         }
2762                                 }
2763                         } else {
2764                                 dev_kfree_skb(skb);
2765                                 goto next_pkt;
2766                         }
2767                 } else {
2768                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2769                                 len = flags & LEN_MASK_V2;
2770                                 if (unlikely(flags & NV_RX2_ERROR)) {
2771                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2772                                                 len = nv_getlen(dev, skb->data, len);
2773                                                 if (len < 0) {
2774                                                         dev->stats.rx_errors++;
2775                                                         dev_kfree_skb(skb);
2776                                                         goto next_pkt;
2777                                                 }
2778                                         }
2779                                         /* framing errors are soft errors */
2780                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2781                                                 if (flags & NV_RX2_SUBSTRACT1) {
2782                                                         len--;
2783                                                 }
2784                                         }
2785                                         /* the rest are hard errors */
2786                                         else {
2787                                                 if (flags & NV_RX2_CRCERR)
2788                                                         dev->stats.rx_crc_errors++;
2789                                                 if (flags & NV_RX2_OVERFLOW)
2790                                                         dev->stats.rx_over_errors++;
2791                                                 dev->stats.rx_errors++;
2792                                                 dev_kfree_skb(skb);
2793                                                 goto next_pkt;
2794                                         }
2795                                 }
2796                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2797                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2798                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2799                         } else {
2800                                 dev_kfree_skb(skb);
2801                                 goto next_pkt;
2802                         }
2803                 }
2804                 /* got a valid packet - forward it to the network core */
2805                 skb_put(skb, len);
2806                 skb->protocol = eth_type_trans(skb, dev);
2807                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2808                                         dev->name, len, skb->protocol);
2809 #ifdef CONFIG_FORCEDETH_NAPI
2810                 netif_receive_skb(skb);
2811 #else
2812                 netif_rx(skb);
2813 #endif
2814                 dev->stats.rx_packets++;
2815                 dev->stats.rx_bytes += len;
2816 next_pkt:
2817                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2818                         np->get_rx.orig = np->first_rx.orig;
2819                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2820                         np->get_rx_ctx = np->first_rx_ctx;
2821
2822                 rx_work++;
2823         }
2824
2825         return rx_work;
2826 }
2827
2828 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2829 {
2830         struct fe_priv *np = netdev_priv(dev);
2831         u32 flags;
2832         u32 vlanflags = 0;
2833         int rx_work = 0;
2834         struct sk_buff *skb;
2835         int len;
2836
2837         while((np->get_rx.ex != np->put_rx.ex) &&
2838               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2839               (rx_work < limit)) {
2840
2841                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2842                                         dev->name, flags);
2843
2844                 /*
2845                  * the packet is for us - immediately tear down the pci mapping.
2846                  * TODO: check if a prefetch of the first cacheline improves
2847                  * the performance.
2848                  */
2849                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2850                                 np->get_rx_ctx->dma_len,
2851                                 PCI_DMA_FROMDEVICE);
2852                 skb = np->get_rx_ctx->skb;
2853                 np->get_rx_ctx->skb = NULL;
2854
2855                 {
2856                         int j;
2857                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2858                         for (j=0; j<64; j++) {
2859                                 if ((j%16) == 0)
2860                                         dprintk("\n%03x:", j);
2861                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2862                         }
2863                         dprintk("\n");
2864                 }
2865                 /* look at what we actually got: */
2866                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2867                         len = flags & LEN_MASK_V2;
2868                         if (unlikely(flags & NV_RX2_ERROR)) {
2869                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2870                                         len = nv_getlen(dev, skb->data, len);
2871                                         if (len < 0) {
2872                                                 dev_kfree_skb(skb);
2873                                                 goto next_pkt;
2874                                         }
2875                                 }
2876                                 /* framing errors are soft errors */
2877                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2878                                         if (flags & NV_RX2_SUBSTRACT1) {
2879                                                 len--;
2880                                         }
2881                                 }
2882                                 /* the rest are hard errors */
2883                                 else {
2884                                         dev_kfree_skb(skb);
2885                                         goto next_pkt;
2886                                 }
2887                         }
2888
2889                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2890                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2891                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2892
2893                         /* got a valid packet - forward it to the network core */
2894                         skb_put(skb, len);
2895                         skb->protocol = eth_type_trans(skb, dev);
2896                         prefetch(skb->data);
2897
2898                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2899                                 dev->name, len, skb->protocol);
2900
2901                         if (likely(!np->vlangrp)) {
2902 #ifdef CONFIG_FORCEDETH_NAPI
2903                                 netif_receive_skb(skb);
2904 #else
2905                                 netif_rx(skb);
2906 #endif
2907                         } else {
2908                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2909                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2910 #ifdef CONFIG_FORCEDETH_NAPI
2911                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2912                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2913 #else
2914                                         vlan_hwaccel_rx(skb, np->vlangrp,
2915                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2916 #endif
2917                                 } else {
2918 #ifdef CONFIG_FORCEDETH_NAPI
2919                                         netif_receive_skb(skb);
2920 #else
2921                                         netif_rx(skb);
2922 #endif
2923                                 }
2924                         }
2925
2926                         dev->stats.rx_packets++;
2927                         dev->stats.rx_bytes += len;
2928                 } else {
2929                         dev_kfree_skb(skb);
2930                 }
2931 next_pkt:
2932                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2933                         np->get_rx.ex = np->first_rx.ex;
2934                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2935                         np->get_rx_ctx = np->first_rx_ctx;
2936
2937                 rx_work++;
2938         }
2939
2940         return rx_work;
2941 }
2942
2943 static void set_bufsize(struct net_device *dev)
2944 {
2945         struct fe_priv *np = netdev_priv(dev);
2946
2947         if (dev->mtu <= ETH_DATA_LEN)
2948                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2949         else
2950                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2951 }
2952
2953 /*
2954  * nv_change_mtu: dev->change_mtu function
2955  * Called with dev_base_lock held for read.
2956  */
2957 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2958 {
2959         struct fe_priv *np = netdev_priv(dev);
2960         int old_mtu;
2961
2962         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2963                 return -EINVAL;
2964
2965         old_mtu = dev->mtu;
2966         dev->mtu = new_mtu;
2967
2968         /* return early if the buffer sizes will not change */
2969         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2970                 return 0;
2971         if (old_mtu == new_mtu)
2972                 return 0;
2973
2974         /* synchronized against open : rtnl_lock() held by caller */
2975         if (netif_running(dev)) {
2976                 u8 __iomem *base = get_hwbase(dev);
2977                 /*
2978                  * It seems that the nic preloads valid ring entries into an
2979                  * internal buffer. The procedure for flushing everything is
2980                  * guessed, there is probably a simpler approach.
2981                  * Changing the MTU is a rare event, it shouldn't matter.
2982                  */
2983                 nv_disable_irq(dev);
2984                 nv_napi_disable(dev);
2985                 netif_tx_lock_bh(dev);
2986                 netif_addr_lock(dev);
2987                 spin_lock(&np->lock);
2988                 /* stop engines */
2989                 nv_stop_rxtx(dev);
2990                 nv_txrx_reset(dev);
2991                 /* drain rx queue */
2992                 nv_drain_rxtx(dev);
2993                 /* reinit driver view of the rx queue */
2994                 set_bufsize(dev);
2995                 if (nv_init_ring(dev)) {
2996                         if (!np->in_shutdown)
2997                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2998                 }
2999                 /* reinit nic view of the rx queue */
3000                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3001                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3002                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3003                         base + NvRegRingSizes);
3004                 pci_push(base);
3005                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3006                 pci_push(base);
3007
3008                 /* restart rx engine */
3009                 nv_start_rxtx(dev);
3010                 spin_unlock(&np->lock);
3011                 netif_addr_unlock(dev);
3012                 netif_tx_unlock_bh(dev);
3013                 nv_napi_enable(dev);
3014                 nv_enable_irq(dev);
3015         }
3016         return 0;
3017 }
3018
3019 static void nv_copy_mac_to_hw(struct net_device *dev)
3020 {
3021         u8 __iomem *base = get_hwbase(dev);
3022         u32 mac[2];
3023
3024         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3025                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3026         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3027
3028         writel(mac[0], base + NvRegMacAddrA);
3029         writel(mac[1], base + NvRegMacAddrB);
3030 }
3031
3032 /*
3033  * nv_set_mac_address: dev->set_mac_address function
3034  * Called with rtnl_lock() held.
3035  */
3036 static int nv_set_mac_address(struct net_device *dev, void *addr)
3037 {
3038         struct fe_priv *np = netdev_priv(dev);
3039         struct sockaddr *macaddr = (struct sockaddr*)addr;
3040
3041         if (!is_valid_ether_addr(macaddr->sa_data))
3042                 return -EADDRNOTAVAIL;
3043
3044         /* synchronized against open : rtnl_lock() held by caller */
3045         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3046
3047         if (netif_running(dev)) {
3048                 netif_tx_lock_bh(dev);
3049                 netif_addr_lock(dev);
3050                 spin_lock_irq(&np->lock);
3051
3052                 /* stop rx engine */
3053                 nv_stop_rx(dev);
3054
3055                 /* set mac address */
3056                 nv_copy_mac_to_hw(dev);
3057
3058                 /* restart rx engine */
3059                 nv_start_rx(dev);
3060                 spin_unlock_irq(&np->lock);
3061                 netif_addr_unlock(dev);
3062                 netif_tx_unlock_bh(dev);
3063         } else {
3064                 nv_copy_mac_to_hw(dev);
3065         }
3066         return 0;
3067 }
3068
3069 /*
3070  * nv_set_multicast: dev->set_multicast function
3071  * Called with netif_tx_lock held.
3072  */
3073 static void nv_set_multicast(struct net_device *dev)
3074 {
3075         struct fe_priv *np = netdev_priv(dev);
3076         u8 __iomem *base = get_hwbase(dev);
3077         u32 addr[2];
3078         u32 mask[2];
3079         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3080
3081         memset(addr, 0, sizeof(addr));
3082         memset(mask, 0, sizeof(mask));
3083
3084         if (dev->flags & IFF_PROMISC) {
3085                 pff |= NVREG_PFF_PROMISC;
3086         } else {
3087                 pff |= NVREG_PFF_MYADDR;
3088
3089                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3090                         u32 alwaysOff[2];
3091                         u32 alwaysOn[2];
3092
3093                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3094                         if (dev->flags & IFF_ALLMULTI) {
3095                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3096                         } else {
3097                                 struct dev_mc_list *walk;
3098
3099                                 walk = dev->mc_list;
3100                                 while (walk != NULL) {
3101                                         u32 a, b;
3102                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3103                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3104                                         alwaysOn[0] &= a;
3105                                         alwaysOff[0] &= ~a;
3106                                         alwaysOn[1] &= b;
3107                                         alwaysOff[1] &= ~b;
3108                                         walk = walk->next;
3109                                 }
3110                         }
3111                         addr[0] = alwaysOn[0];
3112                         addr[1] = alwaysOn[1];
3113                         mask[0] = alwaysOn[0] | alwaysOff[0];
3114                         mask[1] = alwaysOn[1] | alwaysOff[1];
3115                 } else {
3116                         mask[0] = NVREG_MCASTMASKA_NONE;
3117                         mask[1] = NVREG_MCASTMASKB_NONE;
3118                 }
3119         }
3120         addr[0] |= NVREG_MCASTADDRA_FORCE;
3121         pff |= NVREG_PFF_ALWAYS;
3122         spin_lock_irq(&np->lock);
3123         nv_stop_rx(dev);
3124         writel(addr[0], base + NvRegMulticastAddrA);
3125         writel(addr[1], base + NvRegMulticastAddrB);
3126         writel(mask[0], base + NvRegMulticastMaskA);
3127         writel(mask[1], base + NvRegMulticastMaskB);
3128         writel(pff, base + NvRegPacketFilterFlags);
3129         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3130                 dev->name);
3131         nv_start_rx(dev);
3132         spin_unlock_irq(&np->lock);
3133 }
3134
3135 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3136 {
3137         struct fe_priv *np = netdev_priv(dev);
3138         u8 __iomem *base = get_hwbase(dev);
3139
3140         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3141
3142         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3143                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3144                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3145                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3146                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3147                 } else {
3148                         writel(pff, base + NvRegPacketFilterFlags);
3149                 }
3150         }
3151         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3152                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3153                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3154                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3155                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3156                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3157                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3158                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3159                                 /* limit the number of tx pause frames to a default of 8 */
3160                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3161                         }
3162                         writel(pause_enable,  base + NvRegTxPauseFrame);
3163                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3164                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3165                 } else {
3166                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3167                         writel(regmisc, base + NvRegMisc1);
3168                 }
3169         }
3170 }
3171
3172 /**
3173  * nv_update_linkspeed: Setup the MAC according to the link partner
3174  * @dev: Network device to be configured
3175  *
3176  * The function queries the PHY and checks if there is a link partner.
3177  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3178  * set to 10 MBit HD.
3179  *
3180  * The function returns 0 if there is no link partner and 1 if there is
3181  * a good link partner.
3182  */
3183 static int nv_update_linkspeed(struct net_device *dev)
3184 {
3185         struct fe_priv *np = netdev_priv(dev);
3186         u8 __iomem *base = get_hwbase(dev);
3187         int adv = 0;
3188         int lpa = 0;
3189         int adv_lpa, adv_pause, lpa_pause;
3190         int newls = np->linkspeed;
3191         int newdup = np->duplex;
3192         int mii_status;
3193         int retval = 0;
3194         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3195         u32 txrxFlags = 0;
3196         u32 phy_exp;
3197
3198         /* BMSR_LSTATUS is latched, read it twice:
3199          * we want the current value.
3200          */
3201         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3202         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3203
3204         if (!(mii_status & BMSR_LSTATUS)) {
3205                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3206                                 dev->name);
3207                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3208                 newdup = 0;
3209                 retval = 0;
3210                 goto set_speed;
3211         }
3212
3213         if (np->autoneg == 0) {
3214                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3215                                 dev->name, np->fixed_mode);
3216                 if (np->fixed_mode & LPA_100FULL) {
3217                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3218                         newdup = 1;
3219                 } else if (np->fixed_mode & LPA_100HALF) {
3220                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3221                         newdup = 0;
3222                 } else if (np->fixed_mode & LPA_10FULL) {
3223                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3224                         newdup = 1;
3225                 } else {
3226                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3227                         newdup = 0;
3228                 }
3229                 retval = 1;
3230                 goto set_speed;
3231         }
3232         /* check auto negotiation is complete */
3233         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3234                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3235                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3236                 newdup = 0;
3237                 retval = 0;
3238                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3239                 goto set_speed;
3240         }
3241
3242         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3243         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3244         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3245                                 dev->name, adv, lpa);
3246
3247         retval = 1;
3248         if (np->gigabit == PHY_GIGABIT) {
3249                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3250                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3251
3252                 if ((control_1000 & ADVERTISE_1000FULL) &&
3253                         (status_1000 & LPA_1000FULL)) {
3254                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3255                                 dev->name);
3256                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3257                         newdup = 1;
3258                         goto set_speed;
3259                 }
3260         }
3261
3262         /* FIXME: handle parallel detection properly */
3263         adv_lpa = lpa & adv;
3264         if (adv_lpa & LPA_100FULL) {
3265                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3266                 newdup = 1;
3267         } else if (adv_lpa & LPA_100HALF) {
3268                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3269                 newdup = 0;
3270         } else if (adv_lpa & LPA_10FULL) {
3271                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3272                 newdup = 1;
3273         } else if (adv_lpa & LPA_10HALF) {
3274                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3275                 newdup = 0;
3276         } else {
3277                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3278                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3279                 newdup = 0;
3280         }
3281
3282 set_speed:
3283         if (np->duplex == newdup && np->linkspeed == newls)
3284                 return retval;
3285
3286         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3287                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3288
3289         np->duplex = newdup;
3290         np->linkspeed = newls;
3291
3292         /* The transmitter and receiver must be restarted for safe update */
3293         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3294                 txrxFlags |= NV_RESTART_TX;
3295                 nv_stop_tx(dev);
3296         }
3297         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3298                 txrxFlags |= NV_RESTART_RX;
3299                 nv_stop_rx(dev);
3300         }
3301
3302         if (np->gigabit == PHY_GIGABIT) {
3303                 phyreg = readl(base + NvRegSlotTime);
3304                 phyreg &= ~(0x3FF00);
3305                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3306                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3307                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3308                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3309                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3310                 writel(phyreg, base + NvRegSlotTime);
3311         }
3312
3313         phyreg = readl(base + NvRegPhyInterface);
3314         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3315         if (np->duplex == 0)
3316                 phyreg |= PHY_HALF;
3317         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3318                 phyreg |= PHY_100;
3319         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3320                 phyreg |= PHY_1000;
3321         writel(phyreg, base + NvRegPhyInterface);
3322
3323         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3324         if (phyreg & PHY_RGMII) {
3325                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3326                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3327                 } else {
3328                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3329                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3330                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3331                                 else
3332                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3333                         } else {
3334                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3335                         }
3336                 }
3337         } else {
3338                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3339                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3340                 else
3341                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3342         }
3343         writel(txreg, base + NvRegTxDeferral);
3344
3345         if (np->desc_ver == DESC_VER_1) {
3346                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3347         } else {
3348                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3349                         txreg = NVREG_TX_WM_DESC2_3_1000;
3350                 else
3351                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3352         }
3353         writel(txreg, base + NvRegTxWatermark);
3354
3355         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3356                 base + NvRegMisc1);
3357         pci_push(base);
3358         writel(np->linkspeed, base + NvRegLinkSpeed);
3359         pci_push(base);
3360
3361         pause_flags = 0;
3362         /* setup pause frame */
3363         if (np->duplex != 0) {
3364                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3365                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3366                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3367
3368                         switch (adv_pause) {
3369                         case ADVERTISE_PAUSE_CAP:
3370                                 if (lpa_pause & LPA_PAUSE_CAP) {
3371                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3372                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3373                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3374                                 }
3375                                 break;
3376                         case ADVERTISE_PAUSE_ASYM:
3377                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3378                                 {
3379                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3380                                 }
3381                                 break;
3382                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3383                                 if (lpa_pause & LPA_PAUSE_CAP)
3384                                 {
3385                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3386                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3387                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3388                                 }
3389                                 if (lpa_pause == LPA_PAUSE_ASYM)
3390                                 {
3391                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3392                                 }
3393                                 break;
3394                         }
3395                 } else {
3396                         pause_flags = np->pause_flags;
3397                 }
3398         }
3399         nv_update_pause(dev, pause_flags);
3400
3401         if (txrxFlags & NV_RESTART_TX)
3402                 nv_start_tx(dev);
3403         if (txrxFlags & NV_RESTART_RX)
3404                 nv_start_rx(dev);
3405
3406         return retval;
3407 }
3408
3409 static void nv_linkchange(struct net_device *dev)
3410 {
3411         if (nv_update_linkspeed(dev)) {
3412                 if (!netif_carrier_ok(dev)) {
3413                         netif_carrier_on(dev);
3414                         printk(KERN_INFO "%s: link up.\n", dev->name);
3415                         nv_txrx_gate(dev, false);
3416                         nv_start_rx(dev);
3417                 }
3418         } else {
3419                 if (netif_carrier_ok(dev)) {
3420                         netif_carrier_off(dev);
3421                         printk(KERN_INFO "%s: link down.\n", dev->name);
3422                         nv_txrx_gate(dev, true);
3423                         nv_stop_rx(dev);
3424                 }
3425         }
3426 }
3427
3428 static void nv_link_irq(struct net_device *dev)
3429 {
3430         u8 __iomem *base = get_hwbase(dev);
3431         u32 miistat;
3432
3433         miistat = readl(base + NvRegMIIStatus);
3434         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3435         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3436
3437         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3438                 nv_linkchange(dev);
3439         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3440 }
3441
3442 static void nv_msi_workaround(struct fe_priv *np)
3443 {
3444
3445         /* Need to toggle the msi irq mask within the ethernet device,
3446          * otherwise, future interrupts will not be detected.
3447          */
3448         if (np->msi_flags & NV_MSI_ENABLED) {
3449                 u8 __iomem *base = np->base;
3450
3451                 writel(0, base + NvRegMSIIrqMask);
3452                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3453         }
3454 }
3455
3456 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3457 {
3458         struct fe_priv *np = netdev_priv(dev);
3459
3460         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3461                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3462                         /* transition to poll based interrupts */
3463                         np->quiet_count = 0;
3464                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3465                                 np->irqmask = NVREG_IRQMASK_CPU;
3466                                 return 1;
3467                         }
3468                 } else {
3469                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3470                                 np->quiet_count++;
3471                         } else {
3472                                 /* reached a period of low activity, switch
3473                                    to per tx/rx packet interrupts */
3474                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3475                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3476                                         return 1;
3477                                 }
3478                         }
3479                 }
3480         }
3481         return 0;
3482 }
3483
3484 static irqreturn_t nv_nic_irq(int foo, void *data)
3485 {
3486         struct net_device *dev = (struct net_device *) data;
3487         struct fe_priv *np = netdev_priv(dev);
3488         u8 __iomem *base = get_hwbase(dev);
3489 #ifndef CONFIG_FORCEDETH_NAPI
3490         int total_work = 0;
3491         int loop_count = 0;
3492 #endif
3493
3494         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3495
3496         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3497                 np->events = readl(base + NvRegIrqStatus);
3498                 writel(np->events, base + NvRegIrqStatus);
3499         } else {
3500                 np->events = readl(base + NvRegMSIXIrqStatus);
3501                 writel(np->events, base + NvRegMSIXIrqStatus);
3502         }
3503         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3504         if (!(np->events & np->irqmask))
3505                 return IRQ_NONE;
3506
3507         nv_msi_workaround(np);
3508
3509 #ifdef CONFIG_FORCEDETH_NAPI
3510         napi_schedule(&np->napi);
3511
3512         /* Disable furthur irq's
3513            (msix not enabled with napi) */
3514         writel(0, base + NvRegIrqMask);
3515
3516 #else
3517         do
3518         {
3519                 int work = 0;
3520                 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3521                         if (unlikely(nv_alloc_rx(dev))) {
3522                                 spin_lock(&np->lock);
3523                                 if (!np->in_shutdown)
3524                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3525                                 spin_unlock(&np->lock);
3526                         }
3527                 }
3528
3529                 spin_lock(&np->lock);
3530                 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3531                 spin_unlock(&np->lock);
3532
3533                 if (!work)
3534                         break;
3535
3536                 total_work += work;
3537
3538                 loop_count++;
3539         }
3540         while (loop_count < max_interrupt_work);
3541
3542         if (nv_change_interrupt_mode(dev, total_work)) {
3543                 /* setup new irq mask */
3544                 writel(np->irqmask, base + NvRegIrqMask);
3545         }
3546
3547         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3548                 spin_lock(&np->lock);
3549                 nv_link_irq(dev);
3550                 spin_unlock(&np->lock);
3551         }
3552         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3553                 spin_lock(&np->lock);
3554                 nv_linkchange(dev);
3555                 spin_unlock(&np->lock);
3556                 np->link_timeout = jiffies + LINK_TIMEOUT;
3557         }
3558         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3559                 spin_lock(&np->lock);
3560                 /* disable interrupts on the nic */
3561                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3562                         writel(0, base + NvRegIrqMask);
3563                 else
3564                         writel(np->irqmask, base + NvRegIrqMask);
3565                 pci_push(base);
3566
3567                 if (!np->in_shutdown) {
3568                         np->nic_poll_irq = np->irqmask;
3569                         np->recover_error = 1;
3570                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3571                 }
3572                 spin_unlock(&np->lock);
3573         }
3574 #endif
3575         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3576
3577         return IRQ_HANDLED;
3578 }
3579
3580 /**
3581  * All _optimized functions are used to help increase performance
3582  * (reduce CPU and increase throughput). They use descripter version 3,
3583  * compiler directives, and reduce memory accesses.
3584  */
3585 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3586 {
3587         struct net_device *dev = (struct net_device *) data;
3588         struct fe_priv *np = netdev_priv(dev);
3589         u8 __iomem *base = get_hwbase(dev);
3590 #ifndef CONFIG_FORCEDETH_NAPI
3591         int total_work = 0;
3592         int loop_count = 0;
3593 #endif
3594
3595         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3596
3597         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3598                 np->events = readl(base + NvRegIrqStatus);
3599                 writel(np->events, base + NvRegIrqStatus);
3600         } else {
3601                 np->events = readl(base + NvRegMSIXIrqStatus);
3602                 writel(np->events, base + NvRegMSIXIrqStatus);
3603         }
3604         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3605         if (!(np->events & np->irqmask))
3606                 return IRQ_NONE;
3607
3608         nv_msi_workaround(np);
3609
3610 #ifdef CONFIG_FORCEDETH_NAPI
3611         napi_schedule(&np->napi);
3612
3613         /* Disable furthur irq's
3614            (msix not enabled with napi) */
3615         writel(0, base + NvRegIrqMask);
3616
3617 #else
3618         do
3619         {
3620                 int work = 0;
3621                 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3622                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3623                                 spin_lock(&np->lock);
3624                                 if (!np->in_shutdown)
3625                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3626                                 spin_unlock(&np->lock);
3627                         }
3628                 }
3629
3630                 spin_lock(&np->lock);
3631                 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3632                 spin_unlock(&np->lock);
3633
3634                 if (!work)
3635                         break;
3636
3637                 total_work += work;
3638
3639                 loop_count++;
3640         }
3641         while (loop_count < max_interrupt_work);
3642
3643         if (nv_change_interrupt_mode(dev, total_work)) {
3644                 /* setup new irq mask */
3645                 writel(np->irqmask, base + NvRegIrqMask);
3646         }
3647
3648         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3649                 spin_lock(&np->lock);
3650                 nv_link_irq(dev);
3651                 spin_unlock(&np->lock);
3652         }
3653         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3654                 spin_lock(&np->lock);
3655                 nv_linkchange(dev);
3656                 spin_unlock(&np->lock);
3657                 np->link_timeout = jiffies + LINK_TIMEOUT;
3658         }
3659         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3660                 spin_lock(&np->lock);
3661                 /* disable interrupts on the nic */
3662                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3663                         writel(0, base + NvRegIrqMask);
3664                 else
3665                         writel(np->irqmask, base + NvRegIrqMask);
3666                 pci_push(base);
3667
3668                 if (!np->in_shutdown) {
3669                         np->nic_poll_irq = np->irqmask;
3670                         np->recover_error = 1;
3671                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3672                 }
3673                 spin_unlock(&np->lock);
3674         }
3675
3676 #endif
3677         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3678
3679         return IRQ_HANDLED;
3680 }
3681
3682 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3683 {
3684         struct net_device *dev = (struct net_device *) data;
3685         struct fe_priv *np = netdev_priv(dev);
3686         u8 __iomem *base = get_hwbase(dev);
3687         u32 events;
3688         int i;
3689         unsigned long flags;
3690
3691         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3692
3693         for (i=0; ; i++) {
3694                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3695                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3696                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3697                 if (!(events & np->irqmask))
3698                         break;
3699
3700                 spin_lock_irqsave(&np->lock, flags);
3701                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3702                 spin_unlock_irqrestore(&np->lock, flags);
3703
3704                 if (unlikely(i > max_interrupt_work)) {
3705                         spin_lock_irqsave(&np->lock, flags);
3706                         /* disable interrupts on the nic */
3707                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3708                         pci_push(base);
3709
3710                         if (!np->in_shutdown) {
3711                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3712                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3713                         }
3714                         spin_unlock_irqrestore(&np->lock, flags);
3715                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3716                         break;
3717                 }
3718
3719         }
3720         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3721
3722         return IRQ_RETVAL(i);
3723 }
3724
3725 #ifdef CONFIG_FORCEDETH_NAPI
3726 static int nv_napi_poll(struct napi_struct *napi, int budget)
3727 {
3728         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3729         struct net_device *dev = np->dev;
3730         u8 __iomem *base = get_hwbase(dev);
3731         unsigned long flags;
3732         int retcode;
3733         int tx_work, rx_work;
3734
3735         if (!nv_optimized(np)) {
3736                 spin_lock_irqsave(&np->lock, flags);
3737                 tx_work = nv_tx_done(dev, np->tx_ring_size);
3738                 spin_unlock_irqrestore(&np->lock, flags);
3739
3740                 rx_work = nv_rx_process(dev, budget);
3741                 retcode = nv_alloc_rx(dev);
3742         } else {
3743                 spin_lock_irqsave(&np->lock, flags);
3744                 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3745                 spin_unlock_irqrestore(&np->lock, flags);
3746
3747                 rx_work = nv_rx_process_optimized(dev, budget);
3748                 retcode = nv_alloc_rx_optimized(dev);
3749         }
3750
3751         if (retcode) {
3752                 spin_lock_irqsave(&np->lock, flags);
3753                 if (!np->in_shutdown)
3754                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3755                 spin_unlock_irqrestore(&np->lock, flags);
3756         }
3757
3758         nv_change_interrupt_mode(dev, tx_work + rx_work);
3759
3760         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3761                 spin_lock_irqsave(&np->lock, flags);
3762                 nv_link_irq(dev);
3763                 spin_unlock_irqrestore(&np->lock, flags);
3764         }
3765         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3766                 spin_lock_irqsave(&np->lock, flags);
3767                 nv_linkchange(dev);
3768                 spin_unlock_irqrestore(&np->lock, flags);
3769                 np->link_timeout = jiffies + LINK_TIMEOUT;
3770         }
3771         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3772                 spin_lock_irqsave(&np->lock, flags);
3773                 if (!np->in_shutdown) {
3774                         np->nic_poll_irq = np->irqmask;
3775                         np->recover_error = 1;
3776                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3777                 }
3778                 spin_unlock_irqrestore(&np->lock, flags);
3779                 napi_complete(napi);
3780                 return rx_work;
3781         }
3782
3783         if (rx_work < budget) {
3784                 /* re-enable interrupts
3785                    (msix not enabled in napi) */
3786                 napi_complete(napi);
3787
3788                 writel(np->irqmask, base + NvRegIrqMask);
3789         }
3790         return rx_work;
3791 }
3792 #endif
3793
3794 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3795 {
3796         struct net_device *dev = (struct net_device *) data;
3797         struct fe_priv *np = netdev_priv(dev);
3798         u8 __iomem *base = get_hwbase(dev);
3799         u32 events;
3800         int i;
3801         unsigned long flags;
3802
3803         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3804
3805         for (i=0; ; i++) {
3806                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3807                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3808                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3809                 if (!(events & np->irqmask))
3810                         break;
3811
3812                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3813                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3814                                 spin_lock_irqsave(&np->lock, flags);
3815                                 if (!np->in_shutdown)
3816                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3817                                 spin_unlock_irqrestore(&np->lock, flags);
3818                         }
3819                 }
3820
3821                 if (unlikely(i > max_interrupt_work)) {
3822                         spin_lock_irqsave(&np->lock, flags);
3823                         /* disable interrupts on the nic */
3824                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3825                         pci_push(base);
3826
3827                         if (!np->in_shutdown) {
3828                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3829                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3830                         }
3831                         spin_unlock_irqrestore(&np->lock, flags);
3832                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3833                         break;
3834                 }
3835         }
3836         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3837
3838         return IRQ_RETVAL(i);
3839 }
3840
3841 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3842 {
3843         struct net_device *dev = (struct net_device *) data;
3844         struct fe_priv *np = netdev_priv(dev);
3845         u8 __iomem *base = get_hwbase(dev);
3846         u32 events;
3847         int i;
3848         unsigned long flags;
3849
3850         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3851
3852         for (i=0; ; i++) {
3853                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3854                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3855                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3856                 if (!(events & np->irqmask))
3857                         break;
3858
3859                 /* check tx in case we reached max loop limit in tx isr */
3860                 spin_lock_irqsave(&np->lock, flags);
3861                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3862                 spin_unlock_irqrestore(&np->lock, flags);
3863
3864                 if (events & NVREG_IRQ_LINK) {
3865                         spin_lock_irqsave(&np->lock, flags);
3866                         nv_link_irq(dev);
3867                         spin_unlock_irqrestore(&np->lock, flags);
3868                 }
3869                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3870                         spin_lock_irqsave(&np->lock, flags);
3871                         nv_linkchange(dev);
3872                         spin_unlock_irqrestore(&np->lock, flags);
3873                         np->link_timeout = jiffies + LINK_TIMEOUT;
3874                 }
3875                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3876                         spin_lock_irq(&np->lock);
3877                         /* disable interrupts on the nic */
3878                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3879                         pci_push(base);
3880
3881                         if (!np->in_shutdown) {
3882                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3883                                 np->recover_error = 1;
3884                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3885                         }
3886                         spin_unlock_irq(&np->lock);
3887                         break;
3888                 }
3889                 if (unlikely(i > max_interrupt_work)) {
3890                         spin_lock_irqsave(&np->lock, flags);
3891                         /* disable interrupts on the nic */
3892                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3893                         pci_push(base);
3894
3895                         if (!np->in_shutdown) {
3896                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3897                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3898                         }
3899                         spin_unlock_irqrestore(&np->lock, flags);
3900                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3901                         break;
3902                 }
3903
3904         }
3905         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3906
3907         return IRQ_RETVAL(i);
3908 }
3909
3910 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3911 {
3912         struct net_device *dev = (struct net_device *) data;
3913         struct fe_priv *np = netdev_priv(dev);
3914         u8 __iomem *base = get_hwbase(dev);
3915         u32 events;
3916
3917         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3918
3919         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3920                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3921                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3922         } else {
3923                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3924                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3925         }
3926         pci_push(base);
3927         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3928         if (!(events & NVREG_IRQ_TIMER))
3929                 return IRQ_RETVAL(0);
3930
3931         nv_msi_workaround(np);
3932
3933         spin_lock(&np->lock);
3934         np->intr_test = 1;
3935         spin_unlock(&np->lock);
3936
3937         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3938
3939         return IRQ_RETVAL(1);
3940 }
3941
3942 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3943 {
3944         u8 __iomem *base = get_hwbase(dev);
3945         int i;
3946         u32 msixmap = 0;
3947
3948         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3949          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3950          * the remaining 8 interrupts.
3951          */
3952         for (i = 0; i < 8; i++) {
3953                 if ((irqmask >> i) & 0x1) {
3954                         msixmap |= vector << (i << 2);
3955                 }
3956         }
3957         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3958
3959         msixmap = 0;
3960         for (i = 0; i < 8; i++) {
3961                 if ((irqmask >> (i + 8)) & 0x1) {
3962                         msixmap |= vector << (i << 2);
3963                 }
3964         }
3965         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3966 }
3967
3968 static int nv_request_irq(struct net_device *dev, int intr_test)
3969 {
3970         struct fe_priv *np = get_nvpriv(dev);
3971         u8 __iomem *base = get_hwbase(dev);
3972         int ret = 1;
3973         int i;
3974         irqreturn_t (*handler)(int foo, void *data);
3975
3976         if (intr_test) {
3977                 handler = nv_nic_irq_test;
3978         } else {
3979                 if (nv_optimized(np))
3980                         handler = nv_nic_irq_optimized;
3981                 else
3982                         handler = nv_nic_irq;
3983         }
3984
3985         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3986                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3987                         np->msi_x_entry[i].entry = i;
3988                 }
3989                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3990                         np->msi_flags |= NV_MSI_X_ENABLED;
3991                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3992                                 /* Request irq for rx handling */
3993                                 sprintf(np->name_rx, "%s-rx", dev->name);
3994                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3995                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3996                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3997                                         pci_disable_msix(np->pci_dev);
3998                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3999                                         goto out_err;
4000                                 }
4001                                 /* Request irq for tx handling */
4002                                 sprintf(np->name_tx, "%s-tx", dev->name);
4003                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4004                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
4005                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4006                                         pci_disable_msix(np->pci_dev);
4007                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4008                                         goto out_free_rx;
4009                                 }
4010                                 /* Request irq for link and timer handling */
4011                                 sprintf(np->name_other, "%s-other", dev->name);
4012                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4013                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4014                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4015                                         pci_disable_msix(np->pci_dev);
4016                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4017                                         goto out_free_tx;
4018                                 }
4019                                 /* map interrupts to their respective vector */
4020                                 writel(0, base + NvRegMSIXMap0);
4021                                 writel(0, base + NvRegMSIXMap1);
4022                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4023                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4024                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4025                         } else {
4026                                 /* Request irq for all interrupts */
4027                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4028                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4029                                         pci_disable_msix(np->pci_dev);
4030                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4031                                         goto out_err;
4032                                 }
4033
4034                                 /* map interrupts to vector 0 */
4035                                 writel(0, base + NvRegMSIXMap0);
4036                                 writel(0, base + NvRegMSIXMap1);
4037                         }
4038                 }
4039         }
4040         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4041                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4042                         np->msi_flags |= NV_MSI_ENABLED;
4043                         dev->irq = np->pci_dev->irq;
4044                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4045                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4046                                 pci_disable_msi(np->pci_dev);
4047                                 np->msi_flags &= ~NV_MSI_ENABLED;
4048                                 dev->irq = np->pci_dev->irq;
4049                                 goto out_err;
4050                         }
4051
4052                         /* map interrupts to vector 0 */
4053                         writel(0, base + NvRegMSIMap0);
4054                         writel(0, base + NvRegMSIMap1);
4055                         /* enable msi vector 0 */
4056                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4057                 }
4058         }
4059         if (ret != 0) {
4060                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4061                         goto out_err;
4062
4063         }
4064
4065         return 0;
4066 out_free_tx:
4067         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4068 out_free_rx:
4069         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4070 out_err:
4071         return 1;
4072 }
4073
4074 static void nv_free_irq(struct net_device *dev)
4075 {
4076         struct fe_priv *np = get_nvpriv(dev);
4077         int i;
4078
4079         if (np->msi_flags & NV_MSI_X_ENABLED) {
4080                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4081                         free_irq(np->msi_x_entry[i].vector, dev);
4082                 }
4083                 pci_disable_msix(np->pci_dev);
4084                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4085         } else {
4086                 free_irq(np->pci_dev->irq, dev);
4087                 if (np->msi_flags & NV_MSI_ENABLED) {
4088                         pci_disable_msi(np->pci_dev);
4089                         np->msi_flags &= ~NV_MSI_ENABLED;
4090                 }
4091         }
4092 }
4093
4094 static void nv_do_nic_poll(unsigned long data)
4095 {
4096         struct net_device *dev = (struct net_device *) data;
4097         struct fe_priv *np = netdev_priv(dev);
4098         u8 __iomem *base = get_hwbase(dev);
4099         u32 mask = 0;
4100
4101         /*
4102          * First disable irq(s) and then
4103          * reenable interrupts on the nic, we have to do this before calling
4104          * nv_nic_irq because that may decide to do otherwise
4105          */
4106
4107         if (!using_multi_irqs(dev)) {
4108                 if (np->msi_flags & NV_MSI_X_ENABLED)
4109                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4110                 else
4111                         disable_irq_lockdep(np->pci_dev->irq);
4112                 mask = np->irqmask;
4113         } else {
4114                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4115                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4116                         mask |= NVREG_IRQ_RX_ALL;
4117                 }
4118                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4119                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4120                         mask |= NVREG_IRQ_TX_ALL;
4121                 }
4122                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4123                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4124                         mask |= NVREG_IRQ_OTHER;
4125                 }
4126         }
4127         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4128
4129         if (np->recover_error) {
4130                 np->recover_error = 0;
4131                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4132                 if (netif_running(dev)) {
4133                         netif_tx_lock_bh(dev);
4134                         netif_addr_lock(dev);
4135                         spin_lock(&np->lock);
4136                         /* stop engines */
4137                         nv_stop_rxtx(dev);
4138                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4139                                 nv_mac_reset(dev);
4140                         nv_txrx_reset(dev);
4141                         /* drain rx queue */
4142                         nv_drain_rxtx(dev);
4143                         /* reinit driver view of the rx queue */
4144                         set_bufsize(dev);
4145                         if (nv_init_ring(dev)) {
4146                                 if (!np->in_shutdown)
4147                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4148                         }
4149                         /* reinit nic view of the rx queue */
4150                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4151                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4152                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4153                                 base + NvRegRingSizes);
4154                         pci_push(base);
4155                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4156                         pci_push(base);
4157                         /* clear interrupts */
4158                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4159                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4160                         else
4161                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4162
4163                         /* restart rx engine */
4164                         nv_start_rxtx(dev);
4165                         spin_unlock(&np->lock);
4166                         netif_addr_unlock(dev);
4167                         netif_tx_unlock_bh(dev);
4168                 }
4169         }
4170
4171         writel(mask, base + NvRegIrqMask);
4172         pci_push(base);
4173
4174         if (!using_multi_irqs(dev)) {
4175                 np->nic_poll_irq = 0;
4176                 if (nv_optimized(np))
4177                         nv_nic_irq_optimized(0, dev);
4178                 else
4179                         nv_nic_irq(0, dev);
4180                 if (np->msi_flags & NV_MSI_X_ENABLED)
4181                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4182                 else
4183                         enable_irq_lockdep(np->pci_dev->irq);
4184         } else {
4185                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4186                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4187                         nv_nic_irq_rx(0, dev);
4188                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4189                 }
4190                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4191                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4192                         nv_nic_irq_tx(0, dev);
4193                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4194                 }
4195                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4196                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4197                         nv_nic_irq_other(0, dev);
4198                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4199                 }
4200         }
4201
4202 }
4203
4204 #ifdef CONFIG_NET_POLL_CONTROLLER
4205 static void nv_poll_controller(struct net_device *dev)
4206 {
4207         nv_do_nic_poll((unsigned long) dev);
4208 }
4209 #endif
4210
4211 static void nv_do_stats_poll(unsigned long data)
4212 {
4213         struct net_device *dev = (struct net_device *) data;
4214         struct fe_priv *np = netdev_priv(dev);
4215
4216         nv_get_hw_stats(dev);
4217
4218         if (!np->in_shutdown)
4219                 mod_timer(&np->stats_poll,
4220                         round_jiffies(jiffies + STATS_INTERVAL));
4221 }
4222
4223 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4224 {
4225         struct fe_priv *np = netdev_priv(dev);
4226         strcpy(info->driver, DRV_NAME);
4227         strcpy(info->version, FORCEDETH_VERSION);
4228         strcpy(info->bus_info, pci_name(np->pci_dev));
4229 }
4230
4231 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4232 {
4233         struct fe_priv *np = netdev_priv(dev);
4234         wolinfo->supported = WAKE_MAGIC;
4235
4236         spin_lock_irq(&np->lock);
4237         if (np->wolenabled)
4238                 wolinfo->wolopts = WAKE_MAGIC;
4239         spin_unlock_irq(&np->lock);
4240 }
4241
4242 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4243 {
4244         struct fe_priv *np = netdev_priv(dev);
4245         u8 __iomem *base = get_hwbase(dev);
4246         u32 flags = 0;
4247
4248         if (wolinfo->wolopts == 0) {
4249                 np->wolenabled = 0;
4250         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4251                 np->wolenabled = 1;
4252                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4253         }
4254         if (netif_running(dev)) {
4255                 spin_lock_irq(&np->lock);
4256                 writel(flags, base + NvRegWakeUpFlags);
4257                 spin_unlock_irq(&np->lock);
4258         }
4259         return 0;
4260 }
4261
4262 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4263 {
4264         struct fe_priv *np = netdev_priv(dev);
4265         int adv;
4266
4267         spin_lock_irq(&np->lock);
4268         ecmd->port = PORT_MII;
4269         if (!netif_running(dev)) {
4270                 /* We do not track link speed / duplex setting if the
4271                  * interface is disabled. Force a link check */
4272                 if (nv_update_linkspeed(dev)) {
4273                         if (!netif_carrier_ok(dev))
4274                                 netif_carrier_on(dev);
4275                 } else {
4276                         if (netif_carrier_ok(dev))
4277                                 netif_carrier_off(dev);
4278                 }
4279         }
4280
4281         if (netif_carrier_ok(dev)) {
4282                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4283                 case NVREG_LINKSPEED_10:
4284                         ecmd->speed = SPEED_10;
4285                         break;
4286                 case NVREG_LINKSPEED_100:
4287                         ecmd->speed = SPEED_100;
4288                         break;
4289                 case NVREG_LINKSPEED_1000:
4290                         ecmd->speed = SPEED_1000;
4291                         break;
4292                 }
4293                 ecmd->duplex = DUPLEX_HALF;
4294                 if (np->duplex)
4295                         ecmd->duplex = DUPLEX_FULL;
4296         } else {
4297                 ecmd->speed = -1;
4298                 ecmd->duplex = -1;
4299         }
4300
4301         ecmd->autoneg = np->autoneg;
4302
4303         ecmd->advertising = ADVERTISED_MII;
4304         if (np->autoneg) {
4305                 ecmd->advertising |= ADVERTISED_Autoneg;
4306                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4307                 if (adv & ADVERTISE_10HALF)
4308                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4309                 if (adv & ADVERTISE_10FULL)
4310                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4311                 if (adv & ADVERTISE_100HALF)
4312                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4313                 if (adv & ADVERTISE_100FULL)
4314                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4315                 if (np->gigabit == PHY_GIGABIT) {
4316                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4317                         if (adv & ADVERTISE_1000FULL)
4318                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4319                 }
4320         }
4321         ecmd->supported = (SUPPORTED_Autoneg |
4322                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4323                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4324                 SUPPORTED_MII);
4325         if (np->gigabit == PHY_GIGABIT)
4326                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4327
4328         ecmd->phy_address = np->phyaddr;
4329         ecmd->transceiver = XCVR_EXTERNAL;
4330
4331         /* ignore maxtxpkt, maxrxpkt for now */
4332         spin_unlock_irq(&np->lock);
4333         return 0;
4334 }
4335
4336 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4337 {
4338         struct fe_priv *np = netdev_priv(dev);
4339
4340         if (ecmd->port != PORT_MII)
4341                 return -EINVAL;
4342         if (ecmd->transceiver != XCVR_EXTERNAL)
4343                 return -EINVAL;
4344         if (ecmd->phy_address != np->phyaddr) {
4345                 /* TODO: support switching between multiple phys. Should be
4346                  * trivial, but not enabled due to lack of test hardware. */
4347                 return -EINVAL;
4348         }
4349         if (ecmd->autoneg == AUTONEG_ENABLE) {
4350                 u32 mask;
4351
4352                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4353                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4354                 if (np->gigabit == PHY_GIGABIT)
4355                         mask |= ADVERTISED_1000baseT_Full;
4356
4357                 if ((ecmd->advertising & mask) == 0)
4358                         return -EINVAL;
4359
4360         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4361                 /* Note: autonegotiation disable, speed 1000 intentionally
4362                  * forbidden - noone should need that. */
4363
4364                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4365                         return -EINVAL;
4366                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4367                         return -EINVAL;
4368         } else {
4369                 return -EINVAL;
4370         }
4371
4372         netif_carrier_off(dev);
4373         if (netif_running(dev)) {
4374                 unsigned long flags;
4375
4376                 nv_disable_irq(dev);
4377                 netif_tx_lock_bh(dev);
4378                 netif_addr_lock(dev);
4379                 /* with plain spinlock lockdep complains */
4380                 spin_lock_irqsave(&np->lock, flags);
4381                 /* stop engines */
4382                 /* FIXME:
4383                  * this can take some time, and interrupts are disabled
4384                  * due to spin_lock_irqsave, but let's hope no daemon
4385                  * is going to change the settings very often...
4386                  * Worst case:
4387                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4388                  * + some minor delays, which is up to a second approximately
4389                  */
4390                 nv_stop_rxtx(dev);
4391                 spin_unlock_irqrestore(&np->lock, flags);
4392                 netif_addr_unlock(dev);
4393                 netif_tx_unlock_bh(dev);
4394         }
4395
4396         if (ecmd->autoneg == AUTONEG_ENABLE) {
4397                 int adv, bmcr;
4398
4399                 np->autoneg = 1;
4400
4401                 /* advertise only what has been requested */
4402                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4403                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4404                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4405                         adv |= ADVERTISE_10HALF;
4406                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4407                         adv |= ADVERTISE_10FULL;
4408                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4409                         adv |= ADVERTISE_100HALF;
4410                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4411                         adv |= ADVERTISE_100FULL;
4412                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4413                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4414                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4415                         adv |=  ADVERTISE_PAUSE_ASYM;
4416                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4417
4418                 if (np->gigabit == PHY_GIGABIT) {
4419                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4420                         adv &= ~ADVERTISE_1000FULL;
4421                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4422                                 adv |= ADVERTISE_1000FULL;
4423                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4424                 }
4425
4426                 if (netif_running(dev))
4427                         printk(KERN_INFO "%s: link down.\n", dev->name);
4428                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4429                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4430                         bmcr |= BMCR_ANENABLE;
4431                         /* reset the phy in order for settings to stick,
4432                          * and cause autoneg to start */
4433                         if (phy_reset(dev, bmcr)) {
4434                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4435                                 return -EINVAL;
4436                         }
4437                 } else {
4438                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4439                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4440                 }
4441         } else {
4442                 int adv, bmcr;
4443
4444                 np->autoneg = 0;
4445
4446                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4447                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4448                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4449                         adv |= ADVERTISE_10HALF;
4450                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4451                         adv |= ADVERTISE_10FULL;
4452                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4453                         adv |= ADVERTISE_100HALF;
4454                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4455                         adv |= ADVERTISE_100FULL;
4456                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4457                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4458                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4459                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4460                 }
4461                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4462                         adv |=  ADVERTISE_PAUSE_ASYM;
4463                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4464                 }
4465                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4466                 np->fixed_mode = adv;
4467
4468                 if (np->gigabit == PHY_GIGABIT) {
4469                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4470                         adv &= ~ADVERTISE_1000FULL;
4471                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4472                 }
4473
4474                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4475                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4476                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4477                         bmcr |= BMCR_FULLDPLX;
4478                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4479                         bmcr |= BMCR_SPEED100;
4480                 if (np->phy_oui == PHY_OUI_MARVELL) {
4481                         /* reset the phy in order for forced mode settings to stick */
4482                         if (phy_reset(dev, bmcr)) {
4483                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4484                                 return -EINVAL;
4485                         }
4486                 } else {
4487                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4488                         if (netif_running(dev)) {
4489                                 /* Wait a bit and then reconfigure the nic. */
4490                                 udelay(10);
4491                                 nv_linkchange(dev);
4492                         }
4493                 }
4494         }
4495
4496         if (netif_running(dev)) {
4497                 nv_start_rxtx(dev);
4498                 nv_enable_irq(dev);
4499         }
4500
4501         return 0;
4502 }
4503
4504 #define FORCEDETH_REGS_VER      1
4505
4506 static int nv_get_regs_len(struct net_device *dev)
4507 {
4508         struct fe_priv *np = netdev_priv(dev);
4509         return np->register_size;
4510 }
4511
4512 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4513 {
4514         struct fe_priv *np = netdev_priv(dev);
4515         u8 __iomem *base = get_hwbase(dev);
4516         u32 *rbuf = buf;
4517         int i;
4518
4519         regs->version = FORCEDETH_REGS_VER;
4520         spin_lock_irq(&np->lock);
4521         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4522                 rbuf[i] = readl(base + i*sizeof(u32));
4523         spin_unlock_irq(&np->lock);
4524 }
4525
4526 static int nv_nway_reset(struct net_device *dev)
4527 {
4528         struct fe_priv *np = netdev_priv(dev);
4529         int ret;
4530
4531         if (np->autoneg) {
4532                 int bmcr;
4533
4534                 netif_carrier_off(dev);
4535                 if (netif_running(dev)) {
4536                         nv_disable_irq(dev);
4537                         netif_tx_lock_bh(dev);
4538                         netif_addr_lock(dev);
4539                         spin_lock(&np->lock);
4540                         /* stop engines */
4541                         nv_stop_rxtx(dev);
4542                         spin_unlock(&np->lock);
4543                         netif_addr_unlock(dev);
4544                         netif_tx_unlock_bh(dev);
4545                         printk(KERN_INFO "%s: link down.\n", dev->name);
4546                 }
4547
4548                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4549                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4550                         bmcr |= BMCR_ANENABLE;
4551                         /* reset the phy in order for settings to stick*/
4552                         if (phy_reset(dev, bmcr)) {
4553                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4554                                 return -EINVAL;
4555                         }
4556                 } else {
4557                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4558                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4559                 }
4560
4561                 if (netif_running(dev)) {
4562                         nv_start_rxtx(dev);
4563                         nv_enable_irq(dev);
4564                 }
4565                 ret = 0;
4566         } else {
4567                 ret = -EINVAL;
4568         }
4569
4570         return ret;
4571 }
4572
4573 static int nv_set_tso(struct net_device *dev, u32 value)
4574 {
4575         struct fe_priv *np = netdev_priv(dev);
4576
4577         if ((np->driver_data & DEV_HAS_CHECKSUM))
4578                 return ethtool_op_set_tso(dev, value);
4579         else
4580                 return -EOPNOTSUPP;
4581 }
4582
4583 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4584 {
4585         struct fe_priv *np = netdev_priv(dev);
4586
4587         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4588         ring->rx_mini_max_pending = 0;
4589         ring->rx_jumbo_max_pending = 0;
4590         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4591
4592         ring->rx_pending = np->rx_ring_size;
4593         ring->rx_mini_pending = 0;
4594         ring->rx_jumbo_pending = 0;
4595         ring->tx_pending = np->tx_ring_size;
4596 }
4597
4598 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4599 {
4600         struct fe_priv *np = netdev_priv(dev);
4601         u8 __iomem *base = get_hwbase(dev);
4602         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4603         dma_addr_t ring_addr;
4604
4605         if (ring->rx_pending < RX_RING_MIN ||
4606             ring->tx_pending < TX_RING_MIN ||
4607             ring->rx_mini_pending != 0 ||
4608             ring->rx_jumbo_pending != 0 ||
4609             (np->desc_ver == DESC_VER_1 &&
4610              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4611               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4612             (np->desc_ver != DESC_VER_1 &&
4613              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4614               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4615                 return -EINVAL;
4616         }
4617
4618         /* allocate new rings */
4619         if (!nv_optimized(np)) {
4620                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4621                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4622                                             &ring_addr);
4623         } else {
4624                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4625                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4626                                             &ring_addr);
4627         }
4628         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4629         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4630         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4631                 /* fall back to old rings */
4632                 if (!nv_optimized(np)) {
4633                         if (rxtx_ring)
4634                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4635                                                     rxtx_ring, ring_addr);
4636                 } else {
4637                         if (rxtx_ring)
4638                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4639                                                     rxtx_ring, ring_addr);
4640                 }
4641                 if (rx_skbuff)
4642                         kfree(rx_skbuff);
4643                 if (tx_skbuff)
4644                         kfree(tx_skbuff);
4645                 goto exit;
4646         }
4647
4648         if (netif_running(dev)) {
4649                 nv_disable_irq(dev);
4650                 nv_napi_disable(dev);
4651                 netif_tx_lock_bh(dev);
4652                 netif_addr_lock(dev);
4653                 spin_lock(&np->lock);
4654                 /* stop engines */
4655                 nv_stop_rxtx(dev);
4656                 nv_txrx_reset(dev);
4657                 /* drain queues */
4658                 nv_drain_rxtx(dev);
4659                 /* delete queues */
4660                 free_rings(dev);
4661         }
4662
4663         /* set new values */
4664         np->rx_ring_size = ring->rx_pending;
4665         np->tx_ring_size = ring->tx_pending;
4666
4667         if (!nv_optimized(np)) {
4668                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4669                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4670         } else {
4671                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4672                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4673         }
4674         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4675         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4676         np->ring_addr = ring_addr;
4677
4678         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4679         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4680
4681         if (netif_running(dev)) {
4682                 /* reinit driver view of the queues */
4683                 set_bufsize(dev);
4684                 if (nv_init_ring(dev)) {
4685                         if (!np->in_shutdown)
4686                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4687                 }
4688
4689                 /* reinit nic view of the queues */
4690                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4691                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4692                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4693                         base + NvRegRingSizes);
4694                 pci_push(base);
4695                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4696                 pci_push(base);
4697
4698                 /* restart engines */
4699                 nv_start_rxtx(dev);
4700                 spin_unlock(&np->lock);
4701                 netif_addr_unlock(dev);
4702                 netif_tx_unlock_bh(dev);
4703                 nv_napi_enable(dev);
4704                 nv_enable_irq(dev);
4705         }
4706         return 0;
4707 exit:
4708         return -ENOMEM;
4709 }
4710
4711 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4712 {
4713         struct fe_priv *np = netdev_priv(dev);
4714
4715         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4716         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4717         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4718 }
4719
4720 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4721 {
4722         struct fe_priv *np = netdev_priv(dev);
4723         int adv, bmcr;
4724
4725         if ((!np->autoneg && np->duplex == 0) ||
4726             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4727                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4728                        dev->name);
4729                 return -EINVAL;
4730         }
4731         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4732                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4733                 return -EINVAL;
4734         }
4735
4736         netif_carrier_off(dev);
4737         if (netif_running(dev)) {
4738                 nv_disable_irq(dev);
4739                 netif_tx_lock_bh(dev);
4740                 netif_addr_lock(dev);
4741                 spin_lock(&np->lock);
4742                 /* stop engines */
4743                 nv_stop_rxtx(dev);
4744                 spin_unlock(&np->lock);
4745                 netif_addr_unlock(dev);
4746                 netif_tx_unlock_bh(dev);
4747         }
4748
4749         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4750         if (pause->rx_pause)
4751                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4752         if (pause->tx_pause)
4753                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4754
4755         if (np->autoneg && pause->autoneg) {
4756                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4757
4758                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4759                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4760                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4761                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4762                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4763                         adv |=  ADVERTISE_PAUSE_ASYM;
4764                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4765
4766                 if (netif_running(dev))
4767                         printk(KERN_INFO "%s: link down.\n", dev->name);
4768                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4769                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4770                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4771         } else {
4772                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4773                 if (pause->rx_pause)
4774                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4775                 if (pause->tx_pause)
4776                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4777
4778                 if (!netif_running(dev))
4779                         nv_update_linkspeed(dev);
4780                 else
4781                         nv_update_pause(dev, np->pause_flags);
4782         }
4783
4784         if (netif_running(dev)) {
4785                 nv_start_rxtx(dev);
4786                 nv_enable_irq(dev);
4787         }
4788         return 0;
4789 }
4790
4791 static u32 nv_get_rx_csum(struct net_device *dev)
4792 {
4793         struct fe_priv *np = netdev_priv(dev);
4794         return (np->rx_csum) != 0;
4795 }
4796
4797 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4798 {
4799         struct fe_priv *np = netdev_priv(dev);
4800         u8 __iomem *base = get_hwbase(dev);
4801         int retcode = 0;
4802
4803         if (np->driver_data & DEV_HAS_CHECKSUM) {
4804                 if (data) {
4805                         np->rx_csum = 1;
4806                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4807                 } else {
4808                         np->rx_csum = 0;
4809                         /* vlan is dependent on rx checksum offload */
4810                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4811                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4812                 }
4813                 if (netif_running(dev)) {
4814                         spin_lock_irq(&np->lock);
4815                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4816                         spin_unlock_irq(&np->lock);
4817                 }
4818         } else {
4819                 return -EINVAL;
4820         }
4821
4822         return retcode;
4823 }
4824
4825 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4826 {
4827         struct fe_priv *np = netdev_priv(dev);
4828
4829         if (np->driver_data & DEV_HAS_CHECKSUM)
4830                 return ethtool_op_set_tx_csum(dev, data);
4831         else
4832                 return -EOPNOTSUPP;
4833 }
4834
4835 static int nv_set_sg(struct net_device *dev, u32 data)
4836 {
4837         struct fe_priv *np = netdev_priv(dev);
4838
4839         if (np->driver_data & DEV_HAS_CHECKSUM)
4840                 return ethtool_op_set_sg(dev, data);
4841         else
4842                 return -EOPNOTSUPP;
4843 }
4844
4845 static int nv_get_sset_count(struct net_device *dev, int sset)
4846 {
4847         struct fe_priv *np = netdev_priv(dev);
4848
4849         switch (sset) {
4850         case ETH_SS_TEST:
4851                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4852                         return NV_TEST_COUNT_EXTENDED;
4853                 else
4854                         return NV_TEST_COUNT_BASE;
4855         case ETH_SS_STATS:
4856                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4857                         return NV_DEV_STATISTICS_V3_COUNT;
4858                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4859                         return NV_DEV_STATISTICS_V2_COUNT;
4860                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4861                         return NV_DEV_STATISTICS_V1_COUNT;
4862                 else
4863                         return 0;
4864         default:
4865                 return -EOPNOTSUPP;
4866         }
4867 }
4868
4869 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4870 {
4871         struct fe_priv *np = netdev_priv(dev);
4872
4873         /* update stats */
4874         nv_do_stats_poll((unsigned long)dev);
4875
4876         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4877 }
4878
4879 static int nv_link_test(struct net_device *dev)
4880 {
4881         struct fe_priv *np = netdev_priv(dev);
4882         int mii_status;
4883
4884         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4885         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4886
4887         /* check phy link status */
4888         if (!(mii_status & BMSR_LSTATUS))
4889                 return 0;
4890         else
4891                 return 1;
4892 }
4893
4894 static int nv_register_test(struct net_device *dev)
4895 {
4896         u8 __iomem *base = get_hwbase(dev);
4897         int i = 0;
4898         u32 orig_read, new_read;
4899
4900         do {
4901                 orig_read = readl(base + nv_registers_test[i].reg);
4902
4903                 /* xor with mask to toggle bits */
4904                 orig_read ^= nv_registers_test[i].mask;
4905
4906                 writel(orig_read, base + nv_registers_test[i].reg);
4907
4908                 new_read = readl(base + nv_registers_test[i].reg);
4909
4910                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4911                         return 0;
4912
4913                 /* restore original value */
4914                 orig_read ^= nv_registers_test[i].mask;
4915                 writel(orig_read, base + nv_registers_test[i].reg);
4916
4917         } while (nv_registers_test[++i].reg != 0);
4918
4919         return 1;
4920 }
4921
4922 static int nv_interrupt_test(struct net_device *dev)
4923 {
4924         struct fe_priv *np = netdev_priv(dev);
4925         u8 __iomem *base = get_hwbase(dev);
4926         int ret = 1;
4927         int testcnt;
4928         u32 save_msi_flags, save_poll_interval = 0;
4929
4930         if (netif_running(dev)) {
4931                 /* free current irq */
4932                 nv_free_irq(dev);
4933                 save_poll_interval = readl(base+NvRegPollingInterval);
4934         }
4935
4936         /* flag to test interrupt handler */
4937         np->intr_test = 0;
4938
4939         /* setup test irq */
4940         save_msi_flags = np->msi_flags;
4941         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4942         np->msi_flags |= 0x001; /* setup 1 vector */
4943         if (nv_request_irq(dev, 1))
4944                 return 0;
4945
4946         /* setup timer interrupt */
4947         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4948         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4949
4950         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4951
4952         /* wait for at least one interrupt */
4953         msleep(100);
4954
4955         spin_lock_irq(&np->lock);
4956
4957         /* flag should be set within ISR */
4958         testcnt = np->intr_test;
4959         if (!testcnt)
4960                 ret = 2;
4961
4962         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4963         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4964                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4965         else
4966                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4967
4968         spin_unlock_irq(&np->lock);
4969
4970         nv_free_irq(dev);
4971
4972         np->msi_flags = save_msi_flags;
4973
4974         if (netif_running(dev)) {
4975                 writel(save_poll_interval, base + NvRegPollingInterval);
4976                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4977                 /* restore original irq */
4978                 if (nv_request_irq(dev, 0))
4979                         return 0;
4980         }
4981
4982         return ret;
4983 }
4984
4985 static int nv_loopback_test(struct net_device *dev)
4986 {
4987         struct fe_priv *np = netdev_priv(dev);
4988         u8 __iomem *base = get_hwbase(dev);
4989         struct sk_buff *tx_skb, *rx_skb;
4990         dma_addr_t test_dma_addr;
4991         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4992         u32 flags;
4993         int len, i, pkt_len;
4994         u8 *pkt_data;
4995         u32 filter_flags = 0;
4996         u32 misc1_flags = 0;
4997         int ret = 1;
4998
4999         if (netif_running(dev)) {
5000                 nv_disable_irq(dev);
5001                 filter_flags = readl(base + NvRegPacketFilterFlags);
5002                 misc1_flags = readl(base + NvRegMisc1);
5003         } else {
5004                 nv_txrx_reset(dev);
5005         }
5006
5007         /* reinit driver view of the rx queue */
5008         set_bufsize(dev);
5009         nv_init_ring(dev);
5010
5011         /* setup hardware for loopback */
5012         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5013         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5014
5015         /* reinit nic view of the rx queue */
5016         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5017         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5018         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5019                 base + NvRegRingSizes);
5020         pci_push(base);
5021
5022         /* restart rx engine */
5023         nv_start_rxtx(dev);
5024
5025         /* setup packet for tx */
5026         pkt_len = ETH_DATA_LEN;
5027         tx_skb = dev_alloc_skb(pkt_len);
5028         if (!tx_skb) {
5029                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5030                          " of %s\n", dev->name);
5031                 ret = 0;
5032                 goto out;
5033         }
5034         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5035                                        skb_tailroom(tx_skb),
5036                                        PCI_DMA_FROMDEVICE);
5037         pkt_data = skb_put(tx_skb, pkt_len);
5038         for (i = 0; i < pkt_len; i++)
5039                 pkt_data[i] = (u8)(i & 0xff);
5040
5041         if (!nv_optimized(np)) {
5042                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5043                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5044         } else {
5045                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5046                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5047                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5048         }
5049         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5050         pci_push(get_hwbase(dev));
5051
5052         msleep(500);
5053
5054         /* check for rx of the packet */
5055         if (!nv_optimized(np)) {
5056                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5057                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5058
5059         } else {
5060                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5061                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5062         }
5063
5064         if (flags & NV_RX_AVAIL) {
5065                 ret = 0;
5066         } else if (np->desc_ver == DESC_VER_1) {
5067                 if (flags & NV_RX_ERROR)
5068                         ret = 0;
5069         } else {
5070                 if (flags & NV_RX2_ERROR) {
5071                         ret = 0;
5072                 }
5073         }
5074
5075         if (ret) {
5076                 if (len != pkt_len) {
5077                         ret = 0;
5078                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5079                                 dev->name, len, pkt_len);
5080                 } else {
5081                         rx_skb = np->rx_skb[0].skb;
5082                         for (i = 0; i < pkt_len; i++) {
5083                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5084                                         ret = 0;
5085                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5086                                                 dev->name, i);
5087                                         break;
5088                                 }
5089                         }
5090                 }
5091         } else {
5092                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5093         }
5094
5095         pci_unmap_page(np->pci_dev, test_dma_addr,
5096                        (skb_end_pointer(tx_skb) - tx_skb->data),
5097                        PCI_DMA_TODEVICE);
5098         dev_kfree_skb_any(tx_skb);
5099  out:
5100         /* stop engines */
5101         nv_stop_rxtx(dev);
5102         nv_txrx_reset(dev);
5103         /* drain rx queue */
5104         nv_drain_rxtx(dev);
5105
5106         if (netif_running(dev)) {
5107                 writel(misc1_flags, base + NvRegMisc1);
5108                 writel(filter_flags, base + NvRegPacketFilterFlags);
5109                 nv_enable_irq(dev);
5110         }
5111
5112         return ret;
5113 }
5114
5115 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5116 {
5117         struct fe_priv *np = netdev_priv(dev);
5118         u8 __iomem *base = get_hwbase(dev);
5119         int result;
5120         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5121
5122         if (!nv_link_test(dev)) {
5123                 test->flags |= ETH_TEST_FL_FAILED;
5124                 buffer[0] = 1;
5125         }
5126
5127         if (test->flags & ETH_TEST_FL_OFFLINE) {
5128                 if (netif_running(dev)) {
5129                         netif_stop_queue(dev);
5130                         nv_napi_disable(dev);
5131                         netif_tx_lock_bh(dev);
5132                         netif_addr_lock(dev);
5133                         spin_lock_irq(&np->lock);
5134                         nv_disable_hw_interrupts(dev, np->irqmask);
5135                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5136                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5137                         } else {
5138                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5139                         }
5140                         /* stop engines */
5141                         nv_stop_rxtx(dev);
5142                         nv_txrx_reset(dev);
5143                         /* drain rx queue */
5144                         nv_drain_rxtx(dev);
5145                         spin_unlock_irq(&np->lock);
5146                         netif_addr_unlock(dev);
5147                         netif_tx_unlock_bh(dev);
5148                 }
5149
5150                 if (!nv_register_test(dev)) {
5151                         test->flags |= ETH_TEST_FL_FAILED;
5152                         buffer[1] = 1;
5153                 }
5154
5155                 result = nv_interrupt_test(dev);
5156                 if (result != 1) {
5157                         test->flags |= ETH_TEST_FL_FAILED;
5158                         buffer[2] = 1;
5159                 }
5160                 if (result == 0) {
5161                         /* bail out */
5162                         return;
5163                 }
5164
5165                 if (!nv_loopback_test(dev)) {
5166                         test->flags |= ETH_TEST_FL_FAILED;
5167                         buffer[3] = 1;
5168                 }
5169
5170                 if (netif_running(dev)) {
5171                         /* reinit driver view of the rx queue */
5172                         set_bufsize(dev);
5173                         if (nv_init_ring(dev)) {
5174                                 if (!np->in_shutdown)
5175                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5176                         }
5177                         /* reinit nic view of the rx queue */
5178                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5179                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5180                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5181                                 base + NvRegRingSizes);
5182                         pci_push(base);
5183                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5184                         pci_push(base);
5185                         /* restart rx engine */
5186                         nv_start_rxtx(dev);
5187                         netif_start_queue(dev);
5188                         nv_napi_enable(dev);
5189                         nv_enable_hw_interrupts(dev, np->irqmask);
5190                 }
5191         }
5192 }
5193
5194 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5195 {
5196         switch (stringset) {
5197         case ETH_SS_STATS:
5198                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5199                 break;
5200         case ETH_SS_TEST:
5201                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5202                 break;
5203         }
5204 }
5205
5206 static const struct ethtool_ops ops = {
5207         .get_drvinfo = nv_get_drvinfo,
5208         .get_link = ethtool_op_get_link,
5209         .get_wol = nv_get_wol,
5210         .set_wol = nv_set_wol,
5211         .get_settings = nv_get_settings,
5212         .set_settings = nv_set_settings,
5213         .get_regs_len = nv_get_regs_len,
5214         .get_regs = nv_get_regs,
5215         .nway_reset = nv_nway_reset,
5216         .set_tso = nv_set_tso,
5217         .get_ringparam = nv_get_ringparam,
5218         .set_ringparam = nv_set_ringparam,
5219         .get_pauseparam = nv_get_pauseparam,
5220         .set_pauseparam = nv_set_pauseparam,
5221         .get_rx_csum = nv_get_rx_csum,
5222         .set_rx_csum = nv_set_rx_csum,
5223         .set_tx_csum = nv_set_tx_csum,
5224         .set_sg = nv_set_sg,
5225         .get_strings = nv_get_strings,
5226         .get_ethtool_stats = nv_get_ethtool_stats,
5227         .get_sset_count = nv_get_sset_count,
5228         .self_test = nv_self_test,
5229 };
5230
5231 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5232 {
5233         struct fe_priv *np = get_nvpriv(dev);
5234
5235         spin_lock_irq(&np->lock);
5236
5237         /* save vlan group */
5238         np->vlangrp = grp;
5239
5240         if (grp) {
5241                 /* enable vlan on MAC */
5242                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5243         } else {
5244                 /* disable vlan on MAC */
5245                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5246                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5247         }
5248
5249         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5250
5251         spin_unlock_irq(&np->lock);
5252 }
5253
5254 /* The mgmt unit and driver use a semaphore to access the phy during init */
5255 static int nv_mgmt_acquire_sema(struct net_device *dev)
5256 {
5257         struct fe_priv *np = netdev_priv(dev);
5258         u8 __iomem *base = get_hwbase(dev);
5259         int i;
5260         u32 tx_ctrl, mgmt_sema;
5261
5262         for (i = 0; i < 10; i++) {
5263                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5264                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5265                         break;
5266                 msleep(500);
5267         }
5268
5269         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5270                 return 0;
5271
5272         for (i = 0; i < 2; i++) {
5273                 tx_ctrl = readl(base + NvRegTransmitterControl);
5274                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5275                 writel(tx_ctrl, base + NvRegTransmitterControl);
5276
5277                 /* verify that semaphore was acquired */
5278                 tx_ctrl = readl(base + NvRegTransmitterControl);
5279                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5280                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5281                         np->mgmt_sema = 1;
5282                         return 1;
5283                 }
5284                 else
5285                         udelay(50);
5286         }
5287
5288         return 0;
5289 }
5290
5291 static void nv_mgmt_release_sema(struct net_device *dev)
5292 {
5293         struct fe_priv *np = netdev_priv(dev);
5294         u8 __iomem *base = get_hwbase(dev);
5295         u32 tx_ctrl;
5296
5297         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5298                 if (np->mgmt_sema) {
5299                         tx_ctrl = readl(base + NvRegTransmitterControl);
5300                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5301                         writel(tx_ctrl, base + NvRegTransmitterControl);
5302                 }
5303         }
5304 }
5305
5306
5307 static int nv_mgmt_get_version(struct net_device *dev)
5308 {
5309         struct fe_priv *np = netdev_priv(dev);
5310         u8 __iomem *base = get_hwbase(dev);
5311         u32 data_ready = readl(base + NvRegTransmitterControl);
5312         u32 data_ready2 = 0;
5313         unsigned long start;
5314         int ready = 0;
5315
5316         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5317         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5318         start = jiffies;
5319         while (time_before(jiffies, start + 5*HZ)) {
5320                 data_ready2 = readl(base + NvRegTransmitterControl);
5321                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5322                         ready = 1;
5323                         break;
5324                 }
5325                 schedule_timeout_uninterruptible(1);
5326         }
5327
5328         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5329                 return 0;
5330
5331         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5332
5333         return 1;
5334 }
5335
5336 static int nv_open(struct net_device *dev)
5337 {
5338         struct fe_priv *np = netdev_priv(dev);
5339         u8 __iomem *base = get_hwbase(dev);
5340         int ret = 1;
5341         int oom, i;
5342         u32 low;
5343
5344         dprintk(KERN_DEBUG "nv_open: begin\n");
5345
5346         /* power up phy */
5347         mii_rw(dev, np->phyaddr, MII_BMCR,
5348                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5349
5350         nv_txrx_gate(dev, false);
5351         /* erase previous misconfiguration */
5352         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5353                 nv_mac_reset(dev);
5354         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5355         writel(0, base + NvRegMulticastAddrB);
5356         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5357         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5358         writel(0, base + NvRegPacketFilterFlags);
5359
5360         writel(0, base + NvRegTransmitterControl);
5361         writel(0, base + NvRegReceiverControl);
5362
5363         writel(0, base + NvRegAdapterControl);
5364
5365         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5366                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5367
5368         /* initialize descriptor rings */
5369         set_bufsize(dev);
5370         oom = nv_init_ring(dev);
5371
5372         writel(0, base + NvRegLinkSpeed);
5373         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5374         nv_txrx_reset(dev);
5375         writel(0, base + NvRegUnknownSetupReg6);
5376
5377         np->in_shutdown = 0;
5378
5379         /* give hw rings */
5380         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5381         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5382                 base + NvRegRingSizes);
5383
5384         writel(np->linkspeed, base + NvRegLinkSpeed);
5385         if (np->desc_ver == DESC_VER_1)
5386                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5387         else
5388                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5389         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5390         writel(np->vlanctl_bits, base + NvRegVlanControl);
5391         pci_push(base);
5392         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5393         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5394                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5395                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5396
5397         writel(0, base + NvRegMIIMask);
5398         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5399         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5400
5401         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5402         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5403         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5404         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5405
5406         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5407
5408         get_random_bytes(&low, sizeof(low));
5409         low &= NVREG_SLOTTIME_MASK;
5410         if (np->desc_ver == DESC_VER_1) {
5411                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5412         } else {
5413                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5414                         /* setup legacy backoff */
5415                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5416                 } else {
5417                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5418                         nv_gear_backoff_reseed(dev);
5419                 }
5420         }
5421         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5422         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5423         if (poll_interval == -1) {
5424                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5425                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5426                 else
5427                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5428         }
5429         else
5430                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5431         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5432         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5433                         base + NvRegAdapterControl);
5434         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5435         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5436         if (np->wolenabled)
5437                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5438
5439         i = readl(base + NvRegPowerState);
5440         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5441                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5442
5443         pci_push(base);
5444         udelay(10);
5445         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5446
5447         nv_disable_hw_interrupts(dev, np->irqmask);
5448         pci_push(base);
5449         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5450         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5451         pci_push(base);
5452
5453         if (nv_request_irq(dev, 0)) {
5454                 goto out_drain;
5455         }
5456
5457         /* ask for interrupts */
5458         nv_enable_hw_interrupts(dev, np->irqmask);
5459
5460         spin_lock_irq(&np->lock);
5461         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5462         writel(0, base + NvRegMulticastAddrB);
5463         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5464         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5465         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5466         /* One manual link speed update: Interrupts are enabled, future link
5467          * speed changes cause interrupts and are handled by nv_link_irq().
5468          */
5469         {
5470                 u32 miistat;
5471                 miistat = readl(base + NvRegMIIStatus);
5472                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5473                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5474         }
5475         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5476          * to init hw */
5477         np->linkspeed = 0;
5478         ret = nv_update_linkspeed(dev);
5479         nv_start_rxtx(dev);
5480         netif_start_queue(dev);
5481         nv_napi_enable(dev);
5482
5483         if (ret) {
5484                 netif_carrier_on(dev);
5485         } else {
5486                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5487                 netif_carrier_off(dev);
5488         }
5489         if (oom)
5490                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5491
5492         /* start statistics timer */
5493         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5494                 mod_timer(&np->stats_poll,
5495                         round_jiffies(jiffies + STATS_INTERVAL));
5496
5497         spin_unlock_irq(&np->lock);
5498
5499         return 0;
5500 out_drain:
5501         nv_drain_rxtx(dev);
5502         return ret;
5503 }
5504
5505 static int nv_close(struct net_device *dev)
5506 {
5507         struct fe_priv *np = netdev_priv(dev);
5508         u8 __iomem *base;
5509
5510         spin_lock_irq(&np->lock);
5511         np->in_shutdown = 1;
5512         spin_unlock_irq(&np->lock);
5513         nv_napi_disable(dev);
5514         synchronize_irq(np->pci_dev->irq);
5515
5516         del_timer_sync(&np->oom_kick);
5517         del_timer_sync(&np->nic_poll);
5518         del_timer_sync(&np->stats_poll);
5519
5520         netif_stop_queue(dev);
5521         spin_lock_irq(&np->lock);
5522         nv_stop_rxtx(dev);
5523         nv_txrx_reset(dev);
5524
5525         /* disable interrupts on the nic or we will lock up */
5526         base = get_hwbase(dev);
5527         nv_disable_hw_interrupts(dev, np->irqmask);
5528         pci_push(base);
5529         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5530
5531         spin_unlock_irq(&np->lock);
5532
5533         nv_free_irq(dev);
5534
5535         nv_drain_rxtx(dev);
5536
5537         if (np->wolenabled) {
5538                 nv_txrx_gate(dev, false);
5539                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5540                 nv_start_rx(dev);
5541         } else {
5542                 /* power down phy */
5543                 mii_rw(dev, np->phyaddr, MII_BMCR,
5544                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5545                 nv_txrx_gate(dev, true);
5546         }
5547
5548         /* FIXME: power down nic */
5549
5550         return 0;
5551 }
5552
5553 static const struct net_device_ops nv_netdev_ops = {