[netdrvr] forcedeth: save/restore device configuration space
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.61"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk                 printk
69 #else
70 #define dprintk(x...)           do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP  64
74 #define RX_WORK_PER_LOOP  64
75
76 /*
77  * Hardware access:
78  */
79
80 #define DEV_NEED_TIMERIRQ          0x00001  /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER         0x00002  /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC          0x00004  /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA           0x00008  /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM           0x00010  /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN               0x00020  /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI                0x00040  /* device supports MSI */
87 #define DEV_HAS_MSI_X              0x00080  /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL        0x00100  /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1      0x00200  /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2      0x00400  /* device supports hw statistics version 2 */
91 #define DEV_HAS_TEST_EXTENDED      0x00800  /* device supports extended diagnostic test */
92 #define DEV_HAS_MGMT_UNIT          0x01000  /* device supports management unit */
93 #define DEV_HAS_CORRECT_MACADDR    0x02000  /* device supports correct mac address order */
94 #define DEV_HAS_COLLISION_FIX      0x04000  /* device supports tx collision fix */
95 #define DEV_HAS_PAUSEFRAME_TX_V1   0x08000  /* device supports tx pause frames version 1 */
96 #define DEV_HAS_PAUSEFRAME_TX_V2   0x10000  /* device supports tx pause frames version 2 */
97 #define DEV_HAS_PAUSEFRAME_TX_V3   0x20000  /* device supports tx pause frames version 3 */
98 #define DEV_NEED_TX_LIMIT          0x40000  /* device needs to limit tx */
99 #define DEV_HAS_GEAR_MODE          0x80000  /* device supports gear mode */
100
101 enum {
102         NvRegIrqStatus = 0x000,
103 #define NVREG_IRQSTAT_MIIEVENT  0x040
104 #define NVREG_IRQSTAT_MASK              0x81ff
105         NvRegIrqMask = 0x004,
106 #define NVREG_IRQ_RX_ERROR              0x0001
107 #define NVREG_IRQ_RX                    0x0002
108 #define NVREG_IRQ_RX_NOBUF              0x0004
109 #define NVREG_IRQ_TX_ERR                0x0008
110 #define NVREG_IRQ_TX_OK                 0x0010
111 #define NVREG_IRQ_TIMER                 0x0020
112 #define NVREG_IRQ_LINK                  0x0040
113 #define NVREG_IRQ_RX_FORCED             0x0080
114 #define NVREG_IRQ_TX_FORCED             0x0100
115 #define NVREG_IRQ_RECOVER_ERROR         0x8000
116 #define NVREG_IRQMASK_THROUGHPUT        0x00df
117 #define NVREG_IRQMASK_CPU               0x0060
118 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
119 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
120 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
121
122 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
123                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
124                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
125
126         NvRegUnknownSetupReg6 = 0x008,
127 #define NVREG_UNKSETUP6_VAL             3
128
129 /*
130  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
131  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
132  */
133         NvRegPollingInterval = 0x00c,
134 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
135 #define NVREG_POLL_DEFAULT_CPU  13
136         NvRegMSIMap0 = 0x020,
137         NvRegMSIMap1 = 0x024,
138         NvRegMSIIrqMask = 0x030,
139 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
140         NvRegMisc1 = 0x080,
141 #define NVREG_MISC1_PAUSE_TX    0x01
142 #define NVREG_MISC1_HD          0x02
143 #define NVREG_MISC1_FORCE       0x3b0f3c
144
145         NvRegMacReset = 0x34,
146 #define NVREG_MAC_RESET_ASSERT  0x0F3
147         NvRegTransmitterControl = 0x084,
148 #define NVREG_XMITCTL_START     0x01
149 #define NVREG_XMITCTL_MGMT_ST   0x40000000
150 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
151 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
152 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
153 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
154 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
155 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
156 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
157 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
158 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
159         NvRegTransmitterStatus = 0x088,
160 #define NVREG_XMITSTAT_BUSY     0x01
161
162         NvRegPacketFilterFlags = 0x8c,
163 #define NVREG_PFF_PAUSE_RX      0x08
164 #define NVREG_PFF_ALWAYS        0x7F0000
165 #define NVREG_PFF_PROMISC       0x80
166 #define NVREG_PFF_MYADDR        0x20
167 #define NVREG_PFF_LOOPBACK      0x10
168
169         NvRegOffloadConfig = 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY   0x601
171 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
172         NvRegReceiverControl = 0x094,
173 #define NVREG_RCVCTL_START      0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175         NvRegReceiverStatus = 0x98,
176 #define NVREG_RCVSTAT_BUSY      0x01
177
178         NvRegSlotTime = 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
182 #define NVREG_SLOTTIME_HALF             0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
184 #define NVREG_SLOTTIME_MASK             0x000000ff
185
186         NvRegTxDeferral = 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
193         NvRegRxDeferral = 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
195         NvRegMacAddrA = 0xA8,
196         NvRegMacAddrB = 0xAC,
197         NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE  0x01
199         NvRegMulticastAddrB = 0xB4,
200         NvRegMulticastMaskA = 0xB8,
201 #define NVREG_MCASTMASKA_NONE           0xffffffff
202         NvRegMulticastMaskB = 0xBC,
203 #define NVREG_MCASTMASKB_NONE           0xffff
204
205         NvRegPhyInterface = 0xC0,
206 #define PHY_RGMII               0x10000000
207         NvRegBackOffControl = 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT                  24
211 #define NVREG_BKOFFCTRL_GEAR                    12
212
213         NvRegTxRingPhysAddr = 0x100,
214         NvRegRxRingPhysAddr = 0x104,
215         NvRegRingSizes = 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218         NvRegTransmitPoll = 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220         NvRegLinkSpeed = 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10      1000
223 #define NVREG_LINKSPEED_100     100
224 #define NVREG_LINKSPEED_1000    50
225 #define NVREG_LINKSPEED_MASK    (0xFFF)
226         NvRegUnknownSetupReg5 = 0x130,
227 #define NVREG_UNKSETUP5_BIT31   (1<<31)
228         NvRegTxWatermark = 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
232         NvRegTxRxControl = 0x144,
233 #define NVREG_TXRXCTL_KICK      0x0001
234 #define NVREG_TXRXCTL_BIT1      0x0002
235 #define NVREG_TXRXCTL_BIT2      0x0004
236 #define NVREG_TXRXCTL_IDLE      0x0008
237 #define NVREG_TXRXCTL_RESET     0x0010
238 #define NVREG_TXRXCTL_RXCHECK   0x0400
239 #define NVREG_TXRXCTL_DESC_1    0
240 #define NVREG_TXRXCTL_DESC_2    0x002100
241 #define NVREG_TXRXCTL_DESC_3    0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS   0x00080
244         NvRegTxRingPhysAddrHigh = 0x148,
245         NvRegRxRingPhysAddrHigh = 0x14C,
246         NvRegTxPauseFrame = 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
251         NvRegMIIStatus = 0x180,
252 #define NVREG_MIISTAT_ERROR             0x0001
253 #define NVREG_MIISTAT_LINKCHANGE        0x0008
254 #define NVREG_MIISTAT_MASK_RW           0x0007
255 #define NVREG_MIISTAT_MASK_ALL          0x000f
256         NvRegMIIMask = 0x184,
257 #define NVREG_MII_LINKCHANGE            0x0008
258
259         NvRegAdapterControl = 0x188,
260 #define NVREG_ADAPTCTL_START    0x02
261 #define NVREG_ADAPTCTL_LINKUP   0x04
262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
263 #define NVREG_ADAPTCTL_RUNNING  0x100000
264 #define NVREG_ADAPTCTL_PHYSHIFT 24
265         NvRegMIISpeed = 0x18c,
266 #define NVREG_MIISPEED_BIT8     (1<<8)
267 #define NVREG_MIIDELAY  5
268         NvRegMIIControl = 0x190,
269 #define NVREG_MIICTL_INUSE      0x08000
270 #define NVREG_MIICTL_WRITE      0x00400
271 #define NVREG_MIICTL_ADDRSHIFT  5
272         NvRegMIIData = 0x194,
273         NvRegWakeUpFlags = 0x200,
274 #define NVREG_WAKEUPFLAGS_VAL           0x7770
275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
277 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
278 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
279 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
280 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
284 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
285
286         NvRegPatternCRC = 0x204,
287         NvRegPatternMask = 0x208,
288         NvRegPowerCap = 0x268,
289 #define NVREG_POWERCAP_D3SUPP   (1<<30)
290 #define NVREG_POWERCAP_D2SUPP   (1<<26)
291 #define NVREG_POWERCAP_D1SUPP   (1<<25)
292         NvRegPowerState = 0x26c,
293 #define NVREG_POWERSTATE_POWEREDUP      0x8000
294 #define NVREG_POWERSTATE_VALID          0x0100
295 #define NVREG_POWERSTATE_MASK           0x0003
296 #define NVREG_POWERSTATE_D0             0x0000
297 #define NVREG_POWERSTATE_D1             0x0001
298 #define NVREG_POWERSTATE_D2             0x0002
299 #define NVREG_POWERSTATE_D3             0x0003
300         NvRegTxCnt = 0x280,
301         NvRegTxZeroReXmt = 0x284,
302         NvRegTxOneReXmt = 0x288,
303         NvRegTxManyReXmt = 0x28c,
304         NvRegTxLateCol = 0x290,
305         NvRegTxUnderflow = 0x294,
306         NvRegTxLossCarrier = 0x298,
307         NvRegTxExcessDef = 0x29c,
308         NvRegTxRetryErr = 0x2a0,
309         NvRegRxFrameErr = 0x2a4,
310         NvRegRxExtraByte = 0x2a8,
311         NvRegRxLateCol = 0x2ac,
312         NvRegRxRunt = 0x2b0,
313         NvRegRxFrameTooLong = 0x2b4,
314         NvRegRxOverflow = 0x2b8,
315         NvRegRxFCSErr = 0x2bc,
316         NvRegRxFrameAlignErr = 0x2c0,
317         NvRegRxLenErr = 0x2c4,
318         NvRegRxUnicast = 0x2c8,
319         NvRegRxMulticast = 0x2cc,
320         NvRegRxBroadcast = 0x2d0,
321         NvRegTxDef = 0x2d4,
322         NvRegTxFrame = 0x2d8,
323         NvRegRxCnt = 0x2dc,
324         NvRegTxPause = 0x2e0,
325         NvRegRxPause = 0x2e4,
326         NvRegRxDropFrame = 0x2e8,
327         NvRegVlanControl = 0x300,
328 #define NVREG_VLANCONTROL_ENABLE        0x2000
329         NvRegMSIXMap0 = 0x3e0,
330         NvRegMSIXMap1 = 0x3e4,
331         NvRegMSIXIrqStatus = 0x3f0,
332
333         NvRegPowerState2 = 0x600,
334 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
335 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
336 };
337
338 /* Big endian: should work, but is untested */
339 struct ring_desc {
340         __le32 buf;
341         __le32 flaglen;
342 };
343
344 struct ring_desc_ex {
345         __le32 bufhigh;
346         __le32 buflow;
347         __le32 txvlan;
348         __le32 flaglen;
349 };
350
351 union ring_type {
352         struct ring_desc* orig;
353         struct ring_desc_ex* ex;
354 };
355
356 #define FLAG_MASK_V1 0xffff0000
357 #define FLAG_MASK_V2 0xffffc000
358 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
359 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
360
361 #define NV_TX_LASTPACKET        (1<<16)
362 #define NV_TX_RETRYERROR        (1<<19)
363 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
364 #define NV_TX_FORCED_INTERRUPT  (1<<24)
365 #define NV_TX_DEFERRED          (1<<26)
366 #define NV_TX_CARRIERLOST       (1<<27)
367 #define NV_TX_LATECOLLISION     (1<<28)
368 #define NV_TX_UNDERFLOW         (1<<29)
369 #define NV_TX_ERROR             (1<<30)
370 #define NV_TX_VALID             (1<<31)
371
372 #define NV_TX2_LASTPACKET       (1<<29)
373 #define NV_TX2_RETRYERROR       (1<<18)
374 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
375 #define NV_TX2_FORCED_INTERRUPT (1<<30)
376 #define NV_TX2_DEFERRED         (1<<25)
377 #define NV_TX2_CARRIERLOST      (1<<26)
378 #define NV_TX2_LATECOLLISION    (1<<27)
379 #define NV_TX2_UNDERFLOW        (1<<28)
380 /* error and valid are the same for both */
381 #define NV_TX2_ERROR            (1<<30)
382 #define NV_TX2_VALID            (1<<31)
383 #define NV_TX2_TSO              (1<<28)
384 #define NV_TX2_TSO_SHIFT        14
385 #define NV_TX2_TSO_MAX_SHIFT    14
386 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
387 #define NV_TX2_CHECKSUM_L3      (1<<27)
388 #define NV_TX2_CHECKSUM_L4      (1<<26)
389
390 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
391
392 #define NV_RX_DESCRIPTORVALID   (1<<16)
393 #define NV_RX_MISSEDFRAME       (1<<17)
394 #define NV_RX_SUBSTRACT1        (1<<18)
395 #define NV_RX_ERROR1            (1<<23)
396 #define NV_RX_ERROR2            (1<<24)
397 #define NV_RX_ERROR3            (1<<25)
398 #define NV_RX_ERROR4            (1<<26)
399 #define NV_RX_CRCERR            (1<<27)
400 #define NV_RX_OVERFLOW          (1<<28)
401 #define NV_RX_FRAMINGERR        (1<<29)
402 #define NV_RX_ERROR             (1<<30)
403 #define NV_RX_AVAIL             (1<<31)
404
405 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
406 #define NV_RX2_CHECKSUM_IP      (0x10000000)
407 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
408 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
409 #define NV_RX2_DESCRIPTORVALID  (1<<29)
410 #define NV_RX2_SUBSTRACT1       (1<<25)
411 #define NV_RX2_ERROR1           (1<<18)
412 #define NV_RX2_ERROR2           (1<<19)
413 #define NV_RX2_ERROR3           (1<<20)
414 #define NV_RX2_ERROR4           (1<<21)
415 #define NV_RX2_CRCERR           (1<<22)
416 #define NV_RX2_OVERFLOW         (1<<23)
417 #define NV_RX2_FRAMINGERR       (1<<24)
418 /* error and avail are the same for both */
419 #define NV_RX2_ERROR            (1<<30)
420 #define NV_RX2_AVAIL            (1<<31)
421
422 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
423 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
424
425 /* Miscelaneous hardware related defines: */
426 #define NV_PCI_REGSZ_VER1       0x270
427 #define NV_PCI_REGSZ_VER2       0x2d4
428 #define NV_PCI_REGSZ_VER3       0x604
429 #define NV_PCI_REGSZ_MAX        0x604
430
431 /* various timeout delays: all in usec */
432 #define NV_TXRX_RESET_DELAY     4
433 #define NV_TXSTOP_DELAY1        10
434 #define NV_TXSTOP_DELAY1MAX     500000
435 #define NV_TXSTOP_DELAY2        100
436 #define NV_RXSTOP_DELAY1        10
437 #define NV_RXSTOP_DELAY1MAX     500000
438 #define NV_RXSTOP_DELAY2        100
439 #define NV_SETUP5_DELAY         5
440 #define NV_SETUP5_DELAYMAX      50000
441 #define NV_POWERUP_DELAY        5
442 #define NV_POWERUP_DELAYMAX     5000
443 #define NV_MIIBUSY_DELAY        50
444 #define NV_MIIPHY_DELAY 10
445 #define NV_MIIPHY_DELAYMAX      10000
446 #define NV_MAC_RESET_DELAY      64
447
448 #define NV_WAKEUPPATTERNS       5
449 #define NV_WAKEUPMASKENTRIES    4
450
451 /* General driver defaults */
452 #define NV_WATCHDOG_TIMEO       (5*HZ)
453
454 #define RX_RING_DEFAULT         128
455 #define TX_RING_DEFAULT         256
456 #define RX_RING_MIN             128
457 #define TX_RING_MIN             64
458 #define RING_MAX_DESC_VER_1     1024
459 #define RING_MAX_DESC_VER_2_3   16384
460
461 /* rx/tx mac addr + type + vlan + align + slack*/
462 #define NV_RX_HEADERS           (64)
463 /* even more slack. */
464 #define NV_RX_ALLOC_PAD         (64)
465
466 /* maximum mtu size */
467 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
468 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
469
470 #define OOM_REFILL      (1+HZ/20)
471 #define POLL_WAIT       (1+HZ/100)
472 #define LINK_TIMEOUT    (3*HZ)
473 #define STATS_INTERVAL  (10*HZ)
474
475 /*
476  * desc_ver values:
477  * The nic supports three different descriptor types:
478  * - DESC_VER_1: Original
479  * - DESC_VER_2: support for jumbo frames.
480  * - DESC_VER_3: 64-bit format.
481  */
482 #define DESC_VER_1      1
483 #define DESC_VER_2      2
484 #define DESC_VER_3      3
485
486 /* PHY defines */
487 #define PHY_OUI_MARVELL         0x5043
488 #define PHY_OUI_CICADA          0x03f1
489 #define PHY_OUI_VITESSE         0x01c1
490 #define PHY_OUI_REALTEK         0x0732
491 #define PHY_OUI_REALTEK2        0x0020
492 #define PHYID1_OUI_MASK 0x03ff
493 #define PHYID1_OUI_SHFT 6
494 #define PHYID2_OUI_MASK 0xfc00
495 #define PHYID2_OUI_SHFT 10
496 #define PHYID2_MODEL_MASK               0x03f0
497 #define PHY_MODEL_REALTEK_8211          0x0110
498 #define PHY_REV_MASK                    0x0001
499 #define PHY_REV_REALTEK_8211B           0x0000
500 #define PHY_REV_REALTEK_8211C           0x0001
501 #define PHY_MODEL_REALTEK_8201          0x0200
502 #define PHY_MODEL_MARVELL_E3016         0x0220
503 #define PHY_MARVELL_E3016_INITMASK      0x0300
504 #define PHY_CICADA_INIT1        0x0f000
505 #define PHY_CICADA_INIT2        0x0e00
506 #define PHY_CICADA_INIT3        0x01000
507 #define PHY_CICADA_INIT4        0x0200
508 #define PHY_CICADA_INIT5        0x0004
509 #define PHY_CICADA_INIT6        0x02000
510 #define PHY_VITESSE_INIT_REG1   0x1f
511 #define PHY_VITESSE_INIT_REG2   0x10
512 #define PHY_VITESSE_INIT_REG3   0x11
513 #define PHY_VITESSE_INIT_REG4   0x12
514 #define PHY_VITESSE_INIT_MSK1   0xc
515 #define PHY_VITESSE_INIT_MSK2   0x0180
516 #define PHY_VITESSE_INIT1       0x52b5
517 #define PHY_VITESSE_INIT2       0xaf8a
518 #define PHY_VITESSE_INIT3       0x8
519 #define PHY_VITESSE_INIT4       0x8f8a
520 #define PHY_VITESSE_INIT5       0xaf86
521 #define PHY_VITESSE_INIT6       0x8f86
522 #define PHY_VITESSE_INIT7       0xaf82
523 #define PHY_VITESSE_INIT8       0x0100
524 #define PHY_VITESSE_INIT9       0x8f82
525 #define PHY_VITESSE_INIT10      0x0
526 #define PHY_REALTEK_INIT_REG1   0x1f
527 #define PHY_REALTEK_INIT_REG2   0x19
528 #define PHY_REALTEK_INIT_REG3   0x13
529 #define PHY_REALTEK_INIT_REG4   0x14
530 #define PHY_REALTEK_INIT_REG5   0x18
531 #define PHY_REALTEK_INIT_REG6   0x11
532 #define PHY_REALTEK_INIT1       0x0000
533 #define PHY_REALTEK_INIT2       0x8e00
534 #define PHY_REALTEK_INIT3       0x0001
535 #define PHY_REALTEK_INIT4       0xad17
536 #define PHY_REALTEK_INIT5       0xfb54
537 #define PHY_REALTEK_INIT6       0xf5c7
538 #define PHY_REALTEK_INIT7       0x1000
539 #define PHY_REALTEK_INIT8       0x0003
540 #define PHY_REALTEK_INIT_MSK1   0x0003
541
542 #define PHY_GIGABIT     0x0100
543
544 #define PHY_TIMEOUT     0x1
545 #define PHY_ERROR       0x2
546
547 #define PHY_100 0x1
548 #define PHY_1000        0x2
549 #define PHY_HALF        0x100
550
551 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
552 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
553 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
554 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
555 #define NV_PAUSEFRAME_RX_REQ     0x0010
556 #define NV_PAUSEFRAME_TX_REQ     0x0020
557 #define NV_PAUSEFRAME_AUTONEG    0x0040
558
559 /* MSI/MSI-X defines */
560 #define NV_MSI_X_MAX_VECTORS  8
561 #define NV_MSI_X_VECTORS_MASK 0x000f
562 #define NV_MSI_CAPABLE        0x0010
563 #define NV_MSI_X_CAPABLE      0x0020
564 #define NV_MSI_ENABLED        0x0040
565 #define NV_MSI_X_ENABLED      0x0080
566
567 #define NV_MSI_X_VECTOR_ALL   0x0
568 #define NV_MSI_X_VECTOR_RX    0x0
569 #define NV_MSI_X_VECTOR_TX    0x1
570 #define NV_MSI_X_VECTOR_OTHER 0x2
571
572 #define NV_RESTART_TX         0x1
573 #define NV_RESTART_RX         0x2
574
575 #define NV_TX_LIMIT_COUNT     16
576
577 /* statistics */
578 struct nv_ethtool_str {
579         char name[ETH_GSTRING_LEN];
580 };
581
582 static const struct nv_ethtool_str nv_estats_str[] = {
583         { "tx_bytes" },
584         { "tx_zero_rexmt" },
585         { "tx_one_rexmt" },
586         { "tx_many_rexmt" },
587         { "tx_late_collision" },
588         { "tx_fifo_errors" },
589         { "tx_carrier_errors" },
590         { "tx_excess_deferral" },
591         { "tx_retry_error" },
592         { "rx_frame_error" },
593         { "rx_extra_byte" },
594         { "rx_late_collision" },
595         { "rx_runt" },
596         { "rx_frame_too_long" },
597         { "rx_over_errors" },
598         { "rx_crc_errors" },
599         { "rx_frame_align_error" },
600         { "rx_length_error" },
601         { "rx_unicast" },
602         { "rx_multicast" },
603         { "rx_broadcast" },
604         { "rx_packets" },
605         { "rx_errors_total" },
606         { "tx_errors_total" },
607
608         /* version 2 stats */
609         { "tx_deferral" },
610         { "tx_packets" },
611         { "rx_bytes" },
612         { "tx_pause" },
613         { "rx_pause" },
614         { "rx_drop_frame" }
615 };
616
617 struct nv_ethtool_stats {
618         u64 tx_bytes;
619         u64 tx_zero_rexmt;
620         u64 tx_one_rexmt;
621         u64 tx_many_rexmt;
622         u64 tx_late_collision;
623         u64 tx_fifo_errors;
624         u64 tx_carrier_errors;
625         u64 tx_excess_deferral;
626         u64 tx_retry_error;
627         u64 rx_frame_error;
628         u64 rx_extra_byte;
629         u64 rx_late_collision;
630         u64 rx_runt;
631         u64 rx_frame_too_long;
632         u64 rx_over_errors;
633         u64 rx_crc_errors;
634         u64 rx_frame_align_error;
635         u64 rx_length_error;
636         u64 rx_unicast;
637         u64 rx_multicast;
638         u64 rx_broadcast;
639         u64 rx_packets;
640         u64 rx_errors_total;
641         u64 tx_errors_total;
642
643         /* version 2 stats */
644         u64 tx_deferral;
645         u64 tx_packets;
646         u64 rx_bytes;
647         u64 tx_pause;
648         u64 rx_pause;
649         u64 rx_drop_frame;
650 };
651
652 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
653 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
654
655 /* diagnostics */
656 #define NV_TEST_COUNT_BASE 3
657 #define NV_TEST_COUNT_EXTENDED 4
658
659 static const struct nv_ethtool_str nv_etests_str[] = {
660         { "link      (online/offline)" },
661         { "register  (offline)       " },
662         { "interrupt (offline)       " },
663         { "loopback  (offline)       " }
664 };
665
666 struct register_test {
667         __u32 reg;
668         __u32 mask;
669 };
670
671 static const struct register_test nv_registers_test[] = {
672         { NvRegUnknownSetupReg6, 0x01 },
673         { NvRegMisc1, 0x03c },
674         { NvRegOffloadConfig, 0x03ff },
675         { NvRegMulticastAddrA, 0xffffffff },
676         { NvRegTxWatermark, 0x0ff },
677         { NvRegWakeUpFlags, 0x07777 },
678         { 0,0 }
679 };
680
681 struct nv_skb_map {
682         struct sk_buff *skb;
683         dma_addr_t dma;
684         unsigned int dma_len;
685         struct ring_desc_ex *first_tx_desc;
686         struct nv_skb_map *next_tx_ctx;
687 };
688
689 /*
690  * SMP locking:
691  * All hardware access under dev->priv->lock, except the performance
692  * critical parts:
693  * - rx is (pseudo-) lockless: it relies on the single-threading provided
694  *      by the arch code for interrupts.
695  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
696  *      needs dev->priv->lock :-(
697  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
698  */
699
700 /* in dev: base, irq */
701 struct fe_priv {
702         spinlock_t lock;
703
704         struct net_device *dev;
705         struct napi_struct napi;
706
707         /* General data:
708          * Locking: spin_lock(&np->lock); */
709         struct nv_ethtool_stats estats;
710         int in_shutdown;
711         u32 linkspeed;
712         int duplex;
713         int autoneg;
714         int fixed_mode;
715         int phyaddr;
716         int wolenabled;
717         unsigned int phy_oui;
718         unsigned int phy_model;
719         unsigned int phy_rev;
720         u16 gigabit;
721         int intr_test;
722         int recover_error;
723
724         /* General data: RO fields */
725         dma_addr_t ring_addr;
726         struct pci_dev *pci_dev;
727         u32 orig_mac[2];
728         u32 irqmask;
729         u32 desc_ver;
730         u32 txrxctl_bits;
731         u32 vlanctl_bits;
732         u32 driver_data;
733         u32 device_id;
734         u32 register_size;
735         int rx_csum;
736         u32 mac_in_use;
737
738         void __iomem *base;
739
740         /* rx specific fields.
741          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
742          */
743         union ring_type get_rx, put_rx, first_rx, last_rx;
744         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
745         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
746         struct nv_skb_map *rx_skb;
747
748         union ring_type rx_ring;
749         unsigned int rx_buf_sz;
750         unsigned int pkt_limit;
751         struct timer_list oom_kick;
752         struct timer_list nic_poll;
753         struct timer_list stats_poll;
754         u32 nic_poll_irq;
755         int rx_ring_size;
756
757         /* media detection workaround.
758          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
759          */
760         int need_linktimer;
761         unsigned long link_timeout;
762         /*
763          * tx specific fields.
764          */
765         union ring_type get_tx, put_tx, first_tx, last_tx;
766         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
767         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
768         struct nv_skb_map *tx_skb;
769
770         union ring_type tx_ring;
771         u32 tx_flags;
772         int tx_ring_size;
773         int tx_limit;
774         u32 tx_pkts_in_progress;
775         struct nv_skb_map *tx_change_owner;
776         struct nv_skb_map *tx_end_flip;
777         int tx_stop;
778
779         /* vlan fields */
780         struct vlan_group *vlangrp;
781
782         /* msi/msi-x fields */
783         u32 msi_flags;
784         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
785
786         /* flow control */
787         u32 pause_flags;
788
789         /* power saved state */
790         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
791 };
792
793 /*
794  * Maximum number of loops until we assume that a bit in the irq mask
795  * is stuck. Overridable with module param.
796  */
797 static int max_interrupt_work = 5;
798
799 /*
800  * Optimization can be either throuput mode or cpu mode
801  *
802  * Throughput Mode: Every tx and rx packet will generate an interrupt.
803  * CPU Mode: Interrupts are controlled by a timer.
804  */
805 enum {
806         NV_OPTIMIZATION_MODE_THROUGHPUT,
807         NV_OPTIMIZATION_MODE_CPU
808 };
809 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
810
811 /*
812  * Poll interval for timer irq
813  *
814  * This interval determines how frequent an interrupt is generated.
815  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
816  * Min = 0, and Max = 65535
817  */
818 static int poll_interval = -1;
819
820 /*
821  * MSI interrupts
822  */
823 enum {
824         NV_MSI_INT_DISABLED,
825         NV_MSI_INT_ENABLED
826 };
827 static int msi = NV_MSI_INT_ENABLED;
828
829 /*
830  * MSIX interrupts
831  */
832 enum {
833         NV_MSIX_INT_DISABLED,
834         NV_MSIX_INT_ENABLED
835 };
836 static int msix = NV_MSIX_INT_DISABLED;
837
838 /*
839  * DMA 64bit
840  */
841 enum {
842         NV_DMA_64BIT_DISABLED,
843         NV_DMA_64BIT_ENABLED
844 };
845 static int dma_64bit = NV_DMA_64BIT_ENABLED;
846
847 /*
848  * Crossover Detection
849  * Realtek 8201 phy + some OEM boards do not work properly.
850  */
851 enum {
852         NV_CROSSOVER_DETECTION_DISABLED,
853         NV_CROSSOVER_DETECTION_ENABLED
854 };
855 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
856
857 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
858 {
859         return netdev_priv(dev);
860 }
861
862 static inline u8 __iomem *get_hwbase(struct net_device *dev)
863 {
864         return ((struct fe_priv *)netdev_priv(dev))->base;
865 }
866
867 static inline void pci_push(u8 __iomem *base)
868 {
869         /* force out pending posted writes */
870         readl(base);
871 }
872
873 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
874 {
875         return le32_to_cpu(prd->flaglen)
876                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
877 }
878
879 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
880 {
881         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
882 }
883
884 static bool nv_optimized(struct fe_priv *np)
885 {
886         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
887                 return false;
888         return true;
889 }
890
891 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
892                                 int delay, int delaymax, const char *msg)
893 {
894         u8 __iomem *base = get_hwbase(dev);
895
896         pci_push(base);
897         do {
898                 udelay(delay);
899                 delaymax -= delay;
900                 if (delaymax < 0) {
901                         if (msg)
902                                 printk(msg);
903                         return 1;
904                 }
905         } while ((readl(base + offset) & mask) != target);
906         return 0;
907 }
908
909 #define NV_SETUP_RX_RING 0x01
910 #define NV_SETUP_TX_RING 0x02
911
912 static inline u32 dma_low(dma_addr_t addr)
913 {
914         return addr;
915 }
916
917 static inline u32 dma_high(dma_addr_t addr)
918 {
919         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
920 }
921
922 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
923 {
924         struct fe_priv *np = get_nvpriv(dev);
925         u8 __iomem *base = get_hwbase(dev);
926
927         if (!nv_optimized(np)) {
928                 if (rxtx_flags & NV_SETUP_RX_RING) {
929                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
930                 }
931                 if (rxtx_flags & NV_SETUP_TX_RING) {
932                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
933                 }
934         } else {
935                 if (rxtx_flags & NV_SETUP_RX_RING) {
936                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
937                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
938                 }
939                 if (rxtx_flags & NV_SETUP_TX_RING) {
940                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
941                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
942                 }
943         }
944 }
945
946 static void free_rings(struct net_device *dev)
947 {
948         struct fe_priv *np = get_nvpriv(dev);
949
950         if (!nv_optimized(np)) {
951                 if (np->rx_ring.orig)
952                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
953                                             np->rx_ring.orig, np->ring_addr);
954         } else {
955                 if (np->rx_ring.ex)
956                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
957                                             np->rx_ring.ex, np->ring_addr);
958         }
959         if (np->rx_skb)
960                 kfree(np->rx_skb);
961         if (np->tx_skb)
962                 kfree(np->tx_skb);
963 }
964
965 static int using_multi_irqs(struct net_device *dev)
966 {
967         struct fe_priv *np = get_nvpriv(dev);
968
969         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
970             ((np->msi_flags & NV_MSI_X_ENABLED) &&
971              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
972                 return 0;
973         else
974                 return 1;
975 }
976
977 static void nv_enable_irq(struct net_device *dev)
978 {
979         struct fe_priv *np = get_nvpriv(dev);
980
981         if (!using_multi_irqs(dev)) {
982                 if (np->msi_flags & NV_MSI_X_ENABLED)
983                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
984                 else
985                         enable_irq(np->pci_dev->irq);
986         } else {
987                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
988                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
989                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
990         }
991 }
992
993 static void nv_disable_irq(struct net_device *dev)
994 {
995         struct fe_priv *np = get_nvpriv(dev);
996
997         if (!using_multi_irqs(dev)) {
998                 if (np->msi_flags & NV_MSI_X_ENABLED)
999                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1000                 else
1001                         disable_irq(np->pci_dev->irq);
1002         } else {
1003                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1004                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1005                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1006         }
1007 }
1008
1009 /* In MSIX mode, a write to irqmask behaves as XOR */
1010 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1011 {
1012         u8 __iomem *base = get_hwbase(dev);
1013
1014         writel(mask, base + NvRegIrqMask);
1015 }
1016
1017 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1018 {
1019         struct fe_priv *np = get_nvpriv(dev);
1020         u8 __iomem *base = get_hwbase(dev);
1021
1022         if (np->msi_flags & NV_MSI_X_ENABLED) {
1023                 writel(mask, base + NvRegIrqMask);
1024         } else {
1025                 if (np->msi_flags & NV_MSI_ENABLED)
1026                         writel(0, base + NvRegMSIIrqMask);
1027                 writel(0, base + NvRegIrqMask);
1028         }
1029 }
1030
1031 #define MII_READ        (-1)
1032 /* mii_rw: read/write a register on the PHY.
1033  *
1034  * Caller must guarantee serialization
1035  */
1036 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1037 {
1038         u8 __iomem *base = get_hwbase(dev);
1039         u32 reg;
1040         int retval;
1041
1042         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1043
1044         reg = readl(base + NvRegMIIControl);
1045         if (reg & NVREG_MIICTL_INUSE) {
1046                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1047                 udelay(NV_MIIBUSY_DELAY);
1048         }
1049
1050         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1051         if (value != MII_READ) {
1052                 writel(value, base + NvRegMIIData);
1053                 reg |= NVREG_MIICTL_WRITE;
1054         }
1055         writel(reg, base + NvRegMIIControl);
1056
1057         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1058                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1059                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1060                                 dev->name, miireg, addr);
1061                 retval = -1;
1062         } else if (value != MII_READ) {
1063                 /* it was a write operation - fewer failures are detectable */
1064                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1065                                 dev->name, value, miireg, addr);
1066                 retval = 0;
1067         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1068                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1069                                 dev->name, miireg, addr);
1070                 retval = -1;
1071         } else {
1072                 retval = readl(base + NvRegMIIData);
1073                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1074                                 dev->name, miireg, addr, retval);
1075         }
1076
1077         return retval;
1078 }
1079
1080 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1081 {
1082         struct fe_priv *np = netdev_priv(dev);
1083         u32 miicontrol;
1084         unsigned int tries = 0;
1085
1086         miicontrol = BMCR_RESET | bmcr_setup;
1087         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1088                 return -1;
1089         }
1090
1091         /* wait for 500ms */
1092         msleep(500);
1093
1094         /* must wait till reset is deasserted */
1095         while (miicontrol & BMCR_RESET) {
1096                 msleep(10);
1097                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1098                 /* FIXME: 100 tries seem excessive */
1099                 if (tries++ > 100)
1100                         return -1;
1101         }
1102         return 0;
1103 }
1104
1105 static int phy_init(struct net_device *dev)
1106 {
1107         struct fe_priv *np = get_nvpriv(dev);
1108         u8 __iomem *base = get_hwbase(dev);
1109         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1110
1111         /* phy errata for E3016 phy */
1112         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1113                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1114                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1115                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1116                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1117                         return PHY_ERROR;
1118                 }
1119         }
1120         if (np->phy_oui == PHY_OUI_REALTEK) {
1121                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1122                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1123                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1124                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1125                                 return PHY_ERROR;
1126                         }
1127                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1128                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1129                                 return PHY_ERROR;
1130                         }
1131                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1132                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1133                                 return PHY_ERROR;
1134                         }
1135                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1136                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137                                 return PHY_ERROR;
1138                         }
1139                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1140                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1141                                 return PHY_ERROR;
1142                         }
1143                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1144                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145                                 return PHY_ERROR;
1146                         }
1147                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1148                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                                 return PHY_ERROR;
1150                         }
1151                 }
1152                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1153                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1154                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1155                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1156                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1157                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1158                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1159                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1160                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1161                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1162                                 phy_reserved |= PHY_REALTEK_INIT7;
1163                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1164                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165                                         return PHY_ERROR;
1166                                 }
1167                         }
1168                 }
1169         }
1170
1171         /* set advertise register */
1172         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1173         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1174         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1175                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1176                 return PHY_ERROR;
1177         }
1178
1179         /* get phy interface type */
1180         phyinterface = readl(base + NvRegPhyInterface);
1181
1182         /* see if gigabit phy */
1183         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1184         if (mii_status & PHY_GIGABIT) {
1185                 np->gigabit = PHY_GIGABIT;
1186                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1187                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1188                 if (phyinterface & PHY_RGMII)
1189                         mii_control_1000 |= ADVERTISE_1000FULL;
1190                 else
1191                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1192
1193                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1194                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1195                         return PHY_ERROR;
1196                 }
1197         }
1198         else
1199                 np->gigabit = 0;
1200
1201         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1202         mii_control |= BMCR_ANENABLE;
1203
1204         /* reset the phy
1205          * (certain phys need bmcr to be setup with reset)
1206          */
1207         if (phy_reset(dev, mii_control)) {
1208                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1209                 return PHY_ERROR;
1210         }
1211
1212         /* phy vendor specific configuration */
1213         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1214                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1215                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1216                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1217                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1218                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219                         return PHY_ERROR;
1220                 }
1221                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1222                 phy_reserved |= PHY_CICADA_INIT5;
1223                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1224                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225                         return PHY_ERROR;
1226                 }
1227         }
1228         if (np->phy_oui == PHY_OUI_CICADA) {
1229                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1230                 phy_reserved |= PHY_CICADA_INIT6;
1231                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1232                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233                         return PHY_ERROR;
1234                 }
1235         }
1236         if (np->phy_oui == PHY_OUI_VITESSE) {
1237                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1238                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                         return PHY_ERROR;
1240                 }
1241                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1242                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1243                         return PHY_ERROR;
1244                 }
1245                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1246                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1247                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1248                         return PHY_ERROR;
1249                 }
1250                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1251                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1252                 phy_reserved |= PHY_VITESSE_INIT3;
1253                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1254                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255                         return PHY_ERROR;
1256                 }
1257                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1258                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259                         return PHY_ERROR;
1260                 }
1261                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1262                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1263                         return PHY_ERROR;
1264                 }
1265                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1266                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1267                 phy_reserved |= PHY_VITESSE_INIT3;
1268                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1269                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270                         return PHY_ERROR;
1271                 }
1272                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1273                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1274                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275                         return PHY_ERROR;
1276                 }
1277                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1278                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1279                         return PHY_ERROR;
1280                 }
1281                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1282                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1283                         return PHY_ERROR;
1284                 }
1285                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1286                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1287                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1288                         return PHY_ERROR;
1289                 }
1290                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1291                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1292                 phy_reserved |= PHY_VITESSE_INIT8;
1293                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1294                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1295                         return PHY_ERROR;
1296                 }
1297                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1298                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1299                         return PHY_ERROR;
1300                 }
1301                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1302                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1303                         return PHY_ERROR;
1304                 }
1305         }
1306         if (np->phy_oui == PHY_OUI_REALTEK) {
1307                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1308                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1309                         /* reset could have cleared these out, set them back */
1310                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1311                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1312                                 return PHY_ERROR;
1313                         }
1314                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1315                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1316                                 return PHY_ERROR;
1317                         }
1318                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1319                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1320                                 return PHY_ERROR;
1321                         }
1322                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1323                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324                                 return PHY_ERROR;
1325                         }
1326                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1327                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328                                 return PHY_ERROR;
1329                         }
1330                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1331                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332                                 return PHY_ERROR;
1333                         }
1334                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1335                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336                                 return PHY_ERROR;
1337                         }
1338                 }
1339                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1340                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1341                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1342                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1343                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1344                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1345                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1346                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1347                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1348                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1349                                 phy_reserved |= PHY_REALTEK_INIT7;
1350                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1351                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1352                                         return PHY_ERROR;
1353                                 }
1354                         }
1355                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1356                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1357                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1358                                         return PHY_ERROR;
1359                                 }
1360                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1361                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1362                                 phy_reserved |= PHY_REALTEK_INIT3;
1363                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1364                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365                                         return PHY_ERROR;
1366                                 }
1367                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1368                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369                                         return PHY_ERROR;
1370                                 }
1371                         }
1372                 }
1373         }
1374
1375         /* some phys clear out pause advertisment on reset, set it back */
1376         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1377
1378         /* restart auto negotiation */
1379         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1380         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1381         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1382                 return PHY_ERROR;
1383         }
1384
1385         return 0;
1386 }
1387
1388 static void nv_start_rx(struct net_device *dev)
1389 {
1390         struct fe_priv *np = netdev_priv(dev);
1391         u8 __iomem *base = get_hwbase(dev);
1392         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1393
1394         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1395         /* Already running? Stop it. */
1396         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1397                 rx_ctrl &= ~NVREG_RCVCTL_START;
1398                 writel(rx_ctrl, base + NvRegReceiverControl);
1399                 pci_push(base);
1400         }
1401         writel(np->linkspeed, base + NvRegLinkSpeed);
1402         pci_push(base);
1403         rx_ctrl |= NVREG_RCVCTL_START;
1404         if (np->mac_in_use)
1405                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1406         writel(rx_ctrl, base + NvRegReceiverControl);
1407         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1408                                 dev->name, np->duplex, np->linkspeed);
1409         pci_push(base);
1410 }
1411
1412 static void nv_stop_rx(struct net_device *dev)
1413 {
1414         struct fe_priv *np = netdev_priv(dev);
1415         u8 __iomem *base = get_hwbase(dev);
1416         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1417
1418         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1419         if (!np->mac_in_use)
1420                 rx_ctrl &= ~NVREG_RCVCTL_START;
1421         else
1422                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1423         writel(rx_ctrl, base + NvRegReceiverControl);
1424         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1425                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1426                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1427
1428         udelay(NV_RXSTOP_DELAY2);
1429         if (!np->mac_in_use)
1430                 writel(0, base + NvRegLinkSpeed);
1431 }
1432
1433 static void nv_start_tx(struct net_device *dev)
1434 {
1435         struct fe_priv *np = netdev_priv(dev);
1436         u8 __iomem *base = get_hwbase(dev);
1437         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1438
1439         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1440         tx_ctrl |= NVREG_XMITCTL_START;
1441         if (np->mac_in_use)
1442                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1443         writel(tx_ctrl, base + NvRegTransmitterControl);
1444         pci_push(base);
1445 }
1446
1447 static void nv_stop_tx(struct net_device *dev)
1448 {
1449         struct fe_priv *np = netdev_priv(dev);
1450         u8 __iomem *base = get_hwbase(dev);
1451         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1452
1453         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1454         if (!np->mac_in_use)
1455                 tx_ctrl &= ~NVREG_XMITCTL_START;
1456         else
1457                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1458         writel(tx_ctrl, base + NvRegTransmitterControl);
1459         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1460                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1461                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1462
1463         udelay(NV_TXSTOP_DELAY2);
1464         if (!np->mac_in_use)
1465                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1466                        base + NvRegTransmitPoll);
1467 }
1468
1469 static void nv_start_rxtx(struct net_device *dev)
1470 {
1471         nv_start_rx(dev);
1472         nv_start_tx(dev);
1473 }
1474
1475 static void nv_stop_rxtx(struct net_device *dev)
1476 {
1477         nv_stop_rx(dev);
1478         nv_stop_tx(dev);
1479 }
1480
1481 static void nv_txrx_reset(struct net_device *dev)
1482 {
1483         struct fe_priv *np = netdev_priv(dev);
1484         u8 __iomem *base = get_hwbase(dev);
1485
1486         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1487         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1488         pci_push(base);
1489         udelay(NV_TXRX_RESET_DELAY);
1490         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1491         pci_push(base);
1492 }
1493
1494 static void nv_mac_reset(struct net_device *dev)
1495 {
1496         struct fe_priv *np = netdev_priv(dev);
1497         u8 __iomem *base = get_hwbase(dev);
1498         u32 temp1, temp2, temp3;
1499
1500         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1501
1502         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1503         pci_push(base);
1504
1505         /* save registers since they will be cleared on reset */
1506         temp1 = readl(base + NvRegMacAddrA);
1507         temp2 = readl(base + NvRegMacAddrB);
1508         temp3 = readl(base + NvRegTransmitPoll);
1509
1510         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1511         pci_push(base);
1512         udelay(NV_MAC_RESET_DELAY);
1513         writel(0, base + NvRegMacReset);
1514         pci_push(base);
1515         udelay(NV_MAC_RESET_DELAY);
1516
1517         /* restore saved registers */
1518         writel(temp1, base + NvRegMacAddrA);
1519         writel(temp2, base + NvRegMacAddrB);
1520         writel(temp3, base + NvRegTransmitPoll);
1521
1522         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1523         pci_push(base);
1524 }
1525
1526 static void nv_get_hw_stats(struct net_device *dev)
1527 {
1528         struct fe_priv *np = netdev_priv(dev);
1529         u8 __iomem *base = get_hwbase(dev);
1530
1531         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1532         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1533         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1534         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1535         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1536         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1537         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1538         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1539         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1540         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1541         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1542         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1543         np->estats.rx_runt += readl(base + NvRegRxRunt);
1544         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1545         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1546         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1547         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1548         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1549         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1550         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1551         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1552         np->estats.rx_packets =
1553                 np->estats.rx_unicast +
1554                 np->estats.rx_multicast +
1555                 np->estats.rx_broadcast;
1556         np->estats.rx_errors_total =
1557                 np->estats.rx_crc_errors +
1558                 np->estats.rx_over_errors +
1559                 np->estats.rx_frame_error +
1560                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1561                 np->estats.rx_late_collision +
1562                 np->estats.rx_runt +
1563                 np->estats.rx_frame_too_long;
1564         np->estats.tx_errors_total =
1565                 np->estats.tx_late_collision +
1566                 np->estats.tx_fifo_errors +
1567                 np->estats.tx_carrier_errors +
1568                 np->estats.tx_excess_deferral +
1569                 np->estats.tx_retry_error;
1570
1571         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1572                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1573                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1574                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1575                 np->estats.tx_pause += readl(base + NvRegTxPause);
1576                 np->estats.rx_pause += readl(base + NvRegRxPause);
1577                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1578         }
1579 }
1580
1581 /*
1582  * nv_get_stats: dev->get_stats function
1583  * Get latest stats value from the nic.
1584  * Called with read_lock(&dev_base_lock) held for read -
1585  * only synchronized against unregister_netdevice.
1586  */
1587 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1588 {
1589         struct fe_priv *np = netdev_priv(dev);
1590
1591         /* If the nic supports hw counters then retrieve latest values */
1592         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1593                 nv_get_hw_stats(dev);
1594
1595                 /* copy to net_device stats */
1596                 dev->stats.tx_bytes = np->estats.tx_bytes;
1597                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1598                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1599                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1600                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1601                 dev->stats.rx_errors = np->estats.rx_errors_total;
1602                 dev->stats.tx_errors = np->estats.tx_errors_total;
1603         }
1604
1605         return &dev->stats;
1606 }
1607
1608 /*
1609  * nv_alloc_rx: fill rx ring entries.
1610  * Return 1 if the allocations for the skbs failed and the
1611  * rx engine is without Available descriptors
1612  */
1613 static int nv_alloc_rx(struct net_device *dev)
1614 {
1615         struct fe_priv *np = netdev_priv(dev);
1616         struct ring_desc* less_rx;
1617
1618         less_rx = np->get_rx.orig;
1619         if (less_rx-- == np->first_rx.orig)
1620                 less_rx = np->last_rx.orig;
1621
1622         while (np->put_rx.orig != less_rx) {
1623                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1624                 if (skb) {
1625                         np->put_rx_ctx->skb = skb;
1626                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1627                                                              skb->data,
1628                                                              skb_tailroom(skb),
1629                                                              PCI_DMA_FROMDEVICE);
1630                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1631                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1632                         wmb();
1633                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1634                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1635                                 np->put_rx.orig = np->first_rx.orig;
1636                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1637                                 np->put_rx_ctx = np->first_rx_ctx;
1638                 } else {
1639                         return 1;
1640                 }
1641         }
1642         return 0;
1643 }
1644
1645 static int nv_alloc_rx_optimized(struct net_device *dev)
1646 {
1647         struct fe_priv *np = netdev_priv(dev);
1648         struct ring_desc_ex* less_rx;
1649
1650         less_rx = np->get_rx.ex;
1651         if (less_rx-- == np->first_rx.ex)
1652                 less_rx = np->last_rx.ex;
1653
1654         while (np->put_rx.ex != less_rx) {
1655                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1656                 if (skb) {
1657                         np->put_rx_ctx->skb = skb;
1658                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1659                                                              skb->data,
1660                                                              skb_tailroom(skb),
1661                                                              PCI_DMA_FROMDEVICE);
1662                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1663                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1664                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1665                         wmb();
1666                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1667                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1668                                 np->put_rx.ex = np->first_rx.ex;
1669                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1670                                 np->put_rx_ctx = np->first_rx_ctx;
1671                 } else {
1672                         return 1;
1673                 }
1674         }
1675         return 0;
1676 }
1677
1678 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1679 #ifdef CONFIG_FORCEDETH_NAPI
1680 static void nv_do_rx_refill(unsigned long data)
1681 {
1682         struct net_device *dev = (struct net_device *) data;
1683         struct fe_priv *np = netdev_priv(dev);
1684
1685         /* Just reschedule NAPI rx processing */
1686         netif_rx_schedule(dev, &np->napi);
1687 }
1688 #else
1689 static void nv_do_rx_refill(unsigned long data)
1690 {
1691         struct net_device *dev = (struct net_device *) data;
1692         struct fe_priv *np = netdev_priv(dev);
1693         int retcode;
1694
1695         if (!using_multi_irqs(dev)) {
1696                 if (np->msi_flags & NV_MSI_X_ENABLED)
1697                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1698                 else
1699                         disable_irq(np->pci_dev->irq);
1700         } else {
1701                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1702         }
1703         if (!nv_optimized(np))
1704                 retcode = nv_alloc_rx(dev);
1705         else
1706                 retcode = nv_alloc_rx_optimized(dev);
1707         if (retcode) {
1708                 spin_lock_irq(&np->lock);
1709                 if (!np->in_shutdown)
1710                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1711                 spin_unlock_irq(&np->lock);
1712         }
1713         if (!using_multi_irqs(dev)) {
1714                 if (np->msi_flags & NV_MSI_X_ENABLED)
1715                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1716                 else
1717                         enable_irq(np->pci_dev->irq);
1718         } else {
1719                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1720         }
1721 }
1722 #endif
1723
1724 static void nv_init_rx(struct net_device *dev)
1725 {
1726         struct fe_priv *np = netdev_priv(dev);
1727         int i;
1728
1729         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1730
1731         if (!nv_optimized(np))
1732                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1733         else
1734                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1735         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1736         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1737
1738         for (i = 0; i < np->rx_ring_size; i++) {
1739                 if (!nv_optimized(np)) {
1740                         np->rx_ring.orig[i].flaglen = 0;
1741                         np->rx_ring.orig[i].buf = 0;
1742                 } else {
1743                         np->rx_ring.ex[i].flaglen = 0;
1744                         np->rx_ring.ex[i].txvlan = 0;
1745                         np->rx_ring.ex[i].bufhigh = 0;
1746                         np->rx_ring.ex[i].buflow = 0;
1747                 }
1748                 np->rx_skb[i].skb = NULL;
1749                 np->rx_skb[i].dma = 0;
1750         }
1751 }
1752
1753 static void nv_init_tx(struct net_device *dev)
1754 {
1755         struct fe_priv *np = netdev_priv(dev);
1756         int i;
1757
1758         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1759
1760         if (!nv_optimized(np))
1761                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1762         else
1763                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1764         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1765         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1766         np->tx_pkts_in_progress = 0;
1767         np->tx_change_owner = NULL;
1768         np->tx_end_flip = NULL;
1769
1770         for (i = 0; i < np->tx_ring_size; i++) {
1771                 if (!nv_optimized(np)) {
1772                         np->tx_ring.orig[i].flaglen = 0;
1773                         np->tx_ring.orig[i].buf = 0;
1774                 } else {
1775                         np->tx_ring.ex[i].flaglen = 0;
1776                         np->tx_ring.ex[i].txvlan = 0;
1777                         np->tx_ring.ex[i].bufhigh = 0;
1778                         np->tx_ring.ex[i].buflow = 0;
1779                 }
1780                 np->tx_skb[i].skb = NULL;
1781                 np->tx_skb[i].dma = 0;
1782                 np->tx_skb[i].dma_len = 0;
1783                 np->tx_skb[i].first_tx_desc = NULL;
1784                 np->tx_skb[i].next_tx_ctx = NULL;
1785         }
1786 }
1787
1788 static int nv_init_ring(struct net_device *dev)
1789 {
1790         struct fe_priv *np = netdev_priv(dev);
1791
1792         nv_init_tx(dev);
1793         nv_init_rx(dev);
1794
1795         if (!nv_optimized(np))
1796                 return nv_alloc_rx(dev);
1797         else
1798                 return nv_alloc_rx_optimized(dev);
1799 }
1800
1801 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1802 {
1803         struct fe_priv *np = netdev_priv(dev);
1804
1805         if (tx_skb->dma) {
1806                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1807                                tx_skb->dma_len,
1808                                PCI_DMA_TODEVICE);
1809                 tx_skb->dma = 0;
1810         }
1811         if (tx_skb->skb) {
1812                 dev_kfree_skb_any(tx_skb->skb);
1813                 tx_skb->skb = NULL;
1814                 return 1;
1815         } else {
1816                 return 0;
1817         }
1818 }
1819
1820 static void nv_drain_tx(struct net_device *dev)
1821 {
1822         struct fe_priv *np = netdev_priv(dev);
1823         unsigned int i;
1824
1825         for (i = 0; i < np->tx_ring_size; i++) {
1826                 if (!nv_optimized(np)) {
1827                         np->tx_ring.orig[i].flaglen = 0;
1828                         np->tx_ring.orig[i].buf = 0;
1829                 } else {
1830                         np->tx_ring.ex[i].flaglen = 0;
1831                         np->tx_ring.ex[i].txvlan = 0;
1832                         np->tx_ring.ex[i].bufhigh = 0;
1833                         np->tx_ring.ex[i].buflow = 0;
1834                 }
1835                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1836                         dev->stats.tx_dropped++;
1837                 np->tx_skb[i].dma = 0;
1838                 np->tx_skb[i].dma_len = 0;
1839                 np->tx_skb[i].first_tx_desc = NULL;
1840                 np->tx_skb[i].next_tx_ctx = NULL;
1841         }
1842         np->tx_pkts_in_progress = 0;
1843         np->tx_change_owner = NULL;
1844         np->tx_end_flip = NULL;
1845 }
1846
1847 static void nv_drain_rx(struct net_device *dev)
1848 {
1849         struct fe_priv *np = netdev_priv(dev);
1850         int i;
1851
1852         for (i = 0; i < np->rx_ring_size; i++) {
1853                 if (!nv_optimized(np)) {
1854                         np->rx_ring.orig[i].flaglen = 0;
1855                         np->rx_ring.orig[i].buf = 0;
1856                 } else {
1857                         np->rx_ring.ex[i].flaglen = 0;
1858                         np->rx_ring.ex[i].txvlan = 0;
1859                         np->rx_ring.ex[i].bufhigh = 0;
1860                         np->rx_ring.ex[i].buflow = 0;
1861                 }
1862                 wmb();
1863                 if (np->rx_skb[i].skb) {
1864                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1865                                          (skb_end_pointer(np->rx_skb[i].skb) -
1866                                           np->rx_skb[i].skb->data),
1867                                          PCI_DMA_FROMDEVICE);
1868                         dev_kfree_skb(np->rx_skb[i].skb);
1869                         np->rx_skb[i].skb = NULL;
1870                 }
1871         }
1872 }
1873
1874 static void nv_drain_rxtx(struct net_device *dev)
1875 {
1876         nv_drain_tx(dev);
1877         nv_drain_rx(dev);
1878 }
1879
1880 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1881 {
1882         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1883 }
1884
1885 static void nv_legacybackoff_reseed(struct net_device *dev)
1886 {
1887         u8 __iomem *base = get_hwbase(dev);
1888         u32 reg;
1889         u32 low;
1890         int tx_status = 0;
1891
1892         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1893         get_random_bytes(&low, sizeof(low));
1894         reg |= low & NVREG_SLOTTIME_MASK;
1895
1896         /* Need to stop tx before change takes effect.
1897          * Caller has already gained np->lock.
1898          */
1899         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1900         if (tx_status)
1901                 nv_stop_tx(dev);
1902         nv_stop_rx(dev);
1903         writel(reg, base + NvRegSlotTime);
1904         if (tx_status)
1905                 nv_start_tx(dev);
1906         nv_start_rx(dev);
1907 }
1908
1909 /* Gear Backoff Seeds */
1910 #define BACKOFF_SEEDSET_ROWS    8
1911 #define BACKOFF_SEEDSET_LFSRS   15
1912
1913 /* Known Good seed sets */
1914 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1915     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1916     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1917     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1918     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1919     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1920     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1921     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
1922     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1923
1924 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1925     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1926     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1928     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1929     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
1930     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1931     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1932     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1933
1934 static void nv_gear_backoff_reseed(struct net_device *dev)
1935 {
1936         u8 __iomem *base = get_hwbase(dev);
1937         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
1938         u32 temp, seedset, combinedSeed;
1939         int i;
1940
1941         /* Setup seed for free running LFSR */
1942         /* We are going to read the time stamp counter 3 times
1943            and swizzle bits around to increase randomness */
1944         get_random_bytes(&miniseed1, sizeof(miniseed1));
1945         miniseed1 &= 0x0fff;
1946         if (miniseed1 == 0)
1947                 miniseed1 = 0xabc;
1948
1949         get_random_bytes(&miniseed2, sizeof(miniseed2));
1950         miniseed2 &= 0x0fff;
1951         if (miniseed2 == 0)
1952                 miniseed2 = 0xabc;
1953         miniseed2_reversed =
1954                 ((miniseed2 & 0xF00) >> 8) |
1955                  (miniseed2 & 0x0F0) |
1956                  ((miniseed2 & 0x00F) << 8);
1957
1958         get_random_bytes(&miniseed3, sizeof(miniseed3));
1959         miniseed3 &= 0x0fff;
1960         if (miniseed3 == 0)
1961                 miniseed3 = 0xabc;
1962         miniseed3_reversed =
1963                 ((miniseed3 & 0xF00) >> 8) |
1964                  (miniseed3 & 0x0F0) |
1965                  ((miniseed3 & 0x00F) << 8);
1966
1967         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
1968                        (miniseed2 ^ miniseed3_reversed);
1969
1970         /* Seeds can not be zero */
1971         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
1972                 combinedSeed |= 0x08;
1973         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
1974                 combinedSeed |= 0x8000;
1975
1976         /* No need to disable tx here */
1977         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
1978         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
1979         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
1980         writel(temp,base + NvRegBackOffControl);
1981
1982         /* Setup seeds for all gear LFSRs. */
1983         get_random_bytes(&seedset, sizeof(seedset));
1984         seedset = seedset % BACKOFF_SEEDSET_ROWS;
1985         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
1986         {
1987                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
1988                 temp |= main_seedset[seedset][i-1] & 0x3ff;
1989                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
1990                 writel(temp, base + NvRegBackOffControl);
1991         }
1992 }
1993
1994 /*
1995  * nv_start_xmit: dev->hard_start_xmit function
1996  * Called with netif_tx_lock held.
1997  */
1998 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1999 {
2000         struct fe_priv *np = netdev_priv(dev);
2001         u32 tx_flags = 0;
2002         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2003         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2004         unsigned int i;
2005         u32 offset = 0;
2006         u32 bcnt;
2007         u32 size = skb->len-skb->data_len;
2008         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2009         u32 empty_slots;
2010         struct ring_desc* put_tx;
2011         struct ring_desc* start_tx;
2012         struct ring_desc* prev_tx;
2013         struct nv_skb_map* prev_tx_ctx;
2014         unsigned long flags;
2015
2016         /* add fragments to entries count */
2017         for (i = 0; i < fragments; i++) {
2018                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2019                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2020         }
2021
2022         empty_slots = nv_get_empty_tx_slots(np);
2023         if (unlikely(empty_slots <= entries)) {
2024                 spin_lock_irqsave(&np->lock, flags);
2025                 netif_stop_queue(dev);
2026                 np->tx_stop = 1;
2027                 spin_unlock_irqrestore(&np->lock, flags);
2028                 return NETDEV_TX_BUSY;
2029         }
2030
2031         start_tx = put_tx = np->put_tx.orig;
2032
2033         /* setup the header buffer */
2034         do {
2035                 prev_tx = put_tx;
2036                 prev_tx_ctx = np->put_tx_ctx;
2037                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2038                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2039                                                 PCI_DMA_TODEVICE);
2040                 np->put_tx_ctx->dma_len = bcnt;
2041                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2042                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2043
2044                 tx_flags = np->tx_flags;
2045                 offset += bcnt;
2046                 size -= bcnt;
2047                 if (unlikely(put_tx++ == np->last_tx.orig))
2048                         put_tx = np->first_tx.orig;
2049                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2050                         np->put_tx_ctx = np->first_tx_ctx;
2051         } while (size);
2052
2053         /* setup the fragments */
2054         for (i = 0; i < fragments; i++) {
2055                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2056                 u32 size = frag->size;
2057                 offset = 0;
2058
2059                 do {
2060                         prev_tx = put_tx;
2061                         prev_tx_ctx = np->put_tx_ctx;
2062                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2063                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2064                                                            PCI_DMA_TODEVICE);
2065                         np->put_tx_ctx->dma_len = bcnt;
2066                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2067                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2068
2069                         offset += bcnt;
2070                         size -= bcnt;
2071                         if (unlikely(put_tx++ == np->last_tx.orig))
2072                                 put_tx = np->first_tx.orig;
2073                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2074                                 np->put_tx_ctx = np->first_tx_ctx;
2075                 } while (size);
2076         }
2077
2078         /* set last fragment flag  */
2079         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2080
2081         /* save skb in this slot's context area */
2082         prev_tx_ctx->skb = skb;
2083
2084         if (skb_is_gso(skb))
2085                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2086         else
2087                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2088                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2089
2090         spin_lock_irqsave(&np->lock, flags);
2091
2092         /* set tx flags */
2093         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2094         np->put_tx.orig = put_tx;
2095
2096         spin_unlock_irqrestore(&np->lock, flags);
2097
2098         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2099                 dev->name, entries, tx_flags_extra);
2100         {
2101                 int j;
2102                 for (j=0; j<64; j++) {
2103                         if ((j%16) == 0)
2104                                 dprintk("\n%03x:", j);
2105                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2106                 }
2107                 dprintk("\n");
2108         }
2109
2110         dev->trans_start = jiffies;
2111         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2112         return NETDEV_TX_OK;
2113 }
2114
2115 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2116 {
2117         struct fe_priv *np = netdev_priv(dev);
2118         u32 tx_flags = 0;
2119         u32 tx_flags_extra;
2120         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2121         unsigned int i;
2122         u32 offset = 0;
2123         u32 bcnt;
2124         u32 size = skb->len-skb->data_len;
2125         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2126         u32 empty_slots;
2127         struct ring_desc_ex* put_tx;
2128         struct ring_desc_ex* start_tx;
2129         struct ring_desc_ex* prev_tx;
2130         struct nv_skb_map* prev_tx_ctx;
2131         struct nv_skb_map* start_tx_ctx;
2132         unsigned long flags;
2133
2134         /* add fragments to entries count */
2135         for (i = 0; i < fragments; i++) {
2136                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2137                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2138         }
2139
2140         empty_slots = nv_get_empty_tx_slots(np);
2141         if (unlikely(empty_slots <= entries)) {
2142                 spin_lock_irqsave(&np->lock, flags);
2143                 netif_stop_queue(dev);
2144                 np->tx_stop = 1;
2145                 spin_unlock_irqrestore(&np->lock, flags);
2146                 return NETDEV_TX_BUSY;
2147         }
2148
2149         start_tx = put_tx = np->put_tx.ex;
2150         start_tx_ctx = np->put_tx_ctx;
2151
2152         /* setup the header buffer */
2153         do {
2154                 prev_tx = put_tx;
2155                 prev_tx_ctx = np->put_tx_ctx;
2156                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2157                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2158                                                 PCI_DMA_TODEVICE);
2159                 np->put_tx_ctx->dma_len = bcnt;
2160                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2161                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2162                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2163
2164                 tx_flags = NV_TX2_VALID;
2165                 offset += bcnt;
2166                 size -= bcnt;
2167                 if (unlikely(put_tx++ == np->last_tx.ex))
2168                         put_tx = np->first_tx.ex;
2169                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2170                         np->put_tx_ctx = np->first_tx_ctx;
2171         } while (size);
2172
2173         /* setup the fragments */
2174         for (i = 0; i < fragments; i++) {
2175                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2176                 u32 size = frag->size;
2177                 offset = 0;
2178
2179                 do {
2180                         prev_tx = put_tx;
2181                         prev_tx_ctx = np->put_tx_ctx;
2182                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2183                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2184                                                            PCI_DMA_TODEVICE);
2185                         np->put_tx_ctx->dma_len = bcnt;
2186                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2187                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2188                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2189
2190                         offset += bcnt;
2191                         size -= bcnt;
2192                         if (unlikely(put_tx++ == np->last_tx.ex))
2193                                 put_tx = np->first_tx.ex;
2194                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2195                                 np->put_tx_ctx = np->first_tx_ctx;
2196                 } while (size);
2197         }
2198
2199         /* set last fragment flag  */
2200         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2201
2202         /* save skb in this slot's context area */
2203         prev_tx_ctx->skb = skb;
2204
2205         if (skb_is_gso(skb))
2206                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2207         else
2208                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2209                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2210
2211         /* vlan tag */
2212         if (likely(!np->vlangrp)) {
2213                 start_tx->txvlan = 0;
2214         } else {
2215                 if (vlan_tx_tag_present(skb))
2216                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2217                 else
2218                         start_tx->txvlan = 0;
2219         }
2220
2221         spin_lock_irqsave(&np->lock, flags);
2222
2223         if (np->tx_limit) {
2224                 /* Limit the number of outstanding tx. Setup all fragments, but
2225                  * do not set the VALID bit on the first descriptor. Save a pointer
2226                  * to that descriptor and also for next skb_map element.
2227                  */
2228
2229                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2230                         if (!np->tx_change_owner)
2231                                 np->tx_change_owner = start_tx_ctx;
2232
2233                         /* remove VALID bit */
2234                         tx_flags &= ~NV_TX2_VALID;
2235                         start_tx_ctx->first_tx_desc = start_tx;
2236                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2237                         np->tx_end_flip = np->put_tx_ctx;
2238                 } else {
2239                         np->tx_pkts_in_progress++;
2240                 }
2241         }
2242
2243         /* set tx flags */
2244         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2245         np->put_tx.ex = put_tx;
2246
2247         spin_unlock_irqrestore(&np->lock, flags);
2248
2249         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2250                 dev->name, entries, tx_flags_extra);
2251         {
2252                 int j;
2253                 for (j=0; j<64; j++) {
2254                         if ((j%16) == 0)
2255                                 dprintk("\n%03x:", j);
2256                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2257                 }
2258                 dprintk("\n");
2259         }
2260
2261         dev->trans_start = jiffies;
2262         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2263         return NETDEV_TX_OK;
2264 }
2265
2266 static inline void nv_tx_flip_ownership(struct net_device *dev)
2267 {
2268         struct fe_priv *np = netdev_priv(dev);
2269
2270         np->tx_pkts_in_progress--;
2271         if (np->tx_change_owner) {
2272                 np->tx_change_owner->first_tx_desc->flaglen |=
2273                         cpu_to_le32(NV_TX2_VALID);
2274                 np->tx_pkts_in_progress++;
2275
2276                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2277                 if (np->tx_change_owner == np->tx_end_flip)
2278                         np->tx_change_owner = NULL;
2279
2280                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2281         }
2282 }
2283
2284 /*
2285  * nv_tx_done: check for completed packets, release the skbs.
2286  *
2287  * Caller must own np->lock.
2288  */
2289 static void nv_tx_done(struct net_device *dev)
2290 {
2291         struct fe_priv *np = netdev_priv(dev);
2292         u32 flags;
2293         struct ring_desc* orig_get_tx = np->get_tx.orig;
2294
2295         while ((np->get_tx.orig != np->put_tx.orig) &&
2296                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2297
2298                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2299                                         dev->name, flags);
2300
2301                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2302                                np->get_tx_ctx->dma_len,
2303                                PCI_DMA_TODEVICE);
2304                 np->get_tx_ctx->dma = 0;
2305
2306                 if (np->desc_ver == DESC_VER_1) {
2307                         if (flags & NV_TX_LASTPACKET) {
2308                                 if (flags & NV_TX_ERROR) {
2309                                         if (flags & NV_TX_UNDERFLOW)
2310                                                 dev->stats.tx_fifo_errors++;
2311                                         if (flags & NV_TX_CARRIERLOST)
2312                                                 dev->stats.tx_carrier_errors++;
2313                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2314                                                 nv_legacybackoff_reseed(dev);
2315                                         dev->stats.tx_errors++;
2316                                 } else {
2317                                         dev->stats.tx_packets++;
2318                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2319                                 }
2320                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2321                                 np->get_tx_ctx->skb = NULL;
2322                         }
2323                 } else {
2324                         if (flags & NV_TX2_LASTPACKET) {
2325                                 if (flags & NV_TX2_ERROR) {
2326                                         if (flags & NV_TX2_UNDERFLOW)
2327                                                 dev->stats.tx_fifo_errors++;
2328                                         if (flags & NV_TX2_CARRIERLOST)
2329                                                 dev->stats.tx_carrier_errors++;
2330                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2331                                                 nv_legacybackoff_reseed(dev);
2332                                         dev->stats.tx_errors++;
2333                                 } else {
2334                                         dev->stats.tx_packets++;
2335                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2336                                 }
2337                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2338                                 np->get_tx_ctx->skb = NULL;
2339                         }
2340                 }
2341                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2342                         np->get_tx.orig = np->first_tx.orig;
2343                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2344                         np->get_tx_ctx = np->first_tx_ctx;
2345         }
2346         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2347                 np->tx_stop = 0;
2348                 netif_wake_queue(dev);
2349         }
2350 }
2351
2352 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2353 {
2354         struct fe_priv *np = netdev_priv(dev);
2355         u32 flags;
2356         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2357
2358         while ((np->get_tx.ex != np->put_tx.ex) &&
2359                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2360                (limit-- > 0)) {
2361
2362                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2363                                         dev->name, flags);
2364
2365                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2366                                np->get_tx_ctx->dma_len,
2367                                PCI_DMA_TODEVICE);
2368                 np->get_tx_ctx->dma = 0;
2369
2370                 if (flags & NV_TX2_LASTPACKET) {
2371                         if (!(flags & NV_TX2_ERROR))
2372                                 dev->stats.tx_packets++;
2373                         else {
2374                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2375                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2376                                                 nv_gear_backoff_reseed(dev);
2377                                         else
2378                                                 nv_legacybackoff_reseed(dev);
2379                                 }
2380                         }
2381
2382                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2383                         np->get_tx_ctx->skb = NULL;
2384
2385                         if (np->tx_limit) {
2386                                 nv_tx_flip_ownership(dev);
2387                         }
2388                 }
2389                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2390                         np->get_tx.ex = np->first_tx.ex;
2391                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2392                         np->get_tx_ctx = np->first_tx_ctx;
2393         }
2394         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2395                 np->tx_stop = 0;
2396                 netif_wake_queue(dev);
2397         }
2398 }
2399
2400 /*
2401  * nv_tx_timeout: dev->tx_timeout function
2402  * Called with netif_tx_lock held.
2403  */
2404 static void nv_tx_timeout(struct net_device *dev)
2405 {
2406         struct fe_priv *np = netdev_priv(dev);
2407         u8 __iomem *base = get_hwbase(dev);
2408         u32 status;
2409
2410         if (np->msi_flags & NV_MSI_X_ENABLED)
2411                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2412         else
2413                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2414
2415         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2416
2417         {
2418                 int i;
2419
2420                 printk(KERN_INFO "%s: Ring at %lx\n",
2421                        dev->name, (unsigned long)np->ring_addr);
2422                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2423                 for (i=0;i<=np->register_size;i+= 32) {
2424                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2425                                         i,
2426                                         readl(base + i + 0), readl(base + i + 4),
2427                                         readl(base + i + 8), readl(base + i + 12),
2428                                         readl(base + i + 16), readl(base + i + 20),
2429                                         readl(base + i + 24), readl(base + i + 28));
2430                 }
2431                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2432                 for (i=0;i<np->tx_ring_size;i+= 4) {
2433                         if (!nv_optimized(np)) {
2434                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2435                                        i,
2436                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2437                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2438                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2439                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2440                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2441                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2442                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2443                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2444                         } else {
2445                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2446                                        i,
2447                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2448                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2449                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2450                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2451                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2452                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2453                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2454                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2455                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2456                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2457                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2458                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2459                         }
2460                 }
2461         }
2462
2463         spin_lock_irq(&np->lock);
2464
2465         /* 1) stop tx engine */
2466         nv_stop_tx(dev);
2467
2468         /* 2) check that the packets were not sent already: */
2469         if (!nv_optimized(np))
2470                 nv_tx_done(dev);
2471         else
2472                 nv_tx_done_optimized(dev, np->tx_ring_size);
2473
2474         /* 3) if there are dead entries: clear everything */
2475         if (np->get_tx_ctx != np->put_tx_ctx) {
2476                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2477                 nv_drain_tx(dev);
2478                 nv_init_tx(dev);
2479                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2480         }
2481
2482         netif_wake_queue(dev);
2483
2484         /* 4) restart tx engine */
2485         nv_start_tx(dev);
2486         spin_unlock_irq(&np->lock);
2487 }
2488
2489 /*
2490  * Called when the nic notices a mismatch between the actual data len on the
2491  * wire and the len indicated in the 802 header
2492  */
2493 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2494 {
2495         int hdrlen;     /* length of the 802 header */
2496         int protolen;   /* length as stored in the proto field */
2497
2498         /* 1) calculate len according to header */
2499         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2500                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2501                 hdrlen = VLAN_HLEN;
2502         } else {
2503                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2504                 hdrlen = ETH_HLEN;
2505         }
2506         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2507                                 dev->name, datalen, protolen, hdrlen);
2508         if (protolen > ETH_DATA_LEN)
2509                 return datalen; /* Value in proto field not a len, no checks possible */
2510
2511         protolen += hdrlen;
2512         /* consistency checks: */
2513         if (datalen > ETH_ZLEN) {
2514                 if (datalen >= protolen) {
2515                         /* more data on wire than in 802 header, trim of
2516                          * additional data.
2517                          */
2518                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2519                                         dev->name, protolen);
2520                         return protolen;
2521                 } else {
2522                         /* less data on wire than mentioned in header.
2523                          * Discard the packet.
2524                          */
2525                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2526                                         dev->name);
2527                         return -1;
2528                 }
2529         } else {
2530                 /* short packet. Accept only if 802 values are also short */
2531                 if (protolen > ETH_ZLEN) {
2532                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2533                                         dev->name);
2534                         return -1;
2535                 }
2536                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2537                                 dev->name, datalen);
2538                 return datalen;
2539         }
2540 }
2541
2542 static int nv_rx_process(struct net_device *dev, int limit)
2543 {
2544         struct fe_priv *np = netdev_priv(dev);
2545         u32 flags;
2546         int rx_work = 0;
2547         struct sk_buff *skb;
2548         int len;
2549
2550         while((np->get_rx.orig != np->put_rx.orig) &&
2551               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2552                 (rx_work < limit)) {
2553
2554                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2555                                         dev->name, flags);
2556
2557                 /*
2558                  * the packet is for us - immediately tear down the pci mapping.
2559                  * TODO: check if a prefetch of the first cacheline improves
2560                  * the performance.
2561                  */
2562                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2563                                 np->get_rx_ctx->dma_len,
2564                                 PCI_DMA_FROMDEVICE);
2565                 skb = np->get_rx_ctx->skb;
2566                 np->get_rx_ctx->skb = NULL;
2567
2568                 {
2569                         int j;
2570                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2571                         for (j=0; j<64; j++) {
2572                                 if ((j%16) == 0)
2573                                         dprintk("\n%03x:", j);
2574                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2575                         }
2576                         dprintk("\n");
2577                 }
2578                 /* look at what we actually got: */
2579                 if (np->desc_ver == DESC_VER_1) {
2580                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2581                                 len = flags & LEN_MASK_V1;
2582                                 if (unlikely(flags & NV_RX_ERROR)) {
2583                                         if (flags & NV_RX_ERROR4) {
2584                                                 len = nv_getlen(dev, skb->data, len);
2585                                                 if (len < 0) {
2586                                                         dev->stats.rx_errors++;
2587                                                         dev_kfree_skb(skb);
2588                                                         goto next_pkt;
2589                                                 }
2590                                         }
2591                                         /* framing errors are soft errors */
2592                                         else if (flags & NV_RX_FRAMINGERR) {
2593                                                 if (flags & NV_RX_SUBSTRACT1) {
2594                                                         len--;
2595                                                 }
2596                                         }
2597                                         /* the rest are hard errors */
2598                                         else {
2599                                                 if (flags & NV_RX_MISSEDFRAME)
2600                                                         dev->stats.rx_missed_errors++;
2601                                                 if (flags & NV_RX_CRCERR)
2602                                                         dev->stats.rx_crc_errors++;
2603                                                 if (flags & NV_RX_OVERFLOW)
2604                                                         dev->stats.rx_over_errors++;
2605                                                 dev->stats.rx_errors++;
2606                                                 dev_kfree_skb(skb);
2607                                                 goto next_pkt;
2608                                         }
2609                                 }
2610                         } else {
2611                                 dev_kfree_skb(skb);
2612                                 goto next_pkt;
2613                         }
2614                 } else {
2615                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2616                                 len = flags & LEN_MASK_V2;
2617                                 if (unlikely(flags & NV_RX2_ERROR)) {
2618                                         if (flags & NV_RX2_ERROR4) {
2619                                                 len = nv_getlen(dev, skb->data, len);
2620                                                 if (len < 0) {
2621                                                         dev->stats.rx_errors++;
2622                                                         dev_kfree_skb(skb);
2623                                                         goto next_pkt;
2624                                                 }
2625                                         }
2626                                         /* framing errors are soft errors */
2627                                         else if (flags & NV_RX2_FRAMINGERR) {
2628                                                 if (flags & NV_RX2_SUBSTRACT1) {
2629                                                         len--;
2630                                                 }
2631                                         }
2632                                         /* the rest are hard errors */
2633                                         else {
2634                                                 if (flags & NV_RX2_CRCERR)
2635                                                         dev->stats.rx_crc_errors++;
2636                                                 if (flags & NV_RX2_OVERFLOW)
2637                                                         dev->stats.rx_over_errors++;
2638                                                 dev->stats.rx_errors++;
2639                                                 dev_kfree_skb(skb);
2640                                                 goto next_pkt;
2641                                         }
2642                                 }
2643                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2644                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2645                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2646                         } else {
2647                                 dev_kfree_skb(skb);
2648                                 goto next_pkt;
2649                         }
2650                 }
2651                 /* got a valid packet - forward it to the network core */
2652                 skb_put(skb, len);
2653                 skb->protocol = eth_type_trans(skb, dev);
2654                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2655                                         dev->name, len, skb->protocol);
2656 #ifdef CONFIG_FORCEDETH_NAPI
2657                 netif_receive_skb(skb);
2658 #else
2659                 netif_rx(skb);
2660 #endif
2661                 dev->last_rx = jiffies;
2662                 dev->stats.rx_packets++;
2663                 dev->stats.rx_bytes += len;
2664 next_pkt:
2665                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2666                         np->get_rx.orig = np->first_rx.orig;
2667                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2668                         np->get_rx_ctx = np->first_rx_ctx;
2669
2670                 rx_work++;
2671         }
2672
2673         return rx_work;
2674 }
2675
2676 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2677 {
2678         struct fe_priv *np = netdev_priv(dev);
2679         u32 flags;
2680         u32 vlanflags = 0;
2681         int rx_work = 0;
2682         struct sk_buff *skb;
2683         int len;
2684
2685         while((np->get_rx.ex != np->put_rx.ex) &&
2686               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2687               (rx_work < limit)) {
2688
2689                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2690                                         dev->name, flags);
2691
2692                 /*
2693                  * the packet is for us - immediately tear down the pci mapping.
2694                  * TODO: check if a prefetch of the first cacheline improves
2695                  * the performance.
2696                  */
2697                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2698                                 np->get_rx_ctx->dma_len,
2699                                 PCI_DMA_FROMDEVICE);
2700                 skb = np->get_rx_ctx->skb;
2701                 np->get_rx_ctx->skb = NULL;
2702
2703                 {
2704                         int j;
2705                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2706                         for (j=0; j<64; j++) {
2707                                 if ((j%16) == 0)
2708                                         dprintk("\n%03x:", j);
2709                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2710                         }
2711                         dprintk("\n");
2712                 }
2713                 /* look at what we actually got: */
2714                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2715                         len = flags & LEN_MASK_V2;
2716                         if (unlikely(flags & NV_RX2_ERROR)) {
2717                                 if (flags & NV_RX2_ERROR4) {
2718                                         len = nv_getlen(dev, skb->data, len);
2719                                         if (len < 0) {
2720                                                 dev_kfree_skb(skb);
2721                                                 goto next_pkt;
2722                                         }
2723                                 }
2724                                 /* framing errors are soft errors */
2725                                 else if (flags & NV_RX2_FRAMINGERR) {
2726                                         if (flags & NV_RX2_SUBSTRACT1) {
2727                                                 len--;
2728                                         }
2729                                 }
2730                                 /* the rest are hard errors */
2731                                 else {
2732                                         dev_kfree_skb(skb);
2733                                         goto next_pkt;
2734                                 }
2735                         }
2736
2737                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2738                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2739                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2740
2741                         /* got a valid packet - forward it to the network core */
2742                         skb_put(skb, len);
2743                         skb->protocol = eth_type_trans(skb, dev);
2744                         prefetch(skb->data);
2745
2746                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2747                                 dev->name, len, skb->protocol);
2748
2749                         if (likely(!np->vlangrp)) {
2750 #ifdef CONFIG_FORCEDETH_NAPI
2751                                 netif_receive_skb(skb);
2752 #else
2753                                 netif_rx(skb);
2754 #endif
2755                         } else {
2756                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2757                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2758 #ifdef CONFIG_FORCEDETH_NAPI
2759                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2760                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2761 #else
2762                                         vlan_hwaccel_rx(skb, np->vlangrp,
2763                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2764 #endif
2765                                 } else {
2766 #ifdef CONFIG_FORCEDETH_NAPI
2767                                         netif_receive_skb(skb);
2768 #else
2769                                         netif_rx(skb);
2770 #endif
2771                                 }
2772                         }
2773
2774                         dev->last_rx = jiffies;
2775                         dev->stats.rx_packets++;
2776                         dev->stats.rx_bytes += len;
2777                 } else {
2778                         dev_kfree_skb(skb);
2779                 }
2780 next_pkt:
2781                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2782                         np->get_rx.ex = np->first_rx.ex;
2783                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2784                         np->get_rx_ctx = np->first_rx_ctx;
2785
2786                 rx_work++;
2787         }
2788
2789         return rx_work;
2790 }
2791
2792 static void set_bufsize(struct net_device *dev)
2793 {
2794         struct fe_priv *np = netdev_priv(dev);
2795
2796         if (dev->mtu <= ETH_DATA_LEN)
2797                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2798         else
2799                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2800 }
2801
2802 /*
2803  * nv_change_mtu: dev->change_mtu function
2804  * Called with dev_base_lock held for read.
2805  */
2806 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2807 {
2808         struct fe_priv *np = netdev_priv(dev);
2809         int old_mtu;
2810
2811         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2812                 return -EINVAL;
2813
2814         old_mtu = dev->mtu;
2815         dev->mtu = new_mtu;
2816
2817         /* return early if the buffer sizes will not change */
2818         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2819                 return 0;
2820         if (old_mtu == new_mtu)
2821                 return 0;
2822
2823         /* synchronized against open : rtnl_lock() held by caller */
2824         if (netif_running(dev)) {
2825                 u8 __iomem *base = get_hwbase(dev);
2826                 /*
2827                  * It seems that the nic preloads valid ring entries into an
2828                  * internal buffer. The procedure for flushing everything is
2829                  * guessed, there is probably a simpler approach.
2830                  * Changing the MTU is a rare event, it shouldn't matter.
2831                  */
2832                 nv_disable_irq(dev);
2833                 netif_tx_lock_bh(dev);
2834                 spin_lock(&np->lock);
2835                 /* stop engines */
2836                 nv_stop_rxtx(dev);
2837                 nv_txrx_reset(dev);
2838                 /* drain rx queue */
2839                 nv_drain_rxtx(dev);
2840                 /* reinit driver view of the rx queue */
2841                 set_bufsize(dev);
2842                 if (nv_init_ring(dev)) {
2843                         if (!np->in_shutdown)
2844                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2845                 }
2846                 /* reinit nic view of the rx queue */
2847                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2848                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2849                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2850                         base + NvRegRingSizes);
2851                 pci_push(base);
2852                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2853                 pci_push(base);
2854
2855                 /* restart rx engine */
2856                 nv_start_rxtx(dev);
2857                 spin_unlock(&np->lock);
2858                 netif_tx_unlock_bh(dev);
2859                 nv_enable_irq(dev);
2860         }
2861         return 0;
2862 }
2863
2864 static void nv_copy_mac_to_hw(struct net_device *dev)
2865 {
2866         u8 __iomem *base = get_hwbase(dev);
2867         u32 mac[2];
2868
2869         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2870                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2871         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2872
2873         writel(mac[0], base + NvRegMacAddrA);
2874         writel(mac[1], base + NvRegMacAddrB);
2875 }
2876
2877 /*
2878  * nv_set_mac_address: dev->set_mac_address function
2879  * Called with rtnl_lock() held.
2880  */
2881 static int nv_set_mac_address(struct net_device *dev, void *addr)
2882 {
2883         struct fe_priv *np = netdev_priv(dev);
2884         struct sockaddr *macaddr = (struct sockaddr*)addr;
2885
2886         if (!is_valid_ether_addr(macaddr->sa_data))
2887                 return -EADDRNOTAVAIL;
2888
2889         /* synchronized against open : rtnl_lock() held by caller */
2890         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2891
2892         if (netif_running(dev)) {
2893                 netif_tx_lock_bh(dev);
2894                 spin_lock_irq(&np->lock);
2895
2896                 /* stop rx engine */
2897                 nv_stop_rx(dev);
2898
2899                 /* set mac address */
2900                 nv_copy_mac_to_hw(dev);
2901
2902                 /* restart rx engine */
2903                 nv_start_rx(dev);
2904                 spin_unlock_irq(&np->lock);
2905                 netif_tx_unlock_bh(dev);
2906         } else {
2907                 nv_copy_mac_to_hw(dev);
2908         }
2909         return 0;
2910 }
2911
2912 /*
2913  * nv_set_multicast: dev->set_multicast function
2914  * Called with netif_tx_lock held.
2915  */
2916 static void nv_set_multicast(struct net_device *dev)
2917 {
2918         struct fe_priv *np = netdev_priv(dev);
2919         u8 __iomem *base = get_hwbase(dev);
2920         u32 addr[2];
2921         u32 mask[2];
2922         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2923
2924         memset(addr, 0, sizeof(addr));
2925         memset(mask, 0, sizeof(mask));
2926
2927         if (dev->flags & IFF_PROMISC) {
2928                 pff |= NVREG_PFF_PROMISC;
2929         } else {
2930                 pff |= NVREG_PFF_MYADDR;
2931
2932                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2933                         u32 alwaysOff[2];
2934                         u32 alwaysOn[2];
2935
2936                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2937                         if (dev->flags & IFF_ALLMULTI) {
2938                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2939                         } else {
2940                                 struct dev_mc_list *walk;
2941
2942                                 walk = dev->mc_list;
2943                                 while (walk != NULL) {
2944                                         u32 a, b;
2945                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2946                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2947                                         alwaysOn[0] &= a;
2948                                         alwaysOff[0] &= ~a;
2949                                         alwaysOn[1] &= b;
2950                                         alwaysOff[1] &= ~b;
2951                                         walk = walk->next;
2952                                 }
2953                         }
2954                         addr[0] = alwaysOn[0];
2955                         addr[1] = alwaysOn[1];
2956                         mask[0] = alwaysOn[0] | alwaysOff[0];
2957                         mask[1] = alwaysOn[1] | alwaysOff[1];
2958                 } else {
2959                         mask[0] = NVREG_MCASTMASKA_NONE;
2960                         mask[1] = NVREG_MCASTMASKB_NONE;
2961                 }
2962         }
2963         addr[0] |= NVREG_MCASTADDRA_FORCE;
2964         pff |= NVREG_PFF_ALWAYS;
2965         spin_lock_irq(&np->lock);
2966         nv_stop_rx(dev);
2967         writel(addr[0], base + NvRegMulticastAddrA);
2968         writel(addr[1], base + NvRegMulticastAddrB);
2969         writel(mask[0], base + NvRegMulticastMaskA);
2970         writel(mask[1], base + NvRegMulticastMaskB);
2971         writel(pff, base + NvRegPacketFilterFlags);
2972         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2973                 dev->name);
2974         nv_start_rx(dev);
2975         spin_unlock_irq(&np->lock);
2976 }
2977
2978 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2979 {
2980         struct fe_priv *np = netdev_priv(dev);
2981         u8 __iomem *base = get_hwbase(dev);
2982
2983         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2984
2985         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2986                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2987                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2988                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2989                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2990                 } else {
2991                         writel(pff, base + NvRegPacketFilterFlags);
2992                 }
2993         }
2994         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2995                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2996                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2997                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2998                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2999                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3000                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
3001                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3002                         writel(pause_enable,  base + NvRegTxPauseFrame);
3003                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3004                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3005                 } else {
3006                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3007                         writel(regmisc, base + NvRegMisc1);
3008                 }
3009         }
3010 }
3011
3012 /**
3013  * nv_update_linkspeed: Setup the MAC according to the link partner
3014  * @dev: Network device to be configured
3015  *
3016  * The function queries the PHY and checks if there is a link partner.
3017  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3018  * set to 10 MBit HD.
3019  *
3020  * The function returns 0 if there is no link partner and 1 if there is
3021  * a good link partner.
3022  */
3023 static int nv_update_linkspeed(struct net_device *dev)
3024 {
3025         struct fe_priv *np = netdev_priv(dev);
3026         u8 __iomem *base = get_hwbase(dev);
3027         int adv = 0;
3028         int lpa = 0;
3029         int adv_lpa, adv_pause, lpa_pause;
3030         int newls = np->linkspeed;
3031         int newdup = np->duplex;
3032         int mii_status;
3033         int retval = 0;
3034         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3035         u32 txrxFlags = 0;
3036         u32 phy_exp;
3037
3038         /* BMSR_LSTATUS is latched, read it twice:
3039          * we want the current value.
3040          */
3041         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3042         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3043
3044         if (!(mii_status & BMSR_LSTATUS)) {
3045                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3046                                 dev->name);
3047                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3048                 newdup = 0;
3049                 retval = 0;
3050                 goto set_speed;
3051         }
3052
3053         if (np->autoneg == 0) {
3054                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3055                                 dev->name, np->fixed_mode);
3056                 if (np->fixed_mode & LPA_100FULL) {
3057                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3058                         newdup = 1;
3059                 } else if (np->fixed_mode & LPA_100HALF) {
3060                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3061                         newdup = 0;
3062                 } else if (np->fixed_mode & LPA_10FULL) {
3063                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3064                         newdup = 1;
3065                 } else {
3066                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3067                         newdup = 0;
3068                 }
3069                 retval = 1;
3070                 goto set_speed;
3071         }
3072         /* check auto negotiation is complete */
3073         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3074                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3075                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3076                 newdup = 0;
3077                 retval = 0;
3078                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3079                 goto set_speed;
3080         }
3081
3082         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3083         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3084         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3085                                 dev->name, adv, lpa);
3086
3087         retval = 1;
3088         if (np->gigabit == PHY_GIGABIT) {
3089                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3090                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3091
3092                 if ((control_1000 & ADVERTISE_1000FULL) &&
3093                         (status_1000 & LPA_1000FULL)) {
3094                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3095                                 dev->name);
3096                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3097                         newdup = 1;
3098                         goto set_speed;
3099                 }
3100         }
3101
3102         /* FIXME: handle parallel detection properly */
3103         adv_lpa = lpa & adv;
3104         if (adv_lpa & LPA_100FULL) {
3105                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3106                 newdup = 1;
3107         } else if (adv_lpa & LPA_100HALF) {
3108                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3109                 newdup = 0;
3110         } else if (adv_lpa & LPA_10FULL) {
3111                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3112                 newdup = 1;
3113         } else if (adv_lpa & LPA_10HALF) {
3114                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3115                 newdup = 0;
3116         } else {
3117                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3118                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3119                 newdup = 0;
3120         }
3121
3122 set_speed:
3123         if (np->duplex == newdup && np->linkspeed == newls)
3124                 return retval;
3125
3126         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3127                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3128
3129         np->duplex = newdup;
3130         np->linkspeed = newls;
3131
3132         /* The transmitter and receiver must be restarted for safe update */
3133         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3134                 txrxFlags |= NV_RESTART_TX;
3135                 nv_stop_tx(dev);
3136         }
3137         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3138                 txrxFlags |= NV_RESTART_RX;
3139                 nv_stop_rx(dev);
3140         }
3141
3142         if (np->gigabit == PHY_GIGABIT) {
3143                 phyreg = readl(base + NvRegSlotTime);
3144                 phyreg &= ~(0x3FF00);
3145                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3146                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3147                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3148                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3149                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3150                 writel(phyreg, base + NvRegSlotTime);
3151         }
3152
3153         phyreg = readl(base + NvRegPhyInterface);
3154         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3155         if (np->duplex == 0)
3156                 phyreg |= PHY_HALF;
3157         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3158                 phyreg |= PHY_100;
3159         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3160                 phyreg |= PHY_1000;
3161         writel(phyreg, base + NvRegPhyInterface);
3162
3163         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3164         if (phyreg & PHY_RGMII) {
3165                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3166                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3167                 } else {
3168                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3169                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3170                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3171                                 else
3172                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3173                         } else {
3174                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3175                         }
3176                 }
3177         } else {
3178                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3179                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3180                 else
3181                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3182         }
3183         writel(txreg, base + NvRegTxDeferral);
3184
3185         if (np->desc_ver == DESC_VER_1) {
3186                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3187         } else {
3188                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3189                         txreg = NVREG_TX_WM_DESC2_3_1000;
3190                 else
3191                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3192         }
3193         writel(txreg, base + NvRegTxWatermark);
3194
3195         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3196                 base + NvRegMisc1);
3197         pci_push(base);
3198         writel(np->linkspeed, base + NvRegLinkSpeed);
3199         pci_push(base);
3200
3201         pause_flags = 0;
3202         /* setup pause frame */
3203         if (np->duplex != 0) {
3204                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3205                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3206                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3207
3208                         switch (adv_pause) {
3209                         case ADVERTISE_PAUSE_CAP:
3210                                 if (lpa_pause & LPA_PAUSE_CAP) {
3211                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3212                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3213                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3214                                 }
3215                                 break;
3216                         case ADVERTISE_PAUSE_ASYM:
3217                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3218                                 {
3219                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3220                                 }
3221                                 break;
3222                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3223                                 if (lpa_pause & LPA_PAUSE_CAP)
3224                                 {
3225                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3226                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3227                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3228                                 }
3229                                 if (lpa_pause == LPA_PAUSE_ASYM)
3230                                 {
3231                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3232                                 }
3233                                 break;
3234                         }
3235                 } else {
3236                         pause_flags = np->pause_flags;
3237                 }
3238         }
3239         nv_update_pause(dev, pause_flags);
3240
3241         if (txrxFlags & NV_RESTART_TX)
3242                 nv_start_tx(dev);
3243         if (txrxFlags & NV_RESTART_RX)
3244                 nv_start_rx(dev);
3245
3246         return retval;
3247 }
3248
3249 static void nv_linkchange(struct net_device *dev)
3250 {
3251         if (nv_update_linkspeed(dev)) {
3252                 if (!netif_carrier_ok(dev)) {
3253                         netif_carrier_on(dev);
3254                         printk(KERN_INFO "%s: link up.\n", dev->name);
3255                         nv_start_rx(dev);
3256                 }
3257         } else {
3258                 if (netif_carrier_ok(dev)) {
3259                         netif_carrier_off(dev);
3260                         printk(KERN_INFO "%s: link down.\n", dev->name);
3261                         nv_stop_rx(dev);
3262                 }
3263         }
3264 }
3265
3266 static void nv_link_irq(struct net_device *dev)
3267 {
3268         u8 __iomem *base = get_hwbase(dev);
3269         u32 miistat;
3270
3271         miistat = readl(base + NvRegMIIStatus);
3272         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3273         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3274
3275         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3276                 nv_linkchange(dev);
3277         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3278 }
3279
3280 static irqreturn_t nv_nic_irq(int foo, void *data)
3281 {
3282         struct net_device *dev = (struct net_device *) data;
3283         struct fe_priv *np = netdev_priv(dev);
3284         u8 __iomem *base = get_hwbase(dev);
3285         u32 events;
3286         int i;
3287
3288         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3289
3290         for (i=0; ; i++) {
3291                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3292                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3293                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3294                 } else {
3295                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3296                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3297                 }
3298                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3299                 if (!(events & np->irqmask))
3300                         break;
3301
3302                 spin_lock(&np->lock);
3303                 nv_tx_done(dev);
3304                 spin_unlock(&np->lock);
3305
3306 #ifdef CONFIG_FORCEDETH_NAPI
3307                 if (events & NVREG_IRQ_RX_ALL) {
3308                         netif_rx_schedule(dev, &np->napi);
3309
3310                         /* Disable furthur receive irq's */
3311                         spin_lock(&np->lock);
3312                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3313
3314                         if (np->msi_flags & NV_MSI_X_ENABLED)
3315                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3316                         else
3317                                 writel(np->irqmask, base + NvRegIrqMask);
3318                         spin_unlock(&np->lock);
3319                 }
3320 #else
3321                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3322                         if (unlikely(nv_alloc_rx(dev))) {
3323                                 spin_lock(&np->lock);
3324                                 if (!np->in_shutdown)
3325                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3326                                 spin_unlock(&np->lock);
3327                         }
3328                 }
3329 #endif
3330                 if (unlikely(events & NVREG_IRQ_LINK)) {
3331                         spin_lock(&np->lock);
3332                         nv_link_irq(dev);
3333                         spin_unlock(&np->lock);
3334                 }
3335                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3336                         spin_lock(&np->lock);
3337                         nv_linkchange(dev);
3338                         spin_unlock(&np->lock);
3339                         np->link_timeout = jiffies + LINK_TIMEOUT;
3340                 }
3341                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3342                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3343                                                 dev->name, events);
3344                 }
3345                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3346                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3347                                                 dev->name, events);
3348                 }
3349                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3350                         spin_lock(&np->lock);
3351                         /* disable interrupts on the nic */
3352                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3353                                 writel(0, base + NvRegIrqMask);
3354                         else
3355                                 writel(np->irqmask, base + NvRegIrqMask);
3356                         pci_push(base);
3357
3358                         if (!np->in_shutdown) {
3359                                 np->nic_poll_irq = np->irqmask;
3360                                 np->recover_error = 1;
3361                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3362                         }
3363                         spin_unlock(&np->lock);
3364                         break;
3365                 }
3366                 if (unlikely(i > max_interrupt_work)) {
3367                         spin_lock(&np->lock);
3368                         /* disable interrupts on the nic */
3369                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3370                                 writel(0, base + NvRegIrqMask);
3371                         else
3372                                 writel(np->irqmask, base + NvRegIrqMask);
3373                         pci_push(base);
3374
3375                         if (!np->in_shutdown) {
3376                                 np->nic_poll_irq = np->irqmask;
3377                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3378                         }
3379                         spin_unlock(&np->lock);
3380                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3381                         break;
3382                 }
3383
3384         }
3385         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3386
3387         return IRQ_RETVAL(i);
3388 }
3389
3390 /**
3391  * All _optimized functions are used to help increase performance
3392  * (reduce CPU and increase throughput). They use descripter version 3,
3393  * compiler directives, and reduce memory accesses.
3394  */
3395 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3396 {
3397         struct net_device *dev = (struct net_device *) data;
3398         struct fe_priv *np = netdev_priv(dev);
3399         u8 __iomem *base = get_hwbase(dev);
3400         u32 events;
3401         int i;
3402
3403         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3404
3405         for (i=0; ; i++) {
3406                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3407                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3408                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3409                 } else {
3410                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3411                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3412                 }
3413                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3414                 if (!(events & np->irqmask))
3415                         break;
3416
3417                 spin_lock(&np->lock);
3418                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3419                 spin_unlock(&np->lock);
3420
3421 #ifdef CONFIG_FORCEDETH_NAPI
3422                 if (events & NVREG_IRQ_RX_ALL) {
3423                         netif_rx_schedule(dev, &np->napi);
3424
3425                         /* Disable furthur receive irq's */
3426                         spin_lock(&np->lock);
3427                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3428
3429                         if (np->msi_flags & NV_MSI_X_ENABLED)
3430                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3431                         else
3432                                 writel(np->irqmask, base + NvRegIrqMask);
3433                         spin_unlock(&np->lock);
3434                 }
3435 #else
3436                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3437                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3438                                 spin_lock(&np->lock);
3439                                 if (!np->in_shutdown)
3440                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3441                                 spin_unlock(&np->lock);
3442                         }
3443                 }
3444 #endif
3445                 if (unlikely(events & NVREG_IRQ_LINK)) {
3446                         spin_lock(&np->lock);
3447                         nv_link_irq(dev);
3448                         spin_unlock(&np->lock);
3449                 }
3450                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3451                         spin_lock(&np->lock);
3452                         nv_linkchange(dev);
3453                         spin_unlock(&np->lock);
3454                         np->link_timeout = jiffies + LINK_TIMEOUT;
3455                 }
3456                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3457                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3458                                                 dev->name, events);
3459                 }
3460                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3461                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3462                                                 dev->name, events);
3463                 }
3464                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3465                         spin_lock(&np->lock);
3466                         /* disable interrupts on the nic */
3467                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3468                                 writel(0, base + NvRegIrqMask);
3469                         else
3470                                 writel(np->irqmask, base + NvRegIrqMask);
3471                         pci_push(base);
3472
3473                         if (!np->in_shutdown) {
3474                                 np->nic_poll_irq = np->irqmask;
3475                                 np->recover_error = 1;
3476                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3477                         }
3478                         spin_unlock(&np->lock);
3479                         break;
3480                 }
3481
3482                 if (unlikely(i > max_interrupt_work)) {
3483                         spin_lock(&np->lock);
3484                         /* disable interrupts on the nic */
3485                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3486                                 writel(0, base + NvRegIrqMask);
3487                         else
3488                                 writel(np->irqmask, base + NvRegIrqMask);
3489                         pci_push(base);
3490
3491                         if (!np->in_shutdown) {
3492                                 np->nic_poll_irq = np->irqmask;
3493                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3494                         }
3495                         spin_unlock(&np->lock);
3496                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3497                         break;
3498                 }
3499
3500         }
3501         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3502
3503         return IRQ_RETVAL(i);
3504 }
3505
3506 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3507 {
3508         struct net_device *dev = (struct net_device *) data;
3509         struct fe_priv *np = netdev_priv(dev);
3510         u8 __iomem *base = get_hwbase(dev);
3511         u32 events;
3512         int i;
3513         unsigned long flags;
3514
3515         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3516
3517         for (i=0; ; i++) {
3518                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3519                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3520                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3521                 if (!(events & np->irqmask))
3522                         break;
3523
3524                 spin_lock_irqsave(&np->lock, flags);
3525                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3526                 spin_unlock_irqrestore(&np->lock, flags);
3527
3528                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3529                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3530                                                 dev->name, events);
3531                 }
3532                 if (unlikely(i > max_interrupt_work)) {
3533                         spin_lock_irqsave(&np->lock, flags);
3534                         /* disable interrupts on the nic */
3535                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3536                         pci_push(base);
3537
3538                         if (!np->in_shutdown) {
3539                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3540                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3541                         }
3542                         spin_unlock_irqrestore(&np->lock, flags);
3543                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3544                         break;
3545                 }
3546
3547         }
3548         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3549
3550         return IRQ_RETVAL(i);
3551 }
3552
3553 #ifdef CONFIG_FORCEDETH_NAPI
3554 static int nv_napi_poll(struct napi_struct *napi, int budget)
3555 {
3556         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3557         struct net_device *dev = np->dev;
3558         u8 __iomem *base = get_hwbase(dev);
3559         unsigned long flags;
3560         int pkts, retcode;
3561
3562         if (!nv_optimized(np)) {
3563                 pkts = nv_rx_process(dev, budget);
3564                 retcode = nv_alloc_rx(dev);
3565         } else {
3566                 pkts = nv_rx_process_optimized(dev, budget);
3567                 retcode = nv_alloc_rx_optimized(dev);
3568         }
3569
3570         if (retcode) {
3571                 spin_lock_irqsave(&np->lock, flags);
3572                 if (!np->in_shutdown)
3573                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3574                 spin_unlock_irqrestore(&np->lock, flags);
3575         }
3576
3577         if (pkts < budget) {
3578                 /* re-enable receive interrupts */
3579                 spin_lock_irqsave(&np->lock, flags);
3580
3581                 __netif_rx_complete(dev, napi);
3582
3583                 np->irqmask |= NVREG_IRQ_RX_ALL;
3584                 if (np->msi_flags & NV_MSI_X_ENABLED)
3585                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3586                 else
3587                         writel(np->irqmask, base + NvRegIrqMask);
3588
3589                 spin_unlock_irqrestore(&np->lock, flags);
3590         }
3591         return pkts;
3592 }
3593 #endif
3594
3595 #ifdef CONFIG_FORCEDETH_NAPI
3596 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3597 {
3598         struct net_device *dev = (struct net_device *) data;
3599         struct fe_priv *np = netdev_priv(dev);
3600         u8 __iomem *base = get_hwbase(dev);
3601         u32 events;
3602
3603         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3604         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3605
3606         if (events) {
3607                 netif_rx_schedule(dev, &np->napi);
3608                 /* disable receive interrupts on the nic */
3609                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3610                 pci_push(base);
3611         }
3612         return IRQ_HANDLED;
3613 }
3614 #else
3615 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3616 {
3617         struct net_device *dev = (struct net_device *) data;
3618         struct fe_priv *np = netdev_priv(dev);
3619         u8 __iomem *base = get_hwbase(dev);
3620         u32 events;
3621         int i;
3622         unsigned long flags;
3623
3624         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3625
3626         for (i=0; ; i++) {
3627                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3628                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3629                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3630                 if (!(events & np->irqmask))
3631                         break;
3632
3633                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3634                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3635                                 spin_lock_irqsave(&np->lock, flags);
3636                                 if (!np->in_shutdown)
3637                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3638                                 spin_unlock_irqrestore(&np->lock, flags);
3639                         }
3640                 }
3641
3642                 if (unlikely(i > max_interrupt_work)) {
3643                         spin_lock_irqsave(&np->lock, flags);
3644                         /* disable interrupts on the nic */
3645                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3646                         pci_push(base);
3647
3648                         if (!np->in_shutdown) {
3649                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3650                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3651                         }
3652                         spin_unlock_irqrestore(&np->lock, flags);
3653                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3654                         break;
3655                 }
3656         }
3657         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3658
3659         return IRQ_RETVAL(i);
3660 }
3661 #endif
3662
3663 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3664 {
3665         struct net_device *dev = (struct net_device *) data;
3666         struct fe_priv *np = netdev_priv(dev);
3667         u8 __iomem *base = get_hwbase(dev);
3668         u32 events;
3669         int i;
3670         unsigned long flags;
3671
3672         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3673
3674         for (i=0; ; i++) {
3675                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3676                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3677                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3678                 if (!(events & np->irqmask))
3679                         break;
3680
3681                 /* check tx in case we reached max loop limit in tx isr */
3682                 spin_lock_irqsave(&np->lock, flags);
3683                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3684                 spin_unlock_irqrestore(&np->lock, flags);
3685
3686                 if (events & NVREG_IRQ_LINK) {
3687                         spin_lock_irqsave(&np->lock, flags);
3688                         nv_link_irq(dev);
3689                         spin_unlock_irqrestore(&np->lock, flags);
3690                 }
3691                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3692                         spin_lock_irqsave(&np->lock, flags);
3693                         nv_linkchange(dev);
3694                         spin_unlock_irqrestore(&np->lock, flags);
3695                         np->link_timeout = jiffies + LINK_TIMEOUT;
3696                 }
3697                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3698                         spin_lock_irq(&np->lock);
3699                         /* disable interrupts on the nic */
3700                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3701                         pci_push(base);
3702
3703                         if (!np->in_shutdown) {
3704                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3705                                 np->recover_error = 1;
3706                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3707                         }
3708                         spin_unlock_irq(&np->lock);
3709                         break;
3710                 }
3711                 if (events & (NVREG_IRQ_UNKNOWN)) {
3712                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3713                                                 dev->name, events);
3714                 }
3715                 if (unlikely(i > max_interrupt_work)) {
3716                         spin_lock_irqsave(&np->lock, flags);
3717                         /* disable interrupts on the nic */
3718                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3719                         pci_push(base);
3720
3721                         if (!np->in_shutdown) {
3722                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3723                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3724                         }
3725                         spin_unlock_irqrestore(&np->lock, flags);
3726                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3727                         break;
3728                 }
3729
3730         }
3731         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3732
3733         return IRQ_RETVAL(i);
3734 }
3735
3736 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3737 {
3738         struct net_device *dev = (struct net_device *) data;
3739         struct fe_priv *np = netdev_priv(dev);
3740         u8 __iomem *base = get_hwbase(dev);
3741         u32 events;
3742
3743         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3744
3745         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3746                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3747                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3748         } else {
3749                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3750                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3751         }
3752         pci_push(base);
3753         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3754         if (!(events & NVREG_IRQ_TIMER))
3755                 return IRQ_RETVAL(0);
3756
3757         spin_lock(&np->lock);
3758         np->intr_test = 1;
3759         spin_unlock(&np->lock);
3760
3761         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3762
3763         return IRQ_RETVAL(1);
3764 }
3765
3766 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3767 {
3768         u8 __iomem *base = get_hwbase(dev);
3769         int i;
3770         u32 msixmap = 0;
3771
3772         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3773          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3774          * the remaining 8 interrupts.
3775          */
3776         for (i = 0; i < 8; i++) {
3777                 if ((irqmask >> i) & 0x1) {
3778                         msixmap |= vector << (i << 2);
3779                 }
3780         }
3781         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3782
3783         msixmap = 0;
3784         for (i = 0; i < 8; i++) {
3785                 if ((irqmask >> (i + 8)) & 0x1) {
3786                         msixmap |= vector << (i << 2);
3787                 }
3788         }
3789         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3790 }
3791
3792 static int nv_request_irq(struct net_device *dev, int intr_test)
3793 {
3794         struct fe_priv *np = get_nvpriv(dev);
3795         u8 __iomem *base = get_hwbase(dev);
3796         int ret = 1;
3797         int i;
3798         irqreturn_t (*handler)(int foo, void *data);
3799
3800         if (intr_test) {
3801                 handler = nv_nic_irq_test;
3802         } else {
3803                 if (nv_optimized(np))
3804                         handler = nv_nic_irq_optimized;
3805                 else
3806                         handler = nv_nic_irq;
3807         }
3808
3809         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3810                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3811                         np->msi_x_entry[i].entry = i;
3812                 }
3813                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3814                         np->msi_flags |= NV_MSI_X_ENABLED;
3815                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3816                                 /* Request irq for rx handling */
3817                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3818                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3819                                         pci_disable_msix(np->pci_dev);
3820                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3821                                         goto out_err;
3822                                 }
3823                                 /* Request irq for tx handling */
3824                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3825                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3826                                         pci_disable_msix(np->pci_dev);
3827                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3828                                         goto out_free_rx;
3829                                 }
3830                                 /* Request irq for link and timer handling */
3831                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3832                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3833                                         pci_disable_msix(np->pci_dev);
3834                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3835                                         goto out_free_tx;
3836                                 }
3837                                 /* map interrupts to their respective vector */
3838                                 writel(0, base + NvRegMSIXMap0);
3839                                 writel(0, base + NvRegMSIXMap1);
3840                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3841                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3842                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3843                         } else {
3844                                 /* Request irq for all interrupts */
3845                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3846                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3847                                         pci_disable_msix(np->pci_dev);
3848                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3849                                         goto out_err;
3850                                 }
3851
3852                                 /* map interrupts to vector 0 */
3853                                 writel(0, base + NvRegMSIXMap0);
3854                                 writel(0, base + NvRegMSIXMap1);
3855                         }
3856                 }
3857         }
3858         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3859                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3860                         np->msi_flags |= NV_MSI_ENABLED;
3861                         dev->irq = np->pci_dev->irq;
3862                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3863                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3864                                 pci_disable_msi(np->pci_dev);
3865                                 np->msi_flags &= ~NV_MSI_ENABLED;
3866                                 dev->irq = np->pci_dev->irq;
3867                                 goto out_err;
3868                         }
3869
3870                         /* map interrupts to vector 0 */
3871                         writel(0, base + NvRegMSIMap0);
3872                         writel(0, base + NvRegMSIMap1);
3873                         /* enable msi vector 0 */
3874                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3875                 }
3876         }
3877         if (ret != 0) {
3878                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3879                         goto out_err;
3880
3881         }
3882
3883         return 0;
3884 out_free_tx:
3885         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3886 out_free_rx:
3887         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3888 out_err:
3889         return 1;
3890 }
3891
3892 static void nv_free_irq(struct net_device *dev)
3893 {
3894         struct fe_priv *np = get_nvpriv(dev);
3895         int i;
3896
3897         if (np->msi_flags & NV_MSI_X_ENABLED) {
3898                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3899                         free_irq(np->msi_x_entry[i].vector, dev);
3900                 }
3901                 pci_disable_msix(np->pci_dev);
3902                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3903         } else {
3904                 free_irq(np->pci_dev->irq, dev);
3905                 if (np->msi_flags & NV_MSI_ENABLED) {
3906                         pci_disable_msi(np->pci_dev);
3907                         np->msi_flags &= ~NV_MSI_ENABLED;
3908                 }
3909         }
3910 }
3911
3912 static void nv_do_nic_poll(unsigned long data)
3913 {
3914         struct net_device *dev = (struct net_device *) data;
3915         struct fe_priv *np = netdev_priv(dev);
3916         u8 __iomem *base = get_hwbase(dev);
3917         u32 mask = 0;
3918
3919         /*
3920          * First disable irq(s) and then
3921          * reenable interrupts on the nic, we have to do this before calling
3922          * nv_nic_irq because that may decide to do otherwise
3923          */
3924
3925         if (!using_multi_irqs(dev)) {
3926                 if (np->msi_flags & NV_MSI_X_ENABLED)
3927                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3928                 else
3929                         disable_irq_lockdep(np->pci_dev->irq);
3930                 mask = np->irqmask;
3931         } else {
3932                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3933                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3934                         mask |= NVREG_IRQ_RX_ALL;
3935                 }
3936                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3937                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3938                         mask |= NVREG_IRQ_TX_ALL;
3939                 }
3940                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3941                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3942                         mask |= NVREG_IRQ_OTHER;
3943                 }
3944         }
3945         np->nic_poll_irq = 0;
3946
3947         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3948
3949         if (np->recover_error) {
3950                 np->recover_error = 0;
3951                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3952                 if (netif_running(dev)) {
3953                         netif_tx_lock_bh(dev);
3954                         spin_lock(&np->lock);
3955                         /* stop engines */
3956                         nv_stop_rxtx(dev);
3957                         nv_txrx_reset(dev);
3958                         /* drain rx queue */
3959                         nv_drain_rxtx(dev);
3960                         /* reinit driver view of the rx queue */
3961                         set_bufsize(dev);
3962                         if (nv_init_ring(dev)) {
3963                                 if (!np->in_shutdown)
3964                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3965                         }
3966                         /* reinit nic view of the rx queue */
3967                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3968                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3969                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3970                                 base + NvRegRingSizes);
3971                         pci_push(base);
3972                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3973                         pci_push(base);
3974
3975                         /* restart rx engine */
3976                         nv_start_rxtx(dev);
3977                         spin_unlock(&np->lock);
3978                         netif_tx_unlock_bh(dev);
3979                 }
3980         }
3981
3982
3983         writel(mask, base + NvRegIrqMask);
3984         pci_push(base);
3985
3986         if (!using_multi_irqs(dev)) {
3987                 if (nv_optimized(np))
3988                         nv_nic_irq_optimized(0, dev);
3989                 else
3990                         nv_nic_irq(0, dev);
3991                 if (np->msi_flags & NV_MSI_X_ENABLED)
3992                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3993                 else
3994                         enable_irq_lockdep(np->pci_dev->irq);
3995         } else {
3996                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3997                         nv_nic_irq_rx(0, dev);
3998                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3999                 }
4000                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4001                         nv_nic_irq_tx(0, dev);
4002                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4003                 }
4004                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4005                         nv_nic_irq_other(0, dev);
4006                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4007                 }
4008         }
4009 }
4010
4011 #ifdef CONFIG_NET_POLL_CONTROLLER
4012 static void nv_poll_controller(struct net_device *dev)
4013 {
4014         nv_do_nic_poll((unsigned long) dev);
4015 }
4016 #endif
4017
4018 static void nv_do_stats_poll(unsigned long data)
4019 {
4020         struct net_device *dev = (struct net_device *) data;
4021         struct fe_priv *np = netdev_priv(dev);
4022
4023         nv_get_hw_stats(dev);
4024
4025         if (!np->in_shutdown)
4026                 mod_timer(&np->stats_poll,
4027                         round_jiffies(jiffies + STATS_INTERVAL));
4028 }
4029
4030 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4031 {
4032         struct fe_priv *np = netdev_priv(dev);
4033         strcpy(info->driver, DRV_NAME);
4034         strcpy(info->version, FORCEDETH_VERSION);
4035         strcpy(info->bus_info, pci_name(np->pci_dev));
4036 }
4037
4038 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4039 {
4040         struct fe_priv *np = netdev_priv(dev);
4041         wolinfo->supported = WAKE_MAGIC;
4042
4043         spin_lock_irq(&np->lock);
4044         if (np->wolenabled)
4045                 wolinfo->wolopts = WAKE_MAGIC;
4046         spin_unlock_irq(&np->lock);
4047 }
4048
4049 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4050 {
4051         struct fe_priv *np = netdev_priv(dev);
4052         u8 __iomem *base = get_hwbase(dev);
4053         u32 flags = 0;
4054
4055         if (wolinfo->wolopts == 0) {
4056                 np->wolenabled = 0;
4057         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4058                 np->wolenabled = 1;
4059                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4060         }
4061         if (netif_running(dev)) {
4062                 spin_lock_irq(&np->lock);
4063                 writel(flags, base + NvRegWakeUpFlags);
4064                 spin_unlock_irq(&np->lock);
4065         }
4066         return 0;
4067 }
4068
4069 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4070 {
4071         struct fe_priv *np = netdev_priv(dev);
4072         int adv;
4073
4074         spin_lock_irq(&np->lock);
4075         ecmd->port = PORT_MII;
4076         if (!netif_running(dev)) {
4077                 /* We do not track link speed / duplex setting if the
4078                  * interface is disabled. Force a link check */
4079                 if (nv_update_linkspeed(dev)) {
4080                         if (!netif_carrier_ok(dev))
4081                                 netif_carrier_on(dev);
4082                 } else {
4083                         if (netif_carrier_ok(dev))
4084                                 netif_carrier_off(dev);
4085                 }
4086         }
4087
4088         if (netif_carrier_ok(dev)) {
4089                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4090                 case NVREG_LINKSPEED_10:
4091                         ecmd->speed = SPEED_10;
4092                         break;
4093                 case NVREG_LINKSPEED_100:
4094                         ecmd->speed = SPEED_100;
4095                         break;
4096                 case NVREG_LINKSPEED_1000:
4097                         ecmd->speed = SPEED_1000;
4098                         break;
4099                 }
4100                 ecmd->duplex = DUPLEX_HALF;
4101                 if (np->duplex)
4102                         ecmd->duplex = DUPLEX_FULL;
4103         } else {
4104                 ecmd->speed = -1;
4105                 ecmd->duplex = -1;
4106         }
4107
4108         ecmd->autoneg = np->autoneg;
4109
4110         ecmd->advertising = ADVERTISED_MII;
4111         if (np->autoneg) {
4112                 ecmd->advertising |= ADVERTISED_Autoneg;
4113                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4114                 if (adv & ADVERTISE_10HALF)
4115                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4116                 if (adv & ADVERTISE_10FULL)
4117                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4118                 if (adv & ADVERTISE_100HALF)
4119                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4120                 if (adv & ADVERTISE_100FULL)
4121                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4122                 if (np->gigabit == PHY_GIGABIT) {
4123                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4124                         if (adv & ADVERTISE_1000FULL)
4125                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4126                 }
4127         }
4128         ecmd->supported = (SUPPORTED_Autoneg |
4129                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4130                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4131                 SUPPORTED_MII);
4132         if (np->gigabit == PHY_GIGABIT)
4133                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4134
4135         ecmd->phy_address = np->phyaddr;
4136         ecmd->transceiver = XCVR_EXTERNAL;
4137
4138         /* ignore maxtxpkt, maxrxpkt for now */
4139         spin_unlock_irq(&np->lock);
4140         return 0;
4141 }
4142
4143 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4144 {
4145         struct fe_priv *np = netdev_priv(dev);
4146
4147         if (ecmd->port != PORT_MII)
4148                 return -EINVAL;
4149         if (ecmd->transceiver != XCVR_EXTERNAL)
4150                 return -EINVAL;
4151         if (ecmd->phy_address != np->phyaddr) {
4152                 /* TODO: support switching between multiple phys. Should be
4153                  * trivial, but not enabled due to lack of test hardware. */
4154                 return -EINVAL;
4155         }
4156         if (ecmd->autoneg == AUTONEG_ENABLE) {
4157                 u32 mask;
4158
4159                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4160                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4161                 if (np->gigabit == PHY_GIGABIT)
4162                         mask |= ADVERTISED_1000baseT_Full;
4163
4164                 if ((ecmd->advertising & mask) == 0)
4165                         return -EINVAL;
4166
4167         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4168                 /* Note: autonegotiation disable, speed 1000 intentionally
4169                  * forbidden - noone should need that. */
4170
4171                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4172                         return -EINVAL;
4173                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4174                         return -EINVAL;
4175         } else {
4176                 return -EINVAL;
4177         }
4178
4179         netif_carrier_off(dev);
4180         if (netif_running(dev)) {
4181                 nv_disable_irq(dev);
4182                 netif_tx_lock_bh(dev);
4183                 spin_lock(&np->lock);
4184                 /* stop engines */
4185                 nv_stop_rxtx(dev);
4186                 spin_unlock(&np->lock);
4187                 netif_tx_unlock_bh(dev);
4188         }
4189
4190         if (ecmd->autoneg == AUTONEG_ENABLE) {
4191                 int adv, bmcr;
4192
4193                 np->autoneg = 1;
4194
4195                 /* advertise only what has been requested */
4196                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4197                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4198                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4199                         adv |= ADVERTISE_10HALF;
4200                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4201                         adv |= ADVERTISE_10FULL;
4202                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4203                         adv |= ADVERTISE_100HALF;
4204                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4205                         adv |= ADVERTISE_100FULL;
4206                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4207                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4208                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4209                         adv |=  ADVERTISE_PAUSE_ASYM;
4210                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4211
4212                 if (np->gigabit == PHY_GIGABIT) {
4213                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4214                         adv &= ~ADVERTISE_1000FULL;
4215                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4216                                 adv |= ADVERTISE_1000FULL;
4217                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4218                 }
4219
4220                 if (netif_running(dev))
4221                         printk(KERN_INFO "%s: link down.\n", dev->name);
4222                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4223                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4224                         bmcr |= BMCR_ANENABLE;
4225                         /* reset the phy in order for settings to stick,
4226                          * and cause autoneg to start */
4227                         if (phy_reset(dev, bmcr)) {
4228                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4229                                 return -EINVAL;
4230                         }
4231                 } else {
4232                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4233                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4234                 }
4235         } else {
4236                 int adv, bmcr;
4237
4238                 np->autoneg = 0;
4239
4240                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4241                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4242                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4243                         adv |= ADVERTISE_10HALF;
4244                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4245                         adv |= ADVERTISE_10FULL;
4246                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4247                         adv |= ADVERTISE_100HALF;
4248                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4249                         adv |= ADVERTISE_100FULL;
4250                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4251                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4252                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4253                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4254                 }
4255                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4256                         adv |=  ADVERTISE_PAUSE_ASYM;
4257                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4258                 }
4259                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4260                 np->fixed_mode = adv;
4261
4262                 if (np->gigabit == PHY_GIGABIT) {
4263                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4264                         adv &= ~ADVERTISE_1000FULL;
4265                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4266                 }
4267
4268                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4269                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4270                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4271                         bmcr |= BMCR_FULLDPLX;
4272                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4273                         bmcr |= BMCR_SPEED100;
4274                 if (np->phy_oui == PHY_OUI_MARVELL) {
4275                         /* reset the phy in order for forced mode settings to stick */
4276                         if (phy_reset(dev, bmcr)) {
4277                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4278                                 return -EINVAL;
4279                         }
4280                 } else {
4281                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4282                         if (netif_running(dev)) {
4283                                 /* Wait a bit and then reconfigure the nic. */
4284                                 udelay(10);
4285                                 nv_linkchange(dev);
4286                         }
4287                 }
4288         }
4289
4290         if (netif_running(dev)) {
4291                 nv_start_rxtx(dev);
4292                 nv_enable_irq(dev);
4293         }
4294
4295         return 0;
4296 }
4297
4298 #define FORCEDETH_REGS_VER      1
4299
4300 static int nv_get_regs_len(struct net_device *dev)
4301 {
4302         struct fe_priv *np = netdev_priv(dev);
4303         return np->register_size;
4304 }
4305
4306 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4307 {
4308         struct fe_priv *np = netdev_priv(dev);
4309         u8 __iomem *base = get_hwbase(dev);
4310         u32 *rbuf = buf;
4311         int i;
4312
4313         regs->version = FORCEDETH_REGS_VER;
4314         spin_lock_irq(&np->lock);
4315         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4316                 rbuf[i] = readl(base + i*sizeof(u32));
4317         spin_unlock_irq(&np->lock);
4318 }
4319
4320 static int nv_nway_reset(struct net_device *dev)
4321 {
4322         struct fe_priv *np = netdev_priv(dev);
4323         int ret;
4324
4325         if (np->autoneg) {
4326                 int bmcr;
4327
4328                 netif_carrier_off(dev);
4329                 if (netif_running(dev)) {
4330                         nv_disable_irq(dev);
4331                         netif_tx_lock_bh(dev);
4332                         spin_lock(&np->lock);
4333                         /* stop engines */
4334                         nv_stop_rxtx(dev);
4335                         spin_unlock(&np->lock);
4336                         netif_tx_unlock_bh(dev);
4337                         printk(KERN_INFO "%s: link down.\n", dev->name);
4338                 }
4339
4340                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4341                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4342                         bmcr |= BMCR_ANENABLE;
4343                         /* reset the phy in order for settings to stick*/
4344                         if (phy_reset(dev, bmcr)) {
4345                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4346                                 return -EINVAL;
4347                         }
4348                 } else {
4349                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4350                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4351                 }
4352
4353                 if (netif_running(dev)) {
4354                         nv_start_rxtx(dev);
4355                         nv_enable_irq(dev);
4356                 }
4357                 ret = 0;
4358         } else {
4359                 ret = -EINVAL;
4360         }
4361
4362         return ret;
4363 }
4364
4365 static int nv_set_tso(struct net_device *dev, u32 value)
4366 {
4367         struct fe_priv *np = netdev_priv(dev);
4368
4369         if ((np->driver_data & DEV_HAS_CHECKSUM))
4370                 return ethtool_op_set_tso(dev, value);
4371         else
4372                 return -EOPNOTSUPP;
4373 }
4374
4375 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4376 {
4377         struct fe_priv *np = netdev_priv(dev);
4378
4379         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4380         ring->rx_mini_max_pending = 0;
4381         ring->rx_jumbo_max_pending = 0;
4382         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4383
4384         ring->rx_pending = np->rx_ring_size;
4385         ring->rx_mini_pending = 0;
4386         ring->rx_jumbo_pending = 0;
4387         ring->tx_pending = np->tx_ring_size;
4388 }
4389
4390 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4391 {
4392         struct fe_priv *np = netdev_priv(dev);
4393         u8 __iomem *base = get_hwbase(dev);
4394         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4395         dma_addr_t ring_addr;
4396
4397         if (ring->rx_pending < RX_RING_MIN ||
4398             ring->tx_pending < TX_RING_MIN ||
4399             ring->rx_mini_pending != 0 ||
4400             ring->rx_jumbo_pending != 0 ||
4401             (np->desc_ver == DESC_VER_1 &&
4402              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4403               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4404             (np->desc_ver != DESC_VER_1 &&
4405              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4406               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4407                 return -EINVAL;
4408         }
4409
4410         /* allocate new rings */
4411         if (!nv_optimized(np)) {
4412                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4413                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4414                                             &ring_addr);
4415         } else {
4416                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4417                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4418                                             &ring_addr);
4419         }
4420         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4421         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4422         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4423                 /* fall back to old rings */
4424                 if (!nv_optimized(np)) {
4425                         if (rxtx_ring)
4426                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4427                                                     rxtx_ring, ring_addr);
4428                 } else {
4429                         if (rxtx_ring)
4430                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4431                                                     rxtx_ring, ring_addr);
4432                 }
4433                 if (rx_skbuff)
4434                         kfree(rx_skbuff);
4435                 if (tx_skbuff)
4436                         kfree(tx_skbuff);
4437                 goto exit;
4438         }
4439
4440         if (netif_running(dev)) {
4441                 nv_disable_irq(dev);
4442                 netif_tx_lock_bh(dev);
4443                 spin_lock(&np->lock);
4444                 /* stop engines */
4445                 nv_stop_rxtx(dev);
4446                 nv_txrx_reset(dev);
4447                 /* drain queues */
4448                 nv_drain_rxtx(dev);
4449                 /* delete queues */
4450                 free_rings(dev);
4451         }
4452
4453         /* set new values */
4454         np->rx_ring_size = ring->rx_pending;
4455         np->tx_ring_size = ring->tx_pending;
4456
4457         if (!nv_optimized(np)) {
4458                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4459                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4460         } else {
4461                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4462                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4463         }
4464         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4465         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4466         np->ring_addr = ring_addr;
4467
4468         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4469         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4470
4471         if (netif_running(dev)) {
4472                 /* reinit driver view of the queues */
4473                 set_bufsize(dev);
4474                 if (nv_init_ring(dev)) {
4475                         if (!np->in_shutdown)
4476                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4477                 }
4478
4479                 /* reinit nic view of the queues */
4480                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4481                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4482                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4483                         base + NvRegRingSizes);
4484                 pci_push(base);
4485                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4486                 pci_push(base);
4487
4488                 /* restart engines */
4489                 nv_start_rxtx(dev);
4490                 spin_unlock(&np->lock);
4491                 netif_tx_unlock_bh(dev);
4492                 nv_enable_irq(dev);
4493         }
4494         return 0;
4495 exit:
4496         return -ENOMEM;
4497 }
4498
4499 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4500 {
4501         struct fe_priv *np = netdev_priv(dev);
4502
4503         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4504         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4505         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4506 }
4507
4508 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4509 {
4510         struct fe_priv *np = netdev_priv(dev);
4511         int adv, bmcr;
4512
4513         if ((!np->autoneg && np->duplex == 0) ||
4514             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4515                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4516                        dev->name);
4517                 return -EINVAL;
4518         }
4519         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4520                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4521                 return -EINVAL;
4522         }
4523
4524         netif_carrier_off(dev);
4525         if (netif_running(dev)) {
4526                 nv_disable_irq(dev);
4527                 netif_tx_lock_bh(dev);
4528                 spin_lock(&np->lock);
4529                 /* stop engines */
4530                 nv_stop_rxtx(dev);
4531                 spin_unlock(&np->lock);
4532                 netif_tx_unlock_bh(dev);
4533         }
4534
4535         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4536         if (pause->rx_pause)
4537                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4538         if (pause->tx_pause)
4539                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4540
4541         if (np->autoneg && pause->autoneg) {
4542                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4543
4544                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4545                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4546                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4547                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4548                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4549                         adv |=  ADVERTISE_PAUSE_ASYM;
4550                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4551
4552                 if (netif_running(dev))
4553                         printk(KERN_INFO "%s: link down.\n", dev->name);
4554                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4555                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4556                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4557         } else {
4558                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4559                 if (pause->rx_pause)
4560                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4561                 if (pause->tx_pause)
4562                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4563
4564                 if (!netif_running(dev))
4565                         nv_update_linkspeed(dev);
4566                 else
4567                         nv_update_pause(dev, np->pause_flags);
4568         }
4569
4570         if (netif_running(dev)) {
4571                 nv_start_rxtx(dev);
4572                 nv_enable_irq(dev);
4573         }
4574         return 0;
4575 }
4576
4577 static u32 nv_get_rx_csum(struct net_device *dev)
4578 {
4579         struct fe_priv *np = netdev_priv(dev);
4580         return (np->rx_csum) != 0;
4581 }
4582
4583 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4584 {
4585         struct fe_priv *np = netdev_priv(dev);
4586         u8 __iomem *base = get_hwbase(dev);
4587         int retcode = 0;
4588
4589         if (np->driver_data & DEV_HAS_CHECKSUM) {
4590                 if (data) {
4591                         np->rx_csum = 1;
4592                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4593                 } else {
4594                         np->rx_csum = 0;
4595                         /* vlan is dependent on rx checksum offload */
4596                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4597                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4598                 }
4599                 if (netif_running(dev)) {
4600                         spin_lock_irq(&np->lock);
4601                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4602                         spin_unlock_irq(&np->lock);
4603                 }
4604         } else {
4605                 return -EINVAL;
4606         }
4607
4608         return retcode;
4609 }
4610
4611 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4612 {
4613         struct fe_priv *np = netdev_priv(dev);
4614
4615         if (np->driver_data & DEV_HAS_CHECKSUM)
4616                 return ethtool_op_set_tx_hw_csum(dev, data);
4617         else
4618                 return -EOPNOTSUPP;
4619 }
4620
4621 static int nv_set_sg(struct net_device *dev, u32 data)
4622 {
4623         struct fe_priv *np = netdev_priv(dev);
4624
4625         if (np->driver_data & DEV_HAS_CHECKSUM)
4626                 return ethtool_op_set_sg(dev, data);
4627         else
4628                 return -EOPNOTSUPP;
4629 }
4630
4631 static int nv_get_sset_count(struct net_device *dev, int sset)
4632 {
4633         struct fe_priv *np = netdev_priv(dev);
4634
4635         switch (sset) {
4636         case ETH_SS_TEST:
4637                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4638                         return NV_TEST_COUNT_EXTENDED;
4639                 else
4640                         return NV_TEST_COUNT_BASE;
4641         case ETH_SS_STATS:
4642                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4643                         return NV_DEV_STATISTICS_V1_COUNT;
4644                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4645                         return NV_DEV_STATISTICS_V2_COUNT;
4646                 else
4647                         return 0;
4648         default:
4649                 return -EOPNOTSUPP;
4650         }
4651 }
4652
4653 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4654 {
4655         struct fe_priv *np = netdev_priv(dev);
4656
4657         /* update stats */
4658         nv_do_stats_poll((unsigned long)dev);
4659
4660         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4661 }
4662
4663 static int nv_link_test(struct net_device *dev)
4664 {
4665         struct fe_priv *np = netdev_priv(dev);
4666         int mii_status;
4667
4668         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4669         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4670
4671         /* check phy link status */
4672         if (!(mii_status & BMSR_LSTATUS))
4673                 return 0;
4674         else
4675                 return 1;
4676 }
4677
4678 static int nv_register_test(struct net_device *dev)
4679 {
4680         u8 __iomem *base = get_hwbase(dev);
4681         int i = 0;
4682         u32 orig_read, new_read;
4683
4684         do {
4685                 orig_read = readl(base + nv_registers_test[i].reg);
4686
4687                 /* xor with mask to toggle bits */
4688                 orig_read ^= nv_registers_test[i].mask;
4689
4690                 writel(orig_read, base + nv_registers_test[i].reg);
4691
4692                 new_read = readl(base + nv_registers_test[i].reg);
4693
4694                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4695                         return 0;
4696
4697                 /* restore original value */
4698                 orig_read ^= nv_registers_test[i].mask;
4699                 writel(orig_read, base + nv_registers_test[i].reg);
4700
4701         } while (nv_registers_test[++i].reg != 0);
4702
4703         return 1;
4704 }
4705
4706 static int nv_interrupt_test(struct net_device *dev)
4707 {
4708         struct fe_priv *np = netdev_priv(dev);
4709         u8 __iomem *base = get_hwbase(dev);
4710         int ret = 1;
4711         int testcnt;
4712         u32 save_msi_flags, save_poll_interval = 0;
4713
4714         if (netif_running(dev)) {
4715                 /* free current irq */
4716                 nv_free_irq(dev);
4717                 save_poll_interval = readl(base+NvRegPollingInterval);
4718         }
4719
4720         /* flag to test interrupt handler */
4721         np->intr_test = 0;
4722
4723         /* setup test irq */
4724         save_msi_flags = np->msi_flags;
4725         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4726         np->msi_flags |= 0x001; /* setup 1 vector */
4727         if (nv_request_irq(dev, 1))
4728                 return 0;
4729
4730         /* setup timer interrupt */
4731         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4732         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4733
4734         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4735
4736         /* wait for at least one interrupt */
4737         msleep(100);
4738
4739         spin_lock_irq(&np->lock);
4740
4741         /* flag should be set within ISR */
4742         testcnt = np->intr_test;
4743         if (!testcnt)
4744                 ret = 2;
4745
4746         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4747         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4748                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4749         else
4750                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4751
4752         spin_unlock_irq(&np->lock);
4753
4754         nv_free_irq(dev);
4755
4756         np->msi_flags = save_msi_flags;
4757
4758         if (netif_running(dev)) {
4759                 writel(save_poll_interval, base + NvRegPollingInterval);
4760                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4761                 /* restore original irq */
4762                 if (nv_request_irq(dev, 0))
4763                         return 0;
4764         }
4765
4766         return ret;
4767 }
4768
4769 static int nv_loopback_test(struct net_device *dev)
4770 {
4771         struct fe_priv *np = netdev_priv(dev);
4772         u8 __iomem *base = get_hwbase(dev);
4773         struct sk_buff *tx_skb, *rx_skb;
4774         dma_addr_t test_dma_addr;
4775         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4776         u32 flags;
4777         int len, i, pkt_len;
4778         u8 *pkt_data;
4779         u32 filter_flags = 0;
4780         u32 misc1_flags = 0;
4781         int ret = 1;
4782
4783         if (netif_running(dev)) {
4784                 nv_disable_irq(dev);
4785                 filter_flags = readl(base + NvRegPacketFilterFlags);
4786                 misc1_flags = readl(base + NvRegMisc1);
4787         } else {
4788                 nv_txrx_reset(dev);
4789         }
4790
4791         /* reinit driver view of the rx queue */
4792         set_bufsize(dev);
4793         nv_init_ring(dev);
4794
4795         /* setup hardware for loopback */
4796         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4797         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4798
4799         /* reinit nic view of the rx queue */
4800         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4801         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4802         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4803                 base + NvRegRingSizes);
4804         pci_push(base);
4805
4806         /* restart rx engine */
4807         nv_start_rxtx(dev);
4808
4809         /* setup packet for tx */
4810         pkt_len = ETH_DATA_LEN;
4811         tx_skb = dev_alloc_skb(pkt_len);
4812         if (!tx_skb) {
4813                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4814                          " of %s\n", dev->name);
4815                 ret = 0;
4816                 goto out;
4817         }
4818         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4819                                        skb_tailroom(tx_skb),
4820                                        PCI_DMA_FROMDEVICE);
4821         pkt_data = skb_put(tx_skb, pkt_len);
4822         for (i = 0; i < pkt_len; i++)
4823                 pkt_data[i] = (u8)(i & 0xff);
4824
4825         if (!nv_optimized(np)) {
4826                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4827                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4828         } else {
4829                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4830                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4831                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4832         }
4833         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4834         pci_push(get_hwbase(dev));
4835
4836         msleep(500);
4837
4838         /* check for rx of the packet */
4839         if (!nv_optimized(np)) {
4840                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4841                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4842
4843         } else {
4844                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4845                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4846         }
4847
4848         if (flags & NV_RX_AVAIL) {
4849                 ret = 0;
4850         } else if (np->desc_ver == DESC_VER_1) {
4851                 if (flags & NV_RX_ERROR)
4852                         ret = 0;
4853         } else {
4854                 if (flags & NV_RX2_ERROR) {
4855                         ret = 0;
4856                 }
4857         }
4858
4859         if (ret) {
4860                 if (len != pkt_len) {
4861                         ret = 0;
4862                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4863                                 dev->name, len, pkt_len);
4864                 } else {
4865                         rx_skb = np->rx_skb[0].skb;
4866                         for (i = 0; i < pkt_len; i++) {
4867                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4868                                         ret = 0;
4869                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4870                                                 dev->name, i);
4871                                         break;
4872                                 }
4873                         }
4874                 }
4875         } else {
4876                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4877         }
4878
4879         pci_unmap_page(np->pci_dev, test_dma_addr,
4880                        (skb_end_pointer(tx_skb) - tx_skb->data),
4881                        PCI_DMA_TODEVICE);
4882         dev_kfree_skb_any(tx_skb);
4883  out:
4884         /* stop engines */
4885         nv_stop_rxtx(dev);
4886         nv_txrx_reset(dev);
4887         /* drain rx queue */
4888         nv_drain_rxtx(dev);
4889
4890         if (netif_running(dev)) {
4891                 writel(misc1_flags, base + NvRegMisc1);
4892                 writel(filter_flags, base + NvRegPacketFilterFlags);
4893                 nv_enable_irq(dev);
4894         }
4895
4896         return ret;
4897 }
4898
4899 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4900 {
4901         struct fe_priv *np = netdev_priv(dev);
4902         u8 __iomem *base = get_hwbase(dev);
4903         int result;
4904         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4905
4906         if (!nv_link_test(dev)) {
4907                 test->flags |= ETH_TEST_FL_FAILED;
4908                 buffer[0] = 1;
4909         }
4910
4911         if (test->flags & ETH_TEST_FL_OFFLINE) {
4912                 if (netif_running(dev)) {
4913                         netif_stop_queue(dev);
4914 #ifdef CONFIG_FORCEDETH_NAPI
4915                         napi_disable(&np->napi);
4916 #endif
4917                         netif_tx_lock_bh(dev);
4918                         spin_lock_irq(&np->lock);
4919                         nv_disable_hw_interrupts(dev, np->irqmask);
4920                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4921                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4922                         } else {
4923                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4924                         }
4925                         /* stop engines */
4926                         nv_stop_rxtx(dev);
4927                         nv_txrx_reset(dev);
4928                         /* drain rx queue */
4929                         nv_drain_rxtx(dev);
4930                         spin_unlock_irq(&np->lock);
4931                         netif_tx_unlock_bh(dev);
4932                 }
4933
4934                 if (!nv_register_test(dev)) {
4935                         test->flags |= ETH_TEST_FL_FAILED;
4936                         buffer[1] = 1;
4937                 }
4938
4939                 result = nv_interrupt_test(dev);
4940                 if (result != 1) {
4941                         test->flags |= ETH_TEST_FL_FAILED;
4942                         buffer[2] = 1;
4943                 }
4944                 if (result == 0) {
4945                         /* bail out */
4946                         return;
4947                 }
4948
4949                 if (!nv_loopback_test(dev)) {
4950                         test->flags |= ETH_TEST_FL_FAILED;
4951                         buffer[3] = 1;
4952                 }
4953
4954                 if (netif_running(dev)) {
4955                         /* reinit driver view of the rx queue */
4956                         set_bufsize(dev);
4957                         if (nv_init_ring(dev)) {
4958                                 if (!np->in_shutdown)
4959                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4960                         }
4961                         /* reinit nic view of the rx queue */
4962                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4963                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4964                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4965                                 base + NvRegRingSizes);
4966                         pci_push(base);
4967                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4968                         pci_push(base);
4969                         /* restart rx engine */
4970                         nv_start_rxtx(dev);
4971                         netif_start_queue(dev);
4972 #ifdef CONFIG_FORCEDETH_NAPI
4973                         napi_enable(&np->napi);
4974 #endif
4975                         nv_enable_hw_interrupts(dev, np->irqmask);
4976                 }
4977         }
4978 }
4979
4980 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4981 {
4982         switch (stringset) {
4983         case ETH_SS_STATS:
4984                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4985                 break;
4986         case ETH_SS_TEST:
4987                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4988                 break;
4989         }
4990 }
4991
4992 static const struct ethtool_ops ops = {
4993         .get_drvinfo = nv_get_drvinfo,
4994         .get_link = ethtool_op_get_link,
4995         .get_wol = nv_get_wol,
4996         .set_wol = nv_set_wol,
4997         .get_settings = nv_get_settings,
4998         .set_settings = nv_set_settings,
4999         .get_regs_len = nv_get_regs_len,
5000         .get_regs = nv_get_regs,
5001         .nway_reset = nv_nway_reset,
5002         .set_tso = nv_set_tso,
5003         .get_ringparam = nv_get_ringparam,
5004         .set_ringparam = nv_set_ringparam,
5005         .get_pauseparam = nv_get_pauseparam,
5006         .set_pauseparam = nv_set_pauseparam,
5007         .get_rx_csum = nv_get_rx_csum,
5008         .set_rx_csum = nv_set_rx_csum,
5009         .set_tx_csum = nv_set_tx_csum,
5010         .set_sg = nv_set_sg,
5011         .get_strings = nv_get_strings,
5012         .get_ethtool_stats = nv_get_ethtool_stats,
5013         .get_sset_count = nv_get_sset_count,
5014         .self_test = nv_self_test,
5015 };
5016
5017 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5018 {
5019         struct fe_priv *np = get_nvpriv(dev);
5020
5021         spin_lock_irq(&np->lock);
5022
5023         /* save vlan group */
5024         np->vlangrp = grp;
5025
5026         if (grp) {
5027                 /* enable vlan on MAC */
5028                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5029         } else {
5030                 /* disable vlan on MAC */
5031                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5032                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5033         }
5034
5035         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5036
5037         spin_unlock_irq(&np->lock);
5038 }
5039
5040 /* The mgmt unit and driver use a semaphore to access the phy during init */
5041 static int nv_mgmt_acquire_sema(struct net_device *dev)
5042 {
5043         u8 __iomem *base = get_hwbase(dev);
5044         int i;
5045         u32 tx_ctrl, mgmt_sema;
5046
5047         for (i = 0; i < 10; i++) {
5048                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5049                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5050                         break;
5051                 msleep(500);
5052         }
5053
5054         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5055                 return 0;
5056
5057         for (i = 0; i < 2; i++) {
5058                 tx_ctrl = readl(base + NvRegTransmitterControl);
5059                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5060                 writel(tx_ctrl, base + NvRegTransmitterControl);
5061
5062                 /* verify that semaphore was acquired */
5063                 tx_ctrl = readl(base + NvRegTransmitterControl);
5064                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5065                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5066                         return 1;
5067                 else
5068                         udelay(50);
5069         }
5070
5071         return 0;
5072 }
5073
5074 static int nv_open(struct net_device *dev)
5075 {
5076         struct fe_priv *np = netdev_priv(dev);
5077         u8 __iomem *base = get_hwbase(dev);
5078         int ret = 1;
5079         int oom, i;
5080         u32 low;
5081
5082         dprintk(KERN_DEBUG "nv_open: begin\n");
5083
5084         /* erase previous misconfiguration */
5085         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5086                 nv_mac_reset(dev);
5087         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5088         writel(0, base + NvRegMulticastAddrB);
5089         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5090         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5091         writel(0, base + NvRegPacketFilterFlags);
5092
5093         writel(0, base + NvRegTransmitterControl);
5094         writel(0, base + NvRegReceiverControl);
5095
5096         writel(0, base + NvRegAdapterControl);
5097
5098         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5099                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5100
5101         /* initialize descriptor rings */
5102         set_bufsize(dev);
5103         oom = nv_init_ring(dev);
5104
5105         writel(0, base + NvRegLinkSpeed);
5106         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5107         nv_txrx_reset(dev);
5108         writel(0, base + NvRegUnknownSetupReg6);
5109
5110         np->in_shutdown = 0;
5111
5112         /* give hw rings */
5113         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5114         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5115                 base + NvRegRingSizes);
5116
5117         writel(np->linkspeed, base + NvRegLinkSpeed);
5118         if (np->desc_ver == DESC_VER_1)
5119                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5120         else
5121                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5122         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5123         writel(np->vlanctl_bits, base + NvRegVlanControl);
5124         pci_push(base);
5125         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5126         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5127                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5128                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5129
5130         writel(0, base + NvRegMIIMask);
5131         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5132         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5133
5134         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5135         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5136         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5137         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5138
5139         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5140
5141         get_random_bytes(&low, sizeof(low));
5142         low &= NVREG_SLOTTIME_MASK;
5143         if (np->desc_ver == DESC_VER_1) {
5144                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5145         } else {
5146                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5147                         /* setup legacy backoff */
5148                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5149                 } else {
5150                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5151                         nv_gear_backoff_reseed(dev);
5152                 }
5153         }
5154         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5155         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5156         if (poll_interval == -1) {
5157                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5158                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5159                 else
5160                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5161         }
5162         else
5163                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5164         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5165         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5166                         base + NvRegAdapterControl);
5167         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5168         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5169         if (np->wolenabled)
5170                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5171
5172         i = readl(base + NvRegPowerState);
5173         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5174                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5175
5176         pci_push(base);
5177         udelay(10);
5178         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5179
5180         nv_disable_hw_interrupts(dev, np->irqmask);
5181         pci_push(base);
5182         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5183         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5184         pci_push(base);
5185
5186         if (nv_request_irq(dev, 0)) {
5187                 goto out_drain;
5188         }
5189
5190         /* ask for interrupts */
5191         nv_enable_hw_interrupts(dev, np->irqmask);
5192
5193         spin_lock_irq(&np->lock);
5194         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5195         writel(0, base + NvRegMulticastAddrB);
5196         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5197         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5198         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5199         /* One manual link speed update: Interrupts are enabled, future link
5200          * speed changes cause interrupts and are handled by nv_link_irq().
5201          */
5202         {
5203                 u32 miistat;
5204                 miistat = readl(base + NvRegMIIStatus);
5205                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5206                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5207         }
5208         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5209          * to init hw */
5210         np->linkspeed = 0;
5211         ret = nv_update_linkspeed(dev);
5212         nv_start_rxtx(dev);
5213         netif_start_queue(dev);
5214 #ifdef CONFIG_FORCEDETH_NAPI
5215         napi_enable(&np->napi);
5216 #endif
5217
5218         if (ret) {
5219                 netif_carrier_on(dev);
5220         } else {
5221                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5222                 netif_carrier_off(dev);
5223         }
5224         if (oom)
5225                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5226
5227         /* start statistics timer */
5228         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
5229                 mod_timer(&np->stats_poll,
5230                         round_jiffies(jiffies + STATS_INTERVAL));
5231
5232         spin_unlock_irq(&np->lock);
5233
5234         return 0;
5235 out_drain:
5236         nv_drain_rxtx(dev);
5237         return ret;
5238 }
5239
5240 static int nv_close(struct net_device *dev)
5241 {
5242         struct fe_priv *np = netdev_priv(dev);
5243         u8 __iomem *base;
5244
5245         spin_lock_irq(&np->lock);
5246         np->in_shutdown = 1;
5247         spin_unlock_irq(&np->lock);
5248 #ifdef CONFIG_FORCEDETH_NAPI
5249         napi_disable(&np->napi);
5250 #endif
5251         synchronize_irq(np->pci_dev->irq);
5252
5253         del_timer_sync(&np->oom_kick);
5254         del_timer_sync(&np->nic_poll);
5255         del_timer_sync(&np->stats_poll);
5256
5257         netif_stop_queue(dev);
5258         spin_lock_irq(&np->lock);
5259         nv_stop_rxtx(dev);
5260         nv_txrx_reset(dev);
5261
5262         /* disable interrupts on the nic or we will lock up */
5263         base = get_hwbase(dev);
5264         nv_disable_hw_interrupts(dev, np->irqmask);
5265         pci_push(base);
5266         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5267
5268         spin_unlock_irq(&np->lock);
5269
5270         nv_free_irq(dev);
5271
5272         nv_drain_rxtx(dev);
5273
5274         if (np->wolenabled) {
5275                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5276                 nv_start_rx(dev);
5277         }
5278
5279         /* FIXME: power down nic */
5280
5281         return 0;
5282 }
5283
5284 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5285 {
5286         struct net_device *dev;
5287         struct fe_priv *np;
5288         unsigned long addr;
5289         u8 __iomem *base;
5290         int err, i;
5291         u32 powerstate, txreg;
5292         u32 phystate_orig = 0, phystate;
5293         int phyinitialized = 0;
5294         DECLARE_MAC_BUF(mac);
5295         static int printed_version;
5296
5297         if (!printed_version++)
5298                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5299                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5300
5301         dev = alloc_etherdev(sizeof(struct fe_priv));
5302         err = -ENOMEM;
5303         if (!dev)
5304                 goto out;
5305
5306         np = netdev_priv(dev);
5307         np->dev = dev;
5308         np->pci_dev = pci_dev;
5309         spin_lock_init(&np->lock);
5310         SET_NETDEV_DEV(dev, &pci_dev->dev);
5311
5312         init_timer(&np->oom_kick);
5313         np->oom_kick.data = (unsigned long) dev;
5314         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5315         init_timer(&np->nic_poll);
5316         np->nic_poll.data = (unsigned long) dev;
5317         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5318         init_timer(&np->stats_poll);
5319         np->stats_poll.data = (unsigned long) dev;
5320         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5321
5322         err = pci_enable_device(pci_dev);
5323         if (err)
5324                 goto out_free;
5325
5326         pci_set_master(pci_dev);
5327
5328         err = pci_request_regions(pci_dev, DRV_NAME);
5329         if (err < 0)
5330                 goto out_disable;
5331
5332         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5333                 np->register_size = NV_PCI_REGSZ_VER3;
5334         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5335                 np->register_size = NV_PCI_REGSZ_VER2;
5336         else
5337                 np->register_size = NV_PCI_REGSZ_VER1;
5338
5339         err = -EINVAL;
5340         addr = 0;
5341         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5342                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5343                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5344                                 pci_resource_len(pci_dev, i),
5345                                 pci_resource_flags(pci_dev, i));
5346                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5347                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5348                         addr = pci_resource_start(pci_dev, i);
5349                         break;
5350                 }
5351         }
5352         if (i == DEVICE_COUNT_RESOURCE) {
5353                 dev_printk(KERN_INFO, &pci_dev->dev,
5354                            "Couldn't find register window\n");
5355                 goto out_relreg;
5356         }
5357
5358         /* copy of driver data */
5359         np->driver_data = id->driver_data;
5360         /* copy of device id */
5361         np->device_id = id->device;
5362
5363         /* handle different descriptor versions */
5364         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5365                 /* packet format 3: supports 40-bit addressing */
5366                 np->desc_ver = DESC_VER_3;
5367                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5368                 if (dma_64bit) {
5369                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5370                                 dev_printk(KERN_INFO, &pci_dev->dev,
5371                                         "64-bit DMA failed, using 32-bit addressing\n");
5372                         else
5373                                 dev->features |= NETIF_F_HIGHDMA;
5374                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5375                                 dev_printk(KERN_INFO, &pci_dev->dev,
5376                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5377                         }
5378                 }
5379         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5380                 /* packet format 2: supports jumbo frames */
5381                 np->desc_ver = DESC_VER_2;
5382                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5383         } else {
5384                 /* original packet format */
5385                 np->desc_ver = DESC_VER_1;
5386                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5387         }
5388
5389         np->pkt_limit = NV_PKTLIMIT_1;
5390         if (id->driver_data & DEV_HAS_LARGEDESC)
5391                 np->pkt_limit = NV_PKTLIMIT_2;
5392
5393         if (id->driver_data & DEV_HAS_CHECKSUM) {
5394                 np->rx_csum = 1;
5395                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5396                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5397                 dev->features |= NETIF_F_TSO;
5398         }
5399
5400         np->vlanctl_bits = 0;
5401         if (id->driver_data & DEV_HAS_VLAN) {
5402                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5403                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5404                 dev->vlan_rx_register = nv_vlan_rx_register;
5405         }
5406
5407         np->msi_flags = 0;
5408         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5409                 np->msi_flags |= NV_MSI_CAPABLE;
5410         }
5411         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5412                 np->msi_flags |= NV_MSI_X_CAPABLE;
5413         }
5414
5415         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5416         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5417             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5418             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5419                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5420         }
5421
5422
5423         err = -ENOMEM;
5424         np->base = ioremap(addr, np->register_size);
5425         if (!np->base)
5426                 goto out_relreg;
5427         dev->base_addr = (unsigned long)np->base;
5428
5429         dev->irq = pci_dev->irq;
5430
5431         np->rx_ring_size = RX_RING_DEFAULT;
5432         np->tx_ring_size = TX_RING_DEFAULT;
5433
5434         if (!nv_optimized(np)) {
5435                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5436                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5437                                         &np->ring_addr);
5438                 if (!np->rx_ring.orig)
5439                         goto out_unmap;
5440                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5441         } else {
5442                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5443                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5444                                         &np->ring_addr);
5445                 if (!np->rx_ring.ex)
5446                         goto out_unmap;
5447                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5448         }
5449         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5450         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5451         if (!np->rx_skb || !np->tx_skb)
5452                 goto out_freering;
5453
5454         dev->open = nv_open;
5455         dev->stop = nv_close;
5456
5457         if (!nv_optimized(np))
5458                 dev->hard_start_xmit = nv_start_xmit;
5459         else
5460                 dev->hard_start_xmit = nv_start_xmit_optimized;
5461         dev->get_stats = nv_get_stats;
5462         dev->change_mtu = nv_change_mtu;
5463         dev->set_mac_address = nv_set_mac_address;
5464         dev->set_multicast_list = nv_set_multicast;
5465 #ifdef CONFIG_NET_POLL_CONTROLLER
5466         dev->poll_controller = nv_poll_controller;
5467 #endif
5468 #ifdef CONFIG_FORCEDETH_NAPI
5469         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5470 #endif
5471         SET_ETHTOOL_OPS(dev, &ops);
5472         dev->tx_timeout = nv_tx_timeout;
5473         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5474
5475         pci_set_drvdata(pci_dev, dev);
5476
5477         /* read the mac address */
5478         base = get_hwbase(dev);
5479         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5480         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5481
5482         /* check the workaround bit for correct mac address order */
5483         txreg = readl(base + NvRegTransmitPoll);
5484         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5485                 /* mac address is already in correct order */
5486                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5487                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5488                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5489                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5490                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5491                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5492         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5493                 /* mac address is already in correct order */
5494                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5495                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5496                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5497                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5498                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5499                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5500                 /*
5501                  * Set orig mac address back to the reversed version.
5502                  * This flag will be cleared during low power transition.
5503                  * Therefore, we should always put back the reversed address.
5504                  */
5505                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5506                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5507                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5508         } else {
5509                 /* need to reverse mac address to correct order */
5510                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5511       &n