forcedeth: ck804 and mcp55 doesn't need timerirq
[linux-2.6.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.62"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk                 printk
69 #else
70 #define dprintk(x...)           do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP  64
74 #define RX_WORK_PER_LOOP  64
75
76 /*
77  * Hardware access:
78  */
79
80 #define DEV_NEED_TIMERIRQ          0x000001  /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER         0x000002  /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC          0x000004  /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA           0x000008  /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM           0x000010  /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN               0x000020  /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI                0x000040  /* device supports MSI */
87 #define DEV_HAS_MSI_X              0x000080  /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL        0x000100  /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1      0x000200  /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2      0x000400  /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3      0x000800  /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED      0x001000  /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT          0x002000  /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR    0x004000  /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX      0x008000  /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x010000  /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x020000  /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x040000  /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT          0x080000  /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE          0x100000  /* device supports gear mode */
101
102 enum {
103         NvRegIrqStatus = 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT  0x040
105 #define NVREG_IRQSTAT_MASK              0x81ff
106         NvRegIrqMask = 0x004,
107 #define NVREG_IRQ_RX_ERROR              0x0001
108 #define NVREG_IRQ_RX                    0x0002
109 #define NVREG_IRQ_RX_NOBUF              0x0004
110 #define NVREG_IRQ_TX_ERR                0x0008
111 #define NVREG_IRQ_TX_OK                 0x0010
112 #define NVREG_IRQ_TIMER                 0x0020
113 #define NVREG_IRQ_LINK                  0x0040
114 #define NVREG_IRQ_RX_FORCED             0x0080
115 #define NVREG_IRQ_TX_FORCED             0x0100
116 #define NVREG_IRQ_RECOVER_ERROR         0x8000
117 #define NVREG_IRQMASK_THROUGHPUT        0x00df
118 #define NVREG_IRQMASK_CPU               0x0060
119 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122
123 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
124                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
125                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
126
127         NvRegUnknownSetupReg6 = 0x008,
128 #define NVREG_UNKSETUP6_VAL             3
129
130 /*
131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133  */
134         NvRegPollingInterval = 0x00c,
135 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
136 #define NVREG_POLL_DEFAULT_CPU  13
137         NvRegMSIMap0 = 0x020,
138         NvRegMSIMap1 = 0x024,
139         NvRegMSIIrqMask = 0x030,
140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
141         NvRegMisc1 = 0x080,
142 #define NVREG_MISC1_PAUSE_TX    0x01
143 #define NVREG_MISC1_HD          0x02
144 #define NVREG_MISC1_FORCE       0x3b0f3c
145
146         NvRegMacReset = 0x34,
147 #define NVREG_MAC_RESET_ASSERT  0x0F3
148         NvRegTransmitterControl = 0x084,
149 #define NVREG_XMITCTL_START     0x01
150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
160         NvRegTransmitterStatus = 0x088,
161 #define NVREG_XMITSTAT_BUSY     0x01
162
163         NvRegPacketFilterFlags = 0x8c,
164 #define NVREG_PFF_PAUSE_RX      0x08
165 #define NVREG_PFF_ALWAYS        0x7F0000
166 #define NVREG_PFF_PROMISC       0x80
167 #define NVREG_PFF_MYADDR        0x20
168 #define NVREG_PFF_LOOPBACK      0x10
169
170         NvRegOffloadConfig = 0x90,
171 #define NVREG_OFFLOAD_HOMEPHY   0x601
172 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
173         NvRegReceiverControl = 0x094,
174 #define NVREG_RCVCTL_START      0x01
175 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
176         NvRegReceiverStatus = 0x98,
177 #define NVREG_RCVSTAT_BUSY      0x01
178
179         NvRegSlotTime = 0x9c,
180 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
181 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
182 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
183 #define NVREG_SLOTTIME_HALF             0x0000ff00
184 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
185 #define NVREG_SLOTTIME_MASK             0x000000ff
186
187         NvRegTxDeferral = 0xA0,
188 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
189 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
190 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
192 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
193 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
194         NvRegRxDeferral = 0xA4,
195 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
196         NvRegMacAddrA = 0xA8,
197         NvRegMacAddrB = 0xAC,
198         NvRegMulticastAddrA = 0xB0,
199 #define NVREG_MCASTADDRA_FORCE  0x01
200         NvRegMulticastAddrB = 0xB4,
201         NvRegMulticastMaskA = 0xB8,
202 #define NVREG_MCASTMASKA_NONE           0xffffffff
203         NvRegMulticastMaskB = 0xBC,
204 #define NVREG_MCASTMASKB_NONE           0xffff
205
206         NvRegPhyInterface = 0xC0,
207 #define PHY_RGMII               0x10000000
208         NvRegBackOffControl = 0xC4,
209 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
210 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
211 #define NVREG_BKOFFCTRL_SELECT                  24
212 #define NVREG_BKOFFCTRL_GEAR                    12
213
214         NvRegTxRingPhysAddr = 0x100,
215         NvRegRxRingPhysAddr = 0x104,
216         NvRegRingSizes = 0x108,
217 #define NVREG_RINGSZ_TXSHIFT 0
218 #define NVREG_RINGSZ_RXSHIFT 16
219         NvRegTransmitPoll = 0x10c,
220 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
221         NvRegLinkSpeed = 0x110,
222 #define NVREG_LINKSPEED_FORCE 0x10000
223 #define NVREG_LINKSPEED_10      1000
224 #define NVREG_LINKSPEED_100     100
225 #define NVREG_LINKSPEED_1000    50
226 #define NVREG_LINKSPEED_MASK    (0xFFF)
227         NvRegUnknownSetupReg5 = 0x130,
228 #define NVREG_UNKSETUP5_BIT31   (1<<31)
229         NvRegTxWatermark = 0x13c,
230 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
231 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
232 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
233         NvRegTxRxControl = 0x144,
234 #define NVREG_TXRXCTL_KICK      0x0001
235 #define NVREG_TXRXCTL_BIT1      0x0002
236 #define NVREG_TXRXCTL_BIT2      0x0004
237 #define NVREG_TXRXCTL_IDLE      0x0008
238 #define NVREG_TXRXCTL_RESET     0x0010
239 #define NVREG_TXRXCTL_RXCHECK   0x0400
240 #define NVREG_TXRXCTL_DESC_1    0
241 #define NVREG_TXRXCTL_DESC_2    0x002100
242 #define NVREG_TXRXCTL_DESC_3    0xc02200
243 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
244 #define NVREG_TXRXCTL_VLANINS   0x00080
245         NvRegTxRingPhysAddrHigh = 0x148,
246         NvRegRxRingPhysAddrHigh = 0x14C,
247         NvRegTxPauseFrame = 0x170,
248 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
251 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
252         NvRegTxPauseFrameLimit = 0x174,
253 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
254         NvRegMIIStatus = 0x180,
255 #define NVREG_MIISTAT_ERROR             0x0001
256 #define NVREG_MIISTAT_LINKCHANGE        0x0008
257 #define NVREG_MIISTAT_MASK_RW           0x0007
258 #define NVREG_MIISTAT_MASK_ALL          0x000f
259         NvRegMIIMask = 0x184,
260 #define NVREG_MII_LINKCHANGE            0x0008
261
262         NvRegAdapterControl = 0x188,
263 #define NVREG_ADAPTCTL_START    0x02
264 #define NVREG_ADAPTCTL_LINKUP   0x04
265 #define NVREG_ADAPTCTL_PHYVALID 0x40000
266 #define NVREG_ADAPTCTL_RUNNING  0x100000
267 #define NVREG_ADAPTCTL_PHYSHIFT 24
268         NvRegMIISpeed = 0x18c,
269 #define NVREG_MIISPEED_BIT8     (1<<8)
270 #define NVREG_MIIDELAY  5
271         NvRegMIIControl = 0x190,
272 #define NVREG_MIICTL_INUSE      0x08000
273 #define NVREG_MIICTL_WRITE      0x00400
274 #define NVREG_MIICTL_ADDRSHIFT  5
275         NvRegMIIData = 0x194,
276         NvRegTxUnicast = 0x1a0,
277         NvRegTxMulticast = 0x1a4,
278         NvRegTxBroadcast = 0x1a8,
279         NvRegWakeUpFlags = 0x200,
280 #define NVREG_WAKEUPFLAGS_VAL           0x7770
281 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
282 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
283 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
284 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
285 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
286 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
287 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
288 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
289 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
290 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
291
292         NvRegPatternCRC = 0x204,
293         NvRegPatternMask = 0x208,
294         NvRegPowerCap = 0x268,
295 #define NVREG_POWERCAP_D3SUPP   (1<<30)
296 #define NVREG_POWERCAP_D2SUPP   (1<<26)
297 #define NVREG_POWERCAP_D1SUPP   (1<<25)
298         NvRegPowerState = 0x26c,
299 #define NVREG_POWERSTATE_POWEREDUP      0x8000
300 #define NVREG_POWERSTATE_VALID          0x0100
301 #define NVREG_POWERSTATE_MASK           0x0003
302 #define NVREG_POWERSTATE_D0             0x0000
303 #define NVREG_POWERSTATE_D1             0x0001
304 #define NVREG_POWERSTATE_D2             0x0002
305 #define NVREG_POWERSTATE_D3             0x0003
306         NvRegTxCnt = 0x280,
307         NvRegTxZeroReXmt = 0x284,
308         NvRegTxOneReXmt = 0x288,
309         NvRegTxManyReXmt = 0x28c,
310         NvRegTxLateCol = 0x290,
311         NvRegTxUnderflow = 0x294,
312         NvRegTxLossCarrier = 0x298,
313         NvRegTxExcessDef = 0x29c,
314         NvRegTxRetryErr = 0x2a0,
315         NvRegRxFrameErr = 0x2a4,
316         NvRegRxExtraByte = 0x2a8,
317         NvRegRxLateCol = 0x2ac,
318         NvRegRxRunt = 0x2b0,
319         NvRegRxFrameTooLong = 0x2b4,
320         NvRegRxOverflow = 0x2b8,
321         NvRegRxFCSErr = 0x2bc,
322         NvRegRxFrameAlignErr = 0x2c0,
323         NvRegRxLenErr = 0x2c4,
324         NvRegRxUnicast = 0x2c8,
325         NvRegRxMulticast = 0x2cc,
326         NvRegRxBroadcast = 0x2d0,
327         NvRegTxDef = 0x2d4,
328         NvRegTxFrame = 0x2d8,
329         NvRegRxCnt = 0x2dc,
330         NvRegTxPause = 0x2e0,
331         NvRegRxPause = 0x2e4,
332         NvRegRxDropFrame = 0x2e8,
333         NvRegVlanControl = 0x300,
334 #define NVREG_VLANCONTROL_ENABLE        0x2000
335         NvRegMSIXMap0 = 0x3e0,
336         NvRegMSIXMap1 = 0x3e4,
337         NvRegMSIXIrqStatus = 0x3f0,
338
339         NvRegPowerState2 = 0x600,
340 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
341 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
342 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
343 };
344
345 /* Big endian: should work, but is untested */
346 struct ring_desc {
347         __le32 buf;
348         __le32 flaglen;
349 };
350
351 struct ring_desc_ex {
352         __le32 bufhigh;
353         __le32 buflow;
354         __le32 txvlan;
355         __le32 flaglen;
356 };
357
358 union ring_type {
359         struct ring_desc* orig;
360         struct ring_desc_ex* ex;
361 };
362
363 #define FLAG_MASK_V1 0xffff0000
364 #define FLAG_MASK_V2 0xffffc000
365 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
366 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
367
368 #define NV_TX_LASTPACKET        (1<<16)
369 #define NV_TX_RETRYERROR        (1<<19)
370 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
371 #define NV_TX_FORCED_INTERRUPT  (1<<24)
372 #define NV_TX_DEFERRED          (1<<26)
373 #define NV_TX_CARRIERLOST       (1<<27)
374 #define NV_TX_LATECOLLISION     (1<<28)
375 #define NV_TX_UNDERFLOW         (1<<29)
376 #define NV_TX_ERROR             (1<<30)
377 #define NV_TX_VALID             (1<<31)
378
379 #define NV_TX2_LASTPACKET       (1<<29)
380 #define NV_TX2_RETRYERROR       (1<<18)
381 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
382 #define NV_TX2_FORCED_INTERRUPT (1<<30)
383 #define NV_TX2_DEFERRED         (1<<25)
384 #define NV_TX2_CARRIERLOST      (1<<26)
385 #define NV_TX2_LATECOLLISION    (1<<27)
386 #define NV_TX2_UNDERFLOW        (1<<28)
387 /* error and valid are the same for both */
388 #define NV_TX2_ERROR            (1<<30)
389 #define NV_TX2_VALID            (1<<31)
390 #define NV_TX2_TSO              (1<<28)
391 #define NV_TX2_TSO_SHIFT        14
392 #define NV_TX2_TSO_MAX_SHIFT    14
393 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
394 #define NV_TX2_CHECKSUM_L3      (1<<27)
395 #define NV_TX2_CHECKSUM_L4      (1<<26)
396
397 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
398
399 #define NV_RX_DESCRIPTORVALID   (1<<16)
400 #define NV_RX_MISSEDFRAME       (1<<17)
401 #define NV_RX_SUBSTRACT1        (1<<18)
402 #define NV_RX_ERROR1            (1<<23)
403 #define NV_RX_ERROR2            (1<<24)
404 #define NV_RX_ERROR3            (1<<25)
405 #define NV_RX_ERROR4            (1<<26)
406 #define NV_RX_CRCERR            (1<<27)
407 #define NV_RX_OVERFLOW          (1<<28)
408 #define NV_RX_FRAMINGERR        (1<<29)
409 #define NV_RX_ERROR             (1<<30)
410 #define NV_RX_AVAIL             (1<<31)
411 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
412
413 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
414 #define NV_RX2_CHECKSUM_IP      (0x10000000)
415 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
416 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
417 #define NV_RX2_DESCRIPTORVALID  (1<<29)
418 #define NV_RX2_SUBSTRACT1       (1<<25)
419 #define NV_RX2_ERROR1           (1<<18)
420 #define NV_RX2_ERROR2           (1<<19)
421 #define NV_RX2_ERROR3           (1<<20)
422 #define NV_RX2_ERROR4           (1<<21)
423 #define NV_RX2_CRCERR           (1<<22)
424 #define NV_RX2_OVERFLOW         (1<<23)
425 #define NV_RX2_FRAMINGERR       (1<<24)
426 /* error and avail are the same for both */
427 #define NV_RX2_ERROR            (1<<30)
428 #define NV_RX2_AVAIL            (1<<31)
429 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
430
431 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
432 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
433
434 /* Miscelaneous hardware related defines: */
435 #define NV_PCI_REGSZ_VER1       0x270
436 #define NV_PCI_REGSZ_VER2       0x2d4
437 #define NV_PCI_REGSZ_VER3       0x604
438 #define NV_PCI_REGSZ_MAX        0x604
439
440 /* various timeout delays: all in usec */
441 #define NV_TXRX_RESET_DELAY     4
442 #define NV_TXSTOP_DELAY1        10
443 #define NV_TXSTOP_DELAY1MAX     500000
444 #define NV_TXSTOP_DELAY2        100
445 #define NV_RXSTOP_DELAY1        10
446 #define NV_RXSTOP_DELAY1MAX     500000
447 #define NV_RXSTOP_DELAY2        100
448 #define NV_SETUP5_DELAY         5
449 #define NV_SETUP5_DELAYMAX      50000
450 #define NV_POWERUP_DELAY        5
451 #define NV_POWERUP_DELAYMAX     5000
452 #define NV_MIIBUSY_DELAY        50
453 #define NV_MIIPHY_DELAY 10
454 #define NV_MIIPHY_DELAYMAX      10000
455 #define NV_MAC_RESET_DELAY      64
456
457 #define NV_WAKEUPPATTERNS       5
458 #define NV_WAKEUPMASKENTRIES    4
459
460 /* General driver defaults */
461 #define NV_WATCHDOG_TIMEO       (5*HZ)
462
463 #define RX_RING_DEFAULT         128
464 #define TX_RING_DEFAULT         256
465 #define RX_RING_MIN             128
466 #define TX_RING_MIN             64
467 #define RING_MAX_DESC_VER_1     1024
468 #define RING_MAX_DESC_VER_2_3   16384
469
470 /* rx/tx mac addr + type + vlan + align + slack*/
471 #define NV_RX_HEADERS           (64)
472 /* even more slack. */
473 #define NV_RX_ALLOC_PAD         (64)
474
475 /* maximum mtu size */
476 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
477 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
478
479 #define OOM_REFILL      (1+HZ/20)
480 #define POLL_WAIT       (1+HZ/100)
481 #define LINK_TIMEOUT    (3*HZ)
482 #define STATS_INTERVAL  (10*HZ)
483
484 /*
485  * desc_ver values:
486  * The nic supports three different descriptor types:
487  * - DESC_VER_1: Original
488  * - DESC_VER_2: support for jumbo frames.
489  * - DESC_VER_3: 64-bit format.
490  */
491 #define DESC_VER_1      1
492 #define DESC_VER_2      2
493 #define DESC_VER_3      3
494
495 /* PHY defines */
496 #define PHY_OUI_MARVELL         0x5043
497 #define PHY_OUI_CICADA          0x03f1
498 #define PHY_OUI_VITESSE         0x01c1
499 #define PHY_OUI_REALTEK         0x0732
500 #define PHY_OUI_REALTEK2        0x0020
501 #define PHYID1_OUI_MASK 0x03ff
502 #define PHYID1_OUI_SHFT 6
503 #define PHYID2_OUI_MASK 0xfc00
504 #define PHYID2_OUI_SHFT 10
505 #define PHYID2_MODEL_MASK               0x03f0
506 #define PHY_MODEL_REALTEK_8211          0x0110
507 #define PHY_REV_MASK                    0x0001
508 #define PHY_REV_REALTEK_8211B           0x0000
509 #define PHY_REV_REALTEK_8211C           0x0001
510 #define PHY_MODEL_REALTEK_8201          0x0200
511 #define PHY_MODEL_MARVELL_E3016         0x0220
512 #define PHY_MARVELL_E3016_INITMASK      0x0300
513 #define PHY_CICADA_INIT1        0x0f000
514 #define PHY_CICADA_INIT2        0x0e00
515 #define PHY_CICADA_INIT3        0x01000
516 #define PHY_CICADA_INIT4        0x0200
517 #define PHY_CICADA_INIT5        0x0004
518 #define PHY_CICADA_INIT6        0x02000
519 #define PHY_VITESSE_INIT_REG1   0x1f
520 #define PHY_VITESSE_INIT_REG2   0x10
521 #define PHY_VITESSE_INIT_REG3   0x11
522 #define PHY_VITESSE_INIT_REG4   0x12
523 #define PHY_VITESSE_INIT_MSK1   0xc
524 #define PHY_VITESSE_INIT_MSK2   0x0180
525 #define PHY_VITESSE_INIT1       0x52b5
526 #define PHY_VITESSE_INIT2       0xaf8a
527 #define PHY_VITESSE_INIT3       0x8
528 #define PHY_VITESSE_INIT4       0x8f8a
529 #define PHY_VITESSE_INIT5       0xaf86
530 #define PHY_VITESSE_INIT6       0x8f86
531 #define PHY_VITESSE_INIT7       0xaf82
532 #define PHY_VITESSE_INIT8       0x0100
533 #define PHY_VITESSE_INIT9       0x8f82
534 #define PHY_VITESSE_INIT10      0x0
535 #define PHY_REALTEK_INIT_REG1   0x1f
536 #define PHY_REALTEK_INIT_REG2   0x19
537 #define PHY_REALTEK_INIT_REG3   0x13
538 #define PHY_REALTEK_INIT_REG4   0x14
539 #define PHY_REALTEK_INIT_REG5   0x18
540 #define PHY_REALTEK_INIT_REG6   0x11
541 #define PHY_REALTEK_INIT_REG7   0x01
542 #define PHY_REALTEK_INIT1       0x0000
543 #define PHY_REALTEK_INIT2       0x8e00
544 #define PHY_REALTEK_INIT3       0x0001
545 #define PHY_REALTEK_INIT4       0xad17
546 #define PHY_REALTEK_INIT5       0xfb54
547 #define PHY_REALTEK_INIT6       0xf5c7
548 #define PHY_REALTEK_INIT7       0x1000
549 #define PHY_REALTEK_INIT8       0x0003
550 #define PHY_REALTEK_INIT9       0x0008
551 #define PHY_REALTEK_INIT10      0x0005
552 #define PHY_REALTEK_INIT11      0x0200
553 #define PHY_REALTEK_INIT_MSK1   0x0003
554
555 #define PHY_GIGABIT     0x0100
556
557 #define PHY_TIMEOUT     0x1
558 #define PHY_ERROR       0x2
559
560 #define PHY_100 0x1
561 #define PHY_1000        0x2
562 #define PHY_HALF        0x100
563
564 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
565 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
566 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
567 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
568 #define NV_PAUSEFRAME_RX_REQ     0x0010
569 #define NV_PAUSEFRAME_TX_REQ     0x0020
570 #define NV_PAUSEFRAME_AUTONEG    0x0040
571
572 /* MSI/MSI-X defines */
573 #define NV_MSI_X_MAX_VECTORS  8
574 #define NV_MSI_X_VECTORS_MASK 0x000f
575 #define NV_MSI_CAPABLE        0x0010
576 #define NV_MSI_X_CAPABLE      0x0020
577 #define NV_MSI_ENABLED        0x0040
578 #define NV_MSI_X_ENABLED      0x0080
579
580 #define NV_MSI_X_VECTOR_ALL   0x0
581 #define NV_MSI_X_VECTOR_RX    0x0
582 #define NV_MSI_X_VECTOR_TX    0x1
583 #define NV_MSI_X_VECTOR_OTHER 0x2
584
585 #define NV_RESTART_TX         0x1
586 #define NV_RESTART_RX         0x2
587
588 #define NV_TX_LIMIT_COUNT     16
589
590 /* statistics */
591 struct nv_ethtool_str {
592         char name[ETH_GSTRING_LEN];
593 };
594
595 static const struct nv_ethtool_str nv_estats_str[] = {
596         { "tx_bytes" },
597         { "tx_zero_rexmt" },
598         { "tx_one_rexmt" },
599         { "tx_many_rexmt" },
600         { "tx_late_collision" },
601         { "tx_fifo_errors" },
602         { "tx_carrier_errors" },
603         { "tx_excess_deferral" },
604         { "tx_retry_error" },
605         { "rx_frame_error" },
606         { "rx_extra_byte" },
607         { "rx_late_collision" },
608         { "rx_runt" },
609         { "rx_frame_too_long" },
610         { "rx_over_errors" },
611         { "rx_crc_errors" },
612         { "rx_frame_align_error" },
613         { "rx_length_error" },
614         { "rx_unicast" },
615         { "rx_multicast" },
616         { "rx_broadcast" },
617         { "rx_packets" },
618         { "rx_errors_total" },
619         { "tx_errors_total" },
620
621         /* version 2 stats */
622         { "tx_deferral" },
623         { "tx_packets" },
624         { "rx_bytes" },
625         { "tx_pause" },
626         { "rx_pause" },
627         { "rx_drop_frame" },
628
629         /* version 3 stats */
630         { "tx_unicast" },
631         { "tx_multicast" },
632         { "tx_broadcast" }
633 };
634
635 struct nv_ethtool_stats {
636         u64 tx_bytes;
637         u64 tx_zero_rexmt;
638         u64 tx_one_rexmt;
639         u64 tx_many_rexmt;
640         u64 tx_late_collision;
641         u64 tx_fifo_errors;
642         u64 tx_carrier_errors;
643         u64 tx_excess_deferral;
644         u64 tx_retry_error;
645         u64 rx_frame_error;
646         u64 rx_extra_byte;
647         u64 rx_late_collision;
648         u64 rx_runt;
649         u64 rx_frame_too_long;
650         u64 rx_over_errors;
651         u64 rx_crc_errors;
652         u64 rx_frame_align_error;
653         u64 rx_length_error;
654         u64 rx_unicast;
655         u64 rx_multicast;
656         u64 rx_broadcast;
657         u64 rx_packets;
658         u64 rx_errors_total;
659         u64 tx_errors_total;
660
661         /* version 2 stats */
662         u64 tx_deferral;
663         u64 tx_packets;
664         u64 rx_bytes;
665         u64 tx_pause;
666         u64 rx_pause;
667         u64 rx_drop_frame;
668
669         /* version 3 stats */
670         u64 tx_unicast;
671         u64 tx_multicast;
672         u64 tx_broadcast;
673 };
674
675 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
676 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
677 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
678
679 /* diagnostics */
680 #define NV_TEST_COUNT_BASE 3
681 #define NV_TEST_COUNT_EXTENDED 4
682
683 static const struct nv_ethtool_str nv_etests_str[] = {
684         { "link      (online/offline)" },
685         { "register  (offline)       " },
686         { "interrupt (offline)       " },
687         { "loopback  (offline)       " }
688 };
689
690 struct register_test {
691         __u32 reg;
692         __u32 mask;
693 };
694
695 static const struct register_test nv_registers_test[] = {
696         { NvRegUnknownSetupReg6, 0x01 },
697         { NvRegMisc1, 0x03c },
698         { NvRegOffloadConfig, 0x03ff },
699         { NvRegMulticastAddrA, 0xffffffff },
700         { NvRegTxWatermark, 0x0ff },
701         { NvRegWakeUpFlags, 0x07777 },
702         { 0,0 }
703 };
704
705 struct nv_skb_map {
706         struct sk_buff *skb;
707         dma_addr_t dma;
708         unsigned int dma_len;
709         struct ring_desc_ex *first_tx_desc;
710         struct nv_skb_map *next_tx_ctx;
711 };
712
713 /*
714  * SMP locking:
715  * All hardware access under netdev_priv(dev)->lock, except the performance
716  * critical parts:
717  * - rx is (pseudo-) lockless: it relies on the single-threading provided
718  *      by the arch code for interrupts.
719  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
720  *      needs netdev_priv(dev)->lock :-(
721  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
722  */
723
724 /* in dev: base, irq */
725 struct fe_priv {
726         spinlock_t lock;
727
728         struct net_device *dev;
729         struct napi_struct napi;
730
731         /* General data:
732          * Locking: spin_lock(&np->lock); */
733         struct nv_ethtool_stats estats;
734         int in_shutdown;
735         u32 linkspeed;
736         int duplex;
737         int autoneg;
738         int fixed_mode;
739         int phyaddr;
740         int wolenabled;
741         unsigned int phy_oui;
742         unsigned int phy_model;
743         unsigned int phy_rev;
744         u16 gigabit;
745         int intr_test;
746         int recover_error;
747
748         /* General data: RO fields */
749         dma_addr_t ring_addr;
750         struct pci_dev *pci_dev;
751         u32 orig_mac[2];
752         u32 irqmask;
753         u32 desc_ver;
754         u32 txrxctl_bits;
755         u32 vlanctl_bits;
756         u32 driver_data;
757         u32 device_id;
758         u32 register_size;
759         int rx_csum;
760         u32 mac_in_use;
761
762         void __iomem *base;
763
764         /* rx specific fields.
765          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
766          */
767         union ring_type get_rx, put_rx, first_rx, last_rx;
768         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
769         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
770         struct nv_skb_map *rx_skb;
771
772         union ring_type rx_ring;
773         unsigned int rx_buf_sz;
774         unsigned int pkt_limit;
775         struct timer_list oom_kick;
776         struct timer_list nic_poll;
777         struct timer_list stats_poll;
778         u32 nic_poll_irq;
779         int rx_ring_size;
780
781         /* media detection workaround.
782          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
783          */
784         int need_linktimer;
785         unsigned long link_timeout;
786         /*
787          * tx specific fields.
788          */
789         union ring_type get_tx, put_tx, first_tx, last_tx;
790         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
791         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
792         struct nv_skb_map *tx_skb;
793
794         union ring_type tx_ring;
795         u32 tx_flags;
796         int tx_ring_size;
797         int tx_limit;
798         u32 tx_pkts_in_progress;
799         struct nv_skb_map *tx_change_owner;
800         struct nv_skb_map *tx_end_flip;
801         int tx_stop;
802
803         /* vlan fields */
804         struct vlan_group *vlangrp;
805
806         /* msi/msi-x fields */
807         u32 msi_flags;
808         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
809
810         /* flow control */
811         u32 pause_flags;
812
813         /* power saved state */
814         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
815
816         /* for different msi-x irq type */
817         char name_rx[IFNAMSIZ + 3];       /* -rx    */
818         char name_tx[IFNAMSIZ + 3];       /* -tx    */
819         char name_other[IFNAMSIZ + 6];    /* -other */
820 };
821
822 /*
823  * Maximum number of loops until we assume that a bit in the irq mask
824  * is stuck. Overridable with module param.
825  */
826 static int max_interrupt_work = 15;
827
828 /*
829  * Optimization can be either throuput mode or cpu mode
830  *
831  * Throughput Mode: Every tx and rx packet will generate an interrupt.
832  * CPU Mode: Interrupts are controlled by a timer.
833  */
834 enum {
835         NV_OPTIMIZATION_MODE_THROUGHPUT,
836         NV_OPTIMIZATION_MODE_CPU
837 };
838 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
839
840 /*
841  * Poll interval for timer irq
842  *
843  * This interval determines how frequent an interrupt is generated.
844  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
845  * Min = 0, and Max = 65535
846  */
847 static int poll_interval = -1;
848
849 /*
850  * MSI interrupts
851  */
852 enum {
853         NV_MSI_INT_DISABLED,
854         NV_MSI_INT_ENABLED
855 };
856 static int msi = NV_MSI_INT_ENABLED;
857
858 /*
859  * MSIX interrupts
860  */
861 enum {
862         NV_MSIX_INT_DISABLED,
863         NV_MSIX_INT_ENABLED
864 };
865 static int msix = NV_MSIX_INT_DISABLED;
866
867 /*
868  * DMA 64bit
869  */
870 enum {
871         NV_DMA_64BIT_DISABLED,
872         NV_DMA_64BIT_ENABLED
873 };
874 static int dma_64bit = NV_DMA_64BIT_ENABLED;
875
876 /*
877  * Crossover Detection
878  * Realtek 8201 phy + some OEM boards do not work properly.
879  */
880 enum {
881         NV_CROSSOVER_DETECTION_DISABLED,
882         NV_CROSSOVER_DETECTION_ENABLED
883 };
884 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
885
886 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
887 {
888         return netdev_priv(dev);
889 }
890
891 static inline u8 __iomem *get_hwbase(struct net_device *dev)
892 {
893         return ((struct fe_priv *)netdev_priv(dev))->base;
894 }
895
896 static inline void pci_push(u8 __iomem *base)
897 {
898         /* force out pending posted writes */
899         readl(base);
900 }
901
902 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
903 {
904         return le32_to_cpu(prd->flaglen)
905                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
906 }
907
908 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
909 {
910         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
911 }
912
913 static bool nv_optimized(struct fe_priv *np)
914 {
915         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
916                 return false;
917         return true;
918 }
919
920 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
921                                 int delay, int delaymax, const char *msg)
922 {
923         u8 __iomem *base = get_hwbase(dev);
924
925         pci_push(base);
926         do {
927                 udelay(delay);
928                 delaymax -= delay;
929                 if (delaymax < 0) {
930                         if (msg)
931                                 printk(msg);
932                         return 1;
933                 }
934         } while ((readl(base + offset) & mask) != target);
935         return 0;
936 }
937
938 #define NV_SETUP_RX_RING 0x01
939 #define NV_SETUP_TX_RING 0x02
940
941 static inline u32 dma_low(dma_addr_t addr)
942 {
943         return addr;
944 }
945
946 static inline u32 dma_high(dma_addr_t addr)
947 {
948         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
949 }
950
951 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
952 {
953         struct fe_priv *np = get_nvpriv(dev);
954         u8 __iomem *base = get_hwbase(dev);
955
956         if (!nv_optimized(np)) {
957                 if (rxtx_flags & NV_SETUP_RX_RING) {
958                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
959                 }
960                 if (rxtx_flags & NV_SETUP_TX_RING) {
961                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
962                 }
963         } else {
964                 if (rxtx_flags & NV_SETUP_RX_RING) {
965                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
966                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
967                 }
968                 if (rxtx_flags & NV_SETUP_TX_RING) {
969                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
970                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
971                 }
972         }
973 }
974
975 static void free_rings(struct net_device *dev)
976 {
977         struct fe_priv *np = get_nvpriv(dev);
978
979         if (!nv_optimized(np)) {
980                 if (np->rx_ring.orig)
981                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
982                                             np->rx_ring.orig, np->ring_addr);
983         } else {
984                 if (np->rx_ring.ex)
985                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
986                                             np->rx_ring.ex, np->ring_addr);
987         }
988         if (np->rx_skb)
989                 kfree(np->rx_skb);
990         if (np->tx_skb)
991                 kfree(np->tx_skb);
992 }
993
994 static int using_multi_irqs(struct net_device *dev)
995 {
996         struct fe_priv *np = get_nvpriv(dev);
997
998         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
999             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1000              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1001                 return 0;
1002         else
1003                 return 1;
1004 }
1005
1006 static void nv_enable_irq(struct net_device *dev)
1007 {
1008         struct fe_priv *np = get_nvpriv(dev);
1009
1010         if (!using_multi_irqs(dev)) {
1011                 if (np->msi_flags & NV_MSI_X_ENABLED)
1012                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1013                 else
1014                         enable_irq(np->pci_dev->irq);
1015         } else {
1016                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1017                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1018                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1019         }
1020 }
1021
1022 static void nv_disable_irq(struct net_device *dev)
1023 {
1024         struct fe_priv *np = get_nvpriv(dev);
1025
1026         if (!using_multi_irqs(dev)) {
1027                 if (np->msi_flags & NV_MSI_X_ENABLED)
1028                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1029                 else
1030                         disable_irq(np->pci_dev->irq);
1031         } else {
1032                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1033                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1034                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1035         }
1036 }
1037
1038 /* In MSIX mode, a write to irqmask behaves as XOR */
1039 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1040 {
1041         u8 __iomem *base = get_hwbase(dev);
1042
1043         writel(mask, base + NvRegIrqMask);
1044 }
1045
1046 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1047 {
1048         struct fe_priv *np = get_nvpriv(dev);
1049         u8 __iomem *base = get_hwbase(dev);
1050
1051         if (np->msi_flags & NV_MSI_X_ENABLED) {
1052                 writel(mask, base + NvRegIrqMask);
1053         } else {
1054                 if (np->msi_flags & NV_MSI_ENABLED)
1055                         writel(0, base + NvRegMSIIrqMask);
1056                 writel(0, base + NvRegIrqMask);
1057         }
1058 }
1059
1060 #define MII_READ        (-1)
1061 /* mii_rw: read/write a register on the PHY.
1062  *
1063  * Caller must guarantee serialization
1064  */
1065 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1066 {
1067         u8 __iomem *base = get_hwbase(dev);
1068         u32 reg;
1069         int retval;
1070
1071         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1072
1073         reg = readl(base + NvRegMIIControl);
1074         if (reg & NVREG_MIICTL_INUSE) {
1075                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1076                 udelay(NV_MIIBUSY_DELAY);
1077         }
1078
1079         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1080         if (value != MII_READ) {
1081                 writel(value, base + NvRegMIIData);
1082                 reg |= NVREG_MIICTL_WRITE;
1083         }
1084         writel(reg, base + NvRegMIIControl);
1085
1086         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1087                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1088                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1089                                 dev->name, miireg, addr);
1090                 retval = -1;
1091         } else if (value != MII_READ) {
1092                 /* it was a write operation - fewer failures are detectable */
1093                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1094                                 dev->name, value, miireg, addr);
1095                 retval = 0;
1096         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1097                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1098                                 dev->name, miireg, addr);
1099                 retval = -1;
1100         } else {
1101                 retval = readl(base + NvRegMIIData);
1102                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1103                                 dev->name, miireg, addr, retval);
1104         }
1105
1106         return retval;
1107 }
1108
1109 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1110 {
1111         struct fe_priv *np = netdev_priv(dev);
1112         u32 miicontrol;
1113         unsigned int tries = 0;
1114
1115         miicontrol = BMCR_RESET | bmcr_setup;
1116         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1117                 return -1;
1118         }
1119
1120         /* wait for 500ms */
1121         msleep(500);
1122
1123         /* must wait till reset is deasserted */
1124         while (miicontrol & BMCR_RESET) {
1125                 msleep(10);
1126                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1127                 /* FIXME: 100 tries seem excessive */
1128                 if (tries++ > 100)
1129                         return -1;
1130         }
1131         return 0;
1132 }
1133
1134 static int phy_init(struct net_device *dev)
1135 {
1136         struct fe_priv *np = get_nvpriv(dev);
1137         u8 __iomem *base = get_hwbase(dev);
1138         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1139
1140         /* phy errata for E3016 phy */
1141         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1142                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1143                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1144                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1145                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1146                         return PHY_ERROR;
1147                 }
1148         }
1149         if (np->phy_oui == PHY_OUI_REALTEK) {
1150                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1151                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1152                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1153                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1154                                 return PHY_ERROR;
1155                         }
1156                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1157                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1158                                 return PHY_ERROR;
1159                         }
1160                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1161                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1162                                 return PHY_ERROR;
1163                         }
1164                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1165                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1166                                 return PHY_ERROR;
1167                         }
1168                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1169                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1170                                 return PHY_ERROR;
1171                         }
1172                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1173                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1174                                 return PHY_ERROR;
1175                         }
1176                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1177                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1178                                 return PHY_ERROR;
1179                         }
1180                 }
1181                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1182                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1183                         u32 powerstate = readl(base + NvRegPowerState2);
1184
1185                         /* need to perform hw phy reset */
1186                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1187                         writel(powerstate, base + NvRegPowerState2);
1188                         msleep(25);
1189
1190                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1191                         writel(powerstate, base + NvRegPowerState2);
1192                         msleep(25);
1193
1194                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1195                         reg |= PHY_REALTEK_INIT9;
1196                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1197                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1198                                 return PHY_ERROR;
1199                         }
1200                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1201                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1202                                 return PHY_ERROR;
1203                         }
1204                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1205                         if (!(reg & PHY_REALTEK_INIT11)) {
1206                                 reg |= PHY_REALTEK_INIT11;
1207                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1208                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209                                         return PHY_ERROR;
1210                                 }
1211                         }
1212                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1213                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1214                                 return PHY_ERROR;
1215                         }
1216                 }
1217                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1218                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1219                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1220                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1221                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1222                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1223                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1224                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1225                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1226                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1227                                 phy_reserved |= PHY_REALTEK_INIT7;
1228                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1229                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230                                         return PHY_ERROR;
1231                                 }
1232                         }
1233                 }
1234         }
1235
1236         /* set advertise register */
1237         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1238         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1239         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1240                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1241                 return PHY_ERROR;
1242         }
1243
1244         /* get phy interface type */
1245         phyinterface = readl(base + NvRegPhyInterface);
1246
1247         /* see if gigabit phy */
1248         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1249         if (mii_status & PHY_GIGABIT) {
1250                 np->gigabit = PHY_GIGABIT;
1251                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1252                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1253                 if (phyinterface & PHY_RGMII)
1254                         mii_control_1000 |= ADVERTISE_1000FULL;
1255                 else
1256                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1257
1258                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1259                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1260                         return PHY_ERROR;
1261                 }
1262         }
1263         else
1264                 np->gigabit = 0;
1265
1266         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1267         mii_control |= BMCR_ANENABLE;
1268
1269         if (np->phy_oui == PHY_OUI_REALTEK &&
1270             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1271             np->phy_rev == PHY_REV_REALTEK_8211C) {
1272                 /* start autoneg since we already performed hw reset above */
1273                 mii_control |= BMCR_ANRESTART;
1274                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1275                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1276                         return PHY_ERROR;
1277                 }
1278         } else {
1279                 /* reset the phy
1280                  * (certain phys need bmcr to be setup with reset)
1281                  */
1282                 if (phy_reset(dev, mii_control)) {
1283                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1284                         return PHY_ERROR;
1285                 }
1286         }
1287
1288         /* phy vendor specific configuration */
1289         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1290                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1291                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1292                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1293                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1294                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1295                         return PHY_ERROR;
1296                 }
1297                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1298                 phy_reserved |= PHY_CICADA_INIT5;
1299                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1300                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1301                         return PHY_ERROR;
1302                 }
1303         }
1304         if (np->phy_oui == PHY_OUI_CICADA) {
1305                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1306                 phy_reserved |= PHY_CICADA_INIT6;
1307                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1308                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1309                         return PHY_ERROR;
1310                 }
1311         }
1312         if (np->phy_oui == PHY_OUI_VITESSE) {
1313                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1314                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1315                         return PHY_ERROR;
1316                 }
1317                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1318                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1319                         return PHY_ERROR;
1320                 }
1321                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1322                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1323                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324                         return PHY_ERROR;
1325                 }
1326                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1327                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1328                 phy_reserved |= PHY_VITESSE_INIT3;
1329                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1330                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1331                         return PHY_ERROR;
1332                 }
1333                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1334                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1335                         return PHY_ERROR;
1336                 }
1337                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1338                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1339                         return PHY_ERROR;
1340                 }
1341                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1342                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1343                 phy_reserved |= PHY_VITESSE_INIT3;
1344                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1345                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1346                         return PHY_ERROR;
1347                 }
1348                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1349                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1350                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1351                         return PHY_ERROR;
1352                 }
1353                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1354                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1355                         return PHY_ERROR;
1356                 }
1357                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1358                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1359                         return PHY_ERROR;
1360                 }
1361                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1362                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1363                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1364                         return PHY_ERROR;
1365                 }
1366                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1367                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1368                 phy_reserved |= PHY_VITESSE_INIT8;
1369                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1370                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1371                         return PHY_ERROR;
1372                 }
1373                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1374                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1375                         return PHY_ERROR;
1376                 }
1377                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1378                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1379                         return PHY_ERROR;
1380                 }
1381         }
1382         if (np->phy_oui == PHY_OUI_REALTEK) {
1383                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1384                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1385                         /* reset could have cleared these out, set them back */
1386                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1387                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1388                                 return PHY_ERROR;
1389                         }
1390                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1391                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1392                                 return PHY_ERROR;
1393                         }
1394                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1395                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1396                                 return PHY_ERROR;
1397                         }
1398                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1399                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1400                                 return PHY_ERROR;
1401                         }
1402                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1403                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1404                                 return PHY_ERROR;
1405                         }
1406                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1407                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1408                                 return PHY_ERROR;
1409                         }
1410                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1411                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1412                                 return PHY_ERROR;
1413                         }
1414                 }
1415                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1416                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1417                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1418                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1419                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1420                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1421                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1422                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1423                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1424                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1425                                 phy_reserved |= PHY_REALTEK_INIT7;
1426                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1427                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1428                                         return PHY_ERROR;
1429                                 }
1430                         }
1431                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1432                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1433                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1434                                         return PHY_ERROR;
1435                                 }
1436                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1437                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1438                                 phy_reserved |= PHY_REALTEK_INIT3;
1439                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1440                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1441                                         return PHY_ERROR;
1442                                 }
1443                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1444                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1445                                         return PHY_ERROR;
1446                                 }
1447                         }
1448                 }
1449         }
1450
1451         /* some phys clear out pause advertisment on reset, set it back */
1452         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1453
1454         /* restart auto negotiation, power down phy */
1455         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1456         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1457         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1458                 return PHY_ERROR;
1459         }
1460
1461         return 0;
1462 }
1463
1464 static void nv_start_rx(struct net_device *dev)
1465 {
1466         struct fe_priv *np = netdev_priv(dev);
1467         u8 __iomem *base = get_hwbase(dev);
1468         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1469
1470         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1471         /* Already running? Stop it. */
1472         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1473                 rx_ctrl &= ~NVREG_RCVCTL_START;
1474                 writel(rx_ctrl, base + NvRegReceiverControl);
1475                 pci_push(base);
1476         }
1477         writel(np->linkspeed, base + NvRegLinkSpeed);
1478         pci_push(base);
1479         rx_ctrl |= NVREG_RCVCTL_START;
1480         if (np->mac_in_use)
1481                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1482         writel(rx_ctrl, base + NvRegReceiverControl);
1483         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1484                                 dev->name, np->duplex, np->linkspeed);
1485         pci_push(base);
1486 }
1487
1488 static void nv_stop_rx(struct net_device *dev)
1489 {
1490         struct fe_priv *np = netdev_priv(dev);
1491         u8 __iomem *base = get_hwbase(dev);
1492         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1493
1494         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1495         if (!np->mac_in_use)
1496                 rx_ctrl &= ~NVREG_RCVCTL_START;
1497         else
1498                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1499         writel(rx_ctrl, base + NvRegReceiverControl);
1500         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1501                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1502                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1503
1504         udelay(NV_RXSTOP_DELAY2);
1505         if (!np->mac_in_use)
1506                 writel(0, base + NvRegLinkSpeed);
1507 }
1508
1509 static void nv_start_tx(struct net_device *dev)
1510 {
1511         struct fe_priv *np = netdev_priv(dev);
1512         u8 __iomem *base = get_hwbase(dev);
1513         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1514
1515         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1516         tx_ctrl |= NVREG_XMITCTL_START;
1517         if (np->mac_in_use)
1518                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1519         writel(tx_ctrl, base + NvRegTransmitterControl);
1520         pci_push(base);
1521 }
1522
1523 static void nv_stop_tx(struct net_device *dev)
1524 {
1525         struct fe_priv *np = netdev_priv(dev);
1526         u8 __iomem *base = get_hwbase(dev);
1527         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1528
1529         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1530         if (!np->mac_in_use)
1531                 tx_ctrl &= ~NVREG_XMITCTL_START;
1532         else
1533                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1534         writel(tx_ctrl, base + NvRegTransmitterControl);
1535         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1536                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1537                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1538
1539         udelay(NV_TXSTOP_DELAY2);
1540         if (!np->mac_in_use)
1541                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1542                        base + NvRegTransmitPoll);
1543 }
1544
1545 static void nv_start_rxtx(struct net_device *dev)
1546 {
1547         nv_start_rx(dev);
1548         nv_start_tx(dev);
1549 }
1550
1551 static void nv_stop_rxtx(struct net_device *dev)
1552 {
1553         nv_stop_rx(dev);
1554         nv_stop_tx(dev);
1555 }
1556
1557 static void nv_txrx_reset(struct net_device *dev)
1558 {
1559         struct fe_priv *np = netdev_priv(dev);
1560         u8 __iomem *base = get_hwbase(dev);
1561
1562         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1563         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1564         pci_push(base);
1565         udelay(NV_TXRX_RESET_DELAY);
1566         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1567         pci_push(base);
1568 }
1569
1570 static void nv_mac_reset(struct net_device *dev)
1571 {
1572         struct fe_priv *np = netdev_priv(dev);
1573         u8 __iomem *base = get_hwbase(dev);
1574         u32 temp1, temp2, temp3;
1575
1576         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1577
1578         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1579         pci_push(base);
1580
1581         /* save registers since they will be cleared on reset */
1582         temp1 = readl(base + NvRegMacAddrA);
1583         temp2 = readl(base + NvRegMacAddrB);
1584         temp3 = readl(base + NvRegTransmitPoll);
1585
1586         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1587         pci_push(base);
1588         udelay(NV_MAC_RESET_DELAY);
1589         writel(0, base + NvRegMacReset);
1590         pci_push(base);
1591         udelay(NV_MAC_RESET_DELAY);
1592
1593         /* restore saved registers */
1594         writel(temp1, base + NvRegMacAddrA);
1595         writel(temp2, base + NvRegMacAddrB);
1596         writel(temp3, base + NvRegTransmitPoll);
1597
1598         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1599         pci_push(base);
1600 }
1601
1602 static void nv_get_hw_stats(struct net_device *dev)
1603 {
1604         struct fe_priv *np = netdev_priv(dev);
1605         u8 __iomem *base = get_hwbase(dev);
1606
1607         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1608         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1609         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1610         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1611         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1612         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1613         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1614         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1615         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1616         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1617         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1618         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1619         np->estats.rx_runt += readl(base + NvRegRxRunt);
1620         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1621         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1622         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1623         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1624         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1625         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1626         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1627         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1628         np->estats.rx_packets =
1629                 np->estats.rx_unicast +
1630                 np->estats.rx_multicast +
1631                 np->estats.rx_broadcast;
1632         np->estats.rx_errors_total =
1633                 np->estats.rx_crc_errors +
1634                 np->estats.rx_over_errors +
1635                 np->estats.rx_frame_error +
1636                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1637                 np->estats.rx_late_collision +
1638                 np->estats.rx_runt +
1639                 np->estats.rx_frame_too_long;
1640         np->estats.tx_errors_total =
1641                 np->estats.tx_late_collision +
1642                 np->estats.tx_fifo_errors +
1643                 np->estats.tx_carrier_errors +
1644                 np->estats.tx_excess_deferral +
1645                 np->estats.tx_retry_error;
1646
1647         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1648                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1649                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1650                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1651                 np->estats.tx_pause += readl(base + NvRegTxPause);
1652                 np->estats.rx_pause += readl(base + NvRegRxPause);
1653                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1654         }
1655
1656         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1657                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1658                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1659                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1660         }
1661 }
1662
1663 /*
1664  * nv_get_stats: dev->get_stats function
1665  * Get latest stats value from the nic.
1666  * Called with read_lock(&dev_base_lock) held for read -
1667  * only synchronized against unregister_netdevice.
1668  */
1669 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1670 {
1671         struct fe_priv *np = netdev_priv(dev);
1672
1673         /* If the nic supports hw counters then retrieve latest values */
1674         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1675                 nv_get_hw_stats(dev);
1676
1677                 /* copy to net_device stats */
1678                 dev->stats.tx_bytes = np->estats.tx_bytes;
1679                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1680                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1681                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1682                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1683                 dev->stats.rx_errors = np->estats.rx_errors_total;
1684                 dev->stats.tx_errors = np->estats.tx_errors_total;
1685         }
1686
1687         return &dev->stats;
1688 }
1689
1690 /*
1691  * nv_alloc_rx: fill rx ring entries.
1692  * Return 1 if the allocations for the skbs failed and the
1693  * rx engine is without Available descriptors
1694  */
1695 static int nv_alloc_rx(struct net_device *dev)
1696 {
1697         struct fe_priv *np = netdev_priv(dev);
1698         struct ring_desc* less_rx;
1699
1700         less_rx = np->get_rx.orig;
1701         if (less_rx-- == np->first_rx.orig)
1702                 less_rx = np->last_rx.orig;
1703
1704         while (np->put_rx.orig != less_rx) {
1705                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1706                 if (skb) {
1707                         np->put_rx_ctx->skb = skb;
1708                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1709                                                              skb->data,
1710                                                              skb_tailroom(skb),
1711                                                              PCI_DMA_FROMDEVICE);
1712                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1713                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1714                         wmb();
1715                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1716                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1717                                 np->put_rx.orig = np->first_rx.orig;
1718                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1719                                 np->put_rx_ctx = np->first_rx_ctx;
1720                 } else {
1721                         return 1;
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 static int nv_alloc_rx_optimized(struct net_device *dev)
1728 {
1729         struct fe_priv *np = netdev_priv(dev);
1730         struct ring_desc_ex* less_rx;
1731
1732         less_rx = np->get_rx.ex;
1733         if (less_rx-- == np->first_rx.ex)
1734                 less_rx = np->last_rx.ex;
1735
1736         while (np->put_rx.ex != less_rx) {
1737                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1738                 if (skb) {
1739                         np->put_rx_ctx->skb = skb;
1740                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1741                                                              skb->data,
1742                                                              skb_tailroom(skb),
1743                                                              PCI_DMA_FROMDEVICE);
1744                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1745                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1746                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1747                         wmb();
1748                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1749                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1750                                 np->put_rx.ex = np->first_rx.ex;
1751                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1752                                 np->put_rx_ctx = np->first_rx_ctx;
1753                 } else {
1754                         return 1;
1755                 }
1756         }
1757         return 0;
1758 }
1759
1760 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1761 #ifdef CONFIG_FORCEDETH_NAPI
1762 static void nv_do_rx_refill(unsigned long data)
1763 {
1764         struct net_device *dev = (struct net_device *) data;
1765         struct fe_priv *np = netdev_priv(dev);
1766
1767         /* Just reschedule NAPI rx processing */
1768         napi_schedule(&np->napi);
1769 }
1770 #else
1771 static void nv_do_rx_refill(unsigned long data)
1772 {
1773         struct net_device *dev = (struct net_device *) data;
1774         struct fe_priv *np = netdev_priv(dev);
1775         int retcode;
1776
1777         if (!using_multi_irqs(dev)) {
1778                 if (np->msi_flags & NV_MSI_X_ENABLED)
1779                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1780                 else
1781                         disable_irq(np->pci_dev->irq);
1782         } else {
1783                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1784         }
1785         if (!nv_optimized(np))
1786                 retcode = nv_alloc_rx(dev);
1787         else
1788                 retcode = nv_alloc_rx_optimized(dev);
1789         if (retcode) {
1790                 spin_lock_irq(&np->lock);
1791                 if (!np->in_shutdown)
1792                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1793                 spin_unlock_irq(&np->lock);
1794         }
1795         if (!using_multi_irqs(dev)) {
1796                 if (np->msi_flags & NV_MSI_X_ENABLED)
1797                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1798                 else
1799                         enable_irq(np->pci_dev->irq);
1800         } else {
1801                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1802         }
1803 }
1804 #endif
1805
1806 static void nv_init_rx(struct net_device *dev)
1807 {
1808         struct fe_priv *np = netdev_priv(dev);
1809         int i;
1810
1811         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1812
1813         if (!nv_optimized(np))
1814                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1815         else
1816                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1817         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1818         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1819
1820         for (i = 0; i < np->rx_ring_size; i++) {
1821                 if (!nv_optimized(np)) {
1822                         np->rx_ring.orig[i].flaglen = 0;
1823                         np->rx_ring.orig[i].buf = 0;
1824                 } else {
1825                         np->rx_ring.ex[i].flaglen = 0;
1826                         np->rx_ring.ex[i].txvlan = 0;
1827                         np->rx_ring.ex[i].bufhigh = 0;
1828                         np->rx_ring.ex[i].buflow = 0;
1829                 }
1830                 np->rx_skb[i].skb = NULL;
1831                 np->rx_skb[i].dma = 0;
1832         }
1833 }
1834
1835 static void nv_init_tx(struct net_device *dev)
1836 {
1837         struct fe_priv *np = netdev_priv(dev);
1838         int i;
1839
1840         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1841
1842         if (!nv_optimized(np))
1843                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1844         else
1845                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1846         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1847         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1848         np->tx_pkts_in_progress = 0;
1849         np->tx_change_owner = NULL;
1850         np->tx_end_flip = NULL;
1851
1852         for (i = 0; i < np->tx_ring_size; i++) {
1853                 if (!nv_optimized(np)) {
1854                         np->tx_ring.orig[i].flaglen = 0;
1855                         np->tx_ring.orig[i].buf = 0;
1856                 } else {
1857                         np->tx_ring.ex[i].flaglen = 0;
1858                         np->tx_ring.ex[i].txvlan = 0;
1859                         np->tx_ring.ex[i].bufhigh = 0;
1860                         np->tx_ring.ex[i].buflow = 0;
1861                 }
1862                 np->tx_skb[i].skb = NULL;
1863                 np->tx_skb[i].dma = 0;
1864                 np->tx_skb[i].dma_len = 0;
1865                 np->tx_skb[i].first_tx_desc = NULL;
1866                 np->tx_skb[i].next_tx_ctx = NULL;
1867         }
1868 }
1869
1870 static int nv_init_ring(struct net_device *dev)
1871 {
1872         struct fe_priv *np = netdev_priv(dev);
1873
1874         nv_init_tx(dev);
1875         nv_init_rx(dev);
1876
1877         if (!nv_optimized(np))
1878                 return nv_alloc_rx(dev);
1879         else
1880                 return nv_alloc_rx_optimized(dev);
1881 }
1882
1883 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1884 {
1885         struct fe_priv *np = netdev_priv(dev);
1886
1887         if (tx_skb->dma) {
1888                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1889                                tx_skb->dma_len,
1890                                PCI_DMA_TODEVICE);
1891                 tx_skb->dma = 0;
1892         }
1893         if (tx_skb->skb) {
1894                 dev_kfree_skb_any(tx_skb->skb);
1895                 tx_skb->skb = NULL;
1896                 return 1;
1897         } else {
1898                 return 0;
1899         }
1900 }
1901
1902 static void nv_drain_tx(struct net_device *dev)
1903 {
1904         struct fe_priv *np = netdev_priv(dev);
1905         unsigned int i;
1906
1907         for (i = 0; i < np->tx_ring_size; i++) {
1908                 if (!nv_optimized(np)) {
1909                         np->tx_ring.orig[i].flaglen = 0;
1910                         np->tx_ring.orig[i].buf = 0;
1911                 } else {
1912                         np->tx_ring.ex[i].flaglen = 0;
1913                         np->tx_ring.ex[i].txvlan = 0;
1914                         np->tx_ring.ex[i].bufhigh = 0;
1915                         np->tx_ring.ex[i].buflow = 0;
1916                 }
1917                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1918                         dev->stats.tx_dropped++;
1919                 np->tx_skb[i].dma = 0;
1920                 np->tx_skb[i].dma_len = 0;
1921                 np->tx_skb[i].first_tx_desc = NULL;
1922                 np->tx_skb[i].next_tx_ctx = NULL;
1923         }
1924         np->tx_pkts_in_progress = 0;
1925         np->tx_change_owner = NULL;
1926         np->tx_end_flip = NULL;
1927 }
1928
1929 static void nv_drain_rx(struct net_device *dev)
1930 {
1931         struct fe_priv *np = netdev_priv(dev);
1932         int i;
1933
1934         for (i = 0; i < np->rx_ring_size; i++) {
1935                 if (!nv_optimized(np)) {
1936                         np->rx_ring.orig[i].flaglen = 0;
1937                         np->rx_ring.orig[i].buf = 0;
1938                 } else {
1939                         np->rx_ring.ex[i].flaglen = 0;
1940                         np->rx_ring.ex[i].txvlan = 0;
1941                         np->rx_ring.ex[i].bufhigh = 0;
1942                         np->rx_ring.ex[i].buflow = 0;
1943                 }
1944                 wmb();
1945                 if (np->rx_skb[i].skb) {
1946                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1947                                          (skb_end_pointer(np->rx_skb[i].skb) -
1948                                           np->rx_skb[i].skb->data),
1949                                          PCI_DMA_FROMDEVICE);
1950                         dev_kfree_skb(np->rx_skb[i].skb);
1951                         np->rx_skb[i].skb = NULL;
1952                 }
1953         }
1954 }
1955
1956 static void nv_drain_rxtx(struct net_device *dev)
1957 {
1958         nv_drain_tx(dev);
1959         nv_drain_rx(dev);
1960 }
1961
1962 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1963 {
1964         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1965 }
1966
1967 static void nv_legacybackoff_reseed(struct net_device *dev)
1968 {
1969         u8 __iomem *base = get_hwbase(dev);
1970         u32 reg;
1971         u32 low;
1972         int tx_status = 0;
1973
1974         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1975         get_random_bytes(&low, sizeof(low));
1976         reg |= low & NVREG_SLOTTIME_MASK;
1977
1978         /* Need to stop tx before change takes effect.
1979          * Caller has already gained np->lock.
1980          */
1981         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1982         if (tx_status)
1983                 nv_stop_tx(dev);
1984         nv_stop_rx(dev);
1985         writel(reg, base + NvRegSlotTime);
1986         if (tx_status)
1987                 nv_start_tx(dev);
1988         nv_start_rx(dev);
1989 }
1990
1991 /* Gear Backoff Seeds */
1992 #define BACKOFF_SEEDSET_ROWS    8
1993 #define BACKOFF_SEEDSET_LFSRS   15
1994
1995 /* Known Good seed sets */
1996 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1997     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1998     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1999     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2000     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2001     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2002     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2003     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2004     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2005
2006 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2007     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2008     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2009     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2010     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2011     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2012     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2013     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2014     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2015
2016 static void nv_gear_backoff_reseed(struct net_device *dev)
2017 {
2018         u8 __iomem *base = get_hwbase(dev);
2019         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2020         u32 temp, seedset, combinedSeed;
2021         int i;
2022
2023         /* Setup seed for free running LFSR */
2024         /* We are going to read the time stamp counter 3 times
2025            and swizzle bits around to increase randomness */
2026         get_random_bytes(&miniseed1, sizeof(miniseed1));
2027         miniseed1 &= 0x0fff;
2028         if (miniseed1 == 0)
2029                 miniseed1 = 0xabc;
2030
2031         get_random_bytes(&miniseed2, sizeof(miniseed2));
2032         miniseed2 &= 0x0fff;
2033         if (miniseed2 == 0)
2034                 miniseed2 = 0xabc;
2035         miniseed2_reversed =
2036                 ((miniseed2 & 0xF00) >> 8) |
2037                  (miniseed2 & 0x0F0) |
2038                  ((miniseed2 & 0x00F) << 8);
2039
2040         get_random_bytes(&miniseed3, sizeof(miniseed3));
2041         miniseed3 &= 0x0fff;
2042         if (miniseed3 == 0)
2043                 miniseed3 = 0xabc;
2044         miniseed3_reversed =
2045                 ((miniseed3 & 0xF00) >> 8) |
2046                  (miniseed3 & 0x0F0) |
2047                  ((miniseed3 & 0x00F) << 8);
2048
2049         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2050                        (miniseed2 ^ miniseed3_reversed);
2051
2052         /* Seeds can not be zero */
2053         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2054                 combinedSeed |= 0x08;
2055         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2056                 combinedSeed |= 0x8000;
2057
2058         /* No need to disable tx here */
2059         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2060         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2061         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2062         writel(temp,base + NvRegBackOffControl);
2063
2064         /* Setup seeds for all gear LFSRs. */
2065         get_random_bytes(&seedset, sizeof(seedset));
2066         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2067         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2068         {
2069                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2070                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2071                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2072                 writel(temp, base + NvRegBackOffControl);
2073         }
2074 }
2075
2076 /*
2077  * nv_start_xmit: dev->hard_start_xmit function
2078  * Called with netif_tx_lock held.
2079  */
2080 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2081 {
2082         struct fe_priv *np = netdev_priv(dev);
2083         u32 tx_flags = 0;
2084         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2085         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2086         unsigned int i;
2087         u32 offset = 0;
2088         u32 bcnt;
2089         u32 size = skb->len-skb->data_len;
2090         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2091         u32 empty_slots;
2092         struct ring_desc* put_tx;
2093         struct ring_desc* start_tx;
2094         struct ring_desc* prev_tx;
2095         struct nv_skb_map* prev_tx_ctx;
2096         unsigned long flags;
2097
2098         /* add fragments to entries count */
2099         for (i = 0; i < fragments; i++) {
2100                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2101                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2102         }
2103
2104         spin_lock_irqsave(&np->lock, flags);
2105         empty_slots = nv_get_empty_tx_slots(np);
2106         if (unlikely(empty_slots <= entries)) {
2107                 netif_stop_queue(dev);
2108                 np->tx_stop = 1;
2109                 spin_unlock_irqrestore(&np->lock, flags);
2110                 return NETDEV_TX_BUSY;
2111         }
2112         spin_unlock_irqrestore(&np->lock, flags);
2113
2114         start_tx = put_tx = np->put_tx.orig;
2115
2116         /* setup the header buffer */
2117         do {
2118                 prev_tx = put_tx;
2119                 prev_tx_ctx = np->put_tx_ctx;
2120                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2121                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2122                                                 PCI_DMA_TODEVICE);
2123                 np->put_tx_ctx->dma_len = bcnt;
2124                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2125                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2126
2127                 tx_flags = np->tx_flags;
2128                 offset += bcnt;
2129                 size -= bcnt;
2130                 if (unlikely(put_tx++ == np->last_tx.orig))
2131                         put_tx = np->first_tx.orig;
2132                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2133                         np->put_tx_ctx = np->first_tx_ctx;
2134         } while (size);
2135
2136         /* setup the fragments */
2137         for (i = 0; i < fragments; i++) {
2138                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2139                 u32 size = frag->size;
2140                 offset = 0;
2141
2142                 do {
2143                         prev_tx = put_tx;
2144                         prev_tx_ctx = np->put_tx_ctx;
2145                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2146                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2147                                                            PCI_DMA_TODEVICE);
2148                         np->put_tx_ctx->dma_len = bcnt;
2149                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2150                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2151
2152                         offset += bcnt;
2153                         size -= bcnt;
2154                         if (unlikely(put_tx++ == np->last_tx.orig))
2155                                 put_tx = np->first_tx.orig;
2156                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2157                                 np->put_tx_ctx = np->first_tx_ctx;
2158                 } while (size);
2159         }
2160
2161         /* set last fragment flag  */
2162         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2163
2164         /* save skb in this slot's context area */
2165         prev_tx_ctx->skb = skb;
2166
2167         if (skb_is_gso(skb))
2168                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2169         else
2170                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2171                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2172
2173         spin_lock_irqsave(&np->lock, flags);
2174
2175         /* set tx flags */
2176         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2177         np->put_tx.orig = put_tx;
2178
2179         spin_unlock_irqrestore(&np->lock, flags);
2180
2181         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2182                 dev->name, entries, tx_flags_extra);
2183         {
2184                 int j;
2185                 for (j=0; j<64; j++) {
2186                         if ((j%16) == 0)
2187                                 dprintk("\n%03x:", j);
2188                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2189                 }
2190                 dprintk("\n");
2191         }
2192
2193         dev->trans_start = jiffies;
2194         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2195         return NETDEV_TX_OK;
2196 }
2197
2198 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2199 {
2200         struct fe_priv *np = netdev_priv(dev);
2201         u32 tx_flags = 0;
2202         u32 tx_flags_extra;
2203         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2204         unsigned int i;
2205         u32 offset = 0;
2206         u32 bcnt;
2207         u32 size = skb->len-skb->data_len;
2208         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2209         u32 empty_slots;
2210         struct ring_desc_ex* put_tx;
2211         struct ring_desc_ex* start_tx;
2212         struct ring_desc_ex* prev_tx;
2213         struct nv_skb_map* prev_tx_ctx;
2214         struct nv_skb_map* start_tx_ctx;
2215         unsigned long flags;
2216
2217         /* add fragments to entries count */
2218         for (i = 0; i < fragments; i++) {
2219                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2220                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2221         }
2222
2223         spin_lock_irqsave(&np->lock, flags);
2224         empty_slots = nv_get_empty_tx_slots(np);
2225         if (unlikely(empty_slots <= entries)) {
2226                 netif_stop_queue(dev);
2227                 np->tx_stop = 1;
2228                 spin_unlock_irqrestore(&np->lock, flags);
2229                 return NETDEV_TX_BUSY;
2230         }
2231         spin_unlock_irqrestore(&np->lock, flags);
2232
2233         start_tx = put_tx = np->put_tx.ex;
2234         start_tx_ctx = np->put_tx_ctx;
2235
2236         /* setup the header buffer */
2237         do {
2238                 prev_tx = put_tx;
2239                 prev_tx_ctx = np->put_tx_ctx;
2240                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2241                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2242                                                 PCI_DMA_TODEVICE);
2243                 np->put_tx_ctx->dma_len = bcnt;
2244                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2245                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2246                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2247
2248                 tx_flags = NV_TX2_VALID;
2249                 offset += bcnt;
2250                 size -= bcnt;
2251                 if (unlikely(put_tx++ == np->last_tx.ex))
2252                         put_tx = np->first_tx.ex;
2253                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2254                         np->put_tx_ctx = np->first_tx_ctx;
2255         } while (size);
2256
2257         /* setup the fragments */
2258         for (i = 0; i < fragments; i++) {
2259                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2260                 u32 size = frag->size;
2261                 offset = 0;
2262
2263                 do {
2264                         prev_tx = put_tx;
2265                         prev_tx_ctx = np->put_tx_ctx;
2266                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2267                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2268                                                            PCI_DMA_TODEVICE);
2269                         np->put_tx_ctx->dma_len = bcnt;
2270                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2271                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2272                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2273
2274                         offset += bcnt;
2275                         size -= bcnt;
2276                         if (unlikely(put_tx++ == np->last_tx.ex))
2277                                 put_tx = np->first_tx.ex;
2278                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2279                                 np->put_tx_ctx = np->first_tx_ctx;
2280                 } while (size);
2281         }
2282
2283         /* set last fragment flag  */
2284         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2285
2286         /* save skb in this slot's context area */
2287         prev_tx_ctx->skb = skb;
2288
2289         if (skb_is_gso(skb))
2290                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2291         else
2292                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2293                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2294
2295         /* vlan tag */
2296         if (likely(!np->vlangrp)) {
2297                 start_tx->txvlan = 0;
2298         } else {
2299                 if (vlan_tx_tag_present(skb))
2300                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2301                 else
2302                         start_tx->txvlan = 0;
2303         }
2304
2305         spin_lock_irqsave(&np->lock, flags);
2306
2307         if (np->tx_limit) {
2308                 /* Limit the number of outstanding tx. Setup all fragments, but
2309                  * do not set the VALID bit on the first descriptor. Save a pointer
2310                  * to that descriptor and also for next skb_map element.
2311                  */
2312
2313                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2314                         if (!np->tx_change_owner)
2315                                 np->tx_change_owner = start_tx_ctx;
2316
2317                         /* remove VALID bit */
2318                         tx_flags &= ~NV_TX2_VALID;
2319                         start_tx_ctx->first_tx_desc = start_tx;
2320                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2321                         np->tx_end_flip = np->put_tx_ctx;
2322                 } else {
2323                         np->tx_pkts_in_progress++;
2324                 }
2325         }
2326
2327         /* set tx flags */
2328         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2329         np->put_tx.ex = put_tx;
2330
2331         spin_unlock_irqrestore(&np->lock, flags);
2332
2333         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2334                 dev->name, entries, tx_flags_extra);
2335         {
2336                 int j;
2337                 for (j=0; j<64; j++) {
2338                         if ((j%16) == 0)
2339                                 dprintk("\n%03x:", j);
2340                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2341                 }
2342                 dprintk("\n");
2343         }
2344
2345         dev->trans_start = jiffies;
2346         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2347         return NETDEV_TX_OK;
2348 }
2349
2350 static inline void nv_tx_flip_ownership(struct net_device *dev)
2351 {
2352         struct fe_priv *np = netdev_priv(dev);
2353
2354         np->tx_pkts_in_progress--;
2355         if (np->tx_change_owner) {
2356                 np->tx_change_owner->first_tx_desc->flaglen |=
2357                         cpu_to_le32(NV_TX2_VALID);
2358                 np->tx_pkts_in_progress++;
2359
2360                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2361                 if (np->tx_change_owner == np->tx_end_flip)
2362                         np->tx_change_owner = NULL;
2363
2364                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2365         }
2366 }
2367
2368 /*
2369  * nv_tx_done: check for completed packets, release the skbs.
2370  *
2371  * Caller must own np->lock.
2372  */
2373 static void nv_tx_done(struct net_device *dev)
2374 {
2375         struct fe_priv *np = netdev_priv(dev);
2376         u32 flags;
2377         struct ring_desc* orig_get_tx = np->get_tx.orig;
2378
2379         while ((np->get_tx.orig != np->put_tx.orig) &&
2380                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2381
2382                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2383                                         dev->name, flags);
2384
2385                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2386                                np->get_tx_ctx->dma_len,
2387                                PCI_DMA_TODEVICE);
2388                 np->get_tx_ctx->dma = 0;
2389
2390                 if (np->desc_ver == DESC_VER_1) {
2391                         if (flags & NV_TX_LASTPACKET) {
2392                                 if (flags & NV_TX_ERROR) {
2393                                         if (flags & NV_TX_UNDERFLOW)
2394                                                 dev->stats.tx_fifo_errors++;
2395                                         if (flags & NV_TX_CARRIERLOST)
2396                                                 dev->stats.tx_carrier_errors++;
2397                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2398                                                 nv_legacybackoff_reseed(dev);
2399                                         dev->stats.tx_errors++;
2400                                 } else {
2401                                         dev->stats.tx_packets++;
2402                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2403                                 }
2404                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2405                                 np->get_tx_ctx->skb = NULL;
2406                         }
2407                 } else {
2408                         if (flags & NV_TX2_LASTPACKET) {
2409                                 if (flags & NV_TX2_ERROR) {
2410                                         if (flags & NV_TX2_UNDERFLOW)
2411                                                 dev->stats.tx_fifo_errors++;
2412                                         if (flags & NV_TX2_CARRIERLOST)
2413                                                 dev->stats.tx_carrier_errors++;
2414                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2415                                                 nv_legacybackoff_reseed(dev);
2416                                         dev->stats.tx_errors++;
2417                                 } else {
2418                                         dev->stats.tx_packets++;
2419                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2420                                 }
2421                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2422                                 np->get_tx_ctx->skb = NULL;
2423                         }
2424                 }
2425                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2426                         np->get_tx.orig = np->first_tx.orig;
2427                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2428                         np->get_tx_ctx = np->first_tx_ctx;
2429         }
2430         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2431                 np->tx_stop = 0;
2432                 netif_wake_queue(dev);
2433         }
2434 }
2435
2436 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2437 {
2438         struct fe_priv *np = netdev_priv(dev);
2439         u32 flags;
2440         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2441
2442         while ((np->get_tx.ex != np->put_tx.ex) &&
2443                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2444                (limit-- > 0)) {
2445
2446                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2447                                         dev->name, flags);
2448
2449                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2450                                np->get_tx_ctx->dma_len,
2451                                PCI_DMA_TODEVICE);
2452                 np->get_tx_ctx->dma = 0;
2453
2454                 if (flags & NV_TX2_LASTPACKET) {
2455                         if (!(flags & NV_TX2_ERROR))
2456                                 dev->stats.tx_packets++;
2457                         else {
2458                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2459                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2460                                                 nv_gear_backoff_reseed(dev);
2461                                         else
2462                                                 nv_legacybackoff_reseed(dev);
2463                                 }
2464                         }
2465
2466                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2467                         np->get_tx_ctx->skb = NULL;
2468
2469                         if (np->tx_limit) {
2470                                 nv_tx_flip_ownership(dev);
2471                         }
2472                 }
2473                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2474                         np->get_tx.ex = np->first_tx.ex;
2475                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2476                         np->get_tx_ctx = np->first_tx_ctx;
2477         }
2478         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2479                 np->tx_stop = 0;
2480                 netif_wake_queue(dev);
2481         }
2482 }
2483
2484 /*
2485  * nv_tx_timeout: dev->tx_timeout function
2486  * Called with netif_tx_lock held.
2487  */
2488 static void nv_tx_timeout(struct net_device *dev)
2489 {
2490         struct fe_priv *np = netdev_priv(dev);
2491         u8 __iomem *base = get_hwbase(dev);
2492         u32 status;
2493
2494         if (np->msi_flags & NV_MSI_X_ENABLED)
2495                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2496         else
2497                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2498
2499         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2500
2501         {
2502                 int i;
2503
2504                 printk(KERN_INFO "%s: Ring at %lx\n",
2505                        dev->name, (unsigned long)np->ring_addr);
2506                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2507                 for (i=0;i<=np->register_size;i+= 32) {
2508                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2509                                         i,
2510                                         readl(base + i + 0), readl(base + i + 4),
2511                                         readl(base + i + 8), readl(base + i + 12),
2512                                         readl(base + i + 16), readl(base + i + 20),
2513                                         readl(base + i + 24), readl(base + i + 28));
2514                 }
2515                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2516                 for (i=0;i<np->tx_ring_size;i+= 4) {
2517                         if (!nv_optimized(np)) {
2518                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2519                                        i,
2520                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2521                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2522                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2523                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2524                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2525                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2526                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2527                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2528                         } else {
2529                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2530                                        i,
2531                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2532                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2533                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2534                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2535                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2536                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2537                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2538                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2539                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2540                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2541                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2542                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2543                         }
2544                 }
2545         }
2546
2547         spin_lock_irq(&np->lock);
2548
2549         /* 1) stop tx engine */
2550         nv_stop_tx(dev);
2551
2552         /* 2) check that the packets were not sent already: */
2553         if (!nv_optimized(np))
2554                 nv_tx_done(dev);
2555         else
2556                 nv_tx_done_optimized(dev, np->tx_ring_size);
2557
2558         /* 3) if there are dead entries: clear everything */
2559         if (np->get_tx_ctx != np->put_tx_ctx) {
2560                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2561                 nv_drain_tx(dev);
2562                 nv_init_tx(dev);
2563                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2564         }
2565
2566         netif_wake_queue(dev);
2567
2568         /* 4) restart tx engine */
2569         nv_start_tx(dev);
2570         spin_unlock_irq(&np->lock);
2571 }
2572
2573 /*
2574  * Called when the nic notices a mismatch between the actual data len on the
2575  * wire and the len indicated in the 802 header
2576  */
2577 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2578 {
2579         int hdrlen;     /* length of the 802 header */
2580         int protolen;   /* length as stored in the proto field */
2581
2582         /* 1) calculate len according to header */
2583         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2584                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2585                 hdrlen = VLAN_HLEN;
2586         } else {
2587                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2588                 hdrlen = ETH_HLEN;
2589         }
2590         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2591                                 dev->name, datalen, protolen, hdrlen);
2592         if (protolen > ETH_DATA_LEN)
2593                 return datalen; /* Value in proto field not a len, no checks possible */
2594
2595         protolen += hdrlen;
2596         /* consistency checks: */
2597         if (datalen > ETH_ZLEN) {
2598                 if (datalen >= protolen) {
2599                         /* more data on wire than in 802 header, trim of
2600                          * additional data.
2601                          */
2602                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2603                                         dev->name, protolen);
2604                         return protolen;
2605                 } else {
2606                         /* less data on wire than mentioned in header.
2607                          * Discard the packet.
2608                          */
2609                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2610                                         dev->name);
2611                         return -1;
2612                 }
2613         } else {
2614                 /* short packet. Accept only if 802 values are also short */
2615                 if (protolen > ETH_ZLEN) {
2616                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2617                                         dev->name);
2618                         return -1;
2619                 }
2620                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2621                                 dev->name, datalen);
2622                 return datalen;
2623         }
2624 }
2625
2626 static int nv_rx_process(struct net_device *dev, int limit)
2627 {
2628         struct fe_priv *np = netdev_priv(dev);
2629         u32 flags;
2630         int rx_work = 0;
2631         struct sk_buff *skb;
2632         int len;
2633
2634         while((np->get_rx.orig != np->put_rx.orig) &&
2635               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2636                 (rx_work < limit)) {
2637
2638                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2639                                         dev->name, flags);
2640
2641                 /*
2642                  * the packet is for us - immediately tear down the pci mapping.
2643                  * TODO: check if a prefetch of the first cacheline improves
2644                  * the performance.
2645                  */
2646                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2647                                 np->get_rx_ctx->dma_len,
2648                                 PCI_DMA_FROMDEVICE);
2649                 skb = np->get_rx_ctx->skb;
2650                 np->get_rx_ctx->skb = NULL;
2651
2652                 {
2653                         int j;
2654                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2655                         for (j=0; j<64; j++) {
2656                                 if ((j%16) == 0)
2657                                         dprintk("\n%03x:", j);
2658                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2659                         }
2660                         dprintk("\n");
2661                 }
2662                 /* look at what we actually got: */
2663                 if (np->desc_ver == DESC_VER_1) {
2664                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2665                                 len = flags & LEN_MASK_V1;
2666                                 if (unlikely(flags & NV_RX_ERROR)) {
2667                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2668                                                 len = nv_getlen(dev, skb->data, len);
2669                                                 if (len < 0) {
2670                                                         dev->stats.rx_errors++;
2671                                                         dev_kfree_skb(skb);
2672                                                         goto next_pkt;
2673                                                 }
2674                                         }
2675                                         /* framing errors are soft errors */
2676                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2677                                                 if (flags & NV_RX_SUBSTRACT1) {
2678                                                         len--;
2679                                                 }
2680                                         }
2681                                         /* the rest are hard errors */
2682                                         else {
2683                                                 if (flags & NV_RX_MISSEDFRAME)
2684                                                         dev->stats.rx_missed_errors++;
2685                                                 if (flags & NV_RX_CRCERR)
2686                                                         dev->stats.rx_crc_errors++;
2687                                                 if (flags & NV_RX_OVERFLOW)
2688                                                         dev->stats.rx_over_errors++;
2689                                                 dev->stats.rx_errors++;
2690                                                 dev_kfree_skb(skb);
2691                                                 goto next_pkt;
2692                                         }
2693                                 }
2694                         } else {
2695                                 dev_kfree_skb(skb);
2696                                 goto next_pkt;
2697                         }
2698                 } else {
2699                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2700                                 len = flags & LEN_MASK_V2;
2701                                 if (unlikely(flags & NV_RX2_ERROR)) {
2702                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2703                                                 len = nv_getlen(dev, skb->data, len);
2704                                                 if (len < 0) {
2705                                                         dev->stats.rx_errors++;
2706                                                         dev_kfree_skb(skb);
2707                                                         goto next_pkt;
2708                                                 }
2709                                         }
2710                                         /* framing errors are soft errors */
2711                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2712                                                 if (flags & NV_RX2_SUBSTRACT1) {
2713                                                         len--;
2714                                                 }
2715                                         }
2716                                         /* the rest are hard errors */
2717                                         else {
2718                                                 if (flags & NV_RX2_CRCERR)
2719                                                         dev->stats.rx_crc_errors++;
2720                                                 if (flags & NV_RX2_OVERFLOW)
2721                                                         dev->stats.rx_over_errors++;
2722                                                 dev->stats.rx_errors++;
2723                                                 dev_kfree_skb(skb);
2724                                                 goto next_pkt;
2725                                         }
2726                                 }
2727                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2728                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2729                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2730                         } else {
2731                                 dev_kfree_skb(skb);
2732                                 goto next_pkt;
2733                         }
2734                 }
2735                 /* got a valid packet - forward it to the network core */
2736                 skb_put(skb, len);
2737                 skb->protocol = eth_type_trans(skb, dev);
2738                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2739                                         dev->name, len, skb->protocol);
2740 #ifdef CONFIG_FORCEDETH_NAPI
2741                 netif_receive_skb(skb);
2742 #else
2743                 netif_rx(skb);
2744 #endif
2745                 dev->stats.rx_packets++;
2746                 dev->stats.rx_bytes += len;
2747 next_pkt:
2748                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2749                         np->get_rx.orig = np->first_rx.orig;
2750                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2751                         np->get_rx_ctx = np->first_rx_ctx;
2752
2753                 rx_work++;
2754         }
2755
2756         return rx_work;
2757 }
2758
2759 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2760 {
2761         struct fe_priv *np = netdev_priv(dev);
2762         u32 flags;
2763         u32 vlanflags = 0;
2764         int rx_work = 0;
2765         struct sk_buff *skb;
2766         int len;
2767
2768         while((np->get_rx.ex != np->put_rx.ex) &&
2769               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2770               (rx_work < limit)) {
2771
2772                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2773                                         dev->name, flags);
2774
2775                 /*
2776                  * the packet is for us - immediately tear down the pci mapping.
2777                  * TODO: check if a prefetch of the first cacheline improves
2778                  * the performance.
2779                  */
2780                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2781                                 np->get_rx_ctx->dma_len,
2782                                 PCI_DMA_FROMDEVICE);
2783                 skb = np->get_rx_ctx->skb;
2784                 np->get_rx_ctx->skb = NULL;
2785
2786                 {
2787                         int j;
2788                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2789                         for (j=0; j<64; j++) {
2790                                 if ((j%16) == 0)
2791                                         dprintk("\n%03x:", j);
2792                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2793                         }
2794                         dprintk("\n");
2795                 }
2796                 /* look at what we actually got: */
2797                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2798                         len = flags & LEN_MASK_V2;
2799                         if (unlikely(flags & NV_RX2_ERROR)) {
2800                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2801                                         len = nv_getlen(dev, skb->data, len);
2802                                         if (len < 0) {
2803                                                 dev_kfree_skb(skb);
2804                                                 goto next_pkt;
2805                                         }
2806                                 }
2807                                 /* framing errors are soft errors */
2808                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2809                                         if (flags & NV_RX2_SUBSTRACT1) {
2810                                                 len--;
2811                                         }
2812                                 }
2813                                 /* the rest are hard errors */
2814                                 else {
2815                                         dev_kfree_skb(skb);
2816                                         goto next_pkt;
2817                                 }
2818                         }
2819
2820                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2821                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2822                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2823
2824                         /* got a valid packet - forward it to the network core */
2825                         skb_put(skb, len);
2826                         skb->protocol = eth_type_trans(skb, dev);
2827                         prefetch(skb->data);
2828
2829                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2830                                 dev->name, len, skb->protocol);
2831
2832                         if (likely(!np->vlangrp)) {
2833 #ifdef CONFIG_FORCEDETH_NAPI
2834                                 netif_receive_skb(skb);
2835 #else
2836                                 netif_rx(skb);
2837 #endif
2838                         } else {
2839                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2840                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2841 #ifdef CONFIG_FORCEDETH_NAPI
2842                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2843                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2844 #else
2845                                         vlan_hwaccel_rx(skb, np->vlangrp,
2846                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2847 #endif
2848                                 } else {
2849 #ifdef CONFIG_FORCEDETH_NAPI
2850                                         netif_receive_skb(skb);
2851 #else
2852                                         netif_rx(skb);
2853 #endif
2854                                 }
2855                         }
2856
2857                         dev->stats.rx_packets++;
2858                         dev->stats.rx_bytes += len;
2859                 } else {
2860                         dev_kfree_skb(skb);
2861                 }
2862 next_pkt:
2863                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2864                         np->get_rx.ex = np->first_rx.ex;
2865                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2866                         np->get_rx_ctx = np->first_rx_ctx;
2867
2868                 rx_work++;
2869         }
2870
2871         return rx_work;
2872 }
2873
2874 static void set_bufsize(struct net_device *dev)
2875 {
2876         struct fe_priv *np = netdev_priv(dev);
2877
2878         if (dev->mtu <= ETH_DATA_LEN)
2879                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2880         else
2881                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2882 }
2883
2884 /*
2885  * nv_change_mtu: dev->change_mtu function
2886  * Called with dev_base_lock held for read.
2887  */
2888 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2889 {
2890         struct fe_priv *np = netdev_priv(dev);
2891         int old_mtu;
2892
2893         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2894                 return -EINVAL;
2895
2896         old_mtu = dev->mtu;
2897         dev->mtu = new_mtu;
2898
2899         /* return early if the buffer sizes will not change */
2900         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2901                 return 0;
2902         if (old_mtu == new_mtu)
2903                 return 0;
2904
2905         /* synchronized against open : rtnl_lock() held by caller */
2906         if (netif_running(dev)) {
2907                 u8 __iomem *base = get_hwbase(dev);
2908                 /*
2909                  * It seems that the nic preloads valid ring entries into an
2910                  * internal buffer. The procedure for flushing everything is
2911                  * guessed, there is probably a simpler approach.
2912                  * Changing the MTU is a rare event, it shouldn't matter.
2913                  */
2914                 nv_disable_irq(dev);
2915                 netif_tx_lock_bh(dev);
2916                 netif_addr_lock(dev);
2917                 spin_lock(&np->lock);
2918                 /* stop engines */
2919                 nv_stop_rxtx(dev);
2920                 nv_txrx_reset(dev);
2921                 /* drain rx queue */
2922                 nv_drain_rxtx(dev);
2923                 /* reinit driver view of the rx queue */
2924                 set_bufsize(dev);
2925                 if (nv_init_ring(dev)) {
2926                         if (!np->in_shutdown)
2927                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2928                 }
2929                 /* reinit nic view of the rx queue */
2930                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2931                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2932                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2933                         base + NvRegRingSizes);
2934                 pci_push(base);
2935                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2936                 pci_push(base);
2937
2938                 /* restart rx engine */
2939                 nv_start_rxtx(dev);
2940                 spin_unlock(&np->lock);
2941                 netif_addr_unlock(dev);
2942                 netif_tx_unlock_bh(dev);
2943                 nv_enable_irq(dev);
2944         }
2945         return 0;
2946 }
2947
2948 static void nv_copy_mac_to_hw(struct net_device *dev)
2949 {
2950         u8 __iomem *base = get_hwbase(dev);
2951         u32 mac[2];
2952
2953         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2954                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2955         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2956
2957         writel(mac[0], base + NvRegMacAddrA);
2958         writel(mac[1], base + NvRegMacAddrB);
2959 }
2960
2961 /*
2962  * nv_set_mac_address: dev->set_mac_address function
2963  * Called with rtnl_lock() held.
2964  */
2965 static int nv_set_mac_address(struct net_device *dev, void *addr)
2966 {
2967         struct fe_priv *np = netdev_priv(dev);
2968         struct sockaddr *macaddr = (struct sockaddr*)addr;
2969
2970         if (!is_valid_ether_addr(macaddr->sa_data))
2971                 return -EADDRNOTAVAIL;
2972
2973         /* synchronized against open : rtnl_lock() held by caller */
2974         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2975
2976         if (netif_running(dev)) {
2977                 netif_tx_lock_bh(dev);
2978                 netif_addr_lock(dev);
2979                 spin_lock_irq(&np->lock);
2980
2981                 /* stop rx engine */
2982                 nv_stop_rx(dev);
2983
2984                 /* set mac address */
2985                 nv_copy_mac_to_hw(dev);
2986
2987                 /* restart rx engine */
2988                 nv_start_rx(dev);
2989                 spin_unlock_irq(&np->lock);
2990                 netif_addr_unlock(dev);
2991                 netif_tx_unlock_bh(dev);
2992         } else {
2993                 nv_copy_mac_to_hw(dev);
2994         }
2995         return 0;
2996 }
2997
2998 /*
2999  * nv_set_multicast: dev->set_multicast function
3000  * Called with netif_tx_lock held.
3001  */
3002 static void nv_set_multicast(struct net_device *dev)
3003 {
3004         struct fe_priv *np = netdev_priv(dev);
3005         u8 __iomem *base = get_hwbase(dev);
3006         u32 addr[2];
3007         u32 mask[2];
3008         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3009
3010         memset(addr, 0, sizeof(addr));
3011         memset(mask, 0, sizeof(mask));
3012
3013         if (dev->flags & IFF_PROMISC) {
3014                 pff |= NVREG_PFF_PROMISC;
3015         } else {
3016                 pff |= NVREG_PFF_MYADDR;
3017
3018                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3019                         u32 alwaysOff[2];
3020                         u32 alwaysOn[2];
3021
3022                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3023                         if (dev->flags & IFF_ALLMULTI) {
3024                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3025                         } else {
3026                                 struct dev_mc_list *walk;
3027
3028                                 walk = dev->mc_list;
3029                                 while (walk != NULL) {
3030                                         u32 a, b;
3031                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3032                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3033                                         alwaysOn[0] &= a;
3034                                         alwaysOff[0] &= ~a;
3035                                         alwaysOn[1] &= b;
3036                                         alwaysOff[1] &= ~b;
3037                                         walk = walk->next;
3038                                 }
3039                         }
3040                         addr[0] = alwaysOn[0];
3041                         addr[1] = alwaysOn[1];
3042                         mask[0] = alwaysOn[0] | alwaysOff[0];
3043                         mask[1] = alwaysOn[1] | alwaysOff[1];
3044                 } else {
3045                         mask[0] = NVREG_MCASTMASKA_NONE;
3046                         mask[1] = NVREG_MCASTMASKB_NONE;
3047                 }
3048         }
3049         addr[0] |= NVREG_MCASTADDRA_FORCE;
3050         pff |= NVREG_PFF_ALWAYS;
3051         spin_lock_irq(&np->lock);
3052         nv_stop_rx(dev);
3053         writel(addr[0], base + NvRegMulticastAddrA);
3054         writel(addr[1], base + NvRegMulticastAddrB);
3055         writel(mask[0], base + NvRegMulticastMaskA);
3056         writel(mask[1], base + NvRegMulticastMaskB);
3057         writel(pff, base + NvRegPacketFilterFlags);
3058         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3059                 dev->name);
3060         nv_start_rx(dev);
3061         spin_unlock_irq(&np->lock);
3062 }
3063
3064 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3065 {
3066         struct fe_priv *np = netdev_priv(dev);
3067         u8 __iomem *base = get_hwbase(dev);
3068
3069         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3070
3071         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3072                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3073                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3074                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3075                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3076                 } else {
3077                         writel(pff, base + NvRegPacketFilterFlags);
3078                 }
3079         }
3080         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3081                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3082                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3083                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3084                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3085                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3086                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3087                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3088                                 /* limit the number of tx pause frames to a default of 8 */
3089                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3090                         }
3091                         writel(pause_enable,  base + NvRegTxPauseFrame);
3092                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3093                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3094                 } else {
3095                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3096                         writel(regmisc, base + NvRegMisc1);
3097                 }
3098         }
3099 }
3100
3101 /**
3102  * nv_update_linkspeed: Setup the MAC according to the link partner
3103  * @dev: Network device to be configured
3104  *
3105  * The function queries the PHY and checks if there is a link partner.
3106  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3107  * set to 10 MBit HD.
3108  *
3109  * The function returns 0 if there is no link partner and 1 if there is
3110  * a good link partner.
3111  */
3112 static int nv_update_linkspeed(struct net_device *dev)
3113 {
3114         struct fe_priv *np = netdev_priv(dev);
3115         u8 __iomem *base = get_hwbase(dev);
3116         int adv = 0;
3117         int lpa = 0;
3118         int adv_lpa, adv_pause, lpa_pause;
3119         int newls = np->linkspeed;
3120         int newdup = np->duplex;
3121         int mii_status;
3122         int retval = 0;
3123         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3124         u32 txrxFlags = 0;
3125         u32 phy_exp;
3126
3127         /* BMSR_LSTATUS is latched, read it twice:
3128          * we want the current value.
3129          */
3130         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3131         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3132
3133         if (!(mii_status & BMSR_LSTATUS)) {
3134                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3135                                 dev->name);
3136                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3137                 newdup = 0;
3138                 retval = 0;
3139                 goto set_speed;
3140         }
3141
3142         if (np->autoneg == 0) {
3143                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3144                                 dev->name, np->fixed_mode);
3145                 if (np->fixed_mode & LPA_100FULL) {
3146                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3147                         newdup = 1;
3148                 } else if (np->fixed_mode & LPA_100HALF) {
3149                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3150                         newdup = 0;
3151                 } else if (np->fixed_mode & LPA_10FULL) {
3152                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3153                         newdup = 1;
3154                 } else {
3155                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3156                         newdup = 0;
3157                 }
3158                 retval = 1;
3159                 goto set_speed;
3160         }
3161         /* check auto negotiation is complete */
3162         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3163                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3164                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3165                 newdup = 0;
3166                 retval = 0;
3167                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3168                 goto set_speed;
3169         }
3170
3171         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3172         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3173         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3174                                 dev->name, adv, lpa);
3175
3176         retval = 1;
3177         if (np->gigabit == PHY_GIGABIT) {
3178                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3179                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3180
3181                 if ((control_1000 & ADVERTISE_1000FULL) &&
3182                         (status_1000 & LPA_1000FULL)) {
3183                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3184                                 dev->name);
3185                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3186                         newdup = 1;
3187                         goto set_speed;
3188                 }
3189         }
3190
3191         /* FIXME: handle parallel detection properly */
3192         adv_lpa = lpa & adv;
3193         if (adv_lpa & LPA_100FULL) {
3194                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3195                 newdup = 1;
3196         } else if (adv_lpa & LPA_100HALF) {
3197                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3198                 newdup = 0;
3199         } else if (adv_lpa & LPA_10FULL) {
3200                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3201                 newdup = 1;
3202         } else if (adv_lpa & LPA_10HALF) {
3203                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3204                 newdup = 0;
3205         } else {
3206                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3207                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3208                 newdup = 0;
3209         }
3210
3211 set_speed:
3212         if (np->duplex == newdup && np->linkspeed == newls)
3213                 return retval;
3214
3215         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3216                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3217
3218         np->duplex = newdup;
3219         np->linkspeed = newls;
3220
3221         /* The transmitter and receiver must be restarted for safe update */
3222         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3223                 txrxFlags |= NV_RESTART_TX;
3224                 nv_stop_tx(dev);
3225         }
3226         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3227                 txrxFlags |= NV_RESTART_RX;
3228                 nv_stop_rx(dev);
3229         }
3230
3231         if (np->gigabit == PHY_GIGABIT) {
3232                 phyreg = readl(base + NvRegSlotTime);
3233                 phyreg &= ~(0x3FF00);
3234                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3235                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3236                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3237                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3238                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3239                 writel(phyreg, base + NvRegSlotTime);
3240         }
3241
3242         phyreg = readl(base + NvRegPhyInterface);
3243         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3244         if (np->duplex == 0)
3245                 phyreg |= PHY_HALF;
3246         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3247                 phyreg |= PHY_100;
3248         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3249                 phyreg |= PHY_1000;
3250         writel(phyreg, base + NvRegPhyInterface);
3251
3252         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3253         if (phyreg & PHY_RGMII) {
3254                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3255                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3256                 } else {
3257                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3258                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3259                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3260                                 else
3261                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3262                         } else {
3263                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3264                         }
3265                 }
3266         } else {
3267                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3268                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3269                 else
3270                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3271         }
3272         writel(txreg, base + NvRegTxDeferral);
3273
3274         if (np->desc_ver == DESC_VER_1) {
3275                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3276         } else {
3277                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3278                         txreg = NVREG_TX_WM_DESC2_3_1000;
3279                 else
3280                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3281         }
3282         writel(txreg, base + NvRegTxWatermark);
3283
3284         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3285                 base + NvRegMisc1);
3286         pci_push(base);
3287         writel(np->linkspeed, base + NvRegLinkSpeed);
3288         pci_push(base);
3289
3290         pause_flags = 0;
3291         /* setup pause frame */
3292         if (np->duplex != 0) {
3293                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3294                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3295                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3296
3297                         switch (adv_pause) {
3298                         case ADVERTISE_PAUSE_CAP:
3299                                 if (lpa_pause & LPA_PAUSE_CAP) {
3300                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3301                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3302                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3303                                 }
3304                                 break;
3305                         case ADVERTISE_PAUSE_ASYM:
3306                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3307                                 {
3308                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3309                                 }
3310                                 break;
3311                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3312                                 if (lpa_pause & LPA_PAUSE_CAP)
3313                                 {
3314                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3315                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3316                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3317                                 }
3318                                 if (lpa_pause == LPA_PAUSE_ASYM)
3319                                 {
3320                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3321                                 }
3322                                 break;
3323                         }
3324                 } else {
3325                         pause_flags = np->pause_flags;
3326                 }
3327         }
3328         nv_update_pause(dev, pause_flags);
3329
3330         if (txrxFlags & NV_RESTART_TX)
3331                 nv_start_tx(dev);
3332         if (txrxFlags & NV_RESTART_RX)
3333                 nv_start_rx(dev);
3334
3335         return retval;
3336 }
3337
3338 static void nv_linkchange(struct net_device *dev)
3339 {
3340         if (nv_update_linkspeed(dev)) {
3341                 if (!netif_carrier_ok(dev)) {
3342                         netif_carrier_on(dev);
3343                         printk(KERN_INFO "%s: link up.\n", dev->name);
3344                         nv_start_rx(dev);
3345                 }
3346         } else {
3347                 if (netif_carrier_ok(dev)) {
3348                         netif_carrier_off(dev);
3349                         printk(KERN_INFO "%s: link down.\n", dev->name);
3350                         nv_stop_rx(dev);
3351                 }
3352         }
3353 }
3354
3355 static void nv_link_irq(struct net_device *dev)
3356 {
3357         u8 __iomem *base = get_hwbase(dev);
3358         u32 miistat;
3359
3360         miistat = readl(base + NvRegMIIStatus);
3361         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3362         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3363
3364         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3365                 nv_linkchange(dev);
3366         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3367 }
3368
3369 static void nv_msi_workaround(struct fe_priv *np)
3370 {
3371
3372         /* Need to toggle the msi irq mask within the ethernet device,
3373          * otherwise, future interrupts will not be detected.
3374          */
3375         if (np->msi_flags & NV_MSI_ENABLED) {
3376                 u8 __iomem *base = np->base;
3377
3378                 writel(0, base + NvRegMSIIrqMask);
3379                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3380         }
3381 }
3382
3383 static irqreturn_t nv_nic_irq(int foo, void *data)
3384 {
3385         struct net_device *dev = (struct net_device *) data;
3386         struct fe_priv *np = netdev_priv(dev);
3387         u8 __iomem *base = get_hwbase(dev);
3388         u32 events;
3389         int i;
3390
3391         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3392
3393         for (i=0; ; i++) {
3394                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3395                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3396                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3397                 } else {
3398                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3399                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3400                 }
3401                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3402                 if (!(events & np->irqmask))
3403                         break;
3404
3405                 nv_msi_workaround(np);
3406
3407                 spin_lock(&np->lock);
3408                 nv_tx_done(dev);
3409                 spin_unlock(&np->lock);
3410
3411 #ifdef CONFIG_FORCEDETH_NAPI
3412                 if (events & NVREG_IRQ_RX_ALL) {
3413                         spin_lock(&np->lock);
3414                         napi_schedule(&np->napi);
3415
3416                         /* Disable furthur receive irq's */
3417                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3418
3419                         if (np->msi_flags & NV_MSI_X_ENABLED)
3420                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3421                         else
3422                                 writel(np->irqmask, base + NvRegIrqMask);
3423                         spin_unlock(&np->lock);
3424                 }
3425 #else
3426                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3427                         if (unlikely(nv_alloc_rx(dev))) {
3428                                 spin_lock(&np->lock);
3429                                 if (!np->in_shutdown)
3430                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3431                                 spin_unlock(&np->lock);
3432                         }
3433                 }
3434 #endif
3435                 if (unlikely(events & NVREG_IRQ_LINK)) {
3436                         spin_lock(&np->lock);
3437                         nv_link_irq(dev);
3438                         spin_unlock(&np->lock);
3439                 }
3440                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3441                         spin_lock(&np->lock);
3442                         nv_linkchange(dev);
3443                         spin_unlock(&np->lock);
3444                         np->link_timeout = jiffies + LINK_TIMEOUT;
3445                 }
3446                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3447                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3448                                                 dev->name, events);
3449                 }
3450                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3451                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3452                                                 dev->name, events);
3453                 }
3454                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3455                         spin_lock(&np->lock);
3456                         /* disable interrupts on the nic */
3457                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3458                                 writel(0, base + NvRegIrqMask);
3459                         else
3460                                 writel(np->irqmask, base + NvRegIrqMask);
3461                         pci_push(base);
3462
3463                         if (!np->in_shutdown) {
3464                                 np->nic_poll_irq = np->irqmask;
3465                                 np->recover_error = 1;
3466                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3467                         }
3468                         spin_unlock(&np->lock);
3469                         break;
3470                 }
3471                 if (unlikely(i > max_interrupt_work)) {
3472                         spin_lock(&np->lock);
3473                         /* disable interrupts on the nic */
3474                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3475                                 writel(0, base + NvRegIrqMask);
3476                         else
3477                                 writel(np->irqmask, base + NvRegIrqMask);
3478                         pci_push(base);
3479
3480                         if (!np->in_shutdown) {
3481                                 np->nic_poll_irq = np->irqmask;
3482                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3483                         }
3484                         spin_unlock(&np->lock);
3485                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3486                         break;
3487                 }
3488
3489         }
3490         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3491
3492         return IRQ_RETVAL(i);
3493 }
3494
3495 /**
3496  * All _optimized functions are used to help increase performance
3497  * (reduce CPU and increase throughput). They use descripter version 3,
3498  * compiler directives, and reduce memory accesses.
3499  */
3500 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3501 {
3502         struct net_device *dev = (struct net_device *) data;
3503         struct fe_priv *np = netdev_priv(dev);
3504         u8 __iomem *base = get_hwbase(dev);
3505         u32 events;
3506         int i;
3507
3508         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3509
3510         for (i=0; ; i++) {
3511                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3512                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3513                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3514                 } else {
3515                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3516                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3517                 }
3518                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3519                 if (!(events & np->irqmask))
3520                         break;
3521
3522                 nv_msi_workaround(np);
3523
3524                 spin_lock(&np->lock);
3525                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3526                 spin_unlock(&np->lock);
3527
3528 #ifdef CONFIG_FORCEDETH_NAPI
3529                 if (events & NVREG_IRQ_RX_ALL) {
3530                         spin_lock(&np->lock);
3531                         napi_schedule(&np->napi);
3532
3533                         /* Disable furthur receive irq's */
3534                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3535
3536                         if (np->msi_flags & NV_MSI_X_ENABLED)
3537                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3538                         else
3539                                 writel(np->irqmask, base + NvRegIrqMask);
3540                         spin_unlock(&np->lock);
3541                 }
3542 #else
3543                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3544                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3545                                 spin_lock(&np->lock);
3546                                 if (!np->in_shutdown)
3547                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3548                                 spin_unlock(&np->lock);
3549                         }
3550                 }
3551 #endif
3552                 if (unlikely(events & NVREG_IRQ_LINK)) {
3553                         spin_lock(&np->lock);
3554                         nv_link_irq(dev);
3555                         spin_unlock(&np->lock);
3556                 }
3557                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3558                         spin_lock(&np->lock);
3559                         nv_linkchange(dev);
3560                         spin_unlock(&np->lock);
3561                         np->link_timeout = jiffies + LINK_TIMEOUT;
3562                 }
3563                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3564                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3565                                                 dev->name, events);
3566                 }
3567                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3568                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3569                                                 dev->name, events);
3570                 }
3571                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3572                         spin_lock(&np->lock);
3573                         /* disable interrupts on the nic */
3574                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3575                                 writel(0, base + NvRegIrqMask);
3576                         else
3577                                 writel(np->irqmask, base + NvRegIrqMask);
3578                         pci_push(base);
3579
3580                         if (!np->in_shutdown) {
3581                                 np->nic_poll_irq = np->irqmask;
3582                                 np->recover_error = 1;
3583                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3584                         }
3585                         spin_unlock(&np->lock);
3586                         break;
3587                 }
3588
3589                 if (unlikely(i > max_interrupt_work)) {
3590                         spin_lock(&np->lock);
3591                         /* disable interrupts on the nic */
3592                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3593                                 writel(0, base + NvRegIrqMask);
3594                         else
3595                                 writel(np->irqmask, base + NvRegIrqMask);
3596                         pci_push(base);
3597
3598                         if (!np->in_shutdown) {
3599                                 np->nic_poll_irq = np->irqmask;
3600                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3601                         }
3602                         spin_unlock(&np->lock);
3603                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3604                         break;
3605                 }
3606
3607         }
3608         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3609
3610         return IRQ_RETVAL(i);
3611 }
3612
3613 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3614 {
3615         struct net_device *dev = (struct net_device *) data;
3616         struct fe_priv *np = netdev_priv(dev);
3617         u8 __iomem *base = get_hwbase(dev);
3618         u32 events;
3619         int i;
3620         unsigned long flags;
3621
3622         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3623
3624         for (i=0; ; i++) {
3625                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3626                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3627                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3628                 if (!(events & np->irqmask))
3629                         break;
3630
3631                 spin_lock_irqsave(&np->lock, flags);
3632                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3633                 spin_unlock_irqrestore(&np->lock, flags);
3634
3635                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3636                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3637                                                 dev->name, events);
3638                 }
3639                 if (unlikely(i > max_interrupt_work)) {
3640                         spin_lock_irqsave(&np->lock, flags);
3641                         /* disable interrupts on the nic */
3642                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3643                         pci_push(base);
3644
3645                         if (!np->in_shutdown) {
3646                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3647                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3648                         }
3649                         spin_unlock_irqrestore(&np->lock, flags);
3650                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3651                         break;
3652                 }
3653
3654         }
3655         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3656
3657         return IRQ_RETVAL(i);
3658 }
3659
3660 #ifdef CONFIG_FORCEDETH_NAPI
3661 static int nv_napi_poll(struct napi_struct *napi, int budget)
3662 {
3663         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3664         struct net_device *dev = np->dev;
3665         u8 __iomem *base = get_hwbase(dev);
3666         unsigned long flags;
3667         int pkts, retcode;
3668
3669         if (!nv_optimized(np)) {
3670                 pkts = nv_rx_process(dev, budget);
3671                 retcode = nv_alloc_rx(dev);
3672         } else {
3673                 pkts = nv_rx_process_optimized(dev, budget);
3674                 retcode = nv_alloc_rx_optimized(dev);
3675         }
3676
3677         if (retcode) {
3678                 spin_lock_irqsave(&np->lock, flags);
3679                 if (!np->in_shutdown)
3680                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3681                 spin_unlock_irqrestore(&np->lock, flags);
3682         }
3683
3684         if (pkts < budget) {
3685                 /* re-enable receive interrupts */
3686                 spin_lock_irqsave(&np->lock, flags);
3687
3688                 __napi_complete(napi);
3689
3690                 np->irqmask |= NVREG_IRQ_RX_ALL;
3691                 if (np->msi_flags & NV_MSI_X_ENABLED)
3692                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3693                 else
3694                         writel(np->irqmask, base + NvRegIrqMask);
3695
3696                 spin_unlock_irqrestore(&np->lock, flags);
3697         }
3698         return pkts;
3699 }
3700 #endif
3701
3702 #ifdef CONFIG_FORCEDETH_NAPI
3703 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3704 {
3705         struct net_device *dev = (struct net_device *) data;
3706         struct fe_priv *np = netdev_priv(dev);
3707         u8 __iomem *base = get_hwbase(dev);
3708         u32 events;
3709
3710         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3711
3712         if (events) {
3713                 /* disable receive interrupts on the nic */
3714                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3715                 pci_push(base);
3716                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3717                 napi_schedule(&np->napi);
3718         }
3719         return IRQ_HANDLED;
3720 }
3721 #else
3722 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3723 {
3724         struct net_device *dev = (struct net_device *) data;
3725         struct fe_priv *np = netdev_priv(dev);
3726         u8 __iomem *base = get_hwbase(dev);
3727         u32 events;
3728         int i;
3729         unsigned long flags;
3730
3731         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3732
3733         for (i=0; ; i++) {
3734                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3735                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3736                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3737                 if (!(events & np->irqmask))
3738                         break;
3739
3740                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3741                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3742                                 spin_lock_irqsave(&np->lock, flags);
3743                                 if (!np->in_shutdown)
3744                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3745                                 spin_unlock_irqrestore(&np->lock, flags);
3746                         }
3747                 }
3748
3749                 if (unlikely(i > max_interrupt_work)) {
3750                         spin_lock_irqsave(&np->lock, flags);
3751                         /* disable interrupts on the nic */
3752                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3753                         pci_push(base);
3754
3755                         if (!np->in_shutdown) {
3756                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3757                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3758                         }
3759                         spin_unlock_irqrestore(&np->lock, flags);
3760                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3761                         break;
3762                 }
3763         }
3764         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3765
3766         return IRQ_RETVAL(i);
3767 }
3768 #endif
3769
3770 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3771 {
3772         struct net_device *dev = (struct net_device *) data;
3773         struct fe_priv *np = netdev_priv(dev);
3774         u8 __iomem *base = get_hwbase(dev);
3775         u32 events;
3776         int i;
3777         unsigned long flags;
3778
3779         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3780
3781         for (i=0; ; i++) {
3782                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3783                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3784                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3785                 if (!(events & np->irqmask))
3786                         break;
3787
3788                 /* check tx in case we reached max loop limit in tx isr */
3789                 spin_lock_irqsave(&np->lock, flags);
3790                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3791                 spin_unlock_irqrestore(&np->lock, flags);
3792
3793                 if (events & NVREG_IRQ_LINK) {
3794                         spin_lock_irqsave(&np->lock, flags);
3795                         nv_link_irq(dev);
3796                         spin_unlock_irqrestore(&np->lock, flags);
3797                 }
3798                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3799                         spin_lock_irqsave(&np->lock, flags);
3800                         nv_linkchange(dev);
3801                         spin_unlock_irqrestore(&np->lock, flags);
3802                         np->link_timeout = jiffies + LINK_TIMEOUT;
3803                 }
3804                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3805                         spin_lock_irq(&np->lock);
3806                         /* disable interrupts on the nic */
3807                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3808                         pci_push(base);
3809
3810                         if (!np->in_shutdown) {
3811                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3812                                 np->recover_error = 1;
3813                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3814                         }
3815                         spin_unlock_irq(&np->lock);
3816                         break;
3817                 }
3818                 if (events & (NVREG_IRQ_UNKNOWN)) {
3819                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3820                                                 dev->name, events);
3821                 }
3822                 if (unlikely(i > max_interrupt_work)) {
3823                         spin_lock_irqsave(&np->lock, flags);
3824                         /* disable interrupts on the nic */
3825                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3826                         pci_push(base);
3827
3828                         if (!np->in_shutdown) {
3829                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3830                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3831                         }
3832                         spin_unlock_irqrestore(&np->lock, flags);
3833                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3834                         break;
3835                 }
3836
3837         }
3838         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3839
3840         return IRQ_RETVAL(i);
3841 }
3842
3843 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3844 {
3845         struct net_device *dev = (struct net_device *) data;
3846         struct fe_priv *np = netdev_priv(dev);
3847         u8 __iomem *base = get_hwbase(dev);
3848         u32 events;
3849
3850         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3851
3852         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3853                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3854                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3855         } else {
3856                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3857                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3858         }
3859         pci_push(base);
3860         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3861         if (!(events & NVREG_IRQ_TIMER))
3862                 return IRQ_RETVAL(0);
3863
3864         nv_msi_workaround(np);
3865
3866         spin_lock(&np->lock);
3867         np->intr_test = 1;
3868         spin_unlock(&np->lock);
3869
3870         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3871
3872         return IRQ_RETVAL(1);
3873 }
3874
3875 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3876 {
3877         u8 __iomem *base = get_hwbase(dev);
3878         int i;
3879         u32 msixmap = 0;
3880
3881         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3882          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3883          * the remaining 8 interrupts.
3884          */
3885         for (i = 0; i < 8; i++) {
3886                 if ((irqmask >> i) & 0x1) {
3887                         msixmap |= vector << (i << 2);
3888                 }
3889         }
3890         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3891
3892         msixmap = 0;
3893         for (i = 0; i < 8; i++) {
3894                 if ((irqmask >> (i + 8)) & 0x1) {
3895                         msixmap |= vector << (i << 2);
3896                 }
3897         }
3898         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3899 }
3900
3901 static int nv_request_irq(struct net_device *dev, int intr_test)
3902 {
3903         struct fe_priv *np = get_nvpriv(dev);
3904         u8 __iomem *base = get_hwbase(dev);
3905         int ret = 1;
3906         int i;
3907         irqreturn_t (*handler)(int foo, void *data);
3908
3909         if (intr_test) {
3910                 handler = nv_nic_irq_test;
3911         } else {
3912                 if (nv_optimized(np))
3913                         handler = nv_nic_irq_optimized;
3914                 else
3915                         handler = nv_nic_irq;
3916         }
3917
3918         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3919                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3920                         np->msi_x_entry[i].entry = i;
3921                 }
3922                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3923                         np->msi_flags |= NV_MSI_X_ENABLED;
3924                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3925                                 /* Request irq for rx handling */
3926                                 sprintf(np->name_rx, "%s-rx", dev->name);
3927                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3928                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3929                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3930                                         pci_disable_msix(np->pci_dev);
3931                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3932                                         goto out_err;
3933                                 }
3934                                 /* Request irq for tx handling */
3935                                 sprintf(np->name_tx, "%s-tx", dev->name);
3936                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3937                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3938                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3939                                         pci_disable_msix(np->pci_dev);
3940                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3941                                         goto out_free_rx;
3942                                 }
3943                                 /* Request irq for link and timer handling */
3944                                 sprintf(np->name_other, "%s-other", dev->name);
3945                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3946                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3947                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3948                                         pci_disable_msix(np->pci_dev);
3949                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3950                                         goto out_free_tx;
3951                                 }
3952                                 /* map interrupts to their respective vector */
3953                                 writel(0, base + NvRegMSIXMap0);
3954                                 writel(0, base + NvRegMSIXMap1);
3955                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3956                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3957                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3958                         } else {
3959                                 /* Request irq for all interrupts */
3960                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3961                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3962                                         pci_disable_msix(np->pci_dev);
3963                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3964                                         goto out_err;
3965                                 }
3966
3967                                 /* map interrupts to vector 0 */
3968                                 writel(0, base + NvRegMSIXMap0);
3969                                 writel(0, base + NvRegMSIXMap1);
3970                         }
3971                 }
3972         }
3973         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3974                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3975                         np->msi_flags |= NV_MSI_ENABLED;
3976                         dev->irq = np->pci_dev->irq;
3977                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3978                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3979                                 pci_disable_msi(np->pci_dev);
3980                                 np->msi_flags &= ~NV_MSI_ENABLED;
3981                                 dev->irq = np->pci_dev->irq;
3982                                 goto out_err;
3983                         }
3984
3985                         /* map interrupts to vector 0 */
3986                         writel(0, base + NvRegMSIMap0);
3987                         writel(0, base + NvRegMSIMap1);
3988                         /* enable msi vector 0 */
3989                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3990                 }
3991         }
3992         if (ret != 0) {
3993                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3994                         goto out_err;
3995
3996         }
3997
3998         return 0;
3999 out_free_tx:
4000         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4001 out_free_rx:
4002         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4003 out_err:
4004         return 1;
4005 }
4006
4007 static void nv_free_irq(struct net_device *dev)
4008 {
4009         struct fe_priv *np = get_nvpriv(dev);
4010         int i;
4011
4012         if (np->msi_flags & NV_MSI_X_ENABLED) {
4013                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4014                         free_irq(np->msi_x_entry[i].vector, dev);
4015                 }
4016                 pci_disable_msix(np->pci_dev);
4017                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4018         } else {
4019                 free_irq(np->pci_dev->irq, dev);
4020                 if (np->msi_flags & NV_MSI_ENABLED) {
4021                         pci_disable_msi(np->pci_dev);
4022                         np->msi_flags &= ~NV_MSI_ENABLED;
4023                 }
4024         }
4025 }
4026
4027 static void nv_do_nic_poll(unsigned long data)
4028 {
4029         struct net_device *dev = (struct net_device *) data;
4030         struct fe_priv *np = netdev_priv(dev);
4031         u8 __iomem *base = get_hwbase(dev);
4032         u32 mask = 0;
4033
4034         /*
4035          * First disable irq(s) and then
4036          * reenable interrupts on the nic, we have to do this before calling
4037          * nv_nic_irq because that may decide to do otherwise
4038          */
4039
4040         if (!using_multi_irqs(dev)) {
4041                 if (np->msi_flags & NV_MSI_X_ENABLED)
4042                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4043                 else
4044                         disable_irq_lockdep(np->pci_dev->irq);
4045                 mask = np->irqmask;
4046         } else {
4047                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4048                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4049                         mask |= NVREG_IRQ_RX_ALL;
4050                 }
4051                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4052                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4053                         mask |= NVREG_IRQ_TX_ALL;
4054                 }
4055                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4056                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4057                         mask |= NVREG_IRQ_OTHER;
4058                 }
4059         }
4060         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4061
4062         if (np->recover_error) {
4063                 np->recover_error = 0;
4064                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
4065                 if (netif_running(dev)) {
4066                         netif_tx_lock_bh(dev);
4067                         netif_addr_lock(dev);
4068                         spin_lock(&np->lock);
4069                         /* stop engines */
4070                         nv_stop_rxtx(dev);
4071                         nv_txrx_reset(dev);
4072                         /* drain rx queue */
4073                         nv_drain_rxtx(dev);
4074                         /* reinit driver view of the rx queue */
4075                         set_bufsize(dev);
4076                         if (nv_init_ring(dev)) {
4077                                 if (!np->in_shutdown)
4078                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4079                         }
4080                         /* reinit nic view of the rx queue */
4081                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4082                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4083                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4084                                 base + NvRegRingSizes);
4085                         pci_push(base);
4086                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4087                         pci_push(base);
4088
4089                         /* restart rx engine */
4090                         nv_start_rxtx(dev);
4091                         spin_unlock(&np->lock);
4092                         netif_addr_unlock(dev);
4093                         netif_tx_unlock_bh(dev);
4094                 }
4095         }
4096
4097         writel(mask, base + NvRegIrqMask);
4098         pci_push(base);
4099
4100         if (!using_multi_irqs(dev)) {
4101                 np->nic_poll_irq = 0;
4102                 if (nv_optimized(np))
4103                         nv_nic_irq_optimized(0, dev);
4104                 else
4105                         nv_nic_irq(0, dev);
4106                 if (np->msi_flags & NV_MSI_X_ENABLED)
4107                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4108                 else
4109                         enable_irq_lockdep(np->pci_dev->irq);
4110         } else {
4111                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4112                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4113                         nv_nic_irq_rx(0, dev);
4114                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4115                 }
4116                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4117                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4118                         nv_nic_irq_tx(0, dev);
4119                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4120                 }
4121                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4122                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4123                         nv_nic_irq_other(0, dev);
4124                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4125                 }
4126         }
4127
4128 }
4129
4130 #ifdef CONFIG_NET_POLL_CONTROLLER
4131 static void nv_poll_controller(struct net_device *dev)
4132 {
4133         nv_do_nic_poll((unsigned long) dev);
4134 }
4135 #endif
4136
4137 static void nv_do_stats_poll(unsigned long data)
4138 {
4139         struct net_device *dev = (struct net_device *) data;
4140         struct fe_priv *np = netdev_priv(dev);
4141
4142         nv_get_hw_stats(dev);
4143
4144         if (!np->in_shutdown)
4145                 mod_timer(&np->stats_poll,
4146                         round_jiffies(jiffies + STATS_INTERVAL));
4147 }
4148
4149 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4150 {
4151         struct fe_priv *np = netdev_priv(dev);
4152         strcpy(info->driver, DRV_NAME);
4153         strcpy(info->version, FORCEDETH_VERSION);
4154         strcpy(info->bus_info, pci_name(np->pci_dev));
4155 }
4156
4157 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4158 {
4159         struct fe_priv *np = netdev_priv(dev);
4160         wolinfo->supported = WAKE_MAGIC;
4161
4162         spin_lock_irq(&np->lock);
4163         if (np->wolenabled)
4164                 wolinfo->wolopts = WAKE_MAGIC;
4165         spin_unlock_irq(&np->lock);
4166 }
4167
4168 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4169 {
4170         struct fe_priv *np = netdev_priv(dev);
4171         u8 __iomem *base = get_hwbase(dev);
4172         u32 flags = 0;
4173
4174         if (wolinfo->wolopts == 0) {
4175                 np->wolenabled = 0;
4176         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4177                 np->wolenabled = 1;
4178                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4179         }
4180         if (netif_running(dev)) {
4181                 spin_lock_irq(&np->lock);
4182                 writel(flags, base + NvRegWakeUpFlags);
4183                 spin_unlock_irq(&np->lock);
4184         }
4185         return 0;
4186 }
4187
4188 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4189 {
4190         struct fe_priv *np = netdev_priv(dev);
4191         int adv;
4192
4193         spin_lock_irq(&np->lock);
4194         ecmd->port = PORT_MII;
4195         if (!netif_running(dev)) {
4196                 /* We do not track link speed / duplex setting if the
4197                  * interface is disabled. Force a link check */
4198                 if (nv_update_linkspeed(dev)) {
4199                         if (!netif_carrier_ok(dev))
4200                                 netif_carrier_on(dev);
4201                 } else {
4202                         if (netif_carrier_ok(dev))
4203                                 netif_carrier_off(dev);
4204                 }
4205         }
4206
4207         if (netif_carrier_ok(dev)) {
4208                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4209                 case NVREG_LINKSPEED_10:
4210                         ecmd->speed = SPEED_10;
4211                         break;
4212                 case NVREG_LINKSPEED_100:
4213                         ecmd->speed = SPEED_100;
4214                         break;
4215                 case NVREG_LINKSPEED_1000:
4216                         ecmd->speed = SPEED_1000;
4217                         break;
4218                 }
4219                 ecmd->duplex = DUPLEX_HALF;
4220                 if (np->duplex)
4221                         ecmd->duplex = DUPLEX_FULL;
4222         } else {
4223                 ecmd->speed = -1;
4224                 ecmd->duplex = -1;
4225         }
4226
4227         ecmd->autoneg = np->autoneg;
4228
4229         ecmd->advertising = ADVERTISED_MII;
4230         if (np->autoneg) {
4231                 ecmd->advertising |= ADVERTISED_Autoneg;
4232                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4233                 if (adv & ADVERTISE_10HALF)
4234                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4235                 if (adv & ADVERTISE_10FULL)
4236                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4237                 if (adv & ADVERTISE_100HALF)
4238                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4239                 if (adv & ADVERTISE_100FULL)
4240                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4241                 if (np->gigabit == PHY_GIGABIT) {
4242                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4243                         if (adv & ADVERTISE_1000FULL)
4244                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4245                 }
4246         }
4247         ecmd->supported = (SUPPORTED_Autoneg |
4248                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4249                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4250                 SUPPORTED_MII);
4251         if (np->gigabit == PHY_GIGABIT)
4252                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4253
4254         ecmd->phy_address = np->phyaddr;
4255         ecmd->transceiver = XCVR_EXTERNAL;
4256
4257         /* ignore maxtxpkt, maxrxpkt for now */
4258         spin_unlock_irq(&np->lock);
4259         return 0;
4260 }
4261
4262 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4263 {
4264         struct fe_priv *np = netdev_priv(dev);
4265
4266         if (ecmd->port != PORT_MII)
4267                 return -EINVAL;
4268         if (ecmd->transceiver != XCVR_EXTERNAL)
4269                 return -EINVAL;
4270         if (ecmd->phy_address != np->phyaddr) {
4271                 /* TODO: support switching between multiple phys. Should be
4272                  * trivial, but not enabled due to lack of test hardware. */
4273                 return -EINVAL;
4274         }
4275         if (ecmd->autoneg == AUTONEG_ENABLE) {
4276                 u32 mask;
4277
4278                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4279                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4280                 if (np->gigabit == PHY_GIGABIT)
4281                         mask |= ADVERTISED_1000baseT_Full;
4282
4283                 if ((ecmd->advertising & mask) == 0)
4284                         return -EINVAL;
4285
4286         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4287                 /* Note: autonegotiation disable, speed 1000 intentionally
4288                  * forbidden - noone should need that. */
4289
4290                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4291                         return -EINVAL;
4292                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4293                         return -EINVAL;
4294         } else {
4295                 return -EINVAL;
4296         }
4297
4298         netif_carrier_off(dev);
4299         if (netif_running(dev)) {
4300                 unsigned long flags;
4301
4302                 nv_disable_irq(dev);
4303                 netif_tx_lock_bh(dev);
4304                 netif_addr_lock(dev);
4305                 /* with plain spinlock lockdep complains */
4306                 spin_lock_irqsave(&np->lock, flags);
4307                 /* stop engines */
4308                 /* FIXME:
4309                  * this can take some time, and interrupts are disabled
4310                  * due to spin_lock_irqsave, but let's hope no daemon
4311                  * is going to change the settings very often...
4312                  * Worst case:
4313                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4314                  * + some minor delays, which is up to a second approximately
4315                  */
4316                 nv_stop_rxtx(dev);
4317                 spin_unlock_irqrestore(&np->lock, flags);
4318                 netif_addr_unlock(dev);
4319                 netif_tx_unlock_bh(dev);
4320         }
4321
4322         if (ecmd->autoneg == AUTONEG_ENABLE) {
4323                 int adv, bmcr;
4324
4325                 np->autoneg = 1;
4326
4327                 /* advertise only what has been requested */
4328                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4329                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4330                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4331                         adv |= ADVERTISE_10HALF;
4332                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4333                         adv |= ADVERTISE_10FULL;
4334                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4335                         adv |= ADVERTISE_100HALF;
4336                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4337                         adv |= ADVERTISE_100FULL;
4338                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4339                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4340                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4341                         adv |=  ADVERTISE_PAUSE_ASYM;
4342                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4343
4344                 if (np->gigabit == PHY_GIGABIT) {
4345                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4346                         adv &= ~ADVERTISE_1000FULL;
4347                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4348                                 adv |= ADVERTISE_1000FULL;
4349                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4350                 }
4351
4352                 if (netif_running(dev))
4353                         printk(KERN_INFO "%s: link down.\n", dev->name);
4354                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4355                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4356                         bmcr |= BMCR_ANENABLE;
4357                         /* reset the phy in order for settings to stick,
4358                          * and cause autoneg to start */
4359                         if (phy_reset(dev, bmcr)) {
4360                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4361                                 return -EINVAL;
4362                         }
4363                 } else {
4364                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4365                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4366                 }
4367         } else {
4368                 int adv, bmcr;
4369
4370                 np->autoneg = 0;
4371
4372                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4373                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4374                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4375                         adv |= ADVERTISE_10HALF;
4376                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4377                         adv |= ADVERTISE_10FULL;
4378                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4379                         adv |= ADVERTISE_100HALF;
4380                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4381                         adv |= ADVERTISE_100FULL;
4382                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4383                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4384                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4385                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4386                 }
4387                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4388                         adv |=  ADVERTISE_PAUSE_ASYM;
4389                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4390                 }
4391                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4392                 np->fixed_mode = adv;
4393
4394                 if (np->gigabit == PHY_GIGABIT) {
4395                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4396                         adv &= ~ADVERTISE_1000FULL;
4397                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4398                 }
4399
4400                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4401                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4402                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4403                         bmcr |= BMCR_FULLDPLX;
4404                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4405                         bmcr |= BMCR_SPEED100;
4406                 if (np->phy_oui == PHY_OUI_MARVELL) {
4407                         /* reset the phy in order for forced mode settings to stick */
4408                         if (phy_reset(dev, bmcr)) {
4409                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4410                                 return -EINVAL;
4411                         }
4412                 } else {
4413                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4414                         if (netif_running(dev)) {
4415                                 /* Wait a bit and then reconfigure the nic. */
4416                                 udelay(10);
4417                                 nv_linkchange(dev);
4418                         }
4419                 }
4420         }
4421
4422         if (netif_running(dev)) {
4423                 nv_start_rxtx(dev);
4424                 nv_enable_irq(dev);
4425         }
4426
4427         return 0;
4428 }
4429
4430 #define FORCEDETH_REGS_VER      1
4431
4432 static int nv_get_regs_len(struct net_device *dev)
4433 {
4434         struct fe_priv *np = netdev_priv(dev);
4435         return np->register_size;
4436 }
4437
4438 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4439 {
4440         struct fe_priv *np = netdev_priv(dev);
4441         u8 __iomem *base = get_hwbase(dev);
4442         u32 *rbuf = buf;
4443         int i;
4444
4445         regs->version = FORCEDETH_REGS_VER;
4446         spin_lock_irq(&np->lock);
4447         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4448                 rbuf[i] = readl(base + i*sizeof(u32));
4449         spin_unlock_irq(&np->lock);
4450 }
4451
4452 static int nv_nway_reset(struct net_device *dev)
4453 {
4454         struct fe_priv *np = netdev_priv(dev);
4455         int ret;
4456
4457         if (np->autoneg) {
4458                 int bmcr;
4459
4460                 netif_carrier_off(dev);
4461                 if (netif_running(dev)) {
4462                         nv_disable_irq(dev);
4463                         netif_tx_lock_bh(dev);
4464                         netif_addr_lock(dev);
4465                         spin_lock(&np->lock);
4466                         /* stop engines */
4467                         nv_stop_rxtx(dev);
4468                         spin_unlock(&np->lock);
4469                         netif_addr_unlock(dev);
4470                         netif_tx_unlock_bh(dev);
4471                         printk(KERN_INFO "%s: link down.\n", dev->name);
4472                 }
4473
4474                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4475                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4476                         bmcr |= BMCR_ANENABLE;
4477                         /* reset the phy in order for settings to stick*/
4478                         if (phy_reset(dev, bmcr)) {
4479                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4480                                 return -EINVAL;
4481                         }
4482                 } else {
4483                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4484                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4485                 }
4486
4487                 if (netif_running(dev)) {
4488                         nv_start_rxtx(dev);
4489                         nv_enable_irq(dev);
4490                 }
4491                 ret = 0;
4492         } else {
4493                 ret = -EINVAL;
4494         }
4495
4496         return ret;
4497 }
4498
4499 static int nv_set_tso(struct net_device *dev, u32 value)
4500 {
4501         struct fe_priv *np = netdev_priv(dev);
4502
4503         if ((np->driver_data & DEV_HAS_CHECKSUM))
4504                 return ethtool_op_set_tso(dev, value);
4505         else
4506                 return -EOPNOTSUPP;
4507 }
4508
4509 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4510 {
4511         struct fe_priv *np = netdev_priv(dev);
4512
4513         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4514         ring->rx_mini_max_pending = 0;
4515         ring->rx_jumbo_max_pending = 0;
4516         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4517
4518         ring->rx_pending = np->rx_ring_size;
4519         ring->rx_mini_pending = 0;
4520         ring->rx_jumbo_pending = 0;
4521         ring->tx_pending = np->tx_ring_size;
4522 }
4523
4524 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4525 {
4526         struct fe_priv *np = netdev_priv(dev);
4527         u8 __iomem *base = get_hwbase(dev);
4528         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4529         dma_addr_t ring_addr;
4530
4531         if (ring->rx_pending < RX_RING_MIN ||
4532             ring->tx_pending < TX_RING_MIN ||
4533             ring->rx_mini_pending != 0 ||
4534             ring->rx_jumbo_pending != 0 ||
4535             (np->desc_ver == DESC_VER_1 &&
4536              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4537               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4538             (np->desc_ver != DESC_VER_1 &&
4539              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4540               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4541                 return -EINVAL;
4542         }
4543
4544         /* allocate new rings */
4545         if (!nv_optimized(np)) {
4546                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4547                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4548                                             &ring_addr);
4549         } else {
4550                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4551                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4552                                             &ring_addr);
4553         }
4554         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4555         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4556         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4557                 /* fall back to old rings */
4558                 if (!nv_optimized(np)) {
4559                         if (rxtx_ring)
4560                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4561                                                     rxtx_ring, ring_addr);
4562                 } else {
4563                         if (rxtx_ring)
4564                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4565                                                     rxtx_ring, ring_addr);
4566                 }
4567                 if (rx_skbuff)
4568                         kfree(rx_skbuff);
4569                 if (tx_skbuff)
4570                         kfree(tx_skbuff);
4571                 goto exit;
4572         }
4573
4574         if (netif_running(dev)) {
4575                 nv_disable_irq(dev);
4576                 netif_tx_lock_bh(dev);
4577                 netif_addr_lock(dev);
4578                 spin_lock(&np->lock);
4579                 /* stop engines */
4580                 nv_stop_rxtx(dev);
4581                 nv_txrx_reset(dev);
4582                 /* drain queues */
4583                 nv_drain_rxtx(dev);
4584                 /* delete queues */
4585                 free_rings(dev);
4586         }
4587
4588         /* set new values */
4589         np->rx_ring_size = ring->rx_pending;
4590         np->tx_ring_size = ring->tx_pending;
4591
4592         if (!nv_optimized(np)) {
4593                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4594                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4595         } else {
4596                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4597                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4598         }
4599         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4600         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4601         np->ring_addr = ring_addr;
4602
4603         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4604         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4605
4606         if (netif_running(dev)) {
4607                 /* reinit driver view of the queues */
4608                 set_bufsize(dev);
4609                 if (nv_init_ring(dev)) {
4610                         if (!np->in_shutdown)
4611                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4612                 }
4613
4614                 /* reinit nic view of the queues */
4615                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4616                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4617                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4618                         base + NvRegRingSizes);
4619                 pci_push(base);
4620                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4621                 pci_push(base);
4622
4623                 /* restart engines */
4624                 nv_start_rxtx(dev);
4625                 spin_unlock(&np->lock);
4626                 netif_addr_unlock(dev);
4627                 netif_tx_unlock_bh(dev);
4628                 nv_enable_irq(dev);
4629         }
4630         return 0;
4631 exit:
4632         return -ENOMEM;
4633 }
4634
4635 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4636 {
4637         struct fe_priv *np = netdev_priv(dev);
4638
4639         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4640         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4641         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4642 }
4643
4644 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4645 {
4646         struct fe_priv *np = netdev_priv(dev);
4647         int adv, bmcr;
4648
4649         if ((!np->autoneg && np->duplex == 0) ||
4650             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4651                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4652                        dev->name);
4653                 return -EINVAL;
4654         }
4655         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4656                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4657                 return -EINVAL;
4658         }
4659
4660         netif_carrier_off(dev);
4661         if (netif_running(dev)) {
4662                 nv_disable_irq(dev);
4663                 netif_tx_lock_bh(dev);
4664                 netif_addr_lock(dev);
4665                 spin_lock(&np->lock);
4666                 /* stop engines */
4667                 nv_stop_rxtx(dev);
4668                 spin_unlock(&np->lock);
4669                 netif_addr_unlock(dev);
4670                 netif_tx_unlock_bh(dev);
4671         }
4672
4673         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4674         if (pause->rx_pause)
4675                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4676         if (pause->tx_pause)
4677                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4678
4679         if (np->autoneg && pause->autoneg) {
4680                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4681
4682                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4683                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4684                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4685                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4686                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4687                         adv |=  ADVERTISE_PAUSE_ASYM;
4688                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4689
4690                 if (netif_running(dev))
4691                         printk(KERN_INFO "%s: link down.\n", dev->name);
4692                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4693                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4694                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4695         } else {
4696                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4697                 if (pause->rx_pause)
4698                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4699                 if (pause->tx_pause)
4700                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4701
4702                 if (!netif_running(dev))
4703                         nv_update_linkspeed(dev);
4704                 else
4705                         nv_update_pause(dev, np->pause_flags);
4706         }
4707
4708         if (netif_running(dev)) {
4709                 nv_start_rxtx(dev);
4710                 nv_enable_irq(dev);
4711         }
4712         return 0;
4713 }
4714
4715 static u32 nv_get_rx_csum(struct net_device *dev)
4716 {
4717         struct fe_priv *np = netdev_priv(dev);
4718         return (np->rx_csum) != 0;
4719 }
4720
4721 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4722 {
4723         struct fe_priv *np = netdev_priv(dev);
4724         u8 __iomem *base = get_hwbase(dev);
4725         int retcode = 0;
4726
4727         if (np->driver_data & DEV_HAS_CHECKSUM) {
4728                 if (data) {
4729                         np->rx_csum = 1;
4730                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4731                 } else {
4732                         np->rx_csum = 0;
4733                         /* vlan is dependent on rx checksum offload */
4734                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4735                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4736                 }
4737                 if (netif_running(dev)) {
4738                         spin_lock_irq(&np->lock);
4739                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4740                         spin_unlock_irq(&np->lock);
4741                 }
4742         } else {
4743                 return -EINVAL;
4744         }
4745
4746         return retcode;
4747 }
4748
4749 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4750 {
4751         struct fe_priv *np = netdev_priv(dev);
4752
4753         if (np->driver_data & DEV_HAS_CHECKSUM)
4754                 return ethtool_op_set_tx_hw_csum(dev, data);
4755         else
4756                 return -EOPNOTSUPP;
4757 }
4758
4759 static int nv_set_sg(struct net_device *dev, u32 data)
4760 {
4761         struct fe_priv *np = netdev_priv(dev);
4762
4763         if (np->driver_data & DEV_HAS_CHECKSUM)
4764                 return ethtool_op_set_sg(dev, data);
4765         else
4766                 return -EOPNOTSUPP;
4767 }
4768
4769 static int nv_get_sset_count(struct net_device *dev, int sset)
4770 {
4771         struct fe_priv *np = netdev_priv(dev);
4772
4773         switch (sset) {
4774         case ETH_SS_TEST:
4775                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4776                         return NV_TEST_COUNT_EXTENDED;
4777                 else
4778                         return NV_TEST_COUNT_BASE;
4779         case ETH_SS_STATS:
4780                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4781                         return NV_DEV_STATISTICS_V1_COUNT;
4782                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4783                         return NV_DEV_STATISTICS_V2_COUNT;
4784                 else if (np->driver_data & DEV_HAS_STATISTICS_V3)
4785                         return NV_DEV_STATISTICS_V3_COUNT;
4786                 else
4787                         return 0;
4788         default:
4789                 return -EOPNOTSUPP;
4790         }
4791 }
4792
4793 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4794 {
4795         struct fe_priv *np = netdev_priv(dev);
4796
4797         /* update stats */
4798         nv_do_stats_poll((unsigned long)dev);
4799
4800         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4801 }
4802
4803 static int nv_link_test(struct net_device *dev)
4804 {
4805         struct fe_priv *np = netdev_priv(dev);
4806         int mii_status;
4807
4808         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4809         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4810
4811         /* check phy link status */
4812         if (!(mii_status & BMSR_LSTATUS))
4813                 return 0;
4814         else
4815                 return 1;
4816 }
4817
4818 static int nv_register_test(struct net_device *dev)
4819 {
4820         u8 __iomem *base = get_hwbase(dev);
4821         int i = 0;
4822         u32 orig_read, new_read;
4823
4824         do {
4825                 orig_read = readl(base + nv_registers_test[i].reg);
4826
4827                 /* xor with mask to toggle bits */
4828                 orig_read ^= nv_registers_test[i].mask;
4829
4830                 writel(orig_read, base + nv_registers_test[i].reg);
4831
4832                 new_read = readl(base + nv_registers_test[i].reg);
4833
4834                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4835                         return 0;
4836
4837                 /* restore original value */
4838                 orig_read ^= nv_registers_test[i].mask;
4839                 writel(orig_read, base + nv_registers_test[i].reg);
4840
4841         } while (nv_registers_test[++i].reg != 0);
4842
4843         return 1;
4844 }
4845
4846 static int nv_interrupt_test(struct net_device *dev)
4847 {
4848         struct fe_priv *np = netdev_priv(dev);
4849         u8 __iomem *base = get_hwbase(dev);
4850         int ret = 1;
4851         int testcnt;
4852         u32 save_msi_flags, save_poll_interval = 0;
4853
4854         if (netif_running(dev)) {
4855                 /* free current irq */
4856                 nv_free_irq(dev);
4857                 save_poll_interval = readl(base+NvRegPollingInterval);
4858         }
4859
4860         /* flag to test interrupt handler */
4861         np->intr_test = 0;
4862
4863         /* setup test irq */
4864         save_msi_flags = np->msi_flags;
4865         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4866         np->msi_flags |= 0x001; /* setup 1 vector */
4867         if (nv_request_irq(dev, 1))
4868                 return 0;
4869
4870         /* setup timer interrupt */
4871         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4872         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4873
4874         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4875
4876         /* wait for at least one interrupt */
4877         msleep(100);
4878
4879         spin_lock_irq(&np->lock);
4880
4881         /* flag should be set within ISR */
4882         testcnt = np->intr_test;
4883         if (!testcnt)
4884                 ret = 2;
4885
4886         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4887         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4888                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4889         else
4890                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4891
4892         spin_unlock_irq(&np->lock);
4893
4894         nv_free_irq(dev);
4895
4896         np->msi_flags = save_msi_flags;
4897
4898         if (netif_running(dev)) {
4899                 writel(save_poll_interval, base + NvRegPollingInterval);
4900                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4901                 /* restore original irq */
4902                 if (nv_request_irq(dev, 0))
4903                         return 0;
4904         }
4905
4906         return ret;
4907 }
4908
4909 static int nv_loopback_test(struct net_device *dev)
4910 {
4911         struct fe_priv *np = netdev_priv(dev);
4912         u8 __iomem *base = get_hwbase(dev);
4913         struct sk_buff *tx_skb, *rx_skb;
4914         dma_addr_t test_dma_addr;
4915         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4916         u32 flags;
4917         int len, i, pkt_len;
4918         u8 *pkt_data;
4919         u32 filter_flags = 0;
4920         u32 misc1_flags = 0;
4921         int ret = 1;
4922
4923         if (netif_running(dev)) {
4924                 nv_disable_irq(dev);
4925                 filter_flags = readl(base + NvRegPacketFilterFlags);
4926                 misc1_flags = readl(base + NvRegMisc1);
4927         } else {
4928                 nv_txrx_reset(dev);
4929         }
4930
4931         /* reinit driver view of the rx queue */
4932         set_bufsize(dev);
4933         nv_init_ring(dev);
4934
4935         /* setup hardware for loopback */
4936         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4937         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4938
4939         /* reinit nic view of the rx queue */
4940         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4941         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4942         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4943                 base + NvRegRingSizes);
4944         pci_push(base);
4945
4946         /* restart rx engine */
4947         nv_start_rxtx(dev);
4948
4949         /* setup packet for tx */
4950         pkt_len = ETH_DATA_LEN;
4951         tx_skb = dev_alloc_skb(pkt_len);
4952         if (!tx_skb) {
4953                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4954                          " of %s\n", dev->name);
4955                 ret = 0;
4956                 goto out;
4957         }
4958         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4959                                        skb_tailroom(tx_skb),
4960                                        PCI_DMA_FROMDEVICE);
4961         pkt_data = skb_put(tx_skb, pkt_len);
4962         for (i = 0; i < pkt_len; i++)
4963                 pkt_data[i] = (u8)(i & 0xff);
4964
4965         if (!nv_optimized(np)) {
4966                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4967                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4968         } else {
4969                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4970                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4971                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4972         }
4973         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4974         pci_push(get_hwbase(dev));
4975
4976         msleep(500);
4977
4978         /* check for rx of the packet */
4979         if (!nv_optimized(np)) {
4980                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4981                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4982
4983         } else {
4984                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4985                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4986         }
4987
4988         if (flags & NV_RX_AVAIL) {
4989                 ret = 0;
4990         } else if (np->desc_ver == DESC_VER_1) {
4991                 if (flags & NV_RX_ERROR)
4992                         ret = 0;
4993         } else {
4994                 if (flags & NV_RX2_ERROR) {
4995                         ret = 0;
4996                 }
4997         }
4998
4999         if (ret) {
5000                 if (len != pkt_len) {
5001                         ret = 0;
5002                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5003                                 dev->name, len, pkt_len);
5004                 } else {
5005                         rx_skb = np->rx_skb[0].skb;
5006                         for (i = 0; i < pkt_len; i++) {
5007                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5008                                         ret = 0;
5009                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5010                                                 dev->name, i);
5011                                         break;
5012                                 }
5013                         }
5014                 }
5015         } else {
5016                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5017         }
5018
5019         pci_unmap_page(np->pci_dev, test_dma_addr,
5020                        (skb_end_pointer(tx_skb) - tx_skb->data),
5021                        PCI_DMA_TODEVICE);
5022         dev_kfree_skb_any(tx_skb);
5023  out:
5024         /* stop engines */
5025         nv_stop_rxtx(dev);
5026         nv_txrx_reset(dev);
5027         /* drain rx queue */
5028         nv_drain_rxtx(dev);
5029
5030         if (netif_running(dev)) {
5031                 writel(misc1_flags, base + NvRegMisc1);
5032                 writel(filter_flags, base + NvRegPacketFilterFlags);
5033                 nv_enable_irq(dev);
5034         }
5035
5036         return ret;
5037 }
5038
5039 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5040 {
5041         struct fe_priv *np = netdev_priv(dev);
5042         u8 __iomem *base = get_hwbase(dev);
5043         int result;
5044         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5045
5046         if (!nv_link_test(dev)) {
5047                 test->flags |= ETH_TEST_FL_FAILED;
5048                 buffer[0] = 1;
5049         }
5050
5051         if (test->flags & ETH_TEST_FL_OFFLINE) {
5052                 if (netif_running(dev)) {
5053                         netif_stop_queue(dev);
5054 #ifdef CONFIG_FORCEDETH_NAPI
5055                         napi_disable(&np->napi);
5056 #endif
5057                         netif_tx_lock_bh(dev);
5058                         netif_addr_lock(dev);
5059                         spin_lock_irq(&np->lock);
5060                         nv_disable_hw_interrupts(dev, np->irqmask);
5061                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5062                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5063                         } else {
5064                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5065                         }
5066                         /* stop engines */
5067                         nv_stop_rxtx(dev);
5068                         nv_txrx_reset(dev);
5069                         /* drain rx queue */
5070                         nv_drain_rxtx(dev);
5071                         spin_unlock_irq(&np->lock);
5072                         netif_addr_unlock(dev);
5073                         netif_tx_unlock_bh(dev);
5074                 }
5075
5076                 if (!nv_register_test(dev)) {
5077                         test->flags |= ETH_TEST_FL_FAILED;
5078                         buffer[1] = 1;
5079                 }
5080
5081                 result = nv_interrupt_test(dev);
5082                 if (result != 1) {
5083                         test->flags |= ETH_TEST_FL_FAILED;
5084                         buffer[2] = 1;
5085                 }
5086                 if (result == 0) {
5087                         /* bail out */
5088                         return;
5089                 }
5090
5091                 if (!nv_loopback_test(dev)) {
5092                         test->flags |= ETH_TEST_FL_FAILED;
5093                         buffer[3] = 1;
5094                 }
5095
5096                 if (netif_running(dev)) {
5097                         /* reinit driver view of the rx queue */
5098                         set_bufsize(dev);
5099                         if (nv_init_ring(dev)) {
5100                                 if (!np->in_shutdown)
5101                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5102                         }
5103                         /* reinit nic view of the rx queue */
5104                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5105                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5106                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5107                                 base + NvRegRingSizes);
5108                         pci_push(base);
5109                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5110                         pci_push(base);
5111                         /* restart rx engine */
5112                         nv_start_rxtx(dev);
5113                         netif_start_queue(dev);
5114 #ifdef CONFIG_FORCEDETH_NAPI
5115                         napi_enable(&np->napi);
5116 #endif
5117                         nv_enable_hw_interrupts(dev, np->irqmask);
5118                 }
5119         }
5120 }
5121
5122 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5123 {
5124         switch (stringset) {
5125         case ETH_SS_STATS:
5126                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5127                 break;
5128         case ETH_SS_TEST:
5129                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5130                 break;
5131         }
5132 }
5133
5134 static const struct ethtool_ops ops = {
5135         .get_drvinfo = nv_get_drvinfo,
5136         .get_link = ethtool_op_get_link,
5137         .get_wol = nv_get_wol,
5138         .set_wol = nv_set_wol,
5139         .get_settings = nv_get_settings,
5140         .set_settings = nv_set_settings,
5141         .get_regs_len = nv_get_regs_len,
5142         .get_regs = nv_get_regs,
5143         .nway_reset = nv_nway_reset,
5144         .set_tso = nv_set_tso,
5145         .get_ringparam = nv_get_ringparam,
5146         .set_ringparam = nv_set_ringparam,
5147         .get_pauseparam = nv_get_pauseparam,
5148         .set_pauseparam = nv_set_pauseparam,
5149         .get_rx_csum = nv_get_rx_csum,
5150         .set_rx_csum = nv_set_rx_csum,
5151         .set_tx_csum = nv_set_tx_csum,
5152         .set_sg = nv_set_sg,
5153         .get_strings = nv_get_strings,
5154         .get_ethtool_stats = nv_get_ethtool_stats,
5155         .get_sset_count = nv_get_sset_count,
5156         .self_test = nv_self_test,
5157 };
5158
5159 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5160 {
5161         struct fe_priv *np = get_nvpriv(dev);
5162
5163         spin_lock_irq(&np->lock);
5164
5165         /* save vlan group */
5166         np->vlangrp = grp;
5167
5168         if (grp) {
5169                 /* enable vlan on MAC */
5170                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5171         } else {
5172                 /* disable vlan on MAC */
5173                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5174                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5175         }
5176
5177         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5178
5179         spin_unlock_irq(&np->lock);
5180 }
5181
5182 /* The mgmt unit and driver use a semaphore to access the phy during init */
5183 static int nv_mgmt_acquire_sema(struct net_device *dev)
5184 {
5185         u8 __iomem *base = get_hwbase(dev);
5186         int i;
5187         u32 tx_ctrl, mgmt_sema;
5188
5189         for (i = 0; i < 10; i++) {
5190                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5191                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5192                         break;
5193                 msleep(500);
5194         }
5195
5196         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5197                 return 0;
5198
5199         for (i = 0; i < 2; i++) {
5200                 tx_ctrl = readl(base + NvRegTransmitterControl);
5201                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5202                 writel(tx_ctrl, base + NvRegTransmitterControl);
5203
5204                 /* verify that semaphore was acquired */
5205                 tx_ctrl = readl(base + NvRegTransmitterControl);
5206                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5207                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5208                         return 1;
5209                 else
5210                         udelay(50);
5211         }
5212
5213         return 0;
5214 }
5215
5216 static int nv_open(struct net_device *dev)
5217 {
5218         struct fe_priv *np = netdev_priv(dev);
5219         u8 __iomem *base = get_hwbase(dev);
5220         int ret = 1;
5221         int oom, i;
5222         u32 low;
5223
5224         dprintk(KERN_DEBUG "nv_open: begin\n");
5225
5226         /* power up phy */
5227         mii_rw(dev, np->phyaddr, MII_BMCR,
5228                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5229
5230         /* erase previous misconfiguration */
5231         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5232                 nv_mac_reset(dev);
5233         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5234         writel(0, base + NvRegMulticastAddrB);
5235         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5236         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5237         writel(0, base + NvRegPacketFilterFlags);
5238
5239         writel(0, base + NvRegTransmitterControl);
5240         writel(0, base + NvRegReceiverControl);
5241
5242         writel(0, base + NvRegAdapterControl);
5243
5244         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5245                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5246
5247         /* initialize descriptor rings */
5248         set_bufsize(dev);
5249         oom = nv_init_ring(dev);
5250
5251         writel(0, base + NvRegLinkSpeed);
5252         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5253         nv_txrx_reset(dev);
5254         writel(0, base + NvRegUnknownSetupReg6);
5255
5256         np->in_shutdown = 0;
5257
5258         /* give hw rings */
5259         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5260         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5261                 base + NvRegRingSizes);
5262
5263         writel(np->linkspeed, base + NvRegLinkSpeed);
5264         if (np->desc_ver == DESC_VER_1)
5265                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5266         else
5267                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5268         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5269         writel(np->vlanctl_bits, base + NvRegVlanControl);
5270         pci_push(base);
5271         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5272         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5273                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5274                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5275
5276         writel(0, base + NvRegMIIMask);
5277         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5278         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5279
5280         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5281         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5282         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5283         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5284
5285         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5286
5287         get_random_bytes(&low, sizeof(low));
5288         low &= NVREG_SLOTTIME_MASK;
5289         if (np->desc_ver == DESC_VER_1) {
5290                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5291         } else {
5292                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5293                         /* setup legacy backoff */
5294                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5295                 } else {
5296                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5297                         nv_gear_backoff_reseed(dev);
5298                 }
5299         }
5300         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5301         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5302         if (poll_interval == -1) {
5303                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5304                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5305                 else
5306                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5307         }
5308         else
5309                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5310         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5311         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5312                         base + NvRegAdapterControl);
5313         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5314         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5315         if (np->wolenabled)
5316                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5317
5318         i = readl(base + NvRegPowerState);
5319         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5320                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5321
5322         pci_push(base);
5323         udelay(10);
5324         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5325
5326         nv_disable_hw_interrupts(dev, np->irqmask);
5327         pci_push(base);
5328         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5329         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5330         pci_push(base);
5331
5332         if (nv_request_irq(dev, 0)) {
5333                 goto out_drain;
5334         }
5335
5336         /* ask for interrupts */
5337         nv_enable_hw_interrupts(dev, np->irqmask);
5338
5339         spin_lock_irq(&np->lock);
5340         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5341         writel(0, base + NvRegMulticastAddrB);
5342         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5343         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5344         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5345         /* One manual link speed update: Interrupts are enabled, future link
5346          * speed changes cause interrupts and are handled by nv_link_irq().
5347          */
5348         {
5349                 u32 miistat;
5350                 miistat = readl(base + NvRegMIIStatus);
5351                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5352                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5353         }
5354         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5355          * to init hw */
5356         np->linkspeed = 0;
5357         ret = nv_update_linkspeed(dev);
5358         nv_start_rxtx(dev);
5359         netif_start_queue(dev);
5360 #ifdef CONFIG_FORCEDETH_NAPI
5361         napi_enable(&np->napi);
5362 #endif
5363
5364         if (ret) {
5365                 netif_carrier_on(dev);
5366         } else {
5367                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5368                 netif_carrier_off(dev);
5369         }
5370         if (oom)
5371                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5372
5373         /* start statistics timer */
5374         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5375                 mod_timer(&np->stats_poll,
5376                         round_jiffies(jiffies + STATS_INTERVAL));
5377
5378         spin_unlock_irq(&np->lock);
5379
5380         return 0;
5381 out_drain:
5382         nv_drain_rxtx(dev);
5383         return ret;
5384 }
5385
5386 static int nv_close(struct net_device *dev)
5387 {
5388         struct fe_priv *np = netdev_priv(dev);
5389         u8 __iomem *base;
5390
5391         spin_lock_irq(&np->lock);
5392         np->in_shutdown = 1;
5393         spin_unlock_irq(&np->lock);
5394 #ifdef CONFIG_FORCEDETH_NAPI
5395         napi_disable(&np->napi);
5396 #endif
5397         synchronize_irq(np->pci_dev->irq);
5398
5399         del_timer_sync(&np->oom_kick);
5400         del_timer_sync(&np->nic_poll);
5401         del_timer_sync(&np->stats_poll);
5402
5403         netif_stop_queue(dev);
5404         spin_lock_irq(&np->lock);
5405         nv_stop_rxtx(dev);
5406         nv_txrx_reset(dev);
5407
5408         /* disable interrupts on the nic or we will lock up */
5409         base = get_hwbase(dev);
5410         nv_disable_hw_interrupts(dev, np->irqmask);
5411         pci_push(base);
5412         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5413
5414         spin_unlock_irq(&np->lock);
5415
5416         nv_free_irq(dev);
5417
5418         nv_drain_rxtx(dev);
5419
5420         if (np->wolenabled) {
5421                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5422                 nv_start_rx(dev);
5423         } else {
5424                 /* power down phy */
5425                 mii_rw(dev, np->phyaddr, MII_BMCR,
5426                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5427         }
5428
5429         /* FIXME: power down nic */
5430
5431         return 0;
5432 }
5433
5434 static const struct net_device_ops nv_netdev_ops = {
5435         .ndo_open               = nv_open,
5436         .ndo_stop               = nv_close,
5437         .ndo_get_stats          = nv_get_stats,
5438         .ndo_start_xmit         = nv_start_xmit,
5439         .ndo_tx_timeout         = nv_tx_timeout,
5440         .ndo_change_mtu         = nv_change_mtu,
5441         .ndo_validate_addr      = eth_validate_addr,
5442         .ndo_set_mac_address    = nv_set_mac_address,
5443         .ndo_set_multicast_list = nv_set_multicast,
5444         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5445 #ifdef CONFIG_NET_POLL_CONTROLLER
5446         .ndo_poll_controller    = nv_poll_controller,
5447 #endif
5448 };
5449
5450 static const struct net_device_ops nv_netdev_ops_optimized = {
5451         .ndo_open               = nv_open,
5452         .ndo_stop               = nv_close,
5453         .ndo_get_stats          = nv_get_stats,
5454         .ndo_start_xmit         = nv_start_xmit_optimized,
5455         .ndo_tx_timeout         = nv_tx_timeout,
5456         .ndo_change_mtu         = nv_change_mtu,
5457         .ndo_validate_addr      = eth_validate_addr,
5458         .ndo_set_mac_address    = nv_set_mac_address,
5459         .ndo_set_multicast_list = nv_set_multicast,
5460         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5461 #ifdef CONFIG_NET_POLL_CONTROLLER
5462         .ndo_poll_controller    = nv_poll_controller,
5463 #endif
5464 };
5465
5466 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5467 {
5468         struct net_device *dev;
5469         struct fe_priv *np;
5470         unsigned long addr;
5471         u8 __iomem *base;
5472         int err, i;
5473         u32 powerstate, txreg;
5474         u32 phystate_orig = 0, phystate;
5475         int phyinitialized = 0;
5476         static int printed_version;
5477
5478         if (!printed_version++)
5479                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5480                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5481
5482         dev = alloc_etherdev(sizeof(struct fe_priv));
5483         err = -ENOMEM;
5484         if (!dev)
5485                 goto out;
5486
5487         np = netdev_priv(dev);
5488         np->dev = dev;
5489         np->pci_dev = pci_dev;
5490         spin_lock_init(&np->lock);
5491         SET_NETDEV_DEV(dev, &pci_dev->dev);
5492
5493         init_timer(&np->oom_kick);
5494         np->oom_kick.data = (unsigned long) dev;
5495         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5496         init_timer(&np->nic_poll);
5497         np->nic_poll.data = (unsigned long) dev;