tg3: Apply short DMA frag workaround to 5906
[linux-2.6.git] / drivers / net / ethernet / broadcom / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2012 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47
48 #include <net/checksum.h>
49 #include <net/ip.h>
50
51 #include <linux/io.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0   0
61 #define BAR_2   2
62
63 #include "tg3.h"
64
65 /* Functions & macros to verify TG3_FLAGS types */
66
67 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
68 {
69         return test_bit(flag, bits);
70 }
71
72 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
73 {
74         set_bit(flag, bits);
75 }
76
77 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
78 {
79         clear_bit(flag, bits);
80 }
81
82 #define tg3_flag(tp, flag)                              \
83         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
84 #define tg3_flag_set(tp, flag)                          \
85         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
86 #define tg3_flag_clear(tp, flag)                        \
87         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
88
89 #define DRV_MODULE_NAME         "tg3"
90 #define TG3_MAJ_NUM                     3
91 #define TG3_MIN_NUM                     123
92 #define DRV_MODULE_VERSION      \
93         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
94 #define DRV_MODULE_RELDATE      "March 21, 2012"
95
96 #define RESET_KIND_SHUTDOWN     0
97 #define RESET_KIND_INIT         1
98 #define RESET_KIND_SUSPEND      2
99
100 #define TG3_DEF_RX_MODE         0
101 #define TG3_DEF_TX_MODE         0
102 #define TG3_DEF_MSG_ENABLE        \
103         (NETIF_MSG_DRV          | \
104          NETIF_MSG_PROBE        | \
105          NETIF_MSG_LINK         | \
106          NETIF_MSG_TIMER        | \
107          NETIF_MSG_IFDOWN       | \
108          NETIF_MSG_IFUP         | \
109          NETIF_MSG_RX_ERR       | \
110          NETIF_MSG_TX_ERR)
111
112 #define TG3_GRC_LCLCTL_PWRSW_DELAY      100
113
114 /* length of time before we decide the hardware is borked,
115  * and dev->tx_timeout() should be called to fix the problem
116  */
117
118 #define TG3_TX_TIMEOUT                  (5 * HZ)
119
120 /* hardware minimum and maximum for a single frame's data payload */
121 #define TG3_MIN_MTU                     60
122 #define TG3_MAX_MTU(tp) \
123         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
124
125 /* These numbers seem to be hard coded in the NIC firmware somehow.
126  * You can't change the ring sizes, but you can change where you place
127  * them in the NIC onboard memory.
128  */
129 #define TG3_RX_STD_RING_SIZE(tp) \
130         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
131          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
132 #define TG3_DEF_RX_RING_PENDING         200
133 #define TG3_RX_JMB_RING_SIZE(tp) \
134         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
135          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
136 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
137
138 /* Do not place this n-ring entries value into the tp struct itself,
139  * we really want to expose these constants to GCC so that modulo et
140  * al.  operations are done with shifts and masks instead of with
141  * hw multiply/modulo instructions.  Another solution would be to
142  * replace things like '% foo' with '& (foo - 1)'.
143  */
144
145 #define TG3_TX_RING_SIZE                512
146 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
147
148 #define TG3_RX_STD_RING_BYTES(tp) \
149         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
150 #define TG3_RX_JMB_RING_BYTES(tp) \
151         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
152 #define TG3_RX_RCB_RING_BYTES(tp) \
153         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
154 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
155                                  TG3_TX_RING_SIZE)
156 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
157
158 #define TG3_DMA_BYTE_ENAB               64
159
160 #define TG3_RX_STD_DMA_SZ               1536
161 #define TG3_RX_JMB_DMA_SZ               9046
162
163 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
164
165 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
166 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
167
168 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
169         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
170
171 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
172         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
173
174 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
175  * that are at least dword aligned when used in PCIX mode.  The driver
176  * works around this bug by double copying the packet.  This workaround
177  * is built into the normal double copy length check for efficiency.
178  *
179  * However, the double copy is only necessary on those architectures
180  * where unaligned memory accesses are inefficient.  For those architectures
181  * where unaligned memory accesses incur little penalty, we can reintegrate
182  * the 5701 in the normal rx path.  Doing so saves a device structure
183  * dereference by hardcoding the double copy threshold in place.
184  */
185 #define TG3_RX_COPY_THRESHOLD           256
186 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
187         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
188 #else
189         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
190 #endif
191
192 #if (NET_IP_ALIGN != 0)
193 #define TG3_RX_OFFSET(tp)       ((tp)->rx_offset)
194 #else
195 #define TG3_RX_OFFSET(tp)       (NET_SKB_PAD)
196 #endif
197
198 /* minimum number of free TX descriptors required to wake up TX process */
199 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
200 #define TG3_TX_BD_DMA_MAX_2K            2048
201 #define TG3_TX_BD_DMA_MAX_4K            4096
202
203 #define TG3_RAW_IP_ALIGN 2
204
205 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
206 #define TG3_FW_UPDATE_FREQ_SEC          (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
207
208 #define FIRMWARE_TG3            "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
211
212 static char version[] __devinitdata =
213         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
214
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
222
223 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
226
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308         {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
309         {}
310 };
311
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
313
314 static const struct {
315         const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
317         { "rx_octets" },
318         { "rx_fragments" },
319         { "rx_ucast_packets" },
320         { "rx_mcast_packets" },
321         { "rx_bcast_packets" },
322         { "rx_fcs_errors" },
323         { "rx_align_errors" },
324         { "rx_xon_pause_rcvd" },
325         { "rx_xoff_pause_rcvd" },
326         { "rx_mac_ctrl_rcvd" },
327         { "rx_xoff_entered" },
328         { "rx_frame_too_long_errors" },
329         { "rx_jabbers" },
330         { "rx_undersize_packets" },
331         { "rx_in_length_errors" },
332         { "rx_out_length_errors" },
333         { "rx_64_or_less_octet_packets" },
334         { "rx_65_to_127_octet_packets" },
335         { "rx_128_to_255_octet_packets" },
336         { "rx_256_to_511_octet_packets" },
337         { "rx_512_to_1023_octet_packets" },
338         { "rx_1024_to_1522_octet_packets" },
339         { "rx_1523_to_2047_octet_packets" },
340         { "rx_2048_to_4095_octet_packets" },
341         { "rx_4096_to_8191_octet_packets" },
342         { "rx_8192_to_9022_octet_packets" },
343
344         { "tx_octets" },
345         { "tx_collisions" },
346
347         { "tx_xon_sent" },
348         { "tx_xoff_sent" },
349         { "tx_flow_control" },
350         { "tx_mac_errors" },
351         { "tx_single_collisions" },
352         { "tx_mult_collisions" },
353         { "tx_deferred" },
354         { "tx_excessive_collisions" },
355         { "tx_late_collisions" },
356         { "tx_collide_2times" },
357         { "tx_collide_3times" },
358         { "tx_collide_4times" },
359         { "tx_collide_5times" },
360         { "tx_collide_6times" },
361         { "tx_collide_7times" },
362         { "tx_collide_8times" },
363         { "tx_collide_9times" },
364         { "tx_collide_10times" },
365         { "tx_collide_11times" },
366         { "tx_collide_12times" },
367         { "tx_collide_13times" },
368         { "tx_collide_14times" },
369         { "tx_collide_15times" },
370         { "tx_ucast_packets" },
371         { "tx_mcast_packets" },
372         { "tx_bcast_packets" },
373         { "tx_carrier_sense_errors" },
374         { "tx_discards" },
375         { "tx_errors" },
376
377         { "dma_writeq_full" },
378         { "dma_write_prioq_full" },
379         { "rxbds_empty" },
380         { "rx_discards" },
381         { "rx_errors" },
382         { "rx_threshold_hit" },
383
384         { "dma_readq_full" },
385         { "dma_read_prioq_full" },
386         { "tx_comp_queue_full" },
387
388         { "ring_set_send_prod_index" },
389         { "ring_status_update" },
390         { "nic_irqs" },
391         { "nic_avoided_irqs" },
392         { "nic_tx_threshold_hit" },
393
394         { "mbuf_lwm_thresh_hit" },
395 };
396
397 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
398
399
400 static const struct {
401         const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403         { "nvram test        (online) " },
404         { "link test         (online) " },
405         { "register test     (offline)" },
406         { "memory test       (offline)" },
407         { "mac loopback test (offline)" },
408         { "phy loopback test (offline)" },
409         { "ext loopback test (offline)" },
410         { "interrupt test    (offline)" },
411 };
412
413 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
414
415
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
417 {
418         writel(val, tp->regs + off);
419 }
420
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
422 {
423         return readl(tp->regs + off);
424 }
425
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
427 {
428         writel(val, tp->aperegs + off);
429 }
430
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
432 {
433         return readl(tp->aperegs + off);
434 }
435
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
437 {
438         unsigned long flags;
439
440         spin_lock_irqsave(&tp->indirect_lock, flags);
441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
444 }
445
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
447 {
448         writel(val, tp->regs + off);
449         readl(tp->regs + off);
450 }
451
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
453 {
454         unsigned long flags;
455         u32 val;
456
457         spin_lock_irqsave(&tp->indirect_lock, flags);
458         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460         spin_unlock_irqrestore(&tp->indirect_lock, flags);
461         return val;
462 }
463
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
465 {
466         unsigned long flags;
467
468         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470                                        TG3_64BIT_REG_LOW, val);
471                 return;
472         }
473         if (off == TG3_RX_STD_PROD_IDX_REG) {
474                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475                                        TG3_64BIT_REG_LOW, val);
476                 return;
477         }
478
479         spin_lock_irqsave(&tp->indirect_lock, flags);
480         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482         spin_unlock_irqrestore(&tp->indirect_lock, flags);
483
484         /* In indirect mode when disabling interrupts, we also need
485          * to clear the interrupt bit in the GRC local ctrl register.
486          */
487         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
488             (val == 0x1)) {
489                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
491         }
492 }
493
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
495 {
496         unsigned long flags;
497         u32 val;
498
499         spin_lock_irqsave(&tp->indirect_lock, flags);
500         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502         spin_unlock_irqrestore(&tp->indirect_lock, flags);
503         return val;
504 }
505
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507  * where it is unsafe to read back the register without some delay.
508  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
510  */
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
512 {
513         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514                 /* Non-posted methods */
515                 tp->write32(tp, off, val);
516         else {
517                 /* Posted method */
518                 tg3_write32(tp, off, val);
519                 if (usec_wait)
520                         udelay(usec_wait);
521                 tp->read32(tp, off);
522         }
523         /* Wait again after the read for the posted method to guarantee that
524          * the wait time is met.
525          */
526         if (usec_wait)
527                 udelay(usec_wait);
528 }
529
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
531 {
532         tp->write32_mbox(tp, off, val);
533         if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534                 tp->read32_mbox(tp, off);
535 }
536
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
538 {
539         void __iomem *mbox = tp->regs + off;
540         writel(val, mbox);
541         if (tg3_flag(tp, TXD_MBOX_HWBUG))
542                 writel(val, mbox);
543         if (tg3_flag(tp, MBOX_WRITE_REORDER))
544                 readl(mbox);
545 }
546
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
548 {
549         return readl(tp->regs + off + GRCMBOX_BASE);
550 }
551
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
553 {
554         writel(val, tp->regs + off + GRCMBOX_BASE);
555 }
556
557 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
562
563 #define tw32(reg, val)                  tp->write32(tp, reg, val)
564 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg)                       tp->read32(tp, reg)
567
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
569 {
570         unsigned long flags;
571
572         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
574                 return;
575
576         spin_lock_irqsave(&tp->indirect_lock, flags);
577         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
580
581                 /* Always leave this as zero. */
582                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
583         } else {
584                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
586
587                 /* Always leave this as zero. */
588                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
589         }
590         spin_unlock_irqrestore(&tp->indirect_lock, flags);
591 }
592
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
594 {
595         unsigned long flags;
596
597         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
599                 *val = 0;
600                 return;
601         }
602
603         spin_lock_irqsave(&tp->indirect_lock, flags);
604         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
607
608                 /* Always leave this as zero. */
609                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
610         } else {
611                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612                 *val = tr32(TG3PCI_MEM_WIN_DATA);
613
614                 /* Always leave this as zero. */
615                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
616         }
617         spin_unlock_irqrestore(&tp->indirect_lock, flags);
618 }
619
620 static void tg3_ape_lock_init(struct tg3 *tp)
621 {
622         int i;
623         u32 regbase, bit;
624
625         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626                 regbase = TG3_APE_LOCK_GRANT;
627         else
628                 regbase = TG3_APE_PER_LOCK_GRANT;
629
630         /* Make sure the driver hasn't any stale locks. */
631         for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
632                 switch (i) {
633                 case TG3_APE_LOCK_PHY0:
634                 case TG3_APE_LOCK_PHY1:
635                 case TG3_APE_LOCK_PHY2:
636                 case TG3_APE_LOCK_PHY3:
637                         bit = APE_LOCK_GRANT_DRIVER;
638                         break;
639                 default:
640                         if (!tp->pci_fn)
641                                 bit = APE_LOCK_GRANT_DRIVER;
642                         else
643                                 bit = 1 << tp->pci_fn;
644                 }
645                 tg3_ape_write32(tp, regbase + 4 * i, bit);
646         }
647
648 }
649
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
651 {
652         int i, off;
653         int ret = 0;
654         u32 status, req, gnt, bit;
655
656         if (!tg3_flag(tp, ENABLE_APE))
657                 return 0;
658
659         switch (locknum) {
660         case TG3_APE_LOCK_GPIO:
661                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
662                         return 0;
663         case TG3_APE_LOCK_GRC:
664         case TG3_APE_LOCK_MEM:
665                 if (!tp->pci_fn)
666                         bit = APE_LOCK_REQ_DRIVER;
667                 else
668                         bit = 1 << tp->pci_fn;
669                 break;
670         default:
671                 return -EINVAL;
672         }
673
674         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675                 req = TG3_APE_LOCK_REQ;
676                 gnt = TG3_APE_LOCK_GRANT;
677         } else {
678                 req = TG3_APE_PER_LOCK_REQ;
679                 gnt = TG3_APE_PER_LOCK_GRANT;
680         }
681
682         off = 4 * locknum;
683
684         tg3_ape_write32(tp, req + off, bit);
685
686         /* Wait for up to 1 millisecond to acquire lock. */
687         for (i = 0; i < 100; i++) {
688                 status = tg3_ape_read32(tp, gnt + off);
689                 if (status == bit)
690                         break;
691                 udelay(10);
692         }
693
694         if (status != bit) {
695                 /* Revoke the lock request. */
696                 tg3_ape_write32(tp, gnt + off, bit);
697                 ret = -EBUSY;
698         }
699
700         return ret;
701 }
702
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
704 {
705         u32 gnt, bit;
706
707         if (!tg3_flag(tp, ENABLE_APE))
708                 return;
709
710         switch (locknum) {
711         case TG3_APE_LOCK_GPIO:
712                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
713                         return;
714         case TG3_APE_LOCK_GRC:
715         case TG3_APE_LOCK_MEM:
716                 if (!tp->pci_fn)
717                         bit = APE_LOCK_GRANT_DRIVER;
718                 else
719                         bit = 1 << tp->pci_fn;
720                 break;
721         default:
722                 return;
723         }
724
725         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726                 gnt = TG3_APE_LOCK_GRANT;
727         else
728                 gnt = TG3_APE_PER_LOCK_GRANT;
729
730         tg3_ape_write32(tp, gnt + 4 * locknum, bit);
731 }
732
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
734 {
735         int i;
736         u32 apedata;
737
738         /* NCSI does not support APE events */
739         if (tg3_flag(tp, APE_HAS_NCSI))
740                 return;
741
742         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743         if (apedata != APE_SEG_SIG_MAGIC)
744                 return;
745
746         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747         if (!(apedata & APE_FW_STATUS_READY))
748                 return;
749
750         /* Wait for up to 1 millisecond for APE to service previous event. */
751         for (i = 0; i < 10; i++) {
752                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
753                         return;
754
755                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
756
757                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759                                         event | APE_EVENT_STATUS_EVENT_PENDING);
760
761                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
762
763                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
764                         break;
765
766                 udelay(100);
767         }
768
769         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
771 }
772
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
774 {
775         u32 event;
776         u32 apedata;
777
778         if (!tg3_flag(tp, ENABLE_APE))
779                 return;
780
781         switch (kind) {
782         case RESET_KIND_INIT:
783                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784                                 APE_HOST_SEG_SIG_MAGIC);
785                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786                                 APE_HOST_SEG_LEN_MAGIC);
787                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792                                 APE_HOST_BEHAV_NO_PHYLOCK);
793                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794                                     TG3_APE_HOST_DRVR_STATE_START);
795
796                 event = APE_EVENT_STATUS_STATE_START;
797                 break;
798         case RESET_KIND_SHUTDOWN:
799                 /* With the interface we are currently using,
800                  * APE does not track driver state.  Wiping
801                  * out the HOST SEGMENT SIGNATURE forces
802                  * the APE to assume OS absent status.
803                  */
804                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
805
806                 if (device_may_wakeup(&tp->pdev->dev) &&
807                     tg3_flag(tp, WOL_ENABLE)) {
808                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809                                             TG3_APE_HOST_WOL_SPEED_AUTO);
810                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
811                 } else
812                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
813
814                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
815
816                 event = APE_EVENT_STATUS_STATE_UNLOAD;
817                 break;
818         case RESET_KIND_SUSPEND:
819                 event = APE_EVENT_STATUS_STATE_SUSPEND;
820                 break;
821         default:
822                 return;
823         }
824
825         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
826
827         tg3_ape_send_event(tp, event);
828 }
829
830 static void tg3_disable_ints(struct tg3 *tp)
831 {
832         int i;
833
834         tw32(TG3PCI_MISC_HOST_CTRL,
835              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836         for (i = 0; i < tp->irq_max; i++)
837                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
838 }
839
840 static void tg3_enable_ints(struct tg3 *tp)
841 {
842         int i;
843
844         tp->irq_sync = 0;
845         wmb();
846
847         tw32(TG3PCI_MISC_HOST_CTRL,
848              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
849
850         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851         for (i = 0; i < tp->irq_cnt; i++) {
852                 struct tg3_napi *tnapi = &tp->napi[i];
853
854                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855                 if (tg3_flag(tp, 1SHOT_MSI))
856                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
857
858                 tp->coal_now |= tnapi->coal_now;
859         }
860
861         /* Force an initial interrupt */
862         if (!tg3_flag(tp, TAGGED_STATUS) &&
863             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
865         else
866                 tw32(HOSTCC_MODE, tp->coal_now);
867
868         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
869 }
870
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
872 {
873         struct tg3 *tp = tnapi->tp;
874         struct tg3_hw_status *sblk = tnapi->hw_status;
875         unsigned int work_exists = 0;
876
877         /* check for phy events */
878         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879                 if (sblk->status & SD_STATUS_LINK_CHG)
880                         work_exists = 1;
881         }
882
883         /* check for TX work to do */
884         if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
885                 work_exists = 1;
886
887         /* check for RX work to do */
888         if (tnapi->rx_rcb_prod_idx &&
889             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
890                 work_exists = 1;
891
892         return work_exists;
893 }
894
895 /* tg3_int_reenable
896  *  similar to tg3_enable_ints, but it accurately determines whether there
897  *  is new work pending and can return without flushing the PIO write
898  *  which reenables interrupts
899  */
900 static void tg3_int_reenable(struct tg3_napi *tnapi)
901 {
902         struct tg3 *tp = tnapi->tp;
903
904         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
905         mmiowb();
906
907         /* When doing tagged status, this work check is unnecessary.
908          * The last_tag we write above tells the chip which piece of
909          * work we've completed.
910          */
911         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
912                 tw32(HOSTCC_MODE, tp->coalesce_mode |
913                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
914 }
915
916 static void tg3_switch_clocks(struct tg3 *tp)
917 {
918         u32 clock_ctrl;
919         u32 orig_clock_ctrl;
920
921         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
922                 return;
923
924         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
925
926         orig_clock_ctrl = clock_ctrl;
927         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
928                        CLOCK_CTRL_CLKRUN_OENABLE |
929                        0x1f);
930         tp->pci_clock_ctrl = clock_ctrl;
931
932         if (tg3_flag(tp, 5705_PLUS)) {
933                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
934                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
935                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
936                 }
937         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
938                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
939                             clock_ctrl |
940                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
941                             40);
942                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
943                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
944                             40);
945         }
946         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
947 }
948
949 #define PHY_BUSY_LOOPS  5000
950
951 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 {
953         u32 frame_val;
954         unsigned int loops;
955         int ret;
956
957         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
958                 tw32_f(MAC_MI_MODE,
959                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960                 udelay(80);
961         }
962
963         *val = 0x0;
964
965         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
966                       MI_COM_PHY_ADDR_MASK);
967         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
968                       MI_COM_REG_ADDR_MASK);
969         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
970
971         tw32_f(MAC_MI_COM, frame_val);
972
973         loops = PHY_BUSY_LOOPS;
974         while (loops != 0) {
975                 udelay(10);
976                 frame_val = tr32(MAC_MI_COM);
977
978                 if ((frame_val & MI_COM_BUSY) == 0) {
979                         udelay(5);
980                         frame_val = tr32(MAC_MI_COM);
981                         break;
982                 }
983                 loops -= 1;
984         }
985
986         ret = -EBUSY;
987         if (loops != 0) {
988                 *val = frame_val & MI_COM_DATA_MASK;
989                 ret = 0;
990         }
991
992         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
993                 tw32_f(MAC_MI_MODE, tp->mi_mode);
994                 udelay(80);
995         }
996
997         return ret;
998 }
999
1000 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 {
1002         u32 frame_val;
1003         unsigned int loops;
1004         int ret;
1005
1006         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1007             (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1008                 return 0;
1009
1010         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1011                 tw32_f(MAC_MI_MODE,
1012                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1013                 udelay(80);
1014         }
1015
1016         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1017                       MI_COM_PHY_ADDR_MASK);
1018         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1019                       MI_COM_REG_ADDR_MASK);
1020         frame_val |= (val & MI_COM_DATA_MASK);
1021         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1022
1023         tw32_f(MAC_MI_COM, frame_val);
1024
1025         loops = PHY_BUSY_LOOPS;
1026         while (loops != 0) {
1027                 udelay(10);
1028                 frame_val = tr32(MAC_MI_COM);
1029                 if ((frame_val & MI_COM_BUSY) == 0) {
1030                         udelay(5);
1031                         frame_val = tr32(MAC_MI_COM);
1032                         break;
1033                 }
1034                 loops -= 1;
1035         }
1036
1037         ret = -EBUSY;
1038         if (loops != 0)
1039                 ret = 0;
1040
1041         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1042                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1043                 udelay(80);
1044         }
1045
1046         return ret;
1047 }
1048
1049 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1050 {
1051         int err;
1052
1053         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1054         if (err)
1055                 goto done;
1056
1057         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1058         if (err)
1059                 goto done;
1060
1061         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1062                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1063         if (err)
1064                 goto done;
1065
1066         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067
1068 done:
1069         return err;
1070 }
1071
1072 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1073 {
1074         int err;
1075
1076         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1077         if (err)
1078                 goto done;
1079
1080         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1081         if (err)
1082                 goto done;
1083
1084         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1085                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1086         if (err)
1087                 goto done;
1088
1089         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090
1091 done:
1092         return err;
1093 }
1094
1095 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1096 {
1097         int err;
1098
1099         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1100         if (!err)
1101                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1102
1103         return err;
1104 }
1105
1106 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1107 {
1108         int err;
1109
1110         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1111         if (!err)
1112                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1113
1114         return err;
1115 }
1116
1117 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1118 {
1119         int err;
1120
1121         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1122                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1123                            MII_TG3_AUXCTL_SHDWSEL_MISC);
1124         if (!err)
1125                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1126
1127         return err;
1128 }
1129
1130 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1131 {
1132         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1133                 set |= MII_TG3_AUXCTL_MISC_WREN;
1134
1135         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1136 }
1137
1138 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1139         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1141                              MII_TG3_AUXCTL_ACTL_TX_6DB)
1142
1143 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1144         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1145                              MII_TG3_AUXCTL_ACTL_TX_6DB);
1146
1147 static int tg3_bmcr_reset(struct tg3 *tp)
1148 {
1149         u32 phy_control;
1150         int limit, err;
1151
1152         /* OK, reset it, and poll the BMCR_RESET bit until it
1153          * clears or we time out.
1154          */
1155         phy_control = BMCR_RESET;
1156         err = tg3_writephy(tp, MII_BMCR, phy_control);
1157         if (err != 0)
1158                 return -EBUSY;
1159
1160         limit = 5000;
1161         while (limit--) {
1162                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1163                 if (err != 0)
1164                         return -EBUSY;
1165
1166                 if ((phy_control & BMCR_RESET) == 0) {
1167                         udelay(40);
1168                         break;
1169                 }
1170                 udelay(10);
1171         }
1172         if (limit < 0)
1173                 return -EBUSY;
1174
1175         return 0;
1176 }
1177
1178 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1179 {
1180         struct tg3 *tp = bp->priv;
1181         u32 val;
1182
1183         spin_lock_bh(&tp->lock);
1184
1185         if (tg3_readphy(tp, reg, &val))
1186                 val = -EIO;
1187
1188         spin_unlock_bh(&tp->lock);
1189
1190         return val;
1191 }
1192
1193 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1194 {
1195         struct tg3 *tp = bp->priv;
1196         u32 ret = 0;
1197
1198         spin_lock_bh(&tp->lock);
1199
1200         if (tg3_writephy(tp, reg, val))
1201                 ret = -EIO;
1202
1203         spin_unlock_bh(&tp->lock);
1204
1205         return ret;
1206 }
1207
1208 static int tg3_mdio_reset(struct mii_bus *bp)
1209 {
1210         return 0;
1211 }
1212
1213 static void tg3_mdio_config_5785(struct tg3 *tp)
1214 {
1215         u32 val;
1216         struct phy_device *phydev;
1217
1218         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1219         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1220         case PHY_ID_BCM50610:
1221         case PHY_ID_BCM50610M:
1222                 val = MAC_PHYCFG2_50610_LED_MODES;
1223                 break;
1224         case PHY_ID_BCMAC131:
1225                 val = MAC_PHYCFG2_AC131_LED_MODES;
1226                 break;
1227         case PHY_ID_RTL8211C:
1228                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1229                 break;
1230         case PHY_ID_RTL8201E:
1231                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232                 break;
1233         default:
1234                 return;
1235         }
1236
1237         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1238                 tw32(MAC_PHYCFG2, val);
1239
1240                 val = tr32(MAC_PHYCFG1);
1241                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1242                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1243                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1244                 tw32(MAC_PHYCFG1, val);
1245
1246                 return;
1247         }
1248
1249         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1250                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1251                        MAC_PHYCFG2_FMODE_MASK_MASK |
1252                        MAC_PHYCFG2_GMODE_MASK_MASK |
1253                        MAC_PHYCFG2_ACT_MASK_MASK   |
1254                        MAC_PHYCFG2_QUAL_MASK_MASK |
1255                        MAC_PHYCFG2_INBAND_ENABLE;
1256
1257         tw32(MAC_PHYCFG2, val);
1258
1259         val = tr32(MAC_PHYCFG1);
1260         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1261                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1262         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1263                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1264                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1265                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1266                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1267         }
1268         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1269                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1270         tw32(MAC_PHYCFG1, val);
1271
1272         val = tr32(MAC_EXT_RGMII_MODE);
1273         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1274                  MAC_RGMII_MODE_RX_QUALITY |
1275                  MAC_RGMII_MODE_RX_ACTIVITY |
1276                  MAC_RGMII_MODE_RX_ENG_DET |
1277                  MAC_RGMII_MODE_TX_ENABLE |
1278                  MAC_RGMII_MODE_TX_LOWPWR |
1279                  MAC_RGMII_MODE_TX_RESET);
1280         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1281                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1282                         val |= MAC_RGMII_MODE_RX_INT_B |
1283                                MAC_RGMII_MODE_RX_QUALITY |
1284                                MAC_RGMII_MODE_RX_ACTIVITY |
1285                                MAC_RGMII_MODE_RX_ENG_DET;
1286                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1287                         val |= MAC_RGMII_MODE_TX_ENABLE |
1288                                MAC_RGMII_MODE_TX_LOWPWR |
1289                                MAC_RGMII_MODE_TX_RESET;
1290         }
1291         tw32(MAC_EXT_RGMII_MODE, val);
1292 }
1293
1294 static void tg3_mdio_start(struct tg3 *tp)
1295 {
1296         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1297         tw32_f(MAC_MI_MODE, tp->mi_mode);
1298         udelay(80);
1299
1300         if (tg3_flag(tp, MDIOBUS_INITED) &&
1301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1302                 tg3_mdio_config_5785(tp);
1303 }
1304
1305 static int tg3_mdio_init(struct tg3 *tp)
1306 {
1307         int i;
1308         u32 reg;
1309         struct phy_device *phydev;
1310
1311         if (tg3_flag(tp, 5717_PLUS)) {
1312                 u32 is_serdes;
1313
1314                 tp->phy_addr = tp->pci_fn + 1;
1315
1316                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1317                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1318                 else
1319                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1320                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1321                 if (is_serdes)
1322                         tp->phy_addr += 7;
1323         } else
1324                 tp->phy_addr = TG3_PHY_MII_ADDR;
1325
1326         tg3_mdio_start(tp);
1327
1328         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1329                 return 0;
1330
1331         tp->mdio_bus = mdiobus_alloc();
1332         if (tp->mdio_bus == NULL)
1333                 return -ENOMEM;
1334
1335         tp->mdio_bus->name     = "tg3 mdio bus";
1336         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1337                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1338         tp->mdio_bus->priv     = tp;
1339         tp->mdio_bus->parent   = &tp->pdev->dev;
1340         tp->mdio_bus->read     = &tg3_mdio_read;
1341         tp->mdio_bus->write    = &tg3_mdio_write;
1342         tp->mdio_bus->reset    = &tg3_mdio_reset;
1343         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1344         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1345
1346         for (i = 0; i < PHY_MAX_ADDR; i++)
1347                 tp->mdio_bus->irq[i] = PHY_POLL;
1348
1349         /* The bus registration will look for all the PHYs on the mdio bus.
1350          * Unfortunately, it does not ensure the PHY is powered up before
1351          * accessing the PHY ID registers.  A chip reset is the
1352          * quickest way to bring the device back to an operational state..
1353          */
1354         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1355                 tg3_bmcr_reset(tp);
1356
1357         i = mdiobus_register(tp->mdio_bus);
1358         if (i) {
1359                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1360                 mdiobus_free(tp->mdio_bus);
1361                 return i;
1362         }
1363
1364         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1365
1366         if (!phydev || !phydev->drv) {
1367                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1368                 mdiobus_unregister(tp->mdio_bus);
1369                 mdiobus_free(tp->mdio_bus);
1370                 return -ENODEV;
1371         }
1372
1373         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1374         case PHY_ID_BCM57780:
1375                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1376                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1377                 break;
1378         case PHY_ID_BCM50610:
1379         case PHY_ID_BCM50610M:
1380                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1381                                      PHY_BRCM_RX_REFCLK_UNUSED |
1382                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1383                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1384                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1385                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1386                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1387                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1388                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1389                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1390                 /* fallthru */
1391         case PHY_ID_RTL8211C:
1392                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1393                 break;
1394         case PHY_ID_RTL8201E:
1395         case PHY_ID_BCMAC131:
1396                 phydev->interface = PHY_INTERFACE_MODE_MII;
1397                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1398                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1399                 break;
1400         }
1401
1402         tg3_flag_set(tp, MDIOBUS_INITED);
1403
1404         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1405                 tg3_mdio_config_5785(tp);
1406
1407         return 0;
1408 }
1409
1410 static void tg3_mdio_fini(struct tg3 *tp)
1411 {
1412         if (tg3_flag(tp, MDIOBUS_INITED)) {
1413                 tg3_flag_clear(tp, MDIOBUS_INITED);
1414                 mdiobus_unregister(tp->mdio_bus);
1415                 mdiobus_free(tp->mdio_bus);
1416         }
1417 }
1418
1419 /* tp->lock is held. */
1420 static inline void tg3_generate_fw_event(struct tg3 *tp)
1421 {
1422         u32 val;
1423
1424         val = tr32(GRC_RX_CPU_EVENT);
1425         val |= GRC_RX_CPU_DRIVER_EVENT;
1426         tw32_f(GRC_RX_CPU_EVENT, val);
1427
1428         tp->last_event_jiffies = jiffies;
1429 }
1430
1431 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1432
1433 /* tp->lock is held. */
1434 static void tg3_wait_for_event_ack(struct tg3 *tp)
1435 {
1436         int i;
1437         unsigned int delay_cnt;
1438         long time_remain;
1439
1440         /* If enough time has passed, no wait is necessary. */
1441         time_remain = (long)(tp->last_event_jiffies + 1 +
1442                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1443                       (long)jiffies;
1444         if (time_remain < 0)
1445                 return;
1446
1447         /* Check if we can shorten the wait time. */
1448         delay_cnt = jiffies_to_usecs(time_remain);
1449         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1450                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1451         delay_cnt = (delay_cnt >> 3) + 1;
1452
1453         for (i = 0; i < delay_cnt; i++) {
1454                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455                         break;
1456                 udelay(8);
1457         }
1458 }
1459
1460 /* tp->lock is held. */
1461 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1462 {
1463         u32 reg, val;
1464
1465         val = 0;
1466         if (!tg3_readphy(tp, MII_BMCR, &reg))
1467                 val = reg << 16;
1468         if (!tg3_readphy(tp, MII_BMSR, &reg))
1469                 val |= (reg & 0xffff);
1470         *data++ = val;
1471
1472         val = 0;
1473         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1474                 val = reg << 16;
1475         if (!tg3_readphy(tp, MII_LPA, &reg))
1476                 val |= (reg & 0xffff);
1477         *data++ = val;
1478
1479         val = 0;
1480         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1481                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1482                         val = reg << 16;
1483                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1484                         val |= (reg & 0xffff);
1485         }
1486         *data++ = val;
1487
1488         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1489                 val = reg << 16;
1490         else
1491                 val = 0;
1492         *data++ = val;
1493 }
1494
1495 /* tp->lock is held. */
1496 static void tg3_ump_link_report(struct tg3 *tp)
1497 {
1498         u32 data[4];
1499
1500         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1501                 return;
1502
1503         tg3_phy_gather_ump_data(tp, data);
1504
1505         tg3_wait_for_event_ack(tp);
1506
1507         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1508         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1509         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1510         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1511         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1512         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1513
1514         tg3_generate_fw_event(tp);
1515 }
1516
1517 /* tp->lock is held. */
1518 static void tg3_stop_fw(struct tg3 *tp)
1519 {
1520         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1521                 /* Wait for RX cpu to ACK the previous event. */
1522                 tg3_wait_for_event_ack(tp);
1523
1524                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1525
1526                 tg3_generate_fw_event(tp);
1527
1528                 /* Wait for RX cpu to ACK this event. */
1529                 tg3_wait_for_event_ack(tp);
1530         }
1531 }
1532
1533 /* tp->lock is held. */
1534 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1535 {
1536         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1537                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1538
1539         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1540                 switch (kind) {
1541                 case RESET_KIND_INIT:
1542                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1543                                       DRV_STATE_START);
1544                         break;
1545
1546                 case RESET_KIND_SHUTDOWN:
1547                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1548                                       DRV_STATE_UNLOAD);
1549                         break;
1550
1551                 case RESET_KIND_SUSPEND:
1552                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1553                                       DRV_STATE_SUSPEND);
1554                         break;
1555
1556                 default:
1557                         break;
1558                 }
1559         }
1560
1561         if (kind == RESET_KIND_INIT ||
1562             kind == RESET_KIND_SUSPEND)
1563                 tg3_ape_driver_state_change(tp, kind);
1564 }
1565
1566 /* tp->lock is held. */
1567 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1568 {
1569         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1570                 switch (kind) {
1571                 case RESET_KIND_INIT:
1572                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1573                                       DRV_STATE_START_DONE);
1574                         break;
1575
1576                 case RESET_KIND_SHUTDOWN:
1577                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1578                                       DRV_STATE_UNLOAD_DONE);
1579                         break;
1580
1581                 default:
1582                         break;
1583                 }
1584         }
1585
1586         if (kind == RESET_KIND_SHUTDOWN)
1587                 tg3_ape_driver_state_change(tp, kind);
1588 }
1589
1590 /* tp->lock is held. */
1591 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1592 {
1593         if (tg3_flag(tp, ENABLE_ASF)) {
1594                 switch (kind) {
1595                 case RESET_KIND_INIT:
1596                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1597                                       DRV_STATE_START);
1598                         break;
1599
1600                 case RESET_KIND_SHUTDOWN:
1601                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1602                                       DRV_STATE_UNLOAD);
1603                         break;
1604
1605                 case RESET_KIND_SUSPEND:
1606                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1607                                       DRV_STATE_SUSPEND);
1608                         break;
1609
1610                 default:
1611                         break;
1612                 }
1613         }
1614 }
1615
1616 static int tg3_poll_fw(struct tg3 *tp)
1617 {
1618         int i;
1619         u32 val;
1620
1621         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1622                 /* Wait up to 20ms for init done. */
1623                 for (i = 0; i < 200; i++) {
1624                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1625                                 return 0;
1626                         udelay(100);
1627                 }
1628                 return -ENODEV;
1629         }
1630
1631         /* Wait for firmware initialization to complete. */
1632         for (i = 0; i < 100000; i++) {
1633                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1634                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1635                         break;
1636                 udelay(10);
1637         }
1638
1639         /* Chip might not be fitted with firmware.  Some Sun onboard
1640          * parts are configured like that.  So don't signal the timeout
1641          * of the above loop as an error, but do report the lack of
1642          * running firmware once.
1643          */
1644         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1645                 tg3_flag_set(tp, NO_FWARE_REPORTED);
1646
1647                 netdev_info(tp->dev, "No firmware running\n");
1648         }
1649
1650         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1651                 /* The 57765 A0 needs a little more
1652                  * time to do some important work.
1653                  */
1654                 mdelay(10);
1655         }
1656
1657         return 0;
1658 }
1659
1660 static void tg3_link_report(struct tg3 *tp)
1661 {
1662         if (!netif_carrier_ok(tp->dev)) {
1663                 netif_info(tp, link, tp->dev, "Link is down\n");
1664                 tg3_ump_link_report(tp);
1665         } else if (netif_msg_link(tp)) {
1666                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1667                             (tp->link_config.active_speed == SPEED_1000 ?
1668                              1000 :
1669                              (tp->link_config.active_speed == SPEED_100 ?
1670                               100 : 10)),
1671                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1672                              "full" : "half"));
1673
1674                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1675                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1676                             "on" : "off",
1677                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1678                             "on" : "off");
1679
1680                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1681                         netdev_info(tp->dev, "EEE is %s\n",
1682                                     tp->setlpicnt ? "enabled" : "disabled");
1683
1684                 tg3_ump_link_report(tp);
1685         }
1686 }
1687
1688 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1689 {
1690         u16 miireg;
1691
1692         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1693                 miireg = ADVERTISE_1000XPAUSE;
1694         else if (flow_ctrl & FLOW_CTRL_TX)
1695                 miireg = ADVERTISE_1000XPSE_ASYM;
1696         else if (flow_ctrl & FLOW_CTRL_RX)
1697                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1698         else
1699                 miireg = 0;
1700
1701         return miireg;
1702 }
1703
1704 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1705 {
1706         u8 cap = 0;
1707
1708         if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1709                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1710         } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1711                 if (lcladv & ADVERTISE_1000XPAUSE)
1712                         cap = FLOW_CTRL_RX;
1713                 if (rmtadv & ADVERTISE_1000XPAUSE)
1714                         cap = FLOW_CTRL_TX;
1715         }
1716
1717         return cap;
1718 }
1719
1720 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1721 {
1722         u8 autoneg;
1723         u8 flowctrl = 0;
1724         u32 old_rx_mode = tp->rx_mode;
1725         u32 old_tx_mode = tp->tx_mode;
1726
1727         if (tg3_flag(tp, USE_PHYLIB))
1728                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1729         else
1730                 autoneg = tp->link_config.autoneg;
1731
1732         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1733                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1734                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1735                 else
1736                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1737         } else
1738                 flowctrl = tp->link_config.flowctrl;
1739
1740         tp->link_config.active_flowctrl = flowctrl;
1741
1742         if (flowctrl & FLOW_CTRL_RX)
1743                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1744         else
1745                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1746
1747         if (old_rx_mode != tp->rx_mode)
1748                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1749
1750         if (flowctrl & FLOW_CTRL_TX)
1751                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1752         else
1753                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1754
1755         if (old_tx_mode != tp->tx_mode)
1756                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1757 }
1758
1759 static void tg3_adjust_link(struct net_device *dev)
1760 {
1761         u8 oldflowctrl, linkmesg = 0;
1762         u32 mac_mode, lcl_adv, rmt_adv;
1763         struct tg3 *tp = netdev_priv(dev);
1764         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1765
1766         spin_lock_bh(&tp->lock);
1767
1768         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1769                                     MAC_MODE_HALF_DUPLEX);
1770
1771         oldflowctrl = tp->link_config.active_flowctrl;
1772
1773         if (phydev->link) {
1774                 lcl_adv = 0;
1775                 rmt_adv = 0;
1776
1777                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1778                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1779                 else if (phydev->speed == SPEED_1000 ||
1780                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1781                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1782                 else
1783                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1784
1785                 if (phydev->duplex == DUPLEX_HALF)
1786                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1787                 else {
1788                         lcl_adv = mii_advertise_flowctrl(
1789                                   tp->link_config.flowctrl);
1790
1791                         if (phydev->pause)
1792                                 rmt_adv = LPA_PAUSE_CAP;
1793                         if (phydev->asym_pause)
1794                                 rmt_adv |= LPA_PAUSE_ASYM;
1795                 }
1796
1797                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1798         } else
1799                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1800
1801         if (mac_mode != tp->mac_mode) {
1802                 tp->mac_mode = mac_mode;
1803                 tw32_f(MAC_MODE, tp->mac_mode);
1804                 udelay(40);
1805         }
1806
1807         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1808                 if (phydev->speed == SPEED_10)
1809                         tw32(MAC_MI_STAT,
1810                              MAC_MI_STAT_10MBPS_MODE |
1811                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1812                 else
1813                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1814         }
1815
1816         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1817                 tw32(MAC_TX_LENGTHS,
1818                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1819                       (6 << TX_LENGTHS_IPG_SHIFT) |
1820                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1821         else
1822                 tw32(MAC_TX_LENGTHS,
1823                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1824                       (6 << TX_LENGTHS_IPG_SHIFT) |
1825                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1826
1827         if (phydev->link != tp->old_link ||
1828             phydev->speed != tp->link_config.active_speed ||
1829             phydev->duplex != tp->link_config.active_duplex ||
1830             oldflowctrl != tp->link_config.active_flowctrl)
1831                 linkmesg = 1;
1832
1833         tp->old_link = phydev->link;
1834         tp->link_config.active_speed = phydev->speed;
1835         tp->link_config.active_duplex = phydev->duplex;
1836
1837         spin_unlock_bh(&tp->lock);
1838
1839         if (linkmesg)
1840                 tg3_link_report(tp);
1841 }
1842
1843 static int tg3_phy_init(struct tg3 *tp)
1844 {
1845         struct phy_device *phydev;
1846
1847         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1848                 return 0;
1849
1850         /* Bring the PHY back to a known state. */
1851         tg3_bmcr_reset(tp);
1852
1853         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1854
1855         /* Attach the MAC to the PHY. */
1856         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1857                              phydev->dev_flags, phydev->interface);
1858         if (IS_ERR(phydev)) {
1859                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1860                 return PTR_ERR(phydev);
1861         }
1862
1863         /* Mask with MAC supported features. */
1864         switch (phydev->interface) {
1865         case PHY_INTERFACE_MODE_GMII:
1866         case PHY_INTERFACE_MODE_RGMII:
1867                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1868                         phydev->supported &= (PHY_GBIT_FEATURES |
1869                                               SUPPORTED_Pause |
1870                                               SUPPORTED_Asym_Pause);
1871                         break;
1872                 }
1873                 /* fallthru */
1874         case PHY_INTERFACE_MODE_MII:
1875                 phydev->supported &= (PHY_BASIC_FEATURES |
1876                                       SUPPORTED_Pause |
1877                                       SUPPORTED_Asym_Pause);
1878                 break;
1879         default:
1880                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1881                 return -EINVAL;
1882         }
1883
1884         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1885
1886         phydev->advertising = phydev->supported;
1887
1888         return 0;
1889 }
1890
1891 static void tg3_phy_start(struct tg3 *tp)
1892 {
1893         struct phy_device *phydev;
1894
1895         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1896                 return;
1897
1898         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1899
1900         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1901                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1902                 phydev->speed = tp->link_config.speed;
1903                 phydev->duplex = tp->link_config.duplex;
1904                 phydev->autoneg = tp->link_config.autoneg;
1905                 phydev->advertising = tp->link_config.advertising;
1906         }
1907
1908         phy_start(phydev);
1909
1910         phy_start_aneg(phydev);
1911 }
1912
1913 static void tg3_phy_stop(struct tg3 *tp)
1914 {
1915         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1916                 return;
1917
1918         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1919 }
1920
1921 static void tg3_phy_fini(struct tg3 *tp)
1922 {
1923         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1924                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1925                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1926         }
1927 }
1928
1929 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1930 {
1931         int err;
1932         u32 val;
1933
1934         if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1935                 return 0;
1936
1937         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1938                 /* Cannot do read-modify-write on 5401 */
1939                 err = tg3_phy_auxctl_write(tp,
1940                                            MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1941                                            MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1942                                            0x4c20);
1943                 goto done;
1944         }
1945
1946         err = tg3_phy_auxctl_read(tp,
1947                                   MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1948         if (err)
1949                 return err;
1950
1951         val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1952         err = tg3_phy_auxctl_write(tp,
1953                                    MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1954
1955 done:
1956         return err;
1957 }
1958
1959 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1960 {
1961         u32 phytest;
1962
1963         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1964                 u32 phy;
1965
1966                 tg3_writephy(tp, MII_TG3_FET_TEST,
1967                              phytest | MII_TG3_FET_SHADOW_EN);
1968                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1969                         if (enable)
1970                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1971                         else
1972                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1973                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1974                 }
1975                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1976         }
1977 }
1978
1979 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1980 {
1981         u32 reg;
1982
1983         if (!tg3_flag(tp, 5705_PLUS) ||
1984             (tg3_flag(tp, 5717_PLUS) &&
1985              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1986                 return;
1987
1988         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1989                 tg3_phy_fet_toggle_apd(tp, enable);
1990                 return;
1991         }
1992
1993         reg = MII_TG3_MISC_SHDW_WREN |
1994               MII_TG3_MISC_SHDW_SCR5_SEL |
1995               MII_TG3_MISC_SHDW_SCR5_LPED |
1996               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1997               MII_TG3_MISC_SHDW_SCR5_SDTL |
1998               MII_TG3_MISC_SHDW_SCR5_C125OE;
1999         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2000                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2001
2002         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2003
2004
2005         reg = MII_TG3_MISC_SHDW_WREN |
2006               MII_TG3_MISC_SHDW_APD_SEL |
2007               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2008         if (enable)
2009                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2010
2011         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2012 }
2013
2014 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2015 {
2016         u32 phy;
2017
2018         if (!tg3_flag(tp, 5705_PLUS) ||
2019             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2020                 return;
2021
2022         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2023                 u32 ephy;
2024
2025                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2026                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2027
2028                         tg3_writephy(tp, MII_TG3_FET_TEST,
2029                                      ephy | MII_TG3_FET_SHADOW_EN);
2030                         if (!tg3_readphy(tp, reg, &phy)) {
2031                                 if (enable)
2032                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2033                                 else
2034                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2035                                 tg3_writephy(tp, reg, phy);
2036                         }
2037                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2038                 }
2039         } else {
2040                 int ret;
2041
2042                 ret = tg3_phy_auxctl_read(tp,
2043                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2044                 if (!ret) {
2045                         if (enable)
2046                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2047                         else
2048                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2049                         tg3_phy_auxctl_write(tp,
2050                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2051                 }
2052         }
2053 }
2054
2055 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2056 {
2057         int ret;
2058         u32 val;
2059
2060         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2061                 return;
2062
2063         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2064         if (!ret)
2065                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2066                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2067 }
2068
2069 static void tg3_phy_apply_otp(struct tg3 *tp)
2070 {
2071         u32 otp, phy;
2072
2073         if (!tp->phy_otp)
2074                 return;
2075
2076         otp = tp->phy_otp;
2077
2078         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2079                 return;
2080
2081         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2082         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2083         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2084
2085         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2086               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2087         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2088
2089         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2090         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2091         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2092
2093         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2094         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2095
2096         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2097         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2098
2099         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2100               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2101         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2102
2103         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2104 }
2105
2106 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2107 {
2108         u32 val;
2109
2110         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2111                 return;
2112
2113         tp->setlpicnt = 0;
2114
2115         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2116             current_link_up == 1 &&
2117             tp->link_config.active_duplex == DUPLEX_FULL &&
2118             (tp->link_config.active_speed == SPEED_100 ||
2119              tp->link_config.active_speed == SPEED_1000)) {
2120                 u32 eeectl;
2121
2122                 if (tp->link_config.active_speed == SPEED_1000)
2123                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2124                 else
2125                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2126
2127                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2128
2129                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2130                                   TG3_CL45_D7_EEERES_STAT, &val);
2131
2132                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2133                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2134                         tp->setlpicnt = 2;
2135         }
2136
2137         if (!tp->setlpicnt) {
2138                 if (current_link_up == 1 &&
2139                    !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2140                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2141                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2142                 }
2143
2144                 val = tr32(TG3_CPMU_EEE_MODE);
2145                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2146         }
2147 }
2148
2149 static void tg3_phy_eee_enable(struct tg3 *tp)
2150 {
2151         u32 val;
2152
2153         if (tp->link_config.active_speed == SPEED_1000 &&
2154             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2155              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2156              tg3_flag(tp, 57765_CLASS)) &&
2157             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2158                 val = MII_TG3_DSP_TAP26_ALNOKO |
2159                       MII_TG3_DSP_TAP26_RMRXSTO;
2160                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2161                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2162         }
2163
2164         val = tr32(TG3_CPMU_EEE_MODE);
2165         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2166 }
2167
2168 static int tg3_wait_macro_done(struct tg3 *tp)
2169 {
2170         int limit = 100;
2171
2172         while (limit--) {
2173                 u32 tmp32;
2174
2175                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2176                         if ((tmp32 & 0x1000) == 0)
2177                                 break;
2178                 }
2179         }
2180         if (limit < 0)
2181                 return -EBUSY;
2182
2183         return 0;
2184 }
2185
2186 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2187 {
2188         static const u32 test_pat[4][6] = {
2189         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2190         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2191         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2192         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2193         };
2194         int chan;
2195
2196         for (chan = 0; chan < 4; chan++) {
2197                 int i;
2198
2199                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2200                              (chan * 0x2000) | 0x0200);
2201                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2202
2203                 for (i = 0; i < 6; i++)
2204                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2205                                      test_pat[chan][i]);
2206
2207                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2208                 if (tg3_wait_macro_done(tp)) {
2209                         *resetp = 1;
2210                         return -EBUSY;
2211                 }
2212
2213                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2214                              (chan * 0x2000) | 0x0200);
2215                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2216                 if (tg3_wait_macro_done(tp)) {
2217                         *resetp = 1;
2218                         return -EBUSY;
2219                 }
2220
2221                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2222                 if (tg3_wait_macro_done(tp)) {
2223                         *resetp = 1;
2224                         return -EBUSY;
2225                 }
2226
2227                 for (i = 0; i < 6; i += 2) {
2228                         u32 low, high;
2229
2230                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2231                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2232                             tg3_wait_macro_done(tp)) {
2233                                 *resetp = 1;
2234                                 return -EBUSY;
2235                         }
2236                         low &= 0x7fff;
2237                         high &= 0x000f;
2238                         if (low != test_pat[chan][i] ||
2239                             high != test_pat[chan][i+1]) {
2240                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2241                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2242                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2243
2244                                 return -EBUSY;
2245                         }
2246                 }
2247         }
2248
2249         return 0;
2250 }
2251
2252 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2253 {
2254         int chan;
2255
2256         for (chan = 0; chan < 4; chan++) {
2257                 int i;
2258
2259                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2260                              (chan * 0x2000) | 0x0200);
2261                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2262                 for (i = 0; i < 6; i++)
2263                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2264                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2265                 if (tg3_wait_macro_done(tp))
2266                         return -EBUSY;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2273 {
2274         u32 reg32, phy9_orig;
2275         int retries, do_phy_reset, err;
2276
2277         retries = 10;
2278         do_phy_reset = 1;
2279         do {
2280                 if (do_phy_reset) {
2281                         err = tg3_bmcr_reset(tp);
2282                         if (err)
2283                                 return err;
2284                         do_phy_reset = 0;
2285                 }
2286
2287                 /* Disable transmitter and interrupt.  */
2288                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2289                         continue;
2290
2291                 reg32 |= 0x3000;
2292                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2293
2294                 /* Set full-duplex, 1000 mbps.  */
2295                 tg3_writephy(tp, MII_BMCR,
2296                              BMCR_FULLDPLX | BMCR_SPEED1000);
2297
2298                 /* Set to master mode.  */
2299                 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2300                         continue;
2301
2302                 tg3_writephy(tp, MII_CTRL1000,
2303                              CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2304
2305                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2306                 if (err)
2307                         return err;
2308
2309                 /* Block the PHY control access.  */
2310                 tg3_phydsp_write(tp, 0x8005, 0x0800);
2311
2312                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2313                 if (!err)
2314                         break;
2315         } while (--retries);
2316
2317         err = tg3_phy_reset_chanpat(tp);
2318         if (err)
2319                 return err;
2320
2321         tg3_phydsp_write(tp, 0x8005, 0x0000);
2322
2323         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2324         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2325
2326         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2327
2328         tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2329
2330         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2331                 reg32 &= ~0x3000;
2332                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2333         } else if (!err)
2334                 err = -EBUSY;
2335
2336         return err;
2337 }
2338
2339 /* This will reset the tigon3 PHY if there is no valid
2340  * link unless the FORCE argument is non-zero.
2341  */
2342 static int tg3_phy_reset(struct tg3 *tp)
2343 {
2344         u32 val, cpmuctrl;
2345         int err;
2346
2347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2348                 val = tr32(GRC_MISC_CFG);
2349                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2350                 udelay(40);
2351         }
2352         err  = tg3_readphy(tp, MII_BMSR, &val);
2353         err |= tg3_readphy(tp, MII_BMSR, &val);
2354         if (err != 0)
2355                 return -EBUSY;
2356
2357         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2358                 netif_carrier_off(tp->dev);
2359                 tg3_link_report(tp);
2360         }
2361
2362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2363             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2364             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2365                 err = tg3_phy_reset_5703_4_5(tp);
2366                 if (err)
2367                         return err;
2368                 goto out;
2369         }
2370
2371         cpmuctrl = 0;
2372         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2373             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2374                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2375                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2376                         tw32(TG3_CPMU_CTRL,
2377                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2378         }
2379
2380         err = tg3_bmcr_reset(tp);
2381         if (err)
2382                 return err;
2383
2384         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2385                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2386                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2387
2388                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2389         }
2390
2391         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2392             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2393                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2394                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2395                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2396                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2397                         udelay(40);
2398                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2399                 }
2400         }
2401
2402         if (tg3_flag(tp, 5717_PLUS) &&
2403             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2404                 return 0;
2405
2406         tg3_phy_apply_otp(tp);
2407
2408         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2409                 tg3_phy_toggle_apd(tp, true);
2410         else
2411                 tg3_phy_toggle_apd(tp, false);
2412
2413 out:
2414         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2415             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2416                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2417                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2418                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2419         }
2420
2421         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2422                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2423                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2424         }
2425
2426         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2427                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2428                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2429                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2430                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2431                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2432                 }
2433         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2434                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2435                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2436                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2437                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2438                                 tg3_writephy(tp, MII_TG3_TEST1,
2439                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2440                         } else
2441                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2442
2443                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2444                 }
2445         }
2446
2447         /* Set Extended packet length bit (bit 14) on all chips that */
2448         /* support jumbo frames */
2449         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2450                 /* Cannot do read-modify-write on 5401 */
2451                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2452         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2453                 /* Set bit 14 with read-modify-write to preserve other bits */
2454                 err = tg3_phy_auxctl_read(tp,
2455                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2456                 if (!err)
2457                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2458                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2459         }
2460
2461         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2462          * jumbo frames transmission.
2463          */
2464         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2465                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2466                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2467                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2468         }
2469
2470         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2471                 /* adjust output voltage */
2472                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2473         }
2474
2475         tg3_phy_toggle_automdix(tp, 1);
2476         tg3_phy_set_wirespeed(tp);
2477         return 0;
2478 }
2479
2480 #define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2481 #define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2482 #define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2483                                           TG3_GPIO_MSG_NEED_VAUX)
2484 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2485         ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2486          (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2487          (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2488          (TG3_GPIO_MSG_DRVR_PRES << 12))
2489
2490 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2491         ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2492          (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2493          (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2494          (TG3_GPIO_MSG_NEED_VAUX << 12))
2495
2496 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2497 {
2498         u32 status, shift;
2499
2500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2501             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2502                 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2503         else
2504                 status = tr32(TG3_CPMU_DRV_STATUS);
2505
2506         shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2507         status &= ~(TG3_GPIO_MSG_MASK << shift);
2508         status |= (newstat << shift);
2509
2510         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2511             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2512                 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2513         else
2514                 tw32(TG3_CPMU_DRV_STATUS, status);
2515
2516         return status >> TG3_APE_GPIO_MSG_SHIFT;
2517 }
2518
2519 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2520 {
2521         if (!tg3_flag(tp, IS_NIC))
2522                 return 0;
2523
2524         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2525             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2526             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2527                 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2528                         return -EIO;
2529
2530                 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2531
2532                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2533                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2534
2535                 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2536         } else {
2537                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2538                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2539         }
2540
2541         return 0;
2542 }
2543
2544 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2545 {
2546         u32 grc_local_ctrl;
2547
2548         if (!tg3_flag(tp, IS_NIC) ||
2549             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2550             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2551                 return;
2552
2553         grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2554
2555         tw32_wait_f(GRC_LOCAL_CTRL,
2556                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2557                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2558
2559         tw32_wait_f(GRC_LOCAL_CTRL,
2560                     grc_local_ctrl,
2561                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2562
2563         tw32_wait_f(GRC_LOCAL_CTRL,
2564                     grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2565                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2566 }
2567
2568 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2569 {
2570         if (!tg3_flag(tp, IS_NIC))
2571                 return;
2572
2573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2574             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2575                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2576                             (GRC_LCLCTRL_GPIO_OE0 |
2577                              GRC_LCLCTRL_GPIO_OE1 |
2578                              GRC_LCLCTRL_GPIO_OE2 |
2579                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2580                              GRC_LCLCTRL_GPIO_OUTPUT1),
2581                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2582         } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2583                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2584                 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2585                 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2586                                      GRC_LCLCTRL_GPIO_OE1 |
2587                                      GRC_LCLCTRL_GPIO_OE2 |
2588                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2589                                      GRC_LCLCTRL_GPIO_OUTPUT1 |
2590                                      tp->grc_local_ctrl;
2591                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2592                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2593
2594                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2595                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2596                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2597
2598                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2599                 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2600                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2601         } else {
2602                 u32 no_gpio2;
2603                 u32 grc_local_ctrl = 0;
2604
2605                 /* Workaround to prevent overdrawing Amps. */
2606                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2607                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2608                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2609                                     grc_local_ctrl,
2610                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2611                 }
2612
2613                 /* On 5753 and variants, GPIO2 cannot be used. */
2614                 no_gpio2 = tp->nic_sram_data_cfg &
2615                            NIC_SRAM_DATA_CFG_NO_GPIO2;
2616
2617                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2618                                   GRC_LCLCTRL_GPIO_OE1 |
2619                                   GRC_LCLCTRL_GPIO_OE2 |
2620                                   GRC_LCLCTRL_GPIO_OUTPUT1 |
2621                                   GRC_LCLCTRL_GPIO_OUTPUT2;
2622                 if (no_gpio2) {
2623                         grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2624                                             GRC_LCLCTRL_GPIO_OUTPUT2);
2625                 }
2626                 tw32_wait_f(GRC_LOCAL_CTRL,
2627                             tp->grc_local_ctrl | grc_local_ctrl,
2628                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2629
2630                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2631
2632                 tw32_wait_f(GRC_LOCAL_CTRL,
2633                             tp->grc_local_ctrl | grc_local_ctrl,
2634                             TG3_GRC_LCLCTL_PWRSW_DELAY);
2635
2636                 if (!no_gpio2) {
2637                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2638                         tw32_wait_f(GRC_LOCAL_CTRL,
2639                                     tp->grc_local_ctrl | grc_local_ctrl,
2640                                     TG3_GRC_LCLCTL_PWRSW_DELAY);
2641                 }
2642         }
2643 }
2644
2645 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2646 {
2647         u32 msg = 0;
2648
2649         /* Serialize power state transitions */
2650         if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2651                 return;
2652
2653         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2654                 msg = TG3_GPIO_MSG_NEED_VAUX;
2655
2656         msg = tg3_set_function_status(tp, msg);
2657
2658         if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2659                 goto done;
2660
2661         if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2662                 tg3_pwrsrc_switch_to_vaux(tp);
2663         else
2664                 tg3_pwrsrc_die_with_vmain(tp);
2665
2666 done:
2667         tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2668 }
2669
2670 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2671 {
2672         bool need_vaux = false;
2673
2674         /* The GPIOs do something completely different on 57765. */
2675         if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2676                 return;
2677
2678         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2679             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2680             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2681                 tg3_frob_aux_power_5717(tp, include_wol ?
2682                                         tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2683                 return;
2684         }
2685
2686         if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2687                 struct net_device *dev_peer;
2688
2689                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2690
2691                 /* remove_one() may have been run on the peer. */
2692                 if (dev_peer) {
2693                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2694
2695                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2696                                 return;
2697
2698                         if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2699                             tg3_flag(tp_peer, ENABLE_ASF))
2700                                 need_vaux = true;
2701                 }
2702         }
2703
2704         if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2705             tg3_flag(tp, ENABLE_ASF))
2706                 need_vaux = true;
2707
2708         if (need_vaux)
2709                 tg3_pwrsrc_switch_to_vaux(tp);
2710         else
2711                 tg3_pwrsrc_die_with_vmain(tp);
2712 }
2713
2714 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2715 {
2716         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2717                 return 1;
2718         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2719                 if (speed != SPEED_10)
2720                         return 1;
2721         } else if (speed == SPEED_10)
2722                 return 1;
2723
2724         return 0;
2725 }
2726
2727 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2728 {
2729         u32 val;
2730
2731         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2732                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2733                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2734                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2735
2736                         sg_dig_ctrl |=
2737                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2738                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2739                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2740                 }
2741                 return;
2742         }
2743
2744         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2745                 tg3_bmcr_reset(tp);
2746                 val = tr32(GRC_MISC_CFG);
2747                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2748                 udelay(40);
2749                 return;
2750         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2751                 u32 phytest;
2752                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2753                         u32 phy;
2754
2755                         tg3_writephy(tp, MII_ADVERTISE, 0);
2756                         tg3_writephy(tp, MII_BMCR,
2757                                      BMCR_ANENABLE | BMCR_ANRESTART);
2758
2759                         tg3_writephy(tp, MII_TG3_FET_TEST,
2760                                      phytest | MII_TG3_FET_SHADOW_EN);
2761                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2762                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2763                                 tg3_writephy(tp,
2764                                              MII_TG3_FET_SHDW_AUXMODE4,
2765                                              phy);
2766                         }
2767                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2768                 }
2769                 return;
2770         } else if (do_low_power) {
2771                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2772                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2773
2774                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2775                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2776                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2777                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2778         }
2779
2780         /* The PHY should not be powered down on some chips because
2781          * of bugs.
2782          */
2783         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2784             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2785             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2786              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2787             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2788              !tp->pci_fn))
2789                 return;
2790
2791         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2792             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2793                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2794                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2795                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2796                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2797         }
2798
2799         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2800 }
2801
2802 /* tp->lock is held. */
2803 static int tg3_nvram_lock(struct tg3 *tp)
2804 {
2805         if (tg3_flag(tp, NVRAM)) {
2806                 int i;
2807
2808                 if (tp->nvram_lock_cnt == 0) {
2809                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2810                         for (i = 0; i < 8000; i++) {
2811                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2812                                         break;
2813                                 udelay(20);
2814                         }
2815                         if (i == 8000) {
2816                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2817                                 return -ENODEV;
2818                         }
2819                 }
2820                 tp->nvram_lock_cnt++;
2821         }
2822         return 0;
2823 }
2824
2825 /* tp->lock is held. */
2826 static void tg3_nvram_unlock(struct tg3 *tp)
2827 {
2828         if (tg3_flag(tp, NVRAM)) {
2829                 if (tp->nvram_lock_cnt > 0)
2830                         tp->nvram_lock_cnt--;
2831                 if (tp->nvram_lock_cnt == 0)
2832                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2833         }
2834 }
2835
2836 /* tp->lock is held. */
2837 static void tg3_enable_nvram_access(struct tg3 *tp)
2838 {
2839         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2840                 u32 nvaccess = tr32(NVRAM_ACCESS);
2841
2842                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2843         }
2844 }
2845
2846 /* tp->lock is held. */
2847 static void tg3_disable_nvram_access(struct tg3 *tp)
2848 {
2849         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2850                 u32 nvaccess = tr32(NVRAM_ACCESS);
2851
2852                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2853         }
2854 }
2855
2856 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2857                                         u32 offset, u32 *val)
2858 {
2859         u32 tmp;
2860         int i;
2861
2862         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2863                 return -EINVAL;
2864
2865         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2866                                         EEPROM_ADDR_DEVID_MASK |
2867                                         EEPROM_ADDR_READ);
2868         tw32(GRC_EEPROM_ADDR,
2869              tmp |
2870              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2871              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2872               EEPROM_ADDR_ADDR_MASK) |
2873              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2874
2875         for (i = 0; i < 1000; i++) {
2876                 tmp = tr32(GRC_EEPROM_ADDR);
2877
2878                 if (tmp & EEPROM_ADDR_COMPLETE)
2879                         break;
2880                 msleep(1);
2881         }
2882         if (!(tmp & EEPROM_ADDR_COMPLETE))
2883                 return -EBUSY;
2884
2885         tmp = tr32(GRC_EEPROM_DATA);
2886
2887         /*
2888          * The data will always be opposite the native endian
2889          * format.  Perform a blind byteswap to compensate.
2890          */
2891         *val = swab32(tmp);
2892
2893         return 0;
2894 }
2895
2896 #define NVRAM_CMD_TIMEOUT 10000
2897
2898 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2899 {
2900         int i;
2901
2902         tw32(NVRAM_CMD, nvram_cmd);
2903         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2904                 udelay(10);
2905                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2906                         udelay(10);
2907                         break;
2908                 }
2909         }
2910
2911         if (i == NVRAM_CMD_TIMEOUT)
2912                 return -EBUSY;
2913
2914         return 0;
2915 }
2916
2917 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2918 {
2919         if (tg3_flag(tp, NVRAM) &&
2920             tg3_flag(tp, NVRAM_BUFFERED) &&
2921             tg3_flag(tp, FLASH) &&
2922             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2923             (tp->nvram_jedecnum == JEDEC_ATMEL))
2924
2925                 addr = ((addr / tp->nvram_pagesize) <<
2926                         ATMEL_AT45DB0X1B_PAGE_POS) +
2927                        (addr % tp->nvram_pagesize);
2928
2929         return addr;
2930 }
2931
2932 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2933 {
2934         if (tg3_flag(tp, NVRAM) &&
2935             tg3_flag(tp, NVRAM_BUFFERED) &&
2936             tg3_flag(tp, FLASH) &&
2937             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2938             (tp->nvram_jedecnum == JEDEC_ATMEL))
2939
2940                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2941                         tp->nvram_pagesize) +
2942                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2943
2944         return addr;
2945 }
2946
2947 /* NOTE: Data read in from NVRAM is byteswapped according to
2948  * the byteswapping settings for all other register accesses.
2949  * tg3 devices are BE devices, so on a BE machine, the data
2950  * returned will be exactly as it is seen in NVRAM.  On a LE
2951  * machine, the 32-bit value will be byteswapped.
2952  */
2953 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2954 {
2955         int ret;
2956
2957         if (!tg3_flag(tp, NVRAM))
2958                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2959
2960         offset = tg3_nvram_phys_addr(tp, offset);
2961
2962         if (offset > NVRAM_ADDR_MSK)
2963                 return -EINVAL;
2964
2965         ret = tg3_nvram_lock(tp);
2966         if (ret)
2967                 return ret;
2968
2969         tg3_enable_nvram_access(tp);
2970
2971         tw32(NVRAM_ADDR, offset);
2972         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2973                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2974
2975         if (ret == 0)
2976                 *val = tr32(NVRAM_RDDATA);
2977
2978         tg3_disable_nvram_access(tp);
2979
2980         tg3_nvram_unlock(tp);
2981
2982         return ret;
2983 }
2984
2985 /* Ensures NVRAM data is in bytestream format. */
2986 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2987 {
2988         u32 v;
2989         int res = tg3_nvram_read(tp, offset, &v);
2990         if (!res)
2991                 *val = cpu_to_be32(v);
2992         return res;
2993 }
2994
2995 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
2996                                     u32 offset, u32 len, u8 *buf)
2997 {
2998         int i, j, rc = 0;
2999         u32 val;
3000
3001         for (i = 0; i < len; i += 4) {
3002                 u32 addr;
3003                 __be32 data;
3004
3005                 addr = offset + i;
3006
3007                 memcpy(&data, buf + i, 4);
3008
3009                 /*
3010                  * The SEEPROM interface expects the data to always be opposite
3011                  * the native endian format.  We accomplish this by reversing
3012                  * all the operations that would have been performed on the
3013                  * data from a call to tg3_nvram_read_be32().
3014                  */
3015                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3016
3017                 val = tr32(GRC_EEPROM_ADDR);
3018                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3019
3020                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3021                         EEPROM_ADDR_READ);
3022                 tw32(GRC_EEPROM_ADDR, val |
3023                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
3024                         (addr & EEPROM_ADDR_ADDR_MASK) |
3025                         EEPROM_ADDR_START |
3026                         EEPROM_ADDR_WRITE);
3027
3028                 for (j = 0; j < 1000; j++) {
3029                         val = tr32(GRC_EEPROM_ADDR);
3030
3031                         if (val & EEPROM_ADDR_COMPLETE)
3032                                 break;
3033                         msleep(1);
3034                 }
3035                 if (!(val & EEPROM_ADDR_COMPLETE)) {
3036                         rc = -EBUSY;
3037                         break;
3038                 }
3039         }
3040
3041         return rc;
3042 }
3043
3044 /* offset and length are dword aligned */
3045 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3046                 u8 *buf)
3047 {
3048         int ret = 0;
3049         u32 pagesize = tp->nvram_pagesize;
3050         u32 pagemask = pagesize - 1;
3051         u32 nvram_cmd;
3052         u8 *tmp;
3053
3054         tmp = kmalloc(pagesize, GFP_KERNEL);
3055         if (tmp == NULL)
3056                 return -ENOMEM;
3057
3058         while (len) {
3059                 int j;
3060                 u32 phy_addr, page_off, size;
3061
3062                 phy_addr = offset & ~pagemask;
3063
3064                 for (j = 0; j < pagesize; j += 4) {
3065                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
3066                                                   (__be32 *) (tmp + j));
3067                         if (ret)
3068                                 break;
3069                 }
3070                 if (ret)
3071                         break;
3072
3073                 page_off = offset & pagemask;
3074                 size = pagesize;
3075                 if (len < size)
3076                         size = len;
3077
3078                 len -= size;
3079
3080                 memcpy(tmp + page_off, buf, size);
3081
3082                 offset = offset + (pagesize - page_off);
3083
3084                 tg3_enable_nvram_access(tp);
3085
3086                 /*
3087                  * Before we can erase the flash page, we need
3088                  * to issue a special "write enable" command.
3089                  */
3090                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3091
3092                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3093                         break;
3094
3095                 /* Erase the target page */
3096                 tw32(NVRAM_ADDR, phy_addr);
3097
3098                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3099                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3100
3101                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3102                         break;
3103
3104                 /* Issue another write enable to start the write. */
3105                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3106
3107                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3108                         break;
3109
3110                 for (j = 0; j < pagesize; j += 4) {
3111                         __be32 data;
3112
3113                         data = *((__be32 *) (tmp + j));
3114
3115                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
3116
3117                         tw32(NVRAM_ADDR, phy_addr + j);
3118
3119                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3120                                 NVRAM_CMD_WR;
3121
3122                         if (j == 0)
3123                                 nvram_cmd |= NVRAM_CMD_FIRST;
3124                         else if (j == (pagesize - 4))
3125                                 nvram_cmd |= NVRAM_CMD_LAST;
3126
3127                         ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3128                         if (ret)
3129                                 break;
3130                 }
3131                 if (ret)
3132                         break;
3133         }
3134
3135         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3136         tg3_nvram_exec_cmd(tp, nvram_cmd);
3137
3138         kfree(tmp);
3139
3140         return ret;
3141 }
3142
3143 /* offset and length are dword aligned */
3144 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3145                 u8 *buf)
3146 {
3147         int i, ret = 0;
3148
3149         for (i = 0; i < len; i += 4, offset += 4) {
3150                 u32 page_off, phy_addr, nvram_cmd;
3151                 __be32 data;
3152
3153                 memcpy(&data, buf + i, 4);
3154                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3155
3156                 page_off = offset % tp->nvram_pagesize;
3157
3158                 phy_addr = tg3_nvram_phys_addr(tp, offset);
3159
3160                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3161
3162                 if (page_off == 0 || i == 0)
3163                         nvram_cmd |= NVRAM_CMD_FIRST;
3164                 if (page_off == (tp->nvram_pagesize - 4))
3165                         nvram_cmd |= NVRAM_CMD_LAST;
3166
3167                 if (i == (len - 4))
3168                         nvram_cmd |= NVRAM_CMD_LAST;
3169
3170                 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3171                     !tg3_flag(tp, FLASH) ||
3172                     !tg3_flag(tp, 57765_PLUS))
3173                         tw32(NVRAM_ADDR, phy_addr);
3174
3175                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3176                     !tg3_flag(tp, 5755_PLUS) &&
3177                     (tp->nvram_jedecnum == JEDEC_ST) &&
3178                     (nvram_cmd & NVRAM_CMD_FIRST)) {
3179                         u32 cmd;
3180
3181                         cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3182                         ret = tg3_nvram_exec_cmd(tp, cmd);
3183                         if (ret)
3184                                 break;
3185                 }
3186                 if (!tg3_flag(tp, FLASH)) {
3187                         /* We always do complete word writes to eeprom. */
3188                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3189                 }
3190
3191                 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3192                 if (ret)
3193                         break;
3194         }
3195         return ret;
3196 }
3197
3198 /* offset and length are dword aligned */
3199 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3200 {
3201         int ret;
3202
3203         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3204                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3205                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
3206                 udelay(40);
3207         }
3208
3209         if (!tg3_flag(tp, NVRAM)) {
3210                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3211         } else {
3212                 u32 grc_mode;
3213
3214                 ret = tg3_nvram_lock(tp);
3215                 if (ret)
3216                         return ret;
3217
3218                 tg3_enable_nvram_access(tp);
3219                 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3220                         tw32(NVRAM_WRITE1, 0x406);
3221
3222                 grc_mode = tr32(GRC_MODE);
3223                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3224
3225                 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3226                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
3227                                 buf);
3228                 } else {
3229                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3230                                 buf);
3231                 }
3232
3233                 grc_mode = tr32(GRC_MODE);
3234                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3235
3236                 tg3_disable_nvram_access(tp);
3237                 tg3_nvram_unlock(tp);
3238         }
3239
3240         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3241                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3242                 udelay(40);
3243         }
3244
3245         return ret;
3246 }
3247
3248 #define RX_CPU_SCRATCH_BASE     0x30000
3249 #define RX_CPU_SCRATCH_SIZE     0x04000
3250 #define TX_CPU_SCRATCH_BASE     0x34000
3251 #define TX_CPU_SCRATCH_SIZE     0x04000
3252
3253 /* tp->lock is held. */
3254 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3255 {
3256         int i;
3257
3258         BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3259
3260         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3261                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3262
3263                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3264                 return 0;
3265         }
3266         if (offset == RX_CPU_BASE) {
3267                 for (i = 0; i < 10000; i++) {
3268                         tw32(offset + CPU_STATE, 0xffffffff);
3269                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
3270                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3271                                 break;
3272                 }
3273
3274                 tw32(offset + CPU_STATE, 0xffffffff);
3275                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
3276                 udelay(10);
3277         } else {
3278                 for (i = 0; i < 10000; i++) {
3279                         tw32(offset + CPU_STATE, 0xffffffff);
3280                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
3281                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3282                                 break;
3283                 }
3284         }
3285
3286         if (i >= 10000) {
3287                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3288                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3289                 return -ENODEV;
3290         }
3291
3292         /* Clear firmware's nvram arbitration. */
3293         if (tg3_flag(tp, NVRAM))
3294                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3295         return 0;
3296 }
3297
3298 struct fw_info {
3299         unsigned int fw_base;
3300         unsigned int fw_len;
3301         const __be32 *fw_data;
3302 };
3303
3304 /* tp->lock is held. */
3305 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3306                                  u32 cpu_scratch_base, int cpu_scratch_size,
3307                                  struct fw_info *info)
3308 {
3309         int err, lock_err, i;
3310         void (*write_op)(struct tg3 *, u32, u32);
3311
3312         if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3313                 netdev_err(tp->dev,
3314                            "%s: Trying to load TX cpu firmware which is 5705\n",
3315                            __func__);
3316                 return -EINVAL;
3317         }
3318
3319         if (tg3_flag(tp, 5705_PLUS))
3320                 write_op = tg3_write_mem;
3321         else
3322                 write_op = tg3_write_indirect_reg32;
3323
3324         /* It is possible that bootcode is still loading at this point.
3325          * Get the nvram lock first before halting the cpu.
3326          */
3327         lock_err = tg3_nvram_lock(tp);
3328         err = tg3_halt_cpu(tp, cpu_base);
3329         if (!lock_err)
3330                 tg3_nvram_unlock(tp);
3331         if (err)
3332                 goto out;
3333
3334         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3335                 write_op(tp, cpu_scratch_base + i, 0);
3336         tw32(cpu_base + CPU_STATE, 0xffffffff);
3337         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3338         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3339                 write_op(tp, (cpu_scratch_base +
3340                               (info->fw_base & 0xffff) +
3341                               (i * sizeof(u32))),
3342                               be32_to_cpu(info->fw_data[i]));
3343
3344         err = 0;
3345
3346 out:
3347         return err;
3348 }
3349
3350 /* tp->lock is held. */
3351 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3352 {
3353         struct fw_info info;
3354         const __be32 *fw_data;
3355         int err, i;
3356
3357         fw_data = (void *)tp->fw->data;
3358
3359         /* Firmware blob starts with version numbers, followed by
3360            start address and length. We are setting complete length.
3361            length = end_address_of_bss - start_address_of_text.
3362            Remainder is the blob to be loaded contiguously
3363            from start address. */
3364
3365         info.fw_base = be32_to_cpu(fw_data[1]);
3366         info.fw_len = tp->fw->size - 12;
3367         info.fw_data = &fw_data[3];
3368
3369         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3370                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3371                                     &info);
3372         if (err)
3373                 return err;
3374
3375         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3376                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3377                                     &info);
3378         if (err)
3379                 return err;
3380
3381         /* Now startup only the RX cpu. */
3382         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3383         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3384
3385         for (i = 0; i < 5; i++) {
3386                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3387                         break;
3388                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3389                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
3390                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3391                 udelay(1000);
3392         }
3393         if (i >= 5) {
3394                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3395                            "should be %08x\n", __func__,
3396                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3397                 return -ENODEV;
3398         }
3399         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3400         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
3401
3402         return 0;
3403 }
3404
3405 /* tp->lock is held. */
3406 static int tg3_load_tso_firmware(struct tg3 *tp)
3407 {
3408         struct fw_info info;
3409         const __be32 *fw_data;
3410         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3411         int err, i;
3412
3413         if (tg3_flag(tp, HW_TSO_1) ||
3414             tg3_flag(tp, HW_TSO_2) ||
3415             tg3_flag(tp, HW_TSO_3))
3416                 return 0;
3417
3418         fw_data = (void *)tp->fw->data;
3419
3420         /* Firmware blob starts with version numbers, followed by
3421            start address and length. We are setting complete length.
3422            length = end_address_of_bss - start_address_of_text.
3423            Remainder is the blob to be loaded contiguously
3424            from start address. */
3425
3426         info.fw_base = be32_to_cpu(fw_data[1]);
3427         cpu_scratch_size = tp->fw_len;
3428         info.fw_len = tp->fw->size - 12;
3429         info.fw_data = &fw_data[3];
3430
3431         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3432                 cpu_base = RX_CPU_BASE;
3433                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3434         } else {
3435                 cpu_base = TX_CPU_BASE;
3436                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3437                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3438         }
3439
3440         err = tg3_load_firmware_cpu(tp, cpu_base,
3441                                     cpu_scratch_base, cpu_scratch_size,
3442                                     &info);
3443         if (err)
3444                 return err;
3445
3446         /* Now startup the cpu. */
3447         tw32(cpu_base + CPU_STATE, 0xffffffff);
3448         tw32_f(cpu_base + CPU_PC, info.fw_base);
3449
3450         for (i = 0; i < 5; i++) {
3451                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3452                         break;
3453                 tw32(cpu_base + CPU_STATE, 0xffffffff);
3454                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
3455                 tw32_f(cpu_base + CPU_PC, info.fw_base);
3456                 udelay(1000);
3457         }
3458         if (i >= 5) {
3459                 netdev_err(tp->dev,
3460                            "%s fails to set CPU PC, is %08x should be %08x\n",
3461                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3462                 return -ENODEV;
3463         }
3464         tw32(cpu_base + CPU_STATE, 0xffffffff);
3465         tw32_f(cpu_base + CPU_MODE,  0x00000000);
3466         return 0;
3467 }
3468
3469
3470 /* tp->lock is held. */
3471 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3472 {
3473         u32 addr_high, addr_low;
3474         int i;
3475
3476         addr_high = ((tp->dev->dev_addr[0] << 8) |
3477                      tp->dev->dev_addr[1]);
3478         addr_low = ((tp->dev->dev_addr[2] << 24) |
3479                     (tp->dev->dev_addr[3] << 16) |
3480                     (tp->dev->dev_addr[4] <<  8) |
3481                     (tp->dev->dev_addr[5] <<  0));
3482         for (i = 0; i < 4; i++) {
3483                 if (i == 1 && skip_mac_1)
3484                         continue;
3485                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3486                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3487         }
3488
3489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3490             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3491                 for (i = 0; i < 12; i++) {
3492                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3493                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3494                 }
3495         }
3496
3497         addr_high = (tp->dev->dev_addr[0] +
3498                      tp->dev->dev_addr[1] +
3499                      tp->dev->dev_addr[2] +
3500                      tp->dev->dev_addr[3] +
3501                      tp->dev->dev_addr[4] +
3502                      tp->dev->dev_addr[5]) &
3503                 TX_BACKOFF_SEED_MASK;
3504         tw32(MAC_TX_BACKOFF_SEED, addr_high);
3505 }
3506
3507 static void tg3_enable_register_access(struct tg3 *tp)
3508 {
3509         /*
3510          * Make sure register accesses (indirect or otherwise) will function
3511          * correctly.
3512          */
3513         pci_write_config_dword(tp->pdev,
3514                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3515 }
3516
3517 static int tg3_power_up(struct tg3 *tp)
3518 {
3519         int err;
3520
3521         tg3_enable_register_access(tp);
3522
3523         err = pci_set_power_state(tp->pdev, PCI_D0);
3524         if (!err) {
3525                 /* Switch out of Vaux if it is a NIC */
3526                 tg3_pwrsrc_switch_to_vmain(tp);
3527         } else {
3528                 netdev_err(tp->dev, "Transition to D0 failed\n");
3529         }
3530
3531         return err;
3532 }
3533
3534 static int tg3_setup_phy(struct tg3 *, int);
3535
3536 static int tg3_power_down_prepare(struct tg3 *tp)
3537 {
3538         u32 misc_host_ctrl;
3539         bool device_should_wake, do_low_power;
3540
3541         tg3_enable_register_access(tp);
3542
3543         /* Restore the CLKREQ setting. */
3544         if (tg3_flag(tp, CLKREQ_BUG)) {
3545                 u16 lnkctl;
3546
3547                 pci_read_config_word(tp->pdev,
3548                                      pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3549                                      &lnkctl);
3550                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3551                 pci_write_config_word(tp->pdev,
3552                                       pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3553                                       lnkctl);
3554         }
3555
3556         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3557         tw32(TG3PCI_MISC_HOST_CTRL,
3558              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3559
3560         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3561                              tg3_flag(tp, WOL_ENABLE);
3562
3563         if (tg3_flag(tp, USE_PHYLIB)) {
3564                 do_low_power = false;
3565                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3566                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3567                         struct phy_device *phydev;
3568                         u32 phyid, advertising;
3569
3570                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3571
3572                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3573
3574                         tp->link_config.speed = phydev->speed;
3575                         tp->link_config.duplex = phydev->duplex;
3576                         tp->link_config.autoneg = phydev->autoneg;
3577                         tp->link_config.advertising = phydev->advertising;
3578
3579                         advertising = ADVERTISED_TP |
3580                                       ADVERTISED_Pause |
3581                                       ADVERTISED_Autoneg |
3582                                       ADVERTISED_10baseT_Half;
3583
3584                         if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3585                                 if (tg3_flag(tp, WOL_SPEED_100MB))
3586                                         advertising |=
3587                                                 ADVERTISED_100baseT_Half |
3588                                                 ADVERTISED_100baseT_Full |
3589                                                 ADVERTISED_10baseT_Full;
3590                                 else
3591                                         advertising |= ADVERTISED_10baseT_Full;
3592                         }
3593
3594                         phydev->advertising = advertising;
3595
3596                         phy_start_aneg(phydev);
3597
3598                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3599                         if (phyid != PHY_ID_BCMAC131) {
3600                                 phyid &= PHY_BCM_OUI_MASK;
3601                                 if (phyid == PHY_BCM_OUI_1 ||
3602                                     phyid == PHY_BCM_OUI_2 ||
3603                                     phyid == PHY_BCM_OUI_3)
3604                                         do_low_power = true;
3605                         }
3606                 }
3607         } else {
3608                 do_low_power = true;
3609
3610                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3611                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3612
3613                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3614                         tg3_setup_phy(tp, 0);
3615         }
3616
3617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3618                 u32 val;
3619
3620                 val = tr32(GRC_VCPU_EXT_CTRL);
3621                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3622         } else if (!tg3_flag(tp, ENABLE_ASF)) {
3623                 int i;
3624                 u32 val;
3625
3626                 for (i = 0; i < 200; i++) {
3627                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3628                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3629                                 break;
3630                         msleep(1);
3631                 }
3632         }
3633         if (tg3_flag(tp, WOL_CAP))
3634                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3635                                                      WOL_DRV_STATE_SHUTDOWN |
3636                                                      WOL_DRV_WOL |
3637                                                      WOL_SET_MAGIC_PKT);
3638
3639         if (device_should_wake) {
3640                 u32 mac_mode;
3641
3642                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3643                         if (do_low_power &&
3644                             !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3645                                 tg3_phy_auxctl_write(tp,
3646                                                MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3647                                                MII_TG3_AUXCTL_PCTL_WOL_EN |
3648                                                MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3649                                                MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3650                                 udelay(40);
3651                         }
3652
3653                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
3655                         else
3656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
3657
3658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3660                             ASIC_REV_5700) {
3661                                 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3662                                              SPEED_100 : SPEED_10;
3663                                 if (tg3_5700_link_polarity(tp, speed))
3664                                         mac_mode |= MAC_MODE_LINK_POLARITY;
3665                                 else
3666                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
3667                         }
3668                 } else {
3669                         mac_mode = MAC_MODE_PORT_MODE_TBI;
3670                 }
3671
3672                 if (!tg3_flag(tp, 5750_PLUS))
3673                         tw32(MAC_LED_CTRL, tp->led_ctrl);
3674
3675                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3676                 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3677                     (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3678                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3679
3680                 if (tg3_flag(tp, ENABLE_APE))
3681                         mac_mode |= MAC_MODE_APE_TX_EN |
3682                                     MAC_MODE_APE_RX_EN |
3683                                     MAC_MODE_TDE_ENABLE;
3684
3685                 tw32_f(MAC_MODE, mac_mode);
3686                 udelay(100);
3687
3688                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3689                 udelay(10);
3690         }
3691
3692         if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3693             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3694              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3695                 u32 base_val;
3696
3697                 base_val = tp->pci_clock_ctrl;
3698                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3699                              CLOCK_CTRL_TXCLK_DISABLE);
3700
3701                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3702                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
3703         } else if (tg3_flag(tp, 5780_CLASS) ||
3704                    tg3_flag(tp, CPMU_PRESENT) ||
3705                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3706                 /* do nothing */
3707         } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3708                 u32 newbits1, newbits2;
3709
3710                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3711                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3712                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3713                                     CLOCK_CTRL_TXCLK_DISABLE |
3714                                     CLOCK_CTRL_ALTCLK);
3715                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3716                 } else if (tg3_flag(tp, 5705_PLUS)) {
3717                         newbits1 = CLOCK_CTRL_625_CORE;
3718                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3719                 } else {
3720                         newbits1 = CLOCK_CTRL_ALTCLK;
3721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3722                 }
3723
3724                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3725                             40);
3726
3727                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3728                             40);
3729
3730                 if (!tg3_flag(tp, 5705_PLUS)) {
3731                         u32 newbits3;
3732
3733                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3734                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3735                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3736                                             CLOCK_CTRL_TXCLK_DISABLE |
3737                                             CLOCK_CTRL_44MHZ_CORE);
3738                         } else {
3739                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3740                         }
3741
3742                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
3743                                     tp->pci_clock_ctrl | newbits3, 40);
3744                 }
3745         }
3746
3747         if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3748                 tg3_power_down_phy(tp, do_low_power);
3749
3750         tg3_frob_aux_power(tp, true);
3751
3752         /* Workaround for unstable PLL clock */
3753         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3754             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3755                 u32 val = tr32(0x7d00);
3756
3757                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3758                 tw32(0x7d00, val);
3759                 if (!tg3_flag(tp, ENABLE_ASF)) {
3760                         int err;
3761
3762                         err = tg3_nvram_lock(tp);
3763                         tg3_halt_cpu(tp, RX_CPU_BASE);
3764                         if (!err)
3765                                 tg3_nvram_unlock(tp);
3766                 }
3767         }
3768
3769         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3770
3771         return 0;
3772 }
3773
3774 static void tg3_power_down(struct tg3 *tp)
3775 {
3776         tg3_power_down_prepare(tp);
3777
3778         pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3779         pci_set_power_state(tp->pdev, PCI_D3hot);
3780 }
3781
3782 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3783 {
3784         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3785         case MII_TG3_AUX_STAT_10HALF:
3786                 *speed = SPEED_10;
3787                 *duplex = DUPLEX_HALF;
3788                 break;
3789
3790         case MII_TG3_AUX_STAT_10FULL:
3791                 *speed = SPEED_10;
3792                 *duplex = DUPLEX_FULL;
3793                 break;
3794
3795         case MII_TG3_AUX_STAT_100HALF:
3796                 *speed = SPEED_100;
3797                 *duplex = DUPLEX_HALF;
3798                 break;
3799
3800         case MII_TG3_AUX_STAT_100FULL:
3801                 *speed = SPEED_100;
3802                 *duplex = DUPLEX_FULL;
3803                 break;
3804
3805         case MII_TG3_AUX_STAT_1000HALF:
3806                 *speed = SPEED_1000;
3807                 *duplex = DUPLEX_HALF;
3808                 break;
3809
3810         case MII_TG3_AUX_STAT_1000FULL:
3811                 *speed = SPEED_1000;
3812                 *duplex = DUPLEX_FULL;
3813                 break;
3814
3815         default:
3816                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3817                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3818                                  SPEED_10;
3819                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3820                                   DUPLEX_HALF;
3821                         break;
3822                 }
3823                 *speed = SPEED_UNKNOWN;
3824                 *duplex = DUPLEX_UNKNOWN;
3825                 break;
3826         }
3827 }
3828
3829 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3830 {
3831         int err = 0;
3832         u32 val, new_adv;
3833
3834         new_adv = ADVERTISE_CSMA;
3835         new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3836         new_adv |= mii_advertise_flowctrl(flowctrl);
3837
3838         err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3839         if (err)
3840                 goto done;
3841
3842         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3843                 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3844
3845                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3846                     tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3847                         new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3848
3849                 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3850                 if (err)
3851                         goto done;
3852         }
3853
3854         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3855                 goto done;
3856
3857         tw32(TG3_CPMU_EEE_MODE,
3858              tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3859
3860         err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3861         if (!err) {
3862                 u32 err2;
3863
3864                 val = 0;
3865                 /* Advertise 100-BaseTX EEE ability */
3866                 if (advertise & ADVERTISED_100baseT_Full)
3867                         val |= MDIO_AN_EEE_ADV_100TX;
3868                 /* Advertise 1000-BaseT EEE ability */
3869                 if (advertise & ADVERTISED_1000baseT_Full)
3870                         val |= MDIO_AN_EEE_ADV_1000T;
3871                 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3872                 if (err)
3873                         val = 0;
3874
3875                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3876                 case ASIC_REV_5717:
3877                 case ASIC_REV_57765:
3878                 case ASIC_REV_57766:
3879                 case ASIC_REV_5719:
3880                         /* If we advertised any eee advertisements above... */
3881                         if (val)
3882                                 val = MII_TG3_DSP_TAP26_ALNOKO |
3883                                       MII_TG3_DSP_TAP26_RMRXSTO |
3884                                       MII_TG3_DSP_TAP26_OPCSINPT;
3885                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3886                         /* Fall through */
3887                 case ASIC_REV_5720:
3888                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3889                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3890                                                  MII_TG3_DSP_CH34TP2_HIBW01);
3891                 }
3892
3893                 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3894                 if (!err)
3895                         err = err2;
3896         }
3897
3898 done:
3899         return err;
3900 }
3901
3902 static void tg3_phy_copper_begin(struct tg3 *tp)
3903 {
3904         if (tp->link_config.autoneg == AUTONEG_ENABLE ||
3905             (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3906                 u32 adv, fc;
3907
3908                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3909                         adv = ADVERTISED_10baseT_Half |
3910                               ADVERTISED_10baseT_Full;
3911                         if (tg3_flag(tp, WOL_SPEED_100MB))
3912                                 adv |= ADVERTISED_100baseT_Half |
3913                                        ADVERTISED_100baseT_Full;
3914
3915                         fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
3916                 } else {
3917                         adv = tp->link_config.advertising;
3918                         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3919                                 adv &= ~(ADVERTISED_1000baseT_Half |
3920                                          ADVERTISED_1000baseT_Full);
3921
3922                         fc = tp->link_config.flowctrl;
3923                 }
3924
3925                 tg3_phy_autoneg_cfg(tp, adv, fc);
3926
3927                 tg3_writephy(tp, MII_BMCR,
3928                              BMCR_ANENABLE | BMCR_ANRESTART);
3929         } else {
3930                 int i;
3931                 u32 bmcr, orig_bmcr;
3932
3933                 tp->link_config.active_speed = tp->link_config.speed;
3934                 tp->link_config.active_duplex = tp->link_config.duplex;
3935
3936                 bmcr = 0;
3937                 switch (tp->link_config.speed) {
3938                 default:
3939                 case SPEED_10:
3940                         break;
3941
3942                 case SPEED_100:
3943                         bmcr |= BMCR_SPEED100;
3944                         break;
3945
3946                 case SPEED_1000:
3947                         bmcr |= BMCR_SPEED1000;
3948                         break;
3949                 }
3950
3951                 if (tp->link_config.duplex == DUPLEX_FULL)
3952                         bmcr |= BMCR_FULLDPLX;
3953
3954                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3955                     (bmcr != orig_bmcr)) {
3956                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3957                         for (i = 0; i < 1500; i++) {
3958                                 u32 tmp;
3959
3960                                 udelay(10);
3961                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3962                                     tg3_readphy(tp, MII_BMSR, &tmp))
3963                                         continue;
3964                                 if (!(tmp & BMSR_LSTATUS)) {
3965                                         udelay(40);
3966                                         break;
3967                                 }
3968                         }
3969                         tg3_writephy(tp, MII_BMCR, bmcr);
3970                         udelay(40);
3971                 }
3972         }
3973 }
3974
3975 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3976 {
3977         int err;
3978
3979         /* Turn off tap power management. */
3980         /* Set Extended packet length bit */
3981         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3982
3983         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3984         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3985         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3986         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3987         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3988
3989         udelay(40);
3990
3991         return err;
3992 }
3993
3994 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
3995 {
3996         u32 advmsk, tgtadv, advertising;
3997
3998         advertising = tp->link_config.advertising;
3999         tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4000
4001         advmsk = ADVERTISE_ALL;
4002         if (tp->link_config.active_duplex == DUPLEX_FULL) {
4003                 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4004                 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4005         }
4006
4007         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4008                 return false;
4009
4010         if ((*lcladv & advmsk) != tgtadv)
4011                 return false;
4012
4013         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4014                 u32 tg3_ctrl;
4015
4016                 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4017
4018                 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4019                         return false;
4020
4021                 if (tgtadv &&
4022                     (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4023                      tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4024                         tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4025                         tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4026                                      CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4027                 } else {
4028                         tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4029                 }
4030
4031                 if (tg3_ctrl != tgtadv)
4032                         return false;
4033         }
4034
4035         return true;
4036 }
4037
4038 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4039 {
4040         u32 lpeth = 0;
4041
4042         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4043                 u32 val;
4044
4045                 if (tg3_readphy(tp, MII_STAT1000, &val))
4046                         return false;
4047
4048                 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4049         }
4050
4051         if (tg3_readphy(tp, MII_LPA, rmtadv))
4052                 return false;
4053
4054         lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4055         tp->link_config.rmt_adv = lpeth;
4056
4057         return true;
4058 }
4059
4060 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4061 {
4062         int current_link_up;
4063         u32 bmsr, val;
4064         u32 lcl_adv, rmt_adv;
4065         u16 current_speed;
4066         u8 current_duplex;
4067         int i, err;
4068
4069         tw32(MAC_EVENT, 0);
4070
4071         tw32_f(MAC_STATUS,
4072              (MAC_STATUS_SYNC_CHANGED |
4073               MAC_STATUS_CFG_CHANGED |
4074               MAC_STATUS_MI_COMPLETION |
4075               MAC_STATUS_LNKSTATE_CHANGED));
4076         udelay(40);
4077
4078         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4079                 tw32_f(MAC_MI_MODE,
4080                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4081                 udelay(80);
4082         }
4083
4084         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4085
4086         /* Some third-party PHYs need to be reset on link going
4087          * down.
4088          */
4089         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4090              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4091              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4092             netif_carrier_ok(tp->dev)) {
4093                 tg3_readphy(tp, MII_BMSR, &bmsr);
4094                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4095                     !(bmsr & BMSR_LSTATUS))
4096                         force_reset = 1;
4097         }
4098         if (force_reset)
4099                 tg3_phy_reset(tp);
4100
4101         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4102                 tg3_readphy(tp, MII_BMSR, &bmsr);
4103                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4104                     !tg3_flag(tp, INIT_COMPLETE))
4105                         bmsr = 0;
4106
4107                 if (!(bmsr & BMSR_LSTATUS)) {
4108                         err = tg3_init_5401phy_dsp(tp);
4109                         if (err)
4110                                 return err;
4111
4112                         tg3_readphy(tp, MII_BMSR, &bmsr);
4113                         for (i = 0; i < 1000; i++) {
4114                                 udelay(10);
4115                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4116                                     (bmsr & BMSR_LSTATUS)) {
4117                                         udelay(40);
4118                                         break;
4119                                 }
4120                         }
4121
4122                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4123                             TG3_PHY_REV_BCM5401_B0 &&
4124                             !(bmsr & BMSR_LSTATUS) &&
4125                             tp->link_config.active_speed == SPEED_1000) {
4126                                 err = tg3_phy_reset(tp);
4127                                 if (!err)
4128                                         err = tg3_init_5401phy_dsp(tp);
4129                                 if (err)
4130                                         return err;
4131                         }
4132                 }
4133         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4134                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4135                 /* 5701 {A0,B0} CRC bug workaround */
4136                 tg3_writephy(tp, 0x15, 0x0a75);
4137                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4139                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4140         }
4141
4142         /* Clear pending interrupts... */
4143         tg3_readphy(tp, MII_TG3_ISTAT, &val);
4144         tg3_readphy(tp, MII_TG3_ISTAT, &val);
4145
4146         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4147                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4148         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4149                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4150
4151         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4152             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4153                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4154                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
4155                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4156                 else
4157                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4158         }
4159
4160         current_link_up = 0;
4161         current_speed = SPEED_UNKNOWN;
4162         current_duplex = DUPLEX_UNKNOWN;
4163         tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4164         tp->link_config.rmt_adv = 0;
4165
4166         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4167                 err = tg3_phy_auxctl_read(tp,
4168                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4169                                           &val);
4170                 if (!err && !(val & (1 << 10))) {
4171                         tg3_phy_auxctl_write(tp,
4172                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4173                                              val | (1 << 10));
4174                         goto relink;
4175                 }
4176         }
4177
4178         bmsr = 0;
4179         for (i = 0; i < 100; i++) {
4180                 tg3_readphy(tp, MII_BMSR, &bmsr);
4181                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4182                     (bmsr & BMSR_LSTATUS))
4183                         break;
4184                 udelay(40);
4185         }
4186
4187         if (bmsr & BMSR_LSTATUS) {
4188                 u32 aux_stat, bmcr;
4189
4190                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4191                 for (i = 0; i < 2000; i++) {
4192                         udelay(10);
4193                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4194                             aux_stat)
4195                                 break;
4196                 }
4197
4198                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4199                                              &current_speed,
4200                                              &current_duplex);
4201
4202                 bmcr = 0;
4203                 for (i = 0; i < 200; i++) {
4204                         tg3_readphy(tp, MII_BMCR, &bmcr);
4205                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
4206                                 continue;
4207                         if (bmcr && bmcr != 0x7fff)
4208                                 break;
4209                         udelay(10);
4210                 }
4211
4212                 lcl_adv = 0;
4213                 rmt_adv = 0;
4214
4215                 tp->link_config.active_speed = current_speed;
4216                 tp->link_config.active_duplex = current_duplex;
4217
4218                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4219                         if ((bmcr & BMCR_ANENABLE) &&
4220                             tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4221                             tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4222                                 current_link_up = 1;
4223                 } else {
4224                         if (!(bmcr & BMCR_ANENABLE) &&
4225                             tp->link_config.speed == current_speed &&
4226                             tp->link_config.duplex == current_duplex &&
4227                             tp->link_config.flowctrl ==
4228                             tp->link_config.active_flowctrl) {
4229                                 current_link_up = 1;
4230                         }
4231                 }
4232
4233                 if (current_link_up == 1 &&
4234                     tp->link_config.active_duplex == DUPLEX_FULL) {
4235                         u32 reg, bit;
4236
4237                         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4238                                 reg = MII_TG3_FET_GEN_STAT;
4239                                 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4240                         } else {
4241                                 reg = MII_TG3_EXT_STAT;
4242                                 bit = MII_TG3_EXT_STAT_MDIX;
4243                         }
4244
4245                         if (!tg3_readphy(tp, reg, &val) && (val & bit))
4246                                 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4247
4248                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4249                 }
4250         }
4251
4252 relink:
4253         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4254                 tg3_phy_copper_begin(tp);
4255
4256                 tg3_readphy(tp, MII_BMSR, &bmsr);
4257                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4258                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4259                         current_link_up = 1;
4260         }
4261
4262         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4263         if (current_link_up == 1) {
4264                 if (tp->link_config.active_speed == SPEED_100 ||
4265                     tp->link_config.active_speed == SPEED_10)
4266                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4267                 else
4268                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4270                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4271         else
4272                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4273
4274         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4275         if (tp->link_config.active_duplex == DUPLEX_HALF)
4276                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4277
4278         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4279                 if (current_link_up == 1 &&
4280                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4281                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4282                 else
4283                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4284         }
4285
4286         /* ??? Without this setting Netgear GA302T PHY does not
4287          * ??? send/receive packets...
4288          */
4289         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4290             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4291                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4292                 tw32_f(MAC_MI_MODE, tp->mi_mode);
4293                 udelay(80);
4294         }
4295
4296         tw32_f(MAC_MODE, tp->mac_mode);
4297         udelay(40);
4298
4299         tg3_phy_eee_adjust(tp, current_link_up);
4300
4301         if (tg3_flag(tp, USE_LINKCHG_REG)) {
4302                 /* Polled via timer. */
4303                 tw32_f(MAC_EVENT, 0);
4304         } else {
4305                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4306         }
4307         udelay(40);
4308
4309         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4310             current_link_up == 1 &&
4311             tp->link_config.active_speed == SPEED_1000 &&
4312             (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4313                 udelay(120);
4314                 tw32_f(MAC_STATUS,
4315                      (MAC_STATUS_SYNC_CHANGED |
4316                       MAC_STATUS_CFG_CHANGED));
4317                 udelay(40);
4318                 tg3_write_mem(tp,
4319                               NIC_SRAM_FIRMWARE_MBOX,
4320                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4321         }
4322
4323         /* Prevent send BD corruption. */
4324         if (tg3_flag(tp, CLKREQ_BUG)) {
4325                 u16 oldlnkctl, newlnkctl;
4326
4327                 pci_read_config_word(tp->pdev,
4328                                      pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4329                                      &oldlnkctl);
4330                 if (tp->link_config.active_speed == SPEED_100 ||
4331                     tp->link_config.active_speed == SPEED_10)
4332                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4333                 else
4334                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4335                 if (newlnkctl != oldlnkctl)
4336                         pci_write_config_word(tp->pdev,
4337                                               pci_pcie_cap(tp->pdev) +
4338                                               PCI_EXP_LNKCTL, newlnkctl);
4339         }
4340
4341         if (current_link_up != netif_carrier_ok(tp->dev)) {
4342                 if (current_link_up)
4343                         netif_carrier_on(tp->dev);
4344                 else
4345                         netif_carrier_off(tp->dev);
4346                 tg3_link_report(tp);
4347         }
4348
4349         return 0;
4350 }
4351
4352 struct tg3_fiber_aneginfo {
4353         int state;
4354 #define ANEG_STATE_UNKNOWN              0
4355 #define ANEG_STATE_AN_ENABLE            1
4356 #define ANEG_STATE_RESTART_INIT         2
4357 #define ANEG_STATE_RESTART              3
4358 #define ANEG_STATE_DISABLE_LINK_OK      4
4359 #define ANEG_STATE_ABILITY_DETECT_INIT  5
4360 #define ANEG_STATE_ABILITY_DETECT       6
4361 #define ANEG_STATE_ACK_DETECT_INIT      7
4362 #define ANEG_STATE_ACK_DETECT           8
4363 #define ANEG_STATE_COMPLETE_ACK_INIT    9
4364 #define ANEG_STATE_COMPLETE_ACK         10
4365 #define ANEG_STATE_IDLE_DETECT_INIT     11
4366 #define ANEG_STATE_IDLE_DETECT          12
4367 #define ANEG_STATE_LINK_OK              13
4368 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
4369 #define ANEG_STATE_NEXT_PAGE_WAIT       15
4370
4371         u32 flags;
4372 #define MR_AN_ENABLE            0x00000001
4373 #define MR_RESTART_AN           0x00000002
4374 #define MR_AN_COMPLETE          0x00000004
4375 #define MR_PAGE_RX              0x00000008
4376 #define MR_NP_LOADED            0x00000010
4377 #define MR_TOGGLE_TX            0x00000020
4378 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
4379 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
4380 #define MR_LP_ADV_SYM_PAUSE     0x00000100
4381 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
4382 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4383 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4384 #define MR_LP_ADV_NEXT_PAGE     0x00001000
4385 #define MR_TOGGLE_RX            0x00002000
4386 #define MR_NP_RX                0x00004000
4387
4388 #define MR_LINK_OK              0x80000000
4389
4390         unsigned long link_time, cur_time;
4391
4392         u32 ability_match_cfg;
4393         int ability_match_count;
4394
4395         char ability_match, idle_match, ack_match;
4396
4397         u32 txconfig, rxconfig;
4398 #define ANEG_CFG_NP             0x00000080
4399 #define ANEG_CFG_ACK            0x00000040
4400 #define ANEG_CFG_RF2            0x00000020
4401 #define ANEG_CFG_RF1            0x00000010
4402 #define ANEG_CFG_PS2            0x00000001
4403 #define ANEG_CFG_PS1            0x00008000
4404 #define ANEG_CFG_HD             0x00004000
4405 #define ANEG_CFG_FD             0x00002000
4406 #define ANEG_CFG_INVAL          0x00001f06
4407
4408 };
4409 #define ANEG_OK         0
4410 #define ANEG_DONE       1
4411 #define ANEG_TIMER_ENAB 2
4412 #define ANEG_FAILED     -1
4413
4414 #define ANEG_STATE_SETTLE_TIME  10000
4415
4416 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4417                                    struct tg3_fiber_aneginfo *ap)
4418 {
4419         u16 flowctrl;
4420         unsigned long delta;
4421         u32 rx_cfg_reg;
4422         int ret;
4423
4424         if (ap->state == ANEG_STATE_UNKNOWN) {
4425                 ap->rxconfig = 0;
4426                 ap->link_time = 0;
4427                 ap->cur_time = 0;
4428                 ap->ability_match_cfg = 0;
4429                 ap->ability_match_count = 0;
4430                 ap->ability_match = 0;
4431                 ap->idle_match = 0;
4432                 ap->ack_match = 0;
4433         }
4434         ap->cur_time++;
4435
4436         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4437                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4438
4439                 if (rx_cfg_reg != ap->ability_match_cfg) {
4440                         ap->ability_match_cfg = rx_cfg_reg;
4441                         ap->ability_match = 0;
4442                         ap->ability_match_count = 0;
4443                 } else {
4444                         if (++ap->ability_match_count > 1) {
4445                                 ap->ability_match = 1;
4446                                 ap->ability_match_cfg = rx_cfg_reg;
4447                         }
4448                 }
4449                 if (rx_cfg_reg & ANEG_CFG_ACK)
4450                         ap->ack_match = 1;
4451                 else
4452                         ap->ack_match = 0;
4453
4454                 ap->idle_match = 0;
4455         } else {
4456                 ap->idle_match = 1;
4457                 ap->ability_match_cfg = 0;
4458                 ap->ability_match_count = 0;
4459                 ap->ability_match = 0;
4460                 ap->ack_match = 0;
4461
4462                 rx_cfg_reg = 0;
4463         }
4464
4465         ap->rxconfig = rx_cfg_reg;
4466         ret = ANEG_OK;
4467
4468         switch (ap->state) {
4469         case ANEG_STATE_UNKNOWN:
4470                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4471                         ap->state = ANEG_STATE_AN_ENABLE;
4472
4473                 /* fallthru */
4474         case ANEG_STATE_AN_ENABLE:
4475                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4476                 if (ap->flags & MR_AN_ENABLE) {
4477                         ap->link_time = 0;
4478                         ap->cur_time = 0;
4479                         ap->ability_match_cfg = 0;
4480                         ap->ability_match_count = 0;
4481                         ap->ability_match = 0;
4482                         ap->idle_match = 0;
4483                         ap->ack_match = 0;
4484
4485                         ap->state = ANEG_STATE_RESTART_INIT;
4486                 } else {
4487                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
4488                 }
4489                 break;
4490
4491         case ANEG_STATE_RESTART_INIT:
4492                 ap->link_time = ap->cur_time;
4493                 ap->flags &= ~(MR_NP_LOADED);
4494                 ap->txconfig = 0;
4495                 tw32(MAC_TX_AUTO_NEG, 0);
4496                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4497                 tw32_f(MAC_MODE, tp->mac_mode);
4498                 udelay(40);
4499
4500                 ret = ANEG_TIMER_ENAB;
4501                 ap->state = ANEG_STATE_RESTART;
4502
4503                 /* fallthru */
4504         case ANEG_STATE_RESTART:
4505                 delta = ap->cur_time - ap->link_time;
4506                 if (delta > ANEG_STATE_SETTLE_TIME)
4507                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4508                 else
4509                         ret = ANEG_TIMER_ENAB;
4510                 break;
4511
4512         case ANEG_STATE_DISABLE_LINK_OK:
4513                 ret = ANEG_DONE;
4514                 break;
4515
4516         case ANEG_STATE_ABILITY_DETECT_INIT:
4517                 ap->flags &= ~(MR_TOGGLE_TX);
4518                 ap->txconfig = ANEG_CFG_FD;
4519                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4520                 if (flowctrl & ADVERTISE_1000XPAUSE)
4521                         ap->txconfig |= ANEG_CFG_PS1;
4522                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4523                         ap->txconfig |= ANEG_CFG_PS2;
4524                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4525                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4526                 tw32_f(MAC_MODE, tp->mac_mode);
4527                 udelay(40);
4528
4529                 ap->state = ANEG_STATE_ABILITY_DETECT;
4530                 break;
4531
4532         case ANEG_STATE_ABILITY_DETECT:
4533                 if (ap->ability_match != 0 && ap->rxconfig != 0)
4534                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
4535                 break;
4536
4537         case ANEG_STATE_ACK_DETECT_INIT:
4538                 ap->txconfig |= ANEG_CFG_ACK;
4539                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4540                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4541                 tw32_f(MAC_MODE, tp->mac_mode);
4542                 udelay(40);
4543
4544                 ap->state = ANEG_STATE_ACK_DETECT;
4545
4546                 /* fallthru */
4547         case ANEG_STATE_ACK_DETECT:
4548                 if (ap->ack_match != 0) {
4549                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4550                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4551                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4552                         } else {
4553                                 ap->state = ANEG_STATE_AN_ENABLE;
4554                         }
4555                 } else if (ap->ability_match != 0 &&
4556                            ap->rxconfig == 0) {
4557                         ap->state = ANEG_STATE_AN_ENABLE;
4558                 }
4559                 break;
4560
4561         case ANEG_STATE_COMPLETE_ACK_INIT:
4562                 if (ap->rxconfig & ANEG_CFG_INVAL) {
4563                         ret = ANEG_FAILED;
4564                         break;
4565                 }
4566                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4567                                MR_LP_ADV_HALF_DUPLEX |
4568                                MR_LP_ADV_SYM_PAUSE |
4569                                MR_LP_ADV_ASYM_PAUSE |
4570                                MR_LP_ADV_REMOTE_FAULT1 |
4571                                MR_LP_ADV_REMOTE_FAULT2 |
4572                                MR_LP_ADV_NEXT_PAGE |
4573                                MR_TOGGLE_RX |
4574                                MR_NP_RX);
4575                 if (ap->rxconfig & ANEG_CFG_FD)
4576                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4577                 if (ap->rxconfig & ANEG_CFG_HD)
4578                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4579                 if (ap->rxconfig & ANEG_CFG_PS1)
4580                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
4581                 if (ap->rxconfig & ANEG_CFG_PS2)
4582                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4583                 if (ap->rxconfig & ANEG_CFG_RF1)
4584                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4585                 if (ap->rxconfig & ANEG_CFG_RF2)
4586                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4587                 if (ap->rxconfig & ANEG_CFG_NP)
4588                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
4589
4590                 ap->link_time = ap->cur_time;
4591
4592                 ap->flags ^= (MR_TOGGLE_TX);
4593                 if (ap->rxconfig & 0x0008)
4594                         ap->flags |= MR_TOGGLE_RX;
4595                 if (ap->rxconfig & ANEG_CFG_NP)
4596                         ap->flags |= MR_NP_RX;
4597                 ap->flags |= MR_PAGE_RX;
4598
4599                 ap->state = ANEG_STATE_COMPLETE_ACK;
4600                 ret = ANEG_TIMER_ENAB;
4601                 break;
4602
4603         case ANEG_STATE_COMPLETE_ACK:
4604                 if (ap->ability_match != 0 &&
4605                     ap->rxconfig == 0) {
4606                         ap->state = ANEG_STATE_AN_ENABLE;
4607                         break;
4608                 }
4609                 delta = ap->cur_time - ap->link_time;
4610                 if (delta > ANEG_STATE_SETTLE_TIME) {
4611                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4612                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4613                         } else {
4614                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4615                                     !(ap->flags & MR_NP_RX)) {
4616                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4617                                 } else {
4618                                         ret = ANEG_FAILED;
4619                                 }
4620                         }
4621                 }
4622                 break;
4623
4624         case ANEG_STATE_IDLE_DETECT_INIT:
4625                 ap->link_time = ap->cur_time;
4626                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4627                 tw32_f(MAC_MODE, tp->mac_mode);
4628                 udelay(40);
4629
4630                 ap->state = ANEG_STATE_IDLE_DETECT;
4631                 ret = ANEG_TIMER_ENAB;
4632                 break;
4633
4634         case ANEG_STATE_IDLE_DETECT:
4635                 if (ap->ability_match != 0 &&
4636                     ap->rxconfig == 0) {
4637                         ap->state = ANEG_STATE_AN_ENABLE;
4638                         break;
4639                 }
4640                 delta = ap->cur_time - ap->link_time;
4641                 if (delta > ANEG_STATE_SETTLE_TIME) {
4642                         /* XXX another gem from the Broadcom driver :( */
4643                         ap->state = ANEG_STATE_LINK_OK;
4644                 }
4645                 break;
4646
4647         case ANEG_STATE_LINK_OK:
4648                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4649                 ret = ANEG_DONE;
4650                 break;
4651
4652         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4653                 /* ??? unimplemented */
4654                 break;
4655
4656         case ANEG_STATE_NEXT_PAGE_WAIT:
4657                 /* ??? unimplemented */
4658                 break;
4659
4660         default:
4661                 ret = ANEG_FAILED;
4662                 break;
4663         }
4664
4665         return ret;
4666 }
4667
4668 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4669 {
4670         int res = 0;
4671         struct tg3_fiber_aneginfo aninfo;
4672         int status = ANEG_FAILED;
4673         unsigned int tick;
4674         u32 tmp;
4675
4676         tw32_f(MAC_TX_AUTO_NEG, 0);
4677
4678         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4679         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4680         udelay(40);
4681
4682         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4683         udelay(40);
4684
4685         memset(&aninfo, 0, sizeof(aninfo));
4686         aninfo.flags |= MR_AN_ENABLE;
4687         aninfo.state = ANEG_STATE_UNKNOWN;
4688         aninfo.cur_time = 0;
4689         tick = 0;
4690         while (++tick < 195000) {
4691                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4692                 if (status == ANEG_DONE || status == ANEG_FAILED)
4693                         break;
4694
4695                 udelay(1);
4696         }
4697
4698         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4699         tw32_f(MAC_MODE, tp->mac_mode);
4700         udelay(40);
4701
4702         *txflags = aninfo.txconfig;
4703         *rxflags = aninfo.flags;
4704
4705         if (status == ANEG_DONE &&
4706             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4707                              MR_LP_ADV_FULL_DUPLEX)))
4708                 res = 1;
4709
4710         return res;
4711 }
4712
4713 static void tg3_init_bcm8002(struct tg3 *tp)
4714 {
4715         u32 mac_status = tr32(MAC_STATUS);
4716         int i;
4717
4718         /* Reset when initting first time or we have a link. */
4719         if (tg3_flag(tp, INIT_COMPLETE) &&
4720             !(mac_status & MAC_STATUS_PCS_SYNCED))
4721                 return;
4722
4723         /* Set PLL lock range. */
4724         tg3_writephy(tp, 0x16, 0x8007);
4725
4726         /* SW reset */
4727         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4728
4729         /* Wait for reset to complete. */
4730         /* XXX schedule_timeout() ... */
4731         for (i = 0; i < 500; i++)
4732                 udelay(10);
4733
4734         /* Config mode; select PMA/Ch 1 regs. */
4735         tg3_writephy(tp, 0x10, 0x8411);
4736
4737         /* Enable auto-lock and comdet, select txclk for tx. */
4738         tg3_writephy(tp, 0x11, 0x0a10);
4739
4740         tg3_writephy(tp, 0x18, 0x00a0);
4741         tg3_writephy(tp, 0x16, 0x41ff);
4742
4743         /* Assert and deassert POR. */
4744         tg3_writephy(tp, 0x13, 0x0400);
4745         udelay(40);
4746         tg3_writephy(tp, 0x13, 0x0000);
4747
4748         tg3_writephy(tp, 0x11, 0x0a50);
4749         udelay(40);
4750         tg3_writephy(tp, 0x11, 0x0a10);
4751
4752         /* Wait for signal to stabilize */
4753         /* XXX schedule_timeout() ... */
4754         for (i = 0; i < 15000; i++)
4755                 udelay(10);
4756
4757         /* Deselect the channel register so we can read the PHYID
4758          * later.
4759          */
4760         tg3_writephy(tp, 0x10, 0x8011);
4761 }
4762
4763 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4764 {
4765         u16 flowctrl;
4766         u32 sg_dig_ctrl, sg_dig_status;
4767         u32 serdes_cfg, expected_sg_dig_ctrl;
4768         int workaround, port_a;
4769         int current_link_up;
4770
4771         serdes_cfg = 0;
4772         expected_sg_dig_ctrl = 0;
4773         workaround = 0;
4774         port_a = 1;
4775         current_link_up = 0;
4776
4777         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4778             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4779                 workaround = 1;
4780                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4781                         port_a = 0;
4782
4783                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4784                 /* preserve bits 20-23 for voltage regulator */
4785                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4786         }
4787
4788         sg_dig_ctrl = tr32(SG_DIG_CTRL);
4789
4790         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4791                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4792                         if (workaround) {
4793                                 u32 val = serdes_cfg;
4794
4795                                 if (port_a)
4796                                         val |= 0xc010000;
4797                                 else
4798                                         val |= 0x4010000;
4799                                 tw32_f(MAC_SERDES_CFG, val);
4800                         }
4801
4802                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4803                 }
4804                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4805                         tg3_setup_flow_control(tp, 0, 0);
4806                         current_link_up = 1;
4807                 }
4808                 goto out;
4809         }
4810
4811         /* Want auto-negotiation.  */
4812         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4813
4814         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4815         if (flowctrl & ADVERTISE_1000XPAUSE)
4816                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4817         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4818                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4819
4820         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4821                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4822                     tp->serdes_counter &&
4823                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
4824                                     MAC_STATUS_RCVD_CFG)) ==
4825                      MAC_STATUS_PCS_SYNCED)) {
4826                         tp->serdes_counter--;
4827                         current_link_up = 1;
4828                         goto out;
4829                 }
4830 restart_autoneg:
4831                 if (workaround)
4832                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4833                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4834                 udelay(5);
4835                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4836
4837                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4838                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4839         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4840                                  MAC_STATUS_SIGNAL_DET)) {
4841                 sg_dig_status = tr32(SG_DIG_STATUS);
4842                 mac_status = tr32(MAC_STATUS);
4843
4844                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4845                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
4846                         u32 local_adv = 0, remote_adv = 0;
4847
4848                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4849                                 local_adv |= ADVERTISE_1000XPAUSE;
4850                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4851                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4852
4853                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4854                                 remote_adv |= LPA_1000XPAUSE;
4855                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4856                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4857
4858                         tp->link_config.rmt_adv =
4859                                            mii_adv_to_ethtool_adv_x(remote_adv);
4860
4861                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4862                         current_link_up = 1;
4863                         tp->serdes_counter = 0;
4864                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4865                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4866                         if (tp->serdes_counter)
4867                                 tp->serdes_counter--;
4868                         else {
4869                                 if (workaround) {
4870                                         u32 val = serdes_cfg;
4871
4872                                         if (port_a)
4873                                                 val |= 0xc010000;
4874                                         else
4875                                                 val |= 0x4010000;
4876
4877                                         tw32_f(MAC_SERDES_CFG, val);
4878                                 }
4879
4880                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4881                                 udelay(40);
4882
4883                                 /* Link parallel detection - link is up */
4884                                 /* only if we have PCS_SYNC and not */
4885                                 /* receiving config code words */
4886                                 mac_status = tr32(MAC_STATUS);
4887                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4888                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
4889                                         tg3_setup_flow_control(tp, 0, 0);
4890                                         current_link_up = 1;
4891                                         tp->phy_flags |=
4892                                                 TG3_PHYFLG_PARALLEL_DETECT;
4893                                         tp->serdes_counter =
4894                                                 SERDES_PARALLEL_DET_TIMEOUT;
4895                                 } else
4896                                         goto restart_autoneg;
4897                         }
4898                 }
4899         } else {
4900                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4901                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4902         }
4903
4904 out:
4905         return current_link_up;
4906 }
4907
4908 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4909 {
4910         int current_link_up = 0;
4911
4912         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4913                 goto out;
4914
4915         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4916                 u32 txflags, rxflags;
4917                 int i;
4918
4919                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4920                         u32 local_adv = 0, remote_adv = 0;
4921
4922                         if (txflags & ANEG_CFG_PS1)
4923                                 local_adv |= ADVERTISE_1000XPAUSE;
4924                         if (txflags & ANEG_CFG_PS2)
4925                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4926
4927                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4928                                 remote_adv |= LPA_1000XPAUSE;
4929                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4930                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4931
4932                         tp->link_config.rmt_adv =
4933                                            mii_adv_to_ethtool_adv_x(remote_adv);
4934
4935                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4936
4937                         current_link_up = 1;
4938                 }
4939                 for (i = 0; i < 30; i++) {
4940                         udelay(20);
4941                         tw32_f(MAC_STATUS,
4942                                (MAC_STATUS_SYNC_CHANGED |
4943                                 MAC_STATUS_CFG_CHANGED));
4944                         udelay(40);
4945                         if ((tr32(MAC_STATUS) &
4946                              (MAC_STATUS_SYNC_CHANGED |
4947                               MAC_STATUS_CFG_CHANGED)) == 0)
4948                                 break;
4949                 }
4950
4951                 mac_status = tr32(MAC_STATUS);
4952                 if (current_link_up == 0 &&
4953                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4954                     !(mac_status & MAC_STATUS_RCVD_CFG))
4955                         current_link_up = 1;
4956         } else {
4957                 tg3_setup_flow_control(tp, 0, 0);
4958
4959                 /* Forcing 1000FD link up. */
4960                 current_link_up = 1;
4961
4962                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4963                 udelay(40);
4964
4965                 tw32_f(MAC_MODE, tp->mac_mode);
4966                 udelay(40);
4967         }
4968
4969 out:
4970         return current_link_up;
4971 }
4972
4973 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4974 {
4975         u32 orig_pause_cfg;
4976         u16 orig_active_speed;
4977         u8 orig_active_duplex;
4978         u32 mac_status;
4979         int current_link_up;
4980         int i;
4981
4982         orig_pause_cfg = tp->link_config.active_flowctrl;
4983         orig_active_speed = tp->link_config.active_speed;
4984         orig_active_duplex = tp->link_config.active_duplex;
4985
4986         if (!tg3_flag(tp, HW_AUTONEG) &&
4987             netif_carrier_ok(tp->dev) &&
4988             tg3_flag(tp, INIT_COMPLETE)) {
4989                 mac_status = tr32(MAC_STATUS);
4990                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4991                                MAC_STATUS_SIGNAL_DET |
4992                                MAC_STATUS_CFG_CHANGED |
4993                                MAC_STATUS_RCVD_CFG);
4994                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4995                                    MAC_STATUS_SIGNAL_DET)) {
4996                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4997                                             MAC_STATUS_CFG_CHANGED));
4998                         return 0;
4999                 }
5000         }
5001
5002         tw32_f(MAC_TX_AUTO_NEG, 0);
5003
5004         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5005         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5006         tw32_f(MAC_MODE, tp->mac_mode);
5007         udelay(40);
5008
5009         if (tp->phy_id == TG3_PHY_ID_BCM8002)
5010                 tg3_init_bcm8002(tp);
5011
5012         /* Enable link change event even when serdes polling.  */
5013         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5014         udelay(40);
5015
5016         current_link_up = 0;
5017         tp->link_config.rmt_adv = 0;
5018         mac_status = tr32(MAC_STATUS);
5019
5020         if (tg3_flag(tp, HW_AUTONEG))
5021                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5022         else
5023                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5024
5025         tp->napi[0].hw_status->status =
5026                 (SD_STATUS_UPDATED |
5027                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5028
5029         for (i = 0; i < 100; i++) {
5030                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5031                                     MAC_STATUS_CFG_CHANGED));
5032                 udelay(5);
5033                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5034                                          MAC_STATUS_CFG_CHANGED |
5035                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5036                         break;
5037         }
5038
5039         mac_status = tr32(MAC_STATUS);
5040         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5041                 current_link_up = 0;
5042                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5043                     tp->serdes_counter == 0) {
5044                         tw32_f(MAC_MODE, (tp->mac_mode |
5045                                           MAC_MODE_SEND_CONFIGS));
5046                         udelay(1);
5047                         tw32_f(MAC_MODE, tp->mac_mode);
5048                 }
5049         }
5050
5051         if (current_link_up == 1) {
5052                 tp->link_config.active_speed = SPEED_1000;
5053                 tp->link_config.active_duplex = DUPLEX_FULL;
5054                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5055                                     LED_CTRL_LNKLED_OVERRIDE |
5056                                     LED_CTRL_1000MBPS_ON));
5057         } else {
5058                 tp->link_config.active_speed = SPEED_UNKNOWN;
5059                 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5060                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5061                                     LED_CTRL_LNKLED_OVERRIDE |
5062                                     LED_CTRL_TRAFFIC_OVERRIDE));
5063         }
5064
5065         if (current_link_up != netif_carrier_ok(tp->dev)) {
5066                 if (current_link_up)
5067                         netif_carrier_on(tp->dev);
5068                 else
5069                         netif_carrier_off(tp->dev);
5070                 tg3_link_report(tp);
5071         } else {
5072                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5073                 if (orig_pause_cfg != now_pause_cfg ||
5074                     orig_active_speed != tp->link_config.active_speed ||
5075                     orig_active_duplex != tp->link_config.active_duplex)
5076                         tg3_link_report(tp);
5077         }
5078
5079         return 0;
5080 }
5081
5082 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5083 {
5084         int current_link_up, err = 0;
5085         u32 bmsr, bmcr;
5086         u16 current_speed;
5087         u8 current_duplex;
5088         u32 local_adv, remote_adv;
5089
5090         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5091         tw32_f(MAC_MODE, tp->mac_mode);
5092         udelay(40);
5093
5094         tw32(MAC_EVENT, 0);
5095
5096         tw32_f(MAC_STATUS,
5097              (MAC_STATUS_SYNC_CHANGED |
5098               MAC_STATUS_CFG_CHANGED |
5099               MAC_STATUS_MI_COMPLETION |
5100               MAC_STATUS_LNKSTATE_CHANGED));
5101         udelay(40);
5102
5103         if (force_reset)
5104                 tg3_phy_reset(tp);
5105
5106         current_link_up = 0;
5107         current_speed = SPEED_UNKNOWN;
5108         current_duplex = DUPLEX_UNKNOWN;
5109         tp->link_config.rmt_adv = 0;
5110
5111         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5112         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5113         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5114                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5115                         bmsr |= BMSR_LSTATUS;
5116                 else
5117                         bmsr &= ~BMSR_LSTATUS;
5118         }
5119
5120         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5121
5122         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5123             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5124                 /* do nothing, just check for link up at the end */
5125         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5126                 u32 adv, newadv;
5127
5128                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5129                 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5130                                  ADVERTISE_1000XPAUSE |
5131                                  ADVERTISE_1000XPSE_ASYM |
5132                                  ADVERTISE_SLCT);
5133
5134                 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5135                 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5136
5137                 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5138                         tg3_writephy(tp, MII_ADVERTISE, newadv);
5139                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5140                         tg3_writephy(tp, MII_BMCR, bmcr);
5141
5142                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5143                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5144                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5145
5146                         return err;
5147                 }
5148         } else {
5149                 u32 new_bmcr;
5150
5151                 bmcr &= ~BMCR_SPEED1000;
5152                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5153
5154                 if (tp->link_config.duplex == DUPLEX_FULL)
5155                         new_bmcr |= BMCR_FULLDPLX;
5156
5157                 if (new_bmcr != bmcr) {
5158                         /* BMCR_SPEED1000 is a reserved bit that needs
5159                          * to be set on write.
5160                          */
5161                         new_bmcr |= BMCR_SPEED1000;
5162
5163                         /* Force a linkdown */
5164                         if (netif_carrier_ok(tp->dev)) {
5165                                 u32 adv;
5166
5167                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5168                                 adv &= ~(ADVERTISE_1000XFULL |
5169                                          ADVERTISE_1000XHALF |
5170                                          ADVERTISE_SLCT);
5171                                 tg3_writephy(tp, MII_ADVERTISE, adv);
5172                                 tg3_writephy(tp, MII_BMCR, bmcr |
5173                                                            BMCR_ANRESTART |
5174                                                            BMCR_ANENABLE);
5175                                 udelay(10);
5176                                 netif_carrier_off(tp->dev);
5177                         }
5178                         tg3_writephy(tp, MII_BMCR, new_bmcr);
5179                         bmcr = new_bmcr;
5180                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5181                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5182                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5183                             ASIC_REV_5714) {
5184                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5185                                         bmsr |= BMSR_LSTATUS;
5186                                 else
5187                                         bmsr &= ~BMSR_LSTATUS;
5188                         }
5189                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5190                 }
5191         }
5192
5193         if (bmsr & BMSR_LSTATUS) {
5194                 current_speed = SPEED_1000;
5195                 current_link_up = 1;
5196                 if (bmcr & BMCR_FULLDPLX)
5197                         current_duplex = DUPLEX_FULL;
5198                 else
5199                         current_duplex = DUPLEX_HALF;
5200
5201                 local_adv = 0;
5202                 remote_adv = 0;
5203
5204                 if (bmcr & BMCR_ANENABLE) {
5205                         u32 common;
5206
5207                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5208                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5209                         common = local_adv & remote_adv;
5210                         if (common & (ADVERTISE_1000XHALF |
5211                                       ADVERTISE_1000XFULL)) {
5212                                 if (common & ADVERTISE_1000XFULL)
5213                                         current_duplex = DUPLEX_FULL;
5214                                 else
5215                                         current_duplex = DUPLEX_HALF;
5216
5217                                 tp->link_config.rmt_adv =
5218                                            mii_adv_to_ethtool_adv_x(remote_adv);
5219                         } else if (!tg3_flag(tp, 5780_CLASS)) {
5220                                 /* Link is up via parallel detect */
5221                         } else {
5222                                 current_link_up = 0;
5223                         }
5224                 }
5225         }
5226
5227         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5228                 tg3_setup_flow_control(tp, local_adv, remote_adv);
5229
5230         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5231         if (tp->link_config.active_duplex == DUPLEX_HALF)
5232                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5233
5234         tw32_f(MAC_MODE, tp->mac_mode);
5235         udelay(40);
5236
5237         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5238
5239         tp->link_config.active_speed = current_speed;
5240         tp->link_config.active_duplex = current_duplex;
5241
5242         if (current_link_up != netif_carrier_ok(tp->dev)) {
5243                 if (current_link_up)
5244                         netif_carrier_on(tp->dev);
5245                 else {
5246                         netif_carrier_off(tp->dev);
5247                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5248                 }
5249                 tg3_link_report(tp);
5250         }
5251         return err;
5252 }
5253
5254 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5255 {
5256         if (tp->serdes_counter) {
5257                 /* Give autoneg time to complete. */
5258                 tp->serdes_counter--;
5259                 return;
5260         }
5261
5262         if (!netif_carrier_ok(tp->dev) &&
5263             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5264                 u32 bmcr;
5265
5266                 tg3_readphy(tp, MII_BMCR, &bmcr);
5267                 if (bmcr & BMCR_ANENABLE) {
5268                         u32 phy1, phy2;
5269
5270                         /* Select shadow register 0x1f */
5271                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5272                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5273
5274                         /* Select expansion interrupt status register */
5275                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5276                                          MII_TG3_DSP_EXP1_INT_STAT);
5277                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5278                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5279
5280                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5281                                 /* We have signal detect and not receiving
5282                                  * config code words, link is up by parallel
5283                                  * detection.
5284                                  */
5285
5286                                 bmcr &= ~BMCR_ANENABLE;
5287                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5288                                 tg3_writephy(tp, MII_BMCR, bmcr);
5289                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5290                         }
5291                 }
5292         } else if (netif_carrier_ok(tp->dev) &&
5293                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5294                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5295                 u32 phy2;
5296
5297                 /* Select expansion interrupt status register */
5298                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5299                                  MII_TG3_DSP_EXP1_INT_STAT);
5300                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5301                 if (phy2 & 0x20) {
5302                         u32 bmcr;
5303
5304                         /* Config code words received, turn on autoneg. */
5305                         tg3_readphy(tp, MII_BMCR, &bmcr);
5306                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5307
5308                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5309
5310                 }
5311         }
5312 }
5313
5314 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5315 {
5316         u32 val;
5317         int err;
5318
5319         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5320                 err = tg3_setup_fiber_phy(tp, force_reset);
5321         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5322                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5323         else
5324                 err = tg3_setup_copper_phy(tp, force_reset);
5325
5326         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5327                 u32 scale;
5328
5329                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5330                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5331                         scale = 65;
5332                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5333                         scale = 6;
5334                 else
5335                         scale = 12;
5336
5337                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5338                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5339                 tw32(GRC_MISC_CFG, val);
5340         }
5341
5342         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5343               (6 << TX_LENGTHS_IPG_SHIFT);
5344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5345                 val |= tr32(MAC_TX_LENGTHS) &
5346                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
5347                         TX_LENGTHS_CNT_DWN_VAL_MSK);
5348
5349         if (tp->link_config.active_speed == SPEED_1000 &&
5350             tp->link_config.active_duplex == DUPLEX_HALF)
5351                 tw32(MAC_TX_LENGTHS, val |
5352                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5353         else
5354                 tw32(MAC_TX_LENGTHS, val |
5355                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5356
5357         if (!tg3_flag(tp, 5705_PLUS)) {
5358                 if (netif_carrier_ok(tp->dev)) {
5359                         tw32(HOSTCC_STAT_COAL_TICKS,
5360                              tp->coal.stats_block_coalesce_usecs);
5361                 } else {
5362                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
5363                 }
5364         }
5365
5366         if (tg3_flag(tp, ASPM_WORKAROUND)) {
5367                 val = tr32(PCIE_PWR_MGMT_THRESH);
5368                 if (!netif_carrier_ok(tp->dev))
5369                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5370                               tp->pwrmgmt_thresh;
5371                 else
5372                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5373                 tw32(PCIE_PWR_MGMT_THRESH, val);
5374         }
5375
5376         return err;
5377 }
5378
5379 static inline int tg3_irq_sync(struct tg3 *tp)
5380 {
5381         return tp->irq_sync;
5382 }
5383
5384 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5385 {
5386         int i;
5387
5388         dst = (u32 *)((u8 *)dst + off);
5389         for (i = 0; i < len; i += sizeof(u32))
5390                 *dst++ = tr32(off + i);
5391 }
5392
5393 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5394 {
5395         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5396         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5397         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5398         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5399         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5400         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5401         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5402         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5403         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5404         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5405         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5406         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5407         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5408         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5409         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5410         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5411         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5412         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5413         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5414
5415         if (tg3_flag(tp, SUPPORT_MSIX))
5416                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5417
5418         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5419         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5420         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5421         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5422         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5423         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5424         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5425         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5426
5427         if (!tg3_flag(tp, 5705_PLUS)) {
5428                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5429                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5430                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5431         }
5432
5433         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5434         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5435         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5436         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5437         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5438
5439         if (tg3_flag(tp, NVRAM))
5440                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5441 }
5442
5443 static void tg3_dump_state(struct tg3 *tp)
5444 {
5445         int i;
5446         u32 *regs;
5447
5448         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5449         if (!regs) {
5450                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5451                 return;
5452         }
5453
5454         if (tg3_flag(tp, PCI_EXPRESS)) {
5455                 /* Read up to but not including private PCI registers */
5456                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5457                         regs[i / sizeof(u32)] = tr32(i);
5458         } else
5459                 tg3_dump_legacy_regs(tp, regs);
5460
5461         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5462                 if (!regs[i + 0] && !regs[i + 1] &&
5463                     !regs[i + 2] && !regs[i + 3])
5464                         continue;
5465
5466                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5467                            i * 4,
5468                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5469         }
5470
5471         kfree(regs);
5472
5473         for (i = 0; i < tp->irq_cnt; i++) {
5474                 struct tg3_napi *tnapi = &tp->napi[i];
5475
5476                 /* SW status block */
5477                 netdev_err(tp->dev,
5478                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5479                            i,
5480                            tnapi->hw_status->status,
5481                            tnapi->hw_status->status_tag,
5482                            tnapi->hw_status->rx_jumbo_consumer,
5483                            tnapi->hw_status->rx_consumer,
5484                            tnapi->hw_status->rx_mini_consumer,
5485                            tnapi->hw_status->idx[0].rx_producer,
5486                            tnapi->hw_status->idx[0].tx_consumer);
5487
5488                 netdev_err(tp->dev,
5489                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5490                            i,
5491                            tnapi->last_tag, tnapi->last_irq_tag,
5492                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5493                            tnapi->rx_rcb_ptr,
5494                            tnapi->prodring.rx_std_prod_idx,
5495                            tnapi->prodring.rx_std_cons_idx,
5496                            tnapi->prodring.rx_jmb_prod_idx,
5497                            tnapi->prodring.rx_jmb_cons_idx);
5498         }
5499 }
5500
5501 /* This is called whenever we suspect that the system chipset is re-
5502  * ordering the sequence of MMIO to the tx send mailbox. The symptom
5503  * is bogus tx completions. We try to recover by setting the
5504  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5505  * in the workqueue.
5506  */
5507 static void tg3_tx_recover(struct tg3 *tp)
5508 {
5509         BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5510                tp->write32_tx_mbox == tg3_write_indirect_mbox);
5511
5512         netdev_warn(tp->dev,
5513                     "The system may be re-ordering memory-mapped I/O "
5514                     "cycles to the network device, attempting to recover. "
5515                     "Please report the problem to the driver maintainer "
5516                     "and include system chipset information.\n");
5517
5518         spin_lock(&tp->lock);
5519         tg3_flag_set(tp, TX_RECOVERY_PENDING);
5520         spin_unlock(&tp->lock);
5521 }
5522
5523 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5524 {
5525         /* Tell compiler to fetch tx indices from memory. */
5526         barrier();
5527         return tnapi->tx_pending -
5528                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5529 }
5530
5531 /* Tigon3 never reports partial packet sends.  So we do not
5532  * need special logic to handle SKBs that have not had all
5533  * of their frags sent yet, like SunGEM does.
5534  */
5535 static void tg3_tx(struct tg3_napi *tnapi)
5536 {
5537         struct tg3 *tp = tnapi->tp;
5538         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5539         u32 sw_idx = tnapi->tx_cons;
5540         struct netdev_queue *txq;
5541         int index = tnapi - tp->napi;
5542         unsigned int pkts_compl = 0, bytes_compl = 0;
5543
5544         if (tg3_flag(tp, ENABLE_TSS))
5545                 index--;
5546
5547         txq = netdev_get_tx_queue(tp->dev, index);
5548
5549         while (sw_idx != hw_idx) {
5550                 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5551                 struct sk_buff *skb = ri->skb;
5552                 int i, tx_bug = 0;
5553
5554                 if (unlikely(skb == NULL)) {
5555                         tg3_tx_recover(tp);
5556                         return;
5557                 }
5558
5559                 pci_unmap_single(tp->pdev,
5560                                  dma_unmap_addr(ri, mapping),
5561                                  skb_headlen(skb),
5562                                  PCI_DMA_TODEVICE);
5563
5564                 ri->skb = NULL;
5565
5566                 while (ri->fragmented) {
5567                         ri->fragmented = false;
5568                         sw_idx = NEXT_TX(sw_idx);
5569                         ri = &tnapi->tx_buffers[sw_idx];
5570                 }
5571
5572                 sw_idx = NEXT_TX(sw_idx);
5573
5574                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5575                         ri = &tnapi->tx_buffers[sw_idx];
5576                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5577                                 tx_bug = 1;
5578
5579                         pci_unmap_page(tp->pdev,
5580                                        dma_unmap_addr(ri, mapping),
5581                                        skb_frag_size(&skb_shinfo(skb)->frags[i]),
5582                                        PCI_DMA_TODEVICE);
5583
5584                         while (ri->fragmented) {
5585                                 ri->fragmented = false;
5586                                 sw_idx = NEXT_TX(sw_idx);
5587                                 ri = &tnapi->tx_buffers[sw_idx];
5588                         }
5589
5590                         sw_idx = NEXT_TX(sw_idx);
5591                 }
5592
5593                 pkts_compl++;
5594                 bytes_compl += skb->len;
5595
5596                 dev_kfree_skb(skb);
5597
5598                 if (unlikely(tx_bug)) {
5599                         tg3_tx_recover(tp);
5600                         return;
5601                 }
5602         }
5603
5604         netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
5605
5606         tnapi->tx_cons = sw_idx;
5607
5608         /* Need to make the tx_cons update visible to tg3_start_xmit()
5609          * before checking for netif_queue_stopped().  Without the
5610          * memory barrier, there is a small possibility that tg3_start_xmit()
5611          * will miss it and cause the queue to be stopped forever.
5612          */
5613         smp_mb();
5614
5615         if (unlikely(netif_tx_queue_stopped(txq) &&
5616                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5617                 __netif_tx_lock(txq, smp_processor_id());
5618                 if (netif_tx_queue_stopped(txq) &&
5619                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5620                         netif_tx_wake_queue(txq);
5621                 __netif_tx_unlock(txq);
5622         }
5623 }
5624
5625 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5626 {
5627         if (!ri->data)
5628                 return;
5629
5630         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5631                          map_sz, PCI_DMA_FROMDEVICE);
5632         kfree(ri->data);
5633         ri->data = NULL;
5634 }
5635
5636 /* Returns size of skb allocated or < 0 on error.
5637  *
5638  * We only need to fill in the address because the other members
5639  * of the RX descriptor are invariant, see tg3_init_rings.
5640  *
5641  * Note the purposeful assymetry of cpu vs. chip accesses.  For
5642  * posting buffers we only dirty the first cache line of the RX
5643  * descriptor (containing the address).  Whereas for the RX status
5644  * buffers the cpu only reads the last cacheline of the RX descriptor
5645  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5646  */
5647 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5648                             u32 opaque_key, u32 dest_idx_unmasked)
5649 {
5650         struct tg3_rx_buffer_desc *desc;
5651         struct ring_info *map;
5652         u8 *data;
5653         dma_addr_t mapping;
5654         int skb_size, data_size, dest_idx;
5655
5656         switch (opaque_key) {
5657         case RXD_OPAQUE_RING_STD:
5658                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5659                 desc = &tpr->rx_std[dest_idx];
5660                 map = &tpr->rx_std_buffers[dest_idx];
5661                 data_size = tp->rx_pkt_map_sz;
5662                 break;
5663
5664         case RXD_OPAQUE_RING_JUMBO:
5665                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5666                 desc = &tpr->rx_jmb[dest_idx].std;
5667                 map = &tpr->rx_jmb_buffers[dest_idx];
5668                 data_size = TG3_RX_JMB_MAP_SZ;
5669                 break;
5670
5671         default:
5672                 return -EINVAL;
5673         }
5674
5675         /* Do not overwrite any of the map or rp information
5676          * until we are sure we can commit to a new buffer.
5677          *
5678          * Callers depend upon this behavior and assume that
5679          * we leave everything unchanged if we fail.
5680          */
5681         skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5682                    SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5683         data = kmalloc(skb_size, GFP_ATOMIC);
5684         if (!data)
5685                 return -ENOMEM;
5686
5687         mapping = pci_map_single(tp->pdev,
5688                                  data + TG3_RX_OFFSET(tp),
5689                                  data_size,
5690                                  PCI_DMA_FROMDEVICE);
5691         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5692                 kfree(data);
5693                 return -EIO;
5694         }
5695
5696         map->data = data;
5697         dma_unmap_addr_set(map, mapping, mapping);
5698
5699         desc->addr_hi = ((u64)mapping >> 32);
5700         desc->addr_lo = ((u64)mapping & 0xffffffff);
5701
5702         return data_size;
5703 }
5704
5705 /* We only need to move over in the address because the other
5706  * members of the RX descriptor are invariant.  See notes above
5707  * tg3_alloc_rx_data for full details.
5708  */
5709 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5710                            struct tg3_rx_prodring_set *dpr,
5711                            u32 opaque_key, int src_idx,
5712                            u32 dest_idx_unmasked)
5713 {
5714         struct tg3 *tp = tnapi->tp;
5715         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5716         struct ring_info *src_map, *dest_map;
5717         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5718         int dest_idx;
5719
5720         switch (opaque_key) {
5721         case RXD_OPAQUE_RING_STD:
5722                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5723                 dest_desc = &dpr->rx_std[dest_idx];
5724                 dest_map = &dpr->rx_std_buffers[dest_idx];
5725                 src_desc = &spr->rx_std[src_idx];
5726                 src_map = &spr->rx_std_buffers[src_idx];
5727                 break;
5728
5729         case RXD_OPAQUE_RING_JUMBO:
5730                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5731                 dest_desc = &dpr->rx_jmb[dest_idx].std;
5732                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5733                 src_desc = &spr->rx_jmb[src_idx].std;
5734                 src_map = &spr->rx_jmb_buffers[src_idx];
5735                 break;
5736
5737         default:
5738                 return;
5739         }
5740
5741         dest_map->data = src_map->data;
5742         dma_unmap_addr_set(dest_map, mapping,
5743                            dma_unmap_addr(src_map, mapping));
5744         dest_desc->addr_hi = src_desc->addr_hi;
5745         dest_desc->addr_lo = src_desc->addr_lo;
5746
5747         /* Ensure that the update to the skb happens after the physical
5748          * addresses have been transferred to the new BD location.
5749          */
5750         smp_wmb();
5751
5752         src_map->data = NULL;
5753 }
5754
5755 /* The RX ring scheme is composed of multiple rings which post fresh
5756  * buffers to the chip, and one special ring the chip uses to report
5757  * status back to the host.
5758  *
5759  * The special ring reports the status of received packets to the
5760  * host.  The chip does not write into the original descriptor the
5761  * RX buffer was obtained from.  The chip simply takes the original
5762  * descriptor as provided by the host, updates the status and length
5763  * field, then writes this into the next status ring entry.
5764  *
5765  * Each ring the host uses to post buffers to the chip is described
5766  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
5767  * it is first placed into the on-chip ram.  When the packet's length
5768  * is known, it walks down the TG3_BDINFO entries to select the ring.
5769  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5770  * which is within the range of the new packet's length is chosen.
5771  *
5772  * The "separate ring for rx status" scheme may sound queer, but it makes
5773  * sense from a cache coherency perspective.  If only the host writes
5774  * to the buffer post rings, and only the chip writes to the rx status
5775  * rings, then cache lines never move beyond shared-modified state.
5776  * If both the host and chip were to write into the same ring, cache line
5777  * eviction could occur since both entities want it in an exclusive state.
5778  */
5779 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5780 {
5781         struct tg3 *tp = tnapi->tp;
5782         u32 work_mask, rx_std_posted = 0;
5783         u32 std_prod_idx, jmb_prod_idx;
5784         u32 sw_idx = tnapi->rx_rcb_ptr;
5785         u16 hw_idx;
5786         int received;
5787         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5788
5789         hw_idx = *(tnapi->rx_rcb_prod_idx);
5790         /*
5791          * We need to order the read of hw_idx and the read of
5792          * the opaque cookie.
5793          */
5794         rmb();
5795         work_mask = 0;
5796         received = 0;
5797         std_prod_idx = tpr->rx_std_prod_idx;
5798         jmb_prod_idx = tpr->rx_jmb_prod_idx;
5799         while (sw_idx != hw_idx && budget > 0) {
5800                 struct ring_info *ri;
5801                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5802                 unsigned int len;
5803                 struct sk_buff *skb;
5804                 dma_addr_t dma_addr;
5805                 u32 opaque_key, desc_idx, *post_ptr;
5806                 u8 *data;
5807
5808                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5809                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5810                 if (opaque_key == RXD_OPAQUE_RING_STD) {
5811                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5812                         dma_addr = dma_unmap_addr(ri, mapping);
5813                         data = ri->data;
5814                         post_ptr = &std_prod_idx;
5815                         rx_std_posted++;
5816                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5817                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5818                         dma_addr = dma_unmap_addr(ri, mapping);
5819                         data = ri->data;
5820                         post_ptr = &jmb_prod_idx;
5821                 } else
5822                         goto next_pkt_nopost;
5823
5824                 work_mask |= opaque_key;
5825
5826                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5827                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5828                 drop_it:
5829                         tg3_recycle_rx(tnapi, tpr, opaque_key,
5830                                        desc_idx, *post_ptr);
5831                 drop_it_no_recycle:
5832                         /* Other statistics kept track of by card. */
5833                         tp->rx_dropped++;
5834                         goto next_pkt;
5835                 }
5836
5837                 prefetch(data + TG3_RX_OFFSET(tp));
5838                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5839                       ETH_FCS_LEN;
5840
5841                 if (len > TG3_RX_COPY_THRESH(tp)) {
5842                         int skb_size;
5843
5844                         skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5845                                                     *post_ptr);
5846                         if (skb_size < 0)
5847                                 goto drop_it;
5848
5849                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
5850                                          PCI_DMA_FROMDEVICE);
5851
5852                         skb = build_skb(data);
5853                         if (!skb) {
5854                                 kfree(data);
5855                                 goto drop_it_no_r