1 /* Copyright 2008-2011 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
31 /********************************************************/
33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
34 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
35 #define ETH_MIN_PACKET_SIZE 60
36 #define ETH_MAX_PACKET_SIZE 1500
37 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
38 #define MDIO_ACCESS_TIMEOUT 1000
39 #define BMAC_CONTROL_RX_ENABLE 2
41 #define I2C_SWITCH_WIDTH 2
44 #define I2C_WA_RETRY_CNT 3
45 #define MCPR_IMC_COMMAND_READ_OP 1
46 #define MCPR_IMC_COMMAND_WRITE_OP 2
48 /* LED Blink rate that will achieve ~15.9Hz */
49 #define LED_BLINK_RATE_VAL_E3 354
50 #define LED_BLINK_RATE_VAL_E1X_E2 480
51 /***********************************************************/
52 /* Shortcut definitions */
53 /***********************************************************/
55 #define NIG_LATCH_BC_ENABLE_MI_INT 0
57 #define NIG_STATUS_EMAC0_MI_INT \
58 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
59 #define NIG_STATUS_XGXS0_LINK10G \
60 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
61 #define NIG_STATUS_XGXS0_LINK_STATUS \
62 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
63 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
64 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
65 #define NIG_STATUS_SERDES0_LINK_STATUS \
66 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
67 #define NIG_MASK_MI_INT \
68 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
69 #define NIG_MASK_XGXS0_LINK10G \
70 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
71 #define NIG_MASK_XGXS0_LINK_STATUS \
72 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
73 #define NIG_MASK_SERDES0_LINK_STATUS \
74 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
76 #define MDIO_AN_CL73_OR_37_COMPLETE \
77 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
78 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
80 #define XGXS_RESET_BITS \
81 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
87 #define SERDES_RESET_BITS \
88 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
91 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
93 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
94 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
95 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
96 #define AUTONEG_PARALLEL \
97 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
98 #define AUTONEG_SGMII_FIBER_AUTODET \
99 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
100 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
102 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
104 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
106 #define GP_STATUS_SPEED_MASK \
107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
108 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
109 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
110 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
111 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
112 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
113 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
114 #define GP_STATUS_10G_HIG \
115 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
116 #define GP_STATUS_10G_CX4 \
117 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
118 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
119 #define GP_STATUS_10G_KX4 \
120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
121 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
122 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
123 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
124 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
125 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
126 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
127 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
128 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
129 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
130 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
131 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
132 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
133 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
134 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
135 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
136 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
137 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
138 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
139 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
144 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
149 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
154 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
158 #define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160 #define SFP_EEPROM_OPTIONS_SIZE 2
162 #define EDC_MODE_LINEAR 0x0022
163 #define EDC_MODE_LIMITING 0x0044
164 #define EDC_MODE_PASSIVE_DAC 0x0055
166 /* BRB default for class 0 E2 */
167 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
168 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
169 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
170 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
172 /* BRB thresholds for E2*/
173 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
174 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
176 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
177 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
179 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
180 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
182 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
183 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
185 /* BRB default for class 0 E3A0 */
186 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
187 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
188 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
189 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
191 /* BRB thresholds for E3A0 */
192 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
193 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
195 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
196 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
198 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
199 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
201 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
202 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
204 /* BRB default for E3B0 */
205 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
206 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
207 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
208 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
210 /* BRB thresholds for E3B0 2 port mode*/
211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
214 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
215 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
217 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
220 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
221 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
224 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
225 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
227 /* Lossy +Lossless GUARANTIED == GUART */
228 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
229 /* Lossless +Lossless*/
230 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
232 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
235 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
236 /* Lossless +Lossless*/
237 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
239 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
240 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
242 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
243 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
245 /* BRB thresholds for E3B0 4 port mode */
246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
249 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
250 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
252 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
255 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
256 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
260 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
261 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
262 #define PFC_E3B0_4P_LB_GUART 120
264 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
265 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
267 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
268 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
271 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
272 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
273 #define DEFAULT_E3B0_LB_GUART 40
275 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
276 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
278 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
279 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
282 #define DCBX_INVALID_COS (0xFF)
284 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
285 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
286 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
287 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
288 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
290 #define MAX_PACKET_SIZE (9700)
291 #define WC_UC_TIMEOUT 100
292 #define MAX_KR_LINK_RETRY 4
294 /**********************************************************/
296 /**********************************************************/
298 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
299 bnx2x_cl45_write(_bp, _phy, \
300 (_phy)->def_md_devad, \
301 (_bank + (_addr & 0xf)), \
304 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
305 bnx2x_cl45_read(_bp, _phy, \
306 (_phy)->def_md_devad, \
307 (_bank + (_addr & 0xf)), \
310 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
312 u32 val = REG_RD(bp, reg);
315 REG_WR(bp, reg, val);
319 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
321 u32 val = REG_RD(bp, reg);
324 REG_WR(bp, reg, val);
328 /******************************************************************/
329 /* EPIO/GPIO section */
330 /******************************************************************/
331 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
333 u32 epio_mask, gp_oenable;
337 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
341 epio_mask = 1 << epio_pin;
342 /* Set this EPIO to output */
343 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
344 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
346 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
348 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
350 u32 epio_mask, gp_output, gp_oenable;
354 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
357 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
358 epio_mask = 1 << epio_pin;
359 /* Set this EPIO to output */
360 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
362 gp_output |= epio_mask;
364 gp_output &= ~epio_mask;
366 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
368 /* Set the value for this EPIO */
369 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
370 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
373 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
375 if (pin_cfg == PIN_CFG_NA)
377 if (pin_cfg >= PIN_CFG_EPIO0) {
378 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
380 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
381 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
382 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
386 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
388 if (pin_cfg == PIN_CFG_NA)
390 if (pin_cfg >= PIN_CFG_EPIO0) {
391 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
393 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
394 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
395 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
400 /******************************************************************/
402 /******************************************************************/
403 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
405 /* ETS disabled configuration*/
406 struct bnx2x *bp = params->bp;
408 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
411 * mapping between entry priority to client number (0,1,2 -debug and
412 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
414 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
415 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
418 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
420 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
421 * as strict. Bits 0,1,2 - debug and management entries, 3 -
422 * COS0 entry, 4 - COS1 entry.
423 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
424 * bit4 bit3 bit2 bit1 bit0
425 * MCP and debug are strict
428 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
429 /* defines which entries (clients) are subjected to WFQ arbitration */
430 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
432 * For strict priority entries defines the number of consecutive
433 * slots for the highest priority.
435 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
437 * mapping between the CREDIT_WEIGHT registers and actual client
440 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
441 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
442 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
444 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
445 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
446 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
447 /* ETS mode disable */
448 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
450 * If ETS mode is enabled (there is no strict priority) defines a WFQ
451 * weight for COS0/COS1.
453 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
454 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
455 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
456 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
457 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
458 /* Defines the number of consecutive slots for the strict priority */
459 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
461 /******************************************************************************
463 * Getting min_w_val will be set according to line speed .
465 ******************************************************************************/
466 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
469 /* Calculate min_w_val.*/
471 if (SPEED_20000 == vars->line_speed)
472 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
474 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
476 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
478 * If the link isn't up (static configuration for example ) The
479 * link will be according to 20GBPS.
483 /******************************************************************************
485 * Getting credit upper bound form min_w_val.
487 ******************************************************************************/
488 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
490 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
492 return credit_upper_bound;
494 /******************************************************************************
496 * Set credit upper bound for NIG.
498 ******************************************************************************/
499 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
500 const struct link_params *params,
503 struct bnx2x *bp = params->bp;
504 const u8 port = params->port;
505 const u32 credit_upper_bound =
506 bnx2x_ets_get_credit_upper_bound(min_w_val);
508 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
509 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
510 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
511 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
512 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
513 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
514 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
515 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
516 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
517 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
518 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
519 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
522 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
524 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
526 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
530 /******************************************************************************
532 * Will return the NIG ETS registers to init values.Except
533 * credit_upper_bound.
534 * That isn't used in this configuration (No WFQ is enabled) and will be
535 * configured acording to spec
537 ******************************************************************************/
538 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
539 const struct link_vars *vars)
541 struct bnx2x *bp = params->bp;
542 const u8 port = params->port;
543 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
545 * mapping between entry priority to client number (0,1,2 -debug and
546 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
547 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
548 * reset value or init tool
551 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
552 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
554 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
555 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
558 * For strict priority entries defines the number of consecutive
559 * slots for the highest priority.
561 /* TODO_ETS - Should be done by reset value or init tool */
562 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
563 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
565 * mapping between the CREDIT_WEIGHT registers and actual client
568 /* TODO_ETS - Should be done by reset value or init tool */
571 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
572 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
575 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
577 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
581 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
582 * as strict. Bits 0,1,2 - debug and management entries, 3 -
583 * COS0 entry, 4 - COS1 entry.
584 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
585 * bit4 bit3 bit2 bit1 bit0
586 * MCP and debug are strict
589 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
591 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
592 /* defines which entries (clients) are subjected to WFQ arbitration */
593 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
594 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
597 * Please notice the register address are note continuous and a
598 * for here is note appropriate.In 2 port mode port0 only COS0-5
599 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
600 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
601 * are never used for WFQ
603 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
604 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
605 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
606 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
607 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
608 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
609 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
610 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
611 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
612 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
613 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
614 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
616 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
617 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
618 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
621 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
623 /******************************************************************************
625 * Set credit upper bound for PBF.
627 ******************************************************************************/
628 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
629 const struct link_params *params,
632 struct bnx2x *bp = params->bp;
633 const u32 credit_upper_bound =
634 bnx2x_ets_get_credit_upper_bound(min_w_val);
635 const u8 port = params->port;
636 u32 base_upper_bound = 0;
640 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
641 * port mode port1 has COS0-2 that can be used for WFQ.
644 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
645 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
647 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
648 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
651 for (i = 0; i < max_cos; i++)
652 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
655 /******************************************************************************
657 * Will return the PBF ETS registers to init values.Except
658 * credit_upper_bound.
659 * That isn't used in this configuration (No WFQ is enabled) and will be
660 * configured acording to spec
662 ******************************************************************************/
663 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
665 struct bnx2x *bp = params->bp;
666 const u8 port = params->port;
667 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
673 * mapping between entry priority to client number 0 - COS0
674 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
675 * TODO_ETS - Should be done by reset value or init tool
678 /* 0x688 (|011|0 10|00 1|000) */
679 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
681 /* (10 1|100 |011|0 10|00 1|000) */
682 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
684 /* TODO_ETS - Should be done by reset value or init tool */
686 /* 0x688 (|011|0 10|00 1|000)*/
687 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
689 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
690 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
692 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
693 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
696 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
697 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
699 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
700 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
702 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
703 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
706 base_weight = PBF_REG_COS0_WEIGHT_P0;
707 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
709 base_weight = PBF_REG_COS0_WEIGHT_P1;
710 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
713 for (i = 0; i < max_cos; i++)
714 REG_WR(bp, base_weight + (0x4 * i), 0);
716 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
718 /******************************************************************************
720 * E3B0 disable will return basicly the values to init values.
722 ******************************************************************************/
723 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
724 const struct link_vars *vars)
726 struct bnx2x *bp = params->bp;
728 if (!CHIP_IS_E3B0(bp)) {
730 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
734 bnx2x_ets_e3b0_nig_disabled(params, vars);
736 bnx2x_ets_e3b0_pbf_disabled(params);
741 /******************************************************************************
743 * Disable will return basicly the values to init values.
745 ******************************************************************************/
746 int bnx2x_ets_disabled(struct link_params *params,
747 struct link_vars *vars)
749 struct bnx2x *bp = params->bp;
750 int bnx2x_status = 0;
752 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
753 bnx2x_ets_e2e3a0_disabled(params);
754 else if (CHIP_IS_E3B0(bp))
755 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
757 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
764 /******************************************************************************
766 * Set the COS mappimg to SP and BW until this point all the COS are not
768 ******************************************************************************/
769 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
770 const struct bnx2x_ets_params *ets_params,
771 const u8 cos_sp_bitmap,
772 const u8 cos_bw_bitmap)
774 struct bnx2x *bp = params->bp;
775 const u8 port = params->port;
776 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
777 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
778 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
779 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
781 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
782 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
784 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
785 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
787 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
788 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
789 nig_cli_subject2wfq_bitmap);
791 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
792 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
793 pbf_cli_subject2wfq_bitmap);
798 /******************************************************************************
800 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
801 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
802 ******************************************************************************/
803 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
805 const u32 min_w_val_nig,
806 const u32 min_w_val_pbf,
811 u32 nig_reg_adress_crd_weight = 0;
812 u32 pbf_reg_adress_crd_weight = 0;
813 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
814 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
815 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
819 nig_reg_adress_crd_weight =
820 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
821 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
822 pbf_reg_adress_crd_weight = (port) ?
823 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
826 nig_reg_adress_crd_weight = (port) ?
827 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
828 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
829 pbf_reg_adress_crd_weight = (port) ?
830 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
833 nig_reg_adress_crd_weight = (port) ?
834 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
835 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
837 pbf_reg_adress_crd_weight = (port) ?
838 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
843 nig_reg_adress_crd_weight =
844 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
845 pbf_reg_adress_crd_weight =
846 PBF_REG_COS3_WEIGHT_P0;
851 nig_reg_adress_crd_weight =
852 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
853 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
858 nig_reg_adress_crd_weight =
859 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
860 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
864 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
866 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
870 /******************************************************************************
872 * Calculate the total BW.A value of 0 isn't legal.
874 ******************************************************************************/
875 static int bnx2x_ets_e3b0_get_total_bw(
876 const struct link_params *params,
877 struct bnx2x_ets_params *ets_params,
880 struct bnx2x *bp = params->bp;
882 u8 is_bw_cos_exist = 0;
886 /* Calculate total BW requested */
887 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
888 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
890 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
891 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
894 * This is to prevent a state when ramrods
897 ets_params->cos[cos_idx].params.bw_params.bw
901 ets_params->cos[cos_idx].params.bw_params.bw;
905 /* Check total BW is valid */
906 if ((1 == is_bw_cos_exist) && (100 != *total_bw)) {
907 if (0 == *total_bw) {
909 "bnx2x_ets_E3B0_config toatl BW shouldn't be 0\n");
913 "bnx2x_ets_E3B0_config toatl BW should be 100\n");
915 * We can handle a case whre the BW isn't 100 this can happen
916 * if the TC are joined.
922 /******************************************************************************
924 * Invalidate all the sp_pri_to_cos.
926 ******************************************************************************/
927 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
930 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
931 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
933 /******************************************************************************
935 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
936 * according to sp_pri_to_cos.
938 ******************************************************************************/
939 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
940 u8 *sp_pri_to_cos, const u8 pri,
943 struct bnx2x *bp = params->bp;
944 const u8 port = params->port;
945 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
946 DCBX_E3B0_MAX_NUM_COS_PORT0;
948 if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
949 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
950 "parameter There can't be two COS's with "
951 "the same strict pri\n");
955 if (pri > max_num_of_cos) {
956 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
957 "parameter Illegal strict priority\n");
961 sp_pri_to_cos[pri] = cos_entry;
966 /******************************************************************************
968 * Returns the correct value according to COS and priority in
969 * the sp_pri_cli register.
971 ******************************************************************************/
972 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
978 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
979 (pri_set + pri_offset));
983 /******************************************************************************
985 * Returns the correct value according to COS and priority in the
986 * sp_pri_cli register for NIG.
988 ******************************************************************************/
989 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
991 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
992 const u8 nig_cos_offset = 3;
993 const u8 nig_pri_offset = 3;
995 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
999 /******************************************************************************
1001 * Returns the correct value according to COS and priority in the
1002 * sp_pri_cli register for PBF.
1004 ******************************************************************************/
1005 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1007 const u8 pbf_cos_offset = 0;
1008 const u8 pbf_pri_offset = 0;
1010 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1015 /******************************************************************************
1017 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1018 * according to sp_pri_to_cos.(which COS has higher priority)
1020 ******************************************************************************/
1021 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1024 struct bnx2x *bp = params->bp;
1026 const u8 port = params->port;
1027 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1028 u64 pri_cli_nig = 0x210;
1029 u32 pri_cli_pbf = 0x0;
1032 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1033 DCBX_E3B0_MAX_NUM_COS_PORT0;
1035 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1037 /* Set all the strict priority first */
1038 for (i = 0; i < max_num_of_cos; i++) {
1039 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1040 if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1042 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1043 "invalid cos entry\n");
1047 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1048 sp_pri_to_cos[i], pri_set);
1050 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1051 sp_pri_to_cos[i], pri_set);
1052 pri_bitmask = 1 << sp_pri_to_cos[i];
1053 /* COS is used remove it from bitmap.*/
1054 if (0 == (pri_bitmask & cos_bit_to_set)) {
1056 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1057 "invalid There can't be two COS's with"
1058 " the same strict pri\n");
1061 cos_bit_to_set &= ~pri_bitmask;
1066 /* Set all the Non strict priority i= COS*/
1067 for (i = 0; i < max_num_of_cos; i++) {
1068 pri_bitmask = 1 << i;
1069 /* Check if COS was already used for SP */
1070 if (pri_bitmask & cos_bit_to_set) {
1071 /* COS wasn't used for SP */
1072 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1075 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1077 /* COS is used remove it from bitmap.*/
1078 cos_bit_to_set &= ~pri_bitmask;
1083 if (pri_set != max_num_of_cos) {
1084 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1085 "entries were set\n");
1090 /* Only 6 usable clients*/
1091 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1094 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1096 /* Only 9 usable clients*/
1097 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1098 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1100 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1102 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1105 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1110 /******************************************************************************
1112 * Configure the COS to ETS according to BW and SP settings.
1113 ******************************************************************************/
1114 int bnx2x_ets_e3b0_config(const struct link_params *params,
1115 const struct link_vars *vars,
1116 struct bnx2x_ets_params *ets_params)
1118 struct bnx2x *bp = params->bp;
1119 int bnx2x_status = 0;
1120 const u8 port = params->port;
1122 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1123 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1124 u8 cos_bw_bitmap = 0;
1125 u8 cos_sp_bitmap = 0;
1126 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1127 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1128 DCBX_E3B0_MAX_NUM_COS_PORT0;
1131 if (!CHIP_IS_E3B0(bp)) {
1133 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1137 if ((ets_params->num_of_cos > max_num_of_cos)) {
1138 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1139 "isn't supported\n");
1143 /* Prepare sp strict priority parameters*/
1144 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1146 /* Prepare BW parameters*/
1147 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1149 if (0 != bnx2x_status) {
1151 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1156 * Upper bound is set according to current link speed (min_w_val
1157 * should be the same for upper bound and COS credit val).
1159 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1160 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1163 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1164 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1165 cos_bw_bitmap |= (1 << cos_entry);
1167 * The function also sets the BW in HW(not the mappin
1170 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1171 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1173 ets_params->cos[cos_entry].params.bw_params.bw,
1175 } else if (bnx2x_cos_state_strict ==
1176 ets_params->cos[cos_entry].state){
1177 cos_sp_bitmap |= (1 << cos_entry);
1179 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1182 ets_params->cos[cos_entry].params.sp_params.pri,
1187 "bnx2x_ets_e3b0_config cos state not valid\n");
1190 if (0 != bnx2x_status) {
1192 "bnx2x_ets_e3b0_config set cos bw failed\n");
1193 return bnx2x_status;
1197 /* Set SP register (which COS has higher priority) */
1198 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1201 if (0 != bnx2x_status) {
1203 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1204 return bnx2x_status;
1207 /* Set client mapping of BW and strict */
1208 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1212 if (0 != bnx2x_status) {
1213 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1214 return bnx2x_status;
1218 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1220 /* ETS disabled configuration */
1221 struct bnx2x *bp = params->bp;
1222 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1224 * defines which entries (clients) are subjected to WFQ arbitration
1228 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1230 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1231 * client numbers (WEIGHT_0 does not actually have to represent
1233 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1234 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1236 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1238 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1239 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1240 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1241 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1243 /* ETS mode enabled*/
1244 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1246 /* Defines the number of consecutive slots for the strict priority */
1247 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1249 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1250 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1251 * entry, 4 - COS1 entry.
1252 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1253 * bit4 bit3 bit2 bit1 bit0
1254 * MCP and debug are strict
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1258 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1259 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1260 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1262 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1268 /* ETS disabled configuration*/
1269 struct bnx2x *bp = params->bp;
1270 const u32 total_bw = cos0_bw + cos1_bw;
1271 u32 cos0_credit_weight = 0;
1272 u32 cos1_credit_weight = 0;
1274 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1276 if ((0 == total_bw) ||
1279 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1283 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1285 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1288 bnx2x_ets_bw_limit_common(params);
1290 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1291 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1293 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1294 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1299 /* ETS disabled configuration*/
1300 struct bnx2x *bp = params->bp;
1303 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1305 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1306 * as strict. Bits 0,1,2 - debug and management entries,
1307 * 3 - COS0 entry, 4 - COS1 entry.
1308 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1309 * bit4 bit3 bit2 bit1 bit0
1310 * MCP and debug are strict
1312 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1314 * For strict priority entries defines the number of consecutive slots
1315 * for the highest priority.
1317 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1318 /* ETS mode disable */
1319 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1320 /* Defines the number of consecutive slots for the strict priority */
1321 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1323 /* Defines the number of consecutive slots for the strict priority */
1324 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1327 * mapping between entry priority to client number (0,1,2 -debug and
1328 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1330 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1331 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1332 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1334 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1335 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1339 /******************************************************************/
1341 /******************************************************************/
1343 static void bnx2x_update_pfc_xmac(struct link_params *params,
1344 struct link_vars *vars,
1347 struct bnx2x *bp = params->bp;
1349 u32 pause_val, pfc0_val, pfc1_val;
1351 /* XMAC base adrr */
1352 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1354 /* Initialize pause and pfc registers */
1355 pause_val = 0x18000;
1356 pfc0_val = 0xFFFF8000;
1359 /* No PFC support */
1360 if (!(params->feature_config_flags &
1361 FEATURE_CONFIG_PFC_ENABLED)) {
1364 * RX flow control - Process pause frame in receive direction
1366 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1367 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1370 * TX flow control - Send pause packet when buffer is full
1372 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1373 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1374 } else {/* PFC support */
1375 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1376 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1377 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1378 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1381 /* Write pause and PFC registers */
1382 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1383 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1384 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1387 /* Set MAC address for source TX Pause/PFC frames */
1388 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1389 ((params->mac_addr[2] << 24) |
1390 (params->mac_addr[3] << 16) |
1391 (params->mac_addr[4] << 8) |
1392 (params->mac_addr[5])));
1393 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1394 ((params->mac_addr[0] << 8) |
1395 (params->mac_addr[1])));
1401 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1402 u32 pfc_frames_sent[2],
1403 u32 pfc_frames_received[2])
1405 /* Read pfc statistic */
1406 struct bnx2x *bp = params->bp;
1407 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1411 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1413 /* PFC received frames */
1414 val_xoff = REG_RD(bp, emac_base +
1415 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1416 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1417 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1418 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1420 pfc_frames_received[0] = val_xon + val_xoff;
1422 /* PFC received sent */
1423 val_xoff = REG_RD(bp, emac_base +
1424 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1425 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1426 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1427 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1429 pfc_frames_sent[0] = val_xon + val_xoff;
1432 /* Read pfc statistic*/
1433 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1434 u32 pfc_frames_sent[2],
1435 u32 pfc_frames_received[2])
1437 /* Read pfc statistic */
1438 struct bnx2x *bp = params->bp;
1440 DP(NETIF_MSG_LINK, "pfc statistic\n");
1445 if (MAC_TYPE_EMAC == vars->mac_type) {
1446 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1447 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1448 pfc_frames_received);
1451 /******************************************************************/
1452 /* MAC/PBF section */
1453 /******************************************************************/
1454 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1456 u32 mode, emac_base;
1458 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1459 * (a value of 49==0x31) and make sure that the AUTO poll is off
1463 emac_base = GRCBASE_EMAC0;
1465 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1466 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1467 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1468 EMAC_MDIO_MODE_CLOCK_CNT);
1469 if (USES_WARPCORE(bp))
1470 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1472 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1474 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1475 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1480 static void bnx2x_emac_init(struct link_params *params,
1481 struct link_vars *vars)
1483 /* reset and unreset the emac core */
1484 struct bnx2x *bp = params->bp;
1485 u8 port = params->port;
1486 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1491 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1493 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1494 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1496 /* init emac - use read-modify-write */
1497 /* self clear reset */
1498 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1499 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1503 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1504 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1506 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1510 } while (val & EMAC_MODE_RESET);
1511 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1512 /* Set mac address */
1513 val = ((params->mac_addr[0] << 8) |
1514 params->mac_addr[1]);
1515 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1517 val = ((params->mac_addr[2] << 24) |
1518 (params->mac_addr[3] << 16) |
1519 (params->mac_addr[4] << 8) |
1520 params->mac_addr[5]);
1521 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1524 static void bnx2x_set_xumac_nig(struct link_params *params,
1528 struct bnx2x *bp = params->bp;
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1532 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1534 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1535 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1538 static void bnx2x_umac_disable(struct link_params *params)
1540 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1541 struct bnx2x *bp = params->bp;
1542 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1543 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1546 /* Disable RX and TX */
1547 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1550 static void bnx2x_umac_enable(struct link_params *params,
1551 struct link_vars *vars, u8 lb)
1554 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1555 struct bnx2x *bp = params->bp;
1557 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1558 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1559 usleep_range(1000, 1000);
1561 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1562 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1564 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1567 * This register determines on which events the MAC will assert
1568 * error on the i/f to the NIG along w/ EOP.
1572 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1573 * params->port*0x14, 0xfffff.
1575 /* This register opens the gate for the UMAC despite its name */
1576 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1578 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1579 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1580 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1581 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1582 switch (vars->line_speed) {
1596 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1600 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1601 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1603 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1604 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1606 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1609 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1610 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1611 ((params->mac_addr[2] << 24) |
1612 (params->mac_addr[3] << 16) |
1613 (params->mac_addr[4] << 8) |
1614 (params->mac_addr[5])));
1615 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1616 ((params->mac_addr[0] << 8) |
1617 (params->mac_addr[1])));
1619 /* Enable RX and TX */
1620 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1621 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1622 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1623 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1626 /* Remove SW Reset */
1627 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1629 /* Check loopback mode */
1631 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1632 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1635 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1636 * length used by the MAC receive logic to check frames.
1638 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1639 bnx2x_set_xumac_nig(params,
1640 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1641 vars->mac_type = MAC_TYPE_UMAC;
1645 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1647 u32 port4mode_ovwr_val;
1648 /* Check 4-port override enabled */
1649 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1650 if (port4mode_ovwr_val & (1<<0)) {
1651 /* Return 4-port mode override value */
1652 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1654 /* Return 4-port mode from input pin */
1655 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1658 /* Define the XMAC mode */
1659 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1661 struct bnx2x *bp = params->bp;
1662 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1665 * In 4-port mode, need to set the mode only once, so if XMAC is
1666 * already out of reset, it means the mode has already been set,
1667 * and it must not* reset the XMAC again, since it controls both
1671 if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1672 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1673 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1675 "XMAC already out of reset in 4-port mode\n");
1680 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1681 MISC_REGISTERS_RESET_REG_2_XMAC);
1682 usleep_range(1000, 1000);
1684 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1685 MISC_REGISTERS_RESET_REG_2_XMAC);
1687 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1689 /* Set the number of ports on the system side to up to 2 */
1690 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1692 /* Set the number of ports on the Warp Core to 10G */
1693 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1695 /* Set the number of ports on the system side to 1 */
1696 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1697 if (max_speed == SPEED_10000) {
1699 "Init XMAC to 10G x 1 port per path\n");
1700 /* Set the number of ports on the Warp Core to 10G */
1701 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1704 "Init XMAC to 20G x 2 ports per path\n");
1705 /* Set the number of ports on the Warp Core to 20G */
1706 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1711 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1712 usleep_range(1000, 1000);
1714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1715 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1719 static void bnx2x_xmac_disable(struct link_params *params)
1721 u8 port = params->port;
1722 struct bnx2x *bp = params->bp;
1723 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1725 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1726 MISC_REGISTERS_RESET_REG_2_XMAC) {
1728 * Send an indication to change the state in the NIG back to XON
1729 * Clearing this bit enables the next set of this bit to get
1732 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1733 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1734 (pfc_ctrl & ~(1<<1)));
1735 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1736 (pfc_ctrl | (1<<1)));
1737 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1738 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1742 static int bnx2x_xmac_enable(struct link_params *params,
1743 struct link_vars *vars, u8 lb)
1746 struct bnx2x *bp = params->bp;
1747 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1749 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1751 bnx2x_xmac_init(params, vars->line_speed);
1754 * This register determines on which events the MAC will assert
1755 * error on the i/f to the NIG along w/ EOP.
1759 * This register tells the NIG whether to send traffic to UMAC
1762 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1764 /* Set Max packet size */
1765 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1767 /* CRC append for Tx packets */
1768 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1771 bnx2x_update_pfc_xmac(params, vars, 0);
1773 /* Enable TX and RX */
1774 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1776 /* Check loopback mode */
1778 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1779 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1780 bnx2x_set_xumac_nig(params,
1781 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1783 vars->mac_type = MAC_TYPE_XMAC;
1787 static int bnx2x_emac_enable(struct link_params *params,
1788 struct link_vars *vars, u8 lb)
1790 struct bnx2x *bp = params->bp;
1791 u8 port = params->port;
1792 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1795 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1798 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1799 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1801 /* enable emac and not bmac */
1802 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1805 if (vars->phy_flags & PHY_XGXS_FLAG) {
1806 u32 ser_lane = ((params->lane_config &
1807 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1808 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1810 DP(NETIF_MSG_LINK, "XGXS\n");
1811 /* select the master lanes (out of 0-3) */
1812 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1814 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1816 } else { /* SerDes */
1817 DP(NETIF_MSG_LINK, "SerDes\n");
1819 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1822 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1823 EMAC_RX_MODE_RESET);
1824 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1825 EMAC_TX_MODE_RESET);
1827 if (CHIP_REV_IS_SLOW(bp)) {
1828 /* config GMII mode */
1829 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1830 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1832 /* pause enable/disable */
1833 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1834 EMAC_RX_MODE_FLOW_EN);
1836 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1837 (EMAC_TX_MODE_EXT_PAUSE_EN |
1838 EMAC_TX_MODE_FLOW_EN));
1839 if (!(params->feature_config_flags &
1840 FEATURE_CONFIG_PFC_ENABLED)) {
1841 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1842 bnx2x_bits_en(bp, emac_base +
1843 EMAC_REG_EMAC_RX_MODE,
1844 EMAC_RX_MODE_FLOW_EN);
1846 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1847 bnx2x_bits_en(bp, emac_base +
1848 EMAC_REG_EMAC_TX_MODE,
1849 (EMAC_TX_MODE_EXT_PAUSE_EN |
1850 EMAC_TX_MODE_FLOW_EN));
1852 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1853 EMAC_TX_MODE_FLOW_EN);
1856 /* KEEP_VLAN_TAG, promiscuous */
1857 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1858 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1861 * Setting this bit causes MAC control frames (except for pause
1862 * frames) to be passed on for processing. This setting has no
1863 * affect on the operation of the pause frames. This bit effects
1864 * all packets regardless of RX Parser packet sorting logic.
1865 * Turn the PFC off to make sure we are in Xon state before
1868 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1869 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1870 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1871 /* Enable PFC again */
1872 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1873 EMAC_REG_RX_PFC_MODE_RX_EN |
1874 EMAC_REG_RX_PFC_MODE_TX_EN |
1875 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1877 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1879 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1881 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1882 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1884 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1887 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1892 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1895 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1897 /* enable emac for jumbo packets */
1898 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1899 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1900 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1903 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1905 /* disable the NIG in/out to the bmac */
1906 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1907 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1908 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1910 /* enable the NIG in/out to the emac */
1911 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1913 if ((params->feature_config_flags &
1914 FEATURE_CONFIG_PFC_ENABLED) ||
1915 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1918 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1919 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1921 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1923 vars->mac_type = MAC_TYPE_EMAC;
1927 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1928 struct link_vars *vars)
1931 struct bnx2x *bp = params->bp;
1932 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1933 NIG_REG_INGRESS_BMAC0_MEM;
1936 if ((!(params->feature_config_flags &
1937 FEATURE_CONFIG_PFC_ENABLED)) &&
1938 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1939 /* Enable BigMAC to react on received Pause packets */
1943 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1947 if (!(params->feature_config_flags &
1948 FEATURE_CONFIG_PFC_ENABLED) &&
1949 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1953 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1956 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1957 struct link_vars *vars,
1961 * Set rx control: Strip CRC and enable BigMAC to relay
1962 * control packets to the system as well
1965 struct bnx2x *bp = params->bp;
1966 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1967 NIG_REG_INGRESS_BMAC0_MEM;
1970 if ((!(params->feature_config_flags &
1971 FEATURE_CONFIG_PFC_ENABLED)) &&
1972 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1973 /* Enable BigMAC to react on received Pause packets */
1977 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1982 if (!(params->feature_config_flags &
1983 FEATURE_CONFIG_PFC_ENABLED) &&
1984 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1988 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1990 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1991 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1992 /* Enable PFC RX & TX & STATS and set 8 COS */
1994 wb_data[0] |= (1<<0); /* RX */
1995 wb_data[0] |= (1<<1); /* TX */
1996 wb_data[0] |= (1<<2); /* Force initial Xon */
1997 wb_data[0] |= (1<<3); /* 8 cos */
1998 wb_data[0] |= (1<<5); /* STATS */
2000 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2002 /* Clear the force Xon */
2003 wb_data[0] &= ~(1<<2);
2005 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2006 /* disable PFC RX & TX & STATS and set 8 COS */
2011 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2014 * Set Time (based unit is 512 bit time) between automatic
2015 * re-sending of PP packets amd enable automatic re-send of
2016 * Per-Priroity Packet as long as pp_gen is asserted and
2017 * pp_disable is low.
2020 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2021 val |= (1<<16); /* enable automatic re-send */
2025 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2029 val = 0x3; /* Enable RX and TX */
2031 val |= 0x4; /* Local loopback */
2032 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2034 /* When PFC enabled, Pass pause frames towards the NIG. */
2035 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2036 val |= ((1<<6)|(1<<5));
2040 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2044 /* PFC BRB internal port configuration params */
2045 struct bnx2x_pfc_brb_threshold_val {
2052 struct bnx2x_pfc_brb_e3b0_val {
2053 u32 per_class_guaranty_mode;
2054 u32 lb_guarantied_hyst;
2055 u32 full_lb_xoff_th;
2056 u32 full_lb_xon_threshold;
2058 u32 mac_0_class_t_guarantied;
2059 u32 mac_0_class_t_guarantied_hyst;
2060 u32 mac_1_class_t_guarantied;
2061 u32 mac_1_class_t_guarantied_hyst;
2064 struct bnx2x_pfc_brb_th_val {
2065 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2066 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2067 struct bnx2x_pfc_brb_threshold_val default_class0;
2068 struct bnx2x_pfc_brb_threshold_val default_class1;
2071 static int bnx2x_pfc_brb_get_config_params(
2072 struct link_params *params,
2073 struct bnx2x_pfc_brb_th_val *config_val)
2075 struct bnx2x *bp = params->bp;
2076 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2078 config_val->default_class1.pause_xoff = 0;
2079 config_val->default_class1.pause_xon = 0;
2080 config_val->default_class1.full_xoff = 0;
2081 config_val->default_class1.full_xon = 0;
2083 if (CHIP_IS_E2(bp)) {
2084 /* class0 defaults */
2085 config_val->default_class0.pause_xoff =
2086 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2087 config_val->default_class0.pause_xon =
2088 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2089 config_val->default_class0.full_xoff =
2090 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2091 config_val->default_class0.full_xon =
2092 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2094 config_val->pauseable_th.pause_xoff =
2095 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2096 config_val->pauseable_th.pause_xon =
2097 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2098 config_val->pauseable_th.full_xoff =
2099 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2100 config_val->pauseable_th.full_xon =
2101 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2103 config_val->non_pauseable_th.pause_xoff =
2104 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2105 config_val->non_pauseable_th.pause_xon =
2106 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2107 config_val->non_pauseable_th.full_xoff =
2108 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2109 config_val->non_pauseable_th.full_xon =
2110 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2111 } else if (CHIP_IS_E3A0(bp)) {
2112 /* class0 defaults */
2113 config_val->default_class0.pause_xoff =
2114 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2115 config_val->default_class0.pause_xon =
2116 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2117 config_val->default_class0.full_xoff =
2118 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2119 config_val->default_class0.full_xon =
2120 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2122 config_val->pauseable_th.pause_xoff =
2123 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2124 config_val->pauseable_th.pause_xon =
2125 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2126 config_val->pauseable_th.full_xoff =
2127 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2128 config_val->pauseable_th.full_xon =
2129 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2131 config_val->non_pauseable_th.pause_xoff =
2132 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2133 config_val->non_pauseable_th.pause_xon =
2134 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2135 config_val->non_pauseable_th.full_xoff =
2136 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2137 config_val->non_pauseable_th.full_xon =
2138 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2139 } else if (CHIP_IS_E3B0(bp)) {
2140 /* class0 defaults */
2141 config_val->default_class0.pause_xoff =
2142 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2143 config_val->default_class0.pause_xon =
2144 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2145 config_val->default_class0.full_xoff =
2146 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2147 config_val->default_class0.full_xon =
2148 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2150 if (params->phy[INT_PHY].flags &
2151 FLAGS_4_PORT_MODE) {
2152 config_val->pauseable_th.pause_xoff =
2153 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2154 config_val->pauseable_th.pause_xon =
2155 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2156 config_val->pauseable_th.full_xoff =
2157 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2158 config_val->pauseable_th.full_xon =
2159 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2161 config_val->non_pauseable_th.pause_xoff =
2162 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2163 config_val->non_pauseable_th.pause_xon =
2164 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2165 config_val->non_pauseable_th.full_xoff =
2166 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2167 config_val->non_pauseable_th.full_xon =
2168 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2170 config_val->pauseable_th.pause_xoff =
2171 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2172 config_val->pauseable_th.pause_xon =
2173 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2174 config_val->pauseable_th.full_xoff =
2175 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2176 config_val->pauseable_th.full_xon =
2177 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2179 config_val->non_pauseable_th.pause_xoff =
2180 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2181 config_val->non_pauseable_th.pause_xon =
2182 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2183 config_val->non_pauseable_th.full_xoff =
2184 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2185 config_val->non_pauseable_th.full_xon =
2186 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2194 static void bnx2x_pfc_brb_get_e3b0_config_params(
2195 struct link_params *params,
2196 struct bnx2x_pfc_brb_e3b0_val
2198 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2199 const u8 pfc_enabled)
2201 if (pfc_enabled && pfc_params) {
2202 e3b0_val->per_class_guaranty_mode = 1;
2203 e3b0_val->lb_guarantied_hyst = 80;
2205 if (params->phy[INT_PHY].flags &
2206 FLAGS_4_PORT_MODE) {
2207 e3b0_val->full_lb_xoff_th =
2208 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2209 e3b0_val->full_lb_xon_threshold =
2210 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2211 e3b0_val->lb_guarantied =
2212 PFC_E3B0_4P_LB_GUART;
2213 e3b0_val->mac_0_class_t_guarantied =
2214 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2215 e3b0_val->mac_0_class_t_guarantied_hyst =
2216 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2217 e3b0_val->mac_1_class_t_guarantied =
2218 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2219 e3b0_val->mac_1_class_t_guarantied_hyst =
2220 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2222 e3b0_val->full_lb_xoff_th =
2223 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2224 e3b0_val->full_lb_xon_threshold =
2225 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2226 e3b0_val->mac_0_class_t_guarantied_hyst =
2227 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2228 e3b0_val->mac_1_class_t_guarantied =
2229 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2230 e3b0_val->mac_1_class_t_guarantied_hyst =
2231 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2233 if (pfc_params->cos0_pauseable !=
2234 pfc_params->cos1_pauseable) {
2235 /* nonpauseable= Lossy + pauseable = Lossless*/
2236 e3b0_val->lb_guarantied =
2237 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2238 e3b0_val->mac_0_class_t_guarantied =
2239 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2240 } else if (pfc_params->cos0_pauseable) {
2241 /* Lossless +Lossless*/
2242 e3b0_val->lb_guarantied =
2243 PFC_E3B0_2P_PAUSE_LB_GUART;
2244 e3b0_val->mac_0_class_t_guarantied =
2245 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2248 e3b0_val->lb_guarantied =
2249 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2250 e3b0_val->mac_0_class_t_guarantied =
2251 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2255 e3b0_val->per_class_guaranty_mode = 0;
2256 e3b0_val->lb_guarantied_hyst = 0;
2257 e3b0_val->full_lb_xoff_th =
2258 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2259 e3b0_val->full_lb_xon_threshold =
2260 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2261 e3b0_val->lb_guarantied =
2262 DEFAULT_E3B0_LB_GUART;
2263 e3b0_val->mac_0_class_t_guarantied =
2264 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2265 e3b0_val->mac_0_class_t_guarantied_hyst =
2266 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2267 e3b0_val->mac_1_class_t_guarantied =
2268 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2269 e3b0_val->mac_1_class_t_guarantied_hyst =
2270 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2273 static int bnx2x_update_pfc_brb(struct link_params *params,
2274 struct link_vars *vars,
2275 struct bnx2x_nig_brb_pfc_port_params
2278 struct bnx2x *bp = params->bp;
2279 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2280 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2281 &config_val.pauseable_th;
2282 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2283 const int set_pfc = params->feature_config_flags &
2284 FEATURE_CONFIG_PFC_ENABLED;
2285 const u8 pfc_enabled = (set_pfc && pfc_params);
2286 int bnx2x_status = 0;
2287 u8 port = params->port;
2289 /* default - pause configuration */
2290 reg_th_config = &config_val.pauseable_th;
2291 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2292 if (0 != bnx2x_status)
2293 return bnx2x_status;
2297 if (pfc_params->cos0_pauseable)
2298 reg_th_config = &config_val.pauseable_th;
2300 reg_th_config = &config_val.non_pauseable_th;
2302 reg_th_config = &config_val.default_class0;
2304 * The number of free blocks below which the pause signal to class 0
2305 * of MAC #n is asserted. n=0,1
2307 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2308 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2309 reg_th_config->pause_xoff);
2311 * The number of free blocks above which the pause signal to class 0
2312 * of MAC #n is de-asserted. n=0,1
2314 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2315 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2317 * The number of free blocks below which the full signal to class 0
2318 * of MAC #n is asserted. n=0,1
2320 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2321 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2323 * The number of free blocks above which the full signal to class 0
2324 * of MAC #n is de-asserted. n=0,1
2326 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2327 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2331 if (pfc_params->cos1_pauseable)
2332 reg_th_config = &config_val.pauseable_th;
2334 reg_th_config = &config_val.non_pauseable_th;
2336 reg_th_config = &config_val.default_class1;
2338 * The number of free blocks below which the pause signal to
2339 * class 1 of MAC #n is asserted. n=0,1
2341 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2342 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2343 reg_th_config->pause_xoff);
2345 * The number of free blocks above which the pause signal to
2346 * class 1 of MAC #n is de-asserted. n=0,1
2348 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2349 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2350 reg_th_config->pause_xon);
2352 * The number of free blocks below which the full signal to
2353 * class 1 of MAC #n is asserted. n=0,1
2355 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2356 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2357 reg_th_config->full_xoff);
2359 * The number of free blocks above which the full signal to
2360 * class 1 of MAC #n is de-asserted. n=0,1
2362 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2363 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2364 reg_th_config->full_xon);
2366 if (CHIP_IS_E3B0(bp)) {
2367 bnx2x_pfc_brb_get_e3b0_config_params(
2373 /*Should be done by init tool */
2375 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2379 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2380 e3b0_val.per_class_guaranty_mode);
2383 * The hysteresis on the guarantied buffer space for the Lb port
2384 * before signaling XON.
2386 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2387 e3b0_val.lb_guarantied_hyst);
2389 * The number of free blocks below which the full signal to the
2390 * LB port is asserted.
2392 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2393 e3b0_val.full_lb_xoff_th);
2395 * The number of free blocks above which the full signal to the
2396 * LB port is de-asserted.
2398 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2399 e3b0_val.full_lb_xon_threshold);
2401 * The number of blocks guarantied for the MAC #n port. n=0,1
2404 /*The number of blocks guarantied for the LB port.*/
2405 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2406 e3b0_val.lb_guarantied);
2409 * The number of blocks guarantied for the MAC #n port.
2411 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2412 2 * e3b0_val.mac_0_class_t_guarantied);
2413 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2414 2 * e3b0_val.mac_1_class_t_guarantied);
2416 * The number of blocks guarantied for class #t in MAC0. t=0,1
2418 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2419 e3b0_val.mac_0_class_t_guarantied);
2420 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2421 e3b0_val.mac_0_class_t_guarantied);
2423 * The hysteresis on the guarantied buffer space for class in
2426 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2427 e3b0_val.mac_0_class_t_guarantied_hyst);
2428 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2429 e3b0_val.mac_0_class_t_guarantied_hyst);
2432 * The number of blocks guarantied for class #t in MAC1.t=0,1
2434 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2435 e3b0_val.mac_1_class_t_guarantied);
2436 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2437 e3b0_val.mac_1_class_t_guarantied);
2439 * The hysteresis on the guarantied buffer space for class #t
2442 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2443 e3b0_val.mac_1_class_t_guarantied_hyst);
2444 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2445 e3b0_val.mac_1_class_t_guarantied_hyst);
2449 return bnx2x_status;
2452 /******************************************************************************
2454 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2455 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2456 ******************************************************************************/
2457 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2459 u32 priority_mask, u8 port)
2461 u32 nig_reg_rx_priority_mask_add = 0;
2463 switch (cos_entry) {
2465 nig_reg_rx_priority_mask_add = (port) ?
2466 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2467 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2470 nig_reg_rx_priority_mask_add = (port) ?
2471 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2472 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2475 nig_reg_rx_priority_mask_add = (port) ?
2476 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2477 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2482 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2487 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2492 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2496 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2500 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2502 struct bnx2x *bp = params->bp;
2504 REG_WR(bp, params->shmem_base +
2505 offsetof(struct shmem_region,
2506 port_mb[params->port].link_status), link_status);
2509 static void bnx2x_update_pfc_nig(struct link_params *params,
2510 struct link_vars *vars,
2511 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2513 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2514 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2515 u32 pkt_priority_to_cos = 0;
2516 struct bnx2x *bp = params->bp;
2517 u8 port = params->port;
2519 int set_pfc = params->feature_config_flags &
2520 FEATURE_CONFIG_PFC_ENABLED;
2521 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2524 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2525 * MAC control frames (that are not pause packets)
2526 * will be forwarded to the XCM.
2528 xcm_mask = REG_RD(bp,
2529 port ? NIG_REG_LLH1_XCM_MASK :
2530 NIG_REG_LLH0_XCM_MASK);
2532 * nig params will override non PFC params, since it's possible to
2533 * do transition from PFC to SAFC
2543 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2544 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2546 p0_hwpfc_enable = 1;
2549 llfc_out_en = nig_params->llfc_out_en;
2550 llfc_enable = nig_params->llfc_enable;
2551 pause_enable = nig_params->pause_enable;
2552 } else /*defaul non PFC mode - PAUSE */
2555 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2556 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2561 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2562 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2563 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2564 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2565 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2566 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2567 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2568 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2570 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2571 NIG_REG_PPP_ENABLE_0, ppp_enable);
2573 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2574 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2576 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2578 /* output enable for RX_XCM # IF */
2579 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2581 /* HW PFC TX enable */
2582 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2586 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2588 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2589 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2590 nig_params->rx_cos_priority_mask[i], port);
2592 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2593 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2594 nig_params->llfc_high_priority_classes);
2596 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2597 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2598 nig_params->llfc_low_priority_classes);
2600 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2601 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2602 pkt_priority_to_cos);
2605 int bnx2x_update_pfc(struct link_params *params,
2606 struct link_vars *vars,
2607 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2610 * The PFC and pause are orthogonal to one another, meaning when
2611 * PFC is enabled, the pause are disabled, and when PFC is
2612 * disabled, pause are set according to the pause result.
2615 struct bnx2x *bp = params->bp;
2616 int bnx2x_status = 0;
2617 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2619 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2620 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2622 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2624 bnx2x_update_mng(params, vars->link_status);
2626 /* update NIG params */
2627 bnx2x_update_pfc_nig(params, vars, pfc_params);
2629 /* update BRB params */
2630 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2631 if (0 != bnx2x_status)
2632 return bnx2x_status;
2635 return bnx2x_status;
2637 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2639 bnx2x_update_pfc_xmac(params, vars, 0);
2641 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2643 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2645 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2646 bnx2x_emac_enable(params, vars, 0);
2647 return bnx2x_status;
2651 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2653 bnx2x_update_pfc_bmac1(params, vars);
2656 if ((params->feature_config_flags &
2657 FEATURE_CONFIG_PFC_ENABLED) ||
2658 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2660 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2662 return bnx2x_status;
2666 static int bnx2x_bmac1_enable(struct link_params *params,
2667 struct link_vars *vars,
2670 struct bnx2x *bp = params->bp;
2671 u8 port = params->port;
2672 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2673 NIG_REG_INGRESS_BMAC0_MEM;
2677 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2682 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2686 wb_data[0] = ((params->mac_addr[2] << 24) |
2687 (params->mac_addr[3] << 16) |
2688 (params->mac_addr[4] << 8) |
2689 params->mac_addr[5]);
2690 wb_data[1] = ((params->mac_addr[0] << 8) |
2691 params->mac_addr[1]);
2692 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2698 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2702 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2705 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2707 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2709 bnx2x_update_pfc_bmac1(params, vars);
2712 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2714 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2716 /* set cnt max size */
2717 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2719 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2721 /* configure safc */
2722 wb_data[0] = 0x1000200;
2724 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2730 static int bnx2x_bmac2_enable(struct link_params *params,
2731 struct link_vars *vars,
2734 struct bnx2x *bp = params->bp;
2735 u8 port = params->port;
2736 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2737 NIG_REG_INGRESS_BMAC0_MEM;
2740 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2744 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2747 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2750 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2756 wb_data[0] = ((params->mac_addr[2] << 24) |
2757 (params->mac_addr[3] << 16) |
2758 (params->mac_addr[4] << 8) |
2759 params->mac_addr[5]);
2760 wb_data[1] = ((params->mac_addr[0] << 8) |
2761 params->mac_addr[1]);
2762 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2767 /* Configure SAFC */
2768 wb_data[0] = 0x1000200;
2770 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2775 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2777 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2781 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2783 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2785 /* set cnt max size */
2786 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2788 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2790 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2795 static int bnx2x_bmac_enable(struct link_params *params,
2796 struct link_vars *vars,
2800 u8 port = params->port;
2801 struct bnx2x *bp = params->bp;
2803 /* reset and unreset the BigMac */
2804 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2805 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2808 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2809 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2811 /* enable access for bmac registers */
2812 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2814 /* Enable BMAC according to BMAC type*/
2816 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2818 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2819 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2820 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2821 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2823 if ((params->feature_config_flags &
2824 FEATURE_CONFIG_PFC_ENABLED) ||
2825 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2827 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2828 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2829 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2830 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2831 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2832 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2834 vars->mac_type = MAC_TYPE_BMAC;
2838 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2840 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2841 NIG_REG_INGRESS_BMAC0_MEM;
2843 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2845 /* Only if the bmac is out of reset */
2846 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2847 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2850 if (CHIP_IS_E2(bp)) {
2851 /* Clear Rx Enable bit in BMAC_CONTROL register */
2852 REG_RD_DMAE(bp, bmac_addr +
2853 BIGMAC2_REGISTER_BMAC_CONTROL,
2855 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2856 REG_WR_DMAE(bp, bmac_addr +
2857 BIGMAC2_REGISTER_BMAC_CONTROL,
2860 /* Clear Rx Enable bit in BMAC_CONTROL register */
2861 REG_RD_DMAE(bp, bmac_addr +
2862 BIGMAC_REGISTER_BMAC_CONTROL,
2864 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2865 REG_WR_DMAE(bp, bmac_addr +
2866 BIGMAC_REGISTER_BMAC_CONTROL,
2873 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2876 struct bnx2x *bp = params->bp;
2877 u8 port = params->port;
2882 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2884 /* wait for init credit */
2885 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2886 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2887 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2889 while ((init_crd != crd) && count) {
2892 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2895 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2896 if (init_crd != crd) {
2897 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2902 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2903 line_speed == SPEED_10 ||
2904 line_speed == SPEED_100 ||
2905 line_speed == SPEED_1000 ||
2906 line_speed == SPEED_2500) {
2907 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2908 /* update threshold */
2909 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2910 /* update init credit */
2911 init_crd = 778; /* (800-18-4) */
2914 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2916 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2917 /* update threshold */
2918 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2919 /* update init credit */
2920 switch (line_speed) {
2922 init_crd = thresh + 553 - 22;
2925 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2930 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2931 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2932 line_speed, init_crd);
2934 /* probe the credit changes */
2935 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2937 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2940 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2945 * bnx2x_get_emac_base - retrive emac base address
2947 * @bp: driver handle
2948 * @mdc_mdio_access: access type
2951 * This function selects the MDC/MDIO access (through emac0 or
2952 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2953 * phy has a default access mode, which could also be overridden
2954 * by nvram configuration. This parameter, whether this is the
2955 * default phy configuration, or the nvram overrun
2956 * configuration, is passed here as mdc_mdio_access and selects
2957 * the emac_base for the CL45 read/writes operations
2959 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2960 u32 mdc_mdio_access, u8 port)
2963 switch (mdc_mdio_access) {
2964 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2966 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2967 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2968 emac_base = GRCBASE_EMAC1;
2970 emac_base = GRCBASE_EMAC0;
2972 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2973 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2974 emac_base = GRCBASE_EMAC0;
2976 emac_base = GRCBASE_EMAC1;
2978 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2979 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2981 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2982 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2991 /******************************************************************/
2992 /* CL22 access functions */
2993 /******************************************************************/
2994 static int bnx2x_cl22_write(struct bnx2x *bp,
2995 struct bnx2x_phy *phy,
3001 /* Switch to CL22 */
3002 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3003 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3004 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3007 tmp = ((phy->addr << 21) | (reg << 16) | val |
3008 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3009 EMAC_MDIO_COMM_START_BUSY);
3010 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3012 for (i = 0; i < 50; i++) {
3015 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3016 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3021 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3022 DP(NETIF_MSG_LINK, "write phy register failed\n");
3025 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3029 static int bnx2x_cl22_read(struct bnx2x *bp,
3030 struct bnx2x_phy *phy,
3031 u16 reg, u16 *ret_val)
3037 /* Switch to CL22 */
3038 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3039 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3040 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3043 val = ((phy->addr << 21) | (reg << 16) |
3044 EMAC_MDIO_COMM_COMMAND_READ_22 |
3045 EMAC_MDIO_COMM_START_BUSY);
3046 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3048 for (i = 0; i < 50; i++) {
3051 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3052 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3053 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3058 if (val & EMAC_MDIO_COMM_START_BUSY) {
3059 DP(NETIF_MSG_LINK, "read phy register failed\n");
3064 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3068 /******************************************************************/
3069 /* CL45 access functions */
3070 /******************************************************************/
3071 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3072 u8 devad, u16 reg, u16 *ret_val)
3077 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3078 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3079 EMAC_MDIO_STATUS_10MB);
3081 val = ((phy->addr << 21) | (devad << 16) | reg |
3082 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3083 EMAC_MDIO_COMM_START_BUSY);
3084 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3086 for (i = 0; i < 50; i++) {
3089 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3090 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3095 if (val & EMAC_MDIO_COMM_START_BUSY) {
3096 DP(NETIF_MSG_LINK, "read phy register failed\n");
3097 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3102 val = ((phy->addr << 21) | (devad << 16) |
3103 EMAC_MDIO_COMM_COMMAND_READ_45 |
3104 EMAC_MDIO_COMM_START_BUSY);
3105 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3107 for (i = 0; i < 50; i++) {
3110 val = REG_RD(bp, phy->mdio_ctrl +
3111 EMAC_REG_EMAC_MDIO_COMM);
3112 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3113 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3117 if (val & EMAC_MDIO_COMM_START_BUSY) {
3118 DP(NETIF_MSG_LINK, "read phy register failed\n");
3119 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3124 /* Work around for E3 A0 */
3125 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3126 phy->flags ^= FLAGS_DUMMY_READ;
3127 if (phy->flags & FLAGS_DUMMY_READ) {
3129 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3133 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3134 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3135 EMAC_MDIO_STATUS_10MB);
3139 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3140 u8 devad, u16 reg, u16 val)
3145 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3146 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3147 EMAC_MDIO_STATUS_10MB);
3151 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3152 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3153 EMAC_MDIO_COMM_START_BUSY);
3154 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3156 for (i = 0; i < 50; i++) {
3159 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3160 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3165 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3166 DP(NETIF_MSG_LINK, "write phy register failed\n");
3167 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3172 tmp = ((phy->addr << 21) | (devad << 16) | val |
3173 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3174 EMAC_MDIO_COMM_START_BUSY);
3175 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3177 for (i = 0; i < 50; i++) {
3180 tmp = REG_RD(bp, phy->mdio_ctrl +
3181 EMAC_REG_EMAC_MDIO_COMM);
3182 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3187 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3188 DP(NETIF_MSG_LINK, "write phy register failed\n");
3189 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3193 /* Work around for E3 A0 */
3194 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3195 phy->flags ^= FLAGS_DUMMY_READ;
3196 if (phy->flags & FLAGS_DUMMY_READ) {
3198 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3201 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3202 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3203 EMAC_MDIO_STATUS_10MB);
3208 /******************************************************************/
3209 /* BSC access functions from E3 */
3210 /******************************************************************/
3211 static void bnx2x_bsc_module_sel(struct link_params *params)
3214 u32 board_cfg, sfp_ctrl;
3215 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3216 struct bnx2x *bp = params->bp;
3217 u8 port = params->port;
3218 /* Read I2C output PINs */
3219 board_cfg = REG_RD(bp, params->shmem_base +
3220 offsetof(struct shmem_region,
3221 dev_info.shared_hw_config.board));
3222 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3223 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3224 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3226 /* Read I2C output value */
3227 sfp_ctrl = REG_RD(bp, params->shmem_base +
3228 offsetof(struct shmem_region,
3229 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3230 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3231 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3232 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3233 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3234 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3237 static int bnx2x_bsc_read(struct link_params *params,
3238 struct bnx2x_phy *phy,
3247 struct bnx2x *bp = params->bp;
3249 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3250 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3254 if (xfer_cnt > 16) {
3255 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3259 bnx2x_bsc_module_sel(params);
3261 xfer_cnt = 16 - lc_addr;
3263 /* enable the engine */
3264 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3265 val |= MCPR_IMC_COMMAND_ENABLE;
3266 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3268 /* program slave device ID */
3269 val = (sl_devid << 16) | sl_addr;
3270 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3272 /* start xfer with 0 byte to update the address pointer ???*/
3273 val = (MCPR_IMC_COMMAND_ENABLE) |
3274 (MCPR_IMC_COMMAND_WRITE_OP <<
3275 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3276 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3277 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3279 /* poll for completion */
3281 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3282 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3284 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3286 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3295 /* start xfer with read op */
3296 val = (MCPR_IMC_COMMAND_ENABLE) |
3297 (MCPR_IMC_COMMAND_READ_OP <<
3298 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3299 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3301 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3303 /* poll for completion */
3305 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3306 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3308 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3310 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3318 for (i = (lc_addr >> 2); i < 4; i++) {
3319 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3321 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3322 ((data_array[i] & 0x0000ff00) << 8) |
3323 ((data_array[i] & 0x00ff0000) >> 8) |
3324 ((data_array[i] & 0xff000000) >> 24);
3330 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3331 u8 devad, u16 reg, u16 or_val)
3334 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3335 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3338 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3339 u8 devad, u16 reg, u16 *ret_val)
3343 * Probe for the phy according to the given phy_addr, and execute
3344 * the read request on it
3346 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3347 if (params->phy[phy_index].addr == phy_addr) {
3348 return bnx2x_cl45_read(params->bp,
3349 ¶ms->phy[phy_index], devad,
3356 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3357 u8 devad, u16 reg, u16 val)
3361 * Probe for the phy according to the given phy_addr, and execute
3362 * the write request on it
3364 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3365 if (params->phy[phy_index].addr == phy_addr) {
3366 return bnx2x_cl45_write(params->bp,
3367 ¶ms->phy[phy_index], devad,
3373 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3374 struct link_params *params)
3377 struct bnx2x *bp = params->bp;
3378 u32 path_swap, path_swap_ovr;
3382 port = params->port;
3384 if (bnx2x_is_4_port_mode(bp)) {
3385 u32 port_swap, port_swap_ovr;
3387 /*figure out path swap value */
3388 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3389 if (path_swap_ovr & 0x1)
3390 path_swap = (path_swap_ovr & 0x2);
3392 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3397 /*figure out port swap value */
3398 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3399 if (port_swap_ovr & 0x1)
3400 port_swap = (port_swap_ovr & 0x2);
3402 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3407 lane = (port<<1) + path;
3408 } else { /* two port mode - no port swap */
3410 /*figure out path swap value */
3412 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3413 if (path_swap_ovr & 0x1) {
3414 path_swap = (path_swap_ovr & 0x2);
3417 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3427 static void bnx2x_set_aer_mmd(struct link_params *params,
3428 struct bnx2x_phy *phy)
3431 u16 offset, aer_val;
3432 struct bnx2x *bp = params->bp;
3433 ser_lane = ((params->lane_config &
3434 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3435 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3437 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3438 (phy->addr + ser_lane) : 0;
3440 if (USES_WARPCORE(bp)) {
3441 aer_val = bnx2x_get_warpcore_lane(phy, params);
3443 * In Dual-lane mode, two lanes are joined together,
3444 * so in order to configure them, the AER broadcast method is
3446 * 0x200 is the broadcast address for lanes 0,1
3447 * 0x201 is the broadcast address for lanes 2,3
3449 if (phy->flags & FLAGS_WC_DUAL_MODE)
3450 aer_val = (aer_val >> 1) | 0x200;
3451 } else if (CHIP_IS_E2(bp))
3452 aer_val = 0x3800 + offset - 1;
3454 aer_val = 0x3800 + offset;
3455 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3456 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3457 MDIO_AER_BLOCK_AER_REG, aer_val);
3461 /******************************************************************/
3462 /* Internal phy section */
3463 /******************************************************************/
3465 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3467 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3470 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3471 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3473 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3476 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3479 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3483 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3485 val = SERDES_RESET_BITS << (port*16);
3487 /* reset and unreset the SerDes/XGXS */
3488 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3492 bnx2x_set_serdes_access(bp, port);
3494 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3495 DEFAULT_PHY_DEV_ADDR);
3498 static void bnx2x_xgxs_deassert(struct link_params *params)
3500 struct bnx2x *bp = params->bp;
3503 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3504 port = params->port;
3506 val = XGXS_RESET_BITS << (port*16);
3508 /* reset and unreset the SerDes/XGXS */
3509 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3511 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3513 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3514 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3515 params->phy[INT_PHY].def_md_devad);
3518 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3519 struct link_params *params, u16 *ieee_fc)
3521 struct bnx2x *bp = params->bp;
3522 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3524 * resolve pause mode and advertisement Please refer to Table
3525 * 28B-3 of the 802.3ab-1999 spec
3528 switch (phy->req_flow_ctrl) {
3529 case BNX2X_FLOW_CTRL_AUTO:
3530 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3531 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3534 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3537 case BNX2X_FLOW_CTRL_TX:
3538 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3541 case BNX2X_FLOW_CTRL_RX:
3542 case BNX2X_FLOW_CTRL_BOTH:
3543 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3546 case BNX2X_FLOW_CTRL_NONE:
3548 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3551 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3554 static void set_phy_vars(struct link_params *params,
3555 struct link_vars *vars)
3557 struct bnx2x *bp = params->bp;
3558 u8 actual_phy_idx, phy_index, link_cfg_idx;
3559 u8 phy_config_swapped = params->multi_phy_config &
3560 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3561 for (phy_index = INT_PHY; phy_index < params->num_phys;
3563 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3564 actual_phy_idx = phy_index;
3565 if (phy_config_swapped) {
3566 if (phy_index == EXT_PHY1)
3567 actual_phy_idx = EXT_PHY2;
3568 else if (phy_index == EXT_PHY2)
3569 actual_phy_idx = EXT_PHY1;
3571 params->phy[actual_phy_idx].req_flow_ctrl =
3572 params->req_flow_ctrl[link_cfg_idx];
3574 params->phy[actual_phy_idx].req_line_speed =
3575 params->req_line_speed[link_cfg_idx];
3577 params->phy[actual_phy_idx].speed_cap_mask =
3578 params->speed_cap_mask[link_cfg_idx];
3580 params->phy[actual_phy_idx].req_duplex =
3581 params->req_duplex[link_cfg_idx];
3583 if (params->req_line_speed[link_cfg_idx] ==
3585 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3587 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3588 " speed_cap_mask %x\n",
3589 params->phy[actual_phy_idx].req_flow_ctrl,
3590 params->phy[actual_phy_idx].req_line_speed,
3591 params->phy[actual_phy_idx].speed_cap_mask);
3595 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3596 struct bnx2x_phy *phy,
3597 struct link_vars *vars)
3600 struct bnx2x *bp = params->bp;
3601 /* read modify write pause advertizing */
3602 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3604 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3606 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3607 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3608 if ((vars->ieee_fc &
3609 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3610 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3611 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3613 if ((vars->ieee_fc &
3614 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3615 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3616 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3618 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3619 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3622 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3624 switch (pause_result) { /* ASYM P ASYM P */
3625 case 0xb: /* 1 0 1 1 */
3626 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3629 case 0xe: /* 1 1 1 0 */
3630 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3633 case 0x5: /* 0 1 0 1 */
3634 case 0x7: /* 0 1 1 1 */
3635 case 0xd: /* 1 1 0 1 */
3636 case 0xf: /* 1 1 1 1 */
3637 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3643 if (pause_result & (1<<0))
3644 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3645 if (pause_result & (1<<1))
3646 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3649 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3650 struct link_params *params,
3651 struct link_vars *vars)
3653 struct bnx2x *bp = params->bp;
3654 u16 ld_pause; /* local */
3655 u16 lp_pause; /* link partner */
3660 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3662 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3663 vars->flow_ctrl = phy->req_flow_ctrl;
3664 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3665 vars->flow_ctrl = params->req_fc_auto_adv;
3666 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3668 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3669 bnx2x_cl22_read(bp, phy,
3671 bnx2x_cl22_read(bp, phy,
3674 bnx2x_cl45_read(bp, phy,
3676 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3677 bnx2x_cl45_read(bp, phy,
3679 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3681 pause_result = (ld_pause &
3682 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3683 pause_result |= (lp_pause &
3684 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3685 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3687 bnx2x_pause_resolve(vars, pause_result);
3691 /******************************************************************/
3692 /* Warpcore section */
3693 /******************************************************************/
3694 /* The init_internal_warpcore should mirror the xgxs,
3695 * i.e. reset the lane (if needed), set aer for the
3696 * init configuration, and set/clear SGMII flag. Internal
3697 * phy init is done purely in phy_init stage.
3699 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3700 struct link_params *params,
3701 struct link_vars *vars) {
3702 u16 val16 = 0, lane, bam37 = 0;
3703 struct bnx2x *bp = params->bp;
3704 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3706 /* Disable Autoneg: re-enable it after adv is done. */
3707 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3708 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3710 /* Check adding advertisement for 1G KX */
3711 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3712 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3713 (vars->line_speed == SPEED_1000)) {
3717 /* Enable CL37 1G Parallel Detect */
3718 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3719 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3720 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3721 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3722 (sd_digital | 0x1));
3724 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3726 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3727 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3728 (vars->line_speed == SPEED_10000)) {
3729 /* Check adding advertisement for 10G KR */
3731 /* Enable 10G Parallel Detect */
3732 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3733 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3735 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3738 /* Set Transmit PMD settings */
3739 lane = bnx2x_get_warpcore_lane(phy, params);
3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3741 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3742 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3743 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3744 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3745 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3746 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3748 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3749 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3752 /* Advertised speeds */
3753 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3754 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3756 /* Advertised and set FEC (Forward Error Correction) */
3757 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3758 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3759 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3760 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3762 /* Enable CL37 BAM */
3763 if (REG_RD(bp, params->shmem_base +
3764 offsetof(struct shmem_region, dev_info.
3765 port_hw_config[params->port].default_cfg)) &
3766 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3767 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3768 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3769 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3770 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3771 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3774 /* Advertise pause */
3775 bnx2x_ext_phy_set_pause(params, phy, vars);
3777 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3779 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3780 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3785 /* Over 1G - AN local device user page 1 */
3786 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3787 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3789 /* Enable Autoneg */
3790 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3791 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3795 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3796 struct link_params *params,
3797 struct link_vars *vars)
3799 struct bnx2x *bp = params->bp;
3802 /* Disable Autoneg */
3803 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3804 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3806 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3807 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3809 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3810 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3812 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3813 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3815 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3816 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3818 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3819 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3821 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3822 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3824 /* Disable CL36 PCS Tx */
3825 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3826 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3828 /* Double Wide Single Data Rate @ pll rate */
3829 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3830 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3832 /* Leave cl72 training enable, needed for KR */
3833 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3834 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3837 /* Leave CL72 enabled */
3838 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3839 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3841 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3842 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3845 /* Set speed via PMA/PMD register */
3846 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3847 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3849 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3850 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3852 /*Enable encoded forced speed */
3853 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3854 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3856 /* Turn TX scramble payload only the 64/66 scrambler */
3857 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3858 MDIO_WC_REG_TX66_CONTROL, 0x9);
3860 /* Turn RX scramble payload only the 64/66 scrambler */
3861 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3862 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3864 /* set and clear loopback to cause a reset to 64/66 decoder */
3865 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3866 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3867 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3868 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3872 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3873 struct link_params *params,
3876 struct bnx2x *bp = params->bp;
3877 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3878 /* Hold rxSeqStart */
3879 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3880 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3881 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3882 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3884 /* Hold tx_fifo_reset */
3885 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3886 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3887 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3890 /* Disable CL73 AN */
3891 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3893 /* Disable 100FX Enable and Auto-Detect */
3894 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3895 MDIO_WC_REG_FX100_CTRL1, &val);
3896 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3897 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3899 /* Disable 100FX Idle detect */
3900 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3901 MDIO_WC_REG_FX100_CTRL3, &val);
3902 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3903 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3905 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3906 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3907 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3908 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3909 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3911 /* Turn off auto-detect & fiber mode */
3912 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3913 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3914 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3915 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3918 /* Set filter_force_link, disable_false_link and parallel_detect */
3919 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3920 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3921 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3922 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3923 ((val | 0x0006) & 0xFFFE));
3926 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3927 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3929 misc1_val &= ~(0x1f);
3933 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3934 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3935 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3937 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3938 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3939 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3943 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3944 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3945 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3947 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3948 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3949 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3951 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3952 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3954 /* Set Transmit PMD settings */
3955 lane = bnx2x_get_warpcore_lane(phy, params);
3956 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957 MDIO_WC_REG_TX_FIR_TAP,
3958 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3959 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3960 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3963 /* Enable fiber mode, enable and invert sig_det */
3964 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3965 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3966 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3967 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3969 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3970 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3971 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3972 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3973 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3975 /* 10G XFI Full Duplex */
3976 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3977 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3979 /* Release tx_fifo_reset */
3980 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3981 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3982 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3983 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3985 /* Release rxSeqStart */
3986 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3987 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3988 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3992 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3993 struct bnx2x_phy *phy)
3995 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3998 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3999 struct bnx2x_phy *phy,
4002 /* Rx0 anaRxControl1G */
4003 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4004 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4006 /* Rx2 anaRxControl1G */
4007 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4008 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4010 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4011 MDIO_WC_REG_RX66_SCW0, 0xE070);
4013 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4014 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4016 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4019 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4020 MDIO_WC_REG_RX66_SCW3, 0x8090);
4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4025 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4026 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4028 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4029 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4031 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4032 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4034 /* Serdes Digital Misc1 */
4035 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4038 /* Serdes Digital4 Misc3 */
4039 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4040 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4042 /* Set Transmit PMD settings */
4043 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044 MDIO_WC_REG_TX_FIR_TAP,
4045 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4046 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4047 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4048 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4049 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4051 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4052 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4053 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4056 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4057 struct link_params *params,
4061 struct bnx2x *bp = params->bp;
4062 u16 val16, digctrl_kx1, digctrl_kx2;
4064 /* Clear XFI clock comp in non-10G single lane mode. */
4065 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4066 MDIO_WC_REG_RX66_CONTROL, &val16);
4067 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4068 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4070 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4072 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4073 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4074 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4075 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4077 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4079 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4080 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4082 switch (phy->req_line_speed) {
4093 "Speed not supported: 0x%x\n", phy->req_line_speed);
4097 if (phy->req_duplex == DUPLEX_FULL)
4100 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4101 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4103 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4104 phy->req_line_speed);
4105 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4106 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4107 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4110 /* SGMII Slave mode and disable signal detect */
4111 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4112 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4116 digctrl_kx1 &= 0xff4a;
4118 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4119 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4122 /* Turn off parallel detect */
4123 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4124 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4125 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4127 (digctrl_kx2 & ~(1<<2)));
4129 /* Re-enable parallel detect */
4130 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4131 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4132 (digctrl_kx2 | (1<<2)));
4134 /* Enable autodet */
4135 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4136 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4137 (digctrl_kx1 | 0x10));
4140 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4141 struct bnx2x_phy *phy,
4145 /* Take lane out of reset after configuration is finished */
4146 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4147 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4152 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4153 MDIO_WC_REG_DIGITAL5_MISC6, val);
4154 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4155 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4159 /* Clear SFI/XFI link settings registers */
4160 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4161 struct link_params *params,
4164 struct bnx2x *bp = params->bp;
4167 /* Set XFI clock comp as default. */
4168 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4169 MDIO_WC_REG_RX66_CONTROL, &val16);
4170 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4171 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4173 bnx2x_warpcore_reset_lane(bp, phy, 1);
4174 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4175 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4176 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4177 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4178 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4181 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4182 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4183 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4184 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4185 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4186 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4187 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4188 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4189 lane = bnx2x_get_warpcore_lane(phy, params);
4190 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4191 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4192 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4193 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4194 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4195 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4196 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4197 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4198 bnx2x_warpcore_reset_lane(bp, phy, 0);
4201 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4203 u32 shmem_base, u8 port,
4204 u8 *gpio_num, u8 *gpio_port)
4209 if (CHIP_IS_E3(bp)) {
4210 cfg_pin = (REG_RD(bp, shmem_base +
4211 offsetof(struct shmem_region,
4212 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4213 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4214 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4217 * Should not happen. This function called upon interrupt
4218 * triggered by GPIO ( since EPIO can only generate interrupts
4220 * So if this function was called and none of the GPIOs was set,
4221 * it means the shit hit the fan.
4223 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4224 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4226 "ERROR: Invalid cfg pin %x for module detect indication\n",
4231 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4232 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4234 *gpio_num = MISC_REGISTERS_GPIO_3;
4237 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4241 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4242 struct link_params *params)
4244 struct bnx2x *bp = params->bp;
4245 u8 gpio_num, gpio_port;
4247 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4248 params->shmem_base, params->port,
4249 &gpio_num, &gpio_port) != 0)
4251 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4253 /* Call the handling function in case module is detected */
4259 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4260 struct link_params *params)
4262 u16 gp2_status_reg0, lane;
4263 struct bnx2x *bp = params->bp;
4265 lane = bnx2x_get_warpcore_lane(phy, params);
4267 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4270 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4273 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4274 struct link_params *params,
4275 struct link_vars *vars)
4277 struct bnx2x *bp = params->bp;
4279 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4280 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4282 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4284 if (!vars->turn_to_run_wc_rt)
4287 /* return if there is no link partner */
4288 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4289 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4293 if (vars->rx_tx_asic_rst) {
4294 serdes_net_if = (REG_RD(bp, params->shmem_base +
4295 offsetof(struct shmem_region, dev_info.
4296 port_hw_config[params->port].default_cfg)) &
4297 PORT_HW_CFG_NET_SERDES_IF_MASK);
4299 switch (serdes_net_if) {
4300 case PORT_HW_CFG_NET_SERDES_IF_KR:
4301 /* Do we get link yet? */
4302 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4304 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4306 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4309 "gp_status1 0x%x\n", gp_status1);
4311 if (lnkup_kr || lnkup) {
4312 vars->rx_tx_asic_rst = 0;
4314 "link up, rx_tx_asic_rst 0x%x\n",
4315 vars->rx_tx_asic_rst);
4317 /*reset the lane to see if link comes up.*/
4318 bnx2x_warpcore_reset_lane(bp, phy, 1);
4319 bnx2x_warpcore_reset_lane(bp, phy, 0);
4321 /* restart Autoneg */
4322 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4323 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4325 vars->rx_tx_asic_rst--;
4326 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4327 vars->rx_tx_asic_rst);
4335 } /*params->rx_tx_asic_rst*/
4339 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4340 struct link_params *params,
4341 struct link_vars *vars)
4343 struct bnx2x *bp = params->bp;
4346 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4347 serdes_net_if = (REG_RD(bp, params->shmem_base +
4348 offsetof(struct shmem_region, dev_info.
4349 port_hw_config[params->port].default_cfg)) &
4350 PORT_HW_CFG_NET_SERDES_IF_MASK);
4351 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4352 "serdes_net_if = 0x%x\n",
4353 vars->line_speed, serdes_net_if);
4354 bnx2x_set_aer_mmd(params, phy);
4356 vars->phy_flags |= PHY_XGXS_FLAG;
4357 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4358 (phy->req_line_speed &&
4359 ((phy->req_line_speed == SPEED_100) ||
4360 (phy->req_line_speed == SPEED_10)))) {
4361 vars->phy_flags |= PHY_SGMII_FLAG;
4362 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4363 bnx2x_warpcore_clear_regs(phy, params, lane);
4364 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4366 switch (serdes_net_if) {
4367 case PORT_HW_CFG_NET_SERDES_IF_KR:
4368 /* Enable KR Auto Neg */
4369 if (params->loopback_mode == LOOPBACK_NONE)
4370 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4372 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4373 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4377 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4378 bnx2x_warpcore_clear_regs(phy, params, lane);
4379 if (vars->line_speed == SPEED_10000) {
4380 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4381 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4383 if (SINGLE_MEDIA_DIRECT(params)) {
4384 DP(NETIF_MSG_LINK, "1G Fiber\n");
4387 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4390 bnx2x_warpcore_set_sgmii_speed(phy,
4398 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4400 bnx2x_warpcore_clear_regs(phy, params, lane);
4401 if (vars->line_speed == SPEED_10000) {
4402 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4403 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4404 } else if (vars->line_speed == SPEED_1000) {
4405 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4406 bnx2x_warpcore_set_sgmii_speed(
4409 /* Issue Module detection */
4410 if (bnx2x_is_sfp_module_plugged(phy, params))
4411 bnx2x_sfp_module_detection(phy, params);
4414 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4415 if (vars->line_speed != SPEED_20000) {
4416 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4419 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4420 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4421 /* Issue Module detection */
4423 bnx2x_sfp_module_detection(phy, params);
4426 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4427 if (vars->line_speed != SPEED_20000) {
4428 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4431 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4432 bnx2x_warpcore_set_20G_KR2(bp, phy);
4437 "Unsupported Serdes Net Interface 0x%x\n",
4443 /* Take lane out of reset after configuration is finished */
4444 bnx2x_warpcore_reset_lane(bp, phy, 0);
4445 DP(NETIF_MSG_LINK, "Exit config init\n");
4448 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4449 struct bnx2x_phy *phy,
4452 struct bnx2x *bp = params->bp;
4454 u8 port = params->port;
4456 cfg_pin = REG_RD(bp, params->shmem_base +
4457 offsetof(struct shmem_region,
4458 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4459 PORT_HW_CFG_TX_LASER_MASK;
4460 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4461 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4462 /* For 20G, the expected pin to be used is 3 pins after the current */
4464 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4465 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4466 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4469 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4470 struct link_params *params)
4472 struct bnx2x *bp = params->bp;
4474 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4475 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4476 bnx2x_set_aer_mmd(params, phy);
4477 /* Global register */
4478 bnx2x_warpcore_reset_lane(bp, phy, 1);
4480 /* Clear loopback settings (if any) */
4482 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4483 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4484 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4485 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4488 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4489 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4490 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4491 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4493 /* Update those 1-copy registers */
4494 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4495 MDIO_AER_BLOCK_AER_REG, 0);
4496 /* Enable 1G MDIO (1-copy) */
4497 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4498 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4500 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4501 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4504 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4505 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4506 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4507 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4512 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4513 struct link_params *params)
4515 struct bnx2x *bp = params->bp;
4518 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4519 params->loopback_mode, phy->req_line_speed);
4521 if (phy->req_line_speed < SPEED_10000) {
4524 /* Update those 1-copy registers */
4525 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4526 MDIO_AER_BLOCK_AER_REG, 0);
4527 /* Enable 1G MDIO (1-copy) */
4528 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4529 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4531 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4532 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4534 /* Set 1G loopback based on lane (1-copy) */
4535 lane = bnx2x_get_warpcore_lane(phy, params);
4536 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4537 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4538 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4539 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4542 /* Switch back to 4-copy registers */
4543 bnx2x_set_aer_mmd(params, phy);
4546 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4547 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4548 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4549 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4552 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4553 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4554 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4555 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4560 void bnx2x_link_status_update(struct link_params *params,
4561 struct link_vars *vars)
4563 struct bnx2x *bp = params->bp;
4565 u8 port = params->port;
4566 u32 sync_offset, media_types;
4567 /* Update PHY configuration */
4568 set_phy_vars(params, vars);
4570 vars->link_status = REG_RD(bp, params->shmem_base +
4571 offsetof(struct shmem_region,
4572 port_mb[port].link_status));
4574 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4575 vars->phy_flags = PHY_XGXS_FLAG;
4576 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4577 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4579 if (vars->link_up) {
4580 DP(NETIF_MSG_LINK, "phy link up\n");
4582 vars->phy_link_up = 1;
4583 vars->duplex = DUPLEX_FULL;
4584 switch (vars->link_status &
4585 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4587 vars->duplex = DUPLEX_HALF;
4590 vars->line_speed = SPEED_10;
4594 vars->duplex = DUPLEX_HALF;
4598 vars->line_speed = SPEED_100;
4602 vars->duplex = DUPLEX_HALF;
4605 vars->line_speed = SPEED_1000;
4609 vars->duplex = DUPLEX_HALF;
4612 vars->line_speed = SPEED_2500;
4616 vars->line_speed = SPEED_10000;
4619 vars->line_speed = SPEED_20000;
4624 vars->flow_ctrl = 0;
4625 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4626 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4628 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4629 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4631 if (!vars->flow_ctrl)
4632 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4634 if (vars->line_speed &&
4635 ((vars->line_speed == SPEED_10) ||
4636 (vars->line_speed == SPEED_100))) {
4637 vars->phy_flags |= PHY_SGMII_FLAG;
4639 vars->phy_flags &= ~PHY_SGMII_FLAG;
4641 if (vars->line_speed &&
4642 USES_WARPCORE(bp) &&
4643 (vars->line_speed == SPEED_1000))
4644 vars->phy_flags |= PHY_SGMII_FLAG;
4645 /* anything 10 and over uses the bmac */
4646 link_10g_plus = (vars->line_speed >= SPEED_10000);
4648 if (link_10g_plus) {
4649 if (USES_WARPCORE(bp))
4650 vars->mac_type = MAC_TYPE_XMAC;
4652 vars->mac_type = MAC_TYPE_BMAC;
4654 if (USES_WARPCORE(bp))
4655 vars->mac_type = MAC_TYPE_UMAC;
4657 vars->mac_type = MAC_TYPE_EMAC;
4659 } else { /* link down */
4660 DP(NETIF_MSG_LINK, "phy link down\n");
4662 vars->phy_link_up = 0;
4664 vars->line_speed = 0;
4665 vars->duplex = DUPLEX_FULL;
4666 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4668 /* indicate no mac active */
4669 vars->mac_type = MAC_TYPE_NONE;
4670 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4671 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4674 /* Sync media type */
4675 sync_offset = params->shmem_base +
4676 offsetof(struct shmem_region,
4677 dev_info.port_hw_config[port].media_type);
4678 media_types = REG_RD(bp, sync_offset);
4680 params->phy[INT_PHY].media_type =
4681 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4682 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4683 params->phy[EXT_PHY1].media_type =
4684 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4685 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4686 params->phy[EXT_PHY2].media_type =
4687 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4688 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4689 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4691 /* Sync AEU offset */
4692 sync_offset = params->shmem_base +
4693 offsetof(struct shmem_region,
4694 dev_info.port_hw_config[port].aeu_int_mask);
4696 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4698 /* Sync PFC status */
4699 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4700 params->feature_config_flags |=
4701 FEATURE_CONFIG_PFC_ENABLED;
4703 params->feature_config_flags &=
4704 ~FEATURE_CONFIG_PFC_ENABLED;
4706 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4707 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4708 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4709 vars->line_speed, vars->duplex, vars->flow_ctrl);
4713 static void bnx2x_set_master_ln(struct link_params *params,
4714 struct bnx2x_phy *phy)
4716 struct bnx2x *bp = params->bp;
4717 u16 new_master_ln, ser_lane;
4718 ser_lane = ((params->lane_config &
4719 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4720 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4722 /* set the master_ln for AN */
4723 CL22_RD_OVER_CL45(bp, phy,
4724 MDIO_REG_BANK_XGXS_BLOCK2,
4725 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4728 CL22_WR_OVER_CL45(bp, phy,
4729 MDIO_REG_BANK_XGXS_BLOCK2 ,
4730 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4731 (new_master_ln | ser_lane));
4734 static int bnx2x_reset_unicore(struct link_params *params,
4735 struct bnx2x_phy *phy,
4738 struct bnx2x *bp = params->bp;
4741 CL22_RD_OVER_CL45(bp, phy,
4742 MDIO_REG_BANK_COMBO_IEEE0,
4743 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4745 /* reset the unicore */
4746 CL22_WR_OVER_CL45(bp, phy,
4747 MDIO_REG_BANK_COMBO_IEEE0,
4748 MDIO_COMBO_IEEE0_MII_CONTROL,
4750 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4752 bnx2x_set_serdes_access(bp, params->port);
4754 /* wait for the reset to self clear */
4755 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4758 /* the reset erased the previous bank value */
4759 CL22_RD_OVER_CL45(bp, phy,
4760 MDIO_REG_BANK_COMBO_IEEE0,
4761 MDIO_COMBO_IEEE0_MII_CONTROL,
4764 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4770 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4773 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4778 static void bnx2x_set_swap_lanes(struct link_params *params,
4779 struct bnx2x_phy *phy)
4781 struct bnx2x *bp = params->bp;
4783 * Each two bits represents a lane number:
4784 * No swap is 0123 => 0x1b no need to enable the swap
4786 u16 ser_lane, rx_lane_swap, tx_lane_swap;
4788 ser_lane = ((params->lane_config &
4789 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4790 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4791 rx_lane_swap = ((params->lane_config &
4792 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4793 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4794 tx_lane_swap = ((params->lane_config &
4795 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4796 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4798 if (rx_lane_swap != 0x1b) {
4799 CL22_WR_OVER_CL45(bp, phy,
4800 MDIO_REG_BANK_XGXS_BLOCK2,
4801 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4803 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4804 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4806 CL22_WR_OVER_CL45(bp, phy,
4807 MDIO_REG_BANK_XGXS_BLOCK2,
4808 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4811 if (tx_lane_swap != 0x1b) {
4812 CL22_WR_OVER_CL45(bp, phy,
4813 MDIO_REG_BANK_XGXS_BLOCK2,
4814 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4816 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4818 CL22_WR_OVER_CL45(bp, phy,
4819 MDIO_REG_BANK_XGXS_BLOCK2,
4820 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4824 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4825 struct link_params *params)
4827 struct bnx2x *bp = params->bp;
4829 CL22_RD_OVER_CL45(bp, phy,
4830 MDIO_REG_BANK_SERDES_DIGITAL,
4831 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4833 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4834 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4836 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4837 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4838 phy->speed_cap_mask, control2);
4839 CL22_WR_OVER_CL45(bp, phy,
4840 MDIO_REG_BANK_SERDES_DIGITAL,
4841 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4844 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4845 (phy->speed_cap_mask &
4846 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4847 DP(NETIF_MSG_LINK, "XGXS\n");
4849 CL22_WR_OVER_CL45(bp, phy,
4850 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4851 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4852 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4854 CL22_RD_OVER_CL45(bp, phy,
4855 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4856 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4861 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4863 CL22_WR_OVER_CL45(bp, phy,
4864 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4865 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4868 /* Disable parallel detection of HiG */
4869 CL22_WR_OVER_CL45(bp, phy,
4870 MDIO_REG_BANK_XGXS_BLOCK2,
4871 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4872 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4873 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4877 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4878 struct link_params *params,
4879 struct link_vars *vars,
4882 struct bnx2x *bp = params->bp;
4886 CL22_RD_OVER_CL45(bp, phy,
4887 MDIO_REG_BANK_COMBO_IEEE0,
4888 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4890 /* CL37 Autoneg Enabled */
4891 if (vars->line_speed == SPEED_AUTO_NEG)
4892 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4893 else /* CL37 Autoneg Disabled */
4894 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4895 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4897 CL22_WR_OVER_CL45(bp, phy,
4898 MDIO_REG_BANK_COMBO_IEEE0,
4899 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4901 /* Enable/Disable Autodetection */
4903 CL22_RD_OVER_CL45(bp, phy,
4904 MDIO_REG_BANK_SERDES_DIGITAL,
4905 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4906 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4907 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4908 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4909 if (vars->line_speed == SPEED_AUTO_NEG)
4910 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4912 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4914 CL22_WR_OVER_CL45(bp, phy,
4915 MDIO_REG_BANK_SERDES_DIGITAL,
4916 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4918 /* Enable TetonII and BAM autoneg */
4919 CL22_RD_OVER_CL45(bp, phy,
4920 MDIO_REG_BANK_BAM_NEXT_PAGE,
4921 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4923 if (vars->line_speed == SPEED_AUTO_NEG) {
4924 /* Enable BAM aneg Mode and TetonII aneg Mode */
4925 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4926 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4928 /* TetonII and BAM Autoneg Disabled */
4929 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4930 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4932 CL22_WR_OVER_CL45(bp, phy,
4933 MDIO_REG_BANK_BAM_NEXT_PAGE,
4934 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4938 /* Enable Cl73 FSM status bits */
4939 CL22_WR_OVER_CL45(bp, phy,
4940 MDIO_REG_BANK_CL73_USERB0,
4941 MDIO_CL73_USERB0_CL73_UCTRL,
4944 /* Enable BAM Station Manager*/
4945 CL22_WR_OVER_CL45(bp, phy,
4946 MDIO_REG_BANK_CL73_USERB0,
4947 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4948 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4949 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4950 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4952 /* Advertise CL73 link speeds */
4953 CL22_RD_OVER_CL45(bp, phy,
4954 MDIO_REG_BANK_CL73_IEEEB1,
4955 MDIO_CL73_IEEEB1_AN_ADV2,
4957 if (phy->speed_cap_mask &
4958 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4959 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4960 if (phy->speed_cap_mask &
4961 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4962 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4964 CL22_WR_OVER_CL45(bp, phy,
4965 MDIO_REG_BANK_CL73_IEEEB1,
4966 MDIO_CL73_IEEEB1_AN_ADV2,
4969 /* CL73 Autoneg Enabled */
4970 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4972 } else /* CL73 Autoneg Disabled */
4975 CL22_WR_OVER_CL45(bp, phy,
4976 MDIO_REG_BANK_CL73_IEEEB0,
4977 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4980 /* program SerDes, forced speed */
4981 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4982 struct link_params *params,
4983 struct link_vars *vars)
4985 struct bnx2x *bp = params->bp;
4988 /* program duplex, disable autoneg and sgmii*/
4989 CL22_RD_OVER_CL45(bp, phy,
4990 MDIO_REG_BANK_COMBO_IEEE0,
4991 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4992 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4993 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4994 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4995 if (phy->req_duplex == DUPLEX_FULL)
4996 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4997 CL22_WR_OVER_CL45(bp, phy,
4998 MDIO_REG_BANK_COMBO_IEEE0,
4999 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5003 * - needed only if the speed is greater than 1G (2.5G or 10G)
5005 CL22_RD_OVER_CL45(bp, phy,
5006 MDIO_REG_BANK_SERDES_DIGITAL,
5007 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5008 /* clearing the speed value before setting the right speed */
5009 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5011 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5012 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5014 if (!((vars->line_speed == SPEED_1000) ||
5015 (vars->line_speed == SPEED_100) ||
5016 (vars->line_speed == SPEED_10))) {
5018 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5019 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5020 if (vars->line_speed == SPEED_10000)
5022 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5025 CL22_WR_OVER_CL45(bp, phy,
5026 MDIO_REG_BANK_SERDES_DIGITAL,
5027 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5031 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5032 struct link_params *params)
5034 struct bnx2x *bp = params->bp;
5037 /* configure the 48 bits for BAM AN */
5039 /* set extended capabilities */
5040 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5041 val |= MDIO_OVER_1G_UP1_2_5G;
5042 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5043 val |= MDIO_OVER_1G_UP1_10G;
5044 CL22_WR_OVER_CL45(bp, phy,
5045 MDIO_REG_BANK_OVER_1G,
5046 MDIO_OVER_1G_UP1, val);
5048 CL22_WR_OVER_CL45(bp, phy,
5049 MDIO_REG_BANK_OVER_1G,
5050 MDIO_OVER_1G_UP3, 0x400);
5053 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5054 struct link_params *params,
5057 struct bnx2x *bp = params->bp;
5059 /* for AN, we are always publishing full duplex */
5061 CL22_WR_OVER_CL45(bp, phy,
5062 MDIO_REG_BANK_COMBO_IEEE0,
5063 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5064 CL22_RD_OVER_CL45(bp, phy,
5065 MDIO_REG_BANK_CL73_IEEEB1,
5066 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5067 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5068 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5069 CL22_WR_OVER_CL45(bp, phy,
5070 MDIO_REG_BANK_CL73_IEEEB1,
5071 MDIO_CL73_IEEEB1_AN_ADV1, val);
5074 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5075 struct link_params *params,
5078 struct bnx2x *bp = params->bp;
5081 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5082 /* Enable and restart BAM/CL37 aneg */
5085 CL22_RD_OVER_CL45(bp, phy,
5086 MDIO_REG_BANK_CL73_IEEEB0,
5087 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5090 CL22_WR_OVER_CL45(bp, phy,
5091 MDIO_REG_BANK_CL73_IEEEB0,
5092 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5094 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5095 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5098 CL22_RD_OVER_CL45(bp, phy,
5099 MDIO_REG_BANK_COMBO_IEEE0,
5100 MDIO_COMBO_IEEE0_MII_CONTROL,
5103 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5105 CL22_WR_OVER_CL45(bp, phy,
5106 MDIO_REG_BANK_COMBO_IEEE0,
5107 MDIO_COMBO_IEEE0_MII_CONTROL,
5109 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5110 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5114 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5115 struct link_params *params,
5116 struct link_vars *vars)
5118 struct bnx2x *bp = params->bp;
5121 /* in SGMII mode, the unicore is always slave */
5123 CL22_RD_OVER_CL45(bp, phy,
5124 MDIO_REG_BANK_SERDES_DIGITAL,
5125 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5127 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5128 /* set sgmii mode (and not fiber) */
5129 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5130 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5131 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5132 CL22_WR_OVER_CL45(bp, phy,
5133 MDIO_REG_BANK_SERDES_DIGITAL,
5134 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5137 /* if forced speed */
5138 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5139 /* set speed, disable autoneg */
5142 CL22_RD_OVER_CL45(bp, phy,
5143 MDIO_REG_BANK_COMBO_IEEE0,
5144 MDIO_COMBO_IEEE0_MII_CONTROL,
5146 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5147 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5148 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5150 switch (vars->line_speed) {
5153 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5157 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5160 /* there is nothing to set for 10M */
5163 /* invalid speed for SGMII */
5164 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5169 /* setting the full duplex */
5170 if (phy->req_duplex == DUPLEX_FULL)
5172 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5173 CL22_WR_OVER_CL45(bp, phy,
5174 MDIO_REG_BANK_COMBO_IEEE0,
5175 MDIO_COMBO_IEEE0_MII_CONTROL,
5178 } else { /* AN mode */
5179 /* enable and restart AN */
5180 bnx2x_restart_autoneg(phy, params, 0);
5189 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5190 struct link_params *params)
5192 struct bnx2x *bp = params->bp;
5193 u16 pd_10g, status2_1000x;
5194 if (phy->req_line_speed != SPEED_AUTO_NEG)
5196 CL22_RD_OVER_CL45(bp, phy,
5197 MDIO_REG_BANK_SERDES_DIGITAL,
5198 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5200 CL22_RD_OVER_CL45(bp, phy,
5201 MDIO_REG_BANK_SERDES_DIGITAL,
5202 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5204 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5205 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5210 CL22_RD_OVER_CL45(bp, phy,
5211 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5212 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5215 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5216 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5223 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5224 struct link_params *params,
5225 struct link_vars *vars,
5228 struct bnx2x *bp = params->bp;
5229 u16 ld_pause; /* local driver */
5230 u16 lp_pause; /* link partner */
5233 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5235 /* resolve from gp_status in case of AN complete and not sgmii */
5236 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5237 vars->flow_ctrl = phy->req_flow_ctrl;
5238 else if (phy->req_line_speed != SPEED_AUTO_NEG)
5239 vars->flow_ctrl = params->req_fc_auto_adv;
5240 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5241 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5242 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5243 vars->flow_ctrl = params->req_fc_auto_adv;
5247 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5248 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5249 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5250 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5252 CL22_RD_OVER_CL45(bp, phy,
5253 MDIO_REG_BANK_CL73_IEEEB1,
5254 MDIO_CL73_IEEEB1_AN_ADV1,
5256 CL22_RD_OVER_CL45(bp, phy,
5257 MDIO_REG_BANK_CL73_IEEEB1,
5258 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5260 pause_result = (ld_pause &
5261 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5263 pause_result |= (lp_pause &
5264 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5266 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5269 CL22_RD_OVER_CL45(bp, phy,
5270 MDIO_REG_BANK_COMBO_IEEE0,
5271 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5273 CL22_RD_OVER_CL45(bp, phy,
5274 MDIO_REG_BANK_COMBO_IEEE0,
5275 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5277 pause_result = (ld_pause &
5278 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5279 pause_result |= (lp_pause &
5280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5281 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5284 bnx2x_pause_resolve(vars, pause_result);
5286 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5289 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5290 struct link_params *params)
5292 struct bnx2x *bp = params->bp;
5293 u16 rx_status, ustat_val, cl37_fsm_received;
5294 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5295 /* Step 1: Make sure signal is detected */
5296 CL22_RD_OVER_CL45(bp, phy,
5300 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5301 (MDIO_RX0_RX_STATUS_SIGDET)) {
5302 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5303 "rx_status(0x80b0) = 0x%x\n", rx_status);
5304 CL22_WR_OVER_CL45(bp, phy,
5305 MDIO_REG_BANK_CL73_IEEEB0,
5306 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5307 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5310 /* Step 2: Check CL73 state machine */
5311 CL22_RD_OVER_CL45(bp, phy,
5312 MDIO_REG_BANK_CL73_USERB0,
5313 MDIO_CL73_USERB0_CL73_USTAT1,
5316 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5317 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5318 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5319 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5320 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5321 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5325 * Step 3: Check CL37 Message Pages received to indicate LP
5326 * supports only CL37
5328 CL22_RD_OVER_CL45(bp, phy,
5329 MDIO_REG_BANK_REMOTE_PHY,
5330 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5331 &cl37_fsm_received);
5332 if ((cl37_fsm_received &
5333 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5334 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5335 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5336 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5337 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5338 "misc_rx_status(0x8330) = 0x%x\n",
5343 * The combined cl37/cl73 fsm state information indicating that
5344 * we are connected to a device which does not support cl73, but
5345 * does support cl37 BAM. In this case we disable cl73 and
5346 * restart cl37 auto-neg
5350 CL22_WR_OVER_CL45(bp, phy,
5351 MDIO_REG_BANK_CL73_IEEEB0,
5352 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5354 /* Restart CL37 autoneg */
5355 bnx2x_restart_autoneg(phy, params, 0);
5356 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5359 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5360 struct link_params *params,
5361 struct link_vars *vars,
5364 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5365 vars->link_status |=
5366 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5368 if (bnx2x_direct_parallel_detect_used(phy, params))
5369 vars->link_status |=
5370 LINK_STATUS_PARALLEL_DETECTION_USED;
5372 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5373 struct link_params *params,
5374 struct link_vars *vars,
5379 struct bnx2x *bp = params->bp;
5380 if (phy->req_line_speed == SPEED_AUTO_NEG)
5381 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5383 DP(NETIF_MSG_LINK, "phy link up\n");
5385 vars->phy_link_up = 1;
5386 vars->link_status |= LINK_STATUS_LINK_UP;
5388 switch (speed_mask) {
5390 vars->line_speed = SPEED_10;
5391 if (vars->duplex == DUPLEX_FULL)
5392 vars->link_status |= LINK_10TFD;
5394 vars->link_status |= LINK_10THD;
5397 case GP_STATUS_100M:
5398 vars->line_speed = SPEED_100;
5399 if (vars->duplex == DUPLEX_FULL)
5400 vars->link_status |= LINK_100TXFD;
5402 vars->link_status |= LINK_100TXHD;
5406 case GP_STATUS_1G_KX:
5407 vars->line_speed = SPEED_1000;
5408 if (vars->duplex == DUPLEX_FULL)
5409 vars->link_status |= LINK_1000TFD;
5411 vars->link_status |= LINK_1000THD;
5414 case GP_STATUS_2_5G:
5415 vars->line_speed = SPEED_2500;
5416 if (vars->duplex == DUPLEX_FULL)
5417 vars->link_status |= LINK_2500TFD;
5419 vars->link_status |= LINK_2500THD;
5425 "link speed unsupported gp_status 0x%x\n",
5429 case GP_STATUS_10G_KX4:
5430 case GP_STATUS_10G_HIG:
5431 case GP_STATUS_10G_CX4:
5432 case GP_STATUS_10G_KR:
5433 case GP_STATUS_10G_SFI:
5434 case GP_STATUS_10G_XFI:
5435 vars->line_speed = SPEED_10000;
5436 vars->link_status |= LINK_10GTFD;
5438 case GP_STATUS_20G_DXGXS:
5439 vars->line_speed = SPEED_20000;
5440 vars->link_status |= LINK_20GTFD;
5444 "link speed unsupported gp_status 0x%x\n",
5448 } else { /* link_down */
5449 DP(NETIF_MSG_LINK, "phy link down\n");
5451 vars->phy_link_up = 0;
5453 vars->duplex = DUPLEX_FULL;
5454 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5455 vars->mac_type = MAC_TYPE_NONE;
5457 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5458 vars->phy_link_up, vars->line_speed);
5462 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5463 struct link_params *params,
5464 struct link_vars *vars)
5467 struct bnx2x *bp = params->bp;
5469 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5472 /* Read gp_status */
5473 CL22_RD_OVER_CL45(bp, phy,
5474 MDIO_REG_BANK_GP_STATUS,
5475 MDIO_GP_STATUS_TOP_AN_STATUS1,
5477 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5478 duplex = DUPLEX_FULL;
5479 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5481 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5482 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5483 gp_status, link_up, speed_mask);
5484 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5489 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5490 if (SINGLE_MEDIA_DIRECT(params)) {
5491 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5492 if (phy->req_line_speed == SPEED_AUTO_NEG)
5493 bnx2x_xgxs_an_resolve(phy, params, vars,
5496 } else { /* link_down */
5497 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5498 SINGLE_MEDIA_DIRECT(params)) {
5499 /* Check signal is detected */
5500 bnx2x_check_fallback_to_cl37(phy, params);
5504 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5505 vars->duplex, vars->flow_ctrl, vars->link_status);
5509 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5510 struct link_params *params,
5511 struct link_vars *vars)
5514 struct bnx2x *bp = params->bp;
5517 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5519 lane = bnx2x_get_warpcore_lane(phy, params);
5520 /* Read gp_status */
5521 if (phy->req_line_speed > SPEED_10000) {
5523 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5525 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5527 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5528 temp_link_up, link_up);
5531 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5533 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5534 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5535 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5536 /* Check for either KR or generic link up. */
5537 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5538 ((gp_status1 >> 12) & 0xf);
5539 link_up = gp_status1 & (1 << lane);
5540 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5542 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5543 /* Check Autoneg complete */
5544 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5545 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5547 if (gp_status4 & ((1<<12)<<lane))
5548 vars->link_status |=
5549 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5551 /* Check parallel detect used */
5552 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5553 MDIO_WC_REG_PAR_DET_10G_STATUS,
5556 vars->link_status |=
5557 LINK_STATUS_PARALLEL_DETECTION_USED;
5559 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5564 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5565 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5567 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5568 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5570 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5572 if ((lane & 1) == 0)
5577 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5580 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5581 vars->duplex, vars->flow_ctrl, vars->link_status);
5584 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5586 struct bnx2x *bp = params->bp;
5587 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5593 CL22_RD_OVER_CL45(bp, phy,
5594 MDIO_REG_BANK_OVER_1G,
5595 MDIO_OVER_1G_LP_UP2, &lp_up2);
5597 /* bits [10:7] at lp_up2, positioned at [15:12] */
5598 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5599 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5600 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5605 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5606 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5607 CL22_RD_OVER_CL45(bp, phy,
5609 MDIO_TX0_TX_DRIVER, &tx_driver);
5611 /* replace tx_driver bits [15:12] */
5613 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5614 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5615 tx_driver |= lp_up2;
5616 CL22_WR_OVER_CL45(bp, phy,
5618 MDIO_TX0_TX_DRIVER, tx_driver);
5623 static int bnx2x_emac_program(struct link_params *params,
5624 struct link_vars *vars)
5626 struct bnx2x *bp = params->bp;
5627 u8 port = params->port;
5630 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5631 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5633 (EMAC_MODE_25G_MODE |
5634 EMAC_MODE_PORT_MII_10M |
5635 EMAC_MODE_HALF_DUPLEX));
5636 switch (vars->line_speed) {
5638 mode |= EMAC_MODE_PORT_MII_10M;
5642 mode |= EMAC_MODE_PORT_MII;
5646 mode |= EMAC_MODE_PORT_GMII;
5650 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5654 /* 10G not valid for EMAC */
5655 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5660 if (vars->duplex == DUPLEX_HALF)
5661 mode |= EMAC_MODE_HALF_DUPLEX;
5663 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5666 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5670 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5671 struct link_params *params)
5675 struct bnx2x *bp = params->bp;
5677 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5678 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5679 CL22_WR_OVER_CL45(bp, phy,
5681 MDIO_RX0_RX_EQ_BOOST,
5682 phy->rx_preemphasis[i]);
5685 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5686 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5687 CL22_WR_OVER_CL45(bp, phy,
5690 phy->tx_preemphasis[i]);
5694 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5695 struct link_params *params,
5696 struct link_vars *vars)
5698 struct bnx2x *bp = params->bp;
5699 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5700 (params->loopback_mode == LOOPBACK_XGXS));
5701 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5702 if (SINGLE_MEDIA_DIRECT(params) &&
5703 (params->feature_config_flags &
5704 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5705 bnx2x_set_preemphasis(phy, params);
5707 /* forced speed requested? */
5708 if (vars->line_speed != SPEED_AUTO_NEG ||
5709 (SINGLE_MEDIA_DIRECT(params) &&
5710 params->loopback_mode == LOOPBACK_EXT)) {
5711 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5713 /* disable autoneg */
5714 bnx2x_set_autoneg(phy, params, vars, 0);
5716 /* program speed and duplex */
5717 bnx2x_program_serdes(phy, params, vars);
5719 } else { /* AN_mode */
5720 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5723 bnx2x_set_brcm_cl37_advertisement(phy, params);
5725 /* program duplex & pause advertisement (for aneg) */
5726 bnx2x_set_ieee_aneg_advertisement(phy, params,
5729 /* enable autoneg */
5730 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5732 /* enable and restart AN */
5733 bnx2x_restart_autoneg(phy, params, enable_cl73);
5736 } else { /* SGMII mode */
5737 DP(NETIF_MSG_LINK, "SGMII\n");
5739 bnx2x_initialize_sgmii_process(phy, params, vars);
5743 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5744 struct link_params *params,
5745 struct link_vars *vars)
5748 vars->phy_flags |= PHY_XGXS_FLAG;
5749 if ((phy->req_line_speed &&
5750 ((phy->req_line_speed == SPEED_100) ||
5751 (phy->req_line_speed == SPEED_10))) ||
5752 (!phy->req_line_speed &&
5753 (phy->speed_cap_mask >=
5754 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5755 (phy->speed_cap_mask <
5756 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5757 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5758 vars->phy_flags |= PHY_SGMII_FLAG;
5760 vars->phy_flags &= ~PHY_SGMII_FLAG;
5762 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5763 bnx2x_set_aer_mmd(params, phy);
5764 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5765 bnx2x_set_master_ln(params, phy);
5767 rc = bnx2x_reset_unicore(params, phy, 0);
5768 /* reset the SerDes and wait for reset bit return low */
5772 bnx2x_set_aer_mmd(params, phy);
5773 /* setting the masterLn_def again after the reset */
5774 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5775 bnx2x_set_master_ln(params, phy);
5776 bnx2x_set_swap_lanes(params, phy);
5782 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5783 struct bnx2x_phy *phy,
5784 struct link_params *params)
5787 /* Wait for soft reset to get cleared up to 1 sec */
5788 for (cnt = 0; cnt < 1000; cnt++) {
5789 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5790 bnx2x_cl22_read(bp, phy,
5791 MDIO_PMA_REG_CTRL, &ctrl);
5793 bnx2x_cl45_read(bp, phy,
5795 MDIO_PMA_REG_CTRL, &ctrl);
5796 if (!(ctrl & (1<<15)))
5802 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5805 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5809 static void bnx2x_link_int_enable(struct link_params *params)
5811 u8 port = params->port;
5813 struct bnx2x *bp = params->bp;
5815 /* Setting the status to report on link up for either XGXS or SerDes */
5816 if (CHIP_IS_E3(bp)) {
5817 mask = NIG_MASK_XGXS0_LINK_STATUS;
5818 if (!(SINGLE_MEDIA_DIRECT(params)))
5819 mask |= NIG_MASK_MI_INT;
5820 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5821 mask = (NIG_MASK_XGXS0_LINK10G |
5822 NIG_MASK_XGXS0_LINK_STATUS);
5823 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5824 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5825 params->phy[INT_PHY].type !=
5826 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5827 mask |= NIG_MASK_MI_INT;
5828 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5831 } else { /* SerDes */
5832 mask = NIG_MASK_SERDES0_LINK_STATUS;
5833 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5834 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5835 params->phy[INT_PHY].type !=
5836 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5837 mask |= NIG_MASK_MI_INT;
5838 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5842 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5845 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5846 (params->switch_cfg == SWITCH_CFG_10G),
5847 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5848 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5849 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5850 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5851 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5852 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5853 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5854 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5857 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5860 u32 latch_status = 0;
5863 * Disable the MI INT ( external phy int ) by writing 1 to the
5864 * status register. Link down indication is high-active-signal,
5865 * so in this case we need to write the status to clear the XOR
5867 /* Read Latched signals */
5868 latch_status = REG_RD(bp,
5869 NIG_REG_LATCH_STATUS_0 + port*8);
5870 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5871 /* Handle only those with latched-signal=up.*/
5874 NIG_REG_STATUS_INTERRUPT_PORT0
5876 NIG_STATUS_EMAC0_MI_INT);
5879 NIG_REG_STATUS_INTERRUPT_PORT0
5881 NIG_STATUS_EMAC0_MI_INT);
5883 if (latch_status & 1) {
5885 /* For all latched-signal=up : Re-Arm Latch signals */
5886 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5887 (latch_status & 0xfffe) | (latch_status & 1));
5889 /* For all latched-signal=up,Write original_signal to status */
5892 static void bnx2x_link_int_ack(struct link_params *params,
5893 struct link_vars *vars, u8 is_10g_plus)
5895 struct bnx2x *bp = params->bp;
5896 u8 port = params->port;
5899 * First reset all status we assume only one line will be
5902 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5903 (NIG_STATUS_XGXS0_LINK10G |
5904 NIG_STATUS_XGXS0_LINK_STATUS |
5905 NIG_STATUS_SERDES0_LINK_STATUS));
5906 if (vars->phy_link_up) {
5907 if (USES_WARPCORE(bp))
5908 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5911 mask = NIG_STATUS_XGXS0_LINK10G;
5912 else if (params->switch_cfg == SWITCH_CFG_10G) {
5914 * Disable the link interrupt by writing 1 to
5915 * the relevant lane in the status register
5918 ((params->lane_config &
5919 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5920 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5921 mask = ((1 << ser_lane) <<
5922 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5924 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5926 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5929 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5934 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5937 u32 mask = 0xf0000000;
5940 u8 remove_leading_zeros = 1;
5942 /* Need more than 10chars for this format */
5950 digit = ((num & mask) >> shift);
5951 if (digit == 0 && remove_leading_zeros) {
5954 } else if (digit < 0xa)
5955 *str_ptr = digit + '0';
5957 *str_ptr = digit - 0xa + 'a';
5958 remove_leading_zeros = 0;
5966 remove_leading_zeros = 1;
5973 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5980 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5981 u8 *version, u16 len)
5986 u8 *ver_p = version;
5987 u16 remain_len = len;
5988 if (version == NULL || params == NULL)
5992 /* Extract first external phy*/
5994 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5996 if (params->phy[EXT_PHY1].format_fw_ver) {
5997 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6000 ver_p += (len - remain_len);
6002 if ((params->num_phys == MAX_PHYS) &&
6003 (params->phy[EXT_PHY2].ver_addr != 0)) {
6004 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6005 if (params->phy[EXT_PHY2].format_fw_ver) {
6009 status |= params->phy[EXT_PHY2].format_fw_ver(
6013 ver_p = version + (len - remain_len);
6020 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6021 struct link_params *params)
6023 u8 port = params->port;
6024 struct bnx2x *bp = params->bp;
6026 if (phy->req_line_speed != SPEED_1000) {
6029 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6031 if (!CHIP_IS_E3(bp)) {
6032 /* change the uni_phy_addr in the nig */
6033 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6036 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6040 bnx2x_cl45_write(bp, phy,
6042 (MDIO_REG_BANK_AER_BLOCK +
6043 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6046 bnx2x_cl45_write(bp, phy,
6048 (MDIO_REG_BANK_CL73_IEEEB0 +
6049 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6052 /* set aer mmd back */
6053 bnx2x_set_aer_mmd(params, phy);
6055 if (!CHIP_IS_E3(bp)) {
6057 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6062 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6063 bnx2x_cl45_read(bp, phy, 5,
6064 (MDIO_REG_BANK_COMBO_IEEE0 +
6065 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6067 bnx2x_cl45_write(bp, phy, 5,
6068 (MDIO_REG_BANK_COMBO_IEEE0 +
6069 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6071 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6075 int bnx2x_set_led(struct link_params *params,
6076 struct link_vars *vars, u8 mode, u32 speed)
6078 u8 port = params->port;
6079 u16 hw_led_mode = params->hw_led_mode;
6083 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6084 struct bnx2x *bp = params->bp;
6085 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6086 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6087 speed, hw_led_mode);
6089 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6090 if (params->phy[phy_idx].set_link_led) {
6091 params->phy[phy_idx].set_link_led(
6092 ¶ms->phy[phy_idx], params, mode);
6097 case LED_MODE_FRONT_PANEL_OFF:
6099 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6100 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6101 SHARED_HW_CFG_LED_MAC1);
6103 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6104 if (params->phy[EXT_PHY1].type ==
6105 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6106 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp & 0xfff1);
6108 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6109 (tmp | EMAC_LED_OVERRIDE));
6115 * For all other phys, OPER mode is same as ON, so in case
6116 * link is down, do nothing
6121 if (((params->phy[EXT_PHY1].type ==
6122 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6123 (params->phy[EXT_PHY1].type ==
6124 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6125 CHIP_IS_E2(bp) && params->num_phys == 2) {
6127 * This is a work-around for E2+8727 Configurations
6129 if (mode == LED_MODE_ON ||
6130 speed == SPEED_10000){
6131 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6132 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6134 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6135 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6136 (tmp | EMAC_LED_OVERRIDE));
6138 * return here without enabling traffic
6139 * LED blink and setting rate in ON mode.
6140 * In oper mode, enabling LED blink
6141 * and setting rate is needed.
6143 if (mode == LED_MODE_ON)
6146 } else if (SINGLE_MEDIA_DIRECT(params)) {
6148 * This is a work-around for HW issue found when link
6151 if ((!CHIP_IS_E3(bp)) ||
6153 mode == LED_MODE_ON))
6154 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6156 if (CHIP_IS_E1x(bp) ||
6158 (mode == LED_MODE_ON))
6159 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6161 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6163 } else if ((params->phy[EXT_PHY1].type ==
6164 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6165 (mode != LED_MODE_OPER)) {
6166 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6167 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6168 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 0x3);
6170 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6173 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6174 /* Set blinking rate to ~15.9Hz */
6176 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6177 LED_BLINK_RATE_VAL_E3);
6179 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6180 LED_BLINK_RATE_VAL_E1X_E2);
6181 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6183 if ((params->phy[EXT_PHY1].type !=
6184 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6185 (mode != LED_MODE_OPER)) {
6186 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6187 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6188 (tmp & (~EMAC_LED_OVERRIDE)));
6191 if (CHIP_IS_E1(bp) &&
6192 ((speed == SPEED_2500) ||
6193 (speed == SPEED_1000) ||
6194 (speed == SPEED_100) ||
6195 (speed == SPEED_10))) {
6197 * On Everest 1 Ax chip versions for speeds less than
6198 * 10G LED scheme is different
6200 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6202 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6204 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6211 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6220 * This function comes to reflect the actual link state read DIRECTLY from the
6223 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6226 struct bnx2x *bp = params->bp;
6227 u16 gp_status = 0, phy_index = 0;
6228 u8 ext_phy_link_up = 0, serdes_phy_type;
6229 struct link_vars temp_vars;
6230 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6232 if (CHIP_IS_E3(bp)) {
6234 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6236 /* Check 20G link */
6237 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6239 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6243 /* Check 10G link and below*/
6244 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6245 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6246 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6248 gp_status = ((gp_status >> 8) & 0xf) |
6249 ((gp_status >> 12) & 0xf);
6250 link_up = gp_status & (1 << lane);
6255 CL22_RD_OVER_CL45(bp, int_phy,
6256 MDIO_REG_BANK_GP_STATUS,
6257 MDIO_GP_STATUS_TOP_AN_STATUS1,
6259 /* link is up only if both local phy and external phy are up */
6260 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6263 /* In XGXS loopback mode, do not check external PHY */
6264 if (params->loopback_mode == LOOPBACK_XGXS)
6267 switch (params->num_phys) {
6269 /* No external PHY */
6272 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6273 ¶ms->phy[EXT_PHY1],
6274 params, &temp_vars);
6276 case 3: /* Dual Media */
6277 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6279 serdes_phy_type = ((params->phy[phy_index].media_type ==
6280 ETH_PHY_SFP_FIBER) ||
6281 (params->phy[phy_index].media_type ==
6282 ETH_PHY_XFP_FIBER) ||
6283 (params->phy[phy_index].media_type ==
6284 ETH_PHY_DA_TWINAX));
6286 if (is_serdes != serdes_phy_type)
6288 if (params->phy[phy_index].read_status) {
6290 params->phy[phy_index].read_status(
6291 ¶ms->phy[phy_index],
6292 params, &temp_vars);
6297 if (ext_phy_link_up)
6302 static int bnx2x_link_initialize(struct link_params *params,
6303 struct link_vars *vars)
6306 u8 phy_index, non_ext_phy;
6307 struct bnx2x *bp = params->bp;
6309 * In case of external phy existence, the line speed would be the
6310 * line speed linked up by the external phy. In case it is direct
6311 * only, then the line_speed during initialization will be
6312 * equal to the req_line_speed
6314 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6317 * Initialize the internal phy in case this is a direct board
6318 * (no external phys), or this board has external phy which requires
6321 if (!USES_WARPCORE(bp))
6322 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6323 /* init ext phy and enable link state int */
6324 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6325 (params->loopback_mode == LOOPBACK_XGXS));
6328 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6329 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6330 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6331 if (vars->line_speed == SPEED_AUTO_NEG &&
6334 bnx2x_set_parallel_detection(phy, params);
6335 if (params->phy[INT_PHY].config_init)
6336 params->phy[INT_PHY].config_init(phy,
6341 /* Init external phy*/
6343 if (params->phy[INT_PHY].supported &
6345 vars->link_status |= LINK_STATUS_SERDES_LINK;
6347 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6350 * No need to initialize second phy in case of first
6351 * phy only selection. In case of second phy, we do
6352 * need to initialize the first phy, since they are
6355 if (params->phy[phy_index].supported &
6357 vars->link_status |= LINK_STATUS_SERDES_LINK;
6359 if (phy_index == EXT_PHY2 &&
6360 (bnx2x_phy_selection(params) ==
6361 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6363 "Not initializing second phy\n");
6366 params->phy[phy_index].config_init(
6367 ¶ms->phy[phy_index],
6371 /* Reset the interrupt indication after phy was initialized */
6372 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6374 (NIG_STATUS_XGXS0_LINK10G |
6375 NIG_STATUS_XGXS0_LINK_STATUS |
6376 NIG_STATUS_SERDES0_LINK_STATUS |
6378 bnx2x_update_mng(params, vars->link_status);
6382 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6383 struct link_params *params)
6385 /* reset the SerDes/XGXS */
6386 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6387 (0x1ff << (params->port*16)));
6390 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6391 struct link_params *params)
6393 struct bnx2x *bp = params->bp;
6397 gpio_port = BP_PATH(bp);
6399 gpio_port = params->port;
6400 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6401 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6403 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6404 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6406 DP(NETIF_MSG_LINK, "reset external PHY\n");
6409 static int bnx2x_update_link_down(struct link_params *params,
6410 struct link_vars *vars)
6412 struct bnx2x *bp = params->bp;
6413 u8 port = params->port;
6415 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6416 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6417 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6418 /* indicate no mac active */
6419 vars->mac_type = MAC_TYPE_NONE;
6421 /* update shared memory */
6422 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6423 LINK_STATUS_LINK_UP |
6424 LINK_STATUS_PHYSICAL_LINK_FLAG |
6425 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6426 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6427 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6428 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6429 vars->line_speed = 0;
6430 bnx2x_update_mng(params, vars->link_status);
6432 /* activate nig drain */
6433 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6436 if (!CHIP_IS_E3(bp))
6437 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6440 /* reset BigMac/Xmac */
6441 if (CHIP_IS_E1x(bp) ||
6443 bnx2x_bmac_rx_disable(bp, params->port);
6444 REG_WR(bp, GRCBASE_MISC +
6445 MISC_REGISTERS_RESET_REG_2_CLEAR,
6446 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6448 if (CHIP_IS_E3(bp)) {
6449 bnx2x_xmac_disable(params);
6450 bnx2x_umac_disable(params);
6456 static int bnx2x_update_link_up(struct link_params *params,
6457 struct link_vars *vars,
6460 struct bnx2x *bp = params->bp;
6461 u8 port = params->port;
6464 vars->link_status |= (LINK_STATUS_LINK_UP |
6465 LINK_STATUS_PHYSICAL_LINK_FLAG);
6466 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6468 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6469 vars->link_status |=
6470 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6472 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6473 vars->link_status |=
6474 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6475 if (USES_WARPCORE(bp)) {
6477 if (bnx2x_xmac_enable(params, vars, 0) ==
6479 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6481 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6482 vars->link_status &= ~LINK_STATUS_LINK_UP;
6485 bnx2x_umac_enable(params, vars, 0);
6486 bnx2x_set_led(params, vars,
6487 LED_MODE_OPER, vars->line_speed);
6489 if ((CHIP_IS_E1x(bp) ||
6492 if (bnx2x_bmac_enable(params, vars, 0) ==
6494 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6496 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6497 vars->link_status &= ~LINK_STATUS_LINK_UP;
6500 bnx2x_set_led(params, vars,
6501 LED_MODE_OPER, SPEED_10000);
6503 rc = bnx2x_emac_program(params, vars);
6504 bnx2x_emac_enable(params, vars, 0);
6507 if ((vars->link_status &
6508 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6509 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6510 SINGLE_MEDIA_DIRECT(params))
6511 bnx2x_set_gmii_tx_driver(params);
6516 if (CHIP_IS_E1x(bp))
6517 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6521 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6523 /* update shared memory */
6524 bnx2x_update_mng(params, vars->link_status);
6529 * The bnx2x_link_update function should be called upon link
6531 * Link is considered up as follows:
6532 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6534 * - SINGLE_MEDIA - The link between the 577xx and the external
6535 * phy (XGXS) need to up as well as the external link of the
6537 * - DUAL_MEDIA - The link between the 577xx and the first
6538 * external phy needs to be up, and at least one of the 2
6539 * external phy link must be up.
6541 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6543 struct bnx2x *bp = params->bp;
6544 struct link_vars phy_vars[MAX_PHYS];
6545 u8 port = params->port;
6546 u8 link_10g_plus, phy_index;
6547 u8 ext_phy_link_up = 0, cur_link_up;
6550 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6551 u8 active_external_phy = INT_PHY;
6552 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6553 for (phy_index = INT_PHY; phy_index < params->num_phys;
6555 phy_vars[phy_index].flow_ctrl = 0;
6556 phy_vars[phy_index].link_status = 0;
6557 phy_vars[phy_index].line_speed = 0;
6558 phy_vars[phy_index].duplex = DUPLEX_FULL;
6559 phy_vars[phy_index].phy_link_up = 0;
6560 phy_vars[phy_index].link_up = 0;
6561 phy_vars[phy_index].fault_detected = 0;
6564 if (USES_WARPCORE(bp))
6565 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6567 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6568 port, (vars->phy_flags & PHY_XGXS_FLAG),
6569 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6571 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6573 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6574 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6576 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6578 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6579 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6580 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6583 if (!CHIP_IS_E3(bp))
6584 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6588 * Check external link change only for external phys, and apply
6589 * priority selection between them in case the link on both phys
6590 * is up. Note that instead of the common vars, a temporary
6591 * vars argument is used since each phy may have different link/
6592 * speed/duplex result
6594 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6596 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6597 if (!phy->read_status)
6599 /* Read link status and params of this ext phy */
6600 cur_link_up = phy->read_status(phy, params,
6601 &phy_vars[phy_index]);
6603 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6606 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6611 if (!ext_phy_link_up) {
6612 ext_phy_link_up = 1;
6613 active_external_phy = phy_index;
6615 switch (bnx2x_phy_selection(params)) {
6616 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6617 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6619 * In this option, the first PHY makes sure to pass the
6620 * traffic through itself only.
6621 * Its not clear how to reset the link on the second phy
6623 active_external_phy = EXT_PHY1;
6625 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6627 * In this option, the first PHY makes sure to pass the
6628 * traffic through the second PHY.
6630 active_external_phy = EXT_PHY2;
6634 * Link indication on both PHYs with the following cases
6636 * - FIRST_PHY means that second phy wasn't initialized,
6637 * hence its link is expected to be down
6638 * - SECOND_PHY means that first phy should not be able
6639 * to link up by itself (using configuration)
6640 * - DEFAULT should be overriden during initialiazation
6642 DP(NETIF_MSG_LINK, "Invalid link indication"
6643 "mpc=0x%x. DISABLING LINK !!!\n",
6644 params->multi_phy_config);
6645 ext_phy_link_up = 0;
6650 prev_line_speed = vars->line_speed;
6653 * Read the status of the internal phy. In case of
6654 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6655 * otherwise this is the link between the 577xx and the first
6658 if (params->phy[INT_PHY].read_status)
6659 params->phy[INT_PHY].read_status(
6660 ¶ms->phy[INT_PHY],
6663 * The INT_PHY flow control reside in the vars. This include the
6664 * case where the speed or flow control are not set to AUTO.
6665 * Otherwise, the active external phy flow control result is set
6666 * to the vars. The ext_phy_line_speed is needed to check if the
6667 * speed is different between the internal phy and external phy.
6668 * This case may be result of intermediate link speed change.
6670 if (active_external_phy > INT_PHY) {
6671 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6673 * Link speed is taken from the XGXS. AN and FC result from
6676 vars->link_status |= phy_vars[active_external_phy].link_status;
6679 * if active_external_phy is first PHY and link is up - disable
6680 * disable TX on second external PHY
6682 if (active_external_phy == EXT_PHY1) {
6683 if (params->phy[EXT_PHY2].phy_specific_func) {
6685 "Disabling TX on EXT_PHY2\n");
6686 params->phy[EXT_PHY2].phy_specific_func(
6687 ¶ms->phy[EXT_PHY2],
6688 params, DISABLE_TX);
6692 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6693 vars->duplex = phy_vars[active_external_phy].duplex;
6694 if (params->phy[active_external_phy].supported &
6696 vars->link_status |= LINK_STATUS_SERDES_LINK;
6698 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6699 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6700 active_external_phy);
6703 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6705 if (params->phy[phy_index].flags &
6706 FLAGS_REARM_LATCH_SIGNAL) {
6707 bnx2x_rearm_latch_signal(bp, port,
6709 active_external_phy);
6713 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6714 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6715 vars->link_status, ext_phy_line_speed);
6717 * Upon link speed change set the NIG into drain mode. Comes to
6718 * deals with possible FIFO glitch due to clk change when speed
6719 * is decreased without link down indicator
6722 if (vars->phy_link_up) {
6723 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6724 (ext_phy_line_speed != vars->line_speed)) {
6725 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6726 " different than the external"
6727 " link speed %d\n", vars->line_speed,
6728 ext_phy_line_speed);
6729 vars->phy_link_up = 0;
6730 } else if (prev_line_speed != vars->line_speed) {
6731 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6737 /* anything 10 and over uses the bmac */
6738 link_10g_plus = (vars->line_speed >= SPEED_10000);
6740 bnx2x_link_int_ack(params, vars, link_10g_plus);
6743 * In case external phy link is up, and internal link is down
6744 * (not initialized yet probably after link initialization, it
6745 * needs to be initialized.
6746 * Note that after link down-up as result of cable plug, the xgxs
6747 * link would probably become up again without the need
6750 if (!(SINGLE_MEDIA_DIRECT(params))) {
6751 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6752 " init_preceding = %d\n", ext_phy_link_up,
6754 params->phy[EXT_PHY1].flags &
6755 FLAGS_INIT_XGXS_FIRST);
6756 if (!(params->phy[EXT_PHY1].flags &
6757 FLAGS_INIT_XGXS_FIRST)
6758 && ext_phy_link_up && !vars->phy_link_up) {
6759 vars->line_speed = ext_phy_line_speed;
6760 if (vars->line_speed < SPEED_1000)
6761 vars->phy_flags |= PHY_SGMII_FLAG;
6763 vars->phy_flags &= ~PHY_SGMII_FLAG;
6765 if (params->phy[INT_PHY].config_init)
6766 params->phy[INT_PHY].config_init(
6767 ¶ms->phy[INT_PHY], params,
6772 * Link is up only if both local phy and external phy (in case of
6773 * non-direct board) are up and no fault detected on active PHY.
6775 vars->link_up = (vars->phy_link_up &&
6777 SINGLE_MEDIA_DIRECT(params)) &&
6778 (phy_vars[active_external_phy].fault_detected == 0));
6781 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6783 rc = bnx2x_update_link_down(params, vars);
6789 /*****************************************************************************/
6790 /* External Phy section */
6791 /*****************************************************************************/
6792 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6794 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6795 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6797 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6798 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6801 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6802 u32 spirom_ver, u32 ver_addr)
6804 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6805 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6808 REG_WR(bp, ver_addr, spirom_ver);
6811 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6812 struct bnx2x_phy *phy,
6815 u16 fw_ver1, fw_ver2;
6817 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6818 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6819 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6820 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6821 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6825 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6826 struct bnx2x_phy *phy,
6827 struct link_vars *vars)
6830 bnx2x_cl45_read(bp, phy,
6832 MDIO_AN_REG_STATUS, &val);
6833 bnx2x_cl45_read(bp, phy,
6835 MDIO_AN_REG_STATUS, &val);
6837 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6838 if ((val & (1<<0)) == 0)
6839 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6842 /******************************************************************/
6843 /* common BCM8073/BCM8727 PHY SECTION */
6844 /******************************************************************/
6845 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6846 struct link_params *params,
6847 struct link_vars *vars)
6849 struct bnx2x *bp = params->bp;
6850 if (phy->req_line_speed == SPEED_10 ||
6851 phy->req_line_speed == SPEED_100) {
6852 vars->flow_ctrl = phy->req_flow_ctrl;
6856 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6857 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6859 u16 ld_pause; /* local */
6860 u16 lp_pause; /* link partner */
6861 bnx2x_cl45_read(bp, phy,
6863 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6865 bnx2x_cl45_read(bp, phy,
6867 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6868 pause_result = (ld_pause &
6869 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6870 pause_result |= (lp_pause &
6871 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6873 bnx2x_pause_resolve(vars, pause_result);
6874 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6878 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6879 struct bnx2x_phy *phy,
6883 u16 fw_ver1, fw_msgout;
6886 /* Boot port from external ROM */
6888 bnx2x_cl45_write(bp, phy,
6890 MDIO_PMA_REG_GEN_CTRL,
6893 /* ucode reboot and rst */
6894 bnx2x_cl45_write(bp, phy,
6896 MDIO_PMA_REG_GEN_CTRL,
6899 bnx2x_cl45_write(bp, phy,
6901 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6903 /* Reset internal microprocessor */
6904 bnx2x_cl45_write(bp, phy,
6906 MDIO_PMA_REG_GEN_CTRL,
6907 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6909 /* Release srst bit */
6910 bnx2x_cl45_write(bp, phy,
6912 MDIO_PMA_REG_GEN_CTRL,
6913 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6915 /* Delay 100ms per the PHY specifications */
6918 /* 8073 sometimes taking longer to download */
6923 "bnx2x_8073_8727_external_rom_boot port %x:"
6924 "Download failed. fw version = 0x%x\n",
6930 bnx2x_cl45_read(bp, phy,
6932 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6933 bnx2x_cl45_read(bp, phy,
6935 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6938 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6939 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6940 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6942 /* Clear ser_boot_ctl bit */
6943 bnx2x_cl45_write(bp, phy,
6945 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6946 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6949 "bnx2x_8073_8727_external_rom_boot port %x:"
6950 "Download complete. fw version = 0x%x\n",
6956 /******************************************************************/
6957 /* BCM8073 PHY SECTION */
6958 /******************************************************************/
6959 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6961 /* This is only required for 8073A1, version 102 only */
6964 /* Read 8073 HW revision*/
6965 bnx2x_cl45_read(bp, phy,
6967 MDIO_PMA_REG_8073_CHIP_REV, &val);
6970 /* No need to workaround in 8073 A1 */
6974 bnx2x_cl45_read(bp, phy,
6976 MDIO_PMA_REG_ROM_VER2, &val);
6978 /* SNR should be applied only for version 0x102 */
6985 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6987 u16 val, cnt, cnt1 ;
6989 bnx2x_cl45_read(bp, phy,
6991 MDIO_PMA_REG_8073_CHIP_REV, &val);
6994 /* No need to workaround in 8073 A1 */
6997 /* XAUI workaround in 8073 A0: */
7000 * After loading the boot ROM and restarting Autoneg, poll
7004 for (cnt = 0; cnt < 1000; cnt++) {
7005 bnx2x_cl45_read(bp, phy,
7007 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7010 * If bit [14] = 0 or bit [13] = 0, continue on with
7011 * system initialization (XAUI work-around not required, as
7012 * these bits indicate 2.5G or 1G link up).
7014 if (!(val & (1<<14)) || !(val & (1<<13))) {
7015 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7017 } else if (!(val & (1<<15))) {
7018 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7020 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7021 * MSB (bit15) goes to 1 (indicating that the XAUI
7022 * workaround has completed), then continue on with
7023 * system initialization.
7025 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7026 bnx2x_cl45_read(bp, phy,
7028 MDIO_PMA_REG_8073_XAUI_WA, &val);
7029 if (val & (1<<15)) {
7031 "XAUI workaround has completed\n");
7040 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7044 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7046 /* Force KR or KX */
7047 bnx2x_cl45_write(bp, phy,
7048 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7049 bnx2x_cl45_write(bp, phy,
7050 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7051 bnx2x_cl45_write(bp, phy,
7052 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7053 bnx2x_cl45_write(bp, phy,
7054 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7057 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7058 struct bnx2x_phy *phy,
7059 struct link_vars *vars)
7062 struct bnx2x *bp = params->bp;
7063 bnx2x_cl45_read(bp, phy,
7064 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7066 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7067 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7068 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7069 if ((vars->ieee_fc &
7070 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7071 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7072 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7074 if ((vars->ieee_fc &
7075 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7076 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7077 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7079 if ((vars->ieee_fc &
7080 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7082 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7085 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7087 bnx2x_cl45_write(bp, phy,
7088 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7092 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7093 struct link_params *params,
7094 struct link_vars *vars)
7096 struct bnx2x *bp = params->bp;
7099 DP(NETIF_MSG_LINK, "Init 8073\n");
7102 gpio_port = BP_PATH(bp);
7104 gpio_port = params->port;
7105 /* Restore normal power mode*/
7106 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7107 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7109 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7110 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7113 bnx2x_cl45_write(bp, phy,
7114 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7115 bnx2x_cl45_write(bp, phy,
7116 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7118 bnx2x_8073_set_pause_cl37(params, phy, vars);
7120 bnx2x_cl45_read(bp, phy,
7121 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7123 bnx2x_cl45_read(bp, phy,
7124 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7126 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7128 /* Swap polarity if required - Must be done only in non-1G mode */
7129 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7130 /* Configure the 8073 to swap _P and _N of the KR lines */
7131 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7132 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7133 bnx2x_cl45_read(bp, phy,
7135 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7136 bnx2x_cl45_write(bp, phy,
7138 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7143 /* Enable CL37 BAM */
7144 if (REG_RD(bp, params->shmem_base +
7145 offsetof(struct shmem_region, dev_info.
7146 port_hw_config[params->port].default_cfg)) &
7147 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7149 bnx2x_cl45_read(bp, phy,
7151 MDIO_AN_REG_8073_BAM, &val);
7152 bnx2x_cl45_write(bp, phy,
7154 MDIO_AN_REG_8073_BAM, val | 1);
7155 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7157 if (params->loopback_mode == LOOPBACK_EXT) {
7158 bnx2x_807x_force_10G(bp, phy);
7159 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7162 bnx2x_cl45_write(bp, phy,
7163 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7165 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7166 if (phy->req_line_speed == SPEED_10000) {
7168 } else if (phy->req_line_speed == SPEED_2500) {
7171 * Note that 2.5G works only when used with 1G
7178 if (phy->speed_cap_mask &
7179 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7182 /* Note that 2.5G works only when used with 1G advertisement */
7183 if (phy->speed_cap_mask &
7184 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7185 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7187 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7190 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7191 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7193 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7194 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7195 (phy->req_line_speed == SPEED_2500)) {
7197 /* Allow 2.5G for A1 and above */
7198 bnx2x_cl45_read(bp, phy,
7199 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7201 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7207 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7211 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7212 /* Add support for CL37 (passive mode) II */
7214 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7215 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7216 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7219 /* Add support for CL37 (passive mode) III */
7220 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7223 * The SNR will improve about 2db by changing BW and FEE main
7224 * tap. Rest commands are executed after link is up
7225 * Change FFE main cursor to 5 in EDC register
7227 if (bnx2x_8073_is_snr_needed(bp, phy))
7228 bnx2x_cl45_write(bp, phy,
7229 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7232 /* Enable FEC (Forware Error Correction) Request in the AN */
7233 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7235 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7237 bnx2x_ext_phy_set_pause(params, phy, vars);
7239 /* Restart autoneg */
7241 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7242 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7243 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7247 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7248 struct link_params *params,
7249 struct link_vars *vars)
7251 struct bnx2x *bp = params->bp;
7254 u16 link_status = 0;
7255 u16 an1000_status = 0;
7257 bnx2x_cl45_read(bp, phy,
7258 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7260 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7262 /* clear the interrupt LASI status register */
7263 bnx2x_cl45_read(bp, phy,
7264 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7265 bnx2x_cl45_read(bp, phy,
7266 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7267 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7269 bnx2x_cl45_read(bp, phy,
7270 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7272 /* Check the LASI */
7273 bnx2x_cl45_read(bp, phy,
7274 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7276 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7278 /* Check the link status */
7279 bnx2x_cl45_read(bp, phy,
7280 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7281 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7283 bnx2x_cl45_read(bp, phy,
7284 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7285 bnx2x_cl45_read(bp, phy,
7286 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7287 link_up = ((val1 & 4) == 4);
7288 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7291 ((phy->req_line_speed != SPEED_10000))) {
7292 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7295 bnx2x_cl45_read(bp, phy,
7296 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7297 bnx2x_cl45_read(bp, phy,
7298 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7300 /* Check the link status on 1.1.2 */
7301 bnx2x_cl45_read(bp, phy,
7302 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7303 bnx2x_cl45_read(bp, phy,
7304 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7305 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7306 "an_link_status=0x%x\n", val2, val1, an1000_status);
7308 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7309 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7311 * The SNR will improve about 2dbby changing the BW and FEE main
7312 * tap. The 1st write to change FFE main tap is set before
7313 * restart AN. Change PLL Bandwidth in EDC register
7315 bnx2x_cl45_write(bp, phy,
7316 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7319 /* Change CDR Bandwidth in EDC register */
7320 bnx2x_cl45_write(bp, phy,
7321 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7324 bnx2x_cl45_read(bp, phy,
7325 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7328 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7329 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7331 vars->line_speed = SPEED_10000;
7332 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7334 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7336 vars->line_speed = SPEED_2500;
7337 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7339 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7341 vars->line_speed = SPEED_1000;
7342 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7346 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7351 /* Swap polarity if required */
7352 if (params->lane_config &
7353 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7354 /* Configure the 8073 to swap P and N of the KR lines */
7355 bnx2x_cl45_read(bp, phy,
7357 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7359 * Set bit 3 to invert Rx in 1G mode and clear this bit
7360 * when it`s in 10G mode.
7362 if (vars->line_speed == SPEED_1000) {
7363 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7369 bnx2x_cl45_write(bp, phy,
7371 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7374 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7375 bnx2x_8073_resolve_fc(phy, params, vars);
7376 vars->duplex = DUPLEX_FULL;
7381 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7382 struct link_params *params)
7384 struct bnx2x *bp = params->bp;
7387 gpio_port = BP_PATH(bp);
7389 gpio_port = params->port;
7390 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7392 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7393 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7397 /******************************************************************/
7398 /* BCM8705 PHY SECTION */
7399 /******************************************************************/
7400 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7401 struct link_params *params,
7402 struct link_vars *vars)
7404 struct bnx2x *bp = params->bp;
7405 DP(NETIF_MSG_LINK, "init 8705\n");
7406 /* Restore normal power mode*/
7407 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7408 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7410 bnx2x_ext_phy_hw_reset(bp, params->port);
7411 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7412 bnx2x_wait_reset_complete(bp, phy, params);
7414 bnx2x_cl45_write(bp, phy,
7415 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7416 bnx2x_cl45_write(bp, phy,
7417 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7418 bnx2x_cl45_write(bp, phy,
7419 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7420 bnx2x_cl45_write(bp, phy,
7421 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7422 /* BCM8705 doesn't have microcode, hence the 0 */
7423 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7427 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7428 struct link_params *params,
7429 struct link_vars *vars)
7433 struct bnx2x *bp = params->bp;
7434 DP(NETIF_MSG_LINK, "read status 8705\n");
7435 bnx2x_cl45_read(bp, phy,
7436 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7437 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7439 bnx2x_cl45_read(bp, phy,
7440 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7441 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7443 bnx2x_cl45_read(bp, phy,
7444 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7446 bnx2x_cl45_read(bp, phy,
7447 MDIO_PMA_DEVAD, 0xc809, &val1);
7448 bnx2x_cl45_read(bp, phy,
7449 MDIO_PMA_DEVAD, 0xc809, &val1);
7451 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7452 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7454 vars->line_speed = SPEED_10000;
7455 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7460 /******************************************************************/
7461 /* SFP+ module Section */
7462 /******************************************************************/
7463 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7464 struct bnx2x_phy *phy,
7467 struct bnx2x *bp = params->bp;
7469 * Disable transmitter only for bootcodes which can enable it afterwards
7473 if (params->feature_config_flags &
7474 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7475 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7477 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7481 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7482 bnx2x_cl45_write(bp, phy,
7484 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7487 static u8 bnx2x_get_gpio_port(struct link_params *params)
7490 u32 swap_val, swap_override;
7491 struct bnx2x *bp = params->bp;
7493 gpio_port = BP_PATH(bp);
7495 gpio_port = params->port;
7496 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7497 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7498 return gpio_port ^ (swap_val && swap_override);
7501 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7502 struct bnx2x_phy *phy,
7506 u8 port = params->port;
7507 struct bnx2x *bp = params->bp;
7510 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7511 tx_en_mode = REG_RD(bp, params->shmem_base +
7512 offsetof(struct shmem_region,
7513 dev_info.port_hw_config[port].sfp_ctrl)) &
7514 PORT_HW_CFG_TX_LASER_MASK;
7515 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7516 "mode = %x\n", tx_en, port, tx_en_mode);
7517 switch (tx_en_mode) {
7518 case PORT_HW_CFG_TX_LASER_MDIO:
7520 bnx2x_cl45_read(bp, phy,
7522 MDIO_PMA_REG_PHY_IDENTIFIER,
7530 bnx2x_cl45_write(bp, phy,
7532 MDIO_PMA_REG_PHY_IDENTIFIER,
7535 case PORT_HW_CFG_TX_LASER_GPIO0:
7536 case PORT_HW_CFG_TX_LASER_GPIO1:
7537 case PORT_HW_CFG_TX_LASER_GPIO2:
7538 case PORT_HW_CFG_TX_LASER_GPIO3:
7541 u8 gpio_port, gpio_mode;
7543 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7545 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7547 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7548 gpio_port = bnx2x_get_gpio_port(params);
7549 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7553 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7558 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7559 struct bnx2x_phy *phy,
7562 struct bnx2x *bp = params->bp;
7563 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7565 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7567 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7570 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7571 struct link_params *params,
7572 u16 addr, u8 byte_cnt, u8 *o_buf)
7574 struct bnx2x *bp = params->bp;
7577 if (byte_cnt > 16) {
7579 "Reading from eeprom is limited to 0xf\n");
7582 /* Set the read command byte count */
7583 bnx2x_cl45_write(bp, phy,
7584 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7585 (byte_cnt | 0xa000));
7587 /* Set the read command address */
7588 bnx2x_cl45_write(bp, phy,
7589 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7592 /* Activate read command */
7593 bnx2x_cl45_write(bp, phy,
7594 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7597 /* Wait up to 500us for command complete status */
7598 for (i = 0; i < 100; i++) {
7599 bnx2x_cl45_read(bp, phy,
7601 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7602 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7603 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7608 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7609 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7611 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7612 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7616 /* Read the buffer */
7617 for (i = 0; i < byte_cnt; i++) {
7618 bnx2x_cl45_read(bp, phy,
7620 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7621 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7624 for (i = 0; i < 100; i++) {
7625 bnx2x_cl45_read(bp, phy,
7627 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7628 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7629 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7636 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7637 struct link_params *params,
7638 u16 addr, u8 byte_cnt,
7642 u8 i, j = 0, cnt = 0;
7645 struct bnx2x *bp = params->bp;
7646 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7647 " addr %d, cnt %d\n",
7649 if (byte_cnt > 16) {
7651 "Reading from eeprom is limited to 16 bytes\n");
7655 /* 4 byte aligned address */
7656 addr32 = addr & (~0x3);
7658 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7660 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7663 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7664 o_buf[j] = *((u8 *)data_array + i);
7672 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7673 struct link_params *params,
7674 u16 addr, u8 byte_cnt, u8 *o_buf)
7676 struct bnx2x *bp = params->bp;
7679 if (byte_cnt > 16) {
7681 "Reading from eeprom is limited to 0xf\n");
7685 /* Need to read from 1.8000 to clear it */
7686 bnx2x_cl45_read(bp, phy,
7688 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7691 /* Set the read command byte count */
7692 bnx2x_cl45_write(bp, phy,
7694 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7695 ((byte_cnt < 2) ? 2 : byte_cnt));
7697 /* Set the read command address */
7698 bnx2x_cl45_write(bp, phy,
7700 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7702 /* Set the destination address */
7703 bnx2x_cl45_write(bp, phy,
7706 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7708 /* Activate read command */
7709 bnx2x_cl45_write(bp, phy,
7711 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7714 * Wait appropriate time for two-wire command to finish before
7715 * polling the status register
7719 /* Wait up to 500us for command complete status */
7720 for (i = 0; i < 100; i++) {
7721 bnx2x_cl45_read(bp, phy,
7723 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7724 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7725 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7730 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7731 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7733 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7734 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7738 /* Read the buffer */
7739 for (i = 0; i < byte_cnt; i++) {
7740 bnx2x_cl45_read(bp, phy,
7742 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7743 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7746 for (i = 0; i < 100; i++) {
7747 bnx2x_cl45_read(bp, phy,
7749 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7750 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7751 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7759 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7760 struct link_params *params, u16 addr,
7761 u8 byte_cnt, u8 *o_buf)
7764 switch (phy->type) {
7765 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7766 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7769 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7770 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7771 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7774 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7775 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7782 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7783 struct link_params *params,
7786 struct bnx2x *bp = params->bp;
7787 u32 sync_offset = 0, phy_idx, media_types;
7788 u8 val, check_limiting_mode = 0;
7789 *edc_mode = EDC_MODE_LIMITING;
7791 phy->media_type = ETH_PHY_UNSPECIFIED;
7792 /* First check for copper cable */
7793 if (bnx2x_read_sfp_module_eeprom(phy,
7795 SFP_EEPROM_CON_TYPE_ADDR,
7798 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7803 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7805 u8 copper_module_type;
7806 phy->media_type = ETH_PHY_DA_TWINAX;
7808 * Check if its active cable (includes SFP+ module)
7811 if (bnx2x_read_sfp_module_eeprom(phy,
7813 SFP_EEPROM_FC_TX_TECH_ADDR,
7815 &copper_module_type) != 0) {
7817 "Failed to read copper-cable-type"
7818 " from SFP+ EEPROM\n");
7822 if (copper_module_type &
7823 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7824 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7825 check_limiting_mode = 1;
7826 } else if (copper_module_type &
7827 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7829 "Passive Copper cable detected\n");
7831 EDC_MODE_PASSIVE_DAC;
7834 "Unknown copper-cable-type 0x%x !!!\n",
7835 copper_module_type);
7840 case SFP_EEPROM_CON_TYPE_VAL_LC:
7841 phy->media_type = ETH_PHY_SFP_FIBER;
7842 DP(NETIF_MSG_LINK, "Optic module detected\n");
7843 check_limiting_mode = 1;
7846 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7850 sync_offset = params->shmem_base +
7851 offsetof(struct shmem_region,
7852 dev_info.port_hw_config[params->port].media_type);
7853 media_types = REG_RD(bp, sync_offset);
7854 /* Update media type for non-PMF sync */
7855 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7856 if (&(params->phy[phy_idx]) == phy) {
7857 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7858 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7859 media_types |= ((phy->media_type &
7860 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7861 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7865 REG_WR(bp, sync_offset, media_types);
7866 if (check_limiting_mode) {
7867 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7868 if (bnx2x_read_sfp_module_eeprom(phy,
7870 SFP_EEPROM_OPTIONS_ADDR,
7871 SFP_EEPROM_OPTIONS_SIZE,
7874 "Failed to read Option field from module EEPROM\n");
7877 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7878 *edc_mode = EDC_MODE_LINEAR;
7880 *edc_mode = EDC_MODE_LIMITING;
7882 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7886 * This function read the relevant field from the module (SFP+), and verify it
7887 * is compliant with this board
7889 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7890 struct link_params *params)
7892 struct bnx2x *bp = params->bp;
7894 u32 fw_resp, fw_cmd_param;
7895 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7896 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7897 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7898 val = REG_RD(bp, params->shmem_base +
7899 offsetof(struct shmem_region, dev_info.
7900 port_feature_config[params->port].config));
7901 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7902 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7903 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7907 if (params->feature_config_flags &
7908 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7909 /* Use specific phy request */
7910 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7911 } else if (params->feature_config_flags &
7912 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7913 /* Use first phy request only in case of non-dual media*/
7914 if (DUAL_MEDIA(params)) {
7916 "FW does not support OPT MDL verification\n");
7919 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7921 /* No support in OPT MDL detection */
7923 "FW does not support OPT MDL verification\n");
7927 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7928 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7929 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7930 DP(NETIF_MSG_LINK, "Approved module\n");
7934 /* format the warning message */
7935 if (bnx2x_read_sfp_module_eeprom(phy,
7937 SFP_EEPROM_VENDOR_NAME_ADDR,
7938 SFP_EEPROM_VENDOR_NAME_SIZE,
7940 vendor_name[0] = '\0';
7942 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7943 if (bnx2x_read_sfp_module_eeprom(phy,
7945 SFP_EEPROM_PART_NO_ADDR,
7946 SFP_EEPROM_PART_NO_SIZE,
7948 vendor_pn[0] = '\0';
7950 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7952 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7953 " Port %d from %s part number %s\n",
7954 params->port, vendor_name, vendor_pn);
7955 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7959 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7960 struct link_params *params)
7964 struct bnx2x *bp = params->bp;
7967 * Initialization time after hot-plug may take up to 300ms for
7968 * some phys type ( e.g. JDSU )
7971 for (timeout = 0; timeout < 60; timeout++) {
7972 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7975 "SFP+ module initialization took %d ms\n",
7984 static void bnx2x_8727_power_module(struct bnx2x *bp,
7985 struct bnx2x_phy *phy,
7987 /* Make sure GPIOs are not using for LED mode */
7990 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7991 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7993 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7994 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7995 * where the 1st bit is the over-current(only input), and 2nd bit is
7996 * for power( only output )
7998 * In case of NOC feature is disabled and power is up, set GPIO control
7999 * as input to enable listening of over-current indication
8001 if (phy->flags & FLAGS_NOC)
8007 * Set GPIO control to OUTPUT, and set the power bit
8008 * to according to the is_power_up
8012 bnx2x_cl45_write(bp, phy,
8014 MDIO_PMA_REG_8727_GPIO_CTRL,
8018 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8019 struct bnx2x_phy *phy,
8022 u16 cur_limiting_mode;
8024 bnx2x_cl45_read(bp, phy,
8026 MDIO_PMA_REG_ROM_VER2,
8027 &cur_limiting_mode);
8028 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8031 if (edc_mode == EDC_MODE_LIMITING) {
8032 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8033 bnx2x_cl45_write(bp, phy,
8035 MDIO_PMA_REG_ROM_VER2,
8037 } else { /* LRM mode ( default )*/
8039 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8042 * Changing to LRM mode takes quite few seconds. So do it only
8043 * if current mode is limiting (default is LRM)
8045 if (cur_limiting_mode != EDC_MODE_LIMITING)
8048 bnx2x_cl45_write(bp, phy,
8050 MDIO_PMA_REG_LRM_MODE,
8052 bnx2x_cl45_write(bp, phy,
8054 MDIO_PMA_REG_ROM_VER2,
8056 bnx2x_cl45_write(bp, phy,
8058 MDIO_PMA_REG_MISC_CTRL0,
8060 bnx2x_cl45_write(bp, phy,
8062 MDIO_PMA_REG_LRM_MODE,
8068 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8069 struct bnx2x_phy *phy,
8074 bnx2x_cl45_read(bp, phy,
8076 MDIO_PMA_REG_PHY_IDENTIFIER,
8079 bnx2x_cl45_write(bp, phy,
8081 MDIO_PMA_REG_PHY_IDENTIFIER,
8082 (phy_identifier & ~(1<<9)));
8084 bnx2x_cl45_read(bp, phy,
8086 MDIO_PMA_REG_ROM_VER2,
8088 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8089 bnx2x_cl45_write(bp, phy,
8091 MDIO_PMA_REG_ROM_VER2,
8092 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8094 bnx2x_cl45_write(bp, phy,
8096 MDIO_PMA_REG_PHY_IDENTIFIER,
8097 (phy_identifier | (1<<9)));
8102 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8103 struct link_params *params,
8106 struct bnx2x *bp = params->bp;
8110 bnx2x_sfp_set_transmitter(params, phy, 0);
8113 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8114 bnx2x_sfp_set_transmitter(params, phy, 1);
8117 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8123 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8126 struct bnx2x *bp = params->bp;
8128 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8129 offsetof(struct shmem_region,
8130 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8131 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8132 switch (fault_led_gpio) {
8133 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8135 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8136 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8137 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8138 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8140 u8 gpio_port = bnx2x_get_gpio_port(params);
8141 u16 gpio_pin = fault_led_gpio -
8142 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8143 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8144 "pin %x port %x mode %x\n",
8145 gpio_pin, gpio_port, gpio_mode);
8146 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8150 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8155 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8159 u8 port = params->port;
8160 struct bnx2x *bp = params->bp;
8161 pin_cfg = (REG_RD(bp, params->shmem_base +
8162 offsetof(struct shmem_region,
8163 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8164 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8165 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8166 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8167 gpio_mode, pin_cfg);
8168 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8171 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8174 struct bnx2x *bp = params->bp;
8175 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8176 if (CHIP_IS_E3(bp)) {
8178 * Low ==> if SFP+ module is supported otherwise
8179 * High ==> if SFP+ module is not on the approved vendor list
8181 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8183 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8186 static void bnx2x_warpcore_power_module(struct link_params *params,
8187 struct bnx2x_phy *phy,
8191 struct bnx2x *bp = params->bp;
8193 pin_cfg = (REG_RD(bp, params->shmem_base +
8194 offsetof(struct shmem_region,
8195 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8196 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8197 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8199 if (pin_cfg == PIN_CFG_NA)
8201 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8204 * Low ==> corresponding SFP+ module is powered
8205 * high ==> the SFP+ module is powered down
8207 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8210 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8211 struct link_params *params)
8213 struct bnx2x *bp = params->bp;
8214 bnx2x_warpcore_power_module(params, phy, 0);
8215 /* Put Warpcore in low power mode */
8216 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8218 /* Put LCPLL in low power mode */
8219 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8220 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8221 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8224 static void bnx2x_power_sfp_module(struct link_params *params,
8225 struct bnx2x_phy *phy,
8228 struct bnx2x *bp = params->bp;
8229 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8231 switch (phy->type) {
8232 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8233 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8234 bnx2x_8727_power_module(params->bp, phy, power);
8236 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8237 bnx2x_warpcore_power_module(params, phy, power);
8243 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8244 struct bnx2x_phy *phy,
8248 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8249 struct bnx2x *bp = params->bp;
8251 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8252 /* This is a global register which controls all lanes */
8253 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8254 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8255 val &= ~(0xf << (lane << 2));
8258 case EDC_MODE_LINEAR:
8259 case EDC_MODE_LIMITING:
8260 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8262 case EDC_MODE_PASSIVE_DAC:
8263 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8269 val |= (mode << (lane << 2));
8270 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8271 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8273 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8274 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8276 /* Restart microcode to re-read the new mode */
8277 bnx2x_warpcore_reset_lane(bp, phy, 1);
8278 bnx2x_warpcore_reset_lane(bp, phy, 0);
8282 static void bnx2x_set_limiting_mode(struct link_params *params,
8283 struct bnx2x_phy *phy,
8286 switch (phy->type) {
8287 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8288 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8290 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8291 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8292 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8294 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8295 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8300 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8301 struct link_params *params)
8303 struct bnx2x *bp = params->bp;
8307 u32 val = REG_RD(bp, params->shmem_base +
8308 offsetof(struct shmem_region, dev_info.
8309 port_feature_config[params->port].config));
8311 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8313 /* Power up module */
8314 bnx2x_power_sfp_module(params, phy, 1);
8315 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8316 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8318 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8319 /* check SFP+ module compatibility */
8320 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8322 /* Turn on fault module-detected led */
8323 bnx2x_set_sfp_module_fault_led(params,
8324 MISC_REGISTERS_GPIO_HIGH);
8326 /* Check if need to power down the SFP+ module */
8327 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8328 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8329 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8330 bnx2x_power_sfp_module(params, phy, 0);
8334 /* Turn off fault module-detected led */
8335 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8339 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8340 * is done automatically
8342 bnx2x_set_limiting_mode(params, phy, edc_mode);
8345 * Enable transmit for this module if the module is approved, or
8346 * if unapproved modules should also enable the Tx laser
8349 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8350 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8351 bnx2x_sfp_set_transmitter(params, phy, 1);
8353 bnx2x_sfp_set_transmitter(params, phy, 0);
8358 void bnx2x_handle_module_detect_int(struct link_params *params)
8360 struct bnx2x *bp = params->bp;
8361 struct bnx2x_phy *phy;
8363 u8 gpio_num, gpio_port;
8365 phy = ¶ms->phy[INT_PHY];
8367 phy = ¶ms->phy[EXT_PHY1];
8369 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8370 params->port, &gpio_num, &gpio_port) ==
8372 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8376 /* Set valid module led off */
8377 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8379 /* Get current gpio val reflecting module plugged in / out*/
8380 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8382 /* Call the handling function in case module is detected */
8383 if (gpio_val == 0) {
8384 bnx2x_power_sfp_module(params, phy, 1);
8385 bnx2x_set_gpio_int(bp, gpio_num,
8386 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8388 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8389 bnx2x_sfp_module_detection(phy, params);
8391 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8393 u32 val = REG_RD(bp, params->shmem_base +
8394 offsetof(struct shmem_region, dev_info.
8395 port_feature_config[params->port].
8397 bnx2x_set_gpio_int(bp, gpio_num,
8398 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8401 * Module was plugged out.
8402 * Disable transmit for this module
8404 phy->media_type = ETH_PHY_NOT_PRESENT;
8405 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8406 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8408 bnx2x_sfp_set_transmitter(params, phy, 0);
8412 /******************************************************************/
8413 /* Used by 8706 and 8727 */
8414 /******************************************************************/
8415 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8416 struct bnx2x_phy *phy,
8417 u16 alarm_status_offset,
8418 u16 alarm_ctrl_offset)
8420 u16 alarm_status, val;
8421 bnx2x_cl45_read(bp, phy,
8422 MDIO_PMA_DEVAD, alarm_status_offset,
8424 bnx2x_cl45_read(bp, phy,
8425 MDIO_PMA_DEVAD, alarm_status_offset,
8427 /* Mask or enable the fault event. */
8428 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8429 if (alarm_status & (1<<0))
8433 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8435 /******************************************************************/
8436 /* common BCM8706/BCM8726 PHY SECTION */
8437 /******************************************************************/
8438 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8439 struct link_params *params,
8440 struct link_vars *vars)
8443 u16 val1, val2, rx_sd, pcs_status;
8444 struct bnx2x *bp = params->bp;
8445 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8447 bnx2x_cl45_read(bp, phy,
8448 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8450 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8451 MDIO_PMA_LASI_TXCTRL);
8453 /* clear LASI indication*/
8454 bnx2x_cl45_read(bp, phy,
8455 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8456 bnx2x_cl45_read(bp, phy,
8457 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8458 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8460 bnx2x_cl45_read(bp, phy,
8461 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8462 bnx2x_cl45_read(bp, phy,
8463 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8464 bnx2x_cl45_read(bp, phy,
8465 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8466 bnx2x_cl45_read(bp, phy,
8467 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8469 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8470 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8472 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8473 * are set, or if the autoneg bit 1 is set
8475 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8478 vars->line_speed = SPEED_1000;
8480 vars->line_speed = SPEED_10000;
8481 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8482 vars->duplex = DUPLEX_FULL;
8485 /* Capture 10G link fault. Read twice to clear stale value. */
8486 if (vars->line_speed == SPEED_10000) {
8487 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8488 MDIO_PMA_LASI_TXSTAT, &val1);
8489 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8490 MDIO_PMA_LASI_TXSTAT, &val1);
8492 vars->fault_detected = 1;
8498 /******************************************************************/
8499 /* BCM8706 PHY SECTION */
8500 /******************************************************************/
8501 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8502 struct link_params *params,
8503 struct link_vars *vars)
8507 struct bnx2x *bp = params->bp;
8509 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8510 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8512 bnx2x_ext_phy_hw_reset(bp, params->port);
8513 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8514 bnx2x_wait_reset_complete(bp, phy, params);
8516 /* Wait until fw is loaded */
8517 for (cnt = 0; cnt < 100; cnt++) {
8518 bnx2x_cl45_read(bp, phy,
8519 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8524 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8525 if ((params->feature_config_flags &
8526 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8529 for (i = 0; i < 4; i++) {
8530 reg = MDIO_XS_8706_REG_BANK_RX0 +
8531 i*(MDIO_XS_8706_REG_BANK_RX1 -
8532 MDIO_XS_8706_REG_BANK_RX0);
8533 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8534 /* Clear first 3 bits of the control */
8536 /* Set control bits according to configuration */
8537 val |= (phy->rx_preemphasis[i] & 0x7);
8538 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8539 " reg 0x%x <-- val 0x%x\n", reg, val);
8540 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8544 if (phy->req_line_speed == SPEED_10000) {
8545 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8547 bnx2x_cl45_write(bp, phy,
8549 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8550 bnx2x_cl45_write(bp, phy,
8551 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8553 /* Arm LASI for link and Tx fault. */
8554 bnx2x_cl45_write(bp, phy,
8555 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8557 /* Force 1Gbps using autoneg with 1G advertisement */
8559 /* Allow CL37 through CL73 */
8560 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8561 bnx2x_cl45_write(bp, phy,
8562 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8564 /* Enable Full-Duplex advertisement on CL37 */
8565 bnx2x_cl45_write(bp, phy,
8566 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8567 /* Enable CL37 AN */
8568 bnx2x_cl45_write(bp, phy,
8569 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8571 bnx2x_cl45_write(bp, phy,
8572 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8574 /* Enable clause 73 AN */
8575 bnx2x_cl45_write(bp, phy,
8576 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8577 bnx2x_cl45_write(bp, phy,
8578 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8580 bnx2x_cl45_write(bp, phy,
8581 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8584 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8587 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8588 * power mode, if TX Laser is disabled
8591 tx_en_mode = REG_RD(bp, params->shmem_base +
8592 offsetof(struct shmem_region,
8593 dev_info.port_hw_config[params->port].sfp_ctrl))
8594 & PORT_HW_CFG_TX_LASER_MASK;
8596 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8597 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8598 bnx2x_cl45_read(bp, phy,
8599 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8601 bnx2x_cl45_write(bp, phy,
8602 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8608 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8609 struct link_params *params,
8610 struct link_vars *vars)
8612 return bnx2x_8706_8726_read_status(phy, params, vars);
8615 /******************************************************************/
8616 /* BCM8726 PHY SECTION */
8617 /******************************************************************/
8618 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8619 struct link_params *params)
8621 struct bnx2x *bp = params->bp;
8622 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8623 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8626 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8627 struct link_params *params)
8629 struct bnx2x *bp = params->bp;
8630 /* Need to wait 100ms after reset */
8633 /* Micro controller re-boot */
8634 bnx2x_cl45_write(bp, phy,
8635 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8637 /* Set soft reset */
8638 bnx2x_cl45_write(bp, phy,
8640 MDIO_PMA_REG_GEN_CTRL,
8641 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8643 bnx2x_cl45_write(bp, phy,
8645 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8647 bnx2x_cl45_write(bp, phy,
8649 MDIO_PMA_REG_GEN_CTRL,
8650 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8652 /* wait for 150ms for microcode load */
8655 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8656 bnx2x_cl45_write(bp, phy,
8658 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8661 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8664 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8665 struct link_params *params,
8666 struct link_vars *vars)
8668 struct bnx2x *bp = params->bp;
8670 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8672 bnx2x_cl45_read(bp, phy,
8673 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8675 if (val1 & (1<<15)) {
8676 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8678 vars->line_speed = 0;
8685 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8686 struct link_params *params,
8687 struct link_vars *vars)
8689 struct bnx2x *bp = params->bp;
8690 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8692 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8693 bnx2x_wait_reset_complete(bp, phy, params);
8695 bnx2x_8726_external_rom_boot(phy, params);
8698 * Need to call module detected on initialization since the module
8699 * detection triggered by actual module insertion might occur before
8700 * driver is loaded, and when driver is loaded, it reset all
8701 * registers, including the transmitter
8703 bnx2x_sfp_module_detection(phy, params);
8705 if (phy->req_line_speed == SPEED_1000) {
8706 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8707 bnx2x_cl45_write(bp, phy,
8708 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8709 bnx2x_cl45_write(bp, phy,
8710 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8711 bnx2x_cl45_write(bp, phy,
8712 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8713 bnx2x_cl45_write(bp, phy,
8714 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8716 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8717 (phy->speed_cap_mask &
8718 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8719 ((phy->speed_cap_mask &
8720 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8721 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8722 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8723 /* Set Flow control */
8724 bnx2x_ext_phy_set_pause(params, phy, vars);
8725 bnx2x_cl45_write(bp, phy,
8726 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8727 bnx2x_cl45_write(bp, phy,
8728 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8729 bnx2x_cl45_write(bp, phy,
8730 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8731 bnx2x_cl45_write(bp, phy,
8732 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8733 bnx2x_cl45_write(bp, phy,
8734 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8736 * Enable RX-ALARM control to receive interrupt for 1G speed
8739 bnx2x_cl45_write(bp, phy,
8740 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8741 bnx2x_cl45_write(bp, phy,
8742 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8745 } else { /* Default 10G. Set only LASI control */
8746 bnx2x_cl45_write(bp, phy,
8747 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8750 /* Set TX PreEmphasis if needed */
8751 if ((params->feature_config_flags &
8752 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8754 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8755 phy->tx_preemphasis[0],
8756 phy->tx_preemphasis[1]);
8757 bnx2x_cl45_write(bp, phy,
8759 MDIO_PMA_REG_8726_TX_CTRL1,
8760 phy->tx_preemphasis[0]);
8762 bnx2x_cl45_write(bp, phy,
8764 MDIO_PMA_REG_8726_TX_CTRL2,
8765 phy->tx_preemphasis[1]);
8772 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8773 struct link_params *params)
8775 struct bnx2x *bp = params->bp;
8776 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8777 /* Set serial boot control for external load */
8778 bnx2x_cl45_write(bp, phy,
8780 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8783 /******************************************************************/
8784 /* BCM8727 PHY SECTION */
8785 /******************************************************************/
8787 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8788 struct link_params *params, u8 mode)
8790 struct bnx2x *bp = params->bp;
8791 u16 led_mode_bitmask = 0;
8792 u16 gpio_pins_bitmask = 0;
8794 /* Only NOC flavor requires to set the LED specifically */
8795 if (!(phy->flags & FLAGS_NOC))
8798 case LED_MODE_FRONT_PANEL_OFF:
8800 led_mode_bitmask = 0;
8801 gpio_pins_bitmask = 0x03;
8804 led_mode_bitmask = 0;
8805 gpio_pins_bitmask = 0x02;
8808 led_mode_bitmask = 0x60;
8809 gpio_pins_bitmask = 0x11;
8812 bnx2x_cl45_read(bp, phy,
8814 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8817 val |= led_mode_bitmask;
8818 bnx2x_cl45_write(bp, phy,
8820 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8822 bnx2x_cl45_read(bp, phy,
8824 MDIO_PMA_REG_8727_GPIO_CTRL,
8827 val |= gpio_pins_bitmask;
8828 bnx2x_cl45_write(bp, phy,
8830 MDIO_PMA_REG_8727_GPIO_CTRL,
8833 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8834 struct link_params *params) {
8835 u32 swap_val, swap_override;
8838 * The PHY reset is controlled by GPIO 1. Fake the port number
8839 * to cancel the swap done in set_gpio()
8841 struct bnx2x *bp = params->bp;
8842 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8843 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8844 port = (swap_val && swap_override) ^ 1;
8845 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8846 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8849 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8850 struct link_params *params,
8851 struct link_vars *vars)
8854 u16 tmp1, val, mod_abs, tmp2;
8855 u16 rx_alarm_ctrl_val;
8857 struct bnx2x *bp = params->bp;
8858 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8860 bnx2x_wait_reset_complete(bp, phy, params);
8861 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8862 /* Should be 0x6 to enable XS on Tx side. */
8863 lasi_ctrl_val = 0x0006;
8865 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8867 bnx2x_cl45_write(bp, phy,
8868 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8870 bnx2x_cl45_write(bp, phy,
8871 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8873 bnx2x_cl45_write(bp, phy,
8874 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8877 * Initially configure MOD_ABS to interrupt when module is
8880 bnx2x_cl45_read(bp, phy,
8881 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8883 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8884 * When the EDC is off it locks onto a reference clock and avoids
8888 if (!(phy->flags & FLAGS_NOC))
8890 bnx2x_cl45_write(bp, phy,
8891 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8894 /* Enable/Disable PHY transmitter output */
8895 bnx2x_set_disable_pmd_transmit(params, phy, 0);
8897 /* Make MOD_ABS give interrupt on change */
8898 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8901 if (phy->flags & FLAGS_NOC)
8905 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8906 * status which reflect SFP+ module over-current
8908 if (!(phy->flags & FLAGS_NOC))
8909 val &= 0xff8f; /* Reset bits 4-6 */
8910 bnx2x_cl45_write(bp, phy,
8911 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8913 bnx2x_8727_power_module(bp, phy, 1);
8915 bnx2x_cl45_read(bp, phy,
8916 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8918 bnx2x_cl45_read(bp, phy,
8919 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8921 /* Set option 1G speed */
8922 if (phy->req_line_speed == SPEED_1000) {
8923 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8924 bnx2x_cl45_write(bp, phy,
8925 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8926 bnx2x_cl45_write(bp, phy,
8927 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8928 bnx2x_cl45_read(bp, phy,
8929 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8930 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8932 * Power down the XAUI until link is up in case of dual-media
8935 if (DUAL_MEDIA(params)) {
8936 bnx2x_cl45_read(bp, phy,
8938 MDIO_PMA_REG_8727_PCS_GP, &val);
8940 bnx2x_cl45_write(bp, phy,
8942 MDIO_PMA_REG_8727_PCS_GP, val);
8944 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8945 ((phy->speed_cap_mask &
8946 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8947 ((phy->speed_cap_mask &
8948 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8949 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8951 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8952 bnx2x_cl45_write(bp, phy,
8953 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8954 bnx2x_cl45_write(bp, phy,
8955 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8958 * Since the 8727 has only single reset pin, need to set the 10G
8959 * registers although it is default
8961 bnx2x_cl45_write(bp, phy,
8962 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8964 bnx2x_cl45_write(bp, phy,
8965 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8966 bnx2x_cl45_write(bp, phy,
8967 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8968 bnx2x_cl45_write(bp, phy,
8969 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8974 * Set 2-wire transfer rate of SFP+ module EEPROM
8975 * to 100Khz since some DACs(direct attached cables) do
8976 * not work at 400Khz.
8978 bnx2x_cl45_write(bp, phy,
8979 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8982 /* Set TX PreEmphasis if needed */
8983 if ((params->feature_config_flags &
8984 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8985 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8986 phy->tx_preemphasis[0],
8987 phy->tx_preemphasis[1]);
8988 bnx2x_cl45_write(bp, phy,
8989 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8990 phy->tx_preemphasis[0]);
8992 bnx2x_cl45_write(bp, phy,
8993 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8994 phy->tx_preemphasis[1]);
8998 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8999 * power mode, if TX Laser is disabled
9001 tx_en_mode = REG_RD(bp, params->shmem_base +
9002 offsetof(struct shmem_region,
9003 dev_info.port_hw_config[params->port].sfp_ctrl))
9004 & PORT_HW_CFG_TX_LASER_MASK;
9006 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9008 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9009 bnx2x_cl45_read(bp, phy,
9010 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9013 bnx2x_cl45_write(bp, phy,
9014 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9020 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9021 struct link_params *params)
9023 struct bnx2x *bp = params->bp;
9024 u16 mod_abs, rx_alarm_status;
9025 u32 val = REG_RD(bp, params->shmem_base +
9026 offsetof(struct shmem_region, dev_info.
9027 port_feature_config[params->port].
9029 bnx2x_cl45_read(bp, phy,
9031 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9032 if (mod_abs & (1<<8)) {
9034 /* Module is absent */
9036 "MOD_ABS indication show module is absent\n");
9037 phy->media_type = ETH_PHY_NOT_PRESENT;
9039 * 1. Set mod_abs to detect next module
9041 * 2. Set EDC off by setting OPTXLOS signal input to low
9043 * When the EDC is off it locks onto a reference clock and
9044 * avoids becoming 'lost'.
9047 if (!(phy->flags & FLAGS_NOC))
9049 bnx2x_cl45_write(bp, phy,
9051 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9054 * Clear RX alarm since it stays up as long as
9055 * the mod_abs wasn't changed
9057 bnx2x_cl45_read(bp, phy,
9059 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9062 /* Module is present */
9064 "MOD_ABS indication show module is present\n");
9066 * First disable transmitter, and if the module is ok, the
9067 * module_detection will enable it
9068 * 1. Set mod_abs to detect next module absent event ( bit 8)
9069 * 2. Restore the default polarity of the OPRXLOS signal and
9070 * this signal will then correctly indicate the presence or
9071 * absence of the Rx signal. (bit 9)
9074 if (!(phy->flags & FLAGS_NOC))
9076 bnx2x_cl45_write(bp, phy,
9078 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9081 * Clear RX alarm since it stays up as long as the mod_abs
9082 * wasn't changed. This is need to be done before calling the
9083 * module detection, otherwise it will clear* the link update
9086 bnx2x_cl45_read(bp, phy,
9088 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9091 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9092 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9093 bnx2x_sfp_set_transmitter(params, phy, 0);
9095 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9096 bnx2x_sfp_module_detection(phy, params);
9098 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9101 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9103 /* No need to check link status in case of module plugged in/out */
9106 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9107 struct link_params *params,
9108 struct link_vars *vars)
9111 struct bnx2x *bp = params->bp;
9112 u8 link_up = 0, oc_port = params->port;
9113 u16 link_status = 0;
9114 u16 rx_alarm_status, lasi_ctrl, val1;
9116 /* If PHY is not initialized, do not check link status */
9117 bnx2x_cl45_read(bp, phy,
9118 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9123 /* Check the LASI on Rx */
9124 bnx2x_cl45_read(bp, phy,
9125 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9127 vars->line_speed = 0;
9128 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9130 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9131 MDIO_PMA_LASI_TXCTRL);
9133 bnx2x_cl45_read(bp, phy,
9134 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9136 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9139 bnx2x_cl45_read(bp, phy,
9140 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9143 * If a module is present and there is need to check
9146 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9147 /* Check over-current using 8727 GPIO0 input*/
9148 bnx2x_cl45_read(bp, phy,
9149 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9152 if ((val1 & (1<<8)) == 0) {
9153 if (!CHIP_IS_E1x(bp))
9154 oc_port = BP_PATH(bp) + (params->port << 1);
9156 "8727 Power fault has been detected on port %d\n",
9158 netdev_err(bp->dev, "Error: Power fault on Port %d has"
9159 " been detected and the power to "
9160 "that SFP+ module has been removed"
9161 " to prevent failure of the card."
9162 " Please remove the SFP+ module and"
9163 " restart the system to clear this"
9166 /* Disable all RX_ALARMs except for mod_abs */
9167 bnx2x_cl45_write(bp, phy,
9169 MDIO_PMA_LASI_RXCTRL, (1<<5));
9171 bnx2x_cl45_read(bp, phy,
9173 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9174 /* Wait for module_absent_event */
9176 bnx2x_cl45_write(bp, phy,
9178 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9179 /* Clear RX alarm */
9180 bnx2x_cl45_read(bp, phy,
9182 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9185 } /* Over current check */
9187 /* When module absent bit is set, check module */
9188 if (rx_alarm_status & (1<<5)) {
9189 bnx2x_8727_handle_mod_abs(phy, params);
9190 /* Enable all mod_abs and link detection bits */
9191 bnx2x_cl45_write(bp, phy,
9192 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9195 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
9196 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
9197 /* If transmitter is disabled, ignore false link up indication */
9198 bnx2x_cl45_read(bp, phy,
9199 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9200 if (val1 & (1<<15)) {
9201 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9205 bnx2x_cl45_read(bp, phy,
9207 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9210 * Bits 0..2 --> speed detected,
9211 * Bits 13..15--> link is down
9213 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9215 vars->line_speed = SPEED_10000;
9216 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9218 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9220 vars->line_speed = SPEED_1000;
9221 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9225 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9229 /* Capture 10G link fault. */
9230 if (vars->line_speed == SPEED_10000) {
9231 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9232 MDIO_PMA_LASI_TXSTAT, &val1);
9234 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9235 MDIO_PMA_LASI_TXSTAT, &val1);
9237 if (val1 & (1<<0)) {
9238 vars->fault_detected = 1;
9243 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9244 vars->duplex = DUPLEX_FULL;
9245 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9248 if ((DUAL_MEDIA(params)) &&
9249 (phy->req_line_speed == SPEED_1000)) {
9250 bnx2x_cl45_read(bp, phy,
9252 MDIO_PMA_REG_8727_PCS_GP, &val1);
9254 * In case of dual-media board and 1G, power up the XAUI side,
9255 * otherwise power it down. For 10G it is done automatically
9261 bnx2x_cl45_write(bp, phy,
9263 MDIO_PMA_REG_8727_PCS_GP, val1);
9268 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9269 struct link_params *params)
9271 struct bnx2x *bp = params->bp;
9273 /* Enable/Disable PHY transmitter output */
9274 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9276 /* Disable Transmitter */
9277 bnx2x_sfp_set_transmitter(params, phy, 0);
9279 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9283 /******************************************************************/
9284 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9285 /******************************************************************/
9286 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9287 struct link_params *params)
9289 u16 val, fw_ver1, fw_ver2, cnt;
9291 struct bnx2x *bp = params->bp;
9293 port = params->port;
9295 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9296 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9297 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9298 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9299 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9300 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9301 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9303 for (cnt = 0; cnt < 100; cnt++) {
9304 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9310 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9311 bnx2x_save_spirom_version(bp, port, 0,
9317 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9318 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9319 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9320 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9321 for (cnt = 0; cnt < 100; cnt++) {
9322 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9328 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9329 bnx2x_save_spirom_version(bp, port, 0,
9334 /* lower 16 bits of the register SPI_FW_STATUS */
9335 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9336 /* upper 16 bits of register SPI_FW_STATUS */
9337 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9339 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9343 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9344 struct bnx2x_phy *phy)
9348 /* PHYC_CTL_LED_CTL */
9349 bnx2x_cl45_read(bp, phy,
9351 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9355 bnx2x_cl45_write(bp, phy,
9357 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9359 bnx2x_cl45_write(bp, phy,
9361 MDIO_PMA_REG_8481_LED1_MASK,
9364 bnx2x_cl45_write(bp, phy,
9366 MDIO_PMA_REG_8481_LED2_MASK,
9369 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9370 bnx2x_cl45_write(bp, phy,
9372 MDIO_PMA_REG_8481_LED3_MASK,
9375 /* Select the closest activity blink rate to that in 10/100/1000 */
9376 bnx2x_cl45_write(bp, phy,
9378 MDIO_PMA_REG_8481_LED3_BLINK,
9381 /* Configure the blink rate to ~15.9 Hz */
9382 bnx2x_cl45_write(bp, phy,
9384 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9385 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9387 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9388 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9390 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9392 bnx2x_cl45_read(bp, phy,
9393 MDIO_PMA_DEVAD, offset, &val);
9394 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9395 bnx2x_cl45_write(bp, phy,
9396 MDIO_PMA_DEVAD, offset, val);
9398 /* 'Interrupt Mask' */
9399 bnx2x_cl45_write(bp, phy,
9404 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9405 struct link_params *params,
9406 struct link_vars *vars)
9408 struct bnx2x *bp = params->bp;
9409 u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9410 u16 tmp_req_line_speed;
9412 tmp_req_line_speed = phy->req_line_speed;
9413 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9414 if (phy->req_line_speed == SPEED_10000)
9415 phy->req_line_speed = SPEED_AUTO_NEG;
9418 * This phy uses the NIG latch mechanism since link indication
9419 * arrives through its LED4 and not via its LASI signal, so we
9420 * get steady signal instead of clear on read
9422 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9423 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9425 bnx2x_cl45_write(bp, phy,
9426 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9428 bnx2x_848xx_set_led(bp, phy);
9430 /* set 1000 speed advertisement */
9431 bnx2x_cl45_read(bp, phy,
9432 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9435 bnx2x_ext_phy_set_pause(params, phy, vars);
9436 bnx2x_cl45_read(bp, phy,
9438 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9440 bnx2x_cl45_read(bp, phy,
9441 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9443 /* Disable forced speed */
9444 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9445 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9447 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9448 (phy->speed_cap_mask &
9449 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9450 (phy->req_line_speed == SPEED_1000)) {
9451 an_1000_val |= (1<<8);
9452 autoneg_val |= (1<<9 | 1<<12);
9453 if (phy->req_duplex == DUPLEX_FULL)
9454 an_1000_val |= (1<<9);
9455 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9457 an_1000_val &= ~((1<<8) | (1<<9));
9459 bnx2x_cl45_write(bp, phy,
9460 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9463 /* set 100 speed advertisement */
9464 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9465 (phy->speed_cap_mask &
9466 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9467 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9469 (SUPPORTED_100baseT_Half |
9470 SUPPORTED_100baseT_Full)))) {
9471 an_10_100_val |= (1<<7);
9472 /* Enable autoneg and restart autoneg for legacy speeds */
9473 autoneg_val |= (1<<9 | 1<<12);
9475 if (phy->req_duplex == DUPLEX_FULL)
9476 an_10_100_val |= (1<<8);
9477 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9479 /* set 10 speed advertisement */
9480 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9481 (phy->speed_cap_mask &
9482 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9483 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9485 (SUPPORTED_10baseT_Half |
9486 SUPPORTED_10baseT_Full)))) {
9487 an_10_100_val |= (1<<5);
9488 autoneg_val |= (1<<9 | 1<<12);
9489 if (phy->req_duplex == DUPLEX_FULL)
9490 an_10_100_val |= (1<<6);
9491 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9494 /* Only 10/100 are allowed to work in FORCE mode */
9495 if ((phy->req_line_speed == SPEED_100) &&
9497 (SUPPORTED_100baseT_Half |
9498 SUPPORTED_100baseT_Full))) {
9499 autoneg_val |= (1<<13);
9500 /* Enabled AUTO-MDIX when autoneg is disabled */
9501 bnx2x_cl45_write(bp, phy,
9502 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9503 (1<<15 | 1<<9 | 7<<0));
9504 /* The PHY needs this set even for forced link. */
9505 an_10_100_val |= (1<<8) | (1<<7);
9506 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9508 if ((phy->req_line_speed == SPEED_10) &&
9510 (SUPPORTED_10baseT_Half |
9511 SUPPORTED_10baseT_Full))) {
9512 /* Enabled AUTO-MDIX when autoneg is disabled */
9513 bnx2x_cl45_write(bp, phy,
9514 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9515 (1<<15 | 1<<9 | 7<<0));
9516 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9519 bnx2x_cl45_write(bp, phy,
9520 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9523 if (phy->req_duplex == DUPLEX_FULL)
9524 autoneg_val |= (1<<8);
9527 * Always write this if this is not 84833.
9528 * For 84833, write it only when it's a forced speed.
9530 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9531 ((autoneg_val & (1<<12)) == 0))
9532 bnx2x_cl45_write(bp, phy,
9534 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9536 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9537 (phy->speed_cap_mask &
9538 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9539 (phy->req_line_speed == SPEED_10000)) {
9540 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9541 /* Restart autoneg for 10G*/
9543 bnx2x_cl45_read(bp, phy,
9545 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9547 bnx2x_cl45_write(bp, phy,
9549 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9550 an_10g_val | 0x1000);
9551 bnx2x_cl45_write(bp, phy,
9552 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9555 bnx2x_cl45_write(bp, phy,
9557 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9560 /* Save spirom version */
9561 bnx2x_save_848xx_spirom_version(phy, params);
9563 phy->req_line_speed = tmp_req_line_speed;
9568 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9569 struct link_params *params,
9570 struct link_vars *vars)
9572 struct bnx2x *bp = params->bp;
9573 /* Restore normal power mode*/
9574 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9575 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9578 bnx2x_ext_phy_hw_reset(bp, params->port);
9579 bnx2x_wait_reset_complete(bp, phy, params);
9581 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9582 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9585 #define PHY84833_CMDHDLR_WAIT 300
9586 #define PHY84833_CMDHDLR_MAX_ARGS 5
9587 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9588 struct link_params *params,
9594 struct bnx2x *bp = params->bp;
9595 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9596 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9597 MDIO_84833_CMD_HDLR_STATUS,
9598 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9599 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9600 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9601 MDIO_84833_CMD_HDLR_STATUS, &val);
9602 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9606 if (idx >= PHY84833_CMDHDLR_WAIT) {
9607 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9611 /* Prepare argument(s) and issue command */
9612 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9613 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9614 MDIO_84833_CMD_HDLR_DATA1 + idx,
9617 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9618 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9619 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9620 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9621 MDIO_84833_CMD_HDLR_STATUS, &val);
9622 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9623 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9627 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9628 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9629 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9632 /* Gather returning data */
9633 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9634 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9635 MDIO_84833_CMD_HDLR_DATA1 + idx,
9638 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9639 MDIO_84833_CMD_HDLR_STATUS,
9640 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9645 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9646 struct link_params *params,
9647 struct link_vars *vars)
9650 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9652 struct bnx2x *bp = params->bp;
9654 /* Check for configuration. */
9655 pair_swap = REG_RD(bp, params->shmem_base +
9656 offsetof(struct shmem_region,
9657 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9658 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9663 /* Only the second argument is used for this command */
9664 data[1] = (u16)pair_swap;
9666 status = bnx2x_84833_cmd_hdlr(phy, params,
9667 PHY84833_CMD_SET_PAIR_SWAP, data);
9669 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9674 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9675 u32 shmem_base_path[],
9681 if (CHIP_IS_E3(bp)) {
9682 /* Assume that these will be GPIOs, not EPIOs. */
9683 for (idx = 0; idx < 2; idx++) {
9684 /* Map config param to register bit. */
9685 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9686 offsetof(struct shmem_region,
9687 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9688 reset_pin[idx] = (reset_pin[idx] &
9689 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9690 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9691 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9692 reset_pin[idx] = (1 << reset_pin[idx]);
9694 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9696 /* E2, look from diff place of shmem. */
9697 for (idx = 0; idx < 2; idx++) {
9698 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9699 offsetof(struct shmem_region,
9700 dev_info.port_hw_config[0].default_cfg));
9701 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9702 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9703 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9704 reset_pin[idx] = (1 << reset_pin[idx]);
9706 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9712 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9713 struct link_params *params)
9715 struct bnx2x *bp = params->bp;
9717 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9718 offsetof(struct shmem2_region,
9719 other_shmem_base_addr));
9721 u32 shmem_base_path[2];
9722 shmem_base_path[0] = params->shmem_base;
9723 shmem_base_path[1] = other_shmem_base_addr;
9725 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9728 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9730 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9736 #define PHY84833_CONSTANT_LATENCY 1193
9737 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9738 struct link_params *params,
9739 struct link_vars *vars)
9741 struct bnx2x *bp = params->bp;
9742 u8 port, initialize = 1;
9744 u32 actual_phy_selection, cms_enable;
9745 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9750 if (!(CHIP_IS_E1(bp)))
9753 port = params->port;
9755 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9756 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9757 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9761 bnx2x_cl45_write(bp, phy,
9763 MDIO_PMA_REG_CTRL, 0x8000);
9766 bnx2x_wait_reset_complete(bp, phy, params);
9768 /* Wait for GPHY to come out of reset */
9770 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9771 /* Bring PHY out of super isolate mode */
9772 bnx2x_cl45_read(bp, phy,
9774 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9775 val &= ~MDIO_84833_SUPER_ISOLATE;
9776 bnx2x_cl45_write(bp, phy,
9778 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9779 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9782 * BCM84823 requires that XGXS links up first @ 10G for normal
9786 temp = vars->line_speed;
9787 vars->line_speed = SPEED_10000;
9788 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
9789 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
9790 vars->line_speed = temp;
9793 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9794 MDIO_CTL_REG_84823_MEDIA, &val);
9795 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9796 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9797 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9798 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9799 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9801 if (CHIP_IS_E3(bp)) {
9802 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9803 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9805 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9806 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9809 actual_phy_selection = bnx2x_phy_selection(params);
9811 switch (actual_phy_selection) {
9812 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9813 /* Do nothing. Essentially this is like the priority copper */
9815 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9816 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9818 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9819 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9821 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9822 /* Do nothing here. The first PHY won't be initialized at all */
9824 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9825 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9829 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9830 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9832 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9833 MDIO_CTL_REG_84823_MEDIA, val);
9834 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9835 params->multi_phy_config, val);
9838 if (params->feature_config_flags &
9839 FEATURE_CONFIG_AUTOGREEEN_ENABLED)
9845 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9846 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9847 rc = bnx2x_84833_cmd_hdlr(phy, params,
9848 PHY84833_CMD_SET_EEE_MODE, cmd_args);
9850 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
9852 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9854 bnx2x_save_848xx_spirom_version(phy, params);
9855 /* 84833 PHY has a better feature and doesn't need to support this. */
9856 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9857 cms_enable = REG_RD(bp, params->shmem_base +
9858 offsetof(struct shmem_region,
9859 dev_info.port_hw_config[params->port].default_cfg)) &
9860 PORT_HW_CFG_ENABLE_CMS_MASK;
9862 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9863 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9865 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9867 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9868 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9869 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9875 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9876 struct link_params *params,
9877 struct link_vars *vars)
9879 struct bnx2x *bp = params->bp;
9880 u16 val, val1, val2;
9884 /* Check 10G-BaseT link status */
9885 /* Check PMD signal ok */
9886 bnx2x_cl45_read(bp, phy,
9887 MDIO_AN_DEVAD, 0xFFFA, &val1);
9888 bnx2x_cl45_read(bp, phy,
9889 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9891 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9893 /* Check link 10G */
9894 if (val2 & (1<<11)) {
9895 vars->line_speed = SPEED_10000;
9896 vars->duplex = DUPLEX_FULL;
9898 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9899 } else { /* Check Legacy speed link */
9900 u16 legacy_status, legacy_speed;
9902 /* Enable expansion register 0x42 (Operation mode status) */
9903 bnx2x_cl45_write(bp, phy,
9905 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9907 /* Get legacy speed operation status */
9908 bnx2x_cl45_read(bp, phy,
9910 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9913 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
9915 link_up = ((legacy_status & (1<<11)) == (1<<11));
9917 legacy_speed = (legacy_status & (3<<9));
9918 if (legacy_speed == (0<<9))
9919 vars->line_speed = SPEED_10;
9920 else if (legacy_speed == (1<<9))
9921 vars->line_speed = SPEED_100;
9922 else if (legacy_speed == (2<<9))
9923 vars->line_speed = SPEED_1000;
9924 else /* Should not happen */
9925 vars->line_speed = 0;
9927 if (legacy_status & (1<<8))
9928 vars->duplex = DUPLEX_FULL;
9930 vars->duplex = DUPLEX_HALF;
9933 "Link is up in %dMbps, is_duplex_full= %d\n",
9935 (vars->duplex == DUPLEX_FULL));
9936 /* Check legacy speed AN resolution */
9937 bnx2x_cl45_read(bp, phy,
9939 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9942 vars->link_status |=
9943 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9944 bnx2x_cl45_read(bp, phy,
9946 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9948 if ((val & (1<<0)) == 0)
9949 vars->link_status |=
9950 LINK_STATUS_PARALLEL_DETECTION_USED;
9954 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9956 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9963 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9967 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9968 status = bnx2x_format_ver(spirom_ver, str, len);
9972 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9973 struct link_params *params)
9975 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9976 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9977 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9978 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9981 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9982 struct link_params *params)
9984 bnx2x_cl45_write(params->bp, phy,
9985 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9986 bnx2x_cl45_write(params->bp, phy,
9987 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9990 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9991 struct link_params *params)
9993 struct bnx2x *bp = params->bp;
9997 if (!(CHIP_IS_E1(bp)))
10000 port = params->port;
10002 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10003 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10004 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10007 bnx2x_cl45_read(bp, phy,
10010 bnx2x_cl45_write(bp, phy,
10012 MDIO_PMA_REG_CTRL, 0x800);
10016 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10017 struct link_params *params, u8 mode)
10019 struct bnx2x *bp = params->bp;
10023 if (!(CHIP_IS_E1(bp)))
10024 port = BP_PATH(bp);
10026 port = params->port;
10031 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10033 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10034 SHARED_HW_CFG_LED_EXTPHY1) {
10036 /* Set LED masks */
10037 bnx2x_cl45_write(bp, phy,
10039 MDIO_PMA_REG_8481_LED1_MASK,
10042 bnx2x_cl45_write(bp, phy,
10044 MDIO_PMA_REG_8481_LED2_MASK,
10047 bnx2x_cl45_write(bp, phy,
10049 MDIO_PMA_REG_8481_LED3_MASK,
10052 bnx2x_cl45_write(bp, phy,
10054 MDIO_PMA_REG_8481_LED5_MASK,
10058 bnx2x_cl45_write(bp, phy,
10060 MDIO_PMA_REG_8481_LED1_MASK,
10064 case LED_MODE_FRONT_PANEL_OFF:
10066 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10069 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10070 SHARED_HW_CFG_LED_EXTPHY1) {
10072 /* Set LED masks */
10073 bnx2x_cl45_write(bp, phy,
10075 MDIO_PMA_REG_8481_LED1_MASK,
10078 bnx2x_cl45_write(bp, phy,
10080 MDIO_PMA_REG_8481_LED2_MASK,
10083 bnx2x_cl45_write(bp, phy,
10085 MDIO_PMA_REG_8481_LED3_MASK,
10088 bnx2x_cl45_write(bp, phy,
10090 MDIO_PMA_REG_8481_LED5_MASK,
10094 bnx2x_cl45_write(bp, phy,
10096 MDIO_PMA_REG_8481_LED1_MASK,
10102 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10104 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10105 SHARED_HW_CFG_LED_EXTPHY1) {
10106 /* Set control reg */
10107 bnx2x_cl45_read(bp, phy,
10109 MDIO_PMA_REG_8481_LINK_SIGNAL,
10114 bnx2x_cl45_write(bp, phy,
10116 MDIO_PMA_REG_8481_LINK_SIGNAL,
10119 /* Set LED masks */
10120 bnx2x_cl45_write(bp, phy,
10122 MDIO_PMA_REG_8481_LED1_MASK,
10125 bnx2x_cl45_write(bp, phy,
10127 MDIO_PMA_REG_8481_LED2_MASK,
10130 bnx2x_cl45_write(bp, phy,
10132 MDIO_PMA_REG_8481_LED3_MASK,
10135 bnx2x_cl45_write(bp, phy,
10137 MDIO_PMA_REG_8481_LED5_MASK,
10140 bnx2x_cl45_write(bp, phy,
10142 MDIO_PMA_REG_8481_LED1_MASK,
10147 case LED_MODE_OPER:
10149 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10151 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10152 SHARED_HW_CFG_LED_EXTPHY1) {
10154 /* Set control reg */
10155 bnx2x_cl45_read(bp, phy,
10157 MDIO_PMA_REG_8481_LINK_SIGNAL,
10161 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10162 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10163 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10164 bnx2x_cl45_write(bp, phy,
10166 MDIO_PMA_REG_8481_LINK_SIGNAL,
10170 /* Set LED masks */
10171 bnx2x_cl45_write(bp, phy,
10173 MDIO_PMA_REG_8481_LED1_MASK,
10176 bnx2x_cl45_write(bp, phy,
10178 MDIO_PMA_REG_8481_LED2_MASK,
10181 bnx2x_cl45_write(bp, phy,
10183 MDIO_PMA_REG_8481_LED3_MASK,
10186 bnx2x_cl45_write(bp, phy,
10188 MDIO_PMA_REG_8481_LED5_MASK,
10192 bnx2x_cl45_write(bp, phy,
10194 MDIO_PMA_REG_8481_LED1_MASK,
10197 /* Tell LED3 to blink on source */
10198 bnx2x_cl45_read(bp, phy,
10200 MDIO_PMA_REG_8481_LINK_SIGNAL,
10203 val |= (1<<6); /* A83B[8:6]= 1 */
10204 bnx2x_cl45_write(bp, phy,
10206 MDIO_PMA_REG_8481_LINK_SIGNAL,
10213 * This is a workaround for E3+84833 until autoneg
10214 * restart is fixed in f/w
10216 if (CHIP_IS_E3(bp)) {
10217 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10218 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10222 /******************************************************************/
10223 /* 54618SE PHY SECTION */
10224 /******************************************************************/
10225 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10226 struct link_params *params,
10227 struct link_vars *vars)
10229 struct bnx2x *bp = params->bp;
10231 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10234 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10235 usleep_range(1000, 1000);
10237 /* This works with E3 only, no need to check the chip
10238 before determining the port. */
10239 port = params->port;
10241 cfg_pin = (REG_RD(bp, params->shmem_base +
10242 offsetof(struct shmem_region,
10243 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10244 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10245 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10247 /* Drive pin high to bring the GPHY out of reset. */
10248 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10250 /* wait for GPHY to reset */
10254 bnx2x_cl22_write(bp, phy,
10255 MDIO_PMA_REG_CTRL, 0x8000);
10256 bnx2x_wait_reset_complete(bp, phy, params);
10258 /*wait for GPHY to reset */
10261 /* Configure LED4: set to INTR (0x6). */
10262 /* Accessing shadow register 0xe. */
10263 bnx2x_cl22_write(bp, phy,
10264 MDIO_REG_GPHY_SHADOW,
10265 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10266 bnx2x_cl22_read(bp, phy,
10267 MDIO_REG_GPHY_SHADOW,
10269 temp &= ~(0xf << 4);
10270 temp |= (0x6 << 4);
10271 bnx2x_cl22_write(bp, phy,
10272 MDIO_REG_GPHY_SHADOW,
10273 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10274 /* Configure INTR based on link status change. */
10275 bnx2x_cl22_write(bp, phy,
10276 MDIO_REG_INTR_MASK,
10277 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10279 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10280 bnx2x_cl22_write(bp, phy,
10281 MDIO_REG_GPHY_SHADOW,
10282 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10283 bnx2x_cl22_read(bp, phy,
10284 MDIO_REG_GPHY_SHADOW,
10286 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10287 bnx2x_cl22_write(bp, phy,
10288 MDIO_REG_GPHY_SHADOW,
10289 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10292 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10293 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10295 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10296 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10297 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10299 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10300 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10301 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10303 /* read all advertisement */
10304 bnx2x_cl22_read(bp, phy,
10308 bnx2x_cl22_read(bp, phy,
10312 bnx2x_cl22_read(bp, phy,
10316 /* Disable forced speed */
10317 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10318 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10321 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10322 (phy->speed_cap_mask &
10323 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10324 (phy->req_line_speed == SPEED_1000)) {
10325 an_1000_val |= (1<<8);
10326 autoneg_val |= (1<<9 | 1<<12);
10327 if (phy->req_duplex == DUPLEX_FULL)
10328 an_1000_val |= (1<<9);
10329 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10331 an_1000_val &= ~((1<<8) | (1<<9));
10333 bnx2x_cl22_write(bp, phy,
10336 bnx2x_cl22_read(bp, phy,
10340 /* set 100 speed advertisement */
10341 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10342 (phy->speed_cap_mask &
10343 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10344 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10345 an_10_100_val |= (1<<7);
10346 /* Enable autoneg and restart autoneg for legacy speeds */
10347 autoneg_val |= (1<<9 | 1<<12);
10349 if (phy->req_duplex == DUPLEX_FULL)
10350 an_10_100_val |= (1<<8);
10351 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10354 /* set 10 speed advertisement */
10355 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10356 (phy->speed_cap_mask &
10357 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10358 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10359 an_10_100_val |= (1<<5);
10360 autoneg_val |= (1<<9 | 1<<12);
10361 if (phy->req_duplex == DUPLEX_FULL)
10362 an_10_100_val |= (1<<6);
10363 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10366 /* Only 10/100 are allowed to work in FORCE mode */
10367 if (phy->req_line_speed == SPEED_100) {
10368 autoneg_val |= (1<<13);
10369 /* Enabled AUTO-MDIX when autoneg is disabled */
10370 bnx2x_cl22_write(bp, phy,
10372 (1<<15 | 1<<9 | 7<<0));
10373 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10375 if (phy->req_line_speed == SPEED_10) {
10376 /* Enabled AUTO-MDIX when autoneg is disabled */
10377 bnx2x_cl22_write(bp, phy,
10379 (1<<15 | 1<<9 | 7<<0));
10380 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10383 /* Check if we should turn on Auto-GrEEEn */
10384 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10385 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10386 if (params->feature_config_flags &
10387 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10389 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10392 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10394 bnx2x_cl22_write(bp, phy,
10395 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10396 bnx2x_cl22_write(bp, phy,
10397 MDIO_REG_GPHY_CL45_DATA_REG,
10398 MDIO_REG_GPHY_EEE_ADV);
10399 bnx2x_cl22_write(bp, phy,
10400 MDIO_REG_GPHY_CL45_ADDR_REG,
10401 (0x1 << 14) | MDIO_AN_DEVAD);
10402 bnx2x_cl22_write(bp, phy,
10403 MDIO_REG_GPHY_CL45_DATA_REG,
10407 bnx2x_cl22_write(bp, phy,
10409 an_10_100_val | fc_val);
10411 if (phy->req_duplex == DUPLEX_FULL)
10412 autoneg_val |= (1<<8);
10414 bnx2x_cl22_write(bp, phy,
10415 MDIO_PMA_REG_CTRL, autoneg_val);
10421 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10422 struct link_params *params, u8 mode)
10424 struct bnx2x *bp = params->bp;
10427 bnx2x_cl22_write(bp, phy,
10428 MDIO_REG_GPHY_SHADOW,
10429 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10430 bnx2x_cl22_read(bp, phy,
10431 MDIO_REG_GPHY_SHADOW,
10435 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10437 case LED_MODE_FRONT_PANEL_OFF:
10441 case LED_MODE_OPER:
10450 bnx2x_cl22_write(bp, phy,
10451 MDIO_REG_GPHY_SHADOW,
10452 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10457 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10458 struct link_params *params)
10460 struct bnx2x *bp = params->bp;
10465 * In case of no EPIO routed to reset the GPHY, put it
10466 * in low power mode.
10468 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10470 * This works with E3 only, no need to check the chip
10471 * before determining the port.
10473 port = params->port;
10474 cfg_pin = (REG_RD(bp, params->shmem_base +
10475 offsetof(struct shmem_region,
10476 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10477 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10478 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10480 /* Drive pin low to put GPHY in reset. */
10481 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10484 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10485 struct link_params *params,
10486 struct link_vars *vars)
10488 struct bnx2x *bp = params->bp;
10491 u16 legacy_status, legacy_speed;
10493 /* Get speed operation status */
10494 bnx2x_cl22_read(bp, phy,
10497 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10499 /* Read status to clear the PHY interrupt. */
10500 bnx2x_cl22_read(bp, phy,
10501 MDIO_REG_INTR_STATUS,
10504 link_up = ((legacy_status & (1<<2)) == (1<<2));
10507 legacy_speed = (legacy_status & (7<<8));
10508 if (legacy_speed == (7<<8)) {
10509 vars->line_speed = SPEED_1000;
10510 vars->duplex = DUPLEX_FULL;
10511 } else if (legacy_speed == (6<<8)) {
10512 vars->line_speed = SPEED_1000;
10513 vars->duplex = DUPLEX_HALF;
10514 } else if (legacy_speed == (5<<8)) {
10515 vars->line_speed = SPEED_100;
10516 vars->duplex = DUPLEX_FULL;
10518 /* Omitting 100Base-T4 for now */
10519 else if (legacy_speed == (3<<8)) {
10520 vars->line_speed = SPEED_100;
10521 vars->duplex = DUPLEX_HALF;
10522 } else if (legacy_speed == (2<<8)) {
10523 vars->line_speed = SPEED_10;
10524 vars->duplex = DUPLEX_FULL;
10525 } else if (legacy_speed == (1<<8)) {
10526 vars->line_speed = SPEED_10;
10527 vars->duplex = DUPLEX_HALF;
10528 } else /* Should not happen */
10529 vars->line_speed = 0;
10532 "Link is up in %dMbps, is_duplex_full= %d\n",
10534 (vars->duplex == DUPLEX_FULL));
10536 /* Check legacy speed AN resolution */
10537 bnx2x_cl22_read(bp, phy,
10541 vars->link_status |=
10542 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10543 bnx2x_cl22_read(bp, phy,
10546 if ((val & (1<<0)) == 0)
10547 vars->link_status |=
10548 LINK_STATUS_PARALLEL_DETECTION_USED;
10550 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10553 /* Report whether EEE is resolved. */
10554 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10555 if (val == MDIO_REG_GPHY_ID_54618SE) {
10556 if (vars->link_status &
10557 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10560 bnx2x_cl22_write(bp, phy,
10561 MDIO_REG_GPHY_CL45_ADDR_REG,
10563 bnx2x_cl22_write(bp, phy,
10564 MDIO_REG_GPHY_CL45_DATA_REG,
10565 MDIO_REG_GPHY_EEE_RESOLVED);
10566 bnx2x_cl22_write(bp, phy,
10567 MDIO_REG_GPHY_CL45_ADDR_REG,
10568 (0x1 << 14) | MDIO_AN_DEVAD);
10569 bnx2x_cl22_read(bp, phy,
10570 MDIO_REG_GPHY_CL45_DATA_REG,
10573 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10576 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10581 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10582 struct link_params *params)
10584 struct bnx2x *bp = params->bp;
10586 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10588 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10590 /* Enable master/slave manual mmode and set to master */
10591 /* mii write 9 [bits set 11 12] */
10592 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10594 /* forced 1G and disable autoneg */
10595 /* set val [mii read 0] */
10596 /* set val [expr $val & [bits clear 6 12 13]] */
10597 /* set val [expr $val | [bits set 6 8]] */
10598 /* mii write 0 $val */
10599 bnx2x_cl22_read(bp, phy, 0x00, &val);
10600 val &= ~((1<<6) | (1<<12) | (1<<13));
10601 val |= (1<<6) | (1<<8);
10602 bnx2x_cl22_write(bp, phy, 0x00, val);
10604 /* Set external loopback and Tx using 6dB coding */
10605 /* mii write 0x18 7 */
10606 /* set val [mii read 0x18] */
10607 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10608 bnx2x_cl22_write(bp, phy, 0x18, 7);
10609 bnx2x_cl22_read(bp, phy, 0x18, &val);
10610 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10612 /* This register opens the gate for the UMAC despite its name */
10613 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10616 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10617 * length used by the MAC receive logic to check frames.
10619 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10622 /******************************************************************/
10623 /* SFX7101 PHY SECTION */
10624 /******************************************************************/
10625 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10626 struct link_params *params)
10628 struct bnx2x *bp = params->bp;
10629 /* SFX7101_XGXS_TEST1 */
10630 bnx2x_cl45_write(bp, phy,
10631 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10634 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10635 struct link_params *params,
10636 struct link_vars *vars)
10638 u16 fw_ver1, fw_ver2, val;
10639 struct bnx2x *bp = params->bp;
10640 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10642 /* Restore normal power mode*/
10643 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10644 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10646 bnx2x_ext_phy_hw_reset(bp, params->port);
10647 bnx2x_wait_reset_complete(bp, phy, params);
10649 bnx2x_cl45_write(bp, phy,
10650 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10651 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10652 bnx2x_cl45_write(bp, phy,
10653 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10655 bnx2x_ext_phy_set_pause(params, phy, vars);
10656 /* Restart autoneg */
10657 bnx2x_cl45_read(bp, phy,
10658 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10660 bnx2x_cl45_write(bp, phy,
10661 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10663 /* Save spirom version */
10664 bnx2x_cl45_read(bp, phy,
10665 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10667 bnx2x_cl45_read(bp, phy,
10668 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10669 bnx2x_save_spirom_version(bp, params->port,
10670 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10674 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10675 struct link_params *params,
10676 struct link_vars *vars)
10678 struct bnx2x *bp = params->bp;
10681 bnx2x_cl45_read(bp, phy,
10682 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10683 bnx2x_cl45_read(bp, phy,
10684 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10685 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10687 bnx2x_cl45_read(bp, phy,
10688 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10689 bnx2x_cl45_read(bp, phy,
10690 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10691 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10693 link_up = ((val1 & 4) == 4);
10694 /* if link is up print the AN outcome of the SFX7101 PHY */
10696 bnx2x_cl45_read(bp, phy,
10697 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10699 vars->line_speed = SPEED_10000;
10700 vars->duplex = DUPLEX_FULL;
10701 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10702 val2, (val2 & (1<<14)));
10703 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10704 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10709 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10713 str[0] = (spirom_ver & 0xFF);
10714 str[1] = (spirom_ver & 0xFF00) >> 8;
10715 str[2] = (spirom_ver & 0xFF0000) >> 16;
10716 str[3] = (spirom_ver & 0xFF000000) >> 24;
10722 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10726 bnx2x_cl45_read(bp, phy,
10728 MDIO_PMA_REG_7101_RESET, &val);
10730 for (cnt = 0; cnt < 10; cnt++) {
10732 /* Writes a self-clearing reset */
10733 bnx2x_cl45_write(bp, phy,
10735 MDIO_PMA_REG_7101_RESET,
10737 /* Wait for clear */
10738 bnx2x_cl45_read(bp, phy,
10740 MDIO_PMA_REG_7101_RESET, &val);
10742 if ((val & (1<<15)) == 0)
10747 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10748 struct link_params *params) {
10749 /* Low power mode is controlled by GPIO 2 */
10750 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10751 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10752 /* The PHY reset is controlled by GPIO 1 */
10753 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10754 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10757 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10758 struct link_params *params, u8 mode)
10761 struct bnx2x *bp = params->bp;
10763 case LED_MODE_FRONT_PANEL_OFF:
10770 case LED_MODE_OPER:
10774 bnx2x_cl45_write(bp, phy,
10776 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10780 /******************************************************************/
10781 /* STATIC PHY DECLARATION */
10782 /******************************************************************/
10784 static struct bnx2x_phy phy_null = {
10785 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10788 .flags = FLAGS_INIT_XGXS_FIRST,
10789 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10790 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10793 .media_type = ETH_PHY_NOT_PRESENT,
10795 .req_flow_ctrl = 0,
10796 .req_line_speed = 0,
10797 .speed_cap_mask = 0,
10800 .config_init = (config_init_t)NULL,
10801 .read_status = (read_status_t)NULL,
10802 .link_reset = (link_reset_t)NULL,
10803 .config_loopback = (config_loopback_t)NULL,
10804 .format_fw_ver = (format_fw_ver_t)NULL,
10805 .hw_reset = (hw_reset_t)NULL,
10806 .set_link_led = (set_link_led_t)NULL,
10807 .phy_specific_func = (phy_specific_func_t)NULL
10810 static struct bnx2x_phy phy_serdes = {
10811 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10815 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10816 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10818 .supported = (SUPPORTED_10baseT_Half |
10819 SUPPORTED_10baseT_Full |
10820 SUPPORTED_100baseT_Half |
10821 SUPPORTED_100baseT_Full |
10822 SUPPORTED_1000baseT_Full |
10823 SUPPORTED_2500baseX_Full |
10825 SUPPORTED_Autoneg |
10827 SUPPORTED_Asym_Pause),
10828 .media_type = ETH_PHY_BASE_T,
10830 .req_flow_ctrl = 0,
10831 .req_line_speed = 0,
10832 .speed_cap_mask = 0,
10835 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10836 .read_status = (read_status_t)bnx2x_link_settings_status,
10837 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10838 .config_loopback = (config_loopback_t)NULL,
10839 .format_fw_ver = (format_fw_ver_t)NULL,
10840 .hw_reset = (hw_reset_t)NULL,
10841 .set_link_led = (set_link_led_t)NULL,
10842 .phy_specific_func = (phy_specific_func_t)NULL
10845 static struct bnx2x_phy phy_xgxs = {
10846 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10850 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10851 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10853 .supported = (SUPPORTED_10baseT_Half |
10854 SUPPORTED_10baseT_Full |
10855 SUPPORTED_100baseT_Half |
10856 SUPPORTED_100baseT_Full |
10857 SUPPORTED_1000baseT_Full |
10858 SUPPORTED_2500baseX_Full |
10859 SUPPORTED_10000baseT_Full |
10861 SUPPORTED_Autoneg |
10863 SUPPORTED_Asym_Pause),
10864 .media_type = ETH_PHY_CX4,
10866 .req_flow_ctrl = 0,
10867 .req_line_speed = 0,
10868 .speed_cap_mask = 0,
10871 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10872 .read_status = (read_status_t)bnx2x_link_settings_status,
10873 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10874 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10875 .format_fw_ver = (format_fw_ver_t)NULL,
10876 .hw_reset = (hw_reset_t)NULL,
10877 .set_link_led = (set_link_led_t)NULL,
10878 .phy_specific_func = (phy_specific_func_t)NULL
10880 static struct bnx2x_phy phy_warpcore = {
10881 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10884 .flags = FLAGS_HW_LOCK_REQUIRED,
10885 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10886 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10888 .supported = (SUPPORTED_10baseT_Half |
10889 SUPPORTED_10baseT_Full |
10890 SUPPORTED_100baseT_Half |
10891 SUPPORTED_100baseT_Full |
10892 SUPPORTED_1000baseT_Full |
10893 SUPPORTED_10000baseT_Full |
10894 SUPPORTED_20000baseKR2_Full |
10895 SUPPORTED_20000baseMLD2_Full |
10897 SUPPORTED_Autoneg |
10899 SUPPORTED_Asym_Pause),
10900 .media_type = ETH_PHY_UNSPECIFIED,
10902 .req_flow_ctrl = 0,
10903 .req_line_speed = 0,
10904 .speed_cap_mask = 0,
10905 /* req_duplex = */0,
10907 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10908 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10909 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10910 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10911 .format_fw_ver = (format_fw_ver_t)NULL,
10912 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
10913 .set_link_led = (set_link_led_t)NULL,
10914 .phy_specific_func = (phy_specific_func_t)NULL
10918 static struct bnx2x_phy phy_7101 = {
10919 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10922 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10923 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10924 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10926 .supported = (SUPPORTED_10000baseT_Full |
10928 SUPPORTED_Autoneg |
10930 SUPPORTED_Asym_Pause),
10931 .media_type = ETH_PHY_BASE_T,
10933 .req_flow_ctrl = 0,
10934 .req_line_speed = 0,
10935 .speed_cap_mask = 0,
10938 .config_init = (config_init_t)bnx2x_7101_config_init,
10939 .read_status = (read_status_t)bnx2x_7101_read_status,
10940 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10941 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10942 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10943 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10944 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10945 .phy_specific_func = (phy_specific_func_t)NULL
10947 static struct bnx2x_phy phy_8073 = {
10948 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10951 .flags = FLAGS_HW_LOCK_REQUIRED,
10952 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10953 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10955 .supported = (SUPPORTED_10000baseT_Full |
10956 SUPPORTED_2500baseX_Full |
10957 SUPPORTED_1000baseT_Full |
10959 SUPPORTED_Autoneg |
10961 SUPPORTED_Asym_Pause),
10962 .media_type = ETH_PHY_KR,
10964 .req_flow_ctrl = 0,
10965 .req_line_speed = 0,
10966 .speed_cap_mask = 0,
10969 .config_init = (config_init_t)bnx2x_8073_config_init,
10970 .read_status = (read_status_t)bnx2x_8073_read_status,
10971 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10972 .config_loopback = (config_loopback_t)NULL,
10973 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10974 .hw_reset = (hw_reset_t)NULL,
10975 .set_link_led = (set_link_led_t)NULL,
10976 .phy_specific_func = (phy_specific_func_t)NULL
10978 static struct bnx2x_phy phy_8705 = {
10979 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10982 .flags = FLAGS_INIT_XGXS_FIRST,
10983 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10984 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10986 .supported = (SUPPORTED_10000baseT_Full |
10989 SUPPORTED_Asym_Pause),
10990 .media_type = ETH_PHY_XFP_FIBER,
10992 .req_flow_ctrl = 0,
10993 .req_line_speed = 0,
10994 .speed_cap_mask = 0,
10997 .config_init = (config_init_t)bnx2x_8705_config_init,
10998 .read_status = (read_status_t)bnx2x_8705_read_status,
10999 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11000 .config_loopback = (config_loopback_t)NULL,
11001 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11002 .hw_reset = (hw_reset_t)NULL,
11003 .set_link_led = (set_link_led_t)NULL,
11004 .phy_specific_func = (phy_specific_func_t)NULL
11006 static struct bnx2x_phy phy_8706 = {
11007 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11010 .flags = FLAGS_INIT_XGXS_FIRST,
11011 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11012 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11014 .supported = (SUPPORTED_10000baseT_Full |
11015 SUPPORTED_1000baseT_Full |
11018 SUPPORTED_Asym_Pause),
11019 .media_type = ETH_PHY_SFP_FIBER,
11021 .req_flow_ctrl = 0,
11022 .req_line_speed = 0,
11023 .speed_cap_mask = 0,
11026 .config_init = (config_init_t)bnx2x_8706_config_init,
11027 .read_status = (read_status_t)bnx2x_8706_read_status,
11028 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11029 .config_loopback = (config_loopback_t)NULL,
11030 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11031 .hw_reset = (hw_reset_t)NULL,
11032 .set_link_led = (set_link_led_t)NULL,
11033 .phy_specific_func = (phy_specific_func_t)NULL
11036 static struct bnx2x_phy phy_8726 = {
11037 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11040 .flags = (FLAGS_HW_LOCK_REQUIRED |
11041 FLAGS_INIT_XGXS_FIRST),
11042 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11043 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11045 .supported = (SUPPORTED_10000baseT_Full |
11046 SUPPORTED_1000baseT_Full |
11047 SUPPORTED_Autoneg |
11050 SUPPORTED_Asym_Pause),
11051 .media_type = ETH_PHY_NOT_PRESENT,
11053 .req_flow_ctrl = 0,
11054 .req_line_speed = 0,
11055 .speed_cap_mask = 0,
11058 .config_init = (config_init_t)bnx2x_8726_config_init,
11059 .read_status = (read_status_t)bnx2x_8726_read_status,
11060 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11061 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11062 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11063 .hw_reset = (hw_reset_t)NULL,
11064 .set_link_led = (set_link_led_t)NULL,
11065 .phy_specific_func = (phy_specific_func_t)NULL
11068 static struct bnx2x_phy phy_8727 = {
11069 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11072 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11073 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11074 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11076 .supported = (SUPPORTED_10000baseT_Full |
11077 SUPPORTED_1000baseT_Full |
11080 SUPPORTED_Asym_Pause),
11081 .media_type = ETH_PHY_NOT_PRESENT,
11083 .req_flow_ctrl = 0,
11084 .req_line_speed = 0,
11085 .speed_cap_mask = 0,
11088 .config_init = (config_init_t)bnx2x_8727_config_init,
11089 .read_status = (read_status_t)bnx2x_8727_read_status,
11090 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11091 .config_loopback = (config_loopback_t)NULL,
11092 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11093 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11094 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11095 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11097 static struct bnx2x_phy phy_8481 = {
11098 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11101 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11102 FLAGS_REARM_LATCH_SIGNAL,
11103 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11104 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11106 .supported = (SUPPORTED_10baseT_Half |
11107 SUPPORTED_10baseT_Full |
11108 SUPPORTED_100baseT_Half |
11109 SUPPORTED_100baseT_Full |
11110 SUPPORTED_1000baseT_Full |
11111 SUPPORTED_10000baseT_Full |
11113 SUPPORTED_Autoneg |
11115 SUPPORTED_Asym_Pause),
11116 .media_type = ETH_PHY_BASE_T,
11118 .req_flow_ctrl = 0,
11119 .req_line_speed = 0,
11120 .speed_cap_mask = 0,
11123 .config_init = (config_init_t)bnx2x_8481_config_init,
11124 .read_status = (read_status_t)bnx2x_848xx_read_status,
11125 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11126 .config_loopback = (config_loopback_t)NULL,
11127 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11128 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11129 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11130 .phy_specific_func = (phy_specific_func_t)NULL
11133 static struct bnx2x_phy phy_84823 = {
11134 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11137 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11138 FLAGS_REARM_LATCH_SIGNAL,
11139 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11140 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11142 .supported = (SUPPORTED_10baseT_Half |
11143 SUPPORTED_10baseT_Full |
11144 SUPPORTED_100baseT_Half |
11145 SUPPORTED_100baseT_Full |
11146 SUPPORTED_1000baseT_Full |
11147 SUPPORTED_10000baseT_Full |
11149 SUPPORTED_Autoneg |
11151 SUPPORTED_Asym_Pause),
11152 .media_type = ETH_PHY_BASE_T,
11154 .req_flow_ctrl = 0,
11155 .req_line_speed = 0,
11156 .speed_cap_mask = 0,
11159 .config_init = (config_init_t)bnx2x_848x3_config_init,
11160 .read_status = (read_status_t)bnx2x_848xx_read_status,
11161 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11162 .config_loopback = (config_loopback_t)NULL,
11163 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11164 .hw_reset = (hw_reset_t)NULL,
11165 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11166 .phy_specific_func = (phy_specific_func_t)NULL
11169 static struct bnx2x_phy phy_84833 = {
11170 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11173 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11174 FLAGS_REARM_LATCH_SIGNAL,
11175 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11176 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11178 .supported = (SUPPORTED_100baseT_Half |
11179 SUPPORTED_100baseT_Full |
11180 SUPPORTED_1000baseT_Full |
11181 SUPPORTED_10000baseT_Full |
11183 SUPPORTED_Autoneg |
11185 SUPPORTED_Asym_Pause),
11186 .media_type = ETH_PHY_BASE_T,
11188 .req_flow_ctrl = 0,
11189 .req_line_speed = 0,
11190 .speed_cap_mask = 0,
11193 .config_init = (config_init_t)bnx2x_848x3_config_init,
11194 .read_status = (read_status_t)bnx2x_848xx_read_status,
11195 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11196 .config_loopback = (config_loopback_t)NULL,
11197 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11198 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11199 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11200 .phy_specific_func = (phy_specific_func_t)NULL
11203 static struct bnx2x_phy phy_54618se = {
11204 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11207 .flags = FLAGS_INIT_XGXS_FIRST,
11208 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11209 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11211 .supported = (SUPPORTED_10baseT_Half |
11212 SUPPORTED_10baseT_Full |
11213 SUPPORTED_100baseT_Half |
11214 SUPPORTED_100baseT_Full |
11215 SUPPORTED_1000baseT_Full |
11217 SUPPORTED_Autoneg |
11219 SUPPORTED_Asym_Pause),
11220 .media_type = ETH_PHY_BASE_T,
11222 .req_flow_ctrl = 0,
11223 .req_line_speed = 0,
11224 .speed_cap_mask = 0,
11225 /* req_duplex = */0,
11227 .config_init = (config_init_t)bnx2x_54618se_config_init,
11228 .read_status = (read_status_t)bnx2x_54618se_read_status,
11229 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11230 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11231 .format_fw_ver = (format_fw_ver_t)NULL,
11232 .hw_reset = (hw_reset_t)NULL,
11233 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11234 .phy_specific_func = (phy_specific_func_t)NULL
11236 /*****************************************************************/
11238 /* Populate the phy according. Main function: bnx2x_populate_phy */
11240 /*****************************************************************/
11242 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11243 struct bnx2x_phy *phy, u8 port,
11246 /* Get the 4 lanes xgxs config rx and tx */
11247 u32 rx = 0, tx = 0, i;
11248 for (i = 0; i < 2; i++) {
11250 * INT_PHY and EXT_PHY1 share the same value location in the
11251 * shmem. When num_phys is greater than 1, than this value
11252 * applies only to EXT_PHY1
11254 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11255 rx = REG_RD(bp, shmem_base +
11256 offsetof(struct shmem_region,
11257 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11259 tx = REG_RD(bp, shmem_base +
11260 offsetof(struct shmem_region,
11261 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11263 rx = REG_RD(bp, shmem_base +
11264 offsetof(struct shmem_region,
11265 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11267 tx = REG_RD(bp, shmem_base +
11268 offsetof(struct shmem_region,
11269 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11272 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11273 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11275 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11276 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11280 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11281 u8 phy_index, u8 port)
11283 u32 ext_phy_config = 0;
11284 switch (phy_index) {
11286 ext_phy_config = REG_RD(bp, shmem_base +
11287 offsetof(struct shmem_region,
11288 dev_info.port_hw_config[port].external_phy_config));
11291 ext_phy_config = REG_RD(bp, shmem_base +
11292 offsetof(struct shmem_region,
11293 dev_info.port_hw_config[port].external_phy_config2));
11296 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11300 return ext_phy_config;
11302 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11303 struct bnx2x_phy *phy)
11307 u32 switch_cfg = (REG_RD(bp, shmem_base +
11308 offsetof(struct shmem_region,
11309 dev_info.port_feature_config[port].link_config)) &
11310 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11311 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11312 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11314 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11315 if (USES_WARPCORE(bp)) {
11317 phy_addr = REG_RD(bp,
11318 MISC_REG_WC0_CTRL_PHY_ADDR);
11319 *phy = phy_warpcore;
11320 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11321 phy->flags |= FLAGS_4_PORT_MODE;
11323 phy->flags &= ~FLAGS_4_PORT_MODE;
11324 /* Check Dual mode */
11325 serdes_net_if = (REG_RD(bp, shmem_base +
11326 offsetof(struct shmem_region, dev_info.
11327 port_hw_config[port].default_cfg)) &
11328 PORT_HW_CFG_NET_SERDES_IF_MASK);
11330 * Set the appropriate supported and flags indications per
11331 * interface type of the chip
11333 switch (serdes_net_if) {
11334 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11335 phy->supported &= (SUPPORTED_10baseT_Half |
11336 SUPPORTED_10baseT_Full |
11337 SUPPORTED_100baseT_Half |
11338 SUPPORTED_100baseT_Full |
11339 SUPPORTED_1000baseT_Full |
11341 SUPPORTED_Autoneg |
11343 SUPPORTED_Asym_Pause);
11344 phy->media_type = ETH_PHY_BASE_T;
11346 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11347 phy->media_type = ETH_PHY_XFP_FIBER;
11349 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11350 phy->supported &= (SUPPORTED_1000baseT_Full |
11351 SUPPORTED_10000baseT_Full |
11354 SUPPORTED_Asym_Pause);
11355 phy->media_type = ETH_PHY_SFP_FIBER;
11357 case PORT_HW_CFG_NET_SERDES_IF_KR:
11358 phy->media_type = ETH_PHY_KR;
11359 phy->supported &= (SUPPORTED_1000baseT_Full |
11360 SUPPORTED_10000baseT_Full |
11362 SUPPORTED_Autoneg |
11364 SUPPORTED_Asym_Pause);
11366 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11367 phy->media_type = ETH_PHY_KR;
11368 phy->flags |= FLAGS_WC_DUAL_MODE;
11369 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11372 SUPPORTED_Asym_Pause);
11374 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11375 phy->media_type = ETH_PHY_KR;
11376 phy->flags |= FLAGS_WC_DUAL_MODE;
11377 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11380 SUPPORTED_Asym_Pause);
11383 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11389 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11390 * was not set as expected. For B0, ECO will be enabled so there
11391 * won't be an issue there
11393 if (CHIP_REV(bp) == CHIP_REV_Ax)
11394 phy->flags |= FLAGS_MDC_MDIO_WA;
11396 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11398 switch (switch_cfg) {
11399 case SWITCH_CFG_1G:
11400 phy_addr = REG_RD(bp,
11401 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11405 case SWITCH_CFG_10G:
11406 phy_addr = REG_RD(bp,
11407 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11412 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11416 phy->addr = (u8)phy_addr;
11417 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11418 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11420 if (CHIP_IS_E2(bp))
11421 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11423 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11425 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11426 port, phy->addr, phy->mdio_ctrl);
11428 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11432 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11437 struct bnx2x_phy *phy)
11439 u32 ext_phy_config, phy_type, config2;
11440 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11441 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11443 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11444 /* Select the phy type */
11445 switch (phy_type) {
11446 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11447 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11450 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11453 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11456 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11457 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11460 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11461 /* BCM8727_NOC => BCM8727 no over current */
11462 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11464 phy->flags |= FLAGS_NOC;
11466 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11467 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11468 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11471 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11474 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11477 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11480 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11481 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11482 *phy = phy_54618se;
11484 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11487 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11492 /* In case external PHY wasn't found */
11493 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11494 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11499 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11500 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11503 * The shmem address of the phy version is located on different
11504 * structures. In case this structure is too old, do not set
11507 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11508 dev_info.shared_hw_config.config2));
11509 if (phy_index == EXT_PHY1) {
11510 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11511 port_mb[port].ext_phy_fw_version);
11513 /* Check specific mdc mdio settings */
11514 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11515 mdc_mdio_access = config2 &
11516 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11518 u32 size = REG_RD(bp, shmem2_base);
11521 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11522 phy->ver_addr = shmem2_base +
11523 offsetof(struct shmem2_region,
11524 ext_phy_fw_version2[port]);
11526 /* Check specific mdc mdio settings */
11527 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11528 mdc_mdio_access = (config2 &
11529 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11530 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11531 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11533 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11536 * In case mdc/mdio_access of the external phy is different than the
11537 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11538 * to prevent one port interfere with another port's CL45 operations.
11540 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11541 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11542 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11543 phy_type, port, phy_index);
11544 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11545 phy->addr, phy->mdio_ctrl);
11549 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11550 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11553 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11554 if (phy_index == INT_PHY)
11555 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11556 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11561 static void bnx2x_phy_def_cfg(struct link_params *params,
11562 struct bnx2x_phy *phy,
11565 struct bnx2x *bp = params->bp;
11567 /* Populate the default phy configuration for MF mode */
11568 if (phy_index == EXT_PHY2) {
11569 link_config = REG_RD(bp, params->shmem_base +
11570 offsetof(struct shmem_region, dev_info.
11571 port_feature_config[params->port].link_config2));
11572 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11573 offsetof(struct shmem_region,
11575 port_hw_config[params->port].speed_capability_mask2));
11577 link_config = REG_RD(bp, params->shmem_base +
11578 offsetof(struct shmem_region, dev_info.
11579 port_feature_config[params->port].link_config));
11580 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11581 offsetof(struct shmem_region,
11583 port_hw_config[params->port].speed_capability_mask));
11586 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11587 phy_index, link_config, phy->speed_cap_mask);
11589 phy->req_duplex = DUPLEX_FULL;
11590 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11591 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11592 phy->req_duplex = DUPLEX_HALF;
11593 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11594 phy->req_line_speed = SPEED_10;
11596 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11597 phy->req_duplex = DUPLEX_HALF;
11598 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11599 phy->req_line_speed = SPEED_100;
11601 case PORT_FEATURE_LINK_SPEED_1G:
11602 phy->req_line_speed = SPEED_1000;
11604 case PORT_FEATURE_LINK_SPEED_2_5G:
11605 phy->req_line_speed = SPEED_2500;
11607 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11608 phy->req_line_speed = SPEED_10000;
11611 phy->req_line_speed = SPEED_AUTO_NEG;
11615 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11616 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11617 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11619 case PORT_FEATURE_FLOW_CONTROL_TX:
11620 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11622 case PORT_FEATURE_FLOW_CONTROL_RX:
11623 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11625 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11626 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11629 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11634 u32 bnx2x_phy_selection(struct link_params *params)
11636 u32 phy_config_swapped, prio_cfg;
11637 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11639 phy_config_swapped = params->multi_phy_config &
11640 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11642 prio_cfg = params->multi_phy_config &
11643 PORT_HW_CFG_PHY_SELECTION_MASK;
11645 if (phy_config_swapped) {
11646 switch (prio_cfg) {
11647 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11648 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11650 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11651 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11653 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11654 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11656 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11657 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11661 return_cfg = prio_cfg;
11667 int bnx2x_phy_probe(struct link_params *params)
11669 u8 phy_index, actual_phy_idx, link_cfg_idx;
11670 u32 phy_config_swapped, sync_offset, media_types;
11671 struct bnx2x *bp = params->bp;
11672 struct bnx2x_phy *phy;
11673 params->num_phys = 0;
11674 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11675 phy_config_swapped = params->multi_phy_config &
11676 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11678 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11680 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11681 actual_phy_idx = phy_index;
11682 if (phy_config_swapped) {
11683 if (phy_index == EXT_PHY1)
11684 actual_phy_idx = EXT_PHY2;
11685 else if (phy_index == EXT_PHY2)
11686 actual_phy_idx = EXT_PHY1;
11688 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11689 " actual_phy_idx %x\n", phy_config_swapped,
11690 phy_index, actual_phy_idx);
11691 phy = ¶ms->phy[actual_phy_idx];
11692 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11693 params->shmem2_base, params->port,
11695 params->num_phys = 0;
11696 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11698 for (phy_index = INT_PHY;
11699 phy_index < MAX_PHYS;
11704 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11707 sync_offset = params->shmem_base +
11708 offsetof(struct shmem_region,
11709 dev_info.port_hw_config[params->port].media_type);
11710 media_types = REG_RD(bp, sync_offset);
11713 * Update media type for non-PMF sync only for the first time
11714 * In case the media type changes afterwards, it will be updated
11715 * using the update_status function
11717 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11718 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11719 actual_phy_idx))) == 0) {
11720 media_types |= ((phy->media_type &
11721 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11722 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11725 REG_WR(bp, sync_offset, media_types);
11727 bnx2x_phy_def_cfg(params, phy, phy_index);
11728 params->num_phys++;
11731 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11735 void bnx2x_init_bmac_loopback(struct link_params *params,
11736 struct link_vars *vars)
11738 struct bnx2x *bp = params->bp;
11740 vars->line_speed = SPEED_10000;
11741 vars->duplex = DUPLEX_FULL;
11742 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11743 vars->mac_type = MAC_TYPE_BMAC;
11745 vars->phy_flags = PHY_XGXS_FLAG;
11747 bnx2x_xgxs_deassert(params);
11749 /* set bmac loopback */
11750 bnx2x_bmac_enable(params, vars, 1);
11752 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11755 void bnx2x_init_emac_loopback(struct link_params *params,
11756 struct link_vars *vars)
11758 struct bnx2x *bp = params->bp;
11760 vars->line_speed = SPEED_1000;
11761 vars->duplex = DUPLEX_FULL;
11762 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11763 vars->mac_type = MAC_TYPE_EMAC;
11765 vars->phy_flags = PHY_XGXS_FLAG;
11767 bnx2x_xgxs_deassert(params);
11768 /* set bmac loopback */
11769 bnx2x_emac_enable(params, vars, 1);
11770 bnx2x_emac_program(params, vars);
11771 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11774 void bnx2x_init_xmac_loopback(struct link_params *params,
11775 struct link_vars *vars)
11777 struct bnx2x *bp = params->bp;
11779 if (!params->req_line_speed[0])
11780 vars->line_speed = SPEED_10000;
11782 vars->line_speed = params->req_line_speed[0];
11783 vars->duplex = DUPLEX_FULL;
11784 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11785 vars->mac_type = MAC_TYPE_XMAC;
11786 vars->phy_flags = PHY_XGXS_FLAG;
11788 * Set WC to loopback mode since link is required to provide clock
11789 * to the XMAC in 20G mode
11791 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
11792 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
11793 params->phy[INT_PHY].config_loopback(
11794 ¶ms->phy[INT_PHY],
11797 bnx2x_xmac_enable(params, vars, 1);
11798 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11801 void bnx2x_init_umac_loopback(struct link_params *params,
11802 struct link_vars *vars)
11804 struct bnx2x *bp = params->bp;
11806 vars->line_speed = SPEED_1000;
11807 vars->duplex = DUPLEX_FULL;
11808 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11809 vars->mac_type = MAC_TYPE_UMAC;
11810 vars->phy_flags = PHY_XGXS_FLAG;
11811 bnx2x_umac_enable(params, vars, 1);
11813 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11816 void bnx2x_init_xgxs_loopback(struct link_params *params,
11817 struct link_vars *vars)
11819 struct bnx2x *bp = params->bp;
11821 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11822 vars->duplex = DUPLEX_FULL;
11823 if (params->req_line_speed[0] == SPEED_1000)
11824 vars->line_speed = SPEED_1000;
11826 vars->line_speed = SPEED_10000;
11828 if (!USES_WARPCORE(bp))
11829 bnx2x_xgxs_deassert(params);
11830 bnx2x_link_initialize(params, vars);
11832 if (params->req_line_speed[0] == SPEED_1000) {
11833 if (USES_WARPCORE(bp))
11834 bnx2x_umac_enable(params, vars, 0);
11836 bnx2x_emac_program(params, vars);
11837 bnx2x_emac_enable(params, vars, 0);
11840 if (USES_WARPCORE(bp))
11841 bnx2x_xmac_enable(params, vars, 0);
11843 bnx2x_bmac_enable(params, vars, 0);
11846 if (params->loopback_mode == LOOPBACK_XGXS) {
11847 /* set 10G XGXS loopback */
11848 params->phy[INT_PHY].config_loopback(
11849 ¶ms->phy[INT_PHY],
11853 /* set external phy loopback */
11855 for (phy_index = EXT_PHY1;
11856 phy_index < params->num_phys; phy_index++) {
11857 if (params->phy[phy_index].config_loopback)
11858 params->phy[phy_index].config_loopback(
11859 ¶ms->phy[phy_index],
11863 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11865 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11868 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11870 struct bnx2x *bp = params->bp;
11871 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11872 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11873 params->req_line_speed[0], params->req_flow_ctrl[0]);
11874 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11875 params->req_line_speed[1], params->req_flow_ctrl[1]);
11876 vars->link_status = 0;
11877 vars->phy_link_up = 0;
11879 vars->line_speed = 0;
11880 vars->duplex = DUPLEX_FULL;
11881 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11882 vars->mac_type = MAC_TYPE_NONE;
11883 vars->phy_flags = 0;
11885 /* disable attentions */
11886 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11887 (NIG_MASK_XGXS0_LINK_STATUS |
11888 NIG_MASK_XGXS0_LINK10G |
11889 NIG_MASK_SERDES0_LINK_STATUS |
11892 bnx2x_emac_init(params, vars);
11894 if (params->num_phys == 0) {
11895 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11898 set_phy_vars(params, vars);
11900 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11901 switch (params->loopback_mode) {
11902 case LOOPBACK_BMAC:
11903 bnx2x_init_bmac_loopback(params, vars);
11905 case LOOPBACK_EMAC:
11906 bnx2x_init_emac_loopback(params, vars);
11908 case LOOPBACK_XMAC:
11909 bnx2x_init_xmac_loopback(params, vars);
11911 case LOOPBACK_UMAC:
11912 bnx2x_init_umac_loopback(params, vars);
11914 case LOOPBACK_XGXS:
11915 case LOOPBACK_EXT_PHY:
11916 bnx2x_init_xgxs_loopback(params, vars);
11919 if (!CHIP_IS_E3(bp)) {
11920 if (params->switch_cfg == SWITCH_CFG_10G)
11921 bnx2x_xgxs_deassert(params);
11923 bnx2x_serdes_deassert(bp, params->port);
11925 bnx2x_link_initialize(params, vars);
11927 bnx2x_link_int_enable(params);
11933 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11936 struct bnx2x *bp = params->bp;
11937 u8 phy_index, port = params->port, clear_latch_ind = 0;
11938 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11939 /* disable attentions */
11940 vars->link_status = 0;
11941 bnx2x_update_mng(params, vars->link_status);
11942 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11943 (NIG_MASK_XGXS0_LINK_STATUS |
11944 NIG_MASK_XGXS0_LINK10G |
11945 NIG_MASK_SERDES0_LINK_STATUS |
11948 /* activate nig drain */
11949 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11951 /* disable nig egress interface */
11952 if (!CHIP_IS_E3(bp)) {
11953 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11954 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11957 /* Stop BigMac rx */
11958 if (!CHIP_IS_E3(bp))
11959 bnx2x_bmac_rx_disable(bp, port);
11961 bnx2x_xmac_disable(params);
11962 bnx2x_umac_disable(params);
11965 if (!CHIP_IS_E3(bp))
11966 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11969 /* The PHY reset is controlled by GPIO 1
11970 * Hold it as vars low
11972 /* clear link led */
11973 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11975 if (reset_ext_phy) {
11976 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11977 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11979 if (params->phy[phy_index].link_reset) {
11980 bnx2x_set_aer_mmd(params,
11981 ¶ms->phy[phy_index]);
11982 params->phy[phy_index].link_reset(
11983 ¶ms->phy[phy_index],
11986 if (params->phy[phy_index].flags &
11987 FLAGS_REARM_LATCH_SIGNAL)
11988 clear_latch_ind = 1;
11992 if (clear_latch_ind) {
11993 /* Clear latching indication */
11994 bnx2x_rearm_latch_signal(bp, port, 0);
11995 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11996 1 << NIG_LATCH_BC_ENABLE_MI_INT);
11998 if (params->phy[INT_PHY].link_reset)
11999 params->phy[INT_PHY].link_reset(
12000 ¶ms->phy[INT_PHY], params);
12002 /* disable nig ingress interface */
12003 if (!CHIP_IS_E3(bp)) {
12005 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12006 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12007 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12008 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12010 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12011 bnx2x_set_xumac_nig(params, 0, 0);
12012 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12013 MISC_REGISTERS_RESET_REG_2_XMAC)
12014 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12015 XMAC_CTRL_REG_SOFT_RESET);
12018 vars->phy_flags = 0;
12022 /****************************************************************************/
12023 /* Common function */
12024 /****************************************************************************/
12025 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12026 u32 shmem_base_path[],
12027 u32 shmem2_base_path[], u8 phy_index,
12030 struct bnx2x_phy phy[PORT_MAX];
12031 struct bnx2x_phy *phy_blk[PORT_MAX];
12034 s8 port_of_path = 0;
12035 u32 swap_val, swap_override;
12036 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12037 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12038 port ^= (swap_val && swap_override);
12039 bnx2x_ext_phy_hw_reset(bp, port);
12040 /* PART1 - Reset both phys */
12041 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12042 u32 shmem_base, shmem2_base;
12043 /* In E2, same phy is using for port0 of the two paths */
12044 if (CHIP_IS_E1x(bp)) {
12045 shmem_base = shmem_base_path[0];
12046 shmem2_base = shmem2_base_path[0];
12047 port_of_path = port;
12049 shmem_base = shmem_base_path[port];
12050 shmem2_base = shmem2_base_path[port];
12054 /* Extract the ext phy address for the port */
12055 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12056 port_of_path, &phy[port]) !=
12058 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12061 /* disable attentions */
12062 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12064 (NIG_MASK_XGXS0_LINK_STATUS |
12065 NIG_MASK_XGXS0_LINK10G |
12066 NIG_MASK_SERDES0_LINK_STATUS |
12069 /* Need to take the phy out of low power mode in order
12070 to write to access its registers */
12071 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12072 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12075 /* Reset the phy */
12076 bnx2x_cl45_write(bp, &phy[port],
12082 /* Add delay of 150ms after reset */
12085 if (phy[PORT_0].addr & 0x1) {
12086 phy_blk[PORT_0] = &(phy[PORT_1]);
12087 phy_blk[PORT_1] = &(phy[PORT_0]);
12089 phy_blk[PORT_0] = &(phy[PORT_0]);
12090 phy_blk[PORT_1] = &(phy[PORT_1]);
12093 /* PART2 - Download firmware to both phys */
12094 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12095 if (CHIP_IS_E1x(bp))
12096 port_of_path = port;
12100 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12101 phy_blk[port]->addr);
12102 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12106 /* Only set bit 10 = 1 (Tx power down) */
12107 bnx2x_cl45_read(bp, phy_blk[port],
12109 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12111 /* Phase1 of TX_POWER_DOWN reset */
12112 bnx2x_cl45_write(bp, phy_blk[port],
12114 MDIO_PMA_REG_TX_POWER_DOWN,
12119 * Toggle Transmitter: Power down and then up with 600ms delay
12124 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12125 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12126 /* Phase2 of POWER_DOWN_RESET */
12127 /* Release bit 10 (Release Tx power down) */
12128 bnx2x_cl45_read(bp, phy_blk[port],
12130 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12132 bnx2x_cl45_write(bp, phy_blk[port],
12134 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12137 /* Read modify write the SPI-ROM version select register */
12138 bnx2x_cl45_read(bp, phy_blk[port],
12140 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12141 bnx2x_cl45_write(bp, phy_blk[port],
12143 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12145 /* set GPIO2 back to LOW */
12146 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12147 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12151 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12152 u32 shmem_base_path[],
12153 u32 shmem2_base_path[], u8 phy_index,
12158 struct bnx2x_phy phy;
12159 /* Use port1 because of the static port-swap */
12160 /* Enable the module detection interrupt */
12161 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12162 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12163 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12164 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12166 bnx2x_ext_phy_hw_reset(bp, 0);
12168 for (port = 0; port < PORT_MAX; port++) {
12169 u32 shmem_base, shmem2_base;
12171 /* In E2, same phy is using for port0 of the two paths */
12172 if (CHIP_IS_E1x(bp)) {
12173 shmem_base = shmem_base_path[0];
12174 shmem2_base = shmem2_base_path[0];
12176 shmem_base = shmem_base_path[port];
12177 shmem2_base = shmem2_base_path[port];
12179 /* Extract the ext phy address for the port */
12180 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12183 DP(NETIF_MSG_LINK, "populate phy failed\n");
12188 bnx2x_cl45_write(bp, &phy,
12189 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12192 /* Set fault module detected LED on */
12193 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12194 MISC_REGISTERS_GPIO_HIGH,
12200 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12201 u8 *io_gpio, u8 *io_port)
12204 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12205 offsetof(struct shmem_region,
12206 dev_info.port_hw_config[PORT_0].default_cfg));
12207 switch (phy_gpio_reset) {
12208 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12212 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12216 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12220 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12224 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12228 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12232 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12236 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12241 /* Don't override the io_gpio and io_port */
12246 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12247 u32 shmem_base_path[],
12248 u32 shmem2_base_path[], u8 phy_index,
12251 s8 port, reset_gpio;
12252 u32 swap_val, swap_override;
12253 struct bnx2x_phy phy[PORT_MAX];
12254 struct bnx2x_phy *phy_blk[PORT_MAX];
12256 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12257 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12259 reset_gpio = MISC_REGISTERS_GPIO_1;
12263 * Retrieve the reset gpio/port which control the reset.
12264 * Default is GPIO1, PORT1
12266 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12267 (u8 *)&reset_gpio, (u8 *)&port);
12269 /* Calculate the port based on port swap */
12270 port ^= (swap_val && swap_override);
12272 /* Initiate PHY reset*/
12273 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12276 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12281 /* PART1 - Reset both phys */
12282 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12283 u32 shmem_base, shmem2_base;
12285 /* In E2, same phy is using for port0 of the two paths */
12286 if (CHIP_IS_E1x(bp)) {
12287 shmem_base = shmem_base_path[0];
12288 shmem2_base = shmem2_base_path[0];
12289 port_of_path = port;
12291 shmem_base = shmem_base_path[port];
12292 shmem2_base = shmem2_base_path[port];
12296 /* Extract the ext phy address for the port */
12297 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12298 port_of_path, &phy[port]) !=
12300 DP(NETIF_MSG_LINK, "populate phy failed\n");
12303 /* disable attentions */
12304 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12306 (NIG_MASK_XGXS0_LINK_STATUS |
12307 NIG_MASK_XGXS0_LINK10G |
12308 NIG_MASK_SERDES0_LINK_STATUS |
12312 /* Reset the phy */
12313 bnx2x_cl45_write(bp, &phy[port],
12314 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12317 /* Add delay of 150ms after reset */
12319 if (phy[PORT_0].addr & 0x1) {
12320 phy_blk[PORT_0] = &(phy[PORT_1]);
12321 phy_blk[PORT_1] = &(phy[PORT_0]);
12323 phy_blk[PORT_0] = &(phy[PORT_0]);
12324 phy_blk[PORT_1] = &(phy[PORT_1]);
12326 /* PART2 - Download firmware to both phys */
12327 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12328 if (CHIP_IS_E1x(bp))
12329 port_of_path = port;
12332 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12333 phy_blk[port]->addr);
12334 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12337 /* Disable PHY transmitter output */
12338 bnx2x_cl45_write(bp, phy_blk[port],
12340 MDIO_PMA_REG_TX_DISABLE, 1);
12346 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12347 u32 shmem_base_path[],
12348 u32 shmem2_base_path[],
12353 struct bnx2x_phy phy;
12354 u32 shmem_base, shmem2_base, cnt;
12358 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12359 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12361 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12362 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12364 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12365 /* This PHY is for E2 and E3. */
12366 shmem_base = shmem_base_path[port];
12367 shmem2_base = shmem2_base_path[port];
12368 /* Extract the ext phy address for the port */
12369 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12372 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12376 /* Wait for FW completing its initialization. */
12377 for (cnt = 0; cnt < 1000; cnt++) {
12378 bnx2x_cl45_read(bp, &phy,
12380 MDIO_PMA_REG_CTRL, &val);
12381 if (!(val & (1<<15)))
12387 "84833 Cmn reset timeout (%d)\n", port);
12389 /* Put the port in super isolate mode. */
12390 bnx2x_cl45_read(bp, &phy,
12392 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12393 val |= MDIO_84833_SUPER_ISOLATE;
12394 bnx2x_cl45_write(bp, &phy,
12396 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12403 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12404 u32 shmem2_base_path[], u8 phy_index,
12405 u32 ext_phy_type, u32 chip_id)
12409 switch (ext_phy_type) {
12410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12411 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12413 phy_index, chip_id);
12415 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12416 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12417 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12418 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12420 phy_index, chip_id);
12423 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12425 * GPIO1 affects both ports, so there's need to pull
12426 * it for single port alone
12428 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12430 phy_index, chip_id);
12432 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12434 * GPIO3's are linked, and so both need to be toggled
12435 * to obtain required 2us pulse.
12437 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12439 phy_index, chip_id);
12441 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12446 "ext_phy 0x%x common init not required\n",
12452 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12458 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12459 u32 shmem2_base_path[], u32 chip_id)
12464 u32 ext_phy_type, ext_phy_config;
12465 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12466 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12467 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12468 if (CHIP_IS_E3(bp)) {
12470 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12471 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12473 /* Check if common init was already done */
12474 phy_ver = REG_RD(bp, shmem_base_path[0] +
12475 offsetof(struct shmem_region,
12476 port_mb[PORT_0].ext_phy_fw_version));
12478 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12483 /* Read the ext_phy_type for arbitrary port(0) */
12484 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12486 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12487 shmem_base_path[0],
12489 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12490 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12492 phy_index, ext_phy_type,
12498 static void bnx2x_check_over_curr(struct link_params *params,
12499 struct link_vars *vars)
12501 struct bnx2x *bp = params->bp;
12503 u8 port = params->port;
12506 cfg_pin = (REG_RD(bp, params->shmem_base +
12507 offsetof(struct shmem_region,
12508 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12509 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12510 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12512 /* Ignore check if no external input PIN available */
12513 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12517 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12518 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12519 " been detected and the power to "
12520 "that SFP+ module has been removed"
12521 " to prevent failure of the card."
12522 " Please remove the SFP+ module and"
12523 " restart the system to clear this"
12526 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12529 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12532 static void bnx2x_analyze_link_error(struct link_params *params,
12533 struct link_vars *vars, u32 lss_status)
12535 struct bnx2x *bp = params->bp;
12536 /* Compare new value with previous value */
12538 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12540 if ((lss_status ^ half_open_conn) == 0)
12543 /* If values differ */
12544 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12545 half_open_conn, lss_status);
12548 * a. Update shmem->link_status accordingly
12549 * b. Update link_vars->link_up
12552 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12553 vars->link_status &= ~LINK_STATUS_LINK_UP;
12555 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12557 * Set LED mode to off since the PHY doesn't know about these
12560 led_mode = LED_MODE_OFF;
12562 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12563 vars->link_status |= LINK_STATUS_LINK_UP;
12565 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12566 led_mode = LED_MODE_OPER;
12568 /* Update the LED according to the link state */
12569 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12571 /* Update link status in the shared memory */
12572 bnx2x_update_mng(params, vars->link_status);
12574 /* C. Trigger General Attention */
12575 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12576 bnx2x_notify_link_changed(bp);
12579 /******************************************************************************
12581 * This function checks for half opened connection change indication.
12582 * When such change occurs, it calls the bnx2x_analyze_link_error
12583 * to check if Remote Fault is set or cleared. Reception of remote fault
12584 * status message in the MAC indicates that the peer's MAC has detected
12585 * a fault, for example, due to break in the TX side of fiber.
12587 ******************************************************************************/
12588 static void bnx2x_check_half_open_conn(struct link_params *params,
12589 struct link_vars *vars)
12591 struct bnx2x *bp = params->bp;
12592 u32 lss_status = 0;
12594 /* In case link status is physically up @ 10G do */
12595 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12598 if (CHIP_IS_E3(bp) &&
12599 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12600 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12601 /* Check E3 XMAC */
12603 * Note that link speed cannot be queried here, since it may be
12604 * zero while link is down. In case UMAC is active, LSS will
12605 * simply not be set
12607 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12609 /* Clear stick bits (Requires rising edge) */
12610 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12611 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12612 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12613 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12614 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12617 bnx2x_analyze_link_error(params, vars, lss_status);
12618 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12619 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12620 /* Check E1X / E2 BMAC */
12621 u32 lss_status_reg;
12623 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12624 NIG_REG_INGRESS_BMAC0_MEM;
12625 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12626 if (CHIP_IS_E2(bp))
12627 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12629 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12631 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12632 lss_status = (wb_data[0] > 0);
12634 bnx2x_analyze_link_error(params, vars, lss_status);
12638 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12640 struct bnx2x *bp = params->bp;
12642 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12643 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12644 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
12645 bnx2x_check_half_open_conn(params, vars);
12650 if (CHIP_IS_E3(bp)) {
12651 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
12652 bnx2x_set_aer_mmd(params, phy);
12653 bnx2x_check_over_curr(params, vars);
12654 bnx2x_warpcore_config_runtime(phy, params, vars);
12659 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12662 struct bnx2x_phy phy;
12663 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12665 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12667 DP(NETIF_MSG_LINK, "populate phy failed\n");
12671 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12677 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12682 u8 phy_index, fan_failure_det_req = 0;
12683 struct bnx2x_phy phy;
12684 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12686 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12689 DP(NETIF_MSG_LINK, "populate phy failed\n");
12692 fan_failure_det_req |= (phy.flags &
12693 FLAGS_FAN_FAILURE_DET_REQ);
12695 return fan_failure_det_req;
12698 void bnx2x_hw_reset_phy(struct link_params *params)
12701 struct bnx2x *bp = params->bp;
12702 bnx2x_update_mng(params, 0);
12703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12704 (NIG_MASK_XGXS0_LINK_STATUS |
12705 NIG_MASK_XGXS0_LINK10G |
12706 NIG_MASK_SERDES0_LINK_STATUS |
12709 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12711 if (params->phy[phy_index].hw_reset) {
12712 params->phy[phy_index].hw_reset(
12713 ¶ms->phy[phy_index],
12715 params->phy[phy_index] = phy_null;
12720 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12721 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12724 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12726 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12727 if (CHIP_IS_E3(bp)) {
12728 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12735 struct bnx2x_phy phy;
12736 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12738 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12739 shmem2_base, port, &phy)
12741 DP(NETIF_MSG_LINK, "populate phy failed\n");
12744 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12745 gpio_num = MISC_REGISTERS_GPIO_3;
12752 if (gpio_num == 0xff)
12755 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12756 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12758 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12759 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12760 gpio_port ^= (swap_val && swap_override);
12762 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12763 (gpio_num + (gpio_port << 2));
12765 sync_offset = shmem_base +
12766 offsetof(struct shmem_region,
12767 dev_info.port_hw_config[port].aeu_int_mask);
12768 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12770 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12771 gpio_num, gpio_port, vars->aeu_int_mask);
12774 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12776 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12778 /* Open appropriate AEU for interrupts */
12779 aeu_mask = REG_RD(bp, offset);
12780 aeu_mask |= vars->aeu_int_mask;
12781 REG_WR(bp, offset, aeu_mask);
12783 /* Enable the GPIO to trigger interrupt */
12784 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12785 val |= 1 << (gpio_num + (gpio_port << 2));
12786 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);