c05cb159c7726eff1286660aa78716ad49a1aa91
[linux-2.6.git] / drivers / net / enc28j60.c
1 /*
2  * Microchip ENC28J60 ethernet driver (MAC + PHY)
3  *
4  * Copyright (C) 2007 Eurek srl
5  * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6  * based on enc28j60.c written by David Anders for 2.4 kernel version
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14  */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/tcp.h>
29 #include <linux/skbuff.h>
30 #include <linux/delay.h>
31 #include <linux/spi/spi.h>
32
33 #include "enc28j60_hw.h"
34
35 #define DRV_NAME        "enc28j60"
36 #define DRV_VERSION     "1.01"
37
38 #define SPI_OPLEN       1
39
40 #define ENC28J60_MSG_DEFAULT    \
41         (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
42
43 /* Buffer size required for the largest SPI transfer (i.e., reading a
44  * frame). */
45 #define SPI_TRANSFER_BUF_LEN    (4 + MAX_FRAMELEN)
46
47 #define TX_TIMEOUT      (4 * HZ)
48
49 /* Max TX retries in case of collision as suggested by errata datasheet */
50 #define MAX_TX_RETRYCOUNT       16
51
52 enum {
53         RXFILTER_NORMAL,
54         RXFILTER_MULTI,
55         RXFILTER_PROMISC
56 };
57
58 /* Driver local data */
59 struct enc28j60_net {
60         struct net_device *netdev;
61         struct spi_device *spi;
62         struct mutex lock;
63         struct sk_buff *tx_skb;
64         struct work_struct tx_work;
65         struct work_struct irq_work;
66         struct work_struct setrx_work;
67         struct work_struct restart_work;
68         u8 bank;                /* current register bank selected */
69         u16 next_pk_ptr;        /* next packet pointer within FIFO */
70         u16 max_pk_counter;     /* statistics: max packet counter */
71         u16 tx_retry_count;
72         bool hw_enable;
73         bool full_duplex;
74         int rxfilter;
75         u32 msg_enable;
76         u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
77 };
78
79 /* use ethtool to change the level for any given device */
80 static struct {
81         u32 msg_enable;
82 } debug = { -1 };
83
84 /*
85  * SPI read buffer
86  * wait for the SPI transfer and copy received data to destination
87  */
88 static int
89 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
90 {
91         u8 *rx_buf = priv->spi_transfer_buf + 4;
92         u8 *tx_buf = priv->spi_transfer_buf;
93         struct spi_transfer t = {
94                 .tx_buf = tx_buf,
95                 .rx_buf = rx_buf,
96                 .len = SPI_OPLEN + len,
97         };
98         struct spi_message msg;
99         int ret;
100
101         tx_buf[0] = ENC28J60_READ_BUF_MEM;
102         tx_buf[1] = tx_buf[2] = tx_buf[3] = 0;  /* don't care */
103
104         spi_message_init(&msg);
105         spi_message_add_tail(&t, &msg);
106         ret = spi_sync(priv->spi, &msg);
107         if (ret == 0) {
108                 memcpy(data, &rx_buf[SPI_OPLEN], len);
109                 ret = msg.status;
110         }
111         if (ret && netif_msg_drv(priv))
112                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
113                         __FUNCTION__, ret);
114
115         return ret;
116 }
117
118 /*
119  * SPI write buffer
120  */
121 static int spi_write_buf(struct enc28j60_net *priv, int len,
122                          const u8 *data)
123 {
124         int ret;
125
126         if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
127                 ret = -EINVAL;
128         else {
129                 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130                 memcpy(&priv->spi_transfer_buf[1], data, len);
131                 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132                 if (ret && netif_msg_drv(priv))
133                         printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
134                                 __FUNCTION__, ret);
135         }
136         return ret;
137 }
138
139 /*
140  * basic SPI read operation
141  */
142 static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
143                            u8 addr)
144 {
145         u8 tx_buf[2];
146         u8 rx_buf[4];
147         u8 val = 0;
148         int ret;
149         int slen = SPI_OPLEN;
150
151         /* do dummy read if needed */
152         if (addr & SPRD_MASK)
153                 slen++;
154
155         tx_buf[0] = op | (addr & ADDR_MASK);
156         ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
157         if (ret)
158                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
159                         __FUNCTION__, ret);
160         else
161                 val = rx_buf[slen - 1];
162
163         return val;
164 }
165
166 /*
167  * basic SPI write operation
168  */
169 static int spi_write_op(struct enc28j60_net *priv, u8 op,
170                         u8 addr, u8 val)
171 {
172         int ret;
173
174         priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175         priv->spi_transfer_buf[1] = val;
176         ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177         if (ret && netif_msg_drv(priv))
178                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
179                         __FUNCTION__, ret);
180         return ret;
181 }
182
183 static void enc28j60_soft_reset(struct enc28j60_net *priv)
184 {
185         if (netif_msg_hw(priv))
186                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
187
188         spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
189         /* Errata workaround #1, CLKRDY check is unreliable,
190          * delay at least 1 mS instead */
191         udelay(2000);
192 }
193
194 /*
195  * select the current register bank if necessary
196  */
197 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
198 {
199         if ((addr & BANK_MASK) != priv->bank) {
200                 u8 b = (addr & BANK_MASK) >> 5;
201
202                 if (b != (ECON1_BSEL1 | ECON1_BSEL0))
203                         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
204                                      ECON1_BSEL1 | ECON1_BSEL0);
205                 if (b != 0)
206                         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b);
207                 priv->bank = (addr & BANK_MASK);
208         }
209 }
210
211 /*
212  * Register access routines through the SPI bus.
213  * Every register access comes in two flavours:
214  * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
215  *   atomically more than one register
216  * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
217  *
218  * Some registers can be accessed through the bit field clear and
219  * bit field set to avoid a read modify write cycle.
220  */
221
222 /*
223  * Register bit field Set
224  */
225 static void nolock_reg_bfset(struct enc28j60_net *priv,
226                                       u8 addr, u8 mask)
227 {
228         enc28j60_set_bank(priv, addr);
229         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
230 }
231
232 static void locked_reg_bfset(struct enc28j60_net *priv,
233                                       u8 addr, u8 mask)
234 {
235         mutex_lock(&priv->lock);
236         nolock_reg_bfset(priv, addr, mask);
237         mutex_unlock(&priv->lock);
238 }
239
240 /*
241  * Register bit field Clear
242  */
243 static void nolock_reg_bfclr(struct enc28j60_net *priv,
244                                       u8 addr, u8 mask)
245 {
246         enc28j60_set_bank(priv, addr);
247         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
248 }
249
250 static void locked_reg_bfclr(struct enc28j60_net *priv,
251                                       u8 addr, u8 mask)
252 {
253         mutex_lock(&priv->lock);
254         nolock_reg_bfclr(priv, addr, mask);
255         mutex_unlock(&priv->lock);
256 }
257
258 /*
259  * Register byte read
260  */
261 static int nolock_regb_read(struct enc28j60_net *priv,
262                                      u8 address)
263 {
264         enc28j60_set_bank(priv, address);
265         return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
266 }
267
268 static int locked_regb_read(struct enc28j60_net *priv,
269                                      u8 address)
270 {
271         int ret;
272
273         mutex_lock(&priv->lock);
274         ret = nolock_regb_read(priv, address);
275         mutex_unlock(&priv->lock);
276
277         return ret;
278 }
279
280 /*
281  * Register word read
282  */
283 static int nolock_regw_read(struct enc28j60_net *priv,
284                                      u8 address)
285 {
286         int rl, rh;
287
288         enc28j60_set_bank(priv, address);
289         rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
290         rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
291
292         return (rh << 8) | rl;
293 }
294
295 static int locked_regw_read(struct enc28j60_net *priv,
296                                      u8 address)
297 {
298         int ret;
299
300         mutex_lock(&priv->lock);
301         ret = nolock_regw_read(priv, address);
302         mutex_unlock(&priv->lock);
303
304         return ret;
305 }
306
307 /*
308  * Register byte write
309  */
310 static void nolock_regb_write(struct enc28j60_net *priv,
311                                        u8 address, u8 data)
312 {
313         enc28j60_set_bank(priv, address);
314         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
315 }
316
317 static void locked_regb_write(struct enc28j60_net *priv,
318                                        u8 address, u8 data)
319 {
320         mutex_lock(&priv->lock);
321         nolock_regb_write(priv, address, data);
322         mutex_unlock(&priv->lock);
323 }
324
325 /*
326  * Register word write
327  */
328 static void nolock_regw_write(struct enc28j60_net *priv,
329                                        u8 address, u16 data)
330 {
331         enc28j60_set_bank(priv, address);
332         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
333         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
334                      (u8) (data >> 8));
335 }
336
337 static void locked_regw_write(struct enc28j60_net *priv,
338                                        u8 address, u16 data)
339 {
340         mutex_lock(&priv->lock);
341         nolock_regw_write(priv, address, data);
342         mutex_unlock(&priv->lock);
343 }
344
345 /*
346  * Buffer memory read
347  * Select the starting address and execute a SPI buffer read
348  */
349 static void enc28j60_mem_read(struct enc28j60_net *priv,
350                                      u16 addr, int len, u8 *data)
351 {
352         mutex_lock(&priv->lock);
353         nolock_regw_write(priv, ERDPTL, addr);
354 #ifdef CONFIG_ENC28J60_WRITEVERIFY
355         if (netif_msg_drv(priv)) {
356                 u16 reg;
357                 reg = nolock_regw_read(priv, ERDPTL);
358                 if (reg != addr)
359                         printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
360                                 "(0x%04x - 0x%04x)\n", __FUNCTION__, reg, addr);
361         }
362 #endif
363         spi_read_buf(priv, len, data);
364         mutex_unlock(&priv->lock);
365 }
366
367 /*
368  * Write packet to enc28j60 TX buffer memory
369  */
370 static void
371 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
372 {
373         mutex_lock(&priv->lock);
374         /* Set the write pointer to start of transmit buffer area */
375         nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
376 #ifdef CONFIG_ENC28J60_WRITEVERIFY
377         if (netif_msg_drv(priv)) {
378                 u16 reg;
379                 reg = nolock_regw_read(priv, EWRPTL);
380                 if (reg != TXSTART_INIT)
381                         printk(KERN_DEBUG DRV_NAME
382                                 ": %s() ERWPT:0x%04x != 0x%04x\n",
383                                 __FUNCTION__, reg, TXSTART_INIT);
384         }
385 #endif
386         /* Set the TXND pointer to correspond to the packet size given */
387         nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
388         /* write per-packet control byte */
389         spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
390         if (netif_msg_hw(priv))
391                 printk(KERN_DEBUG DRV_NAME
392                         ": %s() after control byte ERWPT:0x%04x\n",
393                         __FUNCTION__, nolock_regw_read(priv, EWRPTL));
394         /* copy the packet into the transmit buffer */
395         spi_write_buf(priv, len, data);
396         if (netif_msg_hw(priv))
397                 printk(KERN_DEBUG DRV_NAME
398                          ": %s() after write packet ERWPT:0x%04x, len=%d\n",
399                          __FUNCTION__, nolock_regw_read(priv, EWRPTL), len);
400         mutex_unlock(&priv->lock);
401 }
402
403 static unsigned long msec20_to_jiffies;
404
405 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
406 {
407         unsigned long timeout = jiffies + msec20_to_jiffies;
408
409         /* 20 msec timeout read */
410         while ((nolock_regb_read(priv, reg) & mask) != val) {
411                 if (time_after(jiffies, timeout)) {
412                         if (netif_msg_drv(priv))
413                                 dev_dbg(&priv->spi->dev,
414                                         "reg %02x ready timeout!\n", reg);
415                         return -ETIMEDOUT;
416                 }
417                 cpu_relax();
418         }
419         return 0;
420 }
421
422 /*
423  * Wait until the PHY operation is complete.
424  */
425 static int wait_phy_ready(struct enc28j60_net *priv)
426 {
427         return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
428 }
429
430 /*
431  * PHY register read
432  * PHY registers are not accessed directly, but through the MII
433  */
434 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
435 {
436         u16 ret;
437
438         mutex_lock(&priv->lock);
439         /* set the PHY register address */
440         nolock_regb_write(priv, MIREGADR, address);
441         /* start the register read operation */
442         nolock_regb_write(priv, MICMD, MICMD_MIIRD);
443         /* wait until the PHY read completes */
444         wait_phy_ready(priv);
445         /* quit reading */
446         nolock_regb_write(priv, MICMD, 0x00);
447         /* return the data */
448         ret  = nolock_regw_read(priv, MIRDL);
449         mutex_unlock(&priv->lock);
450
451         return ret;
452 }
453
454 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
455 {
456         int ret;
457
458         mutex_lock(&priv->lock);
459         /* set the PHY register address */
460         nolock_regb_write(priv, MIREGADR, address);
461         /* write the PHY data */
462         nolock_regw_write(priv, MIWRL, data);
463         /* wait until the PHY write completes and return */
464         ret = wait_phy_ready(priv);
465         mutex_unlock(&priv->lock);
466
467         return ret;
468 }
469
470 /*
471  * Program the hardware MAC address from dev->dev_addr.
472  */
473 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
474 {
475         int ret;
476         struct enc28j60_net *priv = netdev_priv(ndev);
477
478         mutex_lock(&priv->lock);
479         if (!priv->hw_enable) {
480                 if (netif_msg_drv(priv)) {
481                         DECLARE_MAC_BUF(mac);
482                         printk(KERN_INFO DRV_NAME
483                                 ": %s: Setting MAC address to %s\n",
484                                 ndev->name, print_mac(mac, ndev->dev_addr));
485                 }
486                 /* NOTE: MAC address in ENC28J60 is byte-backward */
487                 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
488                 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
489                 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
490                 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
491                 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
492                 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
493                 ret = 0;
494         } else {
495                 if (netif_msg_drv(priv))
496                         printk(KERN_DEBUG DRV_NAME
497                                 ": %s() Hardware must be disabled to set "
498                                 "Mac address\n", __FUNCTION__);
499                 ret = -EBUSY;
500         }
501         mutex_unlock(&priv->lock);
502         return ret;
503 }
504
505 /*
506  * Store the new hardware address in dev->dev_addr, and update the MAC.
507  */
508 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
509 {
510         struct sockaddr *address = addr;
511
512         if (netif_running(dev))
513                 return -EBUSY;
514         if (!is_valid_ether_addr(address->sa_data))
515                 return -EADDRNOTAVAIL;
516
517         memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
518         return enc28j60_set_hw_macaddr(dev);
519 }
520
521 /*
522  * Debug routine to dump useful register contents
523  */
524 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
525 {
526         mutex_lock(&priv->lock);
527         printk(KERN_DEBUG DRV_NAME " %s\n"
528                 "HwRevID: 0x%02x\n"
529                 "Cntrl: ECON1 ECON2 ESTAT  EIR  EIE\n"
530                 "       0x%02x  0x%02x  0x%02x  0x%02x  0x%02x\n"
531                 "MAC  : MACON1 MACON3 MACON4\n"
532                 "       0x%02x   0x%02x   0x%02x\n"
533                 "Rx   : ERXST  ERXND  ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
534                 "       0x%04x 0x%04x 0x%04x  0x%04x  "
535                 "0x%02x    0x%02x    0x%04x\n"
536                 "Tx   : ETXST  ETXND  MACLCON1 MACLCON2 MAPHSUP\n"
537                 "       0x%04x 0x%04x 0x%02x     0x%02x     0x%02x\n",
538                 msg, nolock_regb_read(priv, EREVID),
539                 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
540                 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
541                 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
542                 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
543                 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
544                 nolock_regw_read(priv, ERXWRPTL),
545                 nolock_regw_read(priv, ERXRDPTL),
546                 nolock_regb_read(priv, ERXFCON),
547                 nolock_regb_read(priv, EPKTCNT),
548                 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
549                 nolock_regw_read(priv, ETXNDL),
550                 nolock_regb_read(priv, MACLCON1),
551                 nolock_regb_read(priv, MACLCON2),
552                 nolock_regb_read(priv, MAPHSUP));
553         mutex_unlock(&priv->lock);
554 }
555
556 /*
557  * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
558  */
559 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
560 {
561         u16 erxrdpt;
562
563         if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
564                 erxrdpt = end;
565         else
566                 erxrdpt = next_packet_ptr - 1;
567
568         return erxrdpt;
569 }
570
571 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
572 {
573         u16 erxrdpt;
574
575         if (start > 0x1FFF || end > 0x1FFF || start > end) {
576                 if (netif_msg_drv(priv))
577                         printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
578                                 "bad parameters!\n", __FUNCTION__, start, end);
579                 return;
580         }
581         /* set receive buffer start + end */
582         priv->next_pk_ptr = start;
583         nolock_regw_write(priv, ERXSTL, start);
584         erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
585         nolock_regw_write(priv, ERXRDPTL, erxrdpt);
586         nolock_regw_write(priv, ERXNDL, end);
587 }
588
589 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
590 {
591         if (start > 0x1FFF || end > 0x1FFF || start > end) {
592                 if (netif_msg_drv(priv))
593                         printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
594                                 "bad parameters!\n", __FUNCTION__, start, end);
595                 return;
596         }
597         /* set transmit buffer start + end */
598         nolock_regw_write(priv, ETXSTL, start);
599         nolock_regw_write(priv, ETXNDL, end);
600 }
601
602 /*
603  * Low power mode shrinks power consumption about 100x, so we'd like
604  * the chip to be in that mode whenever it's inactive.  (However, we
605  * can't stay in lowpower mode during suspend with WOL active.)
606  */
607 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
608 {
609         if (netif_msg_drv(priv))
610                 dev_dbg(&priv->spi->dev, "%s power...\n",
611                                 is_low ? "low" : "high");
612
613         mutex_lock(&priv->lock);
614         if (is_low) {
615                 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
616                 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
617                 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
618                 /* ECON2_VRPS was set during initialization */
619                 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
620         } else {
621                 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
622                 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
623                 /* caller sets ECON1_RXEN */
624         }
625         mutex_unlock(&priv->lock);
626 }
627
628 static int enc28j60_hw_init(struct enc28j60_net *priv)
629 {
630         u8 reg;
631
632         if (netif_msg_drv(priv))
633                 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __FUNCTION__,
634                         priv->full_duplex ? "FullDuplex" : "HalfDuplex");
635
636         mutex_lock(&priv->lock);
637         /* first reset the chip */
638         enc28j60_soft_reset(priv);
639         /* Clear ECON1 */
640         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
641         priv->bank = 0;
642         priv->hw_enable = false;
643         priv->tx_retry_count = 0;
644         priv->max_pk_counter = 0;
645         priv->rxfilter = RXFILTER_NORMAL;
646         /* enable address auto increment and voltage regulator powersave */
647         nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
648
649         nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
650         nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
651         mutex_unlock(&priv->lock);
652
653         /*
654          * Check the RevID.
655          * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
656          * damaged
657          */
658         reg = locked_regb_read(priv, EREVID);
659         if (netif_msg_drv(priv))
660                 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
661         if (reg == 0x00 || reg == 0xff) {
662                 if (netif_msg_drv(priv))
663                         printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
664                                 __FUNCTION__, reg);
665                 return 0;
666         }
667
668         /* default filter mode: (unicast OR broadcast) AND crc valid */
669         locked_regb_write(priv, ERXFCON,
670                             ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
671
672         /* enable MAC receive */
673         locked_regb_write(priv, MACON1,
674                             MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
675         /* enable automatic padding and CRC operations */
676         if (priv->full_duplex) {
677                 locked_regb_write(priv, MACON3,
678                                     MACON3_PADCFG0 | MACON3_TXCRCEN |
679                                     MACON3_FRMLNEN | MACON3_FULDPX);
680                 /* set inter-frame gap (non-back-to-back) */
681                 locked_regb_write(priv, MAIPGL, 0x12);
682                 /* set inter-frame gap (back-to-back) */
683                 locked_regb_write(priv, MABBIPG, 0x15);
684         } else {
685                 locked_regb_write(priv, MACON3,
686                                     MACON3_PADCFG0 | MACON3_TXCRCEN |
687                                     MACON3_FRMLNEN);
688                 locked_regb_write(priv, MACON4, 1 << 6);        /* DEFER bit */
689                 /* set inter-frame gap (non-back-to-back) */
690                 locked_regw_write(priv, MAIPGL, 0x0C12);
691                 /* set inter-frame gap (back-to-back) */
692                 locked_regb_write(priv, MABBIPG, 0x12);
693         }
694         /*
695          * MACLCON1 (default)
696          * MACLCON2 (default)
697          * Set the maximum packet size which the controller will accept
698          */
699         locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
700
701         /* Configure LEDs */
702         if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
703                 return 0;
704
705         if (priv->full_duplex) {
706                 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
707                         return 0;
708                 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
709                         return 0;
710         } else {
711                 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
712                         return 0;
713                 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
714                         return 0;
715         }
716         if (netif_msg_hw(priv))
717                 enc28j60_dump_regs(priv, "Hw initialized.");
718
719         return 1;
720 }
721
722 static void enc28j60_hw_enable(struct enc28j60_net *priv)
723 {
724         /* enable interrupts */
725         if (netif_msg_hw(priv))
726                 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
727                         __FUNCTION__);
728
729         enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
730
731         mutex_lock(&priv->lock);
732         nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
733                          EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
734         nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
735                           EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
736
737         /* enable receive logic */
738         nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
739         priv->hw_enable = true;
740         mutex_unlock(&priv->lock);
741 }
742
743 static void enc28j60_hw_disable(struct enc28j60_net *priv)
744 {
745         mutex_lock(&priv->lock);
746         /* disable interrutps and packet reception */
747         nolock_regb_write(priv, EIE, 0x00);
748         nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
749         priv->hw_enable = false;
750         mutex_unlock(&priv->lock);
751 }
752
753 static int
754 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
755 {
756         struct enc28j60_net *priv = netdev_priv(ndev);
757         int ret = 0;
758
759         if (!priv->hw_enable) {
760                 /* link is in low power mode now; duplex setting
761                  * will take effect on next enc28j60_hw_init().
762                  */
763                 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
764                         priv->full_duplex = (duplex == DUPLEX_FULL);
765                 else {
766                         if (netif_msg_link(priv))
767                                 dev_warn(&ndev->dev,
768                                         "unsupported link setting\n");
769                         ret = -EOPNOTSUPP;
770                 }
771         } else {
772                 if (netif_msg_link(priv))
773                         dev_warn(&ndev->dev, "Warning: hw must be disabled "
774                                 "to set link mode\n");
775                 ret = -EBUSY;
776         }
777         return ret;
778 }
779
780 /*
781  * Read the Transmit Status Vector
782  */
783 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
784 {
785         int endptr;
786
787         endptr = locked_regw_read(priv, ETXNDL);
788         if (netif_msg_hw(priv))
789                 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
790                          endptr + 1);
791         enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
792 }
793
794 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
795                                 u8 tsv[TSV_SIZE])
796 {
797         u16 tmp1, tmp2;
798
799         printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
800         tmp1 = tsv[1];
801         tmp1 <<= 8;
802         tmp1 |= tsv[0];
803
804         tmp2 = tsv[5];
805         tmp2 <<= 8;
806         tmp2 |= tsv[4];
807
808         printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
809                 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
810         printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
811                 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
812                 TSV_GETBIT(tsv, TSV_TXCRCERROR),
813                 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
814                 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
815         printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
816                 "PacketDefer: %d, ExDefer: %d\n",
817                 TSV_GETBIT(tsv, TSV_TXMULTICAST),
818                 TSV_GETBIT(tsv, TSV_TXBROADCAST),
819                 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
820                 TSV_GETBIT(tsv, TSV_TXEXDEFER));
821         printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
822                  "Giant: %d, Underrun: %d\n",
823                  TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
824                  TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
825                  TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
826         printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
827                  "BackPressApp: %d, VLanTagFrame: %d\n",
828                  TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
829                  TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
830                  TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
831                  TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
832 }
833
834 /*
835  * Receive Status vector
836  */
837 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
838                               u16 pk_ptr, int len, u16 sts)
839 {
840         printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
841                 msg, pk_ptr);
842         printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
843                  RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
844         printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
845                  " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
846                  RSV_GETBIT(sts, RSV_CRCERROR),
847                  RSV_GETBIT(sts, RSV_LENCHECKERR),
848                  RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
849         printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
850                  "LongDropEvent: %d, CarrierEvent: %d\n",
851                  RSV_GETBIT(sts, RSV_RXMULTICAST),
852                  RSV_GETBIT(sts, RSV_RXBROADCAST),
853                  RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
854                  RSV_GETBIT(sts, RSV_CARRIEREV));
855         printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
856                  " UnknownOp: %d, VLanTagFrame: %d\n",
857                  RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
858                  RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
859                  RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
860                  RSV_GETBIT(sts, RSV_RXTYPEVLAN));
861 }
862
863 static void dump_packet(const char *msg, int len, const char *data)
864 {
865         printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
866         print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
867                         data, len, true);
868 }
869
870 /*
871  * Hardware receive function.
872  * Read the buffer memory, update the FIFO pointer to free the buffer,
873  * check the status vector and decrement the packet counter.
874  */
875 static void enc28j60_hw_rx(struct net_device *ndev)
876 {
877         struct enc28j60_net *priv = netdev_priv(ndev);
878         struct sk_buff *skb = NULL;
879         u16 erxrdpt, next_packet, rxstat;
880         u8 rsv[RSV_SIZE];
881         int len;
882
883         if (netif_msg_rx_status(priv))
884                 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
885                         priv->next_pk_ptr);
886
887         if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
888                 if (netif_msg_rx_err(priv))
889                         dev_err(&ndev->dev,
890                                 "%s() Invalid packet address!! 0x%04x\n",
891                                 __FUNCTION__, priv->next_pk_ptr);
892                 /* packet address corrupted: reset RX logic */
893                 mutex_lock(&priv->lock);
894                 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
895                 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
896                 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
897                 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
898                 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
899                 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
900                 mutex_unlock(&priv->lock);
901                 ndev->stats.rx_errors++;
902                 return;
903         }
904         /* Read next packet pointer and rx status vector */
905         enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
906
907         next_packet = rsv[1];
908         next_packet <<= 8;
909         next_packet |= rsv[0];
910
911         len = rsv[3];
912         len <<= 8;
913         len |= rsv[2];
914
915         rxstat = rsv[5];
916         rxstat <<= 8;
917         rxstat |= rsv[4];
918
919         if (netif_msg_rx_status(priv))
920                 enc28j60_dump_rsv(priv, __FUNCTION__, next_packet, len, rxstat);
921
922         if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
923                 if (netif_msg_rx_err(priv))
924                         dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
925                 ndev->stats.rx_errors++;
926                 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
927                         ndev->stats.rx_crc_errors++;
928                 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
929                         ndev->stats.rx_frame_errors++;
930         } else {
931                 skb = dev_alloc_skb(len + NET_IP_ALIGN);
932                 if (!skb) {
933                         if (netif_msg_rx_err(priv))
934                                 dev_err(&ndev->dev,
935                                         "out of memory for Rx'd frame\n");
936                         ndev->stats.rx_dropped++;
937                 } else {
938                         skb->dev = ndev;
939                         skb_reserve(skb, NET_IP_ALIGN);
940                         /* copy the packet from the receive buffer */
941                         enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv),
942                                         len, skb_put(skb, len));
943                         if (netif_msg_pktdata(priv))
944                                 dump_packet(__FUNCTION__, skb->len, skb->data);
945                         skb->protocol = eth_type_trans(skb, ndev);
946                         /* update statistics */
947                         ndev->stats.rx_packets++;
948                         ndev->stats.rx_bytes += len;
949                         ndev->last_rx = jiffies;
950                         netif_rx(skb);
951                 }
952         }
953         /*
954          * Move the RX read pointer to the start of the next
955          * received packet.
956          * This frees the memory we just read out
957          */
958         erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
959         if (netif_msg_hw(priv))
960                 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
961                         __FUNCTION__, erxrdpt);
962
963         mutex_lock(&priv->lock);
964         nolock_regw_write(priv, ERXRDPTL, erxrdpt);
965 #ifdef CONFIG_ENC28J60_WRITEVERIFY
966         if (netif_msg_drv(priv)) {
967                 u16 reg;
968                 reg = nolock_regw_read(priv, ERXRDPTL);
969                 if (reg != erxrdpt)
970                         printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
971                                 "error (0x%04x - 0x%04x)\n", __FUNCTION__,
972                                 reg, erxrdpt);
973         }
974 #endif
975         priv->next_pk_ptr = next_packet;
976         /* we are done with this packet, decrement the packet counter */
977         nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
978         mutex_unlock(&priv->lock);
979 }
980
981 /*
982  * Calculate free space in RxFIFO
983  */
984 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
985 {
986         int epkcnt, erxst, erxnd, erxwr, erxrd;
987         int free_space;
988
989         mutex_lock(&priv->lock);
990         epkcnt = nolock_regb_read(priv, EPKTCNT);
991         if (epkcnt >= 255)
992                 free_space = -1;
993         else {
994                 erxst = nolock_regw_read(priv, ERXSTL);
995                 erxnd = nolock_regw_read(priv, ERXNDL);
996                 erxwr = nolock_regw_read(priv, ERXWRPTL);
997                 erxrd = nolock_regw_read(priv, ERXRDPTL);
998
999                 if (erxwr > erxrd)
1000                         free_space = (erxnd - erxst) - (erxwr - erxrd);
1001                 else if (erxwr == erxrd)
1002                         free_space = (erxnd - erxst);
1003                 else
1004                         free_space = erxrd - erxwr - 1;
1005         }
1006         mutex_unlock(&priv->lock);
1007         if (netif_msg_rx_status(priv))
1008                 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1009                         __FUNCTION__, free_space);
1010         return free_space;
1011 }
1012
1013 /*
1014  * Access the PHY to determine link status
1015  */
1016 static void enc28j60_check_link_status(struct net_device *ndev)
1017 {
1018         struct enc28j60_net *priv = netdev_priv(ndev);
1019         u16 reg;
1020         int duplex;
1021
1022         reg = enc28j60_phy_read(priv, PHSTAT2);
1023         if (netif_msg_hw(priv))
1024                 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1025                         "PHSTAT2: %04x\n", __FUNCTION__,
1026                         enc28j60_phy_read(priv, PHSTAT1), reg);
1027         duplex = reg & PHSTAT2_DPXSTAT;
1028
1029         if (reg & PHSTAT2_LSTAT) {
1030                 netif_carrier_on(ndev);
1031                 if (netif_msg_ifup(priv))
1032                         dev_info(&ndev->dev, "link up - %s\n",
1033                                 duplex ? "Full duplex" : "Half duplex");
1034         } else {
1035                 if (netif_msg_ifdown(priv))
1036                         dev_info(&ndev->dev, "link down\n");
1037                 netif_carrier_off(ndev);
1038         }
1039 }
1040
1041 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1042 {
1043         struct enc28j60_net *priv = netdev_priv(ndev);
1044
1045         if (err)
1046                 ndev->stats.tx_errors++;
1047         else
1048                 ndev->stats.tx_packets++;
1049
1050         if (priv->tx_skb) {
1051                 if (!err)
1052                         ndev->stats.tx_bytes += priv->tx_skb->len;
1053                 dev_kfree_skb(priv->tx_skb);
1054                 priv->tx_skb = NULL;
1055         }
1056         locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1057         netif_wake_queue(ndev);
1058 }
1059
1060 /*
1061  * RX handler
1062  * ignore PKTIF because is unreliable! (look at the errata datasheet)
1063  * check EPKTCNT is the suggested workaround.
1064  * We don't need to clear interrupt flag, automatically done when
1065  * enc28j60_hw_rx() decrements the packet counter.
1066  * Returns how many packet processed.
1067  */
1068 static int enc28j60_rx_interrupt(struct net_device *ndev)
1069 {
1070         struct enc28j60_net *priv = netdev_priv(ndev);
1071         int pk_counter, ret;
1072
1073         pk_counter = locked_regb_read(priv, EPKTCNT);
1074         if (pk_counter && netif_msg_intr(priv))
1075                 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1076         if (pk_counter > priv->max_pk_counter) {
1077                 /* update statistics */
1078                 priv->max_pk_counter = pk_counter;
1079                 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1080                         printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1081                                 priv->max_pk_counter);
1082         }
1083         ret = pk_counter;
1084         while (pk_counter-- > 0)
1085                 enc28j60_hw_rx(ndev);
1086
1087         return ret;
1088 }
1089
1090 static void enc28j60_irq_work_handler(struct work_struct *work)
1091 {
1092         struct enc28j60_net *priv =
1093                 container_of(work, struct enc28j60_net, irq_work);
1094         struct net_device *ndev = priv->netdev;
1095         int intflags, loop;
1096
1097         if (netif_msg_intr(priv))
1098                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1099         /* disable further interrupts */
1100         locked_reg_bfclr(priv, EIE, EIE_INTIE);
1101
1102         do {
1103                 loop = 0;
1104                 intflags = locked_regb_read(priv, EIR);
1105                 /* DMA interrupt handler (not currently used) */
1106                 if ((intflags & EIR_DMAIF) != 0) {
1107                         loop++;
1108                         if (netif_msg_intr(priv))
1109                                 printk(KERN_DEBUG DRV_NAME
1110                                         ": intDMA(%d)\n", loop);
1111                         locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1112                 }
1113                 /* LINK changed handler */
1114                 if ((intflags & EIR_LINKIF) != 0) {
1115                         loop++;
1116                         if (netif_msg_intr(priv))
1117                                 printk(KERN_DEBUG DRV_NAME
1118                                         ": intLINK(%d)\n", loop);
1119                         enc28j60_check_link_status(ndev);
1120                         /* read PHIR to clear the flag */
1121                         enc28j60_phy_read(priv, PHIR);
1122                 }
1123                 /* TX complete handler */
1124                 if ((intflags & EIR_TXIF) != 0) {
1125                         bool err = false;
1126                         loop++;
1127                         if (netif_msg_intr(priv))
1128                                 printk(KERN_DEBUG DRV_NAME
1129                                         ": intTX(%d)\n", loop);
1130                         priv->tx_retry_count = 0;
1131                         if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1132                                 if (netif_msg_tx_err(priv))
1133                                         dev_err(&ndev->dev,
1134                                                 "Tx Error (aborted)\n");
1135                                 err = true;
1136                         }
1137                         if (netif_msg_tx_done(priv)) {
1138                                 u8 tsv[TSV_SIZE];
1139                                 enc28j60_read_tsv(priv, tsv);
1140                                 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1141                         }
1142                         enc28j60_tx_clear(ndev, err);
1143                         locked_reg_bfclr(priv, EIR, EIR_TXIF);
1144                 }
1145                 /* TX Error handler */
1146                 if ((intflags & EIR_TXERIF) != 0) {
1147                         u8 tsv[TSV_SIZE];
1148
1149                         loop++;
1150                         if (netif_msg_intr(priv))
1151                                 printk(KERN_DEBUG DRV_NAME
1152                                         ": intTXErr(%d)\n", loop);
1153                         locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1154                         enc28j60_read_tsv(priv, tsv);
1155                         if (netif_msg_tx_err(priv))
1156                                 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1157                         /* Reset TX logic */
1158                         mutex_lock(&priv->lock);
1159                         nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1160                         nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1161                         nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1162                         mutex_unlock(&priv->lock);
1163                         /* Transmit Late collision check for retransmit */
1164                         if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1165                                 if (netif_msg_tx_err(priv))
1166                                         printk(KERN_DEBUG DRV_NAME
1167                                                 ": LateCollision TXErr (%d)\n",
1168                                                 priv->tx_retry_count);
1169                                 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1170                                         locked_reg_bfset(priv, ECON1,
1171                                                            ECON1_TXRTS);
1172                                 else
1173                                         enc28j60_tx_clear(ndev, true);
1174                         } else
1175                                 enc28j60_tx_clear(ndev, true);
1176                         locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1177                 }
1178                 /* RX Error handler */
1179                 if ((intflags & EIR_RXERIF) != 0) {
1180                         loop++;
1181                         if (netif_msg_intr(priv))
1182                                 printk(KERN_DEBUG DRV_NAME
1183                                         ": intRXErr(%d)\n", loop);
1184                         /* Check free FIFO space to flag RX overrun */
1185                         if (enc28j60_get_free_rxfifo(priv) <= 0) {
1186                                 if (netif_msg_rx_err(priv))
1187                                         printk(KERN_DEBUG DRV_NAME
1188                                                 ": RX Overrun\n");
1189                                 ndev->stats.rx_dropped++;
1190                         }
1191                         locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1192                 }
1193                 /* RX handler */
1194                 if (enc28j60_rx_interrupt(ndev))
1195                         loop++;
1196         } while (loop);
1197
1198         /* re-enable interrupts */
1199         locked_reg_bfset(priv, EIE, EIE_INTIE);
1200         if (netif_msg_intr(priv))
1201                 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __FUNCTION__);
1202 }
1203
1204 /*
1205  * Hardware transmit function.
1206  * Fill the buffer memory and send the contents of the transmit buffer
1207  * onto the network
1208  */
1209 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1210 {
1211         if (netif_msg_tx_queued(priv))
1212                 printk(KERN_DEBUG DRV_NAME
1213                         ": Tx Packet Len:%d\n", priv->tx_skb->len);
1214
1215         if (netif_msg_pktdata(priv))
1216                 dump_packet(__FUNCTION__,
1217                             priv->tx_skb->len, priv->tx_skb->data);
1218         enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1219
1220 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1221         /* readback and verify written data */
1222         if (netif_msg_drv(priv)) {
1223                 int test_len, k;
1224                 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1225                 int okflag;
1226
1227                 test_len = priv->tx_skb->len;
1228                 if (test_len > sizeof(test_buf))
1229                         test_len = sizeof(test_buf);
1230
1231                 /* + 1 to skip control byte */
1232                 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1233                 okflag = 1;
1234                 for (k = 0; k < test_len; k++) {
1235                         if (priv->tx_skb->data[k] != test_buf[k]) {
1236                                 printk(KERN_DEBUG DRV_NAME
1237                                          ": Error, %d location differ: "
1238                                          "0x%02x-0x%02x\n", k,
1239                                          priv->tx_skb->data[k], test_buf[k]);
1240                                 okflag = 0;
1241                         }
1242                 }
1243                 if (!okflag)
1244                         printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1245                                 "verify ERROR!\n");
1246         }
1247 #endif
1248         /* set TX request flag */
1249         locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1250 }
1251
1252 static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev)
1253 {
1254         struct enc28j60_net *priv = netdev_priv(dev);
1255
1256         if (netif_msg_tx_queued(priv))
1257                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1258
1259         /* If some error occurs while trying to transmit this
1260          * packet, you should return '1' from this function.
1261          * In such a case you _may not_ do anything to the
1262          * SKB, it is still owned by the network queueing
1263          * layer when an error is returned.  This means you
1264          * may not modify any SKB fields, you may not free
1265          * the SKB, etc.
1266          */
1267         netif_stop_queue(dev);
1268
1269         /* save the timestamp */
1270         priv->netdev->trans_start = jiffies;
1271         /* Remember the skb for deferred processing */
1272         priv->tx_skb = skb;
1273         schedule_work(&priv->tx_work);
1274
1275         return 0;
1276 }
1277
1278 static void enc28j60_tx_work_handler(struct work_struct *work)
1279 {
1280         struct enc28j60_net *priv =
1281                 container_of(work, struct enc28j60_net, tx_work);
1282
1283         /* actual delivery of data */
1284         enc28j60_hw_tx(priv);
1285 }
1286
1287 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1288 {
1289         struct enc28j60_net *priv = dev_id;
1290
1291         /*
1292          * Can't do anything in interrupt context because we need to
1293          * block (spi_sync() is blocking) so fire of the interrupt
1294          * handling workqueue.
1295          * Remember that we access enc28j60 registers through SPI bus
1296          * via spi_sync() call.
1297          */
1298         schedule_work(&priv->irq_work);
1299
1300         return IRQ_HANDLED;
1301 }
1302
1303 static void enc28j60_tx_timeout(struct net_device *ndev)
1304 {
1305         struct enc28j60_net *priv = netdev_priv(ndev);
1306
1307         if (netif_msg_timer(priv))
1308                 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1309
1310         ndev->stats.tx_errors++;
1311         /* can't restart safely under softirq */
1312         schedule_work(&priv->restart_work);
1313 }
1314
1315 /*
1316  * Open/initialize the board. This is called (in the current kernel)
1317  * sometime after booting when the 'ifconfig' program is run.
1318  *
1319  * This routine should set everything up anew at each open, even
1320  * registers that "should" only need to be set once at boot, so that
1321  * there is non-reboot way to recover if something goes wrong.
1322  */
1323 static int enc28j60_net_open(struct net_device *dev)
1324 {
1325         struct enc28j60_net *priv = netdev_priv(dev);
1326
1327         if (netif_msg_drv(priv))
1328                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1329
1330         if (!is_valid_ether_addr(dev->dev_addr)) {
1331                 if (netif_msg_ifup(priv)) {
1332                         DECLARE_MAC_BUF(mac);
1333                         dev_err(&dev->dev, "invalid MAC address %s\n",
1334                                 print_mac(mac, dev->dev_addr));
1335                 }
1336                 return -EADDRNOTAVAIL;
1337         }
1338         /* Reset the hardware here (and take it out of low power mode) */
1339         enc28j60_lowpower(priv, false);
1340         enc28j60_hw_disable(priv);
1341         if (!enc28j60_hw_init(priv)) {
1342                 if (netif_msg_ifup(priv))
1343                         dev_err(&dev->dev, "hw_reset() failed\n");
1344                 return -EINVAL;
1345         }
1346         /* Update the MAC address (in case user has changed it) */
1347         enc28j60_set_hw_macaddr(dev);
1348         /* Enable interrupts */
1349         enc28j60_hw_enable(priv);
1350         /* check link status */
1351         enc28j60_check_link_status(dev);
1352         /* We are now ready to accept transmit requests from
1353          * the queueing layer of the networking.
1354          */
1355         netif_start_queue(dev);
1356
1357         return 0;
1358 }
1359
1360 /* The inverse routine to net_open(). */
1361 static int enc28j60_net_close(struct net_device *dev)
1362 {
1363         struct enc28j60_net *priv = netdev_priv(dev);
1364
1365         if (netif_msg_drv(priv))
1366                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1367
1368         enc28j60_hw_disable(priv);
1369         enc28j60_lowpower(priv, true);
1370         netif_stop_queue(dev);
1371
1372         return 0;
1373 }
1374
1375 /*
1376  * Set or clear the multicast filter for this adapter
1377  * num_addrs == -1      Promiscuous mode, receive all packets
1378  * num_addrs == 0       Normal mode, filter out multicast packets
1379  * num_addrs > 0        Multicast mode, receive normal and MC packets
1380  */
1381 static void enc28j60_set_multicast_list(struct net_device *dev)
1382 {
1383         struct enc28j60_net *priv = netdev_priv(dev);
1384         int oldfilter = priv->rxfilter;
1385
1386         if (dev->flags & IFF_PROMISC) {
1387                 if (netif_msg_link(priv))
1388                         dev_info(&dev->dev, "promiscuous mode\n");
1389                 priv->rxfilter = RXFILTER_PROMISC;
1390         } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) {
1391                 if (netif_msg_link(priv))
1392                         dev_info(&dev->dev, "%smulticast mode\n",
1393                                 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1394                 priv->rxfilter = RXFILTER_MULTI;
1395         } else {
1396                 if (netif_msg_link(priv))
1397                         dev_info(&dev->dev, "normal mode\n");
1398                 priv->rxfilter = RXFILTER_NORMAL;
1399         }
1400
1401         if (oldfilter != priv->rxfilter)
1402                 schedule_work(&priv->setrx_work);
1403 }
1404
1405 static void enc28j60_setrx_work_handler(struct work_struct *work)
1406 {
1407         struct enc28j60_net *priv =
1408                 container_of(work, struct enc28j60_net, setrx_work);
1409
1410         if (priv->rxfilter == RXFILTER_PROMISC) {
1411                 if (netif_msg_drv(priv))
1412                         printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1413                 locked_regb_write(priv, ERXFCON, 0x00);
1414         } else if (priv->rxfilter == RXFILTER_MULTI) {
1415                 if (netif_msg_drv(priv))
1416                         printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1417                 locked_regb_write(priv, ERXFCON,
1418                                         ERXFCON_UCEN | ERXFCON_CRCEN |
1419                                         ERXFCON_BCEN | ERXFCON_MCEN);
1420         } else {
1421                 if (netif_msg_drv(priv))
1422                         printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1423                 locked_regb_write(priv, ERXFCON,
1424                                         ERXFCON_UCEN | ERXFCON_CRCEN |
1425                                         ERXFCON_BCEN);
1426         }
1427 }
1428
1429 static void enc28j60_restart_work_handler(struct work_struct *work)
1430 {
1431         struct enc28j60_net *priv =
1432                         container_of(work, struct enc28j60_net, restart_work);
1433         struct net_device *ndev = priv->netdev;
1434         int ret;
1435
1436         rtnl_lock();
1437         if (netif_running(ndev)) {
1438                 enc28j60_net_close(ndev);
1439                 ret = enc28j60_net_open(ndev);
1440                 if (unlikely(ret)) {
1441                         dev_info(&ndev->dev, " could not restart %d\n", ret);
1442                         dev_close(ndev);
1443                 }
1444         }
1445         rtnl_unlock();
1446 }
1447
1448 /* ......................... ETHTOOL SUPPORT ........................... */
1449
1450 static void
1451 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1452 {
1453         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1454         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1455         strlcpy(info->bus_info,
1456                 dev->dev.parent->bus_id, sizeof(info->bus_info));
1457 }
1458
1459 static int
1460 enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1461 {
1462         struct enc28j60_net *priv = netdev_priv(dev);
1463
1464         cmd->transceiver = XCVR_INTERNAL;
1465         cmd->supported  = SUPPORTED_10baseT_Half
1466                         | SUPPORTED_10baseT_Full
1467                         | SUPPORTED_TP;
1468         cmd->speed      = SPEED_10;
1469         cmd->duplex     = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1470         cmd->port       = PORT_TP;
1471         cmd->autoneg    = AUTONEG_DISABLE;
1472
1473         return 0;
1474 }
1475
1476 static int
1477 enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1478 {
1479         return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1480 }
1481
1482 static u32 enc28j60_get_msglevel(struct net_device *dev)
1483 {
1484         struct enc28j60_net *priv = netdev_priv(dev);
1485         return priv->msg_enable;
1486 }
1487
1488 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1489 {
1490         struct enc28j60_net *priv = netdev_priv(dev);
1491         priv->msg_enable = val;
1492 }
1493
1494 static const struct ethtool_ops enc28j60_ethtool_ops = {
1495         .get_settings   = enc28j60_get_settings,
1496         .set_settings   = enc28j60_set_settings,
1497         .get_drvinfo    = enc28j60_get_drvinfo,
1498         .get_msglevel   = enc28j60_get_msglevel,
1499         .set_msglevel   = enc28j60_set_msglevel,
1500 };
1501
1502 static int enc28j60_chipset_init(struct net_device *dev)
1503 {
1504         struct enc28j60_net *priv = netdev_priv(dev);
1505
1506         return enc28j60_hw_init(priv);
1507 }
1508
1509 static int __devinit enc28j60_probe(struct spi_device *spi)
1510 {
1511         struct net_device *dev;
1512         struct enc28j60_net *priv;
1513         int ret = 0;
1514
1515         if (netif_msg_drv(&debug))
1516                 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1517                         DRV_VERSION);
1518
1519         dev = alloc_etherdev(sizeof(struct enc28j60_net));
1520         if (!dev) {
1521                 if (netif_msg_drv(&debug))
1522                         dev_err(&spi->dev, DRV_NAME
1523                                 ": unable to alloc new ethernet\n");
1524                 ret = -ENOMEM;
1525                 goto error_alloc;
1526         }
1527         priv = netdev_priv(dev);
1528
1529         priv->netdev = dev;     /* priv to netdev reference */
1530         priv->spi = spi;        /* priv to spi reference */
1531         priv->msg_enable = netif_msg_init(debug.msg_enable,
1532                                                 ENC28J60_MSG_DEFAULT);
1533         mutex_init(&priv->lock);
1534         INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1535         INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1536         INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1537         INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1538         dev_set_drvdata(&spi->dev, priv);       /* spi to priv reference */
1539         SET_NETDEV_DEV(dev, &spi->dev);
1540
1541         if (!enc28j60_chipset_init(dev)) {
1542                 if (netif_msg_probe(priv))
1543                         dev_info(&spi->dev, DRV_NAME " chip not found\n");
1544                 ret = -EIO;
1545                 goto error_irq;
1546         }
1547         random_ether_addr(dev->dev_addr);
1548         enc28j60_set_hw_macaddr(dev);
1549
1550         ret = request_irq(spi->irq, enc28j60_irq, IRQF_TRIGGER_FALLING,
1551                           DRV_NAME, priv);
1552         if (ret < 0) {
1553                 if (netif_msg_probe(priv))
1554                         dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1555                                 "(ret = %d)\n", spi->irq, ret);
1556                 goto error_irq;
1557         }
1558
1559         dev->if_port = IF_PORT_10BASET;
1560         dev->irq = spi->irq;
1561         dev->open = enc28j60_net_open;
1562         dev->stop = enc28j60_net_close;
1563         dev->hard_start_xmit = enc28j60_send_packet;
1564         dev->set_multicast_list = &enc28j60_set_multicast_list;
1565         dev->set_mac_address = enc28j60_set_mac_address;
1566         dev->tx_timeout = &enc28j60_tx_timeout;
1567         dev->watchdog_timeo = TX_TIMEOUT;
1568         SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1569
1570         enc28j60_lowpower(priv, true);
1571
1572         ret = register_netdev(dev);
1573         if (ret) {
1574                 if (netif_msg_probe(priv))
1575                         dev_err(&spi->dev, "register netdev " DRV_NAME
1576                                 " failed (ret = %d)\n", ret);
1577                 goto error_register;
1578         }
1579         dev_info(&dev->dev, DRV_NAME " driver registered\n");
1580
1581         return 0;
1582
1583 error_register:
1584         free_irq(spi->irq, priv);
1585 error_irq:
1586         free_netdev(dev);
1587 error_alloc:
1588         return ret;
1589 }
1590
1591 static int __devexit enc28j60_remove(struct spi_device *spi)
1592 {
1593         struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1594
1595         if (netif_msg_drv(priv))
1596                 printk(KERN_DEBUG DRV_NAME ": remove\n");
1597
1598         unregister_netdev(priv->netdev);
1599         free_irq(spi->irq, priv);
1600         free_netdev(priv->netdev);
1601
1602         return 0;
1603 }
1604
1605 static struct spi_driver enc28j60_driver = {
1606         .driver = {
1607                    .name = DRV_NAME,
1608                    .owner = THIS_MODULE,
1609          },
1610         .probe = enc28j60_probe,
1611         .remove = __devexit_p(enc28j60_remove),
1612 };
1613
1614 static int __init enc28j60_init(void)
1615 {
1616         msec20_to_jiffies = msecs_to_jiffies(20);
1617
1618         return spi_register_driver(&enc28j60_driver);
1619 }
1620
1621 module_init(enc28j60_init);
1622
1623 static void __exit enc28j60_exit(void)
1624 {
1625         spi_unregister_driver(&enc28j60_driver);
1626 }
1627
1628 module_exit(enc28j60_exit);
1629
1630 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1631 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1632 MODULE_LICENSE("GPL");
1633 module_param_named(debug, debug.msg_enable, int, 0);
1634 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");