Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 82562G 10/100 Network Connection
31  * 82562G-2 10/100 Network Connection
32  * 82562GT 10/100 Network Connection
33  * 82562GT-2 10/100 Network Connection
34  * 82562V 10/100 Network Connection
35  * 82562V-2 10/100 Network Connection
36  * 82566DC-2 Gigabit Network Connection
37  * 82566DC Gigabit Network Connection
38  * 82566DM-2 Gigabit Network Connection
39  * 82566DM Gigabit Network Connection
40  * 82566MC Gigabit Network Connection
41  * 82566MM Gigabit Network Connection
42  * 82567LM Gigabit Network Connection
43  * 82567LF Gigabit Network Connection
44  * 82567V Gigabit Network Connection
45  * 82567LM-2 Gigabit Network Connection
46  * 82567LF-2 Gigabit Network Connection
47  * 82567V-2 Gigabit Network Connection
48  * 82567LF-3 Gigabit Network Connection
49  * 82567LM-3 Gigabit Network Connection
50  * 82567LM-4 Gigabit Network Connection
51  */
52
53 #include <linux/netdevice.h>
54 #include <linux/ethtool.h>
55 #include <linux/delay.h>
56 #include <linux/pci.h>
57
58 #include "e1000.h"
59
60 #define ICH_FLASH_GFPREG                0x0000
61 #define ICH_FLASH_HSFSTS                0x0004
62 #define ICH_FLASH_HSFCTL                0x0006
63 #define ICH_FLASH_FADDR                 0x0008
64 #define ICH_FLASH_FDATA0                0x0010
65 #define ICH_FLASH_PR0                   0x0074
66
67 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
71 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
72
73 #define ICH_CYCLE_READ                  0
74 #define ICH_CYCLE_WRITE                 2
75 #define ICH_CYCLE_ERASE                 3
76
77 #define FLASH_GFPREG_BASE_MASK          0x1FFF
78 #define FLASH_SECTOR_ADDR_SHIFT         12
79
80 #define ICH_FLASH_SEG_SIZE_256          256
81 #define ICH_FLASH_SEG_SIZE_4K           4096
82 #define ICH_FLASH_SEG_SIZE_8K           8192
83 #define ICH_FLASH_SEG_SIZE_64K          65536
84
85
86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87
88 #define E1000_ICH_MNG_IAMT_MODE         0x2
89
90 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
91                                  (ID_LED_DEF1_OFF2 <<  8) | \
92                                  (ID_LED_DEF1_ON2  <<  4) | \
93                                  (ID_LED_DEF1_DEF2))
94
95 #define E1000_ICH_NVM_SIG_WORD          0x13
96 #define E1000_ICH_NVM_SIG_MASK          0xC000
97 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
98 #define E1000_ICH_NVM_SIG_VALUE         0x80
99
100 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
101
102 #define E1000_FEXTNVM_SW_CONFIG         1
103 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
104
105 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
106
107 #define E1000_ICH_RAR_ENTRIES           7
108
109 #define PHY_PAGE_SHIFT 5
110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
111                            ((reg) & MAX_PHY_REG_ADDRESS))
112 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
114
115 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
116 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
117 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
118
119 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120 /* Offset 04h HSFSTS */
121 union ich8_hws_flash_status {
122         struct ich8_hsfsts {
123                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
124                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
125                 u16 dael       :1; /* bit 2 Direct Access error Log */
126                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
127                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
128                 u16 reserved1  :2; /* bit 13:6 Reserved */
129                 u16 reserved2  :6; /* bit 13:6 Reserved */
130                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
131                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
132         } hsf_status;
133         u16 regval;
134 };
135
136 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
137 /* Offset 06h FLCTL */
138 union ich8_hws_flash_ctrl {
139         struct ich8_hsflctl {
140                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
141                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
142                 u16 reserved   :5;   /* 7:3 Reserved  */
143                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
144                 u16 flockdn    :6;   /* 15:10 Reserved */
145         } hsf_ctrl;
146         u16 regval;
147 };
148
149 /* ICH Flash Region Access Permissions */
150 union ich8_hws_flash_regacc {
151         struct ich8_flracc {
152                 u32 grra      :8; /* 0:7 GbE region Read Access */
153                 u32 grwa      :8; /* 8:15 GbE region Write Access */
154                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
155                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
156         } hsf_flregacc;
157         u16 regval;
158 };
159
160 /* ICH Flash Protected Region */
161 union ich8_flash_protected_range {
162         struct ich8_pr {
163                 u32 base:13;     /* 0:12 Protected Range Base */
164                 u32 reserved1:2; /* 13:14 Reserved */
165                 u32 rpe:1;       /* 15 Read Protection Enable */
166                 u32 limit:13;    /* 16:28 Protected Range Limit */
167                 u32 reserved2:2; /* 29:30 Reserved */
168                 u32 wpe:1;       /* 31 Write Protection Enable */
169         } range;
170         u32 regval;
171 };
172
173 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
174 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
175 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
176 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
177 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
178 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
179                                                 u32 offset, u8 byte);
180 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
181                                          u8 *data);
182 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
183                                          u16 *data);
184 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
185                                          u8 size, u16 *data);
186 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
187 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
188 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
189
190 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
191 {
192         return readw(hw->flash_address + reg);
193 }
194
195 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
196 {
197         return readl(hw->flash_address + reg);
198 }
199
200 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
201 {
202         writew(val, hw->flash_address + reg);
203 }
204
205 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
206 {
207         writel(val, hw->flash_address + reg);
208 }
209
210 #define er16flash(reg)          __er16flash(hw, (reg))
211 #define er32flash(reg)          __er32flash(hw, (reg))
212 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
213 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
214
215 /**
216  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
217  *  @hw: pointer to the HW structure
218  *
219  *  Initialize family-specific PHY parameters and function pointers.
220  **/
221 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
222 {
223         struct e1000_phy_info *phy = &hw->phy;
224         s32 ret_val;
225         u16 i = 0;
226
227         phy->addr                       = 1;
228         phy->reset_delay_us             = 100;
229
230         /*
231          * We may need to do this twice - once for IGP and if that fails,
232          * we'll set BM func pointers and try again
233          */
234         ret_val = e1000e_determine_phy_address(hw);
235         if (ret_val) {
236                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
237                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
238                 ret_val = e1000e_determine_phy_address(hw);
239                 if (ret_val)
240                         return ret_val;
241         }
242
243         phy->id = 0;
244         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
245                (i++ < 100)) {
246                 msleep(1);
247                 ret_val = e1000e_get_phy_id(hw);
248                 if (ret_val)
249                         return ret_val;
250         }
251
252         /* Verify phy id */
253         switch (phy->id) {
254         case IGP03E1000_E_PHY_ID:
255                 phy->type = e1000_phy_igp_3;
256                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
257                 break;
258         case IFE_E_PHY_ID:
259         case IFE_PLUS_E_PHY_ID:
260         case IFE_C_E_PHY_ID:
261                 phy->type = e1000_phy_ife;
262                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
263                 break;
264         case BME1000_E_PHY_ID:
265                 phy->type = e1000_phy_bm;
266                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
267                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
268                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
269                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
270                 break;
271         default:
272                 return -E1000_ERR_PHY;
273                 break;
274         }
275
276         return 0;
277 }
278
279 /**
280  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
281  *  @hw: pointer to the HW structure
282  *
283  *  Initialize family-specific NVM parameters and function
284  *  pointers.
285  **/
286 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
287 {
288         struct e1000_nvm_info *nvm = &hw->nvm;
289         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
290         u32 gfpreg;
291         u32 sector_base_addr;
292         u32 sector_end_addr;
293         u16 i;
294
295         /* Can't read flash registers if the register set isn't mapped. */
296         if (!hw->flash_address) {
297                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
298                 return -E1000_ERR_CONFIG;
299         }
300
301         nvm->type = e1000_nvm_flash_sw;
302
303         gfpreg = er32flash(ICH_FLASH_GFPREG);
304
305         /*
306          * sector_X_addr is a "sector"-aligned address (4096 bytes)
307          * Add 1 to sector_end_addr since this sector is included in
308          * the overall size.
309          */
310         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
311         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
312
313         /* flash_base_addr is byte-aligned */
314         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
315
316         /*
317          * find total size of the NVM, then cut in half since the total
318          * size represents two separate NVM banks.
319          */
320         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
321                                 << FLASH_SECTOR_ADDR_SHIFT;
322         nvm->flash_bank_size /= 2;
323         /* Adjust to word count */
324         nvm->flash_bank_size /= sizeof(u16);
325
326         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
327
328         /* Clear shadow ram */
329         for (i = 0; i < nvm->word_size; i++) {
330                 dev_spec->shadow_ram[i].modified = 0;
331                 dev_spec->shadow_ram[i].value    = 0xFFFF;
332         }
333
334         return 0;
335 }
336
337 /**
338  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
339  *  @hw: pointer to the HW structure
340  *
341  *  Initialize family-specific MAC parameters and function
342  *  pointers.
343  **/
344 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
345 {
346         struct e1000_hw *hw = &adapter->hw;
347         struct e1000_mac_info *mac = &hw->mac;
348
349         /* Set media type function pointer */
350         hw->phy.media_type = e1000_media_type_copper;
351
352         /* Set mta register count */
353         mac->mta_reg_count = 32;
354         /* Set rar entry count */
355         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
356         if (mac->type == e1000_ich8lan)
357                 mac->rar_entry_count--;
358         /* Set if manageability features are enabled. */
359         mac->arc_subsystem_valid = 1;
360
361         /* Enable PCS Lock-loss workaround for ICH8 */
362         if (mac->type == e1000_ich8lan)
363                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
364
365         return 0;
366 }
367
368 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
369 {
370         struct e1000_hw *hw = &adapter->hw;
371         s32 rc;
372
373         rc = e1000_init_mac_params_ich8lan(adapter);
374         if (rc)
375                 return rc;
376
377         rc = e1000_init_nvm_params_ich8lan(hw);
378         if (rc)
379                 return rc;
380
381         rc = e1000_init_phy_params_ich8lan(hw);
382         if (rc)
383                 return rc;
384
385         if ((adapter->hw.mac.type == e1000_ich8lan) &&
386             (adapter->hw.phy.type == e1000_phy_igp_3))
387                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
388
389         return 0;
390 }
391
392 static DEFINE_MUTEX(nvm_mutex);
393 static pid_t nvm_owner = -1;
394
395 /**
396  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
397  *  @hw: pointer to the HW structure
398  *
399  *  Acquires the software control flag for performing NVM and PHY
400  *  operations.  This is a function pointer entry point only called by
401  *  read/write routines for the PHY and NVM parts.
402  **/
403 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
404 {
405         u32 extcnf_ctrl;
406         u32 timeout = PHY_CFG_TIMEOUT;
407
408         might_sleep();
409
410         if (!mutex_trylock(&nvm_mutex)) {
411                 WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n",
412                      nvm_owner);
413                 mutex_lock(&nvm_mutex);
414         }
415         nvm_owner = current->pid;
416
417         while (timeout) {
418                 extcnf_ctrl = er32(EXTCNF_CTRL);
419                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
420                 ew32(EXTCNF_CTRL, extcnf_ctrl);
421
422                 extcnf_ctrl = er32(EXTCNF_CTRL);
423                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
424                         break;
425                 mdelay(1);
426                 timeout--;
427         }
428
429         if (!timeout) {
430                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
431                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
432                 ew32(EXTCNF_CTRL, extcnf_ctrl);
433                 nvm_owner = -1;
434                 mutex_unlock(&nvm_mutex);
435                 return -E1000_ERR_CONFIG;
436         }
437
438         return 0;
439 }
440
441 /**
442  *  e1000_release_swflag_ich8lan - Release software control flag
443  *  @hw: pointer to the HW structure
444  *
445  *  Releases the software control flag for performing NVM and PHY operations.
446  *  This is a function pointer entry point only called by read/write
447  *  routines for the PHY and NVM parts.
448  **/
449 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
450 {
451         u32 extcnf_ctrl;
452
453         extcnf_ctrl = er32(EXTCNF_CTRL);
454         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
455         ew32(EXTCNF_CTRL, extcnf_ctrl);
456
457         nvm_owner = -1;
458         mutex_unlock(&nvm_mutex);
459 }
460
461 /**
462  *  e1000_check_mng_mode_ich8lan - Checks management mode
463  *  @hw: pointer to the HW structure
464  *
465  *  This checks if the adapter has manageability enabled.
466  *  This is a function pointer entry point only called by read/write
467  *  routines for the PHY and NVM parts.
468  **/
469 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
470 {
471         u32 fwsm = er32(FWSM);
472
473         return (fwsm & E1000_FWSM_MODE_MASK) ==
474                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
475 }
476
477 /**
478  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
479  *  @hw: pointer to the HW structure
480  *
481  *  Checks if firmware is blocking the reset of the PHY.
482  *  This is a function pointer entry point only called by
483  *  reset routines.
484  **/
485 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
486 {
487         u32 fwsm;
488
489         fwsm = er32(FWSM);
490
491         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
492 }
493
494 /**
495  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
496  *  @hw: pointer to the HW structure
497  *
498  *  Forces the speed and duplex settings of the PHY.
499  *  This is a function pointer entry point only called by
500  *  PHY setup routines.
501  **/
502 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
503 {
504         struct e1000_phy_info *phy = &hw->phy;
505         s32 ret_val;
506         u16 data;
507         bool link;
508
509         if (phy->type != e1000_phy_ife) {
510                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
511                 return ret_val;
512         }
513
514         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
515         if (ret_val)
516                 return ret_val;
517
518         e1000e_phy_force_speed_duplex_setup(hw, &data);
519
520         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
521         if (ret_val)
522                 return ret_val;
523
524         /* Disable MDI-X support for 10/100 */
525         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
526         if (ret_val)
527                 return ret_val;
528
529         data &= ~IFE_PMC_AUTO_MDIX;
530         data &= ~IFE_PMC_FORCE_MDIX;
531
532         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
533         if (ret_val)
534                 return ret_val;
535
536         hw_dbg(hw, "IFE PMC: %X\n", data);
537
538         udelay(1);
539
540         if (phy->autoneg_wait_to_complete) {
541                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
542
543                 ret_val = e1000e_phy_has_link_generic(hw,
544                                                      PHY_FORCE_LIMIT,
545                                                      100000,
546                                                      &link);
547                 if (ret_val)
548                         return ret_val;
549
550                 if (!link)
551                         hw_dbg(hw, "Link taking longer than expected.\n");
552
553                 /* Try once more */
554                 ret_val = e1000e_phy_has_link_generic(hw,
555                                                      PHY_FORCE_LIMIT,
556                                                      100000,
557                                                      &link);
558                 if (ret_val)
559                         return ret_val;
560         }
561
562         return 0;
563 }
564
565 /**
566  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
567  *  @hw: pointer to the HW structure
568  *
569  *  Resets the PHY
570  *  This is a function pointer entry point called by drivers
571  *  or other shared routines.
572  **/
573 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
574 {
575         struct e1000_phy_info *phy = &hw->phy;
576         u32 i;
577         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
578         s32 ret_val;
579         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
580         u16 word_addr, reg_data, reg_addr, phy_page = 0;
581
582         ret_val = e1000e_phy_hw_reset_generic(hw);
583         if (ret_val)
584                 return ret_val;
585
586         /*
587          * Initialize the PHY from the NVM on ICH platforms.  This
588          * is needed due to an issue where the NVM configuration is
589          * not properly autoloaded after power transitions.
590          * Therefore, after each PHY reset, we will load the
591          * configuration data out of the NVM manually.
592          */
593         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
594                 struct e1000_adapter *adapter = hw->adapter;
595
596                 /* Check if SW needs configure the PHY */
597                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
598                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
599                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
600                 else
601                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
602
603                 data = er32(FEXTNVM);
604                 if (!(data & sw_cfg_mask))
605                         return 0;
606
607                 /* Wait for basic configuration completes before proceeding*/
608                 do {
609                         data = er32(STATUS);
610                         data &= E1000_STATUS_LAN_INIT_DONE;
611                         udelay(100);
612                 } while ((!data) && --loop);
613
614                 /*
615                  * If basic configuration is incomplete before the above loop
616                  * count reaches 0, loading the configuration from NVM will
617                  * leave the PHY in a bad state possibly resulting in no link.
618                  */
619                 if (loop == 0) {
620                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
621                 }
622
623                 /* Clear the Init Done bit for the next init event */
624                 data = er32(STATUS);
625                 data &= ~E1000_STATUS_LAN_INIT_DONE;
626                 ew32(STATUS, data);
627
628                 /*
629                  * Make sure HW does not configure LCD from PHY
630                  * extended configuration before SW configuration
631                  */
632                 data = er32(EXTCNF_CTRL);
633                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
634                         return 0;
635
636                 cnf_size = er32(EXTCNF_SIZE);
637                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
638                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
639                 if (!cnf_size)
640                         return 0;
641
642                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
643                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
644
645                 /* Configure LCD from extended configuration region. */
646
647                 /* cnf_base_addr is in DWORD */
648                 word_addr = (u16)(cnf_base_addr << 1);
649
650                 for (i = 0; i < cnf_size; i++) {
651                         ret_val = e1000_read_nvm(hw,
652                                                 (word_addr + i * 2),
653                                                 1,
654                                                 &reg_data);
655                         if (ret_val)
656                                 return ret_val;
657
658                         ret_val = e1000_read_nvm(hw,
659                                                 (word_addr + i * 2 + 1),
660                                                 1,
661                                                 &reg_addr);
662                         if (ret_val)
663                                 return ret_val;
664
665                         /* Save off the PHY page for future writes. */
666                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
667                                 phy_page = reg_data;
668                                 continue;
669                         }
670
671                         reg_addr |= phy_page;
672
673                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
674                         if (ret_val)
675                                 return ret_val;
676                 }
677         }
678
679         return 0;
680 }
681
682 /**
683  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
684  *  @hw: pointer to the HW structure
685  *
686  *  Populates "phy" structure with various feature states.
687  *  This function is only called by other family-specific
688  *  routines.
689  **/
690 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
691 {
692         struct e1000_phy_info *phy = &hw->phy;
693         s32 ret_val;
694         u16 data;
695         bool link;
696
697         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
698         if (ret_val)
699                 return ret_val;
700
701         if (!link) {
702                 hw_dbg(hw, "Phy info is only valid if link is up\n");
703                 return -E1000_ERR_CONFIG;
704         }
705
706         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
707         if (ret_val)
708                 return ret_val;
709         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
710
711         if (phy->polarity_correction) {
712                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
713                 if (ret_val)
714                         return ret_val;
715         } else {
716                 /* Polarity is forced */
717                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
718                                       ? e1000_rev_polarity_reversed
719                                       : e1000_rev_polarity_normal;
720         }
721
722         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
723         if (ret_val)
724                 return ret_val;
725
726         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
727
728         /* The following parameters are undefined for 10/100 operation. */
729         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
730         phy->local_rx = e1000_1000t_rx_status_undefined;
731         phy->remote_rx = e1000_1000t_rx_status_undefined;
732
733         return 0;
734 }
735
736 /**
737  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
738  *  @hw: pointer to the HW structure
739  *
740  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
741  *  This is a function pointer entry point called by drivers
742  *  or other shared routines.
743  **/
744 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
745 {
746         switch (hw->phy.type) {
747         case e1000_phy_ife:
748                 return e1000_get_phy_info_ife_ich8lan(hw);
749                 break;
750         case e1000_phy_igp_3:
751         case e1000_phy_bm:
752                 return e1000e_get_phy_info_igp(hw);
753                 break;
754         default:
755                 break;
756         }
757
758         return -E1000_ERR_PHY_TYPE;
759 }
760
761 /**
762  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
763  *  @hw: pointer to the HW structure
764  *
765  *  Polarity is determined on the polarity reversal feature being enabled.
766  *  This function is only called by other family-specific
767  *  routines.
768  **/
769 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
770 {
771         struct e1000_phy_info *phy = &hw->phy;
772         s32 ret_val;
773         u16 phy_data, offset, mask;
774
775         /*
776          * Polarity is determined based on the reversal feature being enabled.
777          */
778         if (phy->polarity_correction) {
779                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
780                 mask    = IFE_PESC_POLARITY_REVERSED;
781         } else {
782                 offset  = IFE_PHY_SPECIAL_CONTROL;
783                 mask    = IFE_PSC_FORCE_POLARITY;
784         }
785
786         ret_val = e1e_rphy(hw, offset, &phy_data);
787
788         if (!ret_val)
789                 phy->cable_polarity = (phy_data & mask)
790                                       ? e1000_rev_polarity_reversed
791                                       : e1000_rev_polarity_normal;
792
793         return ret_val;
794 }
795
796 /**
797  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
798  *  @hw: pointer to the HW structure
799  *  @active: TRUE to enable LPLU, FALSE to disable
800  *
801  *  Sets the LPLU D0 state according to the active flag.  When
802  *  activating LPLU this function also disables smart speed
803  *  and vice versa.  LPLU will not be activated unless the
804  *  device autonegotiation advertisement meets standards of
805  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
806  *  This is a function pointer entry point only called by
807  *  PHY setup routines.
808  **/
809 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
810 {
811         struct e1000_phy_info *phy = &hw->phy;
812         u32 phy_ctrl;
813         s32 ret_val = 0;
814         u16 data;
815
816         if (phy->type == e1000_phy_ife)
817                 return ret_val;
818
819         phy_ctrl = er32(PHY_CTRL);
820
821         if (active) {
822                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
823                 ew32(PHY_CTRL, phy_ctrl);
824
825                 /*
826                  * Call gig speed drop workaround on LPLU before accessing
827                  * any PHY registers
828                  */
829                 if ((hw->mac.type == e1000_ich8lan) &&
830                     (hw->phy.type == e1000_phy_igp_3))
831                         e1000e_gig_downshift_workaround_ich8lan(hw);
832
833                 /* When LPLU is enabled, we should disable SmartSpeed */
834                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
835                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
836                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
837                 if (ret_val)
838                         return ret_val;
839         } else {
840                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
841                 ew32(PHY_CTRL, phy_ctrl);
842
843                 /*
844                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
845                  * during Dx states where the power conservation is most
846                  * important.  During driver activity we should enable
847                  * SmartSpeed, so performance is maintained.
848                  */
849                 if (phy->smart_speed == e1000_smart_speed_on) {
850                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
851                                            &data);
852                         if (ret_val)
853                                 return ret_val;
854
855                         data |= IGP01E1000_PSCFR_SMART_SPEED;
856                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
857                                            data);
858                         if (ret_val)
859                                 return ret_val;
860                 } else if (phy->smart_speed == e1000_smart_speed_off) {
861                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
862                                            &data);
863                         if (ret_val)
864                                 return ret_val;
865
866                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
867                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
868                                            data);
869                         if (ret_val)
870                                 return ret_val;
871                 }
872         }
873
874         return 0;
875 }
876
877 /**
878  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
879  *  @hw: pointer to the HW structure
880  *  @active: TRUE to enable LPLU, FALSE to disable
881  *
882  *  Sets the LPLU D3 state according to the active flag.  When
883  *  activating LPLU this function also disables smart speed
884  *  and vice versa.  LPLU will not be activated unless the
885  *  device autonegotiation advertisement meets standards of
886  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
887  *  This is a function pointer entry point only called by
888  *  PHY setup routines.
889  **/
890 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
891 {
892         struct e1000_phy_info *phy = &hw->phy;
893         u32 phy_ctrl;
894         s32 ret_val;
895         u16 data;
896
897         phy_ctrl = er32(PHY_CTRL);
898
899         if (!active) {
900                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
901                 ew32(PHY_CTRL, phy_ctrl);
902                 /*
903                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
904                  * during Dx states where the power conservation is most
905                  * important.  During driver activity we should enable
906                  * SmartSpeed, so performance is maintained.
907                  */
908                 if (phy->smart_speed == e1000_smart_speed_on) {
909                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
910                                            &data);
911                         if (ret_val)
912                                 return ret_val;
913
914                         data |= IGP01E1000_PSCFR_SMART_SPEED;
915                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
916                                            data);
917                         if (ret_val)
918                                 return ret_val;
919                 } else if (phy->smart_speed == e1000_smart_speed_off) {
920                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
921                                            &data);
922                         if (ret_val)
923                                 return ret_val;
924
925                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
926                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
927                                            data);
928                         if (ret_val)
929                                 return ret_val;
930                 }
931         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
932                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
933                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
934                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
935                 ew32(PHY_CTRL, phy_ctrl);
936
937                 /*
938                  * Call gig speed drop workaround on LPLU before accessing
939                  * any PHY registers
940                  */
941                 if ((hw->mac.type == e1000_ich8lan) &&
942                     (hw->phy.type == e1000_phy_igp_3))
943                         e1000e_gig_downshift_workaround_ich8lan(hw);
944
945                 /* When LPLU is enabled, we should disable SmartSpeed */
946                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
947                 if (ret_val)
948                         return ret_val;
949
950                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
951                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
952         }
953
954         return 0;
955 }
956
957 /**
958  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
959  *  @hw: pointer to the HW structure
960  *  @bank:  pointer to the variable that returns the active bank
961  *
962  *  Reads signature byte from the NVM using the flash access registers.
963  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
964  **/
965 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
966 {
967         u32 eecd;
968         struct e1000_nvm_info *nvm = &hw->nvm;
969         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
970         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
971         u8 sig_byte = 0;
972         s32 ret_val = 0;
973
974         switch (hw->mac.type) {
975         case e1000_ich8lan:
976         case e1000_ich9lan:
977                 eecd = er32(EECD);
978                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
979                     E1000_EECD_SEC1VAL_VALID_MASK) {
980                         if (eecd & E1000_EECD_SEC1VAL)
981                                 *bank = 1;
982                         else
983                                 *bank = 0;
984
985                         return 0;
986                 }
987                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
988                        "reading flash signature\n");
989                 /* fall-thru */
990         default:
991                 /* set bank to 0 in case flash read fails */
992                 *bank = 0;
993
994                 /* Check bank 0 */
995                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
996                                                         &sig_byte);
997                 if (ret_val)
998                         return ret_val;
999                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1000                     E1000_ICH_NVM_SIG_VALUE) {
1001                         *bank = 0;
1002                         return 0;
1003                 }
1004
1005                 /* Check bank 1 */
1006                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1007                                                         bank1_offset,
1008                                                         &sig_byte);
1009                 if (ret_val)
1010                         return ret_val;
1011                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1012                     E1000_ICH_NVM_SIG_VALUE) {
1013                         *bank = 1;
1014                         return 0;
1015                 }
1016
1017                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1018                 return -E1000_ERR_NVM;
1019         }
1020
1021         return 0;
1022 }
1023
1024 /**
1025  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1026  *  @hw: pointer to the HW structure
1027  *  @offset: The offset (in bytes) of the word(s) to read.
1028  *  @words: Size of data to read in words
1029  *  @data: Pointer to the word(s) to read at offset.
1030  *
1031  *  Reads a word(s) from the NVM using the flash access registers.
1032  **/
1033 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1034                                   u16 *data)
1035 {
1036         struct e1000_nvm_info *nvm = &hw->nvm;
1037         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1038         u32 act_offset;
1039         s32 ret_val;
1040         u32 bank = 0;
1041         u16 i, word;
1042
1043         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1044             (words == 0)) {
1045                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1046                 return -E1000_ERR_NVM;
1047         }
1048
1049         ret_val = e1000_acquire_swflag_ich8lan(hw);
1050         if (ret_val)
1051                 goto out;
1052
1053         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1054         if (ret_val)
1055                 goto release;
1056
1057         act_offset = (bank) ? nvm->flash_bank_size : 0;
1058         act_offset += offset;
1059
1060         for (i = 0; i < words; i++) {
1061                 if ((dev_spec->shadow_ram) &&
1062                     (dev_spec->shadow_ram[offset+i].modified)) {
1063                         data[i] = dev_spec->shadow_ram[offset+i].value;
1064                 } else {
1065                         ret_val = e1000_read_flash_word_ich8lan(hw,
1066                                                                 act_offset + i,
1067                                                                 &word);
1068                         if (ret_val)
1069                                 break;
1070                         data[i] = word;
1071                 }
1072         }
1073
1074 release:
1075         e1000_release_swflag_ich8lan(hw);
1076
1077 out:
1078         if (ret_val)
1079                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1080
1081         return ret_val;
1082 }
1083
1084 /**
1085  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1086  *  @hw: pointer to the HW structure
1087  *
1088  *  This function does initial flash setup so that a new read/write/erase cycle
1089  *  can be started.
1090  **/
1091 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1092 {
1093         union ich8_hws_flash_status hsfsts;
1094         s32 ret_val = -E1000_ERR_NVM;
1095         s32 i = 0;
1096
1097         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1098
1099         /* Check if the flash descriptor is valid */
1100         if (hsfsts.hsf_status.fldesvalid == 0) {
1101                 hw_dbg(hw, "Flash descriptor invalid.  "
1102                          "SW Sequencing must be used.");
1103                 return -E1000_ERR_NVM;
1104         }
1105
1106         /* Clear FCERR and DAEL in hw status by writing 1 */
1107         hsfsts.hsf_status.flcerr = 1;
1108         hsfsts.hsf_status.dael = 1;
1109
1110         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1111
1112         /*
1113          * Either we should have a hardware SPI cycle in progress
1114          * bit to check against, in order to start a new cycle or
1115          * FDONE bit should be changed in the hardware so that it
1116          * is 1 after hardware reset, which can then be used as an
1117          * indication whether a cycle is in progress or has been
1118          * completed.
1119          */
1120
1121         if (hsfsts.hsf_status.flcinprog == 0) {
1122                 /*
1123                  * There is no cycle running at present,
1124                  * so we can start a cycle
1125                  * Begin by setting Flash Cycle Done.
1126                  */
1127                 hsfsts.hsf_status.flcdone = 1;
1128                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1129                 ret_val = 0;
1130         } else {
1131                 /*
1132                  * otherwise poll for sometime so the current
1133                  * cycle has a chance to end before giving up.
1134                  */
1135                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1136                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1137                         if (hsfsts.hsf_status.flcinprog == 0) {
1138                                 ret_val = 0;
1139                                 break;
1140                         }
1141                         udelay(1);
1142                 }
1143                 if (ret_val == 0) {
1144                         /*
1145                          * Successful in waiting for previous cycle to timeout,
1146                          * now set the Flash Cycle Done.
1147                          */
1148                         hsfsts.hsf_status.flcdone = 1;
1149                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1150                 } else {
1151                         hw_dbg(hw, "Flash controller busy, cannot get access");
1152                 }
1153         }
1154
1155         return ret_val;
1156 }
1157
1158 /**
1159  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1160  *  @hw: pointer to the HW structure
1161  *  @timeout: maximum time to wait for completion
1162  *
1163  *  This function starts a flash cycle and waits for its completion.
1164  **/
1165 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1166 {
1167         union ich8_hws_flash_ctrl hsflctl;
1168         union ich8_hws_flash_status hsfsts;
1169         s32 ret_val = -E1000_ERR_NVM;
1170         u32 i = 0;
1171
1172         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1173         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1174         hsflctl.hsf_ctrl.flcgo = 1;
1175         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1176
1177         /* wait till FDONE bit is set to 1 */
1178         do {
1179                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1180                 if (hsfsts.hsf_status.flcdone == 1)
1181                         break;
1182                 udelay(1);
1183         } while (i++ < timeout);
1184
1185         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1186                 return 0;
1187
1188         return ret_val;
1189 }
1190
1191 /**
1192  *  e1000_read_flash_word_ich8lan - Read word from flash
1193  *  @hw: pointer to the HW structure
1194  *  @offset: offset to data location
1195  *  @data: pointer to the location for storing the data
1196  *
1197  *  Reads the flash word at offset into data.  Offset is converted
1198  *  to bytes before read.
1199  **/
1200 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1201                                          u16 *data)
1202 {
1203         /* Must convert offset into bytes. */
1204         offset <<= 1;
1205
1206         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1207 }
1208
1209 /**
1210  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1211  *  @hw: pointer to the HW structure
1212  *  @offset: The offset of the byte to read.
1213  *  @data: Pointer to a byte to store the value read.
1214  *
1215  *  Reads a single byte from the NVM using the flash access registers.
1216  **/
1217 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1218                                          u8 *data)
1219 {
1220         s32 ret_val;
1221         u16 word = 0;
1222
1223         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1224         if (ret_val)
1225                 return ret_val;
1226
1227         *data = (u8)word;
1228
1229         return 0;
1230 }
1231
1232 /**
1233  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1234  *  @hw: pointer to the HW structure
1235  *  @offset: The offset (in bytes) of the byte or word to read.
1236  *  @size: Size of data to read, 1=byte 2=word
1237  *  @data: Pointer to the word to store the value read.
1238  *
1239  *  Reads a byte or word from the NVM using the flash access registers.
1240  **/
1241 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1242                                          u8 size, u16 *data)
1243 {
1244         union ich8_hws_flash_status hsfsts;
1245         union ich8_hws_flash_ctrl hsflctl;
1246         u32 flash_linear_addr;
1247         u32 flash_data = 0;
1248         s32 ret_val = -E1000_ERR_NVM;
1249         u8 count = 0;
1250
1251         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1252                 return -E1000_ERR_NVM;
1253
1254         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1255                             hw->nvm.flash_base_addr;
1256
1257         do {
1258                 udelay(1);
1259                 /* Steps */
1260                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1261                 if (ret_val != 0)
1262                         break;
1263
1264                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1265                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1266                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1267                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1268                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1269
1270                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1271
1272                 ret_val = e1000_flash_cycle_ich8lan(hw,
1273                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1274
1275                 /*
1276                  * Check if FCERR is set to 1, if set to 1, clear it
1277                  * and try the whole sequence a few more times, else
1278                  * read in (shift in) the Flash Data0, the order is
1279                  * least significant byte first msb to lsb
1280                  */
1281                 if (ret_val == 0) {
1282                         flash_data = er32flash(ICH_FLASH_FDATA0);
1283                         if (size == 1) {
1284                                 *data = (u8)(flash_data & 0x000000FF);
1285                         } else if (size == 2) {
1286                                 *data = (u16)(flash_data & 0x0000FFFF);
1287                         }
1288                         break;
1289                 } else {
1290                         /*
1291                          * If we've gotten here, then things are probably
1292                          * completely hosed, but if the error condition is
1293                          * detected, it won't hurt to give it another try...
1294                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1295                          */
1296                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1297                         if (hsfsts.hsf_status.flcerr == 1) {
1298                                 /* Repeat for some time before giving up. */
1299                                 continue;
1300                         } else if (hsfsts.hsf_status.flcdone == 0) {
1301                                 hw_dbg(hw, "Timeout error - flash cycle "
1302                                          "did not complete.");
1303                                 break;
1304                         }
1305                 }
1306         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1307
1308         return ret_val;
1309 }
1310
1311 /**
1312  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1313  *  @hw: pointer to the HW structure
1314  *  @offset: The offset (in bytes) of the word(s) to write.
1315  *  @words: Size of data to write in words
1316  *  @data: Pointer to the word(s) to write at offset.
1317  *
1318  *  Writes a byte or word to the NVM using the flash access registers.
1319  **/
1320 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1321                                    u16 *data)
1322 {
1323         struct e1000_nvm_info *nvm = &hw->nvm;
1324         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1325         s32 ret_val;
1326         u16 i;
1327
1328         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1329             (words == 0)) {
1330                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1331                 return -E1000_ERR_NVM;
1332         }
1333
1334         ret_val = e1000_acquire_swflag_ich8lan(hw);
1335         if (ret_val)
1336                 return ret_val;
1337
1338         for (i = 0; i < words; i++) {
1339                 dev_spec->shadow_ram[offset+i].modified = 1;
1340                 dev_spec->shadow_ram[offset+i].value = data[i];
1341         }
1342
1343         e1000_release_swflag_ich8lan(hw);
1344
1345         return 0;
1346 }
1347
1348 /**
1349  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1350  *  @hw: pointer to the HW structure
1351  *
1352  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1353  *  which writes the checksum to the shadow ram.  The changes in the shadow
1354  *  ram are then committed to the EEPROM by processing each bank at a time
1355  *  checking for the modified bit and writing only the pending changes.
1356  *  After a successful commit, the shadow ram is cleared and is ready for
1357  *  future writes.
1358  **/
1359 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1360 {
1361         struct e1000_nvm_info *nvm = &hw->nvm;
1362         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1363         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1364         s32 ret_val;
1365         u16 data;
1366
1367         ret_val = e1000e_update_nvm_checksum_generic(hw);
1368         if (ret_val)
1369                 goto out;
1370
1371         if (nvm->type != e1000_nvm_flash_sw)
1372                 goto out;
1373
1374         ret_val = e1000_acquire_swflag_ich8lan(hw);
1375         if (ret_val)
1376                 goto out;
1377
1378         /*
1379          * We're writing to the opposite bank so if we're on bank 1,
1380          * write to bank 0 etc.  We also need to erase the segment that
1381          * is going to be written
1382          */
1383         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1384         if (ret_val) {
1385                 e1000_release_swflag_ich8lan(hw);
1386                 goto out;
1387         }
1388
1389         if (bank == 0) {
1390                 new_bank_offset = nvm->flash_bank_size;
1391                 old_bank_offset = 0;
1392                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1393                 if (ret_val) {
1394                         e1000_release_swflag_ich8lan(hw);
1395                         goto out;
1396                 }
1397         } else {
1398                 old_bank_offset = nvm->flash_bank_size;
1399                 new_bank_offset = 0;
1400                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1401                 if (ret_val) {
1402                         e1000_release_swflag_ich8lan(hw);
1403                         goto out;
1404                 }
1405         }
1406
1407         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1408                 /*
1409                  * Determine whether to write the value stored
1410                  * in the other NVM bank or a modified value stored
1411                  * in the shadow RAM
1412                  */
1413                 if (dev_spec->shadow_ram[i].modified) {
1414                         data = dev_spec->shadow_ram[i].value;
1415                 } else {
1416                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1417                                                                 old_bank_offset,
1418                                                                 &data);
1419                         if (ret_val)
1420                                 break;
1421                 }
1422
1423                 /*
1424                  * If the word is 0x13, then make sure the signature bits
1425                  * (15:14) are 11b until the commit has completed.
1426                  * This will allow us to write 10b which indicates the
1427                  * signature is valid.  We want to do this after the write
1428                  * has completed so that we don't mark the segment valid
1429                  * while the write is still in progress
1430                  */
1431                 if (i == E1000_ICH_NVM_SIG_WORD)
1432                         data |= E1000_ICH_NVM_SIG_MASK;
1433
1434                 /* Convert offset to bytes. */
1435                 act_offset = (i + new_bank_offset) << 1;
1436
1437                 udelay(100);
1438                 /* Write the bytes to the new bank. */
1439                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1440                                                                act_offset,
1441                                                                (u8)data);
1442                 if (ret_val)
1443                         break;
1444
1445                 udelay(100);
1446                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1447                                                           act_offset + 1,
1448                                                           (u8)(data >> 8));
1449                 if (ret_val)
1450                         break;
1451         }
1452
1453         /*
1454          * Don't bother writing the segment valid bits if sector
1455          * programming failed.
1456          */
1457         if (ret_val) {
1458                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1459                 hw_dbg(hw, "Flash commit failed.\n");
1460                 e1000_release_swflag_ich8lan(hw);
1461                 goto out;
1462         }
1463
1464         /*
1465          * Finally validate the new segment by setting bit 15:14
1466          * to 10b in word 0x13 , this can be done without an
1467          * erase as well since these bits are 11 to start with
1468          * and we need to change bit 14 to 0b
1469          */
1470         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1471         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1472         if (ret_val) {
1473                 e1000_release_swflag_ich8lan(hw);
1474                 goto out;
1475         }
1476         data &= 0xBFFF;
1477         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1478                                                        act_offset * 2 + 1,
1479                                                        (u8)(data >> 8));
1480         if (ret_val) {
1481                 e1000_release_swflag_ich8lan(hw);
1482                 goto out;
1483         }
1484
1485         /*
1486          * And invalidate the previously valid segment by setting
1487          * its signature word (0x13) high_byte to 0b. This can be
1488          * done without an erase because flash erase sets all bits
1489          * to 1's. We can write 1's to 0's without an erase
1490          */
1491         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1492         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1493         if (ret_val) {
1494                 e1000_release_swflag_ich8lan(hw);
1495                 goto out;
1496         }
1497
1498         /* Great!  Everything worked, we can now clear the cached entries. */
1499         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1500                 dev_spec->shadow_ram[i].modified = 0;
1501                 dev_spec->shadow_ram[i].value = 0xFFFF;
1502         }
1503
1504         e1000_release_swflag_ich8lan(hw);
1505
1506         /*
1507          * Reload the EEPROM, or else modifications will not appear
1508          * until after the next adapter reset.
1509          */
1510         e1000e_reload_nvm(hw);
1511         msleep(10);
1512
1513 out:
1514         if (ret_val)
1515                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1516
1517         return ret_val;
1518 }
1519
1520 /**
1521  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1522  *  @hw: pointer to the HW structure
1523  *
1524  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1525  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1526  *  calculated, in which case we need to calculate the checksum and set bit 6.
1527  **/
1528 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1529 {
1530         s32 ret_val;
1531         u16 data;
1532
1533         /*
1534          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1535          * needs to be fixed.  This bit is an indication that the NVM
1536          * was prepared by OEM software and did not calculate the
1537          * checksum...a likely scenario.
1538          */
1539         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1540         if (ret_val)
1541                 return ret_val;
1542
1543         if ((data & 0x40) == 0) {
1544                 data |= 0x40;
1545                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1546                 if (ret_val)
1547                         return ret_val;
1548                 ret_val = e1000e_update_nvm_checksum(hw);
1549                 if (ret_val)
1550                         return ret_val;
1551         }
1552
1553         return e1000e_validate_nvm_checksum_generic(hw);
1554 }
1555
1556 /**
1557  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1558  *  @hw: pointer to the HW structure
1559  *
1560  *  To prevent malicious write/erase of the NVM, set it to be read-only
1561  *  so that the hardware ignores all write/erase cycles of the NVM via
1562  *  the flash control registers.  The shadow-ram copy of the NVM will
1563  *  still be updated, however any updates to this copy will not stick
1564  *  across driver reloads.
1565  **/
1566 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1567 {
1568         union ich8_flash_protected_range pr0;
1569         union ich8_hws_flash_status hsfsts;
1570         u32 gfpreg;
1571         s32 ret_val;
1572
1573         ret_val = e1000_acquire_swflag_ich8lan(hw);
1574         if (ret_val)
1575                 return;
1576
1577         gfpreg = er32flash(ICH_FLASH_GFPREG);
1578
1579         /* Write-protect GbE Sector of NVM */
1580         pr0.regval = er32flash(ICH_FLASH_PR0);
1581         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1582         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1583         pr0.range.wpe = true;
1584         ew32flash(ICH_FLASH_PR0, pr0.regval);
1585
1586         /*
1587          * Lock down a subset of GbE Flash Control Registers, e.g.
1588          * PR0 to prevent the write-protection from being lifted.
1589          * Once FLOCKDN is set, the registers protected by it cannot
1590          * be written until FLOCKDN is cleared by a hardware reset.
1591          */
1592         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1593         hsfsts.hsf_status.flockdn = true;
1594         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1595
1596         e1000_release_swflag_ich8lan(hw);
1597 }
1598
1599 /**
1600  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1601  *  @hw: pointer to the HW structure
1602  *  @offset: The offset (in bytes) of the byte/word to read.
1603  *  @size: Size of data to read, 1=byte 2=word
1604  *  @data: The byte(s) to write to the NVM.
1605  *
1606  *  Writes one/two bytes to the NVM using the flash access registers.
1607  **/
1608 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1609                                           u8 size, u16 data)
1610 {
1611         union ich8_hws_flash_status hsfsts;
1612         union ich8_hws_flash_ctrl hsflctl;
1613         u32 flash_linear_addr;
1614         u32 flash_data = 0;
1615         s32 ret_val;
1616         u8 count = 0;
1617
1618         if (size < 1 || size > 2 || data > size * 0xff ||
1619             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1620                 return -E1000_ERR_NVM;
1621
1622         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1623                             hw->nvm.flash_base_addr;
1624
1625         do {
1626                 udelay(1);
1627                 /* Steps */
1628                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1629                 if (ret_val)
1630                         break;
1631
1632                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1633                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1634                 hsflctl.hsf_ctrl.fldbcount = size -1;
1635                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1636                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1637
1638                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1639
1640                 if (size == 1)
1641                         flash_data = (u32)data & 0x00FF;
1642                 else
1643                         flash_data = (u32)data;
1644
1645                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1646
1647                 /*
1648                  * check if FCERR is set to 1 , if set to 1, clear it
1649                  * and try the whole sequence a few more times else done
1650                  */
1651                 ret_val = e1000_flash_cycle_ich8lan(hw,
1652                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1653                 if (!ret_val)
1654                         break;
1655
1656                 /*
1657                  * If we're here, then things are most likely
1658                  * completely hosed, but if the error condition
1659                  * is detected, it won't hurt to give it another
1660                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1661                  */
1662                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1663                 if (hsfsts.hsf_status.flcerr == 1)
1664                         /* Repeat for some time before giving up. */
1665                         continue;
1666                 if (hsfsts.hsf_status.flcdone == 0) {
1667                         hw_dbg(hw, "Timeout error - flash cycle "
1668                                  "did not complete.");
1669                         break;
1670                 }
1671         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1672
1673         return ret_val;
1674 }
1675
1676 /**
1677  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1678  *  @hw: pointer to the HW structure
1679  *  @offset: The index of the byte to read.
1680  *  @data: The byte to write to the NVM.
1681  *
1682  *  Writes a single byte to the NVM using the flash access registers.
1683  **/
1684 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1685                                           u8 data)
1686 {
1687         u16 word = (u16)data;
1688
1689         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1690 }
1691
1692 /**
1693  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1694  *  @hw: pointer to the HW structure
1695  *  @offset: The offset of the byte to write.
1696  *  @byte: The byte to write to the NVM.
1697  *
1698  *  Writes a single byte to the NVM using the flash access registers.
1699  *  Goes through a retry algorithm before giving up.
1700  **/
1701 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1702                                                 u32 offset, u8 byte)
1703 {
1704         s32 ret_val;
1705         u16 program_retries;
1706
1707         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1708         if (!ret_val)
1709                 return ret_val;
1710
1711         for (program_retries = 0; program_retries < 100; program_retries++) {
1712                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1713                 udelay(100);
1714                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1715                 if (!ret_val)
1716                         break;
1717         }
1718         if (program_retries == 100)
1719                 return -E1000_ERR_NVM;
1720
1721         return 0;
1722 }
1723
1724 /**
1725  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1726  *  @hw: pointer to the HW structure
1727  *  @bank: 0 for first bank, 1 for second bank, etc.
1728  *
1729  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1730  *  bank N is 4096 * N + flash_reg_addr.
1731  **/
1732 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1733 {
1734         struct e1000_nvm_info *nvm = &hw->nvm;
1735         union ich8_hws_flash_status hsfsts;
1736         union ich8_hws_flash_ctrl hsflctl;
1737         u32 flash_linear_addr;
1738         /* bank size is in 16bit words - adjust to bytes */
1739         u32 flash_bank_size = nvm->flash_bank_size * 2;
1740         s32 ret_val;
1741         s32 count = 0;
1742         s32 iteration;
1743         s32 sector_size;
1744         s32 j;
1745
1746         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1747
1748         /*
1749          * Determine HW Sector size: Read BERASE bits of hw flash status
1750          * register
1751          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1752          *     consecutive sectors.  The start index for the nth Hw sector
1753          *     can be calculated as = bank * 4096 + n * 256
1754          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1755          *     The start index for the nth Hw sector can be calculated
1756          *     as = bank * 4096
1757          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1758          *     (ich9 only, otherwise error condition)
1759          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1760          */
1761         switch (hsfsts.hsf_status.berasesz) {
1762         case 0:
1763                 /* Hw sector size 256 */
1764                 sector_size = ICH_FLASH_SEG_SIZE_256;
1765                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1766                 break;
1767         case 1:
1768                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1769                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1770                 break;
1771         case 2:
1772                 if (hw->mac.type == e1000_ich9lan) {
1773                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1774                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1775                 } else {
1776                         return -E1000_ERR_NVM;
1777                 }
1778                 break;
1779         case 3:
1780                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1781                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1782                 break;
1783         default:
1784                 return -E1000_ERR_NVM;
1785         }
1786
1787         /* Start with the base address, then add the sector offset. */
1788         flash_linear_addr = hw->nvm.flash_base_addr;
1789         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1790
1791         for (j = 0; j < iteration ; j++) {
1792                 do {
1793                         /* Steps */
1794                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1795                         if (ret_val)
1796                                 return ret_val;
1797
1798                         /*
1799                          * Write a value 11 (block Erase) in Flash
1800                          * Cycle field in hw flash control
1801                          */
1802                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1803                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1804                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1805
1806                         /*
1807                          * Write the last 24 bits of an index within the
1808                          * block into Flash Linear address field in Flash
1809                          * Address.
1810                          */
1811                         flash_linear_addr += (j * sector_size);
1812                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1813
1814                         ret_val = e1000_flash_cycle_ich8lan(hw,
1815                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1816                         if (ret_val == 0)
1817                                 break;
1818
1819                         /*
1820                          * Check if FCERR is set to 1.  If 1,
1821                          * clear it and try the whole sequence
1822                          * a few more times else Done
1823                          */
1824                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1825                         if (hsfsts.hsf_status.flcerr == 1)
1826                                 /* repeat for some time before giving up */
1827                                 continue;
1828                         else if (hsfsts.hsf_status.flcdone == 0)
1829                                 return ret_val;
1830                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1831         }
1832
1833         return 0;
1834 }
1835
1836 /**
1837  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1838  *  @hw: pointer to the HW structure
1839  *  @data: Pointer to the LED settings
1840  *
1841  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1842  *  settings is all 0's or F's, set the LED default to a valid LED default
1843  *  setting.
1844  **/
1845 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1846 {
1847         s32 ret_val;
1848
1849         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1850         if (ret_val) {
1851                 hw_dbg(hw, "NVM Read Error\n");
1852                 return ret_val;
1853         }
1854
1855         if (*data == ID_LED_RESERVED_0000 ||
1856             *data == ID_LED_RESERVED_FFFF)
1857                 *data = ID_LED_DEFAULT_ICH8LAN;
1858
1859         return 0;
1860 }
1861
1862 /**
1863  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1864  *  @hw: pointer to the HW structure
1865  *
1866  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1867  *  register, so the the bus width is hard coded.
1868  **/
1869 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1870 {
1871         struct e1000_bus_info *bus = &hw->bus;
1872         s32 ret_val;
1873
1874         ret_val = e1000e_get_bus_info_pcie(hw);
1875
1876         /*
1877          * ICH devices are "PCI Express"-ish.  They have
1878          * a configuration space, but do not contain
1879          * PCI Express Capability registers, so bus width
1880          * must be hardcoded.
1881          */
1882         if (bus->width == e1000_bus_width_unknown)
1883                 bus->width = e1000_bus_width_pcie_x1;
1884
1885         return ret_val;
1886 }
1887
1888 /**
1889  *  e1000_reset_hw_ich8lan - Reset the hardware
1890  *  @hw: pointer to the HW structure
1891  *
1892  *  Does a full reset of the hardware which includes a reset of the PHY and
1893  *  MAC.
1894  **/
1895 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1896 {
1897         u32 ctrl, icr, kab;
1898         s32 ret_val;
1899
1900         /*
1901          * Prevent the PCI-E bus from sticking if there is no TLP connection
1902          * on the last TLP read/write transaction when MAC is reset.
1903          */
1904         ret_val = e1000e_disable_pcie_master(hw);
1905         if (ret_val) {
1906                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1907         }
1908
1909         hw_dbg(hw, "Masking off all interrupts\n");
1910         ew32(IMC, 0xffffffff);
1911
1912         /*
1913          * Disable the Transmit and Receive units.  Then delay to allow
1914          * any pending transactions to complete before we hit the MAC
1915          * with the global reset.
1916          */
1917         ew32(RCTL, 0);
1918         ew32(TCTL, E1000_TCTL_PSP);
1919         e1e_flush();
1920
1921         msleep(10);
1922
1923         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1924         if (hw->mac.type == e1000_ich8lan) {
1925                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1926                 ew32(PBA, E1000_PBA_8K);
1927                 /* Set Packet Buffer Size to 16k. */
1928                 ew32(PBS, E1000_PBS_16K);
1929         }
1930
1931         ctrl = er32(CTRL);
1932
1933         if (!e1000_check_reset_block(hw)) {
1934                 /*
1935                  * PHY HW reset requires MAC CORE reset at the same
1936                  * time to make sure the interface between MAC and the
1937                  * external PHY is reset.
1938                  */
1939                 ctrl |= E1000_CTRL_PHY_RST;
1940         }
1941         ret_val = e1000_acquire_swflag_ich8lan(hw);
1942         /* Whether or not the swflag was acquired, we need to reset the part */
1943         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
1944         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1945         msleep(20);
1946
1947         if (!ret_val) {
1948                 /* release the swflag because it is not reset by
1949                  * hardware reset
1950                  */
1951                 e1000_release_swflag_ich8lan(hw);
1952         }
1953
1954         ret_val = e1000e_get_auto_rd_done(hw);
1955         if (ret_val) {
1956                 /*
1957                  * When auto config read does not complete, do not
1958                  * return with an error. This can happen in situations
1959                  * where there is no eeprom and prevents getting link.
1960                  */
1961                 hw_dbg(hw, "Auto Read Done did not complete\n");
1962         }
1963
1964         ew32(IMC, 0xffffffff);
1965         icr = er32(ICR);
1966
1967         kab = er32(KABGTXD);
1968         kab |= E1000_KABGTXD_BGSQLBIAS;
1969         ew32(KABGTXD, kab);
1970
1971         return ret_val;
1972 }
1973
1974 /**
1975  *  e1000_init_hw_ich8lan - Initialize the hardware
1976  *  @hw: pointer to the HW structure
1977  *
1978  *  Prepares the hardware for transmit and receive by doing the following:
1979  *   - initialize hardware bits
1980  *   - initialize LED identification
1981  *   - setup receive address registers
1982  *   - setup flow control
1983  *   - setup transmit descriptors
1984  *   - clear statistics
1985  **/
1986 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1987 {
1988         struct e1000_mac_info *mac = &hw->mac;
1989         u32 ctrl_ext, txdctl, snoop;
1990         s32 ret_val;
1991         u16 i;
1992
1993         e1000_initialize_hw_bits_ich8lan(hw);
1994
1995         /* Initialize identification LED */
1996         ret_val = e1000e_id_led_init(hw);
1997         if (ret_val) {
1998                 hw_dbg(hw, "Error initializing identification LED\n");
1999                 return ret_val;
2000         }
2001
2002         /* Setup the receive address. */
2003         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2004
2005         /* Zero out the Multicast HASH table */
2006         hw_dbg(hw, "Zeroing the MTA\n");
2007         for (i = 0; i < mac->mta_reg_count; i++)
2008                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2009
2010         /* Setup link and flow control */
2011         ret_val = e1000_setup_link_ich8lan(hw);
2012
2013         /* Set the transmit descriptor write-back policy for both queues */
2014         txdctl = er32(TXDCTL(0));
2015         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2016                  E1000_TXDCTL_FULL_TX_DESC_WB;
2017         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2018                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2019         ew32(TXDCTL(0), txdctl);
2020         txdctl = er32(TXDCTL(1));
2021         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2022                  E1000_TXDCTL_FULL_TX_DESC_WB;
2023         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2024                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2025         ew32(TXDCTL(1), txdctl);
2026
2027         /*
2028          * ICH8 has opposite polarity of no_snoop bits.
2029          * By default, we should use snoop behavior.
2030          */
2031         if (mac->type == e1000_ich8lan)
2032                 snoop = PCIE_ICH8_SNOOP_ALL;
2033         else
2034                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2035         e1000e_set_pcie_no_snoop(hw, snoop);
2036
2037         ctrl_ext = er32(CTRL_EXT);
2038         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2039         ew32(CTRL_EXT, ctrl_ext);
2040
2041         /*
2042          * Clear all of the statistics registers (clear on read).  It is
2043          * important that we do this after we have tried to establish link
2044          * because the symbol error count will increment wildly if there
2045          * is no link.
2046          */
2047         e1000_clear_hw_cntrs_ich8lan(hw);
2048
2049         return 0;
2050 }
2051 /**
2052  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2053  *  @hw: pointer to the HW structure
2054  *
2055  *  Sets/Clears required hardware bits necessary for correctly setting up the
2056  *  hardware for transmit and receive.
2057  **/
2058 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2059 {
2060         u32 reg;
2061
2062         /* Extended Device Control */
2063         reg = er32(CTRL_EXT);
2064         reg |= (1 << 22);
2065         ew32(CTRL_EXT, reg);
2066
2067         /* Transmit Descriptor Control 0 */
2068         reg = er32(TXDCTL(0));
2069         reg |= (1 << 22);
2070         ew32(TXDCTL(0), reg);
2071
2072         /* Transmit Descriptor Control 1 */
2073         reg = er32(TXDCTL(1));
2074         reg |= (1 << 22);
2075         ew32(TXDCTL(1), reg);
2076
2077         /* Transmit Arbitration Control 0 */
2078         reg = er32(TARC(0));
2079         if (hw->mac.type == e1000_ich8lan)
2080                 reg |= (1 << 28) | (1 << 29);
2081         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2082         ew32(TARC(0), reg);
2083
2084         /* Transmit Arbitration Control 1 */
2085         reg = er32(TARC(1));
2086         if (er32(TCTL) & E1000_TCTL_MULR)
2087                 reg &= ~(1 << 28);
2088         else
2089                 reg |= (1 << 28);
2090         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2091         ew32(TARC(1), reg);
2092
2093         /* Device Status */
2094         if (hw->mac.type == e1000_ich8lan) {
2095                 reg = er32(STATUS);
2096                 reg &= ~(1 << 31);
2097                 ew32(STATUS, reg);
2098         }
2099 }
2100
2101 /**
2102  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2103  *  @hw: pointer to the HW structure
2104  *
2105  *  Determines which flow control settings to use, then configures flow
2106  *  control.  Calls the appropriate media-specific link configuration
2107  *  function.  Assuming the adapter has a valid link partner, a valid link
2108  *  should be established.  Assumes the hardware has previously been reset
2109  *  and the transmitter and receiver are not enabled.
2110  **/
2111 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2112 {
2113         s32 ret_val;
2114
2115         if (e1000_check_reset_block(hw))
2116                 return 0;
2117
2118         /*
2119          * ICH parts do not have a word in the NVM to determine
2120          * the default flow control setting, so we explicitly
2121          * set it to full.
2122          */
2123         if (hw->fc.requested_mode == e1000_fc_default)
2124                 hw->fc.requested_mode = e1000_fc_full;
2125
2126         /*
2127          * Save off the requested flow control mode for use later.  Depending
2128          * on the link partner's capabilities, we may or may not use this mode.
2129          */
2130         hw->fc.current_mode = hw->fc.requested_mode;
2131
2132         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2133                 hw->fc.current_mode);
2134
2135         /* Continue to configure the copper link. */
2136         ret_val = e1000_setup_copper_link_ich8lan(hw);
2137         if (ret_val)
2138                 return ret_val;
2139
2140         ew32(FCTTV, hw->fc.pause_time);
2141
2142         return e1000e_set_fc_watermarks(hw);
2143 }
2144
2145 /**
2146  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2147  *  @hw: pointer to the HW structure
2148  *
2149  *  Configures the kumeran interface to the PHY to wait the appropriate time
2150  *  when polling the PHY, then call the generic setup_copper_link to finish
2151  *  configuring the copper link.
2152  **/
2153 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2154 {
2155         u32 ctrl;
2156         s32 ret_val;
2157         u16 reg_data;
2158
2159         ctrl = er32(CTRL);
2160         ctrl |= E1000_CTRL_SLU;
2161         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2162         ew32(CTRL, ctrl);
2163
2164         /*
2165          * Set the mac to wait the maximum time between each iteration
2166          * and increase the max iterations when polling the phy;
2167          * this fixes erroneous timeouts at 10Mbps.
2168          */
2169         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2170         if (ret_val)
2171                 return ret_val;
2172         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2173         if (ret_val)
2174                 return ret_val;
2175         reg_data |= 0x3F;
2176         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2177         if (ret_val)
2178                 return ret_val;
2179
2180         if (hw->phy.type == e1000_phy_igp_3) {
2181                 ret_val = e1000e_copper_link_setup_igp(hw);
2182                 if (ret_val)
2183                         return ret_val;
2184         } else if (hw->phy.type == e1000_phy_bm) {
2185                 ret_val = e1000e_copper_link_setup_m88(hw);
2186                 if (ret_val)
2187                         return ret_val;
2188         }
2189
2190         if (hw->phy.type == e1000_phy_ife) {
2191                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2192                 if (ret_val)
2193                         return ret_val;
2194
2195                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2196
2197                 switch (hw->phy.mdix) {
2198                 case 1:
2199                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2200                         break;
2201                 case 2:
2202                         reg_data |= IFE_PMC_FORCE_MDIX;
2203                         break;
2204                 case 0:
2205                 default:
2206                         reg_data |= IFE_PMC_AUTO_MDIX;
2207                         break;
2208                 }
2209                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2210                 if (ret_val)
2211                         return ret_val;
2212         }
2213         return e1000e_setup_copper_link(hw);
2214 }
2215
2216 /**
2217  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2218  *  @hw: pointer to the HW structure
2219  *  @speed: pointer to store current link speed
2220  *  @duplex: pointer to store the current link duplex
2221  *
2222  *  Calls the generic get_speed_and_duplex to retrieve the current link
2223  *  information and then calls the Kumeran lock loss workaround for links at
2224  *  gigabit speeds.
2225  **/
2226 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2227                                           u16 *duplex)
2228 {
2229         s32 ret_val;
2230
2231         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2232         if (ret_val)
2233                 return ret_val;
2234
2235         if ((hw->mac.type == e1000_ich8lan) &&
2236             (hw->phy.type == e1000_phy_igp_3) &&
2237             (*speed == SPEED_1000)) {
2238                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2239         }
2240
2241         return ret_val;
2242 }
2243
2244 /**
2245  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2246  *  @hw: pointer to the HW structure
2247  *
2248  *  Work-around for 82566 Kumeran PCS lock loss:
2249  *  On link status change (i.e. PCI reset, speed change) and link is up and
2250  *  speed is gigabit-
2251  *    0) if workaround is optionally disabled do nothing
2252  *    1) wait 1ms for Kumeran link to come up
2253  *    2) check Kumeran Diagnostic register PCS lock loss bit
2254  *    3) if not set the link is locked (all is good), otherwise...
2255  *    4) reset the PHY
2256  *    5) repeat up to 10 times
2257  *  Note: this is only called for IGP3 copper when speed is 1gb.
2258  **/
2259 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2260 {
2261         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2262         u32 phy_ctrl;
2263         s32 ret_val;
2264         u16 i, data;
2265         bool link;
2266
2267         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2268                 return 0;
2269
2270         /*
2271          * Make sure link is up before proceeding.  If not just return.
2272          * Attempting this while link is negotiating fouled up link
2273          * stability
2274          */
2275         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2276         if (!link)
2277                 return 0;
2278
2279         for (i = 0; i < 10; i++) {
2280                 /* read once to clear */
2281                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2282                 if (ret_val)
2283                         return ret_val;
2284                 /* and again to get new status */
2285                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2286                 if (ret_val)
2287                         return ret_val;
2288
2289                 /* check for PCS lock */
2290                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2291                         return 0;
2292
2293                 /* Issue PHY reset */
2294                 e1000_phy_hw_reset(hw);
2295                 mdelay(5);
2296         }
2297         /* Disable GigE link negotiation */
2298         phy_ctrl = er32(PHY_CTRL);
2299         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2300                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2301         ew32(PHY_CTRL, phy_ctrl);
2302
2303         /*
2304          * Call gig speed drop workaround on Gig disable before accessing
2305          * any PHY registers
2306          */
2307         e1000e_gig_downshift_workaround_ich8lan(hw);
2308
2309         /* unable to acquire PCS lock */
2310         return -E1000_ERR_PHY;
2311 }
2312
2313 /**
2314  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2315  *  @hw: pointer to the HW structure
2316  *  @state: boolean value used to set the current Kumeran workaround state
2317  *
2318  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2319  *  /disabled - FALSE).
2320  **/
2321 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2322                                                  bool state)
2323 {
2324         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2325
2326         if (hw->mac.type != e1000_ich8lan) {
2327                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2328                 return;
2329         }
2330
2331         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2332 }
2333
2334 /**
2335  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2336  *  @hw: pointer to the HW structure
2337  *
2338  *  Workaround for 82566 power-down on D3 entry:
2339  *    1) disable gigabit link
2340  *    2) write VR power-down enable
2341  *    3) read it back
2342  *  Continue if successful, else issue LCD reset and repeat
2343  **/
2344 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2345 {
2346         u32 reg;
2347         u16 data;
2348         u8  retry = 0;
2349
2350         if (hw->phy.type != e1000_phy_igp_3)
2351                 return;
2352
2353         /* Try the workaround twice (if needed) */
2354         do {
2355                 /* Disable link */
2356                 reg = er32(PHY_CTRL);
2357                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2358                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2359                 ew32(PHY_CTRL, reg);
2360
2361                 /*
2362                  * Call gig speed drop workaround on Gig disable before
2363                  * accessing any PHY registers
2364                  */
2365                 if (hw->mac.type == e1000_ich8lan)
2366                         e1000e_gig_downshift_workaround_ich8lan(hw);
2367
2368                 /* Write VR power-down enable */
2369                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2370                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2371                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2372
2373                 /* Read it back and test */
2374                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2375                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2376                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2377                         break;
2378
2379                 /* Issue PHY reset and repeat at most one more time */
2380                 reg = er32(CTRL);
2381                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2382                 retry++;
2383         } while (retry);
2384 }
2385
2386 /**
2387  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2388  *  @hw: pointer to the HW structure
2389  *
2390  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2391  *  LPLU, Gig disable, MDIC PHY reset):
2392  *    1) Set Kumeran Near-end loopback
2393  *    2) Clear Kumeran Near-end loopback
2394  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2395  **/
2396 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2397 {
2398         s32 ret_val;
2399         u16 reg_data;
2400
2401         if ((hw->mac.type != e1000_ich8lan) ||
2402             (hw->phy.type != e1000_phy_igp_3))
2403                 return;
2404
2405         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2406                                       &reg_data);
2407         if (ret_val)
2408                 return;
2409         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2410         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2411                                        reg_data);
2412         if (ret_val)
2413                 return;
2414         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2415         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2416                                        reg_data);
2417 }
2418
2419 /**
2420  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2421  *  @hw: pointer to the HW structure
2422  *
2423  *  During S0 to Sx transition, it is possible the link remains at gig
2424  *  instead of negotiating to a lower speed.  Before going to Sx, set
2425  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2426  *  to a lower speed.
2427  *
2428  *  Should only be called for ICH9 and ICH10 devices.
2429  **/
2430 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2431 {
2432         u32 phy_ctrl;
2433
2434         if ((hw->mac.type == e1000_ich10lan) ||
2435             (hw->mac.type == e1000_ich9lan)) {
2436                 phy_ctrl = er32(PHY_CTRL);
2437                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2438                             E1000_PHY_CTRL_GBE_DISABLE;
2439                 ew32(PHY_CTRL, phy_ctrl);
2440         }
2441
2442         return;
2443 }
2444
2445 /**
2446  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2447  *  @hw: pointer to the HW structure
2448  *
2449  *  Return the LED back to the default configuration.
2450  **/
2451 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2452 {
2453         if (hw->phy.type == e1000_phy_ife)
2454                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2455
2456         ew32(LEDCTL, hw->mac.ledctl_default);
2457         return 0;
2458 }
2459
2460 /**
2461  *  e1000_led_on_ich8lan - Turn LEDs on
2462  *  @hw: pointer to the HW structure
2463  *
2464  *  Turn on the LEDs.
2465  **/
2466 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2467 {
2468         if (hw->phy.type == e1000_phy_ife)
2469                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2470                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2471
2472         ew32(LEDCTL, hw->mac.ledctl_mode2);
2473         return 0;
2474 }
2475
2476 /**
2477  *  e1000_led_off_ich8lan - Turn LEDs off
2478  *  @hw: pointer to the HW structure
2479  *
2480  *  Turn off the LEDs.
2481  **/
2482 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2483 {
2484         if (hw->phy.type == e1000_phy_ife)
2485                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2486                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2487
2488         ew32(LEDCTL, hw->mac.ledctl_mode1);
2489         return 0;
2490 }
2491
2492 /**
2493  *  e1000_get_cfg_done_ich8lan - Read config done bit
2494  *  @hw: pointer to the HW structure
2495  *
2496  *  Read the management control register for the config done bit for
2497  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2498  *  to read the config done bit, so an error is *ONLY* logged and returns
2499  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2500  *  would not be able to be reset or change link.
2501  **/
2502 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2503 {
2504         u32 bank = 0;
2505
2506         e1000e_get_cfg_done(hw);
2507
2508         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2509         if (hw->mac.type != e1000_ich10lan) {
2510                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2511                     (hw->phy.type == e1000_phy_igp_3)) {
2512                         e1000e_phy_init_script_igp3(hw);
2513                 }
2514         } else {
2515                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2516                         /* Maybe we should do a basic PHY config */
2517                         hw_dbg(hw, "EEPROM not present\n");
2518                         return -E1000_ERR_CONFIG;
2519                 }
2520         }
2521
2522         return 0;
2523 }
2524
2525 /**
2526  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2527  *  @hw: pointer to the HW structure
2528  *
2529  *  Clears hardware counters specific to the silicon family and calls
2530  *  clear_hw_cntrs_generic to clear all general purpose counters.
2531  **/
2532 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2533 {
2534         u32 temp;
2535
2536         e1000e_clear_hw_cntrs_base(hw);
2537
2538         temp = er32(ALGNERRC);
2539         temp = er32(RXERRC);
2540         temp = er32(TNCRS);
2541         temp = er32(CEXTERR);
2542         temp = er32(TSCTC);
2543         temp = er32(TSCTFC);
2544
2545         temp = er32(MGTPRC);
2546         temp = er32(MGTPDC);
2547         temp = er32(MGTPTC);
2548
2549         temp = er32(IAC);
2550         temp = er32(ICRXOC);
2551
2552 }
2553
2554 static struct e1000_mac_operations ich8_mac_ops = {
2555         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
2556         .check_for_link         = e1000e_check_for_copper_link,
2557         .cleanup_led            = e1000_cleanup_led_ich8lan,
2558         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2559         .get_bus_info           = e1000_get_bus_info_ich8lan,
2560         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2561         .led_on                 = e1000_led_on_ich8lan,
2562         .led_off                = e1000_led_off_ich8lan,
2563         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2564         .reset_hw               = e1000_reset_hw_ich8lan,
2565         .init_hw                = e1000_init_hw_ich8lan,
2566         .setup_link             = e1000_setup_link_ich8lan,
2567         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2568 };
2569
2570 static struct e1000_phy_operations ich8_phy_ops = {
2571         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2572         .check_reset_block      = e1000_check_reset_block_ich8lan,
2573         .commit_phy             = NULL,
2574         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2575         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2576         .get_cable_length       = e1000e_get_cable_length_igp_2,
2577         .get_phy_info           = e1000_get_phy_info_ich8lan,
2578         .read_phy_reg           = e1000e_read_phy_reg_igp,
2579         .release_phy            = e1000_release_swflag_ich8lan,
2580         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2581         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2582         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2583         .write_phy_reg          = e1000e_write_phy_reg_igp,
2584 };
2585
2586 static struct e1000_nvm_operations ich8_nvm_ops = {
2587         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2588         .read_nvm               = e1000_read_nvm_ich8lan,
2589         .release_nvm            = e1000_release_swflag_ich8lan,
2590         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2591         .valid_led_default      = e1000_valid_led_default_ich8lan,
2592         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2593         .write_nvm              = e1000_write_nvm_ich8lan,
2594 };
2595
2596 struct e1000_info e1000_ich8_info = {
2597         .mac                    = e1000_ich8lan,
2598         .flags                  = FLAG_HAS_WOL
2599                                   | FLAG_IS_ICH
2600                                   | FLAG_RX_CSUM_ENABLED
2601                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2602                                   | FLAG_HAS_AMT
2603                                   | FLAG_HAS_FLASH
2604                                   | FLAG_APME_IN_WUC,
2605         .pba                    = 8,
2606         .get_variants           = e1000_get_variants_ich8lan,
2607         .mac_ops                = &ich8_mac_ops,
2608         .phy_ops                = &ich8_phy_ops,
2609         .nvm_ops                = &ich8_nvm_ops,
2610 };
2611
2612 struct e1000_info e1000_ich9_info = {
2613         .mac                    = e1000_ich9lan,
2614         .flags                  = FLAG_HAS_JUMBO_FRAMES
2615                                   | FLAG_IS_ICH
2616                                   | FLAG_HAS_WOL
2617                                   | FLAG_RX_CSUM_ENABLED
2618                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2619                                   | FLAG_HAS_AMT
2620                                   | FLAG_HAS_ERT
2621                                   | FLAG_HAS_FLASH
2622                                   | FLAG_APME_IN_WUC,
2623         .pba                    = 10,
2624         .get_variants           = e1000_get_variants_ich8lan,
2625         .mac_ops                = &ich8_mac_ops,
2626         .phy_ops                = &ich8_phy_ops,
2627         .nvm_ops                = &ich8_nvm_ops,
2628 };
2629
2630 struct e1000_info e1000_ich10_info = {
2631         .mac                    = e1000_ich10lan,
2632         .flags                  = FLAG_HAS_JUMBO_FRAMES
2633                                   | FLAG_IS_ICH
2634                                   | FLAG_HAS_WOL
2635                                   | FLAG_RX_CSUM_ENABLED
2636                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2637                                   | FLAG_HAS_AMT
2638                                   | FLAG_HAS_ERT
2639                                   | FLAG_HAS_FLASH
2640                                   | FLAG_APME_IN_WUC,
2641         .pba                    = 10,
2642         .get_variants           = e1000_get_variants_ich8lan,
2643         .mac_ops                = &ich8_mac_ops,
2644         .phy_ops                = &ich8_phy_ops,
2645         .nvm_ops                = &ich8_nvm_ops,
2646 };