e1000e: MDIO slow mode should always be done for 82577
[linux-2.6.git] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 82562G 10/100 Network Connection
31  * 82562G-2 10/100 Network Connection
32  * 82562GT 10/100 Network Connection
33  * 82562GT-2 10/100 Network Connection
34  * 82562V 10/100 Network Connection
35  * 82562V-2 10/100 Network Connection
36  * 82566DC-2 Gigabit Network Connection
37  * 82566DC Gigabit Network Connection
38  * 82566DM-2 Gigabit Network Connection
39  * 82566DM Gigabit Network Connection
40  * 82566MC Gigabit Network Connection
41  * 82566MM Gigabit Network Connection
42  * 82567LM Gigabit Network Connection
43  * 82567LF Gigabit Network Connection
44  * 82567V Gigabit Network Connection
45  * 82567LM-2 Gigabit Network Connection
46  * 82567LF-2 Gigabit Network Connection
47  * 82567V-2 Gigabit Network Connection
48  * 82567LF-3 Gigabit Network Connection
49  * 82567LM-3 Gigabit Network Connection
50  * 82567LM-4 Gigabit Network Connection
51  * 82577LM Gigabit Network Connection
52  * 82577LC Gigabit Network Connection
53  * 82578DM Gigabit Network Connection
54  * 82578DC Gigabit Network Connection
55  */
56
57 #include "e1000.h"
58
59 #define ICH_FLASH_GFPREG                0x0000
60 #define ICH_FLASH_HSFSTS                0x0004
61 #define ICH_FLASH_HSFCTL                0x0006
62 #define ICH_FLASH_FADDR                 0x0008
63 #define ICH_FLASH_FDATA0                0x0010
64 #define ICH_FLASH_PR0                   0x0074
65
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
71
72 #define ICH_CYCLE_READ                  0
73 #define ICH_CYCLE_WRITE                 2
74 #define ICH_CYCLE_ERASE                 3
75
76 #define FLASH_GFPREG_BASE_MASK          0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT         12
78
79 #define ICH_FLASH_SEG_SIZE_256          256
80 #define ICH_FLASH_SEG_SIZE_4K           4096
81 #define ICH_FLASH_SEG_SIZE_8K           8192
82 #define ICH_FLASH_SEG_SIZE_64K          65536
83
84
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86
87 #define E1000_ICH_MNG_IAMT_MODE         0x2
88
89 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
90                                  (ID_LED_DEF1_OFF2 <<  8) | \
91                                  (ID_LED_DEF1_ON2  <<  4) | \
92                                  (ID_LED_DEF1_DEF2))
93
94 #define E1000_ICH_NVM_SIG_WORD          0x13
95 #define E1000_ICH_NVM_SIG_MASK          0xC000
96 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
97 #define E1000_ICH_NVM_SIG_VALUE         0x80
98
99 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
100
101 #define E1000_FEXTNVM_SW_CONFIG         1
102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
103
104 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
105
106 #define E1000_ICH_RAR_ENTRIES           7
107
108 #define PHY_PAGE_SHIFT 5
109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110                            ((reg) & MAX_PHY_REG_ADDRESS))
111 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
112 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
113
114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
117
118 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
119
120 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
121
122 /* SMBus Address Phy Register */
123 #define HV_SMB_ADDR            PHY_REG(768, 26)
124 #define HV_SMB_ADDR_PEC_EN     0x0200
125 #define HV_SMB_ADDR_VALID      0x0080
126
127 /* Strapping Option Register - RO */
128 #define E1000_STRAP                     0x0000C
129 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
131
132 /* OEM Bits Phy Register */
133 #define HV_OEM_BITS            PHY_REG(768, 25)
134 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
135 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
137
138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
140
141 /* KMRN Mode Control */
142 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
143 #define HV_KMRN_MDIO_SLOW      0x0400
144
145 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
146 /* Offset 04h HSFSTS */
147 union ich8_hws_flash_status {
148         struct ich8_hsfsts {
149                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
150                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
151                 u16 dael       :1; /* bit 2 Direct Access error Log */
152                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
153                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
154                 u16 reserved1  :2; /* bit 13:6 Reserved */
155                 u16 reserved2  :6; /* bit 13:6 Reserved */
156                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
157                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
158         } hsf_status;
159         u16 regval;
160 };
161
162 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
163 /* Offset 06h FLCTL */
164 union ich8_hws_flash_ctrl {
165         struct ich8_hsflctl {
166                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
167                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
168                 u16 reserved   :5;   /* 7:3 Reserved  */
169                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
170                 u16 flockdn    :6;   /* 15:10 Reserved */
171         } hsf_ctrl;
172         u16 regval;
173 };
174
175 /* ICH Flash Region Access Permissions */
176 union ich8_hws_flash_regacc {
177         struct ich8_flracc {
178                 u32 grra      :8; /* 0:7 GbE region Read Access */
179                 u32 grwa      :8; /* 8:15 GbE region Write Access */
180                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
181                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
182         } hsf_flregacc;
183         u16 regval;
184 };
185
186 /* ICH Flash Protected Region */
187 union ich8_flash_protected_range {
188         struct ich8_pr {
189                 u32 base:13;     /* 0:12 Protected Range Base */
190                 u32 reserved1:2; /* 13:14 Reserved */
191                 u32 rpe:1;       /* 15 Read Protection Enable */
192                 u32 limit:13;    /* 16:28 Protected Range Limit */
193                 u32 reserved2:2; /* 29:30 Reserved */
194                 u32 wpe:1;       /* 31 Write Protection Enable */
195         } range;
196         u32 regval;
197 };
198
199 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
200 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
201 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
202 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
203 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
204                                                 u32 offset, u8 byte);
205 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
206                                          u8 *data);
207 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
208                                          u16 *data);
209 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
210                                          u8 size, u16 *data);
211 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
212 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
213 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
218 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
219 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
220 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
221 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
222 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
223 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
224 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
225 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
226 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
227
228 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
229 {
230         return readw(hw->flash_address + reg);
231 }
232
233 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
234 {
235         return readl(hw->flash_address + reg);
236 }
237
238 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
239 {
240         writew(val, hw->flash_address + reg);
241 }
242
243 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
244 {
245         writel(val, hw->flash_address + reg);
246 }
247
248 #define er16flash(reg)          __er16flash(hw, (reg))
249 #define er32flash(reg)          __er32flash(hw, (reg))
250 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
251 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
252
253 /**
254  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
255  *  @hw: pointer to the HW structure
256  *
257  *  Initialize family-specific PHY parameters and function pointers.
258  **/
259 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
260 {
261         struct e1000_phy_info *phy = &hw->phy;
262         s32 ret_val = 0;
263
264         phy->addr                     = 1;
265         phy->reset_delay_us           = 100;
266
267         phy->ops.read_reg             = e1000_read_phy_reg_hv;
268         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
269         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
270         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
271         phy->ops.write_reg            = e1000_write_phy_reg_hv;
272         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
273         phy->ops.power_up             = e1000_power_up_phy_copper;
274         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
275         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
276
277         phy->id = e1000_phy_unknown;
278         ret_val = e1000e_get_phy_id(hw);
279         if (ret_val)
280                 goto out;
281         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
282                 /*
283                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
284                  * set slow mode and try to get the PHY id again.
285                  */
286                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
287                 if (ret_val)
288                         goto out;
289                 ret_val = e1000e_get_phy_id(hw);
290                 if (ret_val)
291                         goto out;
292         }
293         phy->type = e1000e_get_phy_type_from_id(phy->id);
294
295         switch (phy->type) {
296         case e1000_phy_82577:
297                 phy->ops.check_polarity = e1000_check_polarity_82577;
298                 phy->ops.force_speed_duplex =
299                         e1000_phy_force_speed_duplex_82577;
300                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
301                 phy->ops.get_info = e1000_get_phy_info_82577;
302                 phy->ops.commit = e1000e_phy_sw_reset;
303         case e1000_phy_82578:
304                 phy->ops.check_polarity = e1000_check_polarity_m88;
305                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
306                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
307                 phy->ops.get_info = e1000e_get_phy_info_m88;
308                 break;
309         default:
310                 ret_val = -E1000_ERR_PHY;
311                 break;
312         }
313
314 out:
315         return ret_val;
316 }
317
318 /**
319  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
320  *  @hw: pointer to the HW structure
321  *
322  *  Initialize family-specific PHY parameters and function pointers.
323  **/
324 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
325 {
326         struct e1000_phy_info *phy = &hw->phy;
327         s32 ret_val;
328         u16 i = 0;
329
330         phy->addr                       = 1;
331         phy->reset_delay_us             = 100;
332
333         phy->ops.power_up               = e1000_power_up_phy_copper;
334         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
335
336         /*
337          * We may need to do this twice - once for IGP and if that fails,
338          * we'll set BM func pointers and try again
339          */
340         ret_val = e1000e_determine_phy_address(hw);
341         if (ret_val) {
342                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
343                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
344                 ret_val = e1000e_determine_phy_address(hw);
345                 if (ret_val) {
346                         e_dbg("Cannot determine PHY addr. Erroring out\n");
347                         return ret_val;
348                 }
349         }
350
351         phy->id = 0;
352         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
353                (i++ < 100)) {
354                 msleep(1);
355                 ret_val = e1000e_get_phy_id(hw);
356                 if (ret_val)
357                         return ret_val;
358         }
359
360         /* Verify phy id */
361         switch (phy->id) {
362         case IGP03E1000_E_PHY_ID:
363                 phy->type = e1000_phy_igp_3;
364                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
365                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
366                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
367                 phy->ops.get_info = e1000e_get_phy_info_igp;
368                 phy->ops.check_polarity = e1000_check_polarity_igp;
369                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
370                 break;
371         case IFE_E_PHY_ID:
372         case IFE_PLUS_E_PHY_ID:
373         case IFE_C_E_PHY_ID:
374                 phy->type = e1000_phy_ife;
375                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
376                 phy->ops.get_info = e1000_get_phy_info_ife;
377                 phy->ops.check_polarity = e1000_check_polarity_ife;
378                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
379                 break;
380         case BME1000_E_PHY_ID:
381                 phy->type = e1000_phy_bm;
382                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
383                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
384                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
385                 phy->ops.commit = e1000e_phy_sw_reset;
386                 phy->ops.get_info = e1000e_get_phy_info_m88;
387                 phy->ops.check_polarity = e1000_check_polarity_m88;
388                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
389                 break;
390         default:
391                 return -E1000_ERR_PHY;
392                 break;
393         }
394
395         return 0;
396 }
397
398 /**
399  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
400  *  @hw: pointer to the HW structure
401  *
402  *  Initialize family-specific NVM parameters and function
403  *  pointers.
404  **/
405 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
406 {
407         struct e1000_nvm_info *nvm = &hw->nvm;
408         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
409         u32 gfpreg, sector_base_addr, sector_end_addr;
410         u16 i;
411
412         /* Can't read flash registers if the register set isn't mapped. */
413         if (!hw->flash_address) {
414                 e_dbg("ERROR: Flash registers not mapped\n");
415                 return -E1000_ERR_CONFIG;
416         }
417
418         nvm->type = e1000_nvm_flash_sw;
419
420         gfpreg = er32flash(ICH_FLASH_GFPREG);
421
422         /*
423          * sector_X_addr is a "sector"-aligned address (4096 bytes)
424          * Add 1 to sector_end_addr since this sector is included in
425          * the overall size.
426          */
427         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
428         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
429
430         /* flash_base_addr is byte-aligned */
431         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
432
433         /*
434          * find total size of the NVM, then cut in half since the total
435          * size represents two separate NVM banks.
436          */
437         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
438                                 << FLASH_SECTOR_ADDR_SHIFT;
439         nvm->flash_bank_size /= 2;
440         /* Adjust to word count */
441         nvm->flash_bank_size /= sizeof(u16);
442
443         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
444
445         /* Clear shadow ram */
446         for (i = 0; i < nvm->word_size; i++) {
447                 dev_spec->shadow_ram[i].modified = false;
448                 dev_spec->shadow_ram[i].value    = 0xFFFF;
449         }
450
451         return 0;
452 }
453
454 /**
455  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
456  *  @hw: pointer to the HW structure
457  *
458  *  Initialize family-specific MAC parameters and function
459  *  pointers.
460  **/
461 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
462 {
463         struct e1000_hw *hw = &adapter->hw;
464         struct e1000_mac_info *mac = &hw->mac;
465
466         /* Set media type function pointer */
467         hw->phy.media_type = e1000_media_type_copper;
468
469         /* Set mta register count */
470         mac->mta_reg_count = 32;
471         /* Set rar entry count */
472         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
473         if (mac->type == e1000_ich8lan)
474                 mac->rar_entry_count--;
475         /* Set if manageability features are enabled. */
476         mac->arc_subsystem_valid = true;
477         /* Adaptive IFS supported */
478         mac->adaptive_ifs = true;
479
480         /* LED operations */
481         switch (mac->type) {
482         case e1000_ich8lan:
483         case e1000_ich9lan:
484         case e1000_ich10lan:
485                 /* ID LED init */
486                 mac->ops.id_led_init = e1000e_id_led_init;
487                 /* setup LED */
488                 mac->ops.setup_led = e1000e_setup_led_generic;
489                 /* cleanup LED */
490                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
491                 /* turn on/off LED */
492                 mac->ops.led_on = e1000_led_on_ich8lan;
493                 mac->ops.led_off = e1000_led_off_ich8lan;
494                 break;
495         case e1000_pchlan:
496                 /* ID LED init */
497                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
498                 /* setup LED */
499                 mac->ops.setup_led = e1000_setup_led_pchlan;
500                 /* cleanup LED */
501                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
502                 /* turn on/off LED */
503                 mac->ops.led_on = e1000_led_on_pchlan;
504                 mac->ops.led_off = e1000_led_off_pchlan;
505                 break;
506         default:
507                 break;
508         }
509
510         /* Enable PCS Lock-loss workaround for ICH8 */
511         if (mac->type == e1000_ich8lan)
512                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
513
514         return 0;
515 }
516
517 /**
518  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
519  *  @hw: pointer to the HW structure
520  *
521  *  Checks to see of the link status of the hardware has changed.  If a
522  *  change in link status has been detected, then we read the PHY registers
523  *  to get the current speed/duplex if link exists.
524  **/
525 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
526 {
527         struct e1000_mac_info *mac = &hw->mac;
528         s32 ret_val;
529         bool link;
530
531         /*
532          * We only want to go out to the PHY registers to see if Auto-Neg
533          * has completed and/or if our link status has changed.  The
534          * get_link_status flag is set upon receiving a Link Status
535          * Change or Rx Sequence Error interrupt.
536          */
537         if (!mac->get_link_status) {
538                 ret_val = 0;
539                 goto out;
540         }
541
542         /*
543          * First we want to see if the MII Status Register reports
544          * link.  If so, then we want to get the current speed/duplex
545          * of the PHY.
546          */
547         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
548         if (ret_val)
549                 goto out;
550
551         if (hw->mac.type == e1000_pchlan) {
552                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
553                 if (ret_val)
554                         goto out;
555         }
556
557         if (!link)
558                 goto out; /* No link detected */
559
560         mac->get_link_status = false;
561
562         if (hw->phy.type == e1000_phy_82578) {
563                 ret_val = e1000_link_stall_workaround_hv(hw);
564                 if (ret_val)
565                         goto out;
566         }
567
568         /*
569          * Check if there was DownShift, must be checked
570          * immediately after link-up
571          */
572         e1000e_check_downshift(hw);
573
574         /*
575          * If we are forcing speed/duplex, then we simply return since
576          * we have already determined whether we have link or not.
577          */
578         if (!mac->autoneg) {
579                 ret_val = -E1000_ERR_CONFIG;
580                 goto out;
581         }
582
583         /*
584          * Auto-Neg is enabled.  Auto Speed Detection takes care
585          * of MAC speed/duplex configuration.  So we only need to
586          * configure Collision Distance in the MAC.
587          */
588         e1000e_config_collision_dist(hw);
589
590         /*
591          * Configure Flow Control now that Auto-Neg has completed.
592          * First, we need to restore the desired flow control
593          * settings because we may have had to re-autoneg with a
594          * different link partner.
595          */
596         ret_val = e1000e_config_fc_after_link_up(hw);
597         if (ret_val)
598                 e_dbg("Error configuring flow control\n");
599
600 out:
601         return ret_val;
602 }
603
604 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
605 {
606         struct e1000_hw *hw = &adapter->hw;
607         s32 rc;
608
609         rc = e1000_init_mac_params_ich8lan(adapter);
610         if (rc)
611                 return rc;
612
613         rc = e1000_init_nvm_params_ich8lan(hw);
614         if (rc)
615                 return rc;
616
617         if (hw->mac.type == e1000_pchlan)
618                 rc = e1000_init_phy_params_pchlan(hw);
619         else
620                 rc = e1000_init_phy_params_ich8lan(hw);
621         if (rc)
622                 return rc;
623
624         if (adapter->hw.phy.type == e1000_phy_ife) {
625                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
626                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
627         }
628
629         if ((adapter->hw.mac.type == e1000_ich8lan) &&
630             (adapter->hw.phy.type == e1000_phy_igp_3))
631                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
632
633         return 0;
634 }
635
636 static DEFINE_MUTEX(nvm_mutex);
637
638 /**
639  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
640  *  @hw: pointer to the HW structure
641  *
642  *  Acquires the mutex for performing NVM operations.
643  **/
644 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
645 {
646         mutex_lock(&nvm_mutex);
647
648         return 0;
649 }
650
651 /**
652  *  e1000_release_nvm_ich8lan - Release NVM mutex
653  *  @hw: pointer to the HW structure
654  *
655  *  Releases the mutex used while performing NVM operations.
656  **/
657 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
658 {
659         mutex_unlock(&nvm_mutex);
660
661         return;
662 }
663
664 static DEFINE_MUTEX(swflag_mutex);
665
666 /**
667  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
668  *  @hw: pointer to the HW structure
669  *
670  *  Acquires the software control flag for performing PHY and select
671  *  MAC CSR accesses.
672  **/
673 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
674 {
675         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
676         s32 ret_val = 0;
677
678         mutex_lock(&swflag_mutex);
679
680         while (timeout) {
681                 extcnf_ctrl = er32(EXTCNF_CTRL);
682                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
683                         break;
684
685                 mdelay(1);
686                 timeout--;
687         }
688
689         if (!timeout) {
690                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
691                 ret_val = -E1000_ERR_CONFIG;
692                 goto out;
693         }
694
695         timeout = SW_FLAG_TIMEOUT;
696
697         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
698         ew32(EXTCNF_CTRL, extcnf_ctrl);
699
700         while (timeout) {
701                 extcnf_ctrl = er32(EXTCNF_CTRL);
702                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
703                         break;
704
705                 mdelay(1);
706                 timeout--;
707         }
708
709         if (!timeout) {
710                 e_dbg("Failed to acquire the semaphore.\n");
711                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
712                 ew32(EXTCNF_CTRL, extcnf_ctrl);
713                 ret_val = -E1000_ERR_CONFIG;
714                 goto out;
715         }
716
717 out:
718         if (ret_val)
719                 mutex_unlock(&swflag_mutex);
720
721         return ret_val;
722 }
723
724 /**
725  *  e1000_release_swflag_ich8lan - Release software control flag
726  *  @hw: pointer to the HW structure
727  *
728  *  Releases the software control flag for performing PHY and select
729  *  MAC CSR accesses.
730  **/
731 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
732 {
733         u32 extcnf_ctrl;
734
735         extcnf_ctrl = er32(EXTCNF_CTRL);
736         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
737         ew32(EXTCNF_CTRL, extcnf_ctrl);
738
739         mutex_unlock(&swflag_mutex);
740
741         return;
742 }
743
744 /**
745  *  e1000_check_mng_mode_ich8lan - Checks management mode
746  *  @hw: pointer to the HW structure
747  *
748  *  This checks if the adapter has manageability enabled.
749  *  This is a function pointer entry point only called by read/write
750  *  routines for the PHY and NVM parts.
751  **/
752 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
753 {
754         u32 fwsm;
755
756         fwsm = er32(FWSM);
757
758         return (fwsm & E1000_FWSM_MODE_MASK) ==
759                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
760 }
761
762 /**
763  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
764  *  @hw: pointer to the HW structure
765  *
766  *  Checks if firmware is blocking the reset of the PHY.
767  *  This is a function pointer entry point only called by
768  *  reset routines.
769  **/
770 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
771 {
772         u32 fwsm;
773
774         fwsm = er32(FWSM);
775
776         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
777 }
778
779 /**
780  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
781  *  @hw:   pointer to the HW structure
782  *
783  *  SW should configure the LCD from the NVM extended configuration region
784  *  as a workaround for certain parts.
785  **/
786 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
787 {
788         struct e1000_phy_info *phy = &hw->phy;
789         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
790         s32 ret_val;
791         u16 word_addr, reg_data, reg_addr, phy_page = 0;
792
793         ret_val = hw->phy.ops.acquire(hw);
794         if (ret_val)
795                 return ret_val;
796
797         /*
798          * Initialize the PHY from the NVM on ICH platforms.  This
799          * is needed due to an issue where the NVM configuration is
800          * not properly autoloaded after power transitions.
801          * Therefore, after each PHY reset, we will load the
802          * configuration data out of the NVM manually.
803          */
804         if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
805                 (hw->mac.type == e1000_pchlan)) {
806                 struct e1000_adapter *adapter = hw->adapter;
807
808                 /* Check if SW needs to configure the PHY */
809                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
810                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
811                     (hw->mac.type == e1000_pchlan))
812                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
813                 else
814                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
815
816                 data = er32(FEXTNVM);
817                 if (!(data & sw_cfg_mask))
818                         goto out;
819
820                 /* Wait for basic configuration completes before proceeding */
821                 e1000_lan_init_done_ich8lan(hw);
822
823                 /*
824                  * Make sure HW does not configure LCD from PHY
825                  * extended configuration before SW configuration
826                  */
827                 data = er32(EXTCNF_CTRL);
828                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
829                         goto out;
830
831                 cnf_size = er32(EXTCNF_SIZE);
832                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
833                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
834                 if (!cnf_size)
835                         goto out;
836
837                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
838                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
839
840                 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
841                     (hw->mac.type == e1000_pchlan)) {
842                         /*
843                          * HW configures the SMBus address and LEDs when the
844                          * OEM and LCD Write Enable bits are set in the NVM.
845                          * When both NVM bits are cleared, SW will configure
846                          * them instead.
847                          */
848                         data = er32(STRAP);
849                         data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
850                         reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
851                         reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
852                         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
853                                                                 reg_data);
854                         if (ret_val)
855                                 goto out;
856
857                         data = er32(LEDCTL);
858                         ret_val = e1000_write_phy_reg_hv_locked(hw,
859                                                                 HV_LED_CONFIG,
860                                                                 (u16)data);
861                         if (ret_val)
862                                 goto out;
863                 }
864                 /* Configure LCD from extended configuration region. */
865
866                 /* cnf_base_addr is in DWORD */
867                 word_addr = (u16)(cnf_base_addr << 1);
868
869                 for (i = 0; i < cnf_size; i++) {
870                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
871                                                    &reg_data);
872                         if (ret_val)
873                                 goto out;
874
875                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
876                                                    1, &reg_addr);
877                         if (ret_val)
878                                 goto out;
879
880                         /* Save off the PHY page for future writes. */
881                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
882                                 phy_page = reg_data;
883                                 continue;
884                         }
885
886                         reg_addr &= PHY_REG_MASK;
887                         reg_addr |= phy_page;
888
889                         ret_val = phy->ops.write_reg_locked(hw,
890                                                             (u32)reg_addr,
891                                                             reg_data);
892                         if (ret_val)
893                                 goto out;
894                 }
895         }
896
897 out:
898         hw->phy.ops.release(hw);
899         return ret_val;
900 }
901
902 /**
903  *  e1000_k1_gig_workaround_hv - K1 Si workaround
904  *  @hw:   pointer to the HW structure
905  *  @link: link up bool flag
906  *
907  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
908  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
909  *  If link is down, the function will restore the default K1 setting located
910  *  in the NVM.
911  **/
912 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
913 {
914         s32 ret_val = 0;
915         u16 status_reg = 0;
916         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
917
918         if (hw->mac.type != e1000_pchlan)
919                 goto out;
920
921         /* Wrap the whole flow with the sw flag */
922         ret_val = hw->phy.ops.acquire(hw);
923         if (ret_val)
924                 goto out;
925
926         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
927         if (link) {
928                 if (hw->phy.type == e1000_phy_82578) {
929                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
930                                                                   &status_reg);
931                         if (ret_val)
932                                 goto release;
933
934                         status_reg &= BM_CS_STATUS_LINK_UP |
935                                       BM_CS_STATUS_RESOLVED |
936                                       BM_CS_STATUS_SPEED_MASK;
937
938                         if (status_reg == (BM_CS_STATUS_LINK_UP |
939                                            BM_CS_STATUS_RESOLVED |
940                                            BM_CS_STATUS_SPEED_1000))
941                                 k1_enable = false;
942                 }
943
944                 if (hw->phy.type == e1000_phy_82577) {
945                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
946                                                                   &status_reg);
947                         if (ret_val)
948                                 goto release;
949
950                         status_reg &= HV_M_STATUS_LINK_UP |
951                                       HV_M_STATUS_AUTONEG_COMPLETE |
952                                       HV_M_STATUS_SPEED_MASK;
953
954                         if (status_reg == (HV_M_STATUS_LINK_UP |
955                                            HV_M_STATUS_AUTONEG_COMPLETE |
956                                            HV_M_STATUS_SPEED_1000))
957                                 k1_enable = false;
958                 }
959
960                 /* Link stall fix for link up */
961                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
962                                                            0x0100);
963                 if (ret_val)
964                         goto release;
965
966         } else {
967                 /* Link stall fix for link down */
968                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
969                                                            0x4100);
970                 if (ret_val)
971                         goto release;
972         }
973
974         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
975
976 release:
977         hw->phy.ops.release(hw);
978 out:
979         return ret_val;
980 }
981
982 /**
983  *  e1000_configure_k1_ich8lan - Configure K1 power state
984  *  @hw: pointer to the HW structure
985  *  @enable: K1 state to configure
986  *
987  *  Configure the K1 power state based on the provided parameter.
988  *  Assumes semaphore already acquired.
989  *
990  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
991  **/
992 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
993 {
994         s32 ret_val = 0;
995         u32 ctrl_reg = 0;
996         u32 ctrl_ext = 0;
997         u32 reg = 0;
998         u16 kmrn_reg = 0;
999
1000         ret_val = e1000e_read_kmrn_reg_locked(hw,
1001                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1002                                              &kmrn_reg);
1003         if (ret_val)
1004                 goto out;
1005
1006         if (k1_enable)
1007                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1008         else
1009                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1010
1011         ret_val = e1000e_write_kmrn_reg_locked(hw,
1012                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1013                                               kmrn_reg);
1014         if (ret_val)
1015                 goto out;
1016
1017         udelay(20);
1018         ctrl_ext = er32(CTRL_EXT);
1019         ctrl_reg = er32(CTRL);
1020
1021         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1022         reg |= E1000_CTRL_FRCSPD;
1023         ew32(CTRL, reg);
1024
1025         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1026         udelay(20);
1027         ew32(CTRL, ctrl_reg);
1028         ew32(CTRL_EXT, ctrl_ext);
1029         udelay(20);
1030
1031 out:
1032         return ret_val;
1033 }
1034
1035 /**
1036  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1037  *  @hw:       pointer to the HW structure
1038  *  @d0_state: boolean if entering d0 or d3 device state
1039  *
1040  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1041  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1042  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1043  **/
1044 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1045 {
1046         s32 ret_val = 0;
1047         u32 mac_reg;
1048         u16 oem_reg;
1049
1050         if (hw->mac.type != e1000_pchlan)
1051                 return ret_val;
1052
1053         ret_val = hw->phy.ops.acquire(hw);
1054         if (ret_val)
1055                 return ret_val;
1056
1057         mac_reg = er32(EXTCNF_CTRL);
1058         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1059                 goto out;
1060
1061         mac_reg = er32(FEXTNVM);
1062         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1063                 goto out;
1064
1065         mac_reg = er32(PHY_CTRL);
1066
1067         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1068         if (ret_val)
1069                 goto out;
1070
1071         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1072
1073         if (d0_state) {
1074                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1075                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1076
1077                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1078                         oem_reg |= HV_OEM_BITS_LPLU;
1079         } else {
1080                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1081                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1082
1083                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1084                         oem_reg |= HV_OEM_BITS_LPLU;
1085         }
1086         /* Restart auto-neg to activate the bits */
1087         if (!e1000_check_reset_block(hw))
1088                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1089         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1090
1091 out:
1092         hw->phy.ops.release(hw);
1093
1094         return ret_val;
1095 }
1096
1097
1098 /**
1099  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1100  *  @hw:   pointer to the HW structure
1101  **/
1102 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1103 {
1104         s32 ret_val;
1105         u16 data;
1106
1107         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1108         if (ret_val)
1109                 return ret_val;
1110
1111         data |= HV_KMRN_MDIO_SLOW;
1112
1113         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1114
1115         return ret_val;
1116 }
1117
1118 /**
1119  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1120  *  done after every PHY reset.
1121  **/
1122 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1123 {
1124         s32 ret_val = 0;
1125
1126         if (hw->mac.type != e1000_pchlan)
1127                 return ret_val;
1128
1129         /* Set MDIO slow mode before any other MDIO access */
1130         if (hw->phy.type == e1000_phy_82577) {
1131                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1132                 if (ret_val)
1133                         goto out;
1134         }
1135
1136         if (((hw->phy.type == e1000_phy_82577) &&
1137              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1138             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1139                 /* Disable generation of early preamble */
1140                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1141                 if (ret_val)
1142                         return ret_val;
1143
1144                 /* Preamble tuning for SSC */
1145                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1146                 if (ret_val)
1147                         return ret_val;
1148         }
1149
1150         if (hw->phy.type == e1000_phy_82578) {
1151                 /*
1152                  * Return registers to default by doing a soft reset then
1153                  * writing 0x3140 to the control register.
1154                  */
1155                 if (hw->phy.revision < 2) {
1156                         e1000e_phy_sw_reset(hw);
1157                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1158                 }
1159         }
1160
1161         /* Select page 0 */
1162         ret_val = hw->phy.ops.acquire(hw);
1163         if (ret_val)
1164                 return ret_val;
1165
1166         hw->phy.addr = 1;
1167         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1168         if (ret_val)
1169                 goto out;
1170         hw->phy.ops.release(hw);
1171
1172         /*
1173          * Configure the K1 Si workaround during phy reset assuming there is
1174          * link so that it disables K1 if link is in 1Gbps.
1175          */
1176         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1177
1178 out:
1179         return ret_val;
1180 }
1181
1182 /**
1183  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1184  *  @hw: pointer to the HW structure
1185  *
1186  *  Check the appropriate indication the MAC has finished configuring the
1187  *  PHY after a software reset.
1188  **/
1189 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1190 {
1191         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1192
1193         /* Wait for basic configuration completes before proceeding */
1194         do {
1195                 data = er32(STATUS);
1196                 data &= E1000_STATUS_LAN_INIT_DONE;
1197                 udelay(100);
1198         } while ((!data) && --loop);
1199
1200         /*
1201          * If basic configuration is incomplete before the above loop
1202          * count reaches 0, loading the configuration from NVM will
1203          * leave the PHY in a bad state possibly resulting in no link.
1204          */
1205         if (loop == 0)
1206                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1207
1208         /* Clear the Init Done bit for the next init event */
1209         data = er32(STATUS);
1210         data &= ~E1000_STATUS_LAN_INIT_DONE;
1211         ew32(STATUS, data);
1212 }
1213
1214 /**
1215  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1216  *  @hw: pointer to the HW structure
1217  *
1218  *  Resets the PHY
1219  *  This is a function pointer entry point called by drivers
1220  *  or other shared routines.
1221  **/
1222 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1223 {
1224         s32 ret_val = 0;
1225         u16 reg;
1226
1227         ret_val = e1000e_phy_hw_reset_generic(hw);
1228         if (ret_val)
1229                 return ret_val;
1230
1231         /* Allow time for h/w to get to a quiescent state after reset */
1232         mdelay(10);
1233
1234         /* Perform any necessary post-reset workarounds */
1235         if (hw->mac.type == e1000_pchlan) {
1236                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1237                 if (ret_val)
1238                         return ret_val;
1239         }
1240
1241         /* Dummy read to clear the phy wakeup bit after lcd reset */
1242         if (hw->mac.type == e1000_pchlan)
1243                 e1e_rphy(hw, BM_WUC, &reg);
1244
1245         /* Configure the LCD with the extended configuration region in NVM */
1246         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1247         if (ret_val)
1248                 goto out;
1249
1250         /* Configure the LCD with the OEM bits in NVM */
1251         if (hw->mac.type == e1000_pchlan)
1252                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1253
1254 out:
1255         return 0;
1256 }
1257
1258 /**
1259  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1260  *  @hw: pointer to the HW structure
1261  *  @active: true to enable LPLU, false to disable
1262  *
1263  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1264  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1265  *  the phy speed. This function will manually set the LPLU bit and restart
1266  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1267  *  since it configures the same bit.
1268  **/
1269 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1270 {
1271         s32 ret_val = 0;
1272         u16 oem_reg;
1273
1274         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1275         if (ret_val)
1276                 goto out;
1277
1278         if (active)
1279                 oem_reg |= HV_OEM_BITS_LPLU;
1280         else
1281                 oem_reg &= ~HV_OEM_BITS_LPLU;
1282
1283         oem_reg |= HV_OEM_BITS_RESTART_AN;
1284         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1285
1286 out:
1287         return ret_val;
1288 }
1289
1290 /**
1291  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1292  *  @hw: pointer to the HW structure
1293  *  @active: true to enable LPLU, false to disable
1294  *
1295  *  Sets the LPLU D0 state according to the active flag.  When
1296  *  activating LPLU this function also disables smart speed
1297  *  and vice versa.  LPLU will not be activated unless the
1298  *  device autonegotiation advertisement meets standards of
1299  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1300  *  This is a function pointer entry point only called by
1301  *  PHY setup routines.
1302  **/
1303 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1304 {
1305         struct e1000_phy_info *phy = &hw->phy;
1306         u32 phy_ctrl;
1307         s32 ret_val = 0;
1308         u16 data;
1309
1310         if (phy->type == e1000_phy_ife)
1311                 return ret_val;
1312
1313         phy_ctrl = er32(PHY_CTRL);
1314
1315         if (active) {
1316                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1317                 ew32(PHY_CTRL, phy_ctrl);
1318
1319                 if (phy->type != e1000_phy_igp_3)
1320                         return 0;
1321
1322                 /*
1323                  * Call gig speed drop workaround on LPLU before accessing
1324                  * any PHY registers
1325                  */
1326                 if (hw->mac.type == e1000_ich8lan)
1327                         e1000e_gig_downshift_workaround_ich8lan(hw);
1328
1329                 /* When LPLU is enabled, we should disable SmartSpeed */
1330                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1331                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1332                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1333                 if (ret_val)
1334                         return ret_val;
1335         } else {
1336                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1337                 ew32(PHY_CTRL, phy_ctrl);
1338
1339                 if (phy->type != e1000_phy_igp_3)
1340                         return 0;
1341
1342                 /*
1343                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1344                  * during Dx states where the power conservation is most
1345                  * important.  During driver activity we should enable
1346                  * SmartSpeed, so performance is maintained.
1347                  */
1348                 if (phy->smart_speed == e1000_smart_speed_on) {
1349                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1350                                            &data);
1351                         if (ret_val)
1352                                 return ret_val;
1353
1354                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1355                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1356                                            data);
1357                         if (ret_val)
1358                                 return ret_val;
1359                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1360                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1361                                            &data);
1362                         if (ret_val)
1363                                 return ret_val;
1364
1365                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1366                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1367                                            data);
1368                         if (ret_val)
1369                                 return ret_val;
1370                 }
1371         }
1372
1373         return 0;
1374 }
1375
1376 /**
1377  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1378  *  @hw: pointer to the HW structure
1379  *  @active: true to enable LPLU, false to disable
1380  *
1381  *  Sets the LPLU D3 state according to the active flag.  When
1382  *  activating LPLU this function also disables smart speed
1383  *  and vice versa.  LPLU will not be activated unless the
1384  *  device autonegotiation advertisement meets standards of
1385  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1386  *  This is a function pointer entry point only called by
1387  *  PHY setup routines.
1388  **/
1389 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1390 {
1391         struct e1000_phy_info *phy = &hw->phy;
1392         u32 phy_ctrl;
1393         s32 ret_val;
1394         u16 data;
1395
1396         phy_ctrl = er32(PHY_CTRL);
1397
1398         if (!active) {
1399                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1400                 ew32(PHY_CTRL, phy_ctrl);
1401
1402                 if (phy->type != e1000_phy_igp_3)
1403                         return 0;
1404
1405                 /*
1406                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1407                  * during Dx states where the power conservation is most
1408                  * important.  During driver activity we should enable
1409                  * SmartSpeed, so performance is maintained.
1410                  */
1411                 if (phy->smart_speed == e1000_smart_speed_on) {
1412                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1413                                            &data);
1414                         if (ret_val)
1415                                 return ret_val;
1416
1417                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1418                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1419                                            data);
1420                         if (ret_val)
1421                                 return ret_val;
1422                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1423                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1424                                            &data);
1425                         if (ret_val)
1426                                 return ret_val;
1427
1428                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1429                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1430                                            data);
1431                         if (ret_val)
1432                                 return ret_val;
1433                 }
1434         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1435                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1436                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1437                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1438                 ew32(PHY_CTRL, phy_ctrl);
1439
1440                 if (phy->type != e1000_phy_igp_3)
1441                         return 0;
1442
1443                 /*
1444                  * Call gig speed drop workaround on LPLU before accessing
1445                  * any PHY registers
1446                  */
1447                 if (hw->mac.type == e1000_ich8lan)
1448                         e1000e_gig_downshift_workaround_ich8lan(hw);
1449
1450                 /* When LPLU is enabled, we should disable SmartSpeed */
1451                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1452                 if (ret_val)
1453                         return ret_val;
1454
1455                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1456                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1457         }
1458
1459         return 0;
1460 }
1461
1462 /**
1463  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1464  *  @hw: pointer to the HW structure
1465  *  @bank:  pointer to the variable that returns the active bank
1466  *
1467  *  Reads signature byte from the NVM using the flash access registers.
1468  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1469  **/
1470 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1471 {
1472         u32 eecd;
1473         struct e1000_nvm_info *nvm = &hw->nvm;
1474         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1475         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1476         u8 sig_byte = 0;
1477         s32 ret_val = 0;
1478
1479         switch (hw->mac.type) {
1480         case e1000_ich8lan:
1481         case e1000_ich9lan:
1482                 eecd = er32(EECD);
1483                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1484                     E1000_EECD_SEC1VAL_VALID_MASK) {
1485                         if (eecd & E1000_EECD_SEC1VAL)
1486                                 *bank = 1;
1487                         else
1488                                 *bank = 0;
1489
1490                         return 0;
1491                 }
1492                 e_dbg("Unable to determine valid NVM bank via EEC - "
1493                        "reading flash signature\n");
1494                 /* fall-thru */
1495         default:
1496                 /* set bank to 0 in case flash read fails */
1497                 *bank = 0;
1498
1499                 /* Check bank 0 */
1500                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1501                                                         &sig_byte);
1502                 if (ret_val)
1503                         return ret_val;
1504                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1505                     E1000_ICH_NVM_SIG_VALUE) {
1506                         *bank = 0;
1507                         return 0;
1508                 }
1509
1510                 /* Check bank 1 */
1511                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1512                                                         bank1_offset,
1513                                                         &sig_byte);
1514                 if (ret_val)
1515                         return ret_val;
1516                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1517                     E1000_ICH_NVM_SIG_VALUE) {
1518                         *bank = 1;
1519                         return 0;
1520                 }
1521
1522                 e_dbg("ERROR: No valid NVM bank present\n");
1523                 return -E1000_ERR_NVM;
1524         }
1525
1526         return 0;
1527 }
1528
1529 /**
1530  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1531  *  @hw: pointer to the HW structure
1532  *  @offset: The offset (in bytes) of the word(s) to read.
1533  *  @words: Size of data to read in words
1534  *  @data: Pointer to the word(s) to read at offset.
1535  *
1536  *  Reads a word(s) from the NVM using the flash access registers.
1537  **/
1538 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1539                                   u16 *data)
1540 {
1541         struct e1000_nvm_info *nvm = &hw->nvm;
1542         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1543         u32 act_offset;
1544         s32 ret_val = 0;
1545         u32 bank = 0;
1546         u16 i, word;
1547
1548         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1549             (words == 0)) {
1550                 e_dbg("nvm parameter(s) out of bounds\n");
1551                 ret_val = -E1000_ERR_NVM;
1552                 goto out;
1553         }
1554
1555         nvm->ops.acquire(hw);
1556
1557         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1558         if (ret_val) {
1559                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1560                 bank = 0;
1561         }
1562
1563         act_offset = (bank) ? nvm->flash_bank_size : 0;
1564         act_offset += offset;
1565
1566         ret_val = 0;
1567         for (i = 0; i < words; i++) {
1568                 if ((dev_spec->shadow_ram) &&
1569                     (dev_spec->shadow_ram[offset+i].modified)) {
1570                         data[i] = dev_spec->shadow_ram[offset+i].value;
1571                 } else {
1572                         ret_val = e1000_read_flash_word_ich8lan(hw,
1573                                                                 act_offset + i,
1574                                                                 &word);
1575                         if (ret_val)
1576                                 break;
1577                         data[i] = word;
1578                 }
1579         }
1580
1581         nvm->ops.release(hw);
1582
1583 out:
1584         if (ret_val)
1585                 e_dbg("NVM read error: %d\n", ret_val);
1586
1587         return ret_val;
1588 }
1589
1590 /**
1591  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1592  *  @hw: pointer to the HW structure
1593  *
1594  *  This function does initial flash setup so that a new read/write/erase cycle
1595  *  can be started.
1596  **/
1597 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1598 {
1599         union ich8_hws_flash_status hsfsts;
1600         s32 ret_val = -E1000_ERR_NVM;
1601         s32 i = 0;
1602
1603         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1604
1605         /* Check if the flash descriptor is valid */
1606         if (hsfsts.hsf_status.fldesvalid == 0) {
1607                 e_dbg("Flash descriptor invalid.  "
1608                          "SW Sequencing must be used.");
1609                 return -E1000_ERR_NVM;
1610         }
1611
1612         /* Clear FCERR and DAEL in hw status by writing 1 */
1613         hsfsts.hsf_status.flcerr = 1;
1614         hsfsts.hsf_status.dael = 1;
1615
1616         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1617
1618         /*
1619          * Either we should have a hardware SPI cycle in progress
1620          * bit to check against, in order to start a new cycle or
1621          * FDONE bit should be changed in the hardware so that it
1622          * is 1 after hardware reset, which can then be used as an
1623          * indication whether a cycle is in progress or has been
1624          * completed.
1625          */
1626
1627         if (hsfsts.hsf_status.flcinprog == 0) {
1628                 /*
1629                  * There is no cycle running at present,
1630                  * so we can start a cycle.
1631                  * Begin by setting Flash Cycle Done.
1632                  */
1633                 hsfsts.hsf_status.flcdone = 1;
1634                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1635                 ret_val = 0;
1636         } else {
1637                 /*
1638                  * Otherwise poll for sometime so the current
1639                  * cycle has a chance to end before giving up.
1640                  */
1641                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1642                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1643                         if (hsfsts.hsf_status.flcinprog == 0) {
1644                                 ret_val = 0;
1645                                 break;
1646                         }
1647                         udelay(1);
1648                 }
1649                 if (ret_val == 0) {
1650                         /*
1651                          * Successful in waiting for previous cycle to timeout,
1652                          * now set the Flash Cycle Done.
1653                          */
1654                         hsfsts.hsf_status.flcdone = 1;
1655                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1656                 } else {
1657                         e_dbg("Flash controller busy, cannot get access");
1658                 }
1659         }
1660
1661         return ret_val;
1662 }
1663
1664 /**
1665  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1666  *  @hw: pointer to the HW structure
1667  *  @timeout: maximum time to wait for completion
1668  *
1669  *  This function starts a flash cycle and waits for its completion.
1670  **/
1671 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1672 {
1673         union ich8_hws_flash_ctrl hsflctl;
1674         union ich8_hws_flash_status hsfsts;
1675         s32 ret_val = -E1000_ERR_NVM;
1676         u32 i = 0;
1677
1678         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1679         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1680         hsflctl.hsf_ctrl.flcgo = 1;
1681         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1682
1683         /* wait till FDONE bit is set to 1 */
1684         do {
1685                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1686                 if (hsfsts.hsf_status.flcdone == 1)
1687                         break;
1688                 udelay(1);
1689         } while (i++ < timeout);
1690
1691         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1692                 return 0;
1693
1694         return ret_val;
1695 }
1696
1697 /**
1698  *  e1000_read_flash_word_ich8lan - Read word from flash
1699  *  @hw: pointer to the HW structure
1700  *  @offset: offset to data location
1701  *  @data: pointer to the location for storing the data
1702  *
1703  *  Reads the flash word at offset into data.  Offset is converted
1704  *  to bytes before read.
1705  **/
1706 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1707                                          u16 *data)
1708 {
1709         /* Must convert offset into bytes. */
1710         offset <<= 1;
1711
1712         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1713 }
1714
1715 /**
1716  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1717  *  @hw: pointer to the HW structure
1718  *  @offset: The offset of the byte to read.
1719  *  @data: Pointer to a byte to store the value read.
1720  *
1721  *  Reads a single byte from the NVM using the flash access registers.
1722  **/
1723 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1724                                          u8 *data)
1725 {
1726         s32 ret_val;
1727         u16 word = 0;
1728
1729         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1730         if (ret_val)
1731                 return ret_val;
1732
1733         *data = (u8)word;
1734
1735         return 0;
1736 }
1737
1738 /**
1739  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1740  *  @hw: pointer to the HW structure
1741  *  @offset: The offset (in bytes) of the byte or word to read.
1742  *  @size: Size of data to read, 1=byte 2=word
1743  *  @data: Pointer to the word to store the value read.
1744  *
1745  *  Reads a byte or word from the NVM using the flash access registers.
1746  **/
1747 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1748                                          u8 size, u16 *data)
1749 {
1750         union ich8_hws_flash_status hsfsts;
1751         union ich8_hws_flash_ctrl hsflctl;
1752         u32 flash_linear_addr;
1753         u32 flash_data = 0;
1754         s32 ret_val = -E1000_ERR_NVM;
1755         u8 count = 0;
1756
1757         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1758                 return -E1000_ERR_NVM;
1759
1760         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1761                             hw->nvm.flash_base_addr;
1762
1763         do {
1764                 udelay(1);
1765                 /* Steps */
1766                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1767                 if (ret_val != 0)
1768                         break;
1769
1770                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1771                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1772                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1773                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1774                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1775
1776                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1777
1778                 ret_val = e1000_flash_cycle_ich8lan(hw,
1779                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1780
1781                 /*
1782                  * Check if FCERR is set to 1, if set to 1, clear it
1783                  * and try the whole sequence a few more times, else
1784                  * read in (shift in) the Flash Data0, the order is
1785                  * least significant byte first msb to lsb
1786                  */
1787                 if (ret_val == 0) {
1788                         flash_data = er32flash(ICH_FLASH_FDATA0);
1789                         if (size == 1) {
1790                                 *data = (u8)(flash_data & 0x000000FF);
1791                         } else if (size == 2) {
1792                                 *data = (u16)(flash_data & 0x0000FFFF);
1793                         }
1794                         break;
1795                 } else {
1796                         /*
1797                          * If we've gotten here, then things are probably
1798                          * completely hosed, but if the error condition is
1799                          * detected, it won't hurt to give it another try...
1800                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1801                          */
1802                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1803                         if (hsfsts.hsf_status.flcerr == 1) {
1804                                 /* Repeat for some time before giving up. */
1805                                 continue;
1806                         } else if (hsfsts.hsf_status.flcdone == 0) {
1807                                 e_dbg("Timeout error - flash cycle "
1808                                          "did not complete.");
1809                                 break;
1810                         }
1811                 }
1812         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1813
1814         return ret_val;
1815 }
1816
1817 /**
1818  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1819  *  @hw: pointer to the HW structure
1820  *  @offset: The offset (in bytes) of the word(s) to write.
1821  *  @words: Size of data to write in words
1822  *  @data: Pointer to the word(s) to write at offset.
1823  *
1824  *  Writes a byte or word to the NVM using the flash access registers.
1825  **/
1826 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1827                                    u16 *data)
1828 {
1829         struct e1000_nvm_info *nvm = &hw->nvm;
1830         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1831         u16 i;
1832
1833         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1834             (words == 0)) {
1835                 e_dbg("nvm parameter(s) out of bounds\n");
1836                 return -E1000_ERR_NVM;
1837         }
1838
1839         nvm->ops.acquire(hw);
1840
1841         for (i = 0; i < words; i++) {
1842                 dev_spec->shadow_ram[offset+i].modified = true;
1843                 dev_spec->shadow_ram[offset+i].value = data[i];
1844         }
1845
1846         nvm->ops.release(hw);
1847
1848         return 0;
1849 }
1850
1851 /**
1852  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1853  *  @hw: pointer to the HW structure
1854  *
1855  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1856  *  which writes the checksum to the shadow ram.  The changes in the shadow
1857  *  ram are then committed to the EEPROM by processing each bank at a time
1858  *  checking for the modified bit and writing only the pending changes.
1859  *  After a successful commit, the shadow ram is cleared and is ready for
1860  *  future writes.
1861  **/
1862 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1863 {
1864         struct e1000_nvm_info *nvm = &hw->nvm;
1865         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1866         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1867         s32 ret_val;
1868         u16 data;
1869
1870         ret_val = e1000e_update_nvm_checksum_generic(hw);
1871         if (ret_val)
1872                 goto out;
1873
1874         if (nvm->type != e1000_nvm_flash_sw)
1875                 goto out;
1876
1877         nvm->ops.acquire(hw);
1878
1879         /*
1880          * We're writing to the opposite bank so if we're on bank 1,
1881          * write to bank 0 etc.  We also need to erase the segment that
1882          * is going to be written
1883          */
1884         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1885         if (ret_val) {
1886                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1887                 bank = 0;
1888         }
1889
1890         if (bank == 0) {
1891                 new_bank_offset = nvm->flash_bank_size;
1892                 old_bank_offset = 0;
1893                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1894                 if (ret_val) {
1895                         nvm->ops.release(hw);
1896                         goto out;
1897                 }
1898         } else {
1899                 old_bank_offset = nvm->flash_bank_size;
1900                 new_bank_offset = 0;
1901                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1902                 if (ret_val) {
1903                         nvm->ops.release(hw);
1904                         goto out;
1905                 }
1906         }
1907
1908         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1909                 /*
1910                  * Determine whether to write the value stored
1911                  * in the other NVM bank or a modified value stored
1912                  * in the shadow RAM
1913                  */
1914                 if (dev_spec->shadow_ram[i].modified) {
1915                         data = dev_spec->shadow_ram[i].value;
1916                 } else {
1917                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1918                                                                 old_bank_offset,
1919                                                                 &data);
1920                         if (ret_val)
1921                                 break;
1922                 }
1923
1924                 /*
1925                  * If the word is 0x13, then make sure the signature bits
1926                  * (15:14) are 11b until the commit has completed.
1927                  * This will allow us to write 10b which indicates the
1928                  * signature is valid.  We want to do this after the write
1929                  * has completed so that we don't mark the segment valid
1930                  * while the write is still in progress
1931                  */
1932                 if (i == E1000_ICH_NVM_SIG_WORD)
1933                         data |= E1000_ICH_NVM_SIG_MASK;
1934
1935                 /* Convert offset to bytes. */
1936                 act_offset = (i + new_bank_offset) << 1;
1937
1938                 udelay(100);
1939                 /* Write the bytes to the new bank. */
1940                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1941                                                                act_offset,
1942                                                                (u8)data);
1943                 if (ret_val)
1944                         break;
1945
1946                 udelay(100);
1947                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1948                                                           act_offset + 1,
1949                                                           (u8)(data >> 8));
1950                 if (ret_val)
1951                         break;
1952         }
1953
1954         /*
1955          * Don't bother writing the segment valid bits if sector
1956          * programming failed.
1957          */
1958         if (ret_val) {
1959                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1960                 e_dbg("Flash commit failed.\n");
1961                 nvm->ops.release(hw);
1962                 goto out;
1963         }
1964
1965         /*
1966          * Finally validate the new segment by setting bit 15:14
1967          * to 10b in word 0x13 , this can be done without an
1968          * erase as well since these bits are 11 to start with
1969          * and we need to change bit 14 to 0b
1970          */
1971         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1972         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1973         if (ret_val) {
1974                 nvm->ops.release(hw);
1975                 goto out;
1976         }
1977         data &= 0xBFFF;
1978         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1979                                                        act_offset * 2 + 1,
1980                                                        (u8)(data >> 8));
1981         if (ret_val) {
1982                 nvm->ops.release(hw);
1983                 goto out;
1984         }
1985
1986         /*
1987          * And invalidate the previously valid segment by setting
1988          * its signature word (0x13) high_byte to 0b. This can be
1989          * done without an erase because flash erase sets all bits
1990          * to 1's. We can write 1's to 0's without an erase
1991          */
1992         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1993         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1994         if (ret_val) {
1995                 nvm->ops.release(hw);
1996                 goto out;
1997         }
1998
1999         /* Great!  Everything worked, we can now clear the cached entries. */
2000         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2001                 dev_spec->shadow_ram[i].modified = false;
2002                 dev_spec->shadow_ram[i].value = 0xFFFF;
2003         }
2004
2005         nvm->ops.release(hw);
2006
2007         /*
2008          * Reload the EEPROM, or else modifications will not appear
2009          * until after the next adapter reset.
2010          */
2011         e1000e_reload_nvm(hw);
2012         msleep(10);
2013
2014 out:
2015         if (ret_val)
2016                 e_dbg("NVM update error: %d\n", ret_val);
2017
2018         return ret_val;
2019 }
2020
2021 /**
2022  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2023  *  @hw: pointer to the HW structure
2024  *
2025  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2026  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2027  *  calculated, in which case we need to calculate the checksum and set bit 6.
2028  **/
2029 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2030 {
2031         s32 ret_val;
2032         u16 data;
2033
2034         /*
2035          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2036          * needs to be fixed.  This bit is an indication that the NVM
2037          * was prepared by OEM software and did not calculate the
2038          * checksum...a likely scenario.
2039          */
2040         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2041         if (ret_val)
2042                 return ret_val;
2043
2044         if ((data & 0x40) == 0) {
2045                 data |= 0x40;
2046                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2047                 if (ret_val)
2048                         return ret_val;
2049                 ret_val = e1000e_update_nvm_checksum(hw);
2050                 if (ret_val)
2051                         return ret_val;
2052         }
2053
2054         return e1000e_validate_nvm_checksum_generic(hw);
2055 }
2056
2057 /**
2058  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2059  *  @hw: pointer to the HW structure
2060  *
2061  *  To prevent malicious write/erase of the NVM, set it to be read-only
2062  *  so that the hardware ignores all write/erase cycles of the NVM via
2063  *  the flash control registers.  The shadow-ram copy of the NVM will
2064  *  still be updated, however any updates to this copy will not stick
2065  *  across driver reloads.
2066  **/
2067 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2068 {
2069         struct e1000_nvm_info *nvm = &hw->nvm;
2070         union ich8_flash_protected_range pr0;
2071         union ich8_hws_flash_status hsfsts;
2072         u32 gfpreg;
2073
2074         nvm->ops.acquire(hw);
2075
2076         gfpreg = er32flash(ICH_FLASH_GFPREG);
2077
2078         /* Write-protect GbE Sector of NVM */
2079         pr0.regval = er32flash(ICH_FLASH_PR0);
2080         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2081         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2082         pr0.range.wpe = true;
2083         ew32flash(ICH_FLASH_PR0, pr0.regval);
2084
2085         /*
2086          * Lock down a subset of GbE Flash Control Registers, e.g.
2087          * PR0 to prevent the write-protection from being lifted.
2088          * Once FLOCKDN is set, the registers protected by it cannot
2089          * be written until FLOCKDN is cleared by a hardware reset.
2090          */
2091         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2092         hsfsts.hsf_status.flockdn = true;
2093         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2094
2095         nvm->ops.release(hw);
2096 }
2097
2098 /**
2099  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2100  *  @hw: pointer to the HW structure
2101  *  @offset: The offset (in bytes) of the byte/word to read.
2102  *  @size: Size of data to read, 1=byte 2=word
2103  *  @data: The byte(s) to write to the NVM.
2104  *
2105  *  Writes one/two bytes to the NVM using the flash access registers.
2106  **/
2107 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2108                                           u8 size, u16 data)
2109 {
2110         union ich8_hws_flash_status hsfsts;
2111         union ich8_hws_flash_ctrl hsflctl;
2112         u32 flash_linear_addr;
2113         u32 flash_data = 0;
2114         s32 ret_val;
2115         u8 count = 0;
2116
2117         if (size < 1 || size > 2 || data > size * 0xff ||
2118             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2119                 return -E1000_ERR_NVM;
2120
2121         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2122                             hw->nvm.flash_base_addr;
2123
2124         do {
2125                 udelay(1);
2126                 /* Steps */
2127                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2128                 if (ret_val)
2129                         break;
2130
2131                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2132                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2133                 hsflctl.hsf_ctrl.fldbcount = size -1;
2134                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2135                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2136
2137                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2138
2139                 if (size == 1)
2140                         flash_data = (u32)data & 0x00FF;
2141                 else
2142                         flash_data = (u32)data;
2143
2144                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2145
2146                 /*
2147                  * check if FCERR is set to 1 , if set to 1, clear it
2148                  * and try the whole sequence a few more times else done
2149                  */
2150                 ret_val = e1000_flash_cycle_ich8lan(hw,
2151                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2152                 if (!ret_val)
2153                         break;
2154
2155                 /*
2156                  * If we're here, then things are most likely
2157                  * completely hosed, but if the error condition
2158                  * is detected, it won't hurt to give it another
2159                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2160                  */
2161                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2162                 if (hsfsts.hsf_status.flcerr == 1)
2163                         /* Repeat for some time before giving up. */
2164                         continue;
2165                 if (hsfsts.hsf_status.flcdone == 0) {
2166                         e_dbg("Timeout error - flash cycle "
2167                                  "did not complete.");
2168                         break;
2169                 }
2170         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2171
2172         return ret_val;
2173 }
2174
2175 /**
2176  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2177  *  @hw: pointer to the HW structure
2178  *  @offset: The index of the byte to read.
2179  *  @data: The byte to write to the NVM.
2180  *
2181  *  Writes a single byte to the NVM using the flash access registers.
2182  **/
2183 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2184                                           u8 data)
2185 {
2186         u16 word = (u16)data;
2187
2188         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2189 }
2190
2191 /**
2192  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2193  *  @hw: pointer to the HW structure
2194  *  @offset: The offset of the byte to write.
2195  *  @byte: The byte to write to the NVM.
2196  *
2197  *  Writes a single byte to the NVM using the flash access registers.
2198  *  Goes through a retry algorithm before giving up.
2199  **/
2200 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2201                                                 u32 offset, u8 byte)
2202 {
2203         s32 ret_val;
2204         u16 program_retries;
2205
2206         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2207         if (!ret_val)
2208                 return ret_val;
2209
2210         for (program_retries = 0; program_retries < 100; program_retries++) {
2211                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2212                 udelay(100);
2213                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2214                 if (!ret_val)
2215                         break;
2216         }
2217         if (program_retries == 100)
2218                 return -E1000_ERR_NVM;
2219
2220         return 0;
2221 }
2222
2223 /**
2224  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2225  *  @hw: pointer to the HW structure
2226  *  @bank: 0 for first bank, 1 for second bank, etc.
2227  *
2228  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2229  *  bank N is 4096 * N + flash_reg_addr.
2230  **/
2231 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2232 {
2233         struct e1000_nvm_info *nvm = &hw->nvm;
2234         union ich8_hws_flash_status hsfsts;
2235         union ich8_hws_flash_ctrl hsflctl;
2236         u32 flash_linear_addr;
2237         /* bank size is in 16bit words - adjust to bytes */
2238         u32 flash_bank_size = nvm->flash_bank_size * 2;
2239         s32 ret_val;
2240         s32 count = 0;
2241         s32 j, iteration, sector_size;
2242
2243         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2244
2245         /*
2246          * Determine HW Sector size: Read BERASE bits of hw flash status
2247          * register
2248          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2249          *     consecutive sectors.  The start index for the nth Hw sector
2250          *     can be calculated as = bank * 4096 + n * 256
2251          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2252          *     The start index for the nth Hw sector can be calculated
2253          *     as = bank * 4096
2254          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2255          *     (ich9 only, otherwise error condition)
2256          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2257          */
2258         switch (hsfsts.hsf_status.berasesz) {
2259         case 0:
2260                 /* Hw sector size 256 */
2261                 sector_size = ICH_FLASH_SEG_SIZE_256;
2262                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2263                 break;
2264         case 1:
2265                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2266                 iteration = 1;
2267                 break;
2268         case 2:
2269                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2270                 iteration = 1;
2271                 break;
2272         case 3:
2273                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2274                 iteration = 1;
2275                 break;
2276         default:
2277                 return -E1000_ERR_NVM;
2278         }
2279
2280         /* Start with the base address, then add the sector offset. */
2281         flash_linear_addr = hw->nvm.flash_base_addr;
2282         flash_linear_addr += (bank) ? flash_bank_size : 0;
2283
2284         for (j = 0; j < iteration ; j++) {
2285                 do {
2286                         /* Steps */
2287                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2288                         if (ret_val)
2289                                 return ret_val;
2290
2291                         /*
2292                          * Write a value 11 (block Erase) in Flash
2293                          * Cycle field in hw flash control
2294                          */
2295                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2296                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2297                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2298
2299                         /*
2300                          * Write the last 24 bits of an index within the
2301                          * block into Flash Linear address field in Flash
2302                          * Address.
2303                          */
2304                         flash_linear_addr += (j * sector_size);
2305                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2306
2307                         ret_val = e1000_flash_cycle_ich8lan(hw,
2308                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2309                         if (ret_val == 0)
2310                                 break;
2311
2312                         /*
2313                          * Check if FCERR is set to 1.  If 1,
2314                          * clear it and try the whole sequence
2315                          * a few more times else Done
2316                          */
2317                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2318                         if (hsfsts.hsf_status.flcerr == 1)
2319                                 /* repeat for some time before giving up */
2320                                 continue;
2321                         else if (hsfsts.hsf_status.flcdone == 0)
2322                                 return ret_val;
2323                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2324         }
2325
2326         return 0;
2327 }
2328
2329 /**
2330  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2331  *  @hw: pointer to the HW structure
2332  *  @data: Pointer to the LED settings
2333  *
2334  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2335  *  settings is all 0's or F's, set the LED default to a valid LED default
2336  *  setting.
2337  **/
2338 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2339 {
2340         s32 ret_val;
2341
2342         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2343         if (ret_val) {
2344                 e_dbg("NVM Read Error\n");
2345                 return ret_val;
2346         }
2347
2348         if (*data == ID_LED_RESERVED_0000 ||
2349             *data == ID_LED_RESERVED_FFFF)
2350                 *data = ID_LED_DEFAULT_ICH8LAN;
2351
2352         return 0;
2353 }
2354
2355 /**
2356  *  e1000_id_led_init_pchlan - store LED configurations
2357  *  @hw: pointer to the HW structure
2358  *
2359  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2360  *  the PHY LED configuration register.
2361  *
2362  *  PCH also does not have an "always on" or "always off" mode which
2363  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2364  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2365  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2366  *  link based on logic in e1000_led_[on|off]_pchlan().
2367  **/
2368 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2369 {
2370         struct e1000_mac_info *mac = &hw->mac;
2371         s32 ret_val;
2372         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2373         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2374         u16 data, i, temp, shift;
2375
2376         /* Get default ID LED modes */
2377         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2378         if (ret_val)
2379                 goto out;
2380
2381         mac->ledctl_default = er32(LEDCTL);
2382         mac->ledctl_mode1 = mac->ledctl_default;
2383         mac->ledctl_mode2 = mac->ledctl_default;
2384
2385         for (i = 0; i < 4; i++) {
2386                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2387                 shift = (i * 5);
2388                 switch (temp) {
2389                 case ID_LED_ON1_DEF2:
2390                 case ID_LED_ON1_ON2:
2391                 case ID_LED_ON1_OFF2:
2392                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2393                         mac->ledctl_mode1 |= (ledctl_on << shift);
2394                         break;
2395                 case ID_LED_OFF1_DEF2:
2396                 case ID_LED_OFF1_ON2:
2397                 case ID_LED_OFF1_OFF2:
2398                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2399                         mac->ledctl_mode1 |= (ledctl_off << shift);
2400                         break;
2401                 default:
2402                         /* Do nothing */
2403                         break;
2404                 }
2405                 switch (temp) {
2406                 case ID_LED_DEF1_ON2:
2407                 case ID_LED_ON1_ON2:
2408                 case ID_LED_OFF1_ON2:
2409                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2410                         mac->ledctl_mode2 |= (ledctl_on << shift);
2411                         break;
2412                 case ID_LED_DEF1_OFF2:
2413                 case ID_LED_ON1_OFF2:
2414                 case ID_LED_OFF1_OFF2:
2415                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2416                         mac->ledctl_mode2 |= (ledctl_off << shift);
2417                         break;
2418                 default:
2419                         /* Do nothing */
2420                         break;
2421                 }
2422         }
2423
2424 out:
2425         return ret_val;
2426 }
2427
2428 /**
2429  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2430  *  @hw: pointer to the HW structure
2431  *
2432  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2433  *  register, so the the bus width is hard coded.
2434  **/
2435 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2436 {
2437         struct e1000_bus_info *bus = &hw->bus;
2438         s32 ret_val;
2439
2440         ret_val = e1000e_get_bus_info_pcie(hw);
2441
2442         /*
2443          * ICH devices are "PCI Express"-ish.  They have
2444          * a configuration space, but do not contain
2445          * PCI Express Capability registers, so bus width
2446          * must be hardcoded.
2447          */
2448         if (bus->width == e1000_bus_width_unknown)
2449                 bus->width = e1000_bus_width_pcie_x1;
2450
2451         return ret_val;
2452 }
2453
2454 /**
2455  *  e1000_reset_hw_ich8lan - Reset the hardware
2456  *  @hw: pointer to the HW structure
2457  *
2458  *  Does a full reset of the hardware which includes a reset of the PHY and
2459  *  MAC.
2460  **/
2461 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2462 {
2463         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2464         u16 reg;
2465         u32 ctrl, icr, kab;
2466         s32 ret_val;
2467
2468         /*
2469          * Prevent the PCI-E bus from sticking if there is no TLP connection
2470          * on the last TLP read/write transaction when MAC is reset.
2471          */
2472         ret_val = e1000e_disable_pcie_master(hw);
2473         if (ret_val) {
2474                 e_dbg("PCI-E Master disable polling has failed.\n");
2475         }
2476
2477         e_dbg("Masking off all interrupts\n");
2478         ew32(IMC, 0xffffffff);
2479
2480         /*
2481          * Disable the Transmit and Receive units.  Then delay to allow
2482          * any pending transactions to complete before we hit the MAC
2483          * with the global reset.
2484          */
2485         ew32(RCTL, 0);
2486         ew32(TCTL, E1000_TCTL_PSP);
2487         e1e_flush();
2488
2489         msleep(10);
2490
2491         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2492         if (hw->mac.type == e1000_ich8lan) {
2493                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2494                 ew32(PBA, E1000_PBA_8K);
2495                 /* Set Packet Buffer Size to 16k. */
2496                 ew32(PBS, E1000_PBS_16K);
2497         }
2498
2499         if (hw->mac.type == e1000_pchlan) {
2500                 /* Save the NVM K1 bit setting*/
2501                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2502                 if (ret_val)
2503                         return ret_val;
2504
2505                 if (reg & E1000_NVM_K1_ENABLE)
2506                         dev_spec->nvm_k1_enabled = true;
2507                 else
2508                         dev_spec->nvm_k1_enabled = false;
2509         }
2510
2511         ctrl = er32(CTRL);
2512
2513         if (!e1000_check_reset_block(hw)) {
2514                 /* Clear PHY Reset Asserted bit */
2515                 if (hw->mac.type >= e1000_pchlan) {
2516                         u32 status = er32(STATUS);
2517                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2518                 }
2519
2520                 /*
2521                  * PHY HW reset requires MAC CORE reset at the same
2522                  * time to make sure the interface between MAC and the
2523                  * external PHY is reset.
2524                  */
2525                 ctrl |= E1000_CTRL_PHY_RST;
2526         }
2527         ret_val = e1000_acquire_swflag_ich8lan(hw);
2528         e_dbg("Issuing a global reset to ich8lan\n");
2529         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2530         msleep(20);
2531
2532         if (!ret_val)
2533                 e1000_release_swflag_ich8lan(hw);
2534
2535         /* Perform any necessary post-reset workarounds */
2536         if (hw->mac.type == e1000_pchlan)
2537                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2538
2539         if (ctrl & E1000_CTRL_PHY_RST)
2540                 ret_val = hw->phy.ops.get_cfg_done(hw);
2541
2542         if (hw->mac.type >= e1000_ich10lan) {
2543                 e1000_lan_init_done_ich8lan(hw);
2544         } else {
2545                 ret_val = e1000e_get_auto_rd_done(hw);
2546                 if (ret_val) {
2547                         /*
2548                          * When auto config read does not complete, do not
2549                          * return with an error. This can happen in situations
2550                          * where there is no eeprom and prevents getting link.
2551                          */
2552                         e_dbg("Auto Read Done did not complete\n");
2553                 }
2554         }
2555         /* Dummy read to clear the phy wakeup bit after lcd reset */
2556         if (hw->mac.type == e1000_pchlan)
2557                 e1e_rphy(hw, BM_WUC, &reg);
2558
2559         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2560         if (ret_val)
2561                 goto out;
2562
2563         if (hw->mac.type == e1000_pchlan) {
2564                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2565                 if (ret_val)
2566                         goto out;
2567         }
2568         /*
2569          * For PCH, this write will make sure that any noise
2570          * will be detected as a CRC error and be dropped rather than show up
2571          * as a bad packet to the DMA engine.
2572          */
2573         if (hw->mac.type == e1000_pchlan)
2574                 ew32(CRC_OFFSET, 0x65656565);
2575
2576         ew32(IMC, 0xffffffff);
2577         icr = er32(ICR);
2578
2579         kab = er32(KABGTXD);
2580         kab |= E1000_KABGTXD_BGSQLBIAS;
2581         ew32(KABGTXD, kab);
2582
2583 out:
2584         return ret_val;
2585 }
2586
2587 /**
2588  *  e1000_init_hw_ich8lan - Initialize the hardware
2589  *  @hw: pointer to the HW structure
2590  *
2591  *  Prepares the hardware for transmit and receive by doing the following:
2592  *   - initialize hardware bits
2593  *   - initialize LED identification
2594  *   - setup receive address registers
2595  *   - setup flow control
2596  *   - setup transmit descriptors
2597  *   - clear statistics
2598  **/
2599 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2600 {
2601         struct e1000_mac_info *mac = &hw->mac;
2602         u32 ctrl_ext, txdctl, snoop;
2603         s32 ret_val;
2604         u16 i;
2605
2606         e1000_initialize_hw_bits_ich8lan(hw);
2607
2608         /* Initialize identification LED */
2609         ret_val = mac->ops.id_led_init(hw);
2610         if (ret_val)
2611                 e_dbg("Error initializing identification LED\n");
2612                 /* This is not fatal and we should not stop init due to this */
2613
2614         /* Setup the receive address. */
2615         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2616
2617         /* Zero out the Multicast HASH table */
2618         e_dbg("Zeroing the MTA\n");
2619         for (i = 0; i < mac->mta_reg_count; i++)
2620                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2621
2622         /*
2623          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2624          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2625          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2626          */
2627         if (hw->phy.type == e1000_phy_82578) {
2628                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2629                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2630                 if (ret_val)
2631                         return ret_val;
2632         }
2633
2634         /* Setup link and flow control */
2635         ret_val = e1000_setup_link_ich8lan(hw);
2636
2637         /* Set the transmit descriptor write-back policy for both queues */
2638         txdctl = er32(TXDCTL(0));
2639         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2640                  E1000_TXDCTL_FULL_TX_DESC_WB;
2641         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2642                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2643         ew32(TXDCTL(0), txdctl);
2644         txdctl = er32(TXDCTL(1));
2645         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2646                  E1000_TXDCTL_FULL_TX_DESC_WB;
2647         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2648                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2649         ew32(TXDCTL(1), txdctl);
2650
2651         /*
2652          * ICH8 has opposite polarity of no_snoop bits.
2653          * By default, we should use snoop behavior.
2654          */
2655         if (mac->type == e1000_ich8lan)
2656                 snoop = PCIE_ICH8_SNOOP_ALL;
2657         else
2658                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2659         e1000e_set_pcie_no_snoop(hw, snoop);
2660
2661         ctrl_ext = er32(CTRL_EXT);
2662         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2663         ew32(CTRL_EXT, ctrl_ext);
2664
2665         /*
2666          * Clear all of the statistics registers (clear on read).  It is
2667          * important that we do this after we have tried to establish link
2668          * because the symbol error count will increment wildly if there
2669          * is no link.
2670          */
2671         e1000_clear_hw_cntrs_ich8lan(hw);
2672
2673         return 0;
2674 }
2675 /**
2676  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2677  *  @hw: pointer to the HW structure
2678  *
2679  *  Sets/Clears required hardware bits necessary for correctly setting up the
2680  *  hardware for transmit and receive.
2681  **/
2682 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2683 {
2684         u32 reg;
2685
2686         /* Extended Device Control */
2687         reg = er32(CTRL_EXT);
2688         reg |= (1 << 22);
2689         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2690         if (hw->mac.type >= e1000_pchlan)
2691                 reg |= E1000_CTRL_EXT_PHYPDEN;
2692         ew32(CTRL_EXT, reg);
2693
2694         /* Transmit Descriptor Control 0 */
2695         reg = er32(TXDCTL(0));
2696         reg |= (1 << 22);
2697         ew32(TXDCTL(0), reg);
2698
2699         /* Transmit Descriptor Control 1 */
2700         reg = er32(TXDCTL(1));
2701         reg |= (1 << 22);
2702         ew32(TXDCTL(1), reg);
2703
2704         /* Transmit Arbitration Control 0 */
2705         reg = er32(TARC(0));
2706         if (hw->mac.type == e1000_ich8lan)
2707                 reg |= (1 << 28) | (1 << 29);
2708         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2709         ew32(TARC(0), reg);
2710
2711         /* Transmit Arbitration Control 1 */
2712         reg = er32(TARC(1));
2713         if (er32(TCTL) & E1000_TCTL_MULR)
2714                 reg &= ~(1 << 28);
2715         else
2716                 reg |= (1 << 28);
2717         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2718         ew32(TARC(1), reg);
2719
2720         /* Device Status */
2721         if (hw->mac.type == e1000_ich8lan) {
2722                 reg = er32(STATUS);
2723                 reg &= ~(1 << 31);
2724                 ew32(STATUS, reg);
2725         }
2726 }
2727
2728 /**
2729  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2730  *  @hw: pointer to the HW structure
2731  *
2732  *  Determines which flow control settings to use, then configures flow
2733  *  control.  Calls the appropriate media-specific link configuration
2734  *  function.  Assuming the adapter has a valid link partner, a valid link
2735  *  should be established.  Assumes the hardware has previously been reset
2736  *  and the transmitter and receiver are not enabled.
2737  **/
2738 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2739 {
2740         s32 ret_val;
2741
2742         if (e1000_check_reset_block(hw))
2743                 return 0;
2744
2745         /*
2746          * ICH parts do not have a word in the NVM to determine
2747          * the default flow control setting, so we explicitly
2748          * set it to full.
2749          */
2750         if (hw->fc.requested_mode == e1000_fc_default) {
2751                 /* Workaround h/w hang when Tx flow control enabled */
2752                 if (hw->mac.type == e1000_pchlan)
2753                         hw->fc.requested_mode = e1000_fc_rx_pause;
2754                 else
2755                         hw->fc.requested_mode = e1000_fc_full;
2756         }
2757
2758         /*
2759          * Save off the requested flow control mode for use later.  Depending
2760          * on the link partner's capabilities, we may or may not use this mode.
2761          */
2762         hw->fc.current_mode = hw->fc.requested_mode;
2763
2764         e_dbg("After fix-ups FlowControl is now = %x\n",
2765                 hw->fc.current_mode);
2766
2767         /* Continue to configure the copper link. */
2768         ret_val = e1000_setup_copper_link_ich8lan(hw);
2769         if (ret_val)
2770                 return ret_val;
2771
2772         ew32(FCTTV, hw->fc.pause_time);
2773         if ((hw->phy.type == e1000_phy_82578) ||
2774             (hw->phy.type == e1000_phy_82577)) {
2775                 ret_val = hw->phy.ops.write_reg(hw,
2776                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2777                                              hw->fc.pause_time);
2778                 if (ret_val)
2779                         return ret_val;
2780         }
2781
2782         return e1000e_set_fc_watermarks(hw);
2783 }
2784
2785 /**
2786  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2787  *  @hw: pointer to the HW structure
2788  *
2789  *  Configures the kumeran interface to the PHY to wait the appropriate time
2790  *  when polling the PHY, then call the generic setup_copper_link to finish
2791  *  configuring the copper link.
2792  **/
2793 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2794 {
2795         u32 ctrl;
2796         s32 ret_val;
2797         u16 reg_data;
2798
2799         ctrl = er32(CTRL);
2800         ctrl |= E1000_CTRL_SLU;
2801         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2802         ew32(CTRL, ctrl);
2803
2804         /*
2805          * Set the mac to wait the maximum time between each iteration
2806          * and increase the max iterations when polling the phy;
2807          * this fixes erroneous timeouts at 10Mbps.
2808          */
2809         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2810         if (ret_val)
2811                 return ret_val;
2812         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2813                                        &reg_data);
2814         if (ret_val)
2815                 return ret_val;
2816         reg_data |= 0x3F;
2817         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2818                                         reg_data);
2819         if (ret_val)
2820                 return ret_val;
2821
2822         switch (hw->phy.type) {
2823         case e1000_phy_igp_3:
2824                 ret_val = e1000e_copper_link_setup_igp(hw);
2825                 if (ret_val)
2826                         return ret_val;
2827                 break;
2828         case e1000_phy_bm:
2829         case e1000_phy_82578:
2830                 ret_val = e1000e_copper_link_setup_m88(hw);
2831                 if (ret_val)
2832                         return ret_val;
2833                 break;
2834         case e1000_phy_82577:
2835                 ret_val = e1000_copper_link_setup_82577(hw);
2836                 if (ret_val)
2837                         return ret_val;
2838                 break;
2839         case e1000_phy_ife:
2840                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2841                                                &reg_data);
2842                 if (ret_val)
2843                         return ret_val;
2844
2845                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2846
2847                 switch (hw->phy.mdix) {
2848                 case 1:
2849                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2850                         break;
2851                 case 2:
2852                         reg_data |= IFE_PMC_FORCE_MDIX;
2853                         break;
2854                 case 0:
2855                 default:
2856                         reg_data |= IFE_PMC_AUTO_MDIX;
2857                         break;
2858                 }
2859                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2860                                                 reg_data);
2861                 if (ret_val)
2862                         return ret_val;
2863                 break;
2864         default:
2865                 break;
2866         }
2867         return e1000e_setup_copper_link(hw);
2868 }
2869
2870 /**
2871  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2872  *  @hw: pointer to the HW structure
2873  *  @speed: pointer to store current link speed
2874  *  @duplex: pointer to store the current link duplex
2875  *
2876  *  Calls the generic get_speed_and_duplex to retrieve the current link
2877  *  information and then calls the Kumeran lock loss workaround for links at
2878  *  gigabit speeds.
2879  **/
2880 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2881                                           u16 *duplex)
2882 {
2883         s32 ret_val;
2884
2885         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2886         if (ret_val)
2887                 return ret_val;
2888
2889         if ((hw->mac.type == e1000_ich8lan) &&
2890             (hw->phy.type == e1000_phy_igp_3) &&
2891             (*speed == SPEED_1000)) {
2892                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2893         }
2894
2895         return ret_val;
2896 }
2897
2898 /**
2899  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2900  *  @hw: pointer to the HW structure
2901  *
2902  *  Work-around for 82566 Kumeran PCS lock loss:
2903  *  On link status change (i.e. PCI reset, speed change) and link is up and
2904  *  speed is gigabit-
2905  *    0) if workaround is optionally disabled do nothing
2906  *    1) wait 1ms for Kumeran link to come up
2907  *    2) check Kumeran Diagnostic register PCS lock loss bit
2908  *    3) if not set the link is locked (all is good), otherwise...
2909  *    4) reset the PHY
2910  *    5) repeat up to 10 times
2911  *  Note: this is only called for IGP3 copper when speed is 1gb.
2912  **/
2913 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2914 {
2915         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2916         u32 phy_ctrl;
2917         s32 ret_val;
2918         u16 i, data;
2919         bool link;
2920
2921         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2922                 return 0;
2923
2924         /*
2925          * Make sure link is up before proceeding.  If not just return.
2926          * Attempting this while link is negotiating fouled up link
2927          * stability
2928          */
2929         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2930         if (!link)
2931                 return 0;
2932
2933         for (i = 0; i < 10; i++) {
2934                 /* read once to clear */
2935                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2936                 if (ret_val)
2937                         return ret_val;
2938                 /* and again to get new status */
2939                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2940                 if (ret_val)
2941                         return ret_val;
2942
2943                 /* check for PCS lock */
2944                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2945                         return 0;
2946
2947                 /* Issue PHY reset */
2948                 e1000_phy_hw_reset(hw);
2949                 mdelay(5);
2950         }
2951         /* Disable GigE link negotiation */
2952         phy_ctrl = er32(PHY_CTRL);
2953         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2954                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2955         ew32(PHY_CTRL, phy_ctrl);
2956
2957         /*
2958          * Call gig speed drop workaround on Gig disable before accessing
2959          * any PHY registers
2960          */
2961         e1000e_gig_downshift_workaround_ich8lan(hw);
2962
2963         /* unable to acquire PCS lock */
2964         return -E1000_ERR_PHY;
2965 }
2966
2967 /**
2968  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2969  *  @hw: pointer to the HW structure
2970  *  @state: boolean value used to set the current Kumeran workaround state
2971  *
2972  *  If ICH8, set the current Kumeran workaround state (enabled - true
2973  *  /disabled - false).
2974  **/
2975 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2976                                                  bool state)
2977 {
2978         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2979
2980         if (hw->mac.type != e1000_ich8lan) {
2981                 e_dbg("Workaround applies to ICH8 only.\n");
2982                 return;
2983         }
2984
2985         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2986 }
2987
2988 /**
2989  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2990  *  @hw: pointer to the HW structure
2991  *
2992  *  Workaround for 82566 power-down on D3 entry:
2993  *    1) disable gigabit link
2994  *    2) write VR power-down enable
2995  *    3) read it back
2996  *  Continue if successful, else issue LCD reset and repeat
2997  **/
2998 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2999 {
3000         u32 reg;
3001         u16 data;
3002         u8  retry = 0;
3003
3004         if (hw->phy.type != e1000_phy_igp_3)
3005                 return;
3006
3007         /* Try the workaround twice (if needed) */
3008         do {
3009                 /* Disable link */
3010                 reg = er32(PHY_CTRL);
3011                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3012                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3013                 ew32(PHY_CTRL, reg);
3014
3015                 /*
3016                  * Call gig speed drop workaround on Gig disable before
3017                  * accessing any PHY registers
3018                  */
3019                 if (hw->mac.type == e1000_ich8lan)
3020                         e1000e_gig_downshift_workaround_ich8lan(hw);
3021
3022                 /* Write VR power-down enable */
3023                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3024                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3025                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3026
3027                 /* Read it back and test */
3028                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3029                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3030                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3031                         break;
3032
3033                 /* Issue PHY reset and repeat at most one more time */
3034                 reg = er32(CTRL);
3035                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3036                 retry++;
3037         } while (retry);
3038 }
3039
3040 /**
3041  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3042  *  @hw: pointer to the HW structure
3043  *
3044  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3045  *  LPLU, Gig disable, MDIC PHY reset):
3046  *    1) Set Kumeran Near-end loopback
3047  *    2) Clear Kumeran Near-end loopback
3048  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3049  **/
3050 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3051 {
3052         s32 ret_val;
3053         u16 reg_data;
3054
3055         if ((hw->mac.type != e1000_ich8lan) ||
3056             (hw->phy.type != e1000_phy_igp_3))
3057                 return;
3058
3059         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3060                                       &reg_data);
3061         if (ret_val)
3062                 return;
3063         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3064         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3065                                        reg_data);
3066         if (ret_val)
3067                 return;
3068         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3069         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3070                                        reg_data);
3071 }
3072
3073 /**
3074  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3075  *  @hw: pointer to the HW structure
3076  *
3077  *  During S0 to Sx transition, it is possible the link remains at gig
3078  *  instead of negotiating to a lower speed.  Before going to Sx, set
3079  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3080  *  to a lower speed.
3081  *
3082  *  Should only be called for applicable parts.
3083  **/
3084 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3085 {
3086         u32 phy_ctrl;
3087
3088         switch (hw->mac.type) {
3089         case e1000_ich8lan:
3090         case e1000_ich9lan:
3091         case e1000_ich10lan:
3092         case e1000_pchlan:
3093                 phy_ctrl = er32(PHY_CTRL);
3094                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3095                             E1000_PHY_CTRL_GBE_DISABLE;
3096                 ew32(PHY_CTRL, phy_ctrl);
3097
3098                 if (hw->mac.type == e1000_pchlan)
3099                         e1000_phy_hw_reset_ich8lan(hw);
3100         default:
3101                 break;
3102         }
3103
3104         return;
3105 }
3106
3107 /**
3108  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3109  *  @hw: pointer to the HW structure
3110  *
3111  *  Return the LED back to the default configuration.
3112  **/
3113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3114 {
3115         if (hw->phy.type == e1000_phy_ife)
3116                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3117
3118         ew32(LEDCTL, hw->mac.ledctl_default);
3119         return 0;
3120 }
3121
3122 /**
3123  *  e1000_led_on_ich8lan - Turn LEDs on
3124  *  @hw: pointer to the HW structure
3125  *
3126  *  Turn on the LEDs.
3127  **/
3128 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3129 {
3130         if (hw->phy.type == e1000_phy_ife)
3131                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3132                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3133
3134         ew32(LEDCTL, hw->mac.ledctl_mode2);
3135         return 0;
3136 }
3137
3138 /**
3139  *  e1000_led_off_ich8lan - Turn LEDs off
3140  *  @hw: pointer to the HW structure
3141  *
3142  *  Turn off the LEDs.
3143  **/
3144 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3145 {
3146         if (hw->phy.type == e1000_phy_ife)
3147                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3148                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3149
3150         ew32(LEDCTL, hw->mac.ledctl_mode1);
3151         return 0;
3152 }
3153
3154 /**
3155  *  e1000_setup_led_pchlan - Configures SW controllable LED
3156  *  @hw: pointer to the HW structure
3157  *
3158  *  This prepares the SW controllable LED for use.
3159  **/
3160 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3161 {
3162         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3163                                         (u16)hw->mac.ledctl_mode1);
3164 }
3165
3166 /**
3167  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3168  *  @hw: pointer to the HW structure
3169  *
3170  *  Return the LED back to the default configuration.
3171  **/
3172 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3173 {
3174         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3175                                         (u16)hw->mac.ledctl_default);
3176 }
3177
3178 /**
3179  *  e1000_led_on_pchlan - Turn LEDs on
3180  *  @hw: pointer to the HW structure
3181  *
3182  *  Turn on the LEDs.
3183  **/
3184 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3185 {
3186         u16 data = (u16)hw->mac.ledctl_mode2;
3187         u32 i, led;
3188
3189         /*
3190          * If no link, then turn LED on by setting the invert bit
3191          * for each LED that's mode is "link_up" in ledctl_mode2.
3192          */
3193         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3194                 for (i = 0; i < 3; i++) {
3195                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3196                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3197                             E1000_LEDCTL_MODE_LINK_UP)
3198                                 continue;
3199                         if (led & E1000_PHY_LED0_IVRT)
3200                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3201                         else
3202                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3203                 }
3204         }
3205
3206         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3207 }
3208
3209 /**
3210  *  e1000_led_off_pchlan - Turn LEDs off
3211  *  @hw: pointer to the HW structure
3212  *
3213  *  Turn off the LEDs.
3214  **/
3215 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3216 {
3217         u16 data = (u16)hw->mac.ledctl_mode1;
3218         u32 i, led;
3219
3220         /*
3221          * If no link, then turn LED off by clearing the invert bit
3222          * for each LED that's mode is "link_up" in ledctl_mode1.
3223          */
3224         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3225                 for (i = 0; i < 3; i++) {
3226                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3227                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3228                             E1000_LEDCTL_MODE_LINK_UP)
3229                                 continue;
3230                         if (led & E1000_PHY_LED0_IVRT)
3231                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3232                         else
3233                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3234                 }
3235         }
3236
3237         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3238 }
3239
3240 /**
3241  *  e1000_get_cfg_done_ich8lan - Read config done bit
3242  *  @hw: pointer to the HW structure
3243  *
3244  *  Read the management control register for the config done bit for
3245  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3246  *  to read the config done bit, so an error is *ONLY* logged and returns
3247  *  0.  If we were to return with error, EEPROM-less silicon
3248  *  would not be able to be reset or change link.
3249  **/
3250 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3251 {
3252         u32 bank = 0;
3253
3254         if (hw->mac.type >= e1000_pchlan) {
3255                 u32 status = er32(STATUS);
3256
3257                 if (status & E1000_STATUS_PHYRA)
3258                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3259                 else
3260                         e_dbg("PHY Reset Asserted not set - needs delay\n");
3261         }
3262
3263         e1000e_get_cfg_done(hw);
3264
3265         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3266         if ((hw->mac.type != e1000_ich10lan) &&
3267             (hw->mac.type != e1000_pchlan)) {
3268                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3269                     (hw->phy.type == e1000_phy_igp_3)) {
3270                         e1000e_phy_init_script_igp3(hw);
3271                 }
3272         } else {
3273                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3274                         /* Maybe we should do a basic PHY config */
3275                         e_dbg("EEPROM not present\n");
3276                         return -E1000_ERR_CONFIG;
3277                 }
3278         }
3279
3280         return 0;
3281 }
3282
3283 /**
3284  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3285  * @hw: pointer to the HW structure
3286  *
3287  * In the case of a PHY power down to save power, or to turn off link during a
3288  * driver unload, or wake on lan is not enabled, remove the link.
3289  **/
3290 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3291 {
3292         /* If the management interface is not enabled, then power down */
3293         if (!(hw->mac.ops.check_mng_mode(hw) ||
3294               hw->phy.ops.check_reset_block(hw)))
3295                 e1000_power_down_phy_copper(hw);
3296
3297         return;
3298 }
3299
3300 /**
3301  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3302  *  @hw: pointer to the HW structure
3303  *
3304  *  Clears hardware counters specific to the silicon family and calls
3305  *  clear_hw_cntrs_generic to clear all general purpose counters.
3306  **/
3307 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3308 {
3309         u16 phy_data;
3310
3311         e1000e_clear_hw_cntrs_base(hw);
3312
3313         er32(ALGNERRC);
3314         er32(RXERRC);
3315         er32(TNCRS);
3316         er32(CEXTERR);
3317         er32(TSCTC);
3318         er32(TSCTFC);
3319
3320         er32(MGTPRC);
3321         er32(MGTPDC);
3322         er32(MGTPTC);
3323
3324         er32(IAC);
3325         er32(ICRXOC);
3326
3327         /* Clear PHY statistics registers */
3328         if ((hw->phy.type == e1000_phy_82578) ||
3329             (hw->phy.type == e1000_phy_82577)) {
3330                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3331                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3332                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3333                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3334                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3335                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3336                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3337                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3338                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3339                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3340                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3341                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3342                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3343                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3344         }
3345 }
3346
3347 static struct e1000_mac_operations ich8_mac_ops = {
3348         .id_led_init            = e1000e_id_led_init,
3349         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3350         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3351         /* cleanup_led dependent on mac type */
3352         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3353         .get_bus_info           = e1000_get_bus_info_ich8lan,
3354         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3355         /* led_on dependent on mac type */
3356         /* led_off dependent on mac type */
3357         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3358         .reset_hw               = e1000_reset_hw_ich8lan,
3359         .init_hw                = e1000_init_hw_ich8lan,
3360         .setup_link             = e1000_setup_link_ich8lan,
3361         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3362         /* id_led_init dependent on mac type */
3363 };
3364
3365 static struct e1000_phy_operations ich8_phy_ops = {
3366         .acquire                = e1000_acquire_swflag_ich8lan,
3367         .check_reset_block      = e1000_check_reset_block_ich8lan,
3368         .commit                 = NULL,
3369         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3370         .get_cable_length       = e1000e_get_cable_length_igp_2,
3371         .read_reg               = e1000e_read_phy_reg_igp,
3372         .release                = e1000_release_swflag_ich8lan,
3373         .reset                  = e1000_phy_hw_reset_ich8lan,
3374         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3375         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3376         .write_reg              = e1000e_write_phy_reg_igp,
3377 };
3378
3379 static struct e1000_nvm_operations ich8_nvm_ops = {
3380         .acquire                = e1000_acquire_nvm_ich8lan,
3381         .read                   = e1000_read_nvm_ich8lan,
3382         .release                = e1000_release_nvm_ich8lan,
3383         .update                 = e1000_update_nvm_checksum_ich8lan,
3384         .valid_led_default      = e1000_valid_led_default_ich8lan,
3385         .validate               = e1000_validate_nvm_checksum_ich8lan,
3386         .write                  = e1000_write_nvm_ich8lan,
3387 };
3388
3389 struct e1000_info e1000_ich8_info = {
3390         .mac                    = e1000_ich8lan,
3391         .flags                  = FLAG_HAS_WOL
3392                                   | FLAG_IS_ICH
3393                                   | FLAG_RX_CSUM_ENABLED
3394                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3395                                   | FLAG_HAS_AMT
3396                                   | FLAG_HAS_FLASH
3397                                   | FLAG_APME_IN_WUC,
3398         .pba                    = 8,
3399         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3400         .get_variants           = e1000_get_variants_ich8lan,
3401         .mac_ops                = &ich8_mac_ops,
3402         .phy_ops                = &ich8_phy_ops,
3403         .nvm_ops                = &ich8_nvm_ops,
3404 };
3405
3406 struct e1000_info e1000_ich9_info = {
3407         .mac                    = e1000_ich9lan,
3408         .flags                  = FLAG_HAS_JUMBO_FRAMES
3409                                   | FLAG_IS_ICH
3410                                   | FLAG_HAS_WOL
3411                                   | FLAG_RX_CSUM_ENABLED
3412                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3413                                   | FLAG_HAS_AMT
3414                                   | FLAG_HAS_ERT
3415                                   | FLAG_HAS_FLASH
3416                                   | FLAG_APME_IN_WUC,
3417         .pba                    = 10,
3418         .max_hw_frame_size      = DEFAULT_JUMBO,
3419         .get_variants           = e1000_get_variants_ich8lan,
3420         .mac_ops                = &ich8_mac_ops,
3421         .phy_ops                = &ich8_phy_ops,
3422         .nvm_ops                = &ich8_nvm_ops,
3423 };
3424
3425 struct e1000_info e1000_ich10_info = {
3426         .mac                    = e1000_ich10lan,
3427         .flags                  = FLAG_HAS_JUMBO_FRAMES
3428                                   | FLAG_IS_ICH
3429                                   | FLAG_HAS_WOL
3430                                   | FLAG_RX_CSUM_ENABLED
3431                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3432                                   | FLAG_HAS_AMT
3433                                   | FLAG_HAS_ERT
3434                                   | FLAG_HAS_FLASH
3435                                   | FLAG_APME_IN_WUC,
3436         .pba                    = 10,
3437         .max_hw_frame_size      = DEFAULT_JUMBO,
3438         .get_variants           = e1000_get_variants_ich8lan,
3439         .mac_ops                = &ich8_mac_ops,
3440         .phy_ops                = &ich8_phy_ops,
3441         .nvm_ops                = &ich8_nvm_ops,
3442 };
3443
3444 struct e1000_info e1000_pch_info = {
3445         .mac                    = e1000_pchlan,
3446         .flags                  = FLAG_IS_ICH
3447                                   | FLAG_HAS_WOL
3448                                   | FLAG_RX_CSUM_ENABLED
3449                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3450                                   | FLAG_HAS_AMT
3451                                   | FLAG_HAS_FLASH
3452                                   | FLAG_HAS_JUMBO_FRAMES
3453                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3454                                   | FLAG_APME_IN_WUC,
3455         .pba                    = 26,
3456         .max_hw_frame_size      = 4096,
3457         .get_variants           = e1000_get_variants_ich8lan,
3458         .mac_ops                = &ich8_mac_ops,
3459         .phy_ops                = &ich8_phy_ops,
3460         .nvm_ops                = &ich8_nvm_ops,
3461 };