b5fc2c90304436682e91a659ca5d9f849ef8cbee
[linux-2.6.git] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 82562G-2 10/100 Network Connection
31  * 82562GT 10/100 Network Connection
32  * 82562GT-2 10/100 Network Connection
33  * 82562V 10/100 Network Connection
34  * 82562V-2 10/100 Network Connection
35  * 82566DC-2 Gigabit Network Connection
36  * 82566DC Gigabit Network Connection
37  * 82566DM-2 Gigabit Network Connection
38  * 82566DM Gigabit Network Connection
39  * 82566MC Gigabit Network Connection
40  * 82566MM Gigabit Network Connection
41  * 82567LM Gigabit Network Connection
42  * 82567LF Gigabit Network Connection
43  * 82567LM-2 Gigabit Network Connection
44  * 82567LF-2 Gigabit Network Connection
45  * 82567V-2 Gigabit Network Connection
46  * 82562GT-3 10/100 Network Connection
47  * 82567LM-4 Gigabit Network Connection
48  */
49
50 #include <linux/netdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/delay.h>
53 #include <linux/pci.h>
54
55 #include "e1000.h"
56
57 #define ICH_FLASH_GFPREG                0x0000
58 #define ICH_FLASH_HSFSTS                0x0004
59 #define ICH_FLASH_HSFCTL                0x0006
60 #define ICH_FLASH_FADDR                 0x0008
61 #define ICH_FLASH_FDATA0                0x0010
62
63 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
64 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
65 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
66 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
67 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
68
69 #define ICH_CYCLE_READ                  0
70 #define ICH_CYCLE_WRITE                 2
71 #define ICH_CYCLE_ERASE                 3
72
73 #define FLASH_GFPREG_BASE_MASK          0x1FFF
74 #define FLASH_SECTOR_ADDR_SHIFT         12
75
76 #define ICH_FLASH_SEG_SIZE_256          256
77 #define ICH_FLASH_SEG_SIZE_4K           4096
78 #define ICH_FLASH_SEG_SIZE_8K           8192
79 #define ICH_FLASH_SEG_SIZE_64K          65536
80
81
82 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
83
84 #define E1000_ICH_MNG_IAMT_MODE         0x2
85
86 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
87                                  (ID_LED_DEF1_OFF2 <<  8) | \
88                                  (ID_LED_DEF1_ON2  <<  4) | \
89                                  (ID_LED_DEF1_DEF2))
90
91 #define E1000_ICH_NVM_SIG_WORD          0x13
92 #define E1000_ICH_NVM_SIG_MASK          0xC000
93
94 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
95
96 #define E1000_FEXTNVM_SW_CONFIG         1
97 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
98
99 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
100
101 #define E1000_ICH_RAR_ENTRIES           7
102
103 #define PHY_PAGE_SHIFT 5
104 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
105                            ((reg) & MAX_PHY_REG_ADDRESS))
106 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
107 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
108
109 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
110 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
111 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
112
113 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
114 /* Offset 04h HSFSTS */
115 union ich8_hws_flash_status {
116         struct ich8_hsfsts {
117                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
118                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
119                 u16 dael       :1; /* bit 2 Direct Access error Log */
120                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
121                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
122                 u16 reserved1  :2; /* bit 13:6 Reserved */
123                 u16 reserved2  :6; /* bit 13:6 Reserved */
124                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
125                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
126         } hsf_status;
127         u16 regval;
128 };
129
130 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
131 /* Offset 06h FLCTL */
132 union ich8_hws_flash_ctrl {
133         struct ich8_hsflctl {
134                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
135                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
136                 u16 reserved   :5;   /* 7:3 Reserved  */
137                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
138                 u16 flockdn    :6;   /* 15:10 Reserved */
139         } hsf_ctrl;
140         u16 regval;
141 };
142
143 /* ICH Flash Region Access Permissions */
144 union ich8_hws_flash_regacc {
145         struct ich8_flracc {
146                 u32 grra      :8; /* 0:7 GbE region Read Access */
147                 u32 grwa      :8; /* 8:15 GbE region Write Access */
148                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
149                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
150         } hsf_flregacc;
151         u16 regval;
152 };
153
154 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
155 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
156 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
157 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
158 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
159 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
160                                                 u32 offset, u8 byte);
161 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
162                                          u16 *data);
163 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
164                                          u8 size, u16 *data);
165 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
166 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
167
168 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
169 {
170         return readw(hw->flash_address + reg);
171 }
172
173 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
174 {
175         return readl(hw->flash_address + reg);
176 }
177
178 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
179 {
180         writew(val, hw->flash_address + reg);
181 }
182
183 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
184 {
185         writel(val, hw->flash_address + reg);
186 }
187
188 #define er16flash(reg)          __er16flash(hw, (reg))
189 #define er32flash(reg)          __er32flash(hw, (reg))
190 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
191 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
192
193 /**
194  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
195  *  @hw: pointer to the HW structure
196  *
197  *  Initialize family-specific PHY parameters and function pointers.
198  **/
199 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
200 {
201         struct e1000_phy_info *phy = &hw->phy;
202         s32 ret_val;
203         u16 i = 0;
204
205         phy->addr                       = 1;
206         phy->reset_delay_us             = 100;
207
208         /*
209          * We may need to do this twice - once for IGP and if that fails,
210          * we'll set BM func pointers and try again
211          */
212         ret_val = e1000e_determine_phy_address(hw);
213         if (ret_val) {
214                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
215                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
216                 ret_val = e1000e_determine_phy_address(hw);
217                 if (ret_val)
218                         return ret_val;
219         }
220
221         phy->id = 0;
222         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
223                (i++ < 100)) {
224                 msleep(1);
225                 ret_val = e1000e_get_phy_id(hw);
226                 if (ret_val)
227                         return ret_val;
228         }
229
230         /* Verify phy id */
231         switch (phy->id) {
232         case IGP03E1000_E_PHY_ID:
233                 phy->type = e1000_phy_igp_3;
234                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
235                 break;
236         case IFE_E_PHY_ID:
237         case IFE_PLUS_E_PHY_ID:
238         case IFE_C_E_PHY_ID:
239                 phy->type = e1000_phy_ife;
240                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
241                 break;
242         case BME1000_E_PHY_ID:
243                 phy->type = e1000_phy_bm;
244                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
245                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
246                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
247                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
248                 break;
249         default:
250                 return -E1000_ERR_PHY;
251                 break;
252         }
253
254         return 0;
255 }
256
257 /**
258  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
259  *  @hw: pointer to the HW structure
260  *
261  *  Initialize family-specific NVM parameters and function
262  *  pointers.
263  **/
264 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
265 {
266         struct e1000_nvm_info *nvm = &hw->nvm;
267         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
268         u32 gfpreg;
269         u32 sector_base_addr;
270         u32 sector_end_addr;
271         u16 i;
272
273         /* Can't read flash registers if the register set isn't mapped. */
274         if (!hw->flash_address) {
275                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
276                 return -E1000_ERR_CONFIG;
277         }
278
279         nvm->type = e1000_nvm_flash_sw;
280
281         gfpreg = er32flash(ICH_FLASH_GFPREG);
282
283         /*
284          * sector_X_addr is a "sector"-aligned address (4096 bytes)
285          * Add 1 to sector_end_addr since this sector is included in
286          * the overall size.
287          */
288         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
289         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
290
291         /* flash_base_addr is byte-aligned */
292         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
293
294         /*
295          * find total size of the NVM, then cut in half since the total
296          * size represents two separate NVM banks.
297          */
298         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
299                                 << FLASH_SECTOR_ADDR_SHIFT;
300         nvm->flash_bank_size /= 2;
301         /* Adjust to word count */
302         nvm->flash_bank_size /= sizeof(u16);
303
304         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
305
306         /* Clear shadow ram */
307         for (i = 0; i < nvm->word_size; i++) {
308                 dev_spec->shadow_ram[i].modified = 0;
309                 dev_spec->shadow_ram[i].value    = 0xFFFF;
310         }
311
312         return 0;
313 }
314
315 /**
316  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
317  *  @hw: pointer to the HW structure
318  *
319  *  Initialize family-specific MAC parameters and function
320  *  pointers.
321  **/
322 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
323 {
324         struct e1000_hw *hw = &adapter->hw;
325         struct e1000_mac_info *mac = &hw->mac;
326
327         /* Set media type function pointer */
328         hw->phy.media_type = e1000_media_type_copper;
329
330         /* Set mta register count */
331         mac->mta_reg_count = 32;
332         /* Set rar entry count */
333         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
334         if (mac->type == e1000_ich8lan)
335                 mac->rar_entry_count--;
336         /* Set if manageability features are enabled. */
337         mac->arc_subsystem_valid = 1;
338
339         /* Enable PCS Lock-loss workaround for ICH8 */
340         if (mac->type == e1000_ich8lan)
341                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
342
343         return 0;
344 }
345
346 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
347 {
348         struct e1000_hw *hw = &adapter->hw;
349         s32 rc;
350
351         rc = e1000_init_mac_params_ich8lan(adapter);
352         if (rc)
353                 return rc;
354
355         rc = e1000_init_nvm_params_ich8lan(hw);
356         if (rc)
357                 return rc;
358
359         rc = e1000_init_phy_params_ich8lan(hw);
360         if (rc)
361                 return rc;
362
363         if ((adapter->hw.mac.type == e1000_ich8lan) &&
364             (adapter->hw.phy.type == e1000_phy_igp_3))
365                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
366
367         return 0;
368 }
369
370 /**
371  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
372  *  @hw: pointer to the HW structure
373  *
374  *  Acquires the software control flag for performing NVM and PHY
375  *  operations.  This is a function pointer entry point only called by
376  *  read/write routines for the PHY and NVM parts.
377  **/
378 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
379 {
380         u32 extcnf_ctrl;
381         u32 timeout = PHY_CFG_TIMEOUT;
382
383         while (timeout) {
384                 extcnf_ctrl = er32(EXTCNF_CTRL);
385                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
386                 ew32(EXTCNF_CTRL, extcnf_ctrl);
387
388                 extcnf_ctrl = er32(EXTCNF_CTRL);
389                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
390                         break;
391                 mdelay(1);
392                 timeout--;
393         }
394
395         if (!timeout) {
396                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
397                 return -E1000_ERR_CONFIG;
398         }
399
400         return 0;
401 }
402
403 /**
404  *  e1000_release_swflag_ich8lan - Release software control flag
405  *  @hw: pointer to the HW structure
406  *
407  *  Releases the software control flag for performing NVM and PHY operations.
408  *  This is a function pointer entry point only called by read/write
409  *  routines for the PHY and NVM parts.
410  **/
411 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
412 {
413         u32 extcnf_ctrl;
414
415         extcnf_ctrl = er32(EXTCNF_CTRL);
416         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
417         ew32(EXTCNF_CTRL, extcnf_ctrl);
418 }
419
420 /**
421  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
422  *  @hw: pointer to the HW structure
423  *
424  *  Checks if firmware is blocking the reset of the PHY.
425  *  This is a function pointer entry point only called by
426  *  reset routines.
427  **/
428 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
429 {
430         u32 fwsm;
431
432         fwsm = er32(FWSM);
433
434         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
435 }
436
437 /**
438  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
439  *  @hw: pointer to the HW structure
440  *
441  *  Forces the speed and duplex settings of the PHY.
442  *  This is a function pointer entry point only called by
443  *  PHY setup routines.
444  **/
445 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
446 {
447         struct e1000_phy_info *phy = &hw->phy;
448         s32 ret_val;
449         u16 data;
450         bool link;
451
452         if (phy->type != e1000_phy_ife) {
453                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
454                 return ret_val;
455         }
456
457         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
458         if (ret_val)
459                 return ret_val;
460
461         e1000e_phy_force_speed_duplex_setup(hw, &data);
462
463         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
464         if (ret_val)
465                 return ret_val;
466
467         /* Disable MDI-X support for 10/100 */
468         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
469         if (ret_val)
470                 return ret_val;
471
472         data &= ~IFE_PMC_AUTO_MDIX;
473         data &= ~IFE_PMC_FORCE_MDIX;
474
475         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
476         if (ret_val)
477                 return ret_val;
478
479         hw_dbg(hw, "IFE PMC: %X\n", data);
480
481         udelay(1);
482
483         if (phy->autoneg_wait_to_complete) {
484                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
485
486                 ret_val = e1000e_phy_has_link_generic(hw,
487                                                      PHY_FORCE_LIMIT,
488                                                      100000,
489                                                      &link);
490                 if (ret_val)
491                         return ret_val;
492
493                 if (!link)
494                         hw_dbg(hw, "Link taking longer than expected.\n");
495
496                 /* Try once more */
497                 ret_val = e1000e_phy_has_link_generic(hw,
498                                                      PHY_FORCE_LIMIT,
499                                                      100000,
500                                                      &link);
501                 if (ret_val)
502                         return ret_val;
503         }
504
505         return 0;
506 }
507
508 /**
509  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
510  *  @hw: pointer to the HW structure
511  *
512  *  Resets the PHY
513  *  This is a function pointer entry point called by drivers
514  *  or other shared routines.
515  **/
516 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
517 {
518         struct e1000_phy_info *phy = &hw->phy;
519         u32 i;
520         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
521         s32 ret_val;
522         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
523         u16 word_addr, reg_data, reg_addr, phy_page = 0;
524
525         ret_val = e1000e_phy_hw_reset_generic(hw);
526         if (ret_val)
527                 return ret_val;
528
529         /*
530          * Initialize the PHY from the NVM on ICH platforms.  This
531          * is needed due to an issue where the NVM configuration is
532          * not properly autoloaded after power transitions.
533          * Therefore, after each PHY reset, we will load the
534          * configuration data out of the NVM manually.
535          */
536         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
537                 struct e1000_adapter *adapter = hw->adapter;
538
539                 /* Check if SW needs configure the PHY */
540                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
541                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
542                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
543                 else
544                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
545
546                 data = er32(FEXTNVM);
547                 if (!(data & sw_cfg_mask))
548                         return 0;
549
550                 /* Wait for basic configuration completes before proceeding*/
551                 do {
552                         data = er32(STATUS);
553                         data &= E1000_STATUS_LAN_INIT_DONE;
554                         udelay(100);
555                 } while ((!data) && --loop);
556
557                 /*
558                  * If basic configuration is incomplete before the above loop
559                  * count reaches 0, loading the configuration from NVM will
560                  * leave the PHY in a bad state possibly resulting in no link.
561                  */
562                 if (loop == 0) {
563                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
564                 }
565
566                 /* Clear the Init Done bit for the next init event */
567                 data = er32(STATUS);
568                 data &= ~E1000_STATUS_LAN_INIT_DONE;
569                 ew32(STATUS, data);
570
571                 /*
572                  * Make sure HW does not configure LCD from PHY
573                  * extended configuration before SW configuration
574                  */
575                 data = er32(EXTCNF_CTRL);
576                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
577                         return 0;
578
579                 cnf_size = er32(EXTCNF_SIZE);
580                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
581                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
582                 if (!cnf_size)
583                         return 0;
584
585                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
586                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
587
588                 /* Configure LCD from extended configuration region. */
589
590                 /* cnf_base_addr is in DWORD */
591                 word_addr = (u16)(cnf_base_addr << 1);
592
593                 for (i = 0; i < cnf_size; i++) {
594                         ret_val = e1000_read_nvm(hw,
595                                                 (word_addr + i * 2),
596                                                 1,
597                                                 &reg_data);
598                         if (ret_val)
599                                 return ret_val;
600
601                         ret_val = e1000_read_nvm(hw,
602                                                 (word_addr + i * 2 + 1),
603                                                 1,
604                                                 &reg_addr);
605                         if (ret_val)
606                                 return ret_val;
607
608                         /* Save off the PHY page for future writes. */
609                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
610                                 phy_page = reg_data;
611                                 continue;
612                         }
613
614                         reg_addr |= phy_page;
615
616                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
617                         if (ret_val)
618                                 return ret_val;
619                 }
620         }
621
622         return 0;
623 }
624
625 /**
626  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
627  *  @hw: pointer to the HW structure
628  *
629  *  Populates "phy" structure with various feature states.
630  *  This function is only called by other family-specific
631  *  routines.
632  **/
633 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
634 {
635         struct e1000_phy_info *phy = &hw->phy;
636         s32 ret_val;
637         u16 data;
638         bool link;
639
640         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
641         if (ret_val)
642                 return ret_val;
643
644         if (!link) {
645                 hw_dbg(hw, "Phy info is only valid if link is up\n");
646                 return -E1000_ERR_CONFIG;
647         }
648
649         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
650         if (ret_val)
651                 return ret_val;
652         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
653
654         if (phy->polarity_correction) {
655                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
656                 if (ret_val)
657                         return ret_val;
658         } else {
659                 /* Polarity is forced */
660                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
661                                       ? e1000_rev_polarity_reversed
662                                       : e1000_rev_polarity_normal;
663         }
664
665         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
666         if (ret_val)
667                 return ret_val;
668
669         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
670
671         /* The following parameters are undefined for 10/100 operation. */
672         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
673         phy->local_rx = e1000_1000t_rx_status_undefined;
674         phy->remote_rx = e1000_1000t_rx_status_undefined;
675
676         return 0;
677 }
678
679 /**
680  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
681  *  @hw: pointer to the HW structure
682  *
683  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
684  *  This is a function pointer entry point called by drivers
685  *  or other shared routines.
686  **/
687 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
688 {
689         switch (hw->phy.type) {
690         case e1000_phy_ife:
691                 return e1000_get_phy_info_ife_ich8lan(hw);
692                 break;
693         case e1000_phy_igp_3:
694         case e1000_phy_bm:
695                 return e1000e_get_phy_info_igp(hw);
696                 break;
697         default:
698                 break;
699         }
700
701         return -E1000_ERR_PHY_TYPE;
702 }
703
704 /**
705  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
706  *  @hw: pointer to the HW structure
707  *
708  *  Polarity is determined on the polarity reversal feature being enabled.
709  *  This function is only called by other family-specific
710  *  routines.
711  **/
712 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
713 {
714         struct e1000_phy_info *phy = &hw->phy;
715         s32 ret_val;
716         u16 phy_data, offset, mask;
717
718         /*
719          * Polarity is determined based on the reversal feature being enabled.
720          */
721         if (phy->polarity_correction) {
722                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
723                 mask    = IFE_PESC_POLARITY_REVERSED;
724         } else {
725                 offset  = IFE_PHY_SPECIAL_CONTROL;
726                 mask    = IFE_PSC_FORCE_POLARITY;
727         }
728
729         ret_val = e1e_rphy(hw, offset, &phy_data);
730
731         if (!ret_val)
732                 phy->cable_polarity = (phy_data & mask)
733                                       ? e1000_rev_polarity_reversed
734                                       : e1000_rev_polarity_normal;
735
736         return ret_val;
737 }
738
739 /**
740  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
741  *  @hw: pointer to the HW structure
742  *  @active: TRUE to enable LPLU, FALSE to disable
743  *
744  *  Sets the LPLU D0 state according to the active flag.  When
745  *  activating LPLU this function also disables smart speed
746  *  and vice versa.  LPLU will not be activated unless the
747  *  device autonegotiation advertisement meets standards of
748  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
749  *  This is a function pointer entry point only called by
750  *  PHY setup routines.
751  **/
752 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
753 {
754         struct e1000_phy_info *phy = &hw->phy;
755         u32 phy_ctrl;
756         s32 ret_val = 0;
757         u16 data;
758
759         if (phy->type == e1000_phy_ife)
760                 return ret_val;
761
762         phy_ctrl = er32(PHY_CTRL);
763
764         if (active) {
765                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
766                 ew32(PHY_CTRL, phy_ctrl);
767
768                 /*
769                  * Call gig speed drop workaround on LPLU before accessing
770                  * any PHY registers
771                  */
772                 if ((hw->mac.type == e1000_ich8lan) &&
773                     (hw->phy.type == e1000_phy_igp_3))
774                         e1000e_gig_downshift_workaround_ich8lan(hw);
775
776                 /* When LPLU is enabled, we should disable SmartSpeed */
777                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
778                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
779                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
780                 if (ret_val)
781                         return ret_val;
782         } else {
783                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
784                 ew32(PHY_CTRL, phy_ctrl);
785
786                 /*
787                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
788                  * during Dx states where the power conservation is most
789                  * important.  During driver activity we should enable
790                  * SmartSpeed, so performance is maintained.
791                  */
792                 if (phy->smart_speed == e1000_smart_speed_on) {
793                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
794                                            &data);
795                         if (ret_val)
796                                 return ret_val;
797
798                         data |= IGP01E1000_PSCFR_SMART_SPEED;
799                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
800                                            data);
801                         if (ret_val)
802                                 return ret_val;
803                 } else if (phy->smart_speed == e1000_smart_speed_off) {
804                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
805                                            &data);
806                         if (ret_val)
807                                 return ret_val;
808
809                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
810                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
811                                            data);
812                         if (ret_val)
813                                 return ret_val;
814                 }
815         }
816
817         return 0;
818 }
819
820 /**
821  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
822  *  @hw: pointer to the HW structure
823  *  @active: TRUE to enable LPLU, FALSE to disable
824  *
825  *  Sets the LPLU D3 state according to the active flag.  When
826  *  activating LPLU this function also disables smart speed
827  *  and vice versa.  LPLU will not be activated unless the
828  *  device autonegotiation advertisement meets standards of
829  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
830  *  This is a function pointer entry point only called by
831  *  PHY setup routines.
832  **/
833 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
834 {
835         struct e1000_phy_info *phy = &hw->phy;
836         u32 phy_ctrl;
837         s32 ret_val;
838         u16 data;
839
840         phy_ctrl = er32(PHY_CTRL);
841
842         if (!active) {
843                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
844                 ew32(PHY_CTRL, phy_ctrl);
845                 /*
846                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
847                  * during Dx states where the power conservation is most
848                  * important.  During driver activity we should enable
849                  * SmartSpeed, so performance is maintained.
850                  */
851                 if (phy->smart_speed == e1000_smart_speed_on) {
852                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
853                                            &data);
854                         if (ret_val)
855                                 return ret_val;
856
857                         data |= IGP01E1000_PSCFR_SMART_SPEED;
858                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
859                                            data);
860                         if (ret_val)
861                                 return ret_val;
862                 } else if (phy->smart_speed == e1000_smart_speed_off) {
863                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
864                                            &data);
865                         if (ret_val)
866                                 return ret_val;
867
868                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
869                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
870                                            data);
871                         if (ret_val)
872                                 return ret_val;
873                 }
874         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
875                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
876                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
877                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
878                 ew32(PHY_CTRL, phy_ctrl);
879
880                 /*
881                  * Call gig speed drop workaround on LPLU before accessing
882                  * any PHY registers
883                  */
884                 if ((hw->mac.type == e1000_ich8lan) &&
885                     (hw->phy.type == e1000_phy_igp_3))
886                         e1000e_gig_downshift_workaround_ich8lan(hw);
887
888                 /* When LPLU is enabled, we should disable SmartSpeed */
889                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
890                 if (ret_val)
891                         return ret_val;
892
893                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
894                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
895         }
896
897         return 0;
898 }
899
900 /**
901  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
902  *  @hw: pointer to the HW structure
903  *  @offset: The offset (in bytes) of the word(s) to read.
904  *  @words: Size of data to read in words
905  *  @data: Pointer to the word(s) to read at offset.
906  *
907  *  Reads a word(s) from the NVM using the flash access registers.
908  **/
909 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
910                                   u16 *data)
911 {
912         struct e1000_nvm_info *nvm = &hw->nvm;
913         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
914         u32 act_offset;
915         s32 ret_val;
916         u16 i, word;
917
918         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
919             (words == 0)) {
920                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
921                 return -E1000_ERR_NVM;
922         }
923
924         ret_val = e1000_acquire_swflag_ich8lan(hw);
925         if (ret_val)
926                 return ret_val;
927
928         /* Start with the bank offset, then add the relative offset. */
929         act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
930                      ? nvm->flash_bank_size
931                      : 0;
932         act_offset += offset;
933
934         for (i = 0; i < words; i++) {
935                 if ((dev_spec->shadow_ram) &&
936                     (dev_spec->shadow_ram[offset+i].modified)) {
937                         data[i] = dev_spec->shadow_ram[offset+i].value;
938                 } else {
939                         ret_val = e1000_read_flash_word_ich8lan(hw,
940                                                                 act_offset + i,
941                                                                 &word);
942                         if (ret_val)
943                                 break;
944                         data[i] = word;
945                 }
946         }
947
948         e1000_release_swflag_ich8lan(hw);
949
950         return ret_val;
951 }
952
953 /**
954  *  e1000_flash_cycle_init_ich8lan - Initialize flash
955  *  @hw: pointer to the HW structure
956  *
957  *  This function does initial flash setup so that a new read/write/erase cycle
958  *  can be started.
959  **/
960 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
961 {
962         union ich8_hws_flash_status hsfsts;
963         s32 ret_val = -E1000_ERR_NVM;
964         s32 i = 0;
965
966         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
967
968         /* Check if the flash descriptor is valid */
969         if (hsfsts.hsf_status.fldesvalid == 0) {
970                 hw_dbg(hw, "Flash descriptor invalid.  "
971                          "SW Sequencing must be used.");
972                 return -E1000_ERR_NVM;
973         }
974
975         /* Clear FCERR and DAEL in hw status by writing 1 */
976         hsfsts.hsf_status.flcerr = 1;
977         hsfsts.hsf_status.dael = 1;
978
979         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
980
981         /*
982          * Either we should have a hardware SPI cycle in progress
983          * bit to check against, in order to start a new cycle or
984          * FDONE bit should be changed in the hardware so that it
985          * is 1 after hardware reset, which can then be used as an
986          * indication whether a cycle is in progress or has been
987          * completed.
988          */
989
990         if (hsfsts.hsf_status.flcinprog == 0) {
991                 /*
992                  * There is no cycle running at present,
993                  * so we can start a cycle
994                  * Begin by setting Flash Cycle Done.
995                  */
996                 hsfsts.hsf_status.flcdone = 1;
997                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
998                 ret_val = 0;
999         } else {
1000                 /*
1001                  * otherwise poll for sometime so the current
1002                  * cycle has a chance to end before giving up.
1003                  */
1004                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1005                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1006                         if (hsfsts.hsf_status.flcinprog == 0) {
1007                                 ret_val = 0;
1008                                 break;
1009                         }
1010                         udelay(1);
1011                 }
1012                 if (ret_val == 0) {
1013                         /*
1014                          * Successful in waiting for previous cycle to timeout,
1015                          * now set the Flash Cycle Done.
1016                          */
1017                         hsfsts.hsf_status.flcdone = 1;
1018                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1019                 } else {
1020                         hw_dbg(hw, "Flash controller busy, cannot get access");
1021                 }
1022         }
1023
1024         return ret_val;
1025 }
1026
1027 /**
1028  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1029  *  @hw: pointer to the HW structure
1030  *  @timeout: maximum time to wait for completion
1031  *
1032  *  This function starts a flash cycle and waits for its completion.
1033  **/
1034 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1035 {
1036         union ich8_hws_flash_ctrl hsflctl;
1037         union ich8_hws_flash_status hsfsts;
1038         s32 ret_val = -E1000_ERR_NVM;
1039         u32 i = 0;
1040
1041         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1042         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1043         hsflctl.hsf_ctrl.flcgo = 1;
1044         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1045
1046         /* wait till FDONE bit is set to 1 */
1047         do {
1048                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1049                 if (hsfsts.hsf_status.flcdone == 1)
1050                         break;
1051                 udelay(1);
1052         } while (i++ < timeout);
1053
1054         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1055                 return 0;
1056
1057         return ret_val;
1058 }
1059
1060 /**
1061  *  e1000_read_flash_word_ich8lan - Read word from flash
1062  *  @hw: pointer to the HW structure
1063  *  @offset: offset to data location
1064  *  @data: pointer to the location for storing the data
1065  *
1066  *  Reads the flash word at offset into data.  Offset is converted
1067  *  to bytes before read.
1068  **/
1069 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1070                                          u16 *data)
1071 {
1072         /* Must convert offset into bytes. */
1073         offset <<= 1;
1074
1075         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1076 }
1077
1078 /**
1079  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1080  *  @hw: pointer to the HW structure
1081  *  @offset: The offset (in bytes) of the byte or word to read.
1082  *  @size: Size of data to read, 1=byte 2=word
1083  *  @data: Pointer to the word to store the value read.
1084  *
1085  *  Reads a byte or word from the NVM using the flash access registers.
1086  **/
1087 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1088                                          u8 size, u16 *data)
1089 {
1090         union ich8_hws_flash_status hsfsts;
1091         union ich8_hws_flash_ctrl hsflctl;
1092         u32 flash_linear_addr;
1093         u32 flash_data = 0;
1094         s32 ret_val = -E1000_ERR_NVM;
1095         u8 count = 0;
1096
1097         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1098                 return -E1000_ERR_NVM;
1099
1100         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1101                             hw->nvm.flash_base_addr;
1102
1103         do {
1104                 udelay(1);
1105                 /* Steps */
1106                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1107                 if (ret_val != 0)
1108                         break;
1109
1110                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1111                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1112                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1113                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1114                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1115
1116                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1117
1118                 ret_val = e1000_flash_cycle_ich8lan(hw,
1119                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1120
1121                 /*
1122                  * Check if FCERR is set to 1, if set to 1, clear it
1123                  * and try the whole sequence a few more times, else
1124                  * read in (shift in) the Flash Data0, the order is
1125                  * least significant byte first msb to lsb
1126                  */
1127                 if (ret_val == 0) {
1128                         flash_data = er32flash(ICH_FLASH_FDATA0);
1129                         if (size == 1) {
1130                                 *data = (u8)(flash_data & 0x000000FF);
1131                         } else if (size == 2) {
1132                                 *data = (u16)(flash_data & 0x0000FFFF);
1133                         }
1134                         break;
1135                 } else {
1136                         /*
1137                          * If we've gotten here, then things are probably
1138                          * completely hosed, but if the error condition is
1139                          * detected, it won't hurt to give it another try...
1140                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1141                          */
1142                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1143                         if (hsfsts.hsf_status.flcerr == 1) {
1144                                 /* Repeat for some time before giving up. */
1145                                 continue;
1146                         } else if (hsfsts.hsf_status.flcdone == 0) {
1147                                 hw_dbg(hw, "Timeout error - flash cycle "
1148                                          "did not complete.");
1149                                 break;
1150                         }
1151                 }
1152         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1153
1154         return ret_val;
1155 }
1156
1157 /**
1158  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1159  *  @hw: pointer to the HW structure
1160  *  @offset: The offset (in bytes) of the word(s) to write.
1161  *  @words: Size of data to write in words
1162  *  @data: Pointer to the word(s) to write at offset.
1163  *
1164  *  Writes a byte or word to the NVM using the flash access registers.
1165  **/
1166 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1167                                    u16 *data)
1168 {
1169         struct e1000_nvm_info *nvm = &hw->nvm;
1170         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1171         s32 ret_val;
1172         u16 i;
1173
1174         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1175             (words == 0)) {
1176                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1177                 return -E1000_ERR_NVM;
1178         }
1179
1180         ret_val = e1000_acquire_swflag_ich8lan(hw);
1181         if (ret_val)
1182                 return ret_val;
1183
1184         for (i = 0; i < words; i++) {
1185                 dev_spec->shadow_ram[offset+i].modified = 1;
1186                 dev_spec->shadow_ram[offset+i].value = data[i];
1187         }
1188
1189         e1000_release_swflag_ich8lan(hw);
1190
1191         return 0;
1192 }
1193
1194 /**
1195  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1196  *  @hw: pointer to the HW structure
1197  *
1198  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1199  *  which writes the checksum to the shadow ram.  The changes in the shadow
1200  *  ram are then committed to the EEPROM by processing each bank at a time
1201  *  checking for the modified bit and writing only the pending changes.
1202  *  After a successful commit, the shadow ram is cleared and is ready for
1203  *  future writes.
1204  **/
1205 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1206 {
1207         struct e1000_nvm_info *nvm = &hw->nvm;
1208         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1209         u32 i, act_offset, new_bank_offset, old_bank_offset;
1210         s32 ret_val;
1211         u16 data;
1212
1213         ret_val = e1000e_update_nvm_checksum_generic(hw);
1214         if (ret_val)
1215                 return ret_val;
1216
1217         if (nvm->type != e1000_nvm_flash_sw)
1218                 return ret_val;
1219
1220         ret_val = e1000_acquire_swflag_ich8lan(hw);
1221         if (ret_val)
1222                 return ret_val;
1223
1224         /*
1225          * We're writing to the opposite bank so if we're on bank 1,
1226          * write to bank 0 etc.  We also need to erase the segment that
1227          * is going to be written
1228          */
1229         if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
1230                 new_bank_offset = nvm->flash_bank_size;
1231                 old_bank_offset = 0;
1232                 e1000_erase_flash_bank_ich8lan(hw, 1);
1233         } else {
1234                 old_bank_offset = nvm->flash_bank_size;
1235                 new_bank_offset = 0;
1236                 e1000_erase_flash_bank_ich8lan(hw, 0);
1237         }
1238
1239         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1240                 /*
1241                  * Determine whether to write the value stored
1242                  * in the other NVM bank or a modified value stored
1243                  * in the shadow RAM
1244                  */
1245                 if (dev_spec->shadow_ram[i].modified) {
1246                         data = dev_spec->shadow_ram[i].value;
1247                 } else {
1248                         e1000_read_flash_word_ich8lan(hw,
1249                                                       i + old_bank_offset,
1250                                                       &data);
1251                 }
1252
1253                 /*
1254                  * If the word is 0x13, then make sure the signature bits
1255                  * (15:14) are 11b until the commit has completed.
1256                  * This will allow us to write 10b which indicates the
1257                  * signature is valid.  We want to do this after the write
1258                  * has completed so that we don't mark the segment valid
1259                  * while the write is still in progress
1260                  */
1261                 if (i == E1000_ICH_NVM_SIG_WORD)
1262                         data |= E1000_ICH_NVM_SIG_MASK;
1263
1264                 /* Convert offset to bytes. */
1265                 act_offset = (i + new_bank_offset) << 1;
1266
1267                 udelay(100);
1268                 /* Write the bytes to the new bank. */
1269                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1270                                                                act_offset,
1271                                                                (u8)data);
1272                 if (ret_val)
1273                         break;
1274
1275                 udelay(100);
1276                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1277                                                           act_offset + 1,
1278                                                           (u8)(data >> 8));
1279                 if (ret_val)
1280                         break;
1281         }
1282
1283         /*
1284          * Don't bother writing the segment valid bits if sector
1285          * programming failed.
1286          */
1287         if (ret_val) {
1288                 hw_dbg(hw, "Flash commit failed.\n");
1289                 e1000_release_swflag_ich8lan(hw);
1290                 return ret_val;
1291         }
1292
1293         /*
1294          * Finally validate the new segment by setting bit 15:14
1295          * to 10b in word 0x13 , this can be done without an
1296          * erase as well since these bits are 11 to start with
1297          * and we need to change bit 14 to 0b
1298          */
1299         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1300         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1301         data &= 0xBFFF;
1302         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1303                                                        act_offset * 2 + 1,
1304                                                        (u8)(data >> 8));
1305         if (ret_val) {
1306                 e1000_release_swflag_ich8lan(hw);
1307                 return ret_val;
1308         }
1309
1310         /*
1311          * And invalidate the previously valid segment by setting
1312          * its signature word (0x13) high_byte to 0b. This can be
1313          * done without an erase because flash erase sets all bits
1314          * to 1's. We can write 1's to 0's without an erase
1315          */
1316         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1317         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1318         if (ret_val) {
1319                 e1000_release_swflag_ich8lan(hw);
1320                 return ret_val;
1321         }
1322
1323         /* Great!  Everything worked, we can now clear the cached entries. */
1324         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1325                 dev_spec->shadow_ram[i].modified = 0;
1326                 dev_spec->shadow_ram[i].value = 0xFFFF;
1327         }
1328
1329         e1000_release_swflag_ich8lan(hw);
1330
1331         /*
1332          * Reload the EEPROM, or else modifications will not appear
1333          * until after the next adapter reset.
1334          */
1335         e1000e_reload_nvm(hw);
1336         msleep(10);
1337
1338         return ret_val;
1339 }
1340
1341 /**
1342  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1343  *  @hw: pointer to the HW structure
1344  *
1345  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1346  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1347  *  calculated, in which case we need to calculate the checksum and set bit 6.
1348  **/
1349 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1350 {
1351         s32 ret_val;
1352         u16 data;
1353
1354         /*
1355          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1356          * needs to be fixed.  This bit is an indication that the NVM
1357          * was prepared by OEM software and did not calculate the
1358          * checksum...a likely scenario.
1359          */
1360         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1361         if (ret_val)
1362                 return ret_val;
1363
1364         if ((data & 0x40) == 0) {
1365                 data |= 0x40;
1366                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1367                 if (ret_val)
1368                         return ret_val;
1369                 ret_val = e1000e_update_nvm_checksum(hw);
1370                 if (ret_val)
1371                         return ret_val;
1372         }
1373
1374         return e1000e_validate_nvm_checksum_generic(hw);
1375 }
1376
1377 /**
1378  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1379  *  @hw: pointer to the HW structure
1380  *  @offset: The offset (in bytes) of the byte/word to read.
1381  *  @size: Size of data to read, 1=byte 2=word
1382  *  @data: The byte(s) to write to the NVM.
1383  *
1384  *  Writes one/two bytes to the NVM using the flash access registers.
1385  **/
1386 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1387                                           u8 size, u16 data)
1388 {
1389         union ich8_hws_flash_status hsfsts;
1390         union ich8_hws_flash_ctrl hsflctl;
1391         u32 flash_linear_addr;
1392         u32 flash_data = 0;
1393         s32 ret_val;
1394         u8 count = 0;
1395
1396         if (size < 1 || size > 2 || data > size * 0xff ||
1397             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1398                 return -E1000_ERR_NVM;
1399
1400         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1401                             hw->nvm.flash_base_addr;
1402
1403         do {
1404                 udelay(1);
1405                 /* Steps */
1406                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1407                 if (ret_val)
1408                         break;
1409
1410                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1411                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1412                 hsflctl.hsf_ctrl.fldbcount = size -1;
1413                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1414                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1415
1416                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1417
1418                 if (size == 1)
1419                         flash_data = (u32)data & 0x00FF;
1420                 else
1421                         flash_data = (u32)data;
1422
1423                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1424
1425                 /*
1426                  * check if FCERR is set to 1 , if set to 1, clear it
1427                  * and try the whole sequence a few more times else done
1428                  */
1429                 ret_val = e1000_flash_cycle_ich8lan(hw,
1430                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1431                 if (!ret_val)
1432                         break;
1433
1434                 /*
1435                  * If we're here, then things are most likely
1436                  * completely hosed, but if the error condition
1437                  * is detected, it won't hurt to give it another
1438                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1439                  */
1440                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1441                 if (hsfsts.hsf_status.flcerr == 1)
1442                         /* Repeat for some time before giving up. */
1443                         continue;
1444                 if (hsfsts.hsf_status.flcdone == 0) {
1445                         hw_dbg(hw, "Timeout error - flash cycle "
1446                                  "did not complete.");
1447                         break;
1448                 }
1449         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1450
1451         return ret_val;
1452 }
1453
1454 /**
1455  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1456  *  @hw: pointer to the HW structure
1457  *  @offset: The index of the byte to read.
1458  *  @data: The byte to write to the NVM.
1459  *
1460  *  Writes a single byte to the NVM using the flash access registers.
1461  **/
1462 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1463                                           u8 data)
1464 {
1465         u16 word = (u16)data;
1466
1467         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1468 }
1469
1470 /**
1471  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1472  *  @hw: pointer to the HW structure
1473  *  @offset: The offset of the byte to write.
1474  *  @byte: The byte to write to the NVM.
1475  *
1476  *  Writes a single byte to the NVM using the flash access registers.
1477  *  Goes through a retry algorithm before giving up.
1478  **/
1479 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1480                                                 u32 offset, u8 byte)
1481 {
1482         s32 ret_val;
1483         u16 program_retries;
1484
1485         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1486         if (!ret_val)
1487                 return ret_val;
1488
1489         for (program_retries = 0; program_retries < 100; program_retries++) {
1490                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1491                 udelay(100);
1492                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1493                 if (!ret_val)
1494                         break;
1495         }
1496         if (program_retries == 100)
1497                 return -E1000_ERR_NVM;
1498
1499         return 0;
1500 }
1501
1502 /**
1503  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1504  *  @hw: pointer to the HW structure
1505  *  @bank: 0 for first bank, 1 for second bank, etc.
1506  *
1507  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1508  *  bank N is 4096 * N + flash_reg_addr.
1509  **/
1510 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1511 {
1512         struct e1000_nvm_info *nvm = &hw->nvm;
1513         union ich8_hws_flash_status hsfsts;
1514         union ich8_hws_flash_ctrl hsflctl;
1515         u32 flash_linear_addr;
1516         /* bank size is in 16bit words - adjust to bytes */
1517         u32 flash_bank_size = nvm->flash_bank_size * 2;
1518         s32 ret_val;
1519         s32 count = 0;
1520         s32 iteration;
1521         s32 sector_size;
1522         s32 j;
1523
1524         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1525
1526         /*
1527          * Determine HW Sector size: Read BERASE bits of hw flash status
1528          * register
1529          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1530          *     consecutive sectors.  The start index for the nth Hw sector
1531          *     can be calculated as = bank * 4096 + n * 256
1532          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1533          *     The start index for the nth Hw sector can be calculated
1534          *     as = bank * 4096
1535          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1536          *     (ich9 only, otherwise error condition)
1537          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1538          */
1539         switch (hsfsts.hsf_status.berasesz) {
1540         case 0:
1541                 /* Hw sector size 256 */
1542                 sector_size = ICH_FLASH_SEG_SIZE_256;
1543                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1544                 break;
1545         case 1:
1546                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1547                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1548                 break;
1549         case 2:
1550                 if (hw->mac.type == e1000_ich9lan) {
1551                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1552                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1553                 } else {
1554                         return -E1000_ERR_NVM;
1555                 }
1556                 break;
1557         case 3:
1558                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1559                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1560                 break;
1561         default:
1562                 return -E1000_ERR_NVM;
1563         }
1564
1565         /* Start with the base address, then add the sector offset. */
1566         flash_linear_addr = hw->nvm.flash_base_addr;
1567         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1568
1569         for (j = 0; j < iteration ; j++) {
1570                 do {
1571                         /* Steps */
1572                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1573                         if (ret_val)
1574                                 return ret_val;
1575
1576                         /*
1577                          * Write a value 11 (block Erase) in Flash
1578                          * Cycle field in hw flash control
1579                          */
1580                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1581                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1582                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1583
1584                         /*
1585                          * Write the last 24 bits of an index within the
1586                          * block into Flash Linear address field in Flash
1587                          * Address.
1588                          */
1589                         flash_linear_addr += (j * sector_size);
1590                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1591
1592                         ret_val = e1000_flash_cycle_ich8lan(hw,
1593                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1594                         if (ret_val == 0)
1595                                 break;
1596
1597                         /*
1598                          * Check if FCERR is set to 1.  If 1,
1599                          * clear it and try the whole sequence
1600                          * a few more times else Done
1601                          */
1602                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1603                         if (hsfsts.hsf_status.flcerr == 1)
1604                                 /* repeat for some time before giving up */
1605                                 continue;
1606                         else if (hsfsts.hsf_status.flcdone == 0)
1607                                 return ret_val;
1608                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1609         }
1610
1611         return 0;
1612 }
1613
1614 /**
1615  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1616  *  @hw: pointer to the HW structure
1617  *  @data: Pointer to the LED settings
1618  *
1619  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1620  *  settings is all 0's or F's, set the LED default to a valid LED default
1621  *  setting.
1622  **/
1623 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1624 {
1625         s32 ret_val;
1626
1627         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1628         if (ret_val) {
1629                 hw_dbg(hw, "NVM Read Error\n");
1630                 return ret_val;
1631         }
1632
1633         if (*data == ID_LED_RESERVED_0000 ||
1634             *data == ID_LED_RESERVED_FFFF)
1635                 *data = ID_LED_DEFAULT_ICH8LAN;
1636
1637         return 0;
1638 }
1639
1640 /**
1641  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1642  *  @hw: pointer to the HW structure
1643  *
1644  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1645  *  register, so the the bus width is hard coded.
1646  **/
1647 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1648 {
1649         struct e1000_bus_info *bus = &hw->bus;
1650         s32 ret_val;
1651
1652         ret_val = e1000e_get_bus_info_pcie(hw);
1653
1654         /*
1655          * ICH devices are "PCI Express"-ish.  They have
1656          * a configuration space, but do not contain
1657          * PCI Express Capability registers, so bus width
1658          * must be hardcoded.
1659          */
1660         if (bus->width == e1000_bus_width_unknown)
1661                 bus->width = e1000_bus_width_pcie_x1;
1662
1663         return ret_val;
1664 }
1665
1666 /**
1667  *  e1000_reset_hw_ich8lan - Reset the hardware
1668  *  @hw: pointer to the HW structure
1669  *
1670  *  Does a full reset of the hardware which includes a reset of the PHY and
1671  *  MAC.
1672  **/
1673 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1674 {
1675         u32 ctrl, icr, kab;
1676         s32 ret_val;
1677
1678         /*
1679          * Prevent the PCI-E bus from sticking if there is no TLP connection
1680          * on the last TLP read/write transaction when MAC is reset.
1681          */
1682         ret_val = e1000e_disable_pcie_master(hw);
1683         if (ret_val) {
1684                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1685         }
1686
1687         hw_dbg(hw, "Masking off all interrupts\n");
1688         ew32(IMC, 0xffffffff);
1689
1690         /*
1691          * Disable the Transmit and Receive units.  Then delay to allow
1692          * any pending transactions to complete before we hit the MAC
1693          * with the global reset.
1694          */
1695         ew32(RCTL, 0);
1696         ew32(TCTL, E1000_TCTL_PSP);
1697         e1e_flush();
1698
1699         msleep(10);
1700
1701         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1702         if (hw->mac.type == e1000_ich8lan) {
1703                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1704                 ew32(PBA, E1000_PBA_8K);
1705                 /* Set Packet Buffer Size to 16k. */
1706                 ew32(PBS, E1000_PBS_16K);
1707         }
1708
1709         ctrl = er32(CTRL);
1710
1711         if (!e1000_check_reset_block(hw)) {
1712                 /*
1713                  * PHY HW reset requires MAC CORE reset at the same
1714                  * time to make sure the interface between MAC and the
1715                  * external PHY is reset.
1716                  */
1717                 ctrl |= E1000_CTRL_PHY_RST;
1718         }
1719         ret_val = e1000_acquire_swflag_ich8lan(hw);
1720         hw_dbg(hw, "Issuing a global reset to ich8lan");
1721         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1722         msleep(20);
1723
1724         ret_val = e1000e_get_auto_rd_done(hw);
1725         if (ret_val) {
1726                 /*
1727                  * When auto config read does not complete, do not
1728                  * return with an error. This can happen in situations
1729                  * where there is no eeprom and prevents getting link.
1730                  */
1731                 hw_dbg(hw, "Auto Read Done did not complete\n");
1732         }
1733
1734         ew32(IMC, 0xffffffff);
1735         icr = er32(ICR);
1736
1737         kab = er32(KABGTXD);
1738         kab |= E1000_KABGTXD_BGSQLBIAS;
1739         ew32(KABGTXD, kab);
1740
1741         return ret_val;
1742 }
1743
1744 /**
1745  *  e1000_init_hw_ich8lan - Initialize the hardware
1746  *  @hw: pointer to the HW structure
1747  *
1748  *  Prepares the hardware for transmit and receive by doing the following:
1749  *   - initialize hardware bits
1750  *   - initialize LED identification
1751  *   - setup receive address registers
1752  *   - setup flow control
1753  *   - setup transmit descriptors
1754  *   - clear statistics
1755  **/
1756 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1757 {
1758         struct e1000_mac_info *mac = &hw->mac;
1759         u32 ctrl_ext, txdctl, snoop;
1760         s32 ret_val;
1761         u16 i;
1762
1763         e1000_initialize_hw_bits_ich8lan(hw);
1764
1765         /* Initialize identification LED */
1766         ret_val = e1000e_id_led_init(hw);
1767         if (ret_val) {
1768                 hw_dbg(hw, "Error initializing identification LED\n");
1769                 return ret_val;
1770         }
1771
1772         /* Setup the receive address. */
1773         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1774
1775         /* Zero out the Multicast HASH table */
1776         hw_dbg(hw, "Zeroing the MTA\n");
1777         for (i = 0; i < mac->mta_reg_count; i++)
1778                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1779
1780         /* Setup link and flow control */
1781         ret_val = e1000_setup_link_ich8lan(hw);
1782
1783         /* Set the transmit descriptor write-back policy for both queues */
1784         txdctl = er32(TXDCTL(0));
1785         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1786                  E1000_TXDCTL_FULL_TX_DESC_WB;
1787         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1788                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1789         ew32(TXDCTL(0), txdctl);
1790         txdctl = er32(TXDCTL(1));
1791         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1792                  E1000_TXDCTL_FULL_TX_DESC_WB;
1793         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1794                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1795         ew32(TXDCTL(1), txdctl);
1796
1797         /*
1798          * ICH8 has opposite polarity of no_snoop bits.
1799          * By default, we should use snoop behavior.
1800          */
1801         if (mac->type == e1000_ich8lan)
1802                 snoop = PCIE_ICH8_SNOOP_ALL;
1803         else
1804                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1805         e1000e_set_pcie_no_snoop(hw, snoop);
1806
1807         ctrl_ext = er32(CTRL_EXT);
1808         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1809         ew32(CTRL_EXT, ctrl_ext);
1810
1811         /*
1812          * Clear all of the statistics registers (clear on read).  It is
1813          * important that we do this after we have tried to establish link
1814          * because the symbol error count will increment wildly if there
1815          * is no link.
1816          */
1817         e1000_clear_hw_cntrs_ich8lan(hw);
1818
1819         return 0;
1820 }
1821 /**
1822  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1823  *  @hw: pointer to the HW structure
1824  *
1825  *  Sets/Clears required hardware bits necessary for correctly setting up the
1826  *  hardware for transmit and receive.
1827  **/
1828 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1829 {
1830         u32 reg;
1831
1832         /* Extended Device Control */
1833         reg = er32(CTRL_EXT);
1834         reg |= (1 << 22);
1835         ew32(CTRL_EXT, reg);
1836
1837         /* Transmit Descriptor Control 0 */
1838         reg = er32(TXDCTL(0));
1839         reg |= (1 << 22);
1840         ew32(TXDCTL(0), reg);
1841
1842         /* Transmit Descriptor Control 1 */
1843         reg = er32(TXDCTL(1));
1844         reg |= (1 << 22);
1845         ew32(TXDCTL(1), reg);
1846
1847         /* Transmit Arbitration Control 0 */
1848         reg = er32(TARC(0));
1849         if (hw->mac.type == e1000_ich8lan)
1850                 reg |= (1 << 28) | (1 << 29);
1851         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
1852         ew32(TARC(0), reg);
1853
1854         /* Transmit Arbitration Control 1 */
1855         reg = er32(TARC(1));
1856         if (er32(TCTL) & E1000_TCTL_MULR)
1857                 reg &= ~(1 << 28);
1858         else
1859                 reg |= (1 << 28);
1860         reg |= (1 << 24) | (1 << 26) | (1 << 30);
1861         ew32(TARC(1), reg);
1862
1863         /* Device Status */
1864         if (hw->mac.type == e1000_ich8lan) {
1865                 reg = er32(STATUS);
1866                 reg &= ~(1 << 31);
1867                 ew32(STATUS, reg);
1868         }
1869 }
1870
1871 /**
1872  *  e1000_setup_link_ich8lan - Setup flow control and link settings
1873  *  @hw: pointer to the HW structure
1874  *
1875  *  Determines which flow control settings to use, then configures flow
1876  *  control.  Calls the appropriate media-specific link configuration
1877  *  function.  Assuming the adapter has a valid link partner, a valid link
1878  *  should be established.  Assumes the hardware has previously been reset
1879  *  and the transmitter and receiver are not enabled.
1880  **/
1881 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
1882 {
1883         s32 ret_val;
1884
1885         if (e1000_check_reset_block(hw))
1886                 return 0;
1887
1888         /*
1889          * ICH parts do not have a word in the NVM to determine
1890          * the default flow control setting, so we explicitly
1891          * set it to full.
1892          */
1893         if (hw->fc.type == e1000_fc_default)
1894                 hw->fc.type = e1000_fc_full;
1895
1896         hw->fc.original_type = hw->fc.type;
1897
1898         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
1899
1900         /* Continue to configure the copper link. */
1901         ret_val = e1000_setup_copper_link_ich8lan(hw);
1902         if (ret_val)
1903                 return ret_val;
1904
1905         ew32(FCTTV, hw->fc.pause_time);
1906
1907         return e1000e_set_fc_watermarks(hw);
1908 }
1909
1910 /**
1911  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
1912  *  @hw: pointer to the HW structure
1913  *
1914  *  Configures the kumeran interface to the PHY to wait the appropriate time
1915  *  when polling the PHY, then call the generic setup_copper_link to finish
1916  *  configuring the copper link.
1917  **/
1918 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
1919 {
1920         u32 ctrl;
1921         s32 ret_val;
1922         u16 reg_data;
1923
1924         ctrl = er32(CTRL);
1925         ctrl |= E1000_CTRL_SLU;
1926         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1927         ew32(CTRL, ctrl);
1928
1929         /*
1930          * Set the mac to wait the maximum time between each iteration
1931          * and increase the max iterations when polling the phy;
1932          * this fixes erroneous timeouts at 10Mbps.
1933          */
1934         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1935         if (ret_val)
1936                 return ret_val;
1937         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1938         if (ret_val)
1939                 return ret_val;
1940         reg_data |= 0x3F;
1941         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1942         if (ret_val)
1943                 return ret_val;
1944
1945         if (hw->phy.type == e1000_phy_igp_3) {
1946                 ret_val = e1000e_copper_link_setup_igp(hw);
1947                 if (ret_val)
1948                         return ret_val;
1949         } else if (hw->phy.type == e1000_phy_bm) {
1950                 ret_val = e1000e_copper_link_setup_m88(hw);
1951                 if (ret_val)
1952                         return ret_val;
1953         }
1954
1955         if (hw->phy.type == e1000_phy_ife) {
1956                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
1957                 if (ret_val)
1958                         return ret_val;
1959
1960                 reg_data &= ~IFE_PMC_AUTO_MDIX;
1961
1962                 switch (hw->phy.mdix) {
1963                 case 1:
1964                         reg_data &= ~IFE_PMC_FORCE_MDIX;
1965                         break;
1966                 case 2:
1967                         reg_data |= IFE_PMC_FORCE_MDIX;
1968                         break;
1969                 case 0:
1970                 default:
1971                         reg_data |= IFE_PMC_AUTO_MDIX;
1972                         break;
1973                 }
1974                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
1975                 if (ret_val)
1976                         return ret_val;
1977         }
1978         return e1000e_setup_copper_link(hw);
1979 }
1980
1981 /**
1982  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
1983  *  @hw: pointer to the HW structure
1984  *  @speed: pointer to store current link speed
1985  *  @duplex: pointer to store the current link duplex
1986  *
1987  *  Calls the generic get_speed_and_duplex to retrieve the current link
1988  *  information and then calls the Kumeran lock loss workaround for links at
1989  *  gigabit speeds.
1990  **/
1991 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
1992                                           u16 *duplex)
1993 {
1994         s32 ret_val;
1995
1996         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
1997         if (ret_val)
1998                 return ret_val;
1999
2000         if ((hw->mac.type == e1000_ich8lan) &&
2001             (hw->phy.type == e1000_phy_igp_3) &&
2002             (*speed == SPEED_1000)) {
2003                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2004         }
2005
2006         return ret_val;
2007 }
2008
2009 /**
2010  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2011  *  @hw: pointer to the HW structure
2012  *
2013  *  Work-around for 82566 Kumeran PCS lock loss:
2014  *  On link status change (i.e. PCI reset, speed change) and link is up and
2015  *  speed is gigabit-
2016  *    0) if workaround is optionally disabled do nothing
2017  *    1) wait 1ms for Kumeran link to come up
2018  *    2) check Kumeran Diagnostic register PCS lock loss bit
2019  *    3) if not set the link is locked (all is good), otherwise...
2020  *    4) reset the PHY
2021  *    5) repeat up to 10 times
2022  *  Note: this is only called for IGP3 copper when speed is 1gb.
2023  **/
2024 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2025 {
2026         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2027         u32 phy_ctrl;
2028         s32 ret_val;
2029         u16 i, data;
2030         bool link;
2031
2032         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2033                 return 0;
2034
2035         /*
2036          * Make sure link is up before proceeding.  If not just return.
2037          * Attempting this while link is negotiating fouled up link
2038          * stability
2039          */
2040         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2041         if (!link)
2042                 return 0;
2043
2044         for (i = 0; i < 10; i++) {
2045                 /* read once to clear */
2046                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2047                 if (ret_val)
2048                         return ret_val;
2049                 /* and again to get new status */
2050                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2051                 if (ret_val)
2052                         return ret_val;
2053
2054                 /* check for PCS lock */
2055                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2056                         return 0;
2057
2058                 /* Issue PHY reset */
2059                 e1000_phy_hw_reset(hw);
2060                 mdelay(5);
2061         }
2062         /* Disable GigE link negotiation */
2063         phy_ctrl = er32(PHY_CTRL);
2064         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2065                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2066         ew32(PHY_CTRL, phy_ctrl);
2067
2068         /*
2069          * Call gig speed drop workaround on Gig disable before accessing
2070          * any PHY registers
2071          */
2072         e1000e_gig_downshift_workaround_ich8lan(hw);
2073
2074         /* unable to acquire PCS lock */
2075         return -E1000_ERR_PHY;
2076 }
2077
2078 /**
2079  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2080  *  @hw: pointer to the HW structure
2081  *  @state: boolean value used to set the current Kumeran workaround state
2082  *
2083  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2084  *  /disabled - FALSE).
2085  **/
2086 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2087                                                  bool state)
2088 {
2089         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2090
2091         if (hw->mac.type != e1000_ich8lan) {
2092                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2093                 return;
2094         }
2095
2096         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2097 }
2098
2099 /**
2100  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2101  *  @hw: pointer to the HW structure
2102  *
2103  *  Workaround for 82566 power-down on D3 entry:
2104  *    1) disable gigabit link
2105  *    2) write VR power-down enable
2106  *    3) read it back
2107  *  Continue if successful, else issue LCD reset and repeat
2108  **/
2109 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2110 {
2111         u32 reg;
2112         u16 data;
2113         u8  retry = 0;
2114
2115         if (hw->phy.type != e1000_phy_igp_3)
2116                 return;
2117
2118         /* Try the workaround twice (if needed) */
2119         do {
2120                 /* Disable link */
2121                 reg = er32(PHY_CTRL);
2122                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2123                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2124                 ew32(PHY_CTRL, reg);
2125
2126                 /*
2127                  * Call gig speed drop workaround on Gig disable before
2128                  * accessing any PHY registers
2129                  */
2130                 if (hw->mac.type == e1000_ich8lan)
2131                         e1000e_gig_downshift_workaround_ich8lan(hw);
2132
2133                 /* Write VR power-down enable */
2134                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2135                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2136                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2137
2138                 /* Read it back and test */
2139                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2140                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2141                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2142                         break;
2143
2144                 /* Issue PHY reset and repeat at most one more time */
2145                 reg = er32(CTRL);
2146                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2147                 retry++;
2148         } while (retry);
2149 }
2150
2151 /**
2152  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2153  *  @hw: pointer to the HW structure
2154  *
2155  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2156  *  LPLU, Gig disable, MDIC PHY reset):
2157  *    1) Set Kumeran Near-end loopback
2158  *    2) Clear Kumeran Near-end loopback
2159  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2160  **/
2161 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2162 {
2163         s32 ret_val;
2164         u16 reg_data;
2165
2166         if ((hw->mac.type != e1000_ich8lan) ||
2167             (hw->phy.type != e1000_phy_igp_3))
2168                 return;
2169
2170         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2171                                       &reg_data);
2172         if (ret_val)
2173                 return;
2174         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2175         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2176                                        reg_data);
2177         if (ret_val)
2178                 return;
2179         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2180         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2181                                        reg_data);
2182 }
2183
2184 /**
2185  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2186  *  @hw: pointer to the HW structure
2187  *
2188  *  During S0 to Sx transition, it is possible the link remains at gig
2189  *  instead of negotiating to a lower speed.  Before going to Sx, set
2190  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2191  *  to a lower speed.
2192  *
2193  *  Should only be called for ICH9 devices.
2194  **/
2195 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2196 {
2197         u32 phy_ctrl;
2198
2199         if (hw->mac.type == e1000_ich9lan) {
2200                 phy_ctrl = er32(PHY_CTRL);
2201                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2202                             E1000_PHY_CTRL_GBE_DISABLE;
2203                 ew32(PHY_CTRL, phy_ctrl);
2204         }
2205
2206         return;
2207 }
2208
2209 /**
2210  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2211  *  @hw: pointer to the HW structure
2212  *
2213  *  Return the LED back to the default configuration.
2214  **/
2215 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2216 {
2217         if (hw->phy.type == e1000_phy_ife)
2218                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2219
2220         ew32(LEDCTL, hw->mac.ledctl_default);
2221         return 0;
2222 }
2223
2224 /**
2225  *  e1000_led_on_ich8lan - Turn LEDs on
2226  *  @hw: pointer to the HW structure
2227  *
2228  *  Turn on the LEDs.
2229  **/
2230 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2231 {
2232         if (hw->phy.type == e1000_phy_ife)
2233                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2234                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2235
2236         ew32(LEDCTL, hw->mac.ledctl_mode2);
2237         return 0;
2238 }
2239
2240 /**
2241  *  e1000_led_off_ich8lan - Turn LEDs off
2242  *  @hw: pointer to the HW structure
2243  *
2244  *  Turn off the LEDs.
2245  **/
2246 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2247 {
2248         if (hw->phy.type == e1000_phy_ife)
2249                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2250                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2251
2252         ew32(LEDCTL, hw->mac.ledctl_mode1);
2253         return 0;
2254 }
2255
2256 /**
2257  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2258  *  @hw: pointer to the HW structure
2259  *
2260  *  Clears hardware counters specific to the silicon family and calls
2261  *  clear_hw_cntrs_generic to clear all general purpose counters.
2262  **/
2263 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2264 {
2265         u32 temp;
2266
2267         e1000e_clear_hw_cntrs_base(hw);
2268
2269         temp = er32(ALGNERRC);
2270         temp = er32(RXERRC);
2271         temp = er32(TNCRS);
2272         temp = er32(CEXTERR);
2273         temp = er32(TSCTC);
2274         temp = er32(TSCTFC);
2275
2276         temp = er32(MGTPRC);
2277         temp = er32(MGTPDC);
2278         temp = er32(MGTPTC);
2279
2280         temp = er32(IAC);
2281         temp = er32(ICRXOC);
2282
2283 }
2284
2285 static struct e1000_mac_operations ich8_mac_ops = {
2286         .mng_mode_enab          = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
2287         .check_for_link         = e1000e_check_for_copper_link,
2288         .cleanup_led            = e1000_cleanup_led_ich8lan,
2289         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2290         .get_bus_info           = e1000_get_bus_info_ich8lan,
2291         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2292         .led_on                 = e1000_led_on_ich8lan,
2293         .led_off                = e1000_led_off_ich8lan,
2294         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2295         .reset_hw               = e1000_reset_hw_ich8lan,
2296         .init_hw                = e1000_init_hw_ich8lan,
2297         .setup_link             = e1000_setup_link_ich8lan,
2298         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2299 };
2300
2301 static struct e1000_phy_operations ich8_phy_ops = {
2302         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2303         .check_reset_block      = e1000_check_reset_block_ich8lan,
2304         .commit_phy             = NULL,
2305         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2306         .get_cfg_done           = e1000e_get_cfg_done,
2307         .get_cable_length       = e1000e_get_cable_length_igp_2,
2308         .get_phy_info           = e1000_get_phy_info_ich8lan,
2309         .read_phy_reg           = e1000e_read_phy_reg_igp,
2310         .release_phy            = e1000_release_swflag_ich8lan,
2311         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2312         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2313         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2314         .write_phy_reg          = e1000e_write_phy_reg_igp,
2315 };
2316
2317 static struct e1000_nvm_operations ich8_nvm_ops = {
2318         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2319         .read_nvm               = e1000_read_nvm_ich8lan,
2320         .release_nvm            = e1000_release_swflag_ich8lan,
2321         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2322         .valid_led_default      = e1000_valid_led_default_ich8lan,
2323         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2324         .write_nvm              = e1000_write_nvm_ich8lan,
2325 };
2326
2327 struct e1000_info e1000_ich8_info = {
2328         .mac                    = e1000_ich8lan,
2329         .flags                  = FLAG_HAS_WOL
2330                                   | FLAG_IS_ICH
2331                                   | FLAG_RX_CSUM_ENABLED
2332                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2333                                   | FLAG_HAS_AMT
2334                                   | FLAG_HAS_FLASH
2335                                   | FLAG_APME_IN_WUC,
2336         .pba                    = 8,
2337         .get_variants           = e1000_get_variants_ich8lan,
2338         .mac_ops                = &ich8_mac_ops,
2339         .phy_ops                = &ich8_phy_ops,
2340         .nvm_ops                = &ich8_nvm_ops,
2341 };
2342
2343 struct e1000_info e1000_ich9_info = {
2344         .mac                    = e1000_ich9lan,
2345         .flags                  = FLAG_HAS_JUMBO_FRAMES
2346                                   | FLAG_IS_ICH
2347                                   | FLAG_HAS_WOL
2348                                   | FLAG_RX_CSUM_ENABLED
2349                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2350                                   | FLAG_HAS_AMT
2351                                   | FLAG_HAS_ERT
2352                                   | FLAG_HAS_FLASH
2353                                   | FLAG_APME_IN_WUC,
2354         .pba                    = 10,
2355         .get_variants           = e1000_get_variants_ich8lan,
2356         .mac_ops                = &ich8_mac_ops,
2357         .phy_ops                = &ich8_phy_ops,
2358         .nvm_ops                = &ich8_nvm_ops,
2359 };
2360