e1000e: add support for 82567LM-3 and 82567LF-3 (ICH10D) parts
[linux-2.6.git] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 82562G-2 10/100 Network Connection
31  * 82562GT 10/100 Network Connection
32  * 82562GT-2 10/100 Network Connection
33  * 82562V 10/100 Network Connection
34  * 82562V-2 10/100 Network Connection
35  * 82566DC-2 Gigabit Network Connection
36  * 82566DC Gigabit Network Connection
37  * 82566DM-2 Gigabit Network Connection
38  * 82566DM Gigabit Network Connection
39  * 82566MC Gigabit Network Connection
40  * 82566MM Gigabit Network Connection
41  * 82567LM Gigabit Network Connection
42  * 82567LF Gigabit Network Connection
43  * 82567LM-2 Gigabit Network Connection
44  * 82567LF-2 Gigabit Network Connection
45  * 82567V-2 Gigabit Network Connection
46  * 82567LF-3 Gigabit Network Connection
47  * 82567LM-3 Gigabit Network Connection
48  * 82567LM-4 Gigabit Network Connection
49  */
50
51 #include <linux/netdevice.h>
52 #include <linux/ethtool.h>
53 #include <linux/delay.h>
54 #include <linux/pci.h>
55
56 #include "e1000.h"
57
58 #define ICH_FLASH_GFPREG                0x0000
59 #define ICH_FLASH_HSFSTS                0x0004
60 #define ICH_FLASH_HSFCTL                0x0006
61 #define ICH_FLASH_FADDR                 0x0008
62 #define ICH_FLASH_FDATA0                0x0010
63
64 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
65 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
66 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
67 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
68 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
69
70 #define ICH_CYCLE_READ                  0
71 #define ICH_CYCLE_WRITE                 2
72 #define ICH_CYCLE_ERASE                 3
73
74 #define FLASH_GFPREG_BASE_MASK          0x1FFF
75 #define FLASH_SECTOR_ADDR_SHIFT         12
76
77 #define ICH_FLASH_SEG_SIZE_256          256
78 #define ICH_FLASH_SEG_SIZE_4K           4096
79 #define ICH_FLASH_SEG_SIZE_8K           8192
80 #define ICH_FLASH_SEG_SIZE_64K          65536
81
82
83 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
84
85 #define E1000_ICH_MNG_IAMT_MODE         0x2
86
87 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
88                                  (ID_LED_DEF1_OFF2 <<  8) | \
89                                  (ID_LED_DEF1_ON2  <<  4) | \
90                                  (ID_LED_DEF1_DEF2))
91
92 #define E1000_ICH_NVM_SIG_WORD          0x13
93 #define E1000_ICH_NVM_SIG_MASK          0xC000
94
95 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
96
97 #define E1000_FEXTNVM_SW_CONFIG         1
98 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
99
100 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
101
102 #define E1000_ICH_RAR_ENTRIES           7
103
104 #define PHY_PAGE_SHIFT 5
105 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
106                            ((reg) & MAX_PHY_REG_ADDRESS))
107 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
108 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
109
110 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
111 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
112 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
113
114 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
115 /* Offset 04h HSFSTS */
116 union ich8_hws_flash_status {
117         struct ich8_hsfsts {
118                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
119                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
120                 u16 dael       :1; /* bit 2 Direct Access error Log */
121                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
122                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
123                 u16 reserved1  :2; /* bit 13:6 Reserved */
124                 u16 reserved2  :6; /* bit 13:6 Reserved */
125                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
126                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
127         } hsf_status;
128         u16 regval;
129 };
130
131 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
132 /* Offset 06h FLCTL */
133 union ich8_hws_flash_ctrl {
134         struct ich8_hsflctl {
135                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
136                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
137                 u16 reserved   :5;   /* 7:3 Reserved  */
138                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
139                 u16 flockdn    :6;   /* 15:10 Reserved */
140         } hsf_ctrl;
141         u16 regval;
142 };
143
144 /* ICH Flash Region Access Permissions */
145 union ich8_hws_flash_regacc {
146         struct ich8_flracc {
147                 u32 grra      :8; /* 0:7 GbE region Read Access */
148                 u32 grwa      :8; /* 8:15 GbE region Write Access */
149                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
150                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
151         } hsf_flregacc;
152         u16 regval;
153 };
154
155 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
156 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
157 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
158 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
159 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
160 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
161                                                 u32 offset, u8 byte);
162 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
163                                          u8 *data);
164 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
165                                          u16 *data);
166 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
167                                          u8 size, u16 *data);
168 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
169 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
170 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
171
172 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
173 {
174         return readw(hw->flash_address + reg);
175 }
176
177 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
178 {
179         return readl(hw->flash_address + reg);
180 }
181
182 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
183 {
184         writew(val, hw->flash_address + reg);
185 }
186
187 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
188 {
189         writel(val, hw->flash_address + reg);
190 }
191
192 #define er16flash(reg)          __er16flash(hw, (reg))
193 #define er32flash(reg)          __er32flash(hw, (reg))
194 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
195 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
196
197 /**
198  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
199  *  @hw: pointer to the HW structure
200  *
201  *  Initialize family-specific PHY parameters and function pointers.
202  **/
203 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
204 {
205         struct e1000_phy_info *phy = &hw->phy;
206         s32 ret_val;
207         u16 i = 0;
208
209         phy->addr                       = 1;
210         phy->reset_delay_us             = 100;
211
212         /*
213          * We may need to do this twice - once for IGP and if that fails,
214          * we'll set BM func pointers and try again
215          */
216         ret_val = e1000e_determine_phy_address(hw);
217         if (ret_val) {
218                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
219                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
220                 ret_val = e1000e_determine_phy_address(hw);
221                 if (ret_val)
222                         return ret_val;
223         }
224
225         phy->id = 0;
226         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
227                (i++ < 100)) {
228                 msleep(1);
229                 ret_val = e1000e_get_phy_id(hw);
230                 if (ret_val)
231                         return ret_val;
232         }
233
234         /* Verify phy id */
235         switch (phy->id) {
236         case IGP03E1000_E_PHY_ID:
237                 phy->type = e1000_phy_igp_3;
238                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
239                 break;
240         case IFE_E_PHY_ID:
241         case IFE_PLUS_E_PHY_ID:
242         case IFE_C_E_PHY_ID:
243                 phy->type = e1000_phy_ife;
244                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
245                 break;
246         case BME1000_E_PHY_ID:
247                 phy->type = e1000_phy_bm;
248                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
249                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
250                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
251                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
252                 break;
253         default:
254                 return -E1000_ERR_PHY;
255                 break;
256         }
257
258         return 0;
259 }
260
261 /**
262  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
263  *  @hw: pointer to the HW structure
264  *
265  *  Initialize family-specific NVM parameters and function
266  *  pointers.
267  **/
268 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
269 {
270         struct e1000_nvm_info *nvm = &hw->nvm;
271         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
272         u32 gfpreg;
273         u32 sector_base_addr;
274         u32 sector_end_addr;
275         u16 i;
276
277         /* Can't read flash registers if the register set isn't mapped. */
278         if (!hw->flash_address) {
279                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
280                 return -E1000_ERR_CONFIG;
281         }
282
283         nvm->type = e1000_nvm_flash_sw;
284
285         gfpreg = er32flash(ICH_FLASH_GFPREG);
286
287         /*
288          * sector_X_addr is a "sector"-aligned address (4096 bytes)
289          * Add 1 to sector_end_addr since this sector is included in
290          * the overall size.
291          */
292         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
293         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
294
295         /* flash_base_addr is byte-aligned */
296         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
297
298         /*
299          * find total size of the NVM, then cut in half since the total
300          * size represents two separate NVM banks.
301          */
302         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
303                                 << FLASH_SECTOR_ADDR_SHIFT;
304         nvm->flash_bank_size /= 2;
305         /* Adjust to word count */
306         nvm->flash_bank_size /= sizeof(u16);
307
308         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
309
310         /* Clear shadow ram */
311         for (i = 0; i < nvm->word_size; i++) {
312                 dev_spec->shadow_ram[i].modified = 0;
313                 dev_spec->shadow_ram[i].value    = 0xFFFF;
314         }
315
316         return 0;
317 }
318
319 /**
320  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
321  *  @hw: pointer to the HW structure
322  *
323  *  Initialize family-specific MAC parameters and function
324  *  pointers.
325  **/
326 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
327 {
328         struct e1000_hw *hw = &adapter->hw;
329         struct e1000_mac_info *mac = &hw->mac;
330
331         /* Set media type function pointer */
332         hw->phy.media_type = e1000_media_type_copper;
333
334         /* Set mta register count */
335         mac->mta_reg_count = 32;
336         /* Set rar entry count */
337         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
338         if (mac->type == e1000_ich8lan)
339                 mac->rar_entry_count--;
340         /* Set if manageability features are enabled. */
341         mac->arc_subsystem_valid = 1;
342
343         /* Enable PCS Lock-loss workaround for ICH8 */
344         if (mac->type == e1000_ich8lan)
345                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
346
347         return 0;
348 }
349
350 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
351 {
352         struct e1000_hw *hw = &adapter->hw;
353         s32 rc;
354
355         rc = e1000_init_mac_params_ich8lan(adapter);
356         if (rc)
357                 return rc;
358
359         rc = e1000_init_nvm_params_ich8lan(hw);
360         if (rc)
361                 return rc;
362
363         rc = e1000_init_phy_params_ich8lan(hw);
364         if (rc)
365                 return rc;
366
367         if ((adapter->hw.mac.type == e1000_ich8lan) &&
368             (adapter->hw.phy.type == e1000_phy_igp_3))
369                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
370
371         return 0;
372 }
373
374 /**
375  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
376  *  @hw: pointer to the HW structure
377  *
378  *  Acquires the software control flag for performing NVM and PHY
379  *  operations.  This is a function pointer entry point only called by
380  *  read/write routines for the PHY and NVM parts.
381  **/
382 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
383 {
384         u32 extcnf_ctrl;
385         u32 timeout = PHY_CFG_TIMEOUT;
386
387         while (timeout) {
388                 extcnf_ctrl = er32(EXTCNF_CTRL);
389                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
390                 ew32(EXTCNF_CTRL, extcnf_ctrl);
391
392                 extcnf_ctrl = er32(EXTCNF_CTRL);
393                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
394                         break;
395                 mdelay(1);
396                 timeout--;
397         }
398
399         if (!timeout) {
400                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
401                 return -E1000_ERR_CONFIG;
402         }
403
404         return 0;
405 }
406
407 /**
408  *  e1000_release_swflag_ich8lan - Release software control flag
409  *  @hw: pointer to the HW structure
410  *
411  *  Releases the software control flag for performing NVM and PHY operations.
412  *  This is a function pointer entry point only called by read/write
413  *  routines for the PHY and NVM parts.
414  **/
415 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
416 {
417         u32 extcnf_ctrl;
418
419         extcnf_ctrl = er32(EXTCNF_CTRL);
420         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
421         ew32(EXTCNF_CTRL, extcnf_ctrl);
422 }
423
424 /**
425  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
426  *  @hw: pointer to the HW structure
427  *
428  *  Checks if firmware is blocking the reset of the PHY.
429  *  This is a function pointer entry point only called by
430  *  reset routines.
431  **/
432 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
433 {
434         u32 fwsm;
435
436         fwsm = er32(FWSM);
437
438         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
439 }
440
441 /**
442  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
443  *  @hw: pointer to the HW structure
444  *
445  *  Forces the speed and duplex settings of the PHY.
446  *  This is a function pointer entry point only called by
447  *  PHY setup routines.
448  **/
449 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
450 {
451         struct e1000_phy_info *phy = &hw->phy;
452         s32 ret_val;
453         u16 data;
454         bool link;
455
456         if (phy->type != e1000_phy_ife) {
457                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
458                 return ret_val;
459         }
460
461         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
462         if (ret_val)
463                 return ret_val;
464
465         e1000e_phy_force_speed_duplex_setup(hw, &data);
466
467         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
468         if (ret_val)
469                 return ret_val;
470
471         /* Disable MDI-X support for 10/100 */
472         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
473         if (ret_val)
474                 return ret_val;
475
476         data &= ~IFE_PMC_AUTO_MDIX;
477         data &= ~IFE_PMC_FORCE_MDIX;
478
479         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
480         if (ret_val)
481                 return ret_val;
482
483         hw_dbg(hw, "IFE PMC: %X\n", data);
484
485         udelay(1);
486
487         if (phy->autoneg_wait_to_complete) {
488                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
489
490                 ret_val = e1000e_phy_has_link_generic(hw,
491                                                      PHY_FORCE_LIMIT,
492                                                      100000,
493                                                      &link);
494                 if (ret_val)
495                         return ret_val;
496
497                 if (!link)
498                         hw_dbg(hw, "Link taking longer than expected.\n");
499
500                 /* Try once more */
501                 ret_val = e1000e_phy_has_link_generic(hw,
502                                                      PHY_FORCE_LIMIT,
503                                                      100000,
504                                                      &link);
505                 if (ret_val)
506                         return ret_val;
507         }
508
509         return 0;
510 }
511
512 /**
513  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
514  *  @hw: pointer to the HW structure
515  *
516  *  Resets the PHY
517  *  This is a function pointer entry point called by drivers
518  *  or other shared routines.
519  **/
520 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
521 {
522         struct e1000_phy_info *phy = &hw->phy;
523         u32 i;
524         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
525         s32 ret_val;
526         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
527         u16 word_addr, reg_data, reg_addr, phy_page = 0;
528
529         ret_val = e1000e_phy_hw_reset_generic(hw);
530         if (ret_val)
531                 return ret_val;
532
533         /*
534          * Initialize the PHY from the NVM on ICH platforms.  This
535          * is needed due to an issue where the NVM configuration is
536          * not properly autoloaded after power transitions.
537          * Therefore, after each PHY reset, we will load the
538          * configuration data out of the NVM manually.
539          */
540         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
541                 struct e1000_adapter *adapter = hw->adapter;
542
543                 /* Check if SW needs configure the PHY */
544                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
545                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
546                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
547                 else
548                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
549
550                 data = er32(FEXTNVM);
551                 if (!(data & sw_cfg_mask))
552                         return 0;
553
554                 /* Wait for basic configuration completes before proceeding*/
555                 do {
556                         data = er32(STATUS);
557                         data &= E1000_STATUS_LAN_INIT_DONE;
558                         udelay(100);
559                 } while ((!data) && --loop);
560
561                 /*
562                  * If basic configuration is incomplete before the above loop
563                  * count reaches 0, loading the configuration from NVM will
564                  * leave the PHY in a bad state possibly resulting in no link.
565                  */
566                 if (loop == 0) {
567                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
568                 }
569
570                 /* Clear the Init Done bit for the next init event */
571                 data = er32(STATUS);
572                 data &= ~E1000_STATUS_LAN_INIT_DONE;
573                 ew32(STATUS, data);
574
575                 /*
576                  * Make sure HW does not configure LCD from PHY
577                  * extended configuration before SW configuration
578                  */
579                 data = er32(EXTCNF_CTRL);
580                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
581                         return 0;
582
583                 cnf_size = er32(EXTCNF_SIZE);
584                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
585                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
586                 if (!cnf_size)
587                         return 0;
588
589                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
590                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
591
592                 /* Configure LCD from extended configuration region. */
593
594                 /* cnf_base_addr is in DWORD */
595                 word_addr = (u16)(cnf_base_addr << 1);
596
597                 for (i = 0; i < cnf_size; i++) {
598                         ret_val = e1000_read_nvm(hw,
599                                                 (word_addr + i * 2),
600                                                 1,
601                                                 &reg_data);
602                         if (ret_val)
603                                 return ret_val;
604
605                         ret_val = e1000_read_nvm(hw,
606                                                 (word_addr + i * 2 + 1),
607                                                 1,
608                                                 &reg_addr);
609                         if (ret_val)
610                                 return ret_val;
611
612                         /* Save off the PHY page for future writes. */
613                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
614                                 phy_page = reg_data;
615                                 continue;
616                         }
617
618                         reg_addr |= phy_page;
619
620                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
621                         if (ret_val)
622                                 return ret_val;
623                 }
624         }
625
626         return 0;
627 }
628
629 /**
630  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
631  *  @hw: pointer to the HW structure
632  *
633  *  Populates "phy" structure with various feature states.
634  *  This function is only called by other family-specific
635  *  routines.
636  **/
637 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
638 {
639         struct e1000_phy_info *phy = &hw->phy;
640         s32 ret_val;
641         u16 data;
642         bool link;
643
644         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
645         if (ret_val)
646                 return ret_val;
647
648         if (!link) {
649                 hw_dbg(hw, "Phy info is only valid if link is up\n");
650                 return -E1000_ERR_CONFIG;
651         }
652
653         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
654         if (ret_val)
655                 return ret_val;
656         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
657
658         if (phy->polarity_correction) {
659                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
660                 if (ret_val)
661                         return ret_val;
662         } else {
663                 /* Polarity is forced */
664                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
665                                       ? e1000_rev_polarity_reversed
666                                       : e1000_rev_polarity_normal;
667         }
668
669         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
670         if (ret_val)
671                 return ret_val;
672
673         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
674
675         /* The following parameters are undefined for 10/100 operation. */
676         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
677         phy->local_rx = e1000_1000t_rx_status_undefined;
678         phy->remote_rx = e1000_1000t_rx_status_undefined;
679
680         return 0;
681 }
682
683 /**
684  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
685  *  @hw: pointer to the HW structure
686  *
687  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
688  *  This is a function pointer entry point called by drivers
689  *  or other shared routines.
690  **/
691 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
692 {
693         switch (hw->phy.type) {
694         case e1000_phy_ife:
695                 return e1000_get_phy_info_ife_ich8lan(hw);
696                 break;
697         case e1000_phy_igp_3:
698         case e1000_phy_bm:
699                 return e1000e_get_phy_info_igp(hw);
700                 break;
701         default:
702                 break;
703         }
704
705         return -E1000_ERR_PHY_TYPE;
706 }
707
708 /**
709  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
710  *  @hw: pointer to the HW structure
711  *
712  *  Polarity is determined on the polarity reversal feature being enabled.
713  *  This function is only called by other family-specific
714  *  routines.
715  **/
716 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
717 {
718         struct e1000_phy_info *phy = &hw->phy;
719         s32 ret_val;
720         u16 phy_data, offset, mask;
721
722         /*
723          * Polarity is determined based on the reversal feature being enabled.
724          */
725         if (phy->polarity_correction) {
726                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
727                 mask    = IFE_PESC_POLARITY_REVERSED;
728         } else {
729                 offset  = IFE_PHY_SPECIAL_CONTROL;
730                 mask    = IFE_PSC_FORCE_POLARITY;
731         }
732
733         ret_val = e1e_rphy(hw, offset, &phy_data);
734
735         if (!ret_val)
736                 phy->cable_polarity = (phy_data & mask)
737                                       ? e1000_rev_polarity_reversed
738                                       : e1000_rev_polarity_normal;
739
740         return ret_val;
741 }
742
743 /**
744  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
745  *  @hw: pointer to the HW structure
746  *  @active: TRUE to enable LPLU, FALSE to disable
747  *
748  *  Sets the LPLU D0 state according to the active flag.  When
749  *  activating LPLU this function also disables smart speed
750  *  and vice versa.  LPLU will not be activated unless the
751  *  device autonegotiation advertisement meets standards of
752  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
753  *  This is a function pointer entry point only called by
754  *  PHY setup routines.
755  **/
756 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
757 {
758         struct e1000_phy_info *phy = &hw->phy;
759         u32 phy_ctrl;
760         s32 ret_val = 0;
761         u16 data;
762
763         if (phy->type == e1000_phy_ife)
764                 return ret_val;
765
766         phy_ctrl = er32(PHY_CTRL);
767
768         if (active) {
769                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
770                 ew32(PHY_CTRL, phy_ctrl);
771
772                 /*
773                  * Call gig speed drop workaround on LPLU before accessing
774                  * any PHY registers
775                  */
776                 if ((hw->mac.type == e1000_ich8lan) &&
777                     (hw->phy.type == e1000_phy_igp_3))
778                         e1000e_gig_downshift_workaround_ich8lan(hw);
779
780                 /* When LPLU is enabled, we should disable SmartSpeed */
781                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
782                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
783                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
784                 if (ret_val)
785                         return ret_val;
786         } else {
787                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
788                 ew32(PHY_CTRL, phy_ctrl);
789
790                 /*
791                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
792                  * during Dx states where the power conservation is most
793                  * important.  During driver activity we should enable
794                  * SmartSpeed, so performance is maintained.
795                  */
796                 if (phy->smart_speed == e1000_smart_speed_on) {
797                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
798                                            &data);
799                         if (ret_val)
800                                 return ret_val;
801
802                         data |= IGP01E1000_PSCFR_SMART_SPEED;
803                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
804                                            data);
805                         if (ret_val)
806                                 return ret_val;
807                 } else if (phy->smart_speed == e1000_smart_speed_off) {
808                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
809                                            &data);
810                         if (ret_val)
811                                 return ret_val;
812
813                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
814                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
815                                            data);
816                         if (ret_val)
817                                 return ret_val;
818                 }
819         }
820
821         return 0;
822 }
823
824 /**
825  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
826  *  @hw: pointer to the HW structure
827  *  @active: TRUE to enable LPLU, FALSE to disable
828  *
829  *  Sets the LPLU D3 state according to the active flag.  When
830  *  activating LPLU this function also disables smart speed
831  *  and vice versa.  LPLU will not be activated unless the
832  *  device autonegotiation advertisement meets standards of
833  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
834  *  This is a function pointer entry point only called by
835  *  PHY setup routines.
836  **/
837 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
838 {
839         struct e1000_phy_info *phy = &hw->phy;
840         u32 phy_ctrl;
841         s32 ret_val;
842         u16 data;
843
844         phy_ctrl = er32(PHY_CTRL);
845
846         if (!active) {
847                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
848                 ew32(PHY_CTRL, phy_ctrl);
849                 /*
850                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
851                  * during Dx states where the power conservation is most
852                  * important.  During driver activity we should enable
853                  * SmartSpeed, so performance is maintained.
854                  */
855                 if (phy->smart_speed == e1000_smart_speed_on) {
856                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
857                                            &data);
858                         if (ret_val)
859                                 return ret_val;
860
861                         data |= IGP01E1000_PSCFR_SMART_SPEED;
862                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
863                                            data);
864                         if (ret_val)
865                                 return ret_val;
866                 } else if (phy->smart_speed == e1000_smart_speed_off) {
867                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
868                                            &data);
869                         if (ret_val)
870                                 return ret_val;
871
872                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
873                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
874                                            data);
875                         if (ret_val)
876                                 return ret_val;
877                 }
878         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
879                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
880                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
881                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
882                 ew32(PHY_CTRL, phy_ctrl);
883
884                 /*
885                  * Call gig speed drop workaround on LPLU before accessing
886                  * any PHY registers
887                  */
888                 if ((hw->mac.type == e1000_ich8lan) &&
889                     (hw->phy.type == e1000_phy_igp_3))
890                         e1000e_gig_downshift_workaround_ich8lan(hw);
891
892                 /* When LPLU is enabled, we should disable SmartSpeed */
893                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
894                 if (ret_val)
895                         return ret_val;
896
897                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
898                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
899         }
900
901         return 0;
902 }
903
904 /**
905  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
906  *  @hw: pointer to the HW structure
907  *  @bank:  pointer to the variable that returns the active bank
908  *
909  *  Reads signature byte from the NVM using the flash access registers.
910  **/
911 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
912 {
913         struct e1000_nvm_info *nvm = &hw->nvm;
914         /* flash bank size is in words */
915         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
916         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
917         u8 bank_high_byte = 0;
918
919         if (hw->mac.type != e1000_ich10lan) {
920                 if (er32(EECD) & E1000_EECD_SEC1VAL)
921                         *bank = 1;
922                 else
923                         *bank = 0;
924         } else {
925                 /*
926                  * Make sure the signature for bank 0 is valid,
927                  * if not check for bank1
928                  */
929                 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
930                 if ((bank_high_byte & 0xC0) == 0x80) {
931                         *bank = 0;
932                 } else {
933                         /*
934                          * find if segment 1 is valid by verifying
935                          * bit 15:14 = 10b in word 0x13
936                          */
937                         e1000_read_flash_byte_ich8lan(hw,
938                                                       act_offset + bank1_offset,
939                                                       &bank_high_byte);
940
941                         /* bank1 has a valid signature equivalent to SEC1V */
942                         if ((bank_high_byte & 0xC0) == 0x80) {
943                                 *bank = 1;
944                         } else {
945                                 hw_dbg(hw, "ERROR: EEPROM not present\n");
946                                 return -E1000_ERR_NVM;
947                         }
948                 }
949         }
950
951         return 0;
952 }
953
954 /**
955  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
956  *  @hw: pointer to the HW structure
957  *  @offset: The offset (in bytes) of the word(s) to read.
958  *  @words: Size of data to read in words
959  *  @data: Pointer to the word(s) to read at offset.
960  *
961  *  Reads a word(s) from the NVM using the flash access registers.
962  **/
963 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
964                                   u16 *data)
965 {
966         struct e1000_nvm_info *nvm = &hw->nvm;
967         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
968         u32 act_offset;
969         s32 ret_val;
970         u32 bank = 0;
971         u16 i, word;
972
973         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
974             (words == 0)) {
975                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
976                 return -E1000_ERR_NVM;
977         }
978
979         ret_val = e1000_acquire_swflag_ich8lan(hw);
980         if (ret_val)
981                 return ret_val;
982
983         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
984         if (ret_val)
985                 return ret_val;
986
987         act_offset = (bank) ? nvm->flash_bank_size : 0;
988         act_offset += offset;
989
990         for (i = 0; i < words; i++) {
991                 if ((dev_spec->shadow_ram) &&
992                     (dev_spec->shadow_ram[offset+i].modified)) {
993                         data[i] = dev_spec->shadow_ram[offset+i].value;
994                 } else {
995                         ret_val = e1000_read_flash_word_ich8lan(hw,
996                                                                 act_offset + i,
997                                                                 &word);
998                         if (ret_val)
999                                 break;
1000                         data[i] = word;
1001                 }
1002         }
1003
1004         e1000_release_swflag_ich8lan(hw);
1005
1006         return ret_val;
1007 }
1008
1009 /**
1010  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1011  *  @hw: pointer to the HW structure
1012  *
1013  *  This function does initial flash setup so that a new read/write/erase cycle
1014  *  can be started.
1015  **/
1016 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1017 {
1018         union ich8_hws_flash_status hsfsts;
1019         s32 ret_val = -E1000_ERR_NVM;
1020         s32 i = 0;
1021
1022         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1023
1024         /* Check if the flash descriptor is valid */
1025         if (hsfsts.hsf_status.fldesvalid == 0) {
1026                 hw_dbg(hw, "Flash descriptor invalid.  "
1027                          "SW Sequencing must be used.");
1028                 return -E1000_ERR_NVM;
1029         }
1030
1031         /* Clear FCERR and DAEL in hw status by writing 1 */
1032         hsfsts.hsf_status.flcerr = 1;
1033         hsfsts.hsf_status.dael = 1;
1034
1035         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1036
1037         /*
1038          * Either we should have a hardware SPI cycle in progress
1039          * bit to check against, in order to start a new cycle or
1040          * FDONE bit should be changed in the hardware so that it
1041          * is 1 after hardware reset, which can then be used as an
1042          * indication whether a cycle is in progress or has been
1043          * completed.
1044          */
1045
1046         if (hsfsts.hsf_status.flcinprog == 0) {
1047                 /*
1048                  * There is no cycle running at present,
1049                  * so we can start a cycle
1050                  * Begin by setting Flash Cycle Done.
1051                  */
1052                 hsfsts.hsf_status.flcdone = 1;
1053                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1054                 ret_val = 0;
1055         } else {
1056                 /*
1057                  * otherwise poll for sometime so the current
1058                  * cycle has a chance to end before giving up.
1059                  */
1060                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1061                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1062                         if (hsfsts.hsf_status.flcinprog == 0) {
1063                                 ret_val = 0;
1064                                 break;
1065                         }
1066                         udelay(1);
1067                 }
1068                 if (ret_val == 0) {
1069                         /*
1070                          * Successful in waiting for previous cycle to timeout,
1071                          * now set the Flash Cycle Done.
1072                          */
1073                         hsfsts.hsf_status.flcdone = 1;
1074                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1075                 } else {
1076                         hw_dbg(hw, "Flash controller busy, cannot get access");
1077                 }
1078         }
1079
1080         return ret_val;
1081 }
1082
1083 /**
1084  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1085  *  @hw: pointer to the HW structure
1086  *  @timeout: maximum time to wait for completion
1087  *
1088  *  This function starts a flash cycle and waits for its completion.
1089  **/
1090 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1091 {
1092         union ich8_hws_flash_ctrl hsflctl;
1093         union ich8_hws_flash_status hsfsts;
1094         s32 ret_val = -E1000_ERR_NVM;
1095         u32 i = 0;
1096
1097         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1098         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1099         hsflctl.hsf_ctrl.flcgo = 1;
1100         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1101
1102         /* wait till FDONE bit is set to 1 */
1103         do {
1104                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1105                 if (hsfsts.hsf_status.flcdone == 1)
1106                         break;
1107                 udelay(1);
1108         } while (i++ < timeout);
1109
1110         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1111                 return 0;
1112
1113         return ret_val;
1114 }
1115
1116 /**
1117  *  e1000_read_flash_word_ich8lan - Read word from flash
1118  *  @hw: pointer to the HW structure
1119  *  @offset: offset to data location
1120  *  @data: pointer to the location for storing the data
1121  *
1122  *  Reads the flash word at offset into data.  Offset is converted
1123  *  to bytes before read.
1124  **/
1125 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1126                                          u16 *data)
1127 {
1128         /* Must convert offset into bytes. */
1129         offset <<= 1;
1130
1131         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1132 }
1133
1134 /**
1135  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1136  *  @hw: pointer to the HW structure
1137  *  @offset: The offset of the byte to read.
1138  *  @data: Pointer to a byte to store the value read.
1139  *
1140  *  Reads a single byte from the NVM using the flash access registers.
1141  **/
1142 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1143                                          u8 *data)
1144 {
1145         s32 ret_val;
1146         u16 word = 0;
1147
1148         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1149         if (ret_val)
1150                 return ret_val;
1151
1152         *data = (u8)word;
1153
1154         return 0;
1155 }
1156
1157 /**
1158  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1159  *  @hw: pointer to the HW structure
1160  *  @offset: The offset (in bytes) of the byte or word to read.
1161  *  @size: Size of data to read, 1=byte 2=word
1162  *  @data: Pointer to the word to store the value read.
1163  *
1164  *  Reads a byte or word from the NVM using the flash access registers.
1165  **/
1166 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1167                                          u8 size, u16 *data)
1168 {
1169         union ich8_hws_flash_status hsfsts;
1170         union ich8_hws_flash_ctrl hsflctl;
1171         u32 flash_linear_addr;
1172         u32 flash_data = 0;
1173         s32 ret_val = -E1000_ERR_NVM;
1174         u8 count = 0;
1175
1176         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1177                 return -E1000_ERR_NVM;
1178
1179         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1180                             hw->nvm.flash_base_addr;
1181
1182         do {
1183                 udelay(1);
1184                 /* Steps */
1185                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1186                 if (ret_val != 0)
1187                         break;
1188
1189                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1190                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1191                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1192                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1193                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1194
1195                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1196
1197                 ret_val = e1000_flash_cycle_ich8lan(hw,
1198                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1199
1200                 /*
1201                  * Check if FCERR is set to 1, if set to 1, clear it
1202                  * and try the whole sequence a few more times, else
1203                  * read in (shift in) the Flash Data0, the order is
1204                  * least significant byte first msb to lsb
1205                  */
1206                 if (ret_val == 0) {
1207                         flash_data = er32flash(ICH_FLASH_FDATA0);
1208                         if (size == 1) {
1209                                 *data = (u8)(flash_data & 0x000000FF);
1210                         } else if (size == 2) {
1211                                 *data = (u16)(flash_data & 0x0000FFFF);
1212                         }
1213                         break;
1214                 } else {
1215                         /*
1216                          * If we've gotten here, then things are probably
1217                          * completely hosed, but if the error condition is
1218                          * detected, it won't hurt to give it another try...
1219                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1220                          */
1221                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1222                         if (hsfsts.hsf_status.flcerr == 1) {
1223                                 /* Repeat for some time before giving up. */
1224                                 continue;
1225                         } else if (hsfsts.hsf_status.flcdone == 0) {
1226                                 hw_dbg(hw, "Timeout error - flash cycle "
1227                                          "did not complete.");
1228                                 break;
1229                         }
1230                 }
1231         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1232
1233         return ret_val;
1234 }
1235
1236 /**
1237  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1238  *  @hw: pointer to the HW structure
1239  *  @offset: The offset (in bytes) of the word(s) to write.
1240  *  @words: Size of data to write in words
1241  *  @data: Pointer to the word(s) to write at offset.
1242  *
1243  *  Writes a byte or word to the NVM using the flash access registers.
1244  **/
1245 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1246                                    u16 *data)
1247 {
1248         struct e1000_nvm_info *nvm = &hw->nvm;
1249         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1250         s32 ret_val;
1251         u16 i;
1252
1253         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1254             (words == 0)) {
1255                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1256                 return -E1000_ERR_NVM;
1257         }
1258
1259         ret_val = e1000_acquire_swflag_ich8lan(hw);
1260         if (ret_val)
1261                 return ret_val;
1262
1263         for (i = 0; i < words; i++) {
1264                 dev_spec->shadow_ram[offset+i].modified = 1;
1265                 dev_spec->shadow_ram[offset+i].value = data[i];
1266         }
1267
1268         e1000_release_swflag_ich8lan(hw);
1269
1270         return 0;
1271 }
1272
1273 /**
1274  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1275  *  @hw: pointer to the HW structure
1276  *
1277  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1278  *  which writes the checksum to the shadow ram.  The changes in the shadow
1279  *  ram are then committed to the EEPROM by processing each bank at a time
1280  *  checking for the modified bit and writing only the pending changes.
1281  *  After a successful commit, the shadow ram is cleared and is ready for
1282  *  future writes.
1283  **/
1284 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1285 {
1286         struct e1000_nvm_info *nvm = &hw->nvm;
1287         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1288         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1289         s32 ret_val;
1290         u16 data;
1291
1292         ret_val = e1000e_update_nvm_checksum_generic(hw);
1293         if (ret_val)
1294                 return ret_val;
1295
1296         if (nvm->type != e1000_nvm_flash_sw)
1297                 return ret_val;
1298
1299         ret_val = e1000_acquire_swflag_ich8lan(hw);
1300         if (ret_val)
1301                 return ret_val;
1302
1303         /*
1304          * We're writing to the opposite bank so if we're on bank 1,
1305          * write to bank 0 etc.  We also need to erase the segment that
1306          * is going to be written
1307          */
1308         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1309         if (ret_val)
1310                 return ret_val;
1311
1312         if (bank == 0) {
1313                 new_bank_offset = nvm->flash_bank_size;
1314                 old_bank_offset = 0;
1315                 e1000_erase_flash_bank_ich8lan(hw, 1);
1316         } else {
1317                 old_bank_offset = nvm->flash_bank_size;
1318                 new_bank_offset = 0;
1319                 e1000_erase_flash_bank_ich8lan(hw, 0);
1320         }
1321
1322         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1323                 /*
1324                  * Determine whether to write the value stored
1325                  * in the other NVM bank or a modified value stored
1326                  * in the shadow RAM
1327                  */
1328                 if (dev_spec->shadow_ram[i].modified) {
1329                         data = dev_spec->shadow_ram[i].value;
1330                 } else {
1331                         e1000_read_flash_word_ich8lan(hw,
1332                                                       i + old_bank_offset,
1333                                                       &data);
1334                 }
1335
1336                 /*
1337                  * If the word is 0x13, then make sure the signature bits
1338                  * (15:14) are 11b until the commit has completed.
1339                  * This will allow us to write 10b which indicates the
1340                  * signature is valid.  We want to do this after the write
1341                  * has completed so that we don't mark the segment valid
1342                  * while the write is still in progress
1343                  */
1344                 if (i == E1000_ICH_NVM_SIG_WORD)
1345                         data |= E1000_ICH_NVM_SIG_MASK;
1346
1347                 /* Convert offset to bytes. */
1348                 act_offset = (i + new_bank_offset) << 1;
1349
1350                 udelay(100);
1351                 /* Write the bytes to the new bank. */
1352                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1353                                                                act_offset,
1354                                                                (u8)data);
1355                 if (ret_val)
1356                         break;
1357
1358                 udelay(100);
1359                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1360                                                           act_offset + 1,
1361                                                           (u8)(data >> 8));
1362                 if (ret_val)
1363                         break;
1364         }
1365
1366         /*
1367          * Don't bother writing the segment valid bits if sector
1368          * programming failed.
1369          */
1370         if (ret_val) {
1371                 hw_dbg(hw, "Flash commit failed.\n");
1372                 e1000_release_swflag_ich8lan(hw);
1373                 return ret_val;
1374         }
1375
1376         /*
1377          * Finally validate the new segment by setting bit 15:14
1378          * to 10b in word 0x13 , this can be done without an
1379          * erase as well since these bits are 11 to start with
1380          * and we need to change bit 14 to 0b
1381          */
1382         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1383         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1384         data &= 0xBFFF;
1385         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1386                                                        act_offset * 2 + 1,
1387                                                        (u8)(data >> 8));
1388         if (ret_val) {
1389                 e1000_release_swflag_ich8lan(hw);
1390                 return ret_val;
1391         }
1392
1393         /*
1394          * And invalidate the previously valid segment by setting
1395          * its signature word (0x13) high_byte to 0b. This can be
1396          * done without an erase because flash erase sets all bits
1397          * to 1's. We can write 1's to 0's without an erase
1398          */
1399         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1400         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1401         if (ret_val) {
1402                 e1000_release_swflag_ich8lan(hw);
1403                 return ret_val;
1404         }
1405
1406         /* Great!  Everything worked, we can now clear the cached entries. */
1407         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1408                 dev_spec->shadow_ram[i].modified = 0;
1409                 dev_spec->shadow_ram[i].value = 0xFFFF;
1410         }
1411
1412         e1000_release_swflag_ich8lan(hw);
1413
1414         /*
1415          * Reload the EEPROM, or else modifications will not appear
1416          * until after the next adapter reset.
1417          */
1418         e1000e_reload_nvm(hw);
1419         msleep(10);
1420
1421         return ret_val;
1422 }
1423
1424 /**
1425  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1426  *  @hw: pointer to the HW structure
1427  *
1428  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1429  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1430  *  calculated, in which case we need to calculate the checksum and set bit 6.
1431  **/
1432 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1433 {
1434         s32 ret_val;
1435         u16 data;
1436
1437         /*
1438          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1439          * needs to be fixed.  This bit is an indication that the NVM
1440          * was prepared by OEM software and did not calculate the
1441          * checksum...a likely scenario.
1442          */
1443         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1444         if (ret_val)
1445                 return ret_val;
1446
1447         if ((data & 0x40) == 0) {
1448                 data |= 0x40;
1449                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1450                 if (ret_val)
1451                         return ret_val;
1452                 ret_val = e1000e_update_nvm_checksum(hw);
1453                 if (ret_val)
1454                         return ret_val;
1455         }
1456
1457         return e1000e_validate_nvm_checksum_generic(hw);
1458 }
1459
1460 /**
1461  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1462  *  @hw: pointer to the HW structure
1463  *  @offset: The offset (in bytes) of the byte/word to read.
1464  *  @size: Size of data to read, 1=byte 2=word
1465  *  @data: The byte(s) to write to the NVM.
1466  *
1467  *  Writes one/two bytes to the NVM using the flash access registers.
1468  **/
1469 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1470                                           u8 size, u16 data)
1471 {
1472         union ich8_hws_flash_status hsfsts;
1473         union ich8_hws_flash_ctrl hsflctl;
1474         u32 flash_linear_addr;
1475         u32 flash_data = 0;
1476         s32 ret_val;
1477         u8 count = 0;
1478
1479         if (size < 1 || size > 2 || data > size * 0xff ||
1480             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1481                 return -E1000_ERR_NVM;
1482
1483         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1484                             hw->nvm.flash_base_addr;
1485
1486         do {
1487                 udelay(1);
1488                 /* Steps */
1489                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1490                 if (ret_val)
1491                         break;
1492
1493                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1494                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1495                 hsflctl.hsf_ctrl.fldbcount = size -1;
1496                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1497                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1498
1499                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1500
1501                 if (size == 1)
1502                         flash_data = (u32)data & 0x00FF;
1503                 else
1504                         flash_data = (u32)data;
1505
1506                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1507
1508                 /*
1509                  * check if FCERR is set to 1 , if set to 1, clear it
1510                  * and try the whole sequence a few more times else done
1511                  */
1512                 ret_val = e1000_flash_cycle_ich8lan(hw,
1513                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1514                 if (!ret_val)
1515                         break;
1516
1517                 /*
1518                  * If we're here, then things are most likely
1519                  * completely hosed, but if the error condition
1520                  * is detected, it won't hurt to give it another
1521                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1522                  */
1523                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1524                 if (hsfsts.hsf_status.flcerr == 1)
1525                         /* Repeat for some time before giving up. */
1526                         continue;
1527                 if (hsfsts.hsf_status.flcdone == 0) {
1528                         hw_dbg(hw, "Timeout error - flash cycle "
1529                                  "did not complete.");
1530                         break;
1531                 }
1532         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1533
1534         return ret_val;
1535 }
1536
1537 /**
1538  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1539  *  @hw: pointer to the HW structure
1540  *  @offset: The index of the byte to read.
1541  *  @data: The byte to write to the NVM.
1542  *
1543  *  Writes a single byte to the NVM using the flash access registers.
1544  **/
1545 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1546                                           u8 data)
1547 {
1548         u16 word = (u16)data;
1549
1550         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1551 }
1552
1553 /**
1554  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1555  *  @hw: pointer to the HW structure
1556  *  @offset: The offset of the byte to write.
1557  *  @byte: The byte to write to the NVM.
1558  *
1559  *  Writes a single byte to the NVM using the flash access registers.
1560  *  Goes through a retry algorithm before giving up.
1561  **/
1562 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1563                                                 u32 offset, u8 byte)
1564 {
1565         s32 ret_val;
1566         u16 program_retries;
1567
1568         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1569         if (!ret_val)
1570                 return ret_val;
1571
1572         for (program_retries = 0; program_retries < 100; program_retries++) {
1573                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1574                 udelay(100);
1575                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1576                 if (!ret_val)
1577                         break;
1578         }
1579         if (program_retries == 100)
1580                 return -E1000_ERR_NVM;
1581
1582         return 0;
1583 }
1584
1585 /**
1586  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1587  *  @hw: pointer to the HW structure
1588  *  @bank: 0 for first bank, 1 for second bank, etc.
1589  *
1590  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1591  *  bank N is 4096 * N + flash_reg_addr.
1592  **/
1593 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1594 {
1595         struct e1000_nvm_info *nvm = &hw->nvm;
1596         union ich8_hws_flash_status hsfsts;
1597         union ich8_hws_flash_ctrl hsflctl;
1598         u32 flash_linear_addr;
1599         /* bank size is in 16bit words - adjust to bytes */
1600         u32 flash_bank_size = nvm->flash_bank_size * 2;
1601         s32 ret_val;
1602         s32 count = 0;
1603         s32 iteration;
1604         s32 sector_size;
1605         s32 j;
1606
1607         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1608
1609         /*
1610          * Determine HW Sector size: Read BERASE bits of hw flash status
1611          * register
1612          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1613          *     consecutive sectors.  The start index for the nth Hw sector
1614          *     can be calculated as = bank * 4096 + n * 256
1615          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1616          *     The start index for the nth Hw sector can be calculated
1617          *     as = bank * 4096
1618          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1619          *     (ich9 only, otherwise error condition)
1620          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1621          */
1622         switch (hsfsts.hsf_status.berasesz) {
1623         case 0:
1624                 /* Hw sector size 256 */
1625                 sector_size = ICH_FLASH_SEG_SIZE_256;
1626                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1627                 break;
1628         case 1:
1629                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1630                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1631                 break;
1632         case 2:
1633                 if (hw->mac.type == e1000_ich9lan) {
1634                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1635                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1636                 } else {
1637                         return -E1000_ERR_NVM;
1638                 }
1639                 break;
1640         case 3:
1641                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1642                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1643                 break;
1644         default:
1645                 return -E1000_ERR_NVM;
1646         }
1647
1648         /* Start with the base address, then add the sector offset. */
1649         flash_linear_addr = hw->nvm.flash_base_addr;
1650         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1651
1652         for (j = 0; j < iteration ; j++) {
1653                 do {
1654                         /* Steps */
1655                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1656                         if (ret_val)
1657                                 return ret_val;
1658
1659                         /*
1660                          * Write a value 11 (block Erase) in Flash
1661                          * Cycle field in hw flash control
1662                          */
1663                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1664                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1665                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1666
1667                         /*
1668                          * Write the last 24 bits of an index within the
1669                          * block into Flash Linear address field in Flash
1670                          * Address.
1671                          */
1672                         flash_linear_addr += (j * sector_size);
1673                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1674
1675                         ret_val = e1000_flash_cycle_ich8lan(hw,
1676                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1677                         if (ret_val == 0)
1678                                 break;
1679
1680                         /*
1681                          * Check if FCERR is set to 1.  If 1,
1682                          * clear it and try the whole sequence
1683                          * a few more times else Done
1684                          */
1685                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1686                         if (hsfsts.hsf_status.flcerr == 1)
1687                                 /* repeat for some time before giving up */
1688                                 continue;
1689                         else if (hsfsts.hsf_status.flcdone == 0)
1690                                 return ret_val;
1691                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1692         }
1693
1694         return 0;
1695 }
1696
1697 /**
1698  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1699  *  @hw: pointer to the HW structure
1700  *  @data: Pointer to the LED settings
1701  *
1702  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1703  *  settings is all 0's or F's, set the LED default to a valid LED default
1704  *  setting.
1705  **/
1706 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1707 {
1708         s32 ret_val;
1709
1710         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1711         if (ret_val) {
1712                 hw_dbg(hw, "NVM Read Error\n");
1713                 return ret_val;
1714         }
1715
1716         if (*data == ID_LED_RESERVED_0000 ||
1717             *data == ID_LED_RESERVED_FFFF)
1718                 *data = ID_LED_DEFAULT_ICH8LAN;
1719
1720         return 0;
1721 }
1722
1723 /**
1724  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1725  *  @hw: pointer to the HW structure
1726  *
1727  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1728  *  register, so the the bus width is hard coded.
1729  **/
1730 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1731 {
1732         struct e1000_bus_info *bus = &hw->bus;
1733         s32 ret_val;
1734
1735         ret_val = e1000e_get_bus_info_pcie(hw);
1736
1737         /*
1738          * ICH devices are "PCI Express"-ish.  They have
1739          * a configuration space, but do not contain
1740          * PCI Express Capability registers, so bus width
1741          * must be hardcoded.
1742          */
1743         if (bus->width == e1000_bus_width_unknown)
1744                 bus->width = e1000_bus_width_pcie_x1;
1745
1746         return ret_val;
1747 }
1748
1749 /**
1750  *  e1000_reset_hw_ich8lan - Reset the hardware
1751  *  @hw: pointer to the HW structure
1752  *
1753  *  Does a full reset of the hardware which includes a reset of the PHY and
1754  *  MAC.
1755  **/
1756 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1757 {
1758         u32 ctrl, icr, kab;
1759         s32 ret_val;
1760
1761         /*
1762          * Prevent the PCI-E bus from sticking if there is no TLP connection
1763          * on the last TLP read/write transaction when MAC is reset.
1764          */
1765         ret_val = e1000e_disable_pcie_master(hw);
1766         if (ret_val) {
1767                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1768         }
1769
1770         hw_dbg(hw, "Masking off all interrupts\n");
1771         ew32(IMC, 0xffffffff);
1772
1773         /*
1774          * Disable the Transmit and Receive units.  Then delay to allow
1775          * any pending transactions to complete before we hit the MAC
1776          * with the global reset.
1777          */
1778         ew32(RCTL, 0);
1779         ew32(TCTL, E1000_TCTL_PSP);
1780         e1e_flush();
1781
1782         msleep(10);
1783
1784         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1785         if (hw->mac.type == e1000_ich8lan) {
1786                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1787                 ew32(PBA, E1000_PBA_8K);
1788                 /* Set Packet Buffer Size to 16k. */
1789                 ew32(PBS, E1000_PBS_16K);
1790         }
1791
1792         ctrl = er32(CTRL);
1793
1794         if (!e1000_check_reset_block(hw)) {
1795                 /*
1796                  * PHY HW reset requires MAC CORE reset at the same
1797                  * time to make sure the interface between MAC and the
1798                  * external PHY is reset.
1799                  */
1800                 ctrl |= E1000_CTRL_PHY_RST;
1801         }
1802         ret_val = e1000_acquire_swflag_ich8lan(hw);
1803         hw_dbg(hw, "Issuing a global reset to ich8lan");
1804         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1805         msleep(20);
1806
1807         ret_val = e1000e_get_auto_rd_done(hw);
1808         if (ret_val) {
1809                 /*
1810                  * When auto config read does not complete, do not
1811                  * return with an error. This can happen in situations
1812                  * where there is no eeprom and prevents getting link.
1813                  */
1814                 hw_dbg(hw, "Auto Read Done did not complete\n");
1815         }
1816
1817         ew32(IMC, 0xffffffff);
1818         icr = er32(ICR);
1819
1820         kab = er32(KABGTXD);
1821         kab |= E1000_KABGTXD_BGSQLBIAS;
1822         ew32(KABGTXD, kab);
1823
1824         return ret_val;
1825 }
1826
1827 /**
1828  *  e1000_init_hw_ich8lan - Initialize the hardware
1829  *  @hw: pointer to the HW structure
1830  *
1831  *  Prepares the hardware for transmit and receive by doing the following:
1832  *   - initialize hardware bits
1833  *   - initialize LED identification
1834  *   - setup receive address registers
1835  *   - setup flow control
1836  *   - setup transmit descriptors
1837  *   - clear statistics
1838  **/
1839 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1840 {
1841         struct e1000_mac_info *mac = &hw->mac;
1842         u32 ctrl_ext, txdctl, snoop;
1843         s32 ret_val;
1844         u16 i;
1845
1846         e1000_initialize_hw_bits_ich8lan(hw);
1847
1848         /* Initialize identification LED */
1849         ret_val = e1000e_id_led_init(hw);
1850         if (ret_val) {
1851                 hw_dbg(hw, "Error initializing identification LED\n");
1852                 return ret_val;
1853         }
1854
1855         /* Setup the receive address. */
1856         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1857
1858         /* Zero out the Multicast HASH table */
1859         hw_dbg(hw, "Zeroing the MTA\n");
1860         for (i = 0; i < mac->mta_reg_count; i++)
1861                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1862
1863         /* Setup link and flow control */
1864         ret_val = e1000_setup_link_ich8lan(hw);
1865
1866         /* Set the transmit descriptor write-back policy for both queues */
1867         txdctl = er32(TXDCTL(0));
1868         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1869                  E1000_TXDCTL_FULL_TX_DESC_WB;
1870         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1871                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1872         ew32(TXDCTL(0), txdctl);
1873         txdctl = er32(TXDCTL(1));
1874         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1875                  E1000_TXDCTL_FULL_TX_DESC_WB;
1876         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1877                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1878         ew32(TXDCTL(1), txdctl);
1879
1880         /*
1881          * ICH8 has opposite polarity of no_snoop bits.
1882          * By default, we should use snoop behavior.
1883          */
1884         if (mac->type == e1000_ich8lan)
1885                 snoop = PCIE_ICH8_SNOOP_ALL;
1886         else
1887                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1888         e1000e_set_pcie_no_snoop(hw, snoop);
1889
1890         ctrl_ext = er32(CTRL_EXT);
1891         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1892         ew32(CTRL_EXT, ctrl_ext);
1893
1894         /*
1895          * Clear all of the statistics registers (clear on read).  It is
1896          * important that we do this after we have tried to establish link
1897          * because the symbol error count will increment wildly if there
1898          * is no link.
1899          */
1900         e1000_clear_hw_cntrs_ich8lan(hw);
1901
1902         return 0;
1903 }
1904 /**
1905  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1906  *  @hw: pointer to the HW structure
1907  *
1908  *  Sets/Clears required hardware bits necessary for correctly setting up the
1909  *  hardware for transmit and receive.
1910  **/
1911 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1912 {
1913         u32 reg;
1914
1915         /* Extended Device Control */
1916         reg = er32(CTRL_EXT);
1917         reg |= (1 << 22);
1918         ew32(CTRL_EXT, reg);
1919
1920         /* Transmit Descriptor Control 0 */
1921         reg = er32(TXDCTL(0));
1922         reg |= (1 << 22);
1923         ew32(TXDCTL(0), reg);
1924
1925         /* Transmit Descriptor Control 1 */
1926         reg = er32(TXDCTL(1));
1927         reg |= (1 << 22);
1928         ew32(TXDCTL(1), reg);
1929
1930         /* Transmit Arbitration Control 0 */
1931         reg = er32(TARC(0));
1932         if (hw->mac.type == e1000_ich8lan)
1933                 reg |= (1 << 28) | (1 << 29);
1934         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
1935         ew32(TARC(0), reg);
1936
1937         /* Transmit Arbitration Control 1 */
1938         reg = er32(TARC(1));
1939         if (er32(TCTL) & E1000_TCTL_MULR)
1940                 reg &= ~(1 << 28);
1941         else
1942                 reg |= (1 << 28);
1943         reg |= (1 << 24) | (1 << 26) | (1 << 30);
1944         ew32(TARC(1), reg);
1945
1946         /* Device Status */
1947         if (hw->mac.type == e1000_ich8lan) {
1948                 reg = er32(STATUS);
1949                 reg &= ~(1 << 31);
1950                 ew32(STATUS, reg);
1951         }
1952 }
1953
1954 /**
1955  *  e1000_setup_link_ich8lan - Setup flow control and link settings
1956  *  @hw: pointer to the HW structure
1957  *
1958  *  Determines which flow control settings to use, then configures flow
1959  *  control.  Calls the appropriate media-specific link configuration
1960  *  function.  Assuming the adapter has a valid link partner, a valid link
1961  *  should be established.  Assumes the hardware has previously been reset
1962  *  and the transmitter and receiver are not enabled.
1963  **/
1964 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
1965 {
1966         s32 ret_val;
1967
1968         if (e1000_check_reset_block(hw))
1969                 return 0;
1970
1971         /*
1972          * ICH parts do not have a word in the NVM to determine
1973          * the default flow control setting, so we explicitly
1974          * set it to full.
1975          */
1976         if (hw->fc.type == e1000_fc_default)
1977                 hw->fc.type = e1000_fc_full;
1978
1979         hw->fc.original_type = hw->fc.type;
1980
1981         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
1982
1983         /* Continue to configure the copper link. */
1984         ret_val = e1000_setup_copper_link_ich8lan(hw);
1985         if (ret_val)
1986                 return ret_val;
1987
1988         ew32(FCTTV, hw->fc.pause_time);
1989
1990         return e1000e_set_fc_watermarks(hw);
1991 }
1992
1993 /**
1994  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
1995  *  @hw: pointer to the HW structure
1996  *
1997  *  Configures the kumeran interface to the PHY to wait the appropriate time
1998  *  when polling the PHY, then call the generic setup_copper_link to finish
1999  *  configuring the copper link.
2000  **/
2001 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2002 {
2003         u32 ctrl;
2004         s32 ret_val;
2005         u16 reg_data;
2006
2007         ctrl = er32(CTRL);
2008         ctrl |= E1000_CTRL_SLU;
2009         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2010         ew32(CTRL, ctrl);
2011
2012         /*
2013          * Set the mac to wait the maximum time between each iteration
2014          * and increase the max iterations when polling the phy;
2015          * this fixes erroneous timeouts at 10Mbps.
2016          */
2017         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2018         if (ret_val)
2019                 return ret_val;
2020         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2021         if (ret_val)
2022                 return ret_val;
2023         reg_data |= 0x3F;
2024         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2025         if (ret_val)
2026                 return ret_val;
2027
2028         if (hw->phy.type == e1000_phy_igp_3) {
2029                 ret_val = e1000e_copper_link_setup_igp(hw);
2030                 if (ret_val)
2031                         return ret_val;
2032         } else if (hw->phy.type == e1000_phy_bm) {
2033                 ret_val = e1000e_copper_link_setup_m88(hw);
2034                 if (ret_val)
2035                         return ret_val;
2036         }
2037
2038         if (hw->phy.type == e1000_phy_ife) {
2039                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2040                 if (ret_val)
2041                         return ret_val;
2042
2043                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2044
2045                 switch (hw->phy.mdix) {
2046                 case 1:
2047                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2048                         break;
2049                 case 2:
2050                         reg_data |= IFE_PMC_FORCE_MDIX;
2051                         break;
2052                 case 0:
2053                 default:
2054                         reg_data |= IFE_PMC_AUTO_MDIX;
2055                         break;
2056                 }
2057                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2058                 if (ret_val)
2059                         return ret_val;
2060         }
2061         return e1000e_setup_copper_link(hw);
2062 }
2063
2064 /**
2065  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2066  *  @hw: pointer to the HW structure
2067  *  @speed: pointer to store current link speed
2068  *  @duplex: pointer to store the current link duplex
2069  *
2070  *  Calls the generic get_speed_and_duplex to retrieve the current link
2071  *  information and then calls the Kumeran lock loss workaround for links at
2072  *  gigabit speeds.
2073  **/
2074 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2075                                           u16 *duplex)
2076 {
2077         s32 ret_val;
2078
2079         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2080         if (ret_val)
2081                 return ret_val;
2082
2083         if ((hw->mac.type == e1000_ich8lan) &&
2084             (hw->phy.type == e1000_phy_igp_3) &&
2085             (*speed == SPEED_1000)) {
2086                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2087         }
2088
2089         return ret_val;
2090 }
2091
2092 /**
2093  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2094  *  @hw: pointer to the HW structure
2095  *
2096  *  Work-around for 82566 Kumeran PCS lock loss:
2097  *  On link status change (i.e. PCI reset, speed change) and link is up and
2098  *  speed is gigabit-
2099  *    0) if workaround is optionally disabled do nothing
2100  *    1) wait 1ms for Kumeran link to come up
2101  *    2) check Kumeran Diagnostic register PCS lock loss bit
2102  *    3) if not set the link is locked (all is good), otherwise...
2103  *    4) reset the PHY
2104  *    5) repeat up to 10 times
2105  *  Note: this is only called for IGP3 copper when speed is 1gb.
2106  **/
2107 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2108 {
2109         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2110         u32 phy_ctrl;
2111         s32 ret_val;
2112         u16 i, data;
2113         bool link;
2114
2115         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2116                 return 0;
2117
2118         /*
2119          * Make sure link is up before proceeding.  If not just return.
2120          * Attempting this while link is negotiating fouled up link
2121          * stability
2122          */
2123         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2124         if (!link)
2125                 return 0;
2126
2127         for (i = 0; i < 10; i++) {
2128                 /* read once to clear */
2129                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2130                 if (ret_val)
2131                         return ret_val;
2132                 /* and again to get new status */
2133                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2134                 if (ret_val)
2135                         return ret_val;
2136
2137                 /* check for PCS lock */
2138                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2139                         return 0;
2140
2141                 /* Issue PHY reset */
2142                 e1000_phy_hw_reset(hw);
2143                 mdelay(5);
2144         }
2145         /* Disable GigE link negotiation */
2146         phy_ctrl = er32(PHY_CTRL);
2147         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2148                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2149         ew32(PHY_CTRL, phy_ctrl);
2150
2151         /*
2152          * Call gig speed drop workaround on Gig disable before accessing
2153          * any PHY registers
2154          */
2155         e1000e_gig_downshift_workaround_ich8lan(hw);
2156
2157         /* unable to acquire PCS lock */
2158         return -E1000_ERR_PHY;
2159 }
2160
2161 /**
2162  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2163  *  @hw: pointer to the HW structure
2164  *  @state: boolean value used to set the current Kumeran workaround state
2165  *
2166  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2167  *  /disabled - FALSE).
2168  **/
2169 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2170                                                  bool state)
2171 {
2172         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2173
2174         if (hw->mac.type != e1000_ich8lan) {
2175                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2176                 return;
2177         }
2178
2179         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2180 }
2181
2182 /**
2183  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2184  *  @hw: pointer to the HW structure
2185  *
2186  *  Workaround for 82566 power-down on D3 entry:
2187  *    1) disable gigabit link
2188  *    2) write VR power-down enable
2189  *    3) read it back
2190  *  Continue if successful, else issue LCD reset and repeat
2191  **/
2192 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2193 {
2194         u32 reg;
2195         u16 data;
2196         u8  retry = 0;
2197
2198         if (hw->phy.type != e1000_phy_igp_3)
2199                 return;
2200
2201         /* Try the workaround twice (if needed) */
2202         do {
2203                 /* Disable link */
2204                 reg = er32(PHY_CTRL);
2205                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2206                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2207                 ew32(PHY_CTRL, reg);
2208
2209                 /*
2210                  * Call gig speed drop workaround on Gig disable before
2211                  * accessing any PHY registers
2212                  */
2213                 if (hw->mac.type == e1000_ich8lan)
2214                         e1000e_gig_downshift_workaround_ich8lan(hw);
2215
2216                 /* Write VR power-down enable */
2217                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2218                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2219                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2220
2221                 /* Read it back and test */
2222                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2223                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2224                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2225                         break;
2226
2227                 /* Issue PHY reset and repeat at most one more time */
2228                 reg = er32(CTRL);
2229                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2230                 retry++;
2231         } while (retry);
2232 }
2233
2234 /**
2235  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2236  *  @hw: pointer to the HW structure
2237  *
2238  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2239  *  LPLU, Gig disable, MDIC PHY reset):
2240  *    1) Set Kumeran Near-end loopback
2241  *    2) Clear Kumeran Near-end loopback
2242  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2243  **/
2244 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2245 {
2246         s32 ret_val;
2247         u16 reg_data;
2248
2249         if ((hw->mac.type != e1000_ich8lan) ||
2250             (hw->phy.type != e1000_phy_igp_3))
2251                 return;
2252
2253         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2254                                       &reg_data);
2255         if (ret_val)
2256                 return;
2257         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2258         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2259                                        reg_data);
2260         if (ret_val)
2261                 return;
2262         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2263         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2264                                        reg_data);
2265 }
2266
2267 /**
2268  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2269  *  @hw: pointer to the HW structure
2270  *
2271  *  During S0 to Sx transition, it is possible the link remains at gig
2272  *  instead of negotiating to a lower speed.  Before going to Sx, set
2273  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2274  *  to a lower speed.
2275  *
2276  *  Should only be called for ICH9 and ICH10 devices.
2277  **/
2278 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2279 {
2280         u32 phy_ctrl;
2281
2282         if ((hw->mac.type == e1000_ich10lan) ||
2283             (hw->mac.type == e1000_ich9lan)) {
2284                 phy_ctrl = er32(PHY_CTRL);
2285                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2286                             E1000_PHY_CTRL_GBE_DISABLE;
2287                 ew32(PHY_CTRL, phy_ctrl);
2288         }
2289
2290         return;
2291 }
2292
2293 /**
2294  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2295  *  @hw: pointer to the HW structure
2296  *
2297  *  Return the LED back to the default configuration.
2298  **/
2299 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2300 {
2301         if (hw->phy.type == e1000_phy_ife)
2302                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2303
2304         ew32(LEDCTL, hw->mac.ledctl_default);
2305         return 0;
2306 }
2307
2308 /**
2309  *  e1000_led_on_ich8lan - Turn LEDs on
2310  *  @hw: pointer to the HW structure
2311  *
2312  *  Turn on the LEDs.
2313  **/
2314 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2315 {
2316         if (hw->phy.type == e1000_phy_ife)
2317                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2318                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2319
2320         ew32(LEDCTL, hw->mac.ledctl_mode2);
2321         return 0;
2322 }
2323
2324 /**
2325  *  e1000_led_off_ich8lan - Turn LEDs off
2326  *  @hw: pointer to the HW structure
2327  *
2328  *  Turn off the LEDs.
2329  **/
2330 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2331 {
2332         if (hw->phy.type == e1000_phy_ife)
2333                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2334                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2335
2336         ew32(LEDCTL, hw->mac.ledctl_mode1);
2337         return 0;
2338 }
2339
2340 /**
2341  *  e1000_get_cfg_done_ich8lan - Read config done bit
2342  *  @hw: pointer to the HW structure
2343  *
2344  *  Read the management control register for the config done bit for
2345  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2346  *  to read the config done bit, so an error is *ONLY* logged and returns
2347  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2348  *  would not be able to be reset or change link.
2349  **/
2350 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2351 {
2352         u32 bank = 0;
2353
2354         e1000e_get_cfg_done(hw);
2355
2356         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2357         if (hw->mac.type != e1000_ich10lan) {
2358                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2359                     (hw->phy.type == e1000_phy_igp_3)) {
2360                         e1000e_phy_init_script_igp3(hw);
2361                 }
2362         } else {
2363                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2364                         /* Maybe we should do a basic PHY config */
2365                         hw_dbg(hw, "EEPROM not present\n");
2366                         return -E1000_ERR_CONFIG;
2367                 }
2368         }
2369
2370         return 0;
2371 }
2372
2373 /**
2374  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2375  *  @hw: pointer to the HW structure
2376  *
2377  *  Clears hardware counters specific to the silicon family and calls
2378  *  clear_hw_cntrs_generic to clear all general purpose counters.
2379  **/
2380 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2381 {
2382         u32 temp;
2383
2384         e1000e_clear_hw_cntrs_base(hw);
2385
2386         temp = er32(ALGNERRC);
2387         temp = er32(RXERRC);
2388         temp = er32(TNCRS);
2389         temp = er32(CEXTERR);
2390         temp = er32(TSCTC);
2391         temp = er32(TSCTFC);
2392
2393         temp = er32(MGTPRC);
2394         temp = er32(MGTPDC);
2395         temp = er32(MGTPTC);
2396
2397         temp = er32(IAC);
2398         temp = er32(ICRXOC);
2399
2400 }
2401
2402 static struct e1000_mac_operations ich8_mac_ops = {
2403         .mng_mode_enab          = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
2404         .check_for_link         = e1000e_check_for_copper_link,
2405         .cleanup_led            = e1000_cleanup_led_ich8lan,
2406         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2407         .get_bus_info           = e1000_get_bus_info_ich8lan,
2408         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2409         .led_on                 = e1000_led_on_ich8lan,
2410         .led_off                = e1000_led_off_ich8lan,
2411         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2412         .reset_hw               = e1000_reset_hw_ich8lan,
2413         .init_hw                = e1000_init_hw_ich8lan,
2414         .setup_link             = e1000_setup_link_ich8lan,
2415         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2416 };
2417
2418 static struct e1000_phy_operations ich8_phy_ops = {
2419         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2420         .check_reset_block      = e1000_check_reset_block_ich8lan,
2421         .commit_phy             = NULL,
2422         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2423         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2424         .get_cable_length       = e1000e_get_cable_length_igp_2,
2425         .get_phy_info           = e1000_get_phy_info_ich8lan,
2426         .read_phy_reg           = e1000e_read_phy_reg_igp,
2427         .release_phy            = e1000_release_swflag_ich8lan,
2428         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2429         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2430         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2431         .write_phy_reg          = e1000e_write_phy_reg_igp,
2432 };
2433
2434 static struct e1000_nvm_operations ich8_nvm_ops = {
2435         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2436         .read_nvm               = e1000_read_nvm_ich8lan,
2437         .release_nvm            = e1000_release_swflag_ich8lan,
2438         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2439         .valid_led_default      = e1000_valid_led_default_ich8lan,
2440         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2441         .write_nvm              = e1000_write_nvm_ich8lan,
2442 };
2443
2444 struct e1000_info e1000_ich8_info = {
2445         .mac                    = e1000_ich8lan,
2446         .flags                  = FLAG_HAS_WOL
2447                                   | FLAG_IS_ICH
2448                                   | FLAG_RX_CSUM_ENABLED
2449                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2450                                   | FLAG_HAS_AMT
2451                                   | FLAG_HAS_FLASH
2452                                   | FLAG_APME_IN_WUC,
2453         .pba                    = 8,
2454         .get_variants           = e1000_get_variants_ich8lan,
2455         .mac_ops                = &ich8_mac_ops,
2456         .phy_ops                = &ich8_phy_ops,
2457         .nvm_ops                = &ich8_nvm_ops,
2458 };
2459
2460 struct e1000_info e1000_ich9_info = {
2461         .mac                    = e1000_ich9lan,
2462         .flags                  = FLAG_HAS_JUMBO_FRAMES
2463                                   | FLAG_IS_ICH
2464                                   | FLAG_HAS_WOL
2465                                   | FLAG_RX_CSUM_ENABLED
2466                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2467                                   | FLAG_HAS_AMT
2468                                   | FLAG_HAS_ERT
2469                                   | FLAG_HAS_FLASH
2470                                   | FLAG_APME_IN_WUC,
2471         .pba                    = 10,
2472         .get_variants           = e1000_get_variants_ich8lan,
2473         .mac_ops                = &ich8_mac_ops,
2474         .phy_ops                = &ich8_phy_ops,
2475         .nvm_ops                = &ich8_nvm_ops,
2476 };
2477
2478 struct e1000_info e1000_ich10_info = {
2479         .mac                    = e1000_ich10lan,
2480         .flags                  = FLAG_HAS_JUMBO_FRAMES
2481                                   | FLAG_IS_ICH
2482                                   | FLAG_HAS_WOL
2483                                   | FLAG_RX_CSUM_ENABLED
2484                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2485                                   | FLAG_HAS_AMT
2486                                   | FLAG_HAS_ERT
2487                                   | FLAG_HAS_FLASH
2488                                   | FLAG_APME_IN_WUC,
2489         .pba                    = 10,
2490         .get_variants           = e1000_get_variants_ich8lan,
2491         .mac_ops                = &ich8_mac_ops,
2492         .phy_ops                = &ich8_phy_ops,
2493         .nvm_ops                = &ich8_nvm_ops,
2494 };