2d1415610d7719fc93b7071f919e966812581263
[linux-2.6.git] / drivers / net / e1000e / es2lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
32  */
33
34 #include "e1000.h"
35
36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
40
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
44
45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
48
49 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
50 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
51
52 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
53 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
54
55 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
56 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
57 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
58 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
59 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
60 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
61
62 /* PHY Specific Control Register 2 (Page 0, Register 26) */
63 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
64                                                 /* 1=Reverse Auto-Negotiation */
65
66 /* MAC Specific Control Register (Page 2, Register 21) */
67 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
68 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
69 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
70 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
71 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
72
73 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
74
75 /* DSP Distance Register (Page 5, Register 26) */
76 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
77                                                            1 = 50-80M
78                                                            2 = 80-110M
79                                                            3 = 110-140M
80                                                            4 = >140M */
81
82 /* Kumeran Mode Control Register (Page 193, Register 16) */
83 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
84
85 /* Max number of times Kumeran read/write should be validated */
86 #define GG82563_MAX_KMRN_RETRY  0x5
87
88 /* Power Management Control Register (Page 193, Register 20) */
89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
90                                            /* 1=Enable SERDES Electrical Idle */
91
92 /* In-Band Control Register (Page 194, Register 18) */
93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
94
95 /*
96  * A table for the GG82563 cable length where the range is defined
97  * with a lower bound at "index" and the upper bound at
98  * "index + 5".
99  */
100 static const u16 e1000_gg82563_cable_length_table[] =
101          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
102
103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
110 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
111 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
112                                             u16 *data);
113 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
114                                              u16 data);
115
116 /**
117  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
118  *  @hw: pointer to the HW structure
119  **/
120 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
121 {
122         struct e1000_phy_info *phy = &hw->phy;
123         s32 ret_val;
124
125         if (hw->phy.media_type != e1000_media_type_copper) {
126                 phy->type       = e1000_phy_none;
127                 return 0;
128         }
129
130         phy->addr               = 1;
131         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
132         phy->reset_delay_us      = 100;
133         phy->type               = e1000_phy_gg82563;
134
135         /* This can only be done after all function pointers are setup. */
136         ret_val = e1000e_get_phy_id(hw);
137
138         /* Verify phy id */
139         if (phy->id != GG82563_E_PHY_ID)
140                 return -E1000_ERR_PHY;
141
142         return ret_val;
143 }
144
145 /**
146  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
147  *  @hw: pointer to the HW structure
148  **/
149 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
150 {
151         struct e1000_nvm_info *nvm = &hw->nvm;
152         u32 eecd = er32(EECD);
153         u16 size;
154
155         nvm->opcode_bits        = 8;
156         nvm->delay_usec  = 1;
157         switch (nvm->override) {
158         case e1000_nvm_override_spi_large:
159                 nvm->page_size    = 32;
160                 nvm->address_bits = 16;
161                 break;
162         case e1000_nvm_override_spi_small:
163                 nvm->page_size    = 8;
164                 nvm->address_bits = 8;
165                 break;
166         default:
167                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
168                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
169                 break;
170         }
171
172         nvm->type = e1000_nvm_eeprom_spi;
173
174         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
175                           E1000_EECD_SIZE_EX_SHIFT);
176
177         /*
178          * Added to a constant, "size" becomes the left-shift value
179          * for setting word_size.
180          */
181         size += NVM_WORD_SIZE_BASE_SHIFT;
182
183         /* EEPROM access above 16k is unsupported */
184         if (size > 14)
185                 size = 14;
186         nvm->word_size  = 1 << size;
187
188         return 0;
189 }
190
191 /**
192  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
193  *  @hw: pointer to the HW structure
194  **/
195 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
196 {
197         struct e1000_hw *hw = &adapter->hw;
198         struct e1000_mac_info *mac = &hw->mac;
199         struct e1000_mac_operations *func = &mac->ops;
200
201         /* Set media type */
202         switch (adapter->pdev->device) {
203         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
204                 hw->phy.media_type = e1000_media_type_internal_serdes;
205                 break;
206         default:
207                 hw->phy.media_type = e1000_media_type_copper;
208                 break;
209         }
210
211         /* Set mta register count */
212         mac->mta_reg_count = 128;
213         /* Set rar entry count */
214         mac->rar_entry_count = E1000_RAR_ENTRIES;
215         /* Set if manageability features are enabled. */
216         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
217
218         /* check for link */
219         switch (hw->phy.media_type) {
220         case e1000_media_type_copper:
221                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
222                 func->check_for_link = e1000e_check_for_copper_link;
223                 break;
224         case e1000_media_type_fiber:
225                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
226                 func->check_for_link = e1000e_check_for_fiber_link;
227                 break;
228         case e1000_media_type_internal_serdes:
229                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
230                 func->check_for_link = e1000e_check_for_serdes_link;
231                 break;
232         default:
233                 return -E1000_ERR_CONFIG;
234                 break;
235         }
236
237         return 0;
238 }
239
240 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
241 {
242         struct e1000_hw *hw = &adapter->hw;
243         s32 rc;
244
245         rc = e1000_init_mac_params_80003es2lan(adapter);
246         if (rc)
247                 return rc;
248
249         rc = e1000_init_nvm_params_80003es2lan(hw);
250         if (rc)
251                 return rc;
252
253         rc = e1000_init_phy_params_80003es2lan(hw);
254         if (rc)
255                 return rc;
256
257         return 0;
258 }
259
260 /**
261  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
262  *  @hw: pointer to the HW structure
263  *
264  *  A wrapper to acquire access rights to the correct PHY.
265  **/
266 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
267 {
268         u16 mask;
269
270         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
271         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
272 }
273
274 /**
275  *  e1000_release_phy_80003es2lan - Release rights to access PHY
276  *  @hw: pointer to the HW structure
277  *
278  *  A wrapper to release access rights to the correct PHY.
279  **/
280 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
281 {
282         u16 mask;
283
284         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
285         e1000_release_swfw_sync_80003es2lan(hw, mask);
286 }
287
288 /**
289  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
290  *  @hw: pointer to the HW structure
291  *
292  *  Acquire the semaphore to access the Kumeran interface.
293  *
294  **/
295 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
296 {
297         u16 mask;
298
299         mask = E1000_SWFW_CSR_SM;
300
301         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
302 }
303
304 /**
305  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
306  *  @hw: pointer to the HW structure
307  *
308  *  Release the semaphore used to access the Kumeran interface
309  **/
310 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
311 {
312         u16 mask;
313
314         mask = E1000_SWFW_CSR_SM;
315
316         e1000_release_swfw_sync_80003es2lan(hw, mask);
317 }
318
319 /**
320  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
321  *  @hw: pointer to the HW structure
322  *
323  *  Acquire the semaphore to access the EEPROM.
324  **/
325 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
326 {
327         s32 ret_val;
328
329         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
330         if (ret_val)
331                 return ret_val;
332
333         ret_val = e1000e_acquire_nvm(hw);
334
335         if (ret_val)
336                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
337
338         return ret_val;
339 }
340
341 /**
342  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
343  *  @hw: pointer to the HW structure
344  *
345  *  Release the semaphore used to access the EEPROM.
346  **/
347 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
348 {
349         e1000e_release_nvm(hw);
350         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
351 }
352
353 /**
354  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
355  *  @hw: pointer to the HW structure
356  *  @mask: specifies which semaphore to acquire
357  *
358  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
359  *  will also specify which port we're acquiring the lock for.
360  **/
361 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
362 {
363         u32 swfw_sync;
364         u32 swmask = mask;
365         u32 fwmask = mask << 16;
366         s32 i = 0;
367         s32 timeout = 50;
368
369         while (i < timeout) {
370                 if (e1000e_get_hw_semaphore(hw))
371                         return -E1000_ERR_SWFW_SYNC;
372
373                 swfw_sync = er32(SW_FW_SYNC);
374                 if (!(swfw_sync & (fwmask | swmask)))
375                         break;
376
377                 /*
378                  * Firmware currently using resource (fwmask)
379                  * or other software thread using resource (swmask)
380                  */
381                 e1000e_put_hw_semaphore(hw);
382                 mdelay(5);
383                 i++;
384         }
385
386         if (i == timeout) {
387                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
388                 return -E1000_ERR_SWFW_SYNC;
389         }
390
391         swfw_sync |= swmask;
392         ew32(SW_FW_SYNC, swfw_sync);
393
394         e1000e_put_hw_semaphore(hw);
395
396         return 0;
397 }
398
399 /**
400  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
401  *  @hw: pointer to the HW structure
402  *  @mask: specifies which semaphore to acquire
403  *
404  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
405  *  will also specify which port we're releasing the lock for.
406  **/
407 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
408 {
409         u32 swfw_sync;
410
411         while (e1000e_get_hw_semaphore(hw) != 0);
412         /* Empty */
413
414         swfw_sync = er32(SW_FW_SYNC);
415         swfw_sync &= ~mask;
416         ew32(SW_FW_SYNC, swfw_sync);
417
418         e1000e_put_hw_semaphore(hw);
419 }
420
421 /**
422  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
423  *  @hw: pointer to the HW structure
424  *  @offset: offset of the register to read
425  *  @data: pointer to the data returned from the operation
426  *
427  *  Read the GG82563 PHY register.
428  **/
429 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
430                                                   u32 offset, u16 *data)
431 {
432         s32 ret_val;
433         u32 page_select;
434         u16 temp;
435
436         ret_val = e1000_acquire_phy_80003es2lan(hw);
437         if (ret_val)
438                 return ret_val;
439
440         /* Select Configuration Page */
441         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
442                 page_select = GG82563_PHY_PAGE_SELECT;
443         } else {
444                 /*
445                  * Use Alternative Page Select register to access
446                  * registers 30 and 31
447                  */
448                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
449         }
450
451         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
452         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
453         if (ret_val) {
454                 e1000_release_phy_80003es2lan(hw);
455                 return ret_val;
456         }
457
458         /*
459          * The "ready" bit in the MDIC register may be incorrectly set
460          * before the device has completed the "Page Select" MDI
461          * transaction.  So we wait 200us after each MDI command...
462          */
463         udelay(200);
464
465         /* ...and verify the command was successful. */
466         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
467
468         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
469                 ret_val = -E1000_ERR_PHY;
470                 e1000_release_phy_80003es2lan(hw);
471                 return ret_val;
472         }
473
474         udelay(200);
475
476         ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
477                                            data);
478
479         udelay(200);
480         e1000_release_phy_80003es2lan(hw);
481
482         return ret_val;
483 }
484
485 /**
486  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
487  *  @hw: pointer to the HW structure
488  *  @offset: offset of the register to read
489  *  @data: value to write to the register
490  *
491  *  Write to the GG82563 PHY register.
492  **/
493 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
494                                                    u32 offset, u16 data)
495 {
496         s32 ret_val;
497         u32 page_select;
498         u16 temp;
499
500         ret_val = e1000_acquire_phy_80003es2lan(hw);
501         if (ret_val)
502                 return ret_val;
503
504         /* Select Configuration Page */
505         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
506                 page_select = GG82563_PHY_PAGE_SELECT;
507         } else {
508                 /*
509                  * Use Alternative Page Select register to access
510                  * registers 30 and 31
511                  */
512                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
513         }
514
515         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
516         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
517         if (ret_val) {
518                 e1000_release_phy_80003es2lan(hw);
519                 return ret_val;
520         }
521
522
523         /*
524          * The "ready" bit in the MDIC register may be incorrectly set
525          * before the device has completed the "Page Select" MDI
526          * transaction.  So we wait 200us after each MDI command...
527          */
528         udelay(200);
529
530         /* ...and verify the command was successful. */
531         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
532
533         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
534                 e1000_release_phy_80003es2lan(hw);
535                 return -E1000_ERR_PHY;
536         }
537
538         udelay(200);
539
540         ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
541                                             data);
542
543         udelay(200);
544         e1000_release_phy_80003es2lan(hw);
545
546         return ret_val;
547 }
548
549 /**
550  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
551  *  @hw: pointer to the HW structure
552  *  @offset: offset of the register to read
553  *  @words: number of words to write
554  *  @data: buffer of data to write to the NVM
555  *
556  *  Write "words" of data to the ESB2 NVM.
557  **/
558 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
559                                        u16 words, u16 *data)
560 {
561         return e1000e_write_nvm_spi(hw, offset, words, data);
562 }
563
564 /**
565  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
566  *  @hw: pointer to the HW structure
567  *
568  *  Wait a specific amount of time for manageability processes to complete.
569  *  This is a function pointer entry point called by the phy module.
570  **/
571 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
572 {
573         s32 timeout = PHY_CFG_TIMEOUT;
574         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
575
576         if (hw->bus.func == 1)
577                 mask = E1000_NVM_CFG_DONE_PORT_1;
578
579         while (timeout) {
580                 if (er32(EEMNGCTL) & mask)
581                         break;
582                 msleep(1);
583                 timeout--;
584         }
585         if (!timeout) {
586                 e_dbg("MNG configuration cycle has not completed.\n");
587                 return -E1000_ERR_RESET;
588         }
589
590         return 0;
591 }
592
593 /**
594  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
595  *  @hw: pointer to the HW structure
596  *
597  *  Force the speed and duplex settings onto the PHY.  This is a
598  *  function pointer entry point called by the phy module.
599  **/
600 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
601 {
602         s32 ret_val;
603         u16 phy_data;
604         bool link;
605
606         /*
607          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
608          * forced whenever speed and duplex are forced.
609          */
610         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
611         if (ret_val)
612                 return ret_val;
613
614         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
615         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
616         if (ret_val)
617                 return ret_val;
618
619         e_dbg("GG82563 PSCR: %X\n", phy_data);
620
621         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
622         if (ret_val)
623                 return ret_val;
624
625         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
626
627         /* Reset the phy to commit changes. */
628         phy_data |= MII_CR_RESET;
629
630         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
631         if (ret_val)
632                 return ret_val;
633
634         udelay(1);
635
636         if (hw->phy.autoneg_wait_to_complete) {
637                 e_dbg("Waiting for forced speed/duplex link "
638                          "on GG82563 phy.\n");
639
640                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
641                                                      100000, &link);
642                 if (ret_val)
643                         return ret_val;
644
645                 if (!link) {
646                         /*
647                          * We didn't get link.
648                          * Reset the DSP and cross our fingers.
649                          */
650                         ret_val = e1000e_phy_reset_dsp(hw);
651                         if (ret_val)
652                                 return ret_val;
653                 }
654
655                 /* Try once more */
656                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
657                                                      100000, &link);
658                 if (ret_val)
659                         return ret_val;
660         }
661
662         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
663         if (ret_val)
664                 return ret_val;
665
666         /*
667          * Resetting the phy means we need to verify the TX_CLK corresponds
668          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
669          */
670         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
671         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
672                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
673         else
674                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
675
676         /*
677          * In addition, we must re-enable CRS on Tx for both half and full
678          * duplex.
679          */
680         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
681         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
682
683         return ret_val;
684 }
685
686 /**
687  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
688  *  @hw: pointer to the HW structure
689  *
690  *  Find the approximate cable length as measured by the GG82563 PHY.
691  *  This is a function pointer entry point called by the phy module.
692  **/
693 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
694 {
695         struct e1000_phy_info *phy = &hw->phy;
696         s32 ret_val;
697         u16 phy_data;
698         u16 index;
699
700         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
701         if (ret_val)
702                 return ret_val;
703
704         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
705         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
706         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
707
708         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
709
710         return 0;
711 }
712
713 /**
714  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
715  *  @hw: pointer to the HW structure
716  *  @speed: pointer to speed buffer
717  *  @duplex: pointer to duplex buffer
718  *
719  *  Retrieve the current speed and duplex configuration.
720  **/
721 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
722                                               u16 *duplex)
723 {
724         s32 ret_val;
725
726         if (hw->phy.media_type == e1000_media_type_copper) {
727                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
728                                                                     speed,
729                                                                     duplex);
730                 hw->phy.ops.cfg_on_link_up(hw);
731         } else {
732                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
733                                                                   speed,
734                                                                   duplex);
735         }
736
737         return ret_val;
738 }
739
740 /**
741  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
742  *  @hw: pointer to the HW structure
743  *
744  *  Perform a global reset to the ESB2 controller.
745  **/
746 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
747 {
748         u32 ctrl;
749         u32 icr;
750         s32 ret_val;
751
752         /*
753          * Prevent the PCI-E bus from sticking if there is no TLP connection
754          * on the last TLP read/write transaction when MAC is reset.
755          */
756         ret_val = e1000e_disable_pcie_master(hw);
757         if (ret_val)
758                 e_dbg("PCI-E Master disable polling has failed.\n");
759
760         e_dbg("Masking off all interrupts\n");
761         ew32(IMC, 0xffffffff);
762
763         ew32(RCTL, 0);
764         ew32(TCTL, E1000_TCTL_PSP);
765         e1e_flush();
766
767         msleep(10);
768
769         ctrl = er32(CTRL);
770
771         ret_val = e1000_acquire_phy_80003es2lan(hw);
772         e_dbg("Issuing a global reset to MAC\n");
773         ew32(CTRL, ctrl | E1000_CTRL_RST);
774         e1000_release_phy_80003es2lan(hw);
775
776         ret_val = e1000e_get_auto_rd_done(hw);
777         if (ret_val)
778                 /* We don't want to continue accessing MAC registers. */
779                 return ret_val;
780
781         /* Clear any pending interrupt events. */
782         ew32(IMC, 0xffffffff);
783         icr = er32(ICR);
784
785         return 0;
786 }
787
788 /**
789  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
790  *  @hw: pointer to the HW structure
791  *
792  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
793  **/
794 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
795 {
796         struct e1000_mac_info *mac = &hw->mac;
797         u32 reg_data;
798         s32 ret_val;
799         u16 i;
800
801         e1000_initialize_hw_bits_80003es2lan(hw);
802
803         /* Initialize identification LED */
804         ret_val = e1000e_id_led_init(hw);
805         if (ret_val) {
806                 e_dbg("Error initializing identification LED\n");
807                 return ret_val;
808         }
809
810         /* Disabling VLAN filtering */
811         e_dbg("Initializing the IEEE VLAN\n");
812         e1000e_clear_vfta(hw);
813
814         /* Setup the receive address. */
815         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
816
817         /* Zero out the Multicast HASH table */
818         e_dbg("Zeroing the MTA\n");
819         for (i = 0; i < mac->mta_reg_count; i++)
820                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
821
822         /* Setup link and flow control */
823         ret_val = e1000e_setup_link(hw);
824
825         /* Set the transmit descriptor write-back policy */
826         reg_data = er32(TXDCTL(0));
827         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
828                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
829         ew32(TXDCTL(0), reg_data);
830
831         /* ...for both queues. */
832         reg_data = er32(TXDCTL(1));
833         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
834                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
835         ew32(TXDCTL(1), reg_data);
836
837         /* Enable retransmit on late collisions */
838         reg_data = er32(TCTL);
839         reg_data |= E1000_TCTL_RTLC;
840         ew32(TCTL, reg_data);
841
842         /* Configure Gigabit Carry Extend Padding */
843         reg_data = er32(TCTL_EXT);
844         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
845         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
846         ew32(TCTL_EXT, reg_data);
847
848         /* Configure Transmit Inter-Packet Gap */
849         reg_data = er32(TIPG);
850         reg_data &= ~E1000_TIPG_IPGT_MASK;
851         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
852         ew32(TIPG, reg_data);
853
854         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
855         reg_data &= ~0x00100000;
856         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
857
858         /*
859          * Clear all of the statistics registers (clear on read).  It is
860          * important that we do this after we have tried to establish link
861          * because the symbol error count will increment wildly if there
862          * is no link.
863          */
864         e1000_clear_hw_cntrs_80003es2lan(hw);
865
866         return ret_val;
867 }
868
869 /**
870  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
871  *  @hw: pointer to the HW structure
872  *
873  *  Initializes required hardware-dependent bits needed for normal operation.
874  **/
875 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
876 {
877         u32 reg;
878
879         /* Transmit Descriptor Control 0 */
880         reg = er32(TXDCTL(0));
881         reg |= (1 << 22);
882         ew32(TXDCTL(0), reg);
883
884         /* Transmit Descriptor Control 1 */
885         reg = er32(TXDCTL(1));
886         reg |= (1 << 22);
887         ew32(TXDCTL(1), reg);
888
889         /* Transmit Arbitration Control 0 */
890         reg = er32(TARC(0));
891         reg &= ~(0xF << 27); /* 30:27 */
892         if (hw->phy.media_type != e1000_media_type_copper)
893                 reg &= ~(1 << 20);
894         ew32(TARC(0), reg);
895
896         /* Transmit Arbitration Control 1 */
897         reg = er32(TARC(1));
898         if (er32(TCTL) & E1000_TCTL_MULR)
899                 reg &= ~(1 << 28);
900         else
901                 reg |= (1 << 28);
902         ew32(TARC(1), reg);
903 }
904
905 /**
906  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
907  *  @hw: pointer to the HW structure
908  *
909  *  Setup some GG82563 PHY registers for obtaining link
910  **/
911 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
912 {
913         struct e1000_phy_info *phy = &hw->phy;
914         s32 ret_val;
915         u32 ctrl_ext;
916         u16 data;
917
918         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
919         if (ret_val)
920                 return ret_val;
921
922         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
923         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
924         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
925
926         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
927         if (ret_val)
928                 return ret_val;
929
930         /*
931          * Options:
932          *   MDI/MDI-X = 0 (default)
933          *   0 - Auto for all speeds
934          *   1 - MDI mode
935          *   2 - MDI-X mode
936          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
937          */
938         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
939         if (ret_val)
940                 return ret_val;
941
942         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
943
944         switch (phy->mdix) {
945         case 1:
946                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
947                 break;
948         case 2:
949                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
950                 break;
951         case 0:
952         default:
953                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
954                 break;
955         }
956
957         /*
958          * Options:
959          *   disable_polarity_correction = 0 (default)
960          *       Automatic Correction for Reversed Cable Polarity
961          *   0 - Disabled
962          *   1 - Enabled
963          */
964         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
965         if (phy->disable_polarity_correction)
966                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
967
968         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
969         if (ret_val)
970                 return ret_val;
971
972         /* SW Reset the PHY so all changes take effect */
973         ret_val = e1000e_commit_phy(hw);
974         if (ret_val) {
975                 e_dbg("Error Resetting the PHY\n");
976                 return ret_val;
977         }
978
979         /* Bypass Rx and Tx FIFO's */
980         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
981                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
982                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
983                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
984         if (ret_val)
985                 return ret_val;
986
987         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
988                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
989                                        &data);
990         if (ret_val)
991                 return ret_val;
992         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
993         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
994                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
995                                         data);
996         if (ret_val)
997                 return ret_val;
998
999         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1000         if (ret_val)
1001                 return ret_val;
1002
1003         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1004         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1005         if (ret_val)
1006                 return ret_val;
1007
1008         ctrl_ext = er32(CTRL_EXT);
1009         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1010         ew32(CTRL_EXT, ctrl_ext);
1011
1012         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1013         if (ret_val)
1014                 return ret_val;
1015
1016         /*
1017          * Do not init these registers when the HW is in IAMT mode, since the
1018          * firmware will have already initialized them.  We only initialize
1019          * them if the HW is not in IAMT mode.
1020          */
1021         if (!e1000e_check_mng_mode(hw)) {
1022                 /* Enable Electrical Idle on the PHY */
1023                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1024                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1025                 if (ret_val)
1026                         return ret_val;
1027
1028                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1029                 if (ret_val)
1030                         return ret_val;
1031
1032                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1033                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1034                 if (ret_val)
1035                         return ret_val;
1036         }
1037
1038         /*
1039          * Workaround: Disable padding in Kumeran interface in the MAC
1040          * and in the PHY to avoid CRC errors.
1041          */
1042         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1043         if (ret_val)
1044                 return ret_val;
1045
1046         data |= GG82563_ICR_DIS_PADDING;
1047         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1048         if (ret_val)
1049                 return ret_val;
1050
1051         return 0;
1052 }
1053
1054 /**
1055  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1056  *  @hw: pointer to the HW structure
1057  *
1058  *  Essentially a wrapper for setting up all things "copper" related.
1059  *  This is a function pointer entry point called by the mac module.
1060  **/
1061 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1062 {
1063         u32 ctrl;
1064         s32 ret_val;
1065         u16 reg_data;
1066
1067         ctrl = er32(CTRL);
1068         ctrl |= E1000_CTRL_SLU;
1069         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1070         ew32(CTRL, ctrl);
1071
1072         /*
1073          * Set the mac to wait the maximum time between each
1074          * iteration and increase the max iterations when
1075          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1076          */
1077         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1078                                                    0xFFFF);
1079         if (ret_val)
1080                 return ret_val;
1081         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1082                                                   &reg_data);
1083         if (ret_val)
1084                 return ret_val;
1085         reg_data |= 0x3F;
1086         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1087                                                    reg_data);
1088         if (ret_val)
1089                 return ret_val;
1090         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1091                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1092                                       &reg_data);
1093         if (ret_val)
1094                 return ret_val;
1095         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1096         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1097                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1098                                         reg_data);
1099         if (ret_val)
1100                 return ret_val;
1101
1102         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1103         if (ret_val)
1104                 return ret_val;
1105
1106         ret_val = e1000e_setup_copper_link(hw);
1107
1108         return 0;
1109 }
1110
1111 /**
1112  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1113  *  @hw: pointer to the HW structure
1114  *  @duplex: current duplex setting
1115  *
1116  *  Configure the KMRN interface by applying last minute quirks for
1117  *  10/100 operation.
1118  **/
1119 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1120 {
1121         s32 ret_val = 0;
1122         u16 speed;
1123         u16 duplex;
1124
1125         if (hw->phy.media_type == e1000_media_type_copper) {
1126                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1127                                                              &duplex);
1128                 if (ret_val)
1129                         return ret_val;
1130
1131                 if (speed == SPEED_1000)
1132                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1133                 else
1134                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1135         }
1136
1137         return ret_val;
1138 }
1139
1140 /**
1141  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1142  *  @hw: pointer to the HW structure
1143  *  @duplex: current duplex setting
1144  *
1145  *  Configure the KMRN interface by applying last minute quirks for
1146  *  10/100 operation.
1147  **/
1148 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1149 {
1150         s32 ret_val;
1151         u32 tipg;
1152         u32 i = 0;
1153         u16 reg_data, reg_data2;
1154
1155         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1156         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1157                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1158                                        reg_data);
1159         if (ret_val)
1160                 return ret_val;
1161
1162         /* Configure Transmit Inter-Packet Gap */
1163         tipg = er32(TIPG);
1164         tipg &= ~E1000_TIPG_IPGT_MASK;
1165         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1166         ew32(TIPG, tipg);
1167
1168         do {
1169                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1170                 if (ret_val)
1171                         return ret_val;
1172
1173                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1174                 if (ret_val)
1175                         return ret_val;
1176                 i++;
1177         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1178
1179         if (duplex == HALF_DUPLEX)
1180                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1181         else
1182                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1183
1184         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1185
1186         return 0;
1187 }
1188
1189 /**
1190  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  Configure the KMRN interface by applying last minute quirks for
1194  *  gigabit operation.
1195  **/
1196 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1197 {
1198         s32 ret_val;
1199         u16 reg_data, reg_data2;
1200         u32 tipg;
1201         u32 i = 0;
1202
1203         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1204         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1205                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1206                                        reg_data);
1207         if (ret_val)
1208                 return ret_val;
1209
1210         /* Configure Transmit Inter-Packet Gap */
1211         tipg = er32(TIPG);
1212         tipg &= ~E1000_TIPG_IPGT_MASK;
1213         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1214         ew32(TIPG, tipg);
1215
1216         do {
1217                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1218                 if (ret_val)
1219                         return ret_val;
1220
1221                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1222                 if (ret_val)
1223                         return ret_val;
1224                 i++;
1225         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1226
1227         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1228         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1229
1230         return ret_val;
1231 }
1232
1233 /**
1234  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1235  *  @hw: pointer to the HW structure
1236  *  @offset: register offset to be read
1237  *  @data: pointer to the read data
1238  *
1239  *  Acquire semaphore, then read the PHY register at offset
1240  *  using the kumeran interface.  The information retrieved is stored in data.
1241  *  Release the semaphore before exiting.
1242  **/
1243 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1244                                            u16 *data)
1245 {
1246         u32 kmrnctrlsta;
1247         s32 ret_val = 0;
1248
1249         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1250         if (ret_val)
1251                 return ret_val;
1252
1253         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1254                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1255         ew32(KMRNCTRLSTA, kmrnctrlsta);
1256
1257         udelay(2);
1258
1259         kmrnctrlsta = er32(KMRNCTRLSTA);
1260         *data = (u16)kmrnctrlsta;
1261
1262         e1000_release_mac_csr_80003es2lan(hw);
1263
1264         return ret_val;
1265 }
1266
1267 /**
1268  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1269  *  @hw: pointer to the HW structure
1270  *  @offset: register offset to write to
1271  *  @data: data to write at register offset
1272  *
1273  *  Acquire semaphore, then write the data to PHY register
1274  *  at the offset using the kumeran interface.  Release semaphore
1275  *  before exiting.
1276  **/
1277 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1278                                             u16 data)
1279 {
1280         u32 kmrnctrlsta;
1281         s32 ret_val = 0;
1282
1283         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1284         if (ret_val)
1285                 return ret_val;
1286
1287         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1288                        E1000_KMRNCTRLSTA_OFFSET) | data;
1289         ew32(KMRNCTRLSTA, kmrnctrlsta);
1290
1291         udelay(2);
1292
1293         e1000_release_mac_csr_80003es2lan(hw);
1294
1295         return ret_val;
1296 }
1297
1298 /**
1299  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1300  *  @hw: pointer to the HW structure
1301  *
1302  *  Clears the hardware counters by reading the counter registers.
1303  **/
1304 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1305 {
1306         u32 temp;
1307
1308         e1000e_clear_hw_cntrs_base(hw);
1309
1310         temp = er32(PRC64);
1311         temp = er32(PRC127);
1312         temp = er32(PRC255);
1313         temp = er32(PRC511);
1314         temp = er32(PRC1023);
1315         temp = er32(PRC1522);
1316         temp = er32(PTC64);
1317         temp = er32(PTC127);
1318         temp = er32(PTC255);
1319         temp = er32(PTC511);
1320         temp = er32(PTC1023);
1321         temp = er32(PTC1522);
1322
1323         temp = er32(ALGNERRC);
1324         temp = er32(RXERRC);
1325         temp = er32(TNCRS);
1326         temp = er32(CEXTERR);
1327         temp = er32(TSCTC);
1328         temp = er32(TSCTFC);
1329
1330         temp = er32(MGTPRC);
1331         temp = er32(MGTPDC);
1332         temp = er32(MGTPTC);
1333
1334         temp = er32(IAC);
1335         temp = er32(ICRXOC);
1336
1337         temp = er32(ICRXPTC);
1338         temp = er32(ICRXATC);
1339         temp = er32(ICTXPTC);
1340         temp = er32(ICTXATC);
1341         temp = er32(ICTXQEC);
1342         temp = er32(ICTXQMTC);
1343         temp = er32(ICRXDMTC);
1344 }
1345
1346 static struct e1000_mac_operations es2_mac_ops = {
1347         .id_led_init            = e1000e_id_led_init,
1348         .check_mng_mode         = e1000e_check_mng_mode_generic,
1349         /* check_for_link dependent on media type */
1350         .cleanup_led            = e1000e_cleanup_led_generic,
1351         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1352         .get_bus_info           = e1000e_get_bus_info_pcie,
1353         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1354         .led_on                 = e1000e_led_on_generic,
1355         .led_off                = e1000e_led_off_generic,
1356         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1357         .reset_hw               = e1000_reset_hw_80003es2lan,
1358         .init_hw                = e1000_init_hw_80003es2lan,
1359         .setup_link             = e1000e_setup_link,
1360         /* setup_physical_interface dependent on media type */
1361         .setup_led              = e1000e_setup_led_generic,
1362 };
1363
1364 static struct e1000_phy_operations es2_phy_ops = {
1365         .acquire                = e1000_acquire_phy_80003es2lan,
1366         .check_reset_block      = e1000e_check_reset_block_generic,
1367         .commit                 = e1000e_phy_sw_reset,
1368         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1369         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1370         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1371         .get_info               = e1000e_get_phy_info_m88,
1372         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1373         .release                = e1000_release_phy_80003es2lan,
1374         .reset                  = e1000e_phy_hw_reset_generic,
1375         .set_d0_lplu_state      = NULL,
1376         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1377         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1378         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1379 };
1380
1381 static struct e1000_nvm_operations es2_nvm_ops = {
1382         .acquire                = e1000_acquire_nvm_80003es2lan,
1383         .read                   = e1000e_read_nvm_eerd,
1384         .release                = e1000_release_nvm_80003es2lan,
1385         .update                 = e1000e_update_nvm_checksum_generic,
1386         .valid_led_default      = e1000e_valid_led_default,
1387         .validate               = e1000e_validate_nvm_checksum_generic,
1388         .write                  = e1000_write_nvm_80003es2lan,
1389 };
1390
1391 struct e1000_info e1000_es2_info = {
1392         .mac                    = e1000_80003es2lan,
1393         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1394                                   | FLAG_HAS_JUMBO_FRAMES
1395                                   | FLAG_HAS_WOL
1396                                   | FLAG_APME_IN_CTRL3
1397                                   | FLAG_RX_CSUM_ENABLED
1398                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1399                                   | FLAG_RX_NEEDS_RESTART /* errata */
1400                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1401                                   | FLAG_APME_CHECK_PORT_B
1402                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1403                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1404         .pba                    = 38,
1405         .max_hw_frame_size      = DEFAULT_JUMBO,
1406         .get_variants           = e1000_get_variants_80003es2lan,
1407         .mac_ops                = &es2_mac_ops,
1408         .phy_ops                = &es2_phy_ops,
1409         .nvm_ops                = &es2_nvm_ops,
1410 };
1411