drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Copper)
  32  * 82571EB Gigabit Ethernet Controller (Fiber)
  33  * 82571EB Dual Port Gigabit Mezzanine Adapter
  34  * 82571EB Quad Port Gigabit Mezzanine Adapter
  35  * 82571PT Gigabit PT Quad Port Server ExpressModule
  36  * 82572EI Gigabit Ethernet Controller (Copper)
  37  * 82572EI Gigabit Ethernet Controller (Fiber)
  38  * 82572EI Gigabit Ethernet Controller
  39  * 82573V Gigabit Ethernet Controller (Copper)
  40  * 82573E Gigabit Ethernet Controller (Copper)
  41  * 82573L Gigabit Ethernet Controller
  42  * 82574L Gigabit Network Connection
  43  * 82583V Gigabit Network Connection
  44  */
  45
  46 #include "e1000.h"
  47
  48 #define ID_LED_RESERVED_F746 0xF746
  49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  50                               (ID_LED_OFF1_ON2  <<  8) | \
  51                               (ID_LED_DEF1_DEF2 <<  4) | \
  52                               (ID_LED_DEF1_DEF2))
  53
  54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  55
  56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  57
  58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  63                                       u16 words, u16 *data);
  64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  68 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  69 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  70 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  71
  72 /**
  73  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  74  *  @hw: pointer to the HW structure
  75  *
  76  *  This is a function pointer entry point called by the api module.
  77  **/
  78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  79 {
  80         struct e1000_phy_info *phy = &hw->phy;
  81         s32 ret_val;
  82
  83         if (hw->phy.media_type != e1000_media_type_copper) {
  84                 phy->type = e1000_phy_none;
  85                 return 0;
  86         }
  87
  88         phy->addr                        = 1;
  89         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  90         phy->reset_delay_us              = 100;
  91
  92         switch (hw->mac.type) {
  93         case e1000_82571:
  94         case e1000_82572:
  95                 phy->type                = e1000_phy_igp_2;
  96                 break;
  97         case e1000_82573:
  98                 phy->type                = e1000_phy_m88;
  99                 break;
 100         case e1000_82574:
 101         case e1000_82583:
 102                 phy->type                = e1000_phy_bm;
 103                 break;
 104         default:
 105                 return -E1000_ERR_PHY;
 106                 break;
 107         }
 108
 109         /* This can only be done after all function pointers are setup. */
 110         ret_val = e1000_get_phy_id_82571(hw);
 111
 112         /* Verify phy id */
 113         switch (hw->mac.type) {
 114         case e1000_82571:
 115         case e1000_82572:
 116                 if (phy->id != IGP01E1000_I_PHY_ID)
 117                         return -E1000_ERR_PHY;
 118                 break;
 119         case e1000_82573:
 120                 if (phy->id != M88E1111_I_PHY_ID)
 121                         return -E1000_ERR_PHY;
 122                 break;
 123         case e1000_82574:
 124         case e1000_82583:
 125                 if (phy->id != BME1000_E_PHY_ID_R2)
 126                         return -E1000_ERR_PHY;
 127                 break;
 128         default:
 129                 return -E1000_ERR_PHY;
 130                 break;
 131         }
 132
 133         return 0;
 134 }
 135
 136 /**
 137  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 138  *  @hw: pointer to the HW structure
 139  *
 140  *  This is a function pointer entry point called by the api module.
 141  **/
 142 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 143 {
 144         struct e1000_nvm_info *nvm = &hw->nvm;
 145         u32 eecd = er32(EECD);
 146         u16 size;
 147
 148         nvm->opcode_bits = 8;
 149         nvm->delay_usec = 1;
 150         switch (nvm->override) {
 151         case e1000_nvm_override_spi_large:
 152                 nvm->page_size = 32;
 153                 nvm->address_bits = 16;
 154                 break;
 155         case e1000_nvm_override_spi_small:
 156                 nvm->page_size = 8;
 157                 nvm->address_bits = 8;
 158                 break;
 159         default:
 160                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 161                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 162                 break;
 163         }
 164
 165         switch (hw->mac.type) {
 166         case e1000_82573:
 167         case e1000_82574:
 168         case e1000_82583:
 169                 if (((eecd >> 15) & 0x3) == 0x3) {
 170                         nvm->type = e1000_nvm_flash_hw;
 171                         nvm->word_size = 2048;
 172                         /*
 173                          * Autonomous Flash update bit must be cleared due
 174                          * to Flash update issue.
 175                          */
 176                         eecd &= ~E1000_EECD_AUPDEN;
 177                         ew32(EECD, eecd);
 178                         break;
 179                 }
 180                 /* Fall Through */
 181         default:
 182                 nvm->type = e1000_nvm_eeprom_spi;
 183                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 184                                   E1000_EECD_SIZE_EX_SHIFT);
 185                 /*
 186                  * Added to a constant, "size" becomes the left-shift value
 187                  * for setting word_size.
 188                  */
 189                 size += NVM_WORD_SIZE_BASE_SHIFT;
 190
 191                 /* EEPROM access above 16k is unsupported */
 192                 if (size > 14)
 193                         size = 14;
 194                 nvm->word_size  = 1 << size;
 195                 break;
 196         }
 197
 198         return 0;
 199 }
 200
 201 /**
 202  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 203  *  @hw: pointer to the HW structure
 204  *
 205  *  This is a function pointer entry point called by the api module.
 206  **/
 207 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 208 {
 209         struct e1000_hw *hw = &adapter->hw;
 210         struct e1000_mac_info *mac = &hw->mac;
 211         struct e1000_mac_operations *func = &mac->ops;
 212         u32 swsm = 0;
 213         u32 swsm2 = 0;
 214         bool force_clear_smbi = false;
 215
 216         /* Set media type */
 217         switch (adapter->pdev->device) {
 218         case E1000_DEV_ID_82571EB_FIBER:
 219         case E1000_DEV_ID_82572EI_FIBER:
 220         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 221                 hw->phy.media_type = e1000_media_type_fiber;
 222                 break;
 223         case E1000_DEV_ID_82571EB_SERDES:
 224         case E1000_DEV_ID_82572EI_SERDES:
 225         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 226         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 227                 hw->phy.media_type = e1000_media_type_internal_serdes;
 228                 break;
 229         default:
 230                 hw->phy.media_type = e1000_media_type_copper;
 231                 break;
 232         }
 233
 234         /* Set mta register count */
 235         mac->mta_reg_count = 128;
 236         /* Set rar entry count */
 237         mac->rar_entry_count = E1000_RAR_ENTRIES;
 238         /* Set if manageability features are enabled. */
 239         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 240
 241         /* check for link */
 242         switch (hw->phy.media_type) {
 243         case e1000_media_type_copper:
 244                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 245                 func->check_for_link = e1000e_check_for_copper_link;
 246                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 247                 break;
 248         case e1000_media_type_fiber:
 249                 func->setup_physical_interface =
 250                         e1000_setup_fiber_serdes_link_82571;
 251                 func->check_for_link = e1000e_check_for_fiber_link;
 252                 func->get_link_up_info =
 253                         e1000e_get_speed_and_duplex_fiber_serdes;
 254                 break;
 255         case e1000_media_type_internal_serdes:
 256                 func->setup_physical_interface =
 257                         e1000_setup_fiber_serdes_link_82571;
 258                 func->check_for_link = e1000_check_for_serdes_link_82571;
 259                 func->get_link_up_info =
 260                         e1000e_get_speed_and_duplex_fiber_serdes;
 261                 break;
 262         default:
 263                 return -E1000_ERR_CONFIG;
 264                 break;
 265         }
 266
 267         switch (hw->mac.type) {
 268         case e1000_82574:
 269         case e1000_82583:
 270                 func->check_mng_mode = e1000_check_mng_mode_82574;
 271                 func->led_on = e1000_led_on_82574;
 272                 break;
 273         default:
 274                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 275                 func->led_on = e1000e_led_on_generic;
 276                 break;
 277         }
 278
 279         /*
 280          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 281          * first NVM or PHY acess. This should be done for single-port
 282          * devices, and for one port only on dual-port devices so that
 283          * for those devices we can still use the SMBI lock to synchronize
 284          * inter-port accesses to the PHY & NVM.
 285          */
 286         switch (hw->mac.type) {
 287         case e1000_82571:
 288         case e1000_82572:
 289                 swsm2 = er32(SWSM2);
 290
 291                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 292                         /* Only do this for the first interface on this card */
 293                         ew32(SWSM2,
 294                             swsm2 | E1000_SWSM2_LOCK);
 295                         force_clear_smbi = true;
 296                 } else
 297                         force_clear_smbi = false;
 298                 break;
 299         default:
 300                 force_clear_smbi = true;
 301                 break;
 302         }
 303
 304         if (force_clear_smbi) {
 305                 /* Make sure SWSM.SMBI is clear */
 306                 swsm = er32(SWSM);
 307                 if (swsm & E1000_SWSM_SMBI) {
 308                         /* This bit should not be set on a first interface, and
 309                          * indicates that the bootagent or EFI code has
 310                          * improperly left this bit enabled
 311                          */
 312                         e_dbg("Please update your 82571 Bootagent\n");
 313                 }
 314                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 315         }
 316
 317         /*
 318          * Initialze device specific counter of SMBI acquisition
 319          * timeouts.
 320          */
 321          hw->dev_spec.e82571.smb_counter = 0;
 322
 323         return 0;
 324 }
 325
 326 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 327 {
 328         struct e1000_hw *hw = &adapter->hw;
 329         static int global_quad_port_a; /* global port a indication */
 330         struct pci_dev *pdev = adapter->pdev;
 331         u16 eeprom_data = 0;
 332         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 333         s32 rc;
 334
 335         rc = e1000_init_mac_params_82571(adapter);
 336         if (rc)
 337                 return rc;
 338
 339         rc = e1000_init_nvm_params_82571(hw);
 340         if (rc)
 341                 return rc;
 342
 343         rc = e1000_init_phy_params_82571(hw);
 344         if (rc)
 345                 return rc;
 346
 347         /* tag quad port adapters first, it's used below */
 348         switch (pdev->device) {
 349         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 350         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 351         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 352         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 353                 adapter->flags |= FLAG_IS_QUAD_PORT;
 354                 /* mark the first port */
 355                 if (global_quad_port_a == 0)
 356                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 357                 /* Reset for multiple quad port adapters */
 358                 global_quad_port_a++;
 359                 if (global_quad_port_a == 4)
 360                         global_quad_port_a = 0;
 361                 break;
 362         default:
 363                 break;
 364         }
 365
 366         switch (adapter->hw.mac.type) {
 367         case e1000_82571:
 368                 /* these dual ports don't have WoL on port B at all */
 369                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 370                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 371                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 372                     (is_port_b))
 373                         adapter->flags &= ~FLAG_HAS_WOL;
 374                 /* quad ports only support WoL on port A */
 375                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 376                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 377                         adapter->flags &= ~FLAG_HAS_WOL;
 378                 /* Does not support WoL on any port */
 379                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 380                         adapter->flags &= ~FLAG_HAS_WOL;
 381                 break;
 382
 383         case e1000_82573:
 384                 if (pdev->device == E1000_DEV_ID_82573L) {
 385                         if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
 386                                        &eeprom_data) < 0)
 387                                 break;
 388                         if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
 389                                 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 390                                 adapter->max_hw_frame_size = DEFAULT_JUMBO;
 391                         }
 392                 }
 393                 break;
 394         default:
 395                 break;
 396         }
 397
 398         return 0;
 399 }
 400
 401 /**
 402  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 403  *  @hw: pointer to the HW structure
 404  *
 405  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 406  *  revision in the hardware structure.
 407  **/
 408 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 409 {
 410         struct e1000_phy_info *phy = &hw->phy;
 411         s32 ret_val;
 412         u16 phy_id = 0;
 413
 414         switch (hw->mac.type) {
 415         case e1000_82571:
 416         case e1000_82572:
 417                 /*
 418                  * The 82571 firmware may still be configuring the PHY.
 419                  * In this case, we cannot access the PHY until the
 420                  * configuration is done.  So we explicitly set the
 421                  * PHY ID.
 422                  */
 423                 phy->id = IGP01E1000_I_PHY_ID;
 424                 break;
 425         case e1000_82573:
 426                 return e1000e_get_phy_id(hw);
 427                 break;
 428         case e1000_82574:
 429         case e1000_82583:
 430                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 431                 if (ret_val)
 432                         return ret_val;
 433
 434                 phy->id = (u32)(phy_id << 16);
 435                 udelay(20);
 436                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 437                 if (ret_val)
 438                         return ret_val;
 439
 440                 phy->id |= (u32)(phy_id);
 441                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 442                 break;
 443         default:
 444                 return -E1000_ERR_PHY;
 445                 break;
 446         }
 447
 448         return 0;
 449 }
 450
 451 /**
 452  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 453  *  @hw: pointer to the HW structure
 454  *
 455  *  Acquire the HW semaphore to access the PHY or NVM
 456  **/
 457 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 458 {
 459         u32 swsm;
 460         s32 sw_timeout = hw->nvm.word_size + 1;
 461         s32 fw_timeout = hw->nvm.word_size + 1;
 462         s32 i = 0;
 463
 464         /*
 465          * If we have timedout 3 times on trying to acquire
 466          * the inter-port SMBI semaphore, there is old code
 467          * operating on the other port, and it is not
 468          * releasing SMBI. Modify the number of times that
 469          * we try for the semaphore to interwork with this
 470          * older code.
 471          */
 472         if (hw->dev_spec.e82571.smb_counter > 2)
 473                 sw_timeout = 1;
 474
 475         /* Get the SW semaphore */
 476         while (i < sw_timeout) {
 477                 swsm = er32(SWSM);
 478                 if (!(swsm & E1000_SWSM_SMBI))
 479                         break;
 480
 481                 udelay(50);
 482                 i++;
 483         }
 484
 485         if (i == sw_timeout) {
 486                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 487                 hw->dev_spec.e82571.smb_counter++;
 488         }
 489         /* Get the FW semaphore. */
 490         for (i = 0; i < fw_timeout; i++) {
 491                 swsm = er32(SWSM);
 492                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 493
 494                 /* Semaphore acquired if bit latched */
 495                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 496                         break;
 497
 498                 udelay(50);
 499         }
 500
 501         if (i == fw_timeout) {
 502                 /* Release semaphores */
 503                 e1000_put_hw_semaphore_82571(hw);
 504                 e_dbg("Driver can't access the NVM\n");
 505                 return -E1000_ERR_NVM;
 506         }
 507
 508         return 0;
 509 }
 510
 511 /**
 512  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 513  *  @hw: pointer to the HW structure
 514  *
 515  *  Release hardware semaphore used to access the PHY or NVM
 516  **/
 517 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 518 {
 519         u32 swsm;
 520
 521         swsm = er32(SWSM);
 522         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 523         ew32(SWSM, swsm);
 524 }
 525
 526 /**
 527  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 528  *  @hw: pointer to the HW structure
 529  *
 530  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 531  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 532  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 533  *  hardware semaphore.
 534  **/
 535 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 536 {
 537         s32 ret_val;
 538
 539         ret_val = e1000_get_hw_semaphore_82571(hw);
 540         if (ret_val)
 541                 return ret_val;
 542
 543         switch (hw->mac.type) {
 544         case e1000_82573:
 545         case e1000_82574:
 546         case e1000_82583:
 547                 break;
 548         default:
 549                 ret_val = e1000e_acquire_nvm(hw);
 550                 break;
 551         }
 552
 553         if (ret_val)
 554                 e1000_put_hw_semaphore_82571(hw);
 555
 556         return ret_val;
 557 }
 558
 559 /**
 560  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 561  *  @hw: pointer to the HW structure
 562  *
 563  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 564  **/
 565 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 566 {
 567         e1000e_release_nvm(hw);
 568         e1000_put_hw_semaphore_82571(hw);
 569 }
 570
 571 /**
 572  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 573  *  @hw: pointer to the HW structure
 574  *  @offset: offset within the EEPROM to be written to
 575  *  @words: number of words to write
 576  *  @data: 16 bit word(s) to be written to the EEPROM
 577  *
 578  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 579  *
 580  *  If e1000e_update_nvm_checksum is not called after this function, the
 581  *  EEPROM will most likely contain an invalid checksum.
 582  **/
 583 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 584                                  u16 *data)
 585 {
 586         s32 ret_val;
 587
 588         switch (hw->mac.type) {
 589         case e1000_82573:
 590         case e1000_82574:
 591         case e1000_82583:
 592                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 593                 break;
 594         case e1000_82571:
 595         case e1000_82572:
 596                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 597                 break;
 598         default:
 599                 ret_val = -E1000_ERR_NVM;
 600                 break;
 601         }
 602
 603         return ret_val;
 604 }
 605
 606 /**
 607  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 608  *  @hw: pointer to the HW structure
 609  *
 610  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 611  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 612  *  value to the EEPROM.
 613  **/
 614 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 615 {
 616         u32 eecd;
 617         s32 ret_val;
 618         u16 i;
 619
 620         ret_val = e1000e_update_nvm_checksum_generic(hw);
 621         if (ret_val)
 622                 return ret_val;
 623
 624         /*
 625          * If our nvm is an EEPROM, then we're done
 626          * otherwise, commit the checksum to the flash NVM.
 627          */
 628         if (hw->nvm.type != e1000_nvm_flash_hw)
 629                 return ret_val;
 630
 631         /* Check for pending operations. */
 632         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 633                 msleep(1);
 634                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 635                         break;
 636         }
 637
 638         if (i == E1000_FLASH_UPDATES)
 639                 return -E1000_ERR_NVM;
 640
 641         /* Reset the firmware if using STM opcode. */
 642         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 643                 /*
 644                  * The enabling of and the actual reset must be done
 645                  * in two write cycles.
 646                  */
 647                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 648                 e1e_flush();
 649                 ew32(HICR, E1000_HICR_FW_RESET);
 650         }
 651
 652         /* Commit the write to flash */
 653         eecd = er32(EECD) | E1000_EECD_FLUPD;
 654         ew32(EECD, eecd);
 655
 656         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 657                 msleep(1);
 658                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 659                         break;
 660         }
 661
 662         if (i == E1000_FLASH_UPDATES)
 663                 return -E1000_ERR_NVM;
 664
 665         return 0;
 666 }
 667
 668 /**
 669  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 670  *  @hw: pointer to the HW structure
 671  *
 672  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 673  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 674  **/
 675 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 676 {
 677         if (hw->nvm.type == e1000_nvm_flash_hw)
 678                 e1000_fix_nvm_checksum_82571(hw);
 679
 680         return e1000e_validate_nvm_checksum_generic(hw);
 681 }
 682
 683 /**
 684  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 685  *  @hw: pointer to the HW structure
 686  *  @offset: offset within the EEPROM to be written to
 687  *  @words: number of words to write
 688  *  @data: 16 bit word(s) to be written to the EEPROM
 689  *
 690  *  After checking for invalid values, poll the EEPROM to ensure the previous
 691  *  command has completed before trying to write the next word.  After write
 692  *  poll for completion.
 693  *
 694  *  If e1000e_update_nvm_checksum is not called after this function, the
 695  *  EEPROM will most likely contain an invalid checksum.
 696  **/
 697 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 698                                       u16 words, u16 *data)
 699 {
 700         struct e1000_nvm_info *nvm = &hw->nvm;
 701         u32 i;
 702         u32 eewr = 0;
 703         s32 ret_val = 0;
 704
 705         /*
 706          * A check for invalid values:  offset too large, too many words,
 707          * and not enough words.
 708          */
 709         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 710             (words == 0)) {
 711                 e_dbg("nvm parameter(s) out of bounds\n");
 712                 return -E1000_ERR_NVM;
 713         }
 714
 715         for (i = 0; i < words; i++) {
 716                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 717                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 718                        E1000_NVM_RW_REG_START;
 719
 720                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 721                 if (ret_val)
 722                         break;
 723
 724                 ew32(EEWR, eewr);
 725
 726                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 727                 if (ret_val)
 728                         break;
 729         }
 730
 731         return ret_val;
 732 }
 733
 734 /**
 735  *  e1000_get_cfg_done_82571 - Poll for configuration done
 736  *  @hw: pointer to the HW structure
 737  *
 738  *  Reads the management control register for the config done bit to be set.
 739  **/
 740 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 741 {
 742         s32 timeout = PHY_CFG_TIMEOUT;
 743
 744         while (timeout) {
 745                 if (er32(EEMNGCTL) &
 746                     E1000_NVM_CFG_DONE_PORT_0)
 747                         break;
 748                 msleep(1);
 749                 timeout--;
 750         }
 751         if (!timeout) {
 752                 e_dbg("MNG configuration cycle has not completed.\n");
 753                 return -E1000_ERR_RESET;
 754         }
 755
 756         return 0;
 757 }
 758
 759 /**
 760  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 761  *  @hw: pointer to the HW structure
 762  *  @active: TRUE to enable LPLU, FALSE to disable
 763  *
 764  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 765  *  this function also disables smart speed and vice versa.  LPLU will not be
 766  *  activated unless the device autonegotiation advertisement meets standards
 767  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 768  *  pointer entry point only called by PHY setup routines.
 769  **/
 770 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 771 {
 772         struct e1000_phy_info *phy = &hw->phy;
 773         s32 ret_val;
 774         u16 data;
 775
 776         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 777         if (ret_val)
 778                 return ret_val;
 779
 780         if (active) {
 781                 data |= IGP02E1000_PM_D0_LPLU;
 782                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 783                 if (ret_val)
 784                         return ret_val;
 785
 786                 /* When LPLU is enabled, we should disable SmartSpeed */
 787                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 788                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 789                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 790                 if (ret_val)
 791                         return ret_val;
 792         } else {
 793                 data &= ~IGP02E1000_PM_D0_LPLU;
 794                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 795                 /*
 796                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 797                  * during Dx states where the power conservation is most
 798                  * important.  During driver activity we should enable
 799                  * SmartSpeed, so performance is maintained.
 800                  */
 801                 if (phy->smart_speed == e1000_smart_speed_on) {
 802                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 803                                            &data);
 804                         if (ret_val)
 805                                 return ret_val;
 806
 807                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 808                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 809                                            data);
 810                         if (ret_val)
 811                                 return ret_val;
 812                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 813                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 814                                            &data);
 815                         if (ret_val)
 816                                 return ret_val;
 817
 818                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 819                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 820                                            data);
 821                         if (ret_val)
 822                                 return ret_val;
 823                 }
 824         }
 825
 826         return 0;
 827 }
 828
 829 /**
 830  *  e1000_reset_hw_82571 - Reset hardware
 831  *  @hw: pointer to the HW structure
 832  *
 833  *  This resets the hardware into a known state.  This is a
 834  *  function pointer entry point called by the api module.
 835  **/
 836 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 837 {
 838         u32 ctrl;
 839         u32 extcnf_ctrl;
 840         u32 ctrl_ext;
 841         u32 icr;
 842         s32 ret_val;
 843         u16 i = 0;
 844
 845         /*
 846          * Prevent the PCI-E bus from sticking if there is no TLP connection
 847          * on the last TLP read/write transaction when MAC is reset.
 848          */
 849         ret_val = e1000e_disable_pcie_master(hw);
 850         if (ret_val)
 851                 e_dbg("PCI-E Master disable polling has failed.\n");
 852
 853         e_dbg("Masking off all interrupts\n");
 854         ew32(IMC, 0xffffffff);
 855
 856         ew32(RCTL, 0);
 857         ew32(TCTL, E1000_TCTL_PSP);
 858         e1e_flush();
 859
 860         msleep(10);
 861
 862         /*
 863          * Must acquire the MDIO ownership before MAC reset.
 864          * Ownership defaults to firmware after a reset.
 865          */
 866         switch (hw->mac.type) {
 867         case e1000_82573:
 868         case e1000_82574:
 869         case e1000_82583:
 870                 extcnf_ctrl = er32(EXTCNF_CTRL);
 871                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 872
 873                 do {
 874                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 875                         extcnf_ctrl = er32(EXTCNF_CTRL);
 876
 877                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 878                                 break;
 879
 880                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 881
 882                         msleep(2);
 883                         i++;
 884                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 885                 break;
 886         default:
 887                 break;
 888         }
 889
 890         ctrl = er32(CTRL);
 891
 892         e_dbg("Issuing a global reset to MAC\n");
 893         ew32(CTRL, ctrl | E1000_CTRL_RST);
 894
 895         if (hw->nvm.type == e1000_nvm_flash_hw) {
 896                 udelay(10);
 897                 ctrl_ext = er32(CTRL_EXT);
 898                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 899                 ew32(CTRL_EXT, ctrl_ext);
 900                 e1e_flush();
 901         }
 902
 903         ret_val = e1000e_get_auto_rd_done(hw);
 904         if (ret_val)
 905                 /* We don't want to continue accessing MAC registers. */
 906                 return ret_val;
 907
 908         /*
 909          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 910          * Need to wait for Phy configuration completion before accessing
 911          * NVM and Phy.
 912          */
 913
 914         switch (hw->mac.type) {
 915         case e1000_82573:
 916         case e1000_82574:
 917         case e1000_82583:
 918                 msleep(25);
 919                 break;
 920         default:
 921                 break;
 922         }
 923
 924         /* Clear any pending interrupt events. */
 925         ew32(IMC, 0xffffffff);
 926         icr = er32(ICR);
 927
 928         if (hw->mac.type == e1000_82571 &&
 929                 hw->dev_spec.e82571.alt_mac_addr_is_present)
 930                         e1000e_set_laa_state_82571(hw, true);
 931
 932         /* Reinitialize the 82571 serdes link state machine */
 933         if (hw->phy.media_type == e1000_media_type_internal_serdes)
 934                 hw->mac.serdes_link_state = e1000_serdes_link_down;
 935
 936         return 0;
 937 }
 938
 939 /**
 940  *  e1000_init_hw_82571 - Initialize hardware
 941  *  @hw: pointer to the HW structure
 942  *
 943  *  This inits the hardware readying it for operation.
 944  **/
 945 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 946 {
 947         struct e1000_mac_info *mac = &hw->mac;
 948         u32 reg_data;
 949         s32 ret_val;
 950         u16 i;
 951         u16 rar_count = mac->rar_entry_count;
 952
 953         e1000_initialize_hw_bits_82571(hw);
 954
 955         /* Initialize identification LED */
 956         ret_val = e1000e_id_led_init(hw);
 957         if (ret_val) {
 958                 e_dbg("Error initializing identification LED\n");
 959                 return ret_val;
 960         }
 961
 962         /* Disabling VLAN filtering */
 963         e_dbg("Initializing the IEEE VLAN\n");
 964         e1000e_clear_vfta(hw);
 965
 966         /* Setup the receive address. */
 967         /*
 968          * If, however, a locally administered address was assigned to the
 969          * 82571, we must reserve a RAR for it to work around an issue where
 970          * resetting one port will reload the MAC on the other port.
 971          */
 972         if (e1000e_get_laa_state_82571(hw))
 973                 rar_count--;
 974         e1000e_init_rx_addrs(hw, rar_count);
 975
 976         /* Zero out the Multicast HASH table */
 977         e_dbg("Zeroing the MTA\n");
 978         for (i = 0; i < mac->mta_reg_count; i++)
 979                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 980
 981         /* Setup link and flow control */
 982         ret_val = e1000_setup_link_82571(hw);
 983
 984         /* Set the transmit descriptor write-back policy */
 985         reg_data = er32(TXDCTL(0));
 986         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 987                    E1000_TXDCTL_FULL_TX_DESC_WB |
 988                    E1000_TXDCTL_COUNT_DESC;
 989         ew32(TXDCTL(0), reg_data);
 990
 991         /* ...for both queues. */
 992         switch (mac->type) {
 993         case e1000_82573:
 994         case e1000_82574:
 995         case e1000_82583:
 996                 e1000e_enable_tx_pkt_filtering(hw);
 997                 reg_data = er32(GCR);
 998                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
 999                 ew32(GCR, reg_data);
1000                 break;
1001         default:
1002                 reg_data = er32(TXDCTL(1));
1003                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1004                            E1000_TXDCTL_FULL_TX_DESC_WB |
1005                            E1000_TXDCTL_COUNT_DESC;
1006                 ew32(TXDCTL(1), reg_data);
1007                 break;
1008         }
1009
1010         /*
1011          * Clear all of the statistics registers (clear on read).  It is
1012          * important that we do this after we have tried to establish link
1013          * because the symbol error count will increment wildly if there
1014          * is no link.
1015          */
1016         e1000_clear_hw_cntrs_82571(hw);
1017
1018         return ret_val;
1019 }
1020
1021 /**
1022  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1023  *  @hw: pointer to the HW structure
1024  *
1025  *  Initializes required hardware-dependent bits needed for normal operation.
1026  **/
1027 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1028 {
1029         u32 reg;
1030
1031         /* Transmit Descriptor Control 0 */
1032         reg = er32(TXDCTL(0));
1033         reg |= (1 << 22);
1034         ew32(TXDCTL(0), reg);
1035
1036         /* Transmit Descriptor Control 1 */
1037         reg = er32(TXDCTL(1));
1038         reg |= (1 << 22);
1039         ew32(TXDCTL(1), reg);
1040
1041         /* Transmit Arbitration Control 0 */
1042         reg = er32(TARC(0));
1043         reg &= ~(0xF << 27); /* 30:27 */
1044         switch (hw->mac.type) {
1045         case e1000_82571:
1046         case e1000_82572:
1047                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1048                 break;
1049         default:
1050                 break;
1051         }
1052         ew32(TARC(0), reg);
1053
1054         /* Transmit Arbitration Control 1 */
1055         reg = er32(TARC(1));
1056         switch (hw->mac.type) {
1057         case e1000_82571:
1058         case e1000_82572:
1059                 reg &= ~((1 << 29) | (1 << 30));
1060                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1061                 if (er32(TCTL) & E1000_TCTL_MULR)
1062                         reg &= ~(1 << 28);
1063                 else
1064                         reg |= (1 << 28);
1065                 ew32(TARC(1), reg);
1066                 break;
1067         default:
1068                 break;
1069         }
1070
1071         /* Device Control */
1072         switch (hw->mac.type) {
1073         case e1000_82573:
1074         case e1000_82574:
1075         case e1000_82583:
1076                 reg = er32(CTRL);
1077                 reg &= ~(1 << 29);
1078                 ew32(CTRL, reg);
1079                 break;
1080         default:
1081                 break;
1082         }
1083
1084         /* Extended Device Control */
1085         switch (hw->mac.type) {
1086         case e1000_82573:
1087         case e1000_82574:
1088         case e1000_82583:
1089                 reg = er32(CTRL_EXT);
1090                 reg &= ~(1 << 23);
1091                 reg |= (1 << 22);
1092                 ew32(CTRL_EXT, reg);
1093                 break;
1094         default:
1095                 break;
1096         }
1097
1098         if (hw->mac.type == e1000_82571) {
1099                 reg = er32(PBA_ECC);
1100                 reg |= E1000_PBA_ECC_CORR_EN;
1101                 ew32(PBA_ECC, reg);
1102         }
1103         /*
1104          * Workaround for hardware errata.
1105          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1106          */
1107
1108         if ((hw->mac.type == e1000_82571) ||
1109            (hw->mac.type == e1000_82572)) {
1110                 reg = er32(CTRL_EXT);
1111                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1112                 ew32(CTRL_EXT, reg);
1113         }
1114
1115
1116         /* PCI-Ex Control Registers */
1117         switch (hw->mac.type) {
1118         case e1000_82574:
1119         case e1000_82583:
1120                 reg = er32(GCR);
1121                 reg |= (1 << 22);
1122                 ew32(GCR, reg);
1123
1124                 reg = er32(GCR2);
1125                 reg |= 1;
1126                 ew32(GCR2, reg);
1127                 break;
1128         default:
1129                 break;
1130         }
1131
1132         return;
1133 }
1134
1135 /**
1136  *  e1000e_clear_vfta - Clear VLAN filter table
1137  *  @hw: pointer to the HW structure
1138  *
1139  *  Clears the register array which contains the VLAN filter table by
1140  *  setting all the values to 0.
1141  **/
1142 void e1000e_clear_vfta(struct e1000_hw *hw)
1143 {
1144         u32 offset;
1145         u32 vfta_value = 0;
1146         u32 vfta_offset = 0;
1147         u32 vfta_bit_in_reg = 0;
1148
1149         switch (hw->mac.type) {
1150         case e1000_82573:
1151         case e1000_82574:
1152         case e1000_82583:
1153                 if (hw->mng_cookie.vlan_id != 0) {
1154                         /*
1155                          * The VFTA is a 4096b bit-field, each identifying
1156                          * a single VLAN ID.  The following operations
1157                          * determine which 32b entry (i.e. offset) into the
1158                          * array we want to set the VLAN ID (i.e. bit) of
1159                          * the manageability unit.
1160                          */
1161                         vfta_offset = (hw->mng_cookie.vlan_id >>
1162                                        E1000_VFTA_ENTRY_SHIFT) &
1163                                       E1000_VFTA_ENTRY_MASK;
1164                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1165                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1166                 }
1167                 break;
1168         default:
1169                 break;
1170         }
1171         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1172                 /*
1173                  * If the offset we want to clear is the same offset of the
1174                  * manageability VLAN ID, then clear all bits except that of
1175                  * the manageability unit.
1176                  */
1177                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1178                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1179                 e1e_flush();
1180         }
1181 }
1182
1183 /**
1184  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1185  *  @hw: pointer to the HW structure
1186  *
1187  *  Reads the NVM Initialization Control Word 2 and returns true
1188  *  (>0) if any manageability is enabled, else false (0).
1189  **/
1190 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1191 {
1192         u16 data;
1193
1194         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1195         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1196 }
1197
1198 /**
1199  *  e1000_led_on_82574 - Turn LED on
1200  *  @hw: pointer to the HW structure
1201  *
1202  *  Turn LED on.
1203  **/
1204 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1205 {
1206         u32 ctrl;
1207         u32 i;
1208
1209         ctrl = hw->mac.ledctl_mode2;
1210         if (!(E1000_STATUS_LU & er32(STATUS))) {
1211                 /*
1212                  * If no link, then turn LED on by setting the invert bit
1213                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1214                  */
1215                 for (i = 0; i < 4; i++)
1216                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1217                             E1000_LEDCTL_MODE_LED_ON)
1218                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1219         }
1220         ew32(LEDCTL, ctrl);
1221
1222         return 0;
1223 }
1224
1225 /**
1226  *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
1227  *  @hw: pointer to the HW structure
1228  *  @mc_addr_list: array of multicast addresses to program
1229  *  @mc_addr_count: number of multicast addresses to program
1230  *  @rar_used_count: the first RAR register free to program
1231  *  @rar_count: total number of supported Receive Address Registers
1232  *
1233  *  Updates the Receive Address Registers and Multicast Table Array.
1234  *  The caller must have a packed mc_addr_list of multicast addresses.
1235  *  The parameter rar_count will usually be hw->mac.rar_entry_count
1236  *  unless there are workarounds that change this.
1237  **/
1238 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1239                                             u8 *mc_addr_list,
1240                                             u32 mc_addr_count,
1241                                             u32 rar_used_count,
1242                                             u32 rar_count)
1243 {
1244         if (e1000e_get_laa_state_82571(hw))
1245                 rar_count--;
1246
1247         e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1248                                            rar_used_count, rar_count);
1249 }
1250
1251 /**
1252  *  e1000_setup_link_82571 - Setup flow control and link settings
1253  *  @hw: pointer to the HW structure
1254  *
1255  *  Determines which flow control settings to use, then configures flow
1256  *  control.  Calls the appropriate media-specific link configuration
1257  *  function.  Assuming the adapter has a valid link partner, a valid link
1258  *  should be established.  Assumes the hardware has previously been reset
1259  *  and the transmitter and receiver are not enabled.
1260  **/
1261 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1262 {
1263         /*
1264          * 82573 does not have a word in the NVM to determine
1265          * the default flow control setting, so we explicitly
1266          * set it to full.
1267          */
1268         switch (hw->mac.type) {
1269         case e1000_82573:
1270         case e1000_82574:
1271         case e1000_82583:
1272                 if (hw->fc.requested_mode == e1000_fc_default)
1273                         hw->fc.requested_mode = e1000_fc_full;
1274                 break;
1275         default:
1276                 break;
1277         }
1278
1279         return e1000e_setup_link(hw);
1280 }
1281
1282 /**
1283  *  e1000_setup_copper_link_82571 - Configure copper link settings
1284  *  @hw: pointer to the HW structure
1285  *
1286  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1287  *  for link, once link is established calls to configure collision distance
1288  *  and flow control are called.
1289  **/
1290 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1291 {
1292         u32 ctrl;
1293         u32 led_ctrl;
1294         s32 ret_val;
1295
1296         ctrl = er32(CTRL);
1297         ctrl |= E1000_CTRL_SLU;
1298         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1299         ew32(CTRL, ctrl);
1300
1301         switch (hw->phy.type) {
1302         case e1000_phy_m88:
1303         case e1000_phy_bm:
1304                 ret_val = e1000e_copper_link_setup_m88(hw);
1305                 break;
1306         case e1000_phy_igp_2:
1307                 ret_val = e1000e_copper_link_setup_igp(hw);
1308                 /* Setup activity LED */
1309                 led_ctrl = er32(LEDCTL);
1310                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1311                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1312                 ew32(LEDCTL, led_ctrl);
1313                 break;
1314         default:
1315                 return -E1000_ERR_PHY;
1316                 break;
1317         }
1318
1319         if (ret_val)
1320                 return ret_val;
1321
1322         ret_val = e1000e_setup_copper_link(hw);
1323
1324         return ret_val;
1325 }
1326
1327 /**
1328  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1329  *  @hw: pointer to the HW structure
1330  *
1331  *  Configures collision distance and flow control for fiber and serdes links.
1332  *  Upon successful setup, poll for link.
1333  **/
1334 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1335 {
1336         switch (hw->mac.type) {
1337         case e1000_82571:
1338         case e1000_82572:
1339                 /*
1340                  * If SerDes loopback mode is entered, there is no form
1341                  * of reset to take the adapter out of that mode.  So we
1342                  * have to explicitly take the adapter out of loopback
1343                  * mode.  This prevents drivers from twiddling their thumbs
1344                  * if another tool failed to take it out of loopback mode.
1345                  */
1346                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1347                 break;
1348         default:
1349                 break;
1350         }
1351
1352         return e1000e_setup_fiber_serdes_link(hw);
1353 }
1354
1355 /**
1356  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1357  *  @hw: pointer to the HW structure
1358  *
1359  *  Checks for link up on the hardware.  If link is not up and we have
1360  *  a signal, then we need to force link up.
1361  **/
1362 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1363 {
1364         struct e1000_mac_info *mac = &hw->mac;
1365         u32 rxcw;
1366         u32 ctrl;
1367         u32 status;
1368         s32 ret_val = 0;
1369
1370         ctrl = er32(CTRL);
1371         status = er32(STATUS);
1372         rxcw = er32(RXCW);
1373
1374         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1375
1376                 /* Receiver is synchronized with no invalid bits.  */
1377                 switch (mac->serdes_link_state) {
1378                 case e1000_serdes_link_autoneg_complete:
1379                         if (!(status & E1000_STATUS_LU)) {
1380                                 /*
1381                                  * We have lost link, retry autoneg before
1382                                  * reporting link failure
1383                                  */
1384                                 mac->serdes_link_state =
1385                                     e1000_serdes_link_autoneg_progress;
1386                                 e_dbg("AN_UP     -> AN_PROG\n");
1387                         }
1388                 break;
1389
1390                 case e1000_serdes_link_forced_up:
1391                         /*
1392                          * If we are receiving /C/ ordered sets, re-enable
1393                          * auto-negotiation in the TXCW register and disable
1394                          * forced link in the Device Control register in an
1395                          * attempt to auto-negotiate with our link partner.
1396                          */
1397                         if (rxcw & E1000_RXCW_C) {
1398                                 /* Enable autoneg, and unforce link up */
1399                                 ew32(TXCW, mac->txcw);
1400                                 ew32(CTRL,
1401                                     (ctrl & ~E1000_CTRL_SLU));
1402                                 mac->serdes_link_state =
1403                                     e1000_serdes_link_autoneg_progress;
1404                                 e_dbg("FORCED_UP -> AN_PROG\n");
1405                         }
1406                         break;
1407
1408                 case e1000_serdes_link_autoneg_progress:
1409                         /*
1410                          * If the LU bit is set in the STATUS register,
1411                          * autoneg has completed sucessfully. If not,
1412                          * try foring the link because the far end may be
1413                          * available but not capable of autonegotiation.
1414                          */
1415                         if (status & E1000_STATUS_LU)  {
1416                                 mac->serdes_link_state =
1417                                     e1000_serdes_link_autoneg_complete;
1418                                 e_dbg("AN_PROG   -> AN_UP\n");
1419                         } else {
1420                                 /*
1421                                  * Disable autoneg, force link up and
1422                                  * full duplex, and change state to forced
1423                                  */
1424                                 ew32(TXCW,
1425                                     (mac->txcw & ~E1000_TXCW_ANE));
1426                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1427                                 ew32(CTRL, ctrl);
1428
1429                                 /* Configure Flow Control after link up. */
1430                                 ret_val =
1431                                     e1000e_config_fc_after_link_up(hw);
1432                                 if (ret_val) {
1433                                         e_dbg("Error config flow control\n");
1434                                         break;
1435                                 }
1436                                 mac->serdes_link_state =
1437                                     e1000_serdes_link_forced_up;
1438                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1439                         }
1440                         mac->serdes_has_link = true;
1441                         break;
1442
1443                 case e1000_serdes_link_down:
1444                 default:
1445                         /* The link was down but the receiver has now gained
1446                          * valid sync, so lets see if we can bring the link
1447                          * up. */
1448                         ew32(TXCW, mac->txcw);
1449                         ew32(CTRL,
1450                             (ctrl & ~E1000_CTRL_SLU));
1451                         mac->serdes_link_state =
1452                             e1000_serdes_link_autoneg_progress;
1453                         e_dbg("DOWN      -> AN_PROG\n");
1454                         break;
1455                 }
1456         } else {
1457                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1458                         mac->serdes_has_link = false;
1459                         mac->serdes_link_state = e1000_serdes_link_down;
1460                         e_dbg("ANYSTATE  -> DOWN\n");
1461                 } else {
1462                         /*
1463                          * We have sync, and can tolerate one
1464                          * invalid (IV) codeword before declaring
1465                          * link down, so reread to look again
1466                          */
1467                         udelay(10);
1468                         rxcw = er32(RXCW);
1469                         if (rxcw & E1000_RXCW_IV) {
1470                                 mac->serdes_link_state = e1000_serdes_link_down;
1471                                 mac->serdes_has_link = false;
1472                                 e_dbg("ANYSTATE  -> DOWN\n");
1473                         }
1474                 }
1475         }
1476
1477         return ret_val;
1478 }
1479
1480 /**
1481  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1482  *  @hw: pointer to the HW structure
1483  *  @data: pointer to the NVM (EEPROM)
1484  *
1485  *  Read the EEPROM for the current default LED configuration.  If the
1486  *  LED configuration is not valid, set to a valid LED configuration.
1487  **/
1488 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1489 {
1490         s32 ret_val;
1491
1492         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1493         if (ret_val) {
1494                 e_dbg("NVM Read Error\n");
1495                 return ret_val;
1496         }
1497
1498         switch (hw->mac.type) {
1499         case e1000_82573:
1500         case e1000_82574:
1501         case e1000_82583:
1502                 if (*data == ID_LED_RESERVED_F746)
1503                         *data = ID_LED_DEFAULT_82573;
1504                 break;
1505         default:
1506                 if (*data == ID_LED_RESERVED_0000 ||
1507                     *data == ID_LED_RESERVED_FFFF)
1508                         *data = ID_LED_DEFAULT;
1509                 break;
1510         }
1511
1512         return 0;
1513 }
1514
1515 /**
1516  *  e1000e_get_laa_state_82571 - Get locally administered address state
1517  *  @hw: pointer to the HW structure
1518  *
1519  *  Retrieve and return the current locally administered address state.
1520  **/
1521 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1522 {
1523         if (hw->mac.type != e1000_82571)
1524                 return 0;
1525
1526         return hw->dev_spec.e82571.laa_is_present;
1527 }
1528
1529 /**
1530  *  e1000e_set_laa_state_82571 - Set locally administered address state
1531  *  @hw: pointer to the HW structure
1532  *  @state: enable/disable locally administered address
1533  *
1534  *  Enable/Disable the current locally administers address state.
1535  **/
1536 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1537 {
1538         if (hw->mac.type != e1000_82571)
1539                 return;
1540
1541         hw->dev_spec.e82571.laa_is_present = state;
1542
1543         /* If workaround is activated... */
1544         if (state)
1545                 /*
1546                  * Hold a copy of the LAA in RAR[14] This is done so that
1547                  * between the time RAR[0] gets clobbered and the time it
1548                  * gets fixed, the actual LAA is in one of the RARs and no
1549                  * incoming packets directed to this port are dropped.
1550                  * Eventually the LAA will be in RAR[0] and RAR[14].
1551                  */
1552                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1553 }
1554
1555 /**
1556  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1557  *  @hw: pointer to the HW structure
1558  *
1559  *  Verifies that the EEPROM has completed the update.  After updating the
1560  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1561  *  the checksum fix is not implemented, we need to set the bit and update
1562  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1563  *  we need to return bad checksum.
1564  **/
1565 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1566 {
1567         struct e1000_nvm_info *nvm = &hw->nvm;
1568         s32 ret_val;
1569         u16 data;
1570
1571         if (nvm->type != e1000_nvm_flash_hw)
1572                 return 0;
1573
1574         /*
1575          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1576          * 10h-12h.  Checksum may need to be fixed.
1577          */
1578         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1579         if (ret_val)
1580                 return ret_val;
1581
1582         if (!(data & 0x10)) {
1583                 /*
1584                  * Read 0x23 and check bit 15.  This bit is a 1
1585                  * when the checksum has already been fixed.  If
1586                  * the checksum is still wrong and this bit is a
1587                  * 1, we need to return bad checksum.  Otherwise,
1588                  * we need to set this bit to a 1 and update the
1589                  * checksum.
1590                  */
1591                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1592                 if (ret_val)
1593                         return ret_val;
1594
1595                 if (!(data & 0x8000)) {
1596                         data |= 0x8000;
1597                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1598                         if (ret_val)
1599                                 return ret_val;
1600                         ret_val = e1000e_update_nvm_checksum(hw);
1601                 }
1602         }
1603
1604         return 0;
1605 }
1606
1607 /**
1608  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1609  *  @hw: pointer to the HW structure
1610  *
1611  *  Clears the hardware counters by reading the counter registers.
1612  **/
1613 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1614 {
1615         u32 temp;
1616
1617         e1000e_clear_hw_cntrs_base(hw);
1618
1619         temp = er32(PRC64);
1620         temp = er32(PRC127);
1621         temp = er32(PRC255);
1622         temp = er32(PRC511);
1623         temp = er32(PRC1023);
1624         temp = er32(PRC1522);
1625         temp = er32(PTC64);
1626         temp = er32(PTC127);
1627         temp = er32(PTC255);
1628         temp = er32(PTC511);
1629         temp = er32(PTC1023);
1630         temp = er32(PTC1522);
1631
1632         temp = er32(ALGNERRC);
1633         temp = er32(RXERRC);
1634         temp = er32(TNCRS);
1635         temp = er32(CEXTERR);
1636         temp = er32(TSCTC);
1637         temp = er32(TSCTFC);
1638
1639         temp = er32(MGTPRC);
1640         temp = er32(MGTPDC);
1641         temp = er32(MGTPTC);
1642
1643         temp = er32(IAC);
1644         temp = er32(ICRXOC);
1645
1646         temp = er32(ICRXPTC);
1647         temp = er32(ICRXATC);
1648         temp = er32(ICTXPTC);
1649         temp = er32(ICTXATC);
1650         temp = er32(ICTXQEC);
1651         temp = er32(ICTXQMTC);
1652         temp = er32(ICRXDMTC);
1653 }
1654
1655 static struct e1000_mac_operations e82571_mac_ops = {
1656         /* .check_mng_mode: mac type dependent */
1657         /* .check_for_link: media type dependent */
1658         .id_led_init            = e1000e_id_led_init,
1659         .cleanup_led            = e1000e_cleanup_led_generic,
1660         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1661         .get_bus_info           = e1000e_get_bus_info_pcie,
1662         /* .get_link_up_info: media type dependent */
1663         /* .led_on: mac type dependent */
1664         .led_off                = e1000e_led_off_generic,
1665         .update_mc_addr_list    = e1000_update_mc_addr_list_82571,
1666         .reset_hw               = e1000_reset_hw_82571,
1667         .init_hw                = e1000_init_hw_82571,
1668         .setup_link             = e1000_setup_link_82571,
1669         /* .setup_physical_interface: media type dependent */
1670         .setup_led              = e1000e_setup_led_generic,
1671 };
1672
1673 static struct e1000_phy_operations e82_phy_ops_igp = {
1674         .acquire                = e1000_get_hw_semaphore_82571,
1675         .check_reset_block      = e1000e_check_reset_block_generic,
1676         .commit                 = NULL,
1677         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1678         .get_cfg_done           = e1000_get_cfg_done_82571,
1679         .get_cable_length       = e1000e_get_cable_length_igp_2,
1680         .get_info               = e1000e_get_phy_info_igp,
1681         .read_reg               = e1000e_read_phy_reg_igp,
1682         .release                = e1000_put_hw_semaphore_82571,
1683         .reset                  = e1000e_phy_hw_reset_generic,
1684         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1685         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1686         .write_reg              = e1000e_write_phy_reg_igp,
1687         .cfg_on_link_up         = NULL,
1688 };
1689
1690 static struct e1000_phy_operations e82_phy_ops_m88 = {
1691         .acquire                = e1000_get_hw_semaphore_82571,
1692         .check_reset_block      = e1000e_check_reset_block_generic,
1693         .commit                 = e1000e_phy_sw_reset,
1694         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1695         .get_cfg_done           = e1000e_get_cfg_done,
1696         .get_cable_length       = e1000e_get_cable_length_m88,
1697         .get_info               = e1000e_get_phy_info_m88,
1698         .read_reg               = e1000e_read_phy_reg_m88,
1699         .release                = e1000_put_hw_semaphore_82571,
1700         .reset                  = e1000e_phy_hw_reset_generic,
1701         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1702         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1703         .write_reg              = e1000e_write_phy_reg_m88,
1704         .cfg_on_link_up         = NULL,
1705 };
1706
1707 static struct e1000_phy_operations e82_phy_ops_bm = {
1708         .acquire                = e1000_get_hw_semaphore_82571,
1709         .check_reset_block      = e1000e_check_reset_block_generic,
1710         .commit                 = e1000e_phy_sw_reset,
1711         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1712         .get_cfg_done           = e1000e_get_cfg_done,
1713         .get_cable_length       = e1000e_get_cable_length_m88,
1714         .get_info               = e1000e_get_phy_info_m88,
1715         .read_reg               = e1000e_read_phy_reg_bm2,
1716         .release                = e1000_put_hw_semaphore_82571,
1717         .reset                  = e1000e_phy_hw_reset_generic,
1718         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1719         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1720         .write_reg              = e1000e_write_phy_reg_bm2,
1721         .cfg_on_link_up         = NULL,
1722 };
1723
1724 static struct e1000_nvm_operations e82571_nvm_ops = {
1725         .acquire                = e1000_acquire_nvm_82571,
1726         .read                   = e1000e_read_nvm_eerd,
1727         .release                = e1000_release_nvm_82571,
1728         .update                 = e1000_update_nvm_checksum_82571,
1729         .valid_led_default      = e1000_valid_led_default_82571,
1730         .validate               = e1000_validate_nvm_checksum_82571,
1731         .write                  = e1000_write_nvm_82571,
1732 };
1733
1734 struct e1000_info e1000_82571_info = {
1735         .mac                    = e1000_82571,
1736         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1737                                   | FLAG_HAS_JUMBO_FRAMES
1738                                   | FLAG_HAS_WOL
1739                                   | FLAG_APME_IN_CTRL3
1740                                   | FLAG_RX_CSUM_ENABLED
1741                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1742                                   | FLAG_HAS_SMART_POWER_DOWN
1743                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1744                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1745                                   | FLAG_APME_CHECK_PORT_B,
1746         .pba                    = 38,
1747         .max_hw_frame_size      = DEFAULT_JUMBO,
1748         .get_variants           = e1000_get_variants_82571,
1749         .mac_ops                = &e82571_mac_ops,
1750         .phy_ops                = &e82_phy_ops_igp,
1751         .nvm_ops                = &e82571_nvm_ops,
1752 };
1753
1754 struct e1000_info e1000_82572_info = {
1755         .mac                    = e1000_82572,
1756         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1757                                   | FLAG_HAS_JUMBO_FRAMES
1758                                   | FLAG_HAS_WOL
1759                                   | FLAG_APME_IN_CTRL3
1760                                   | FLAG_RX_CSUM_ENABLED
1761                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1762                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1763         .pba                    = 38,
1764         .max_hw_frame_size      = DEFAULT_JUMBO,
1765         .get_variants           = e1000_get_variants_82571,
1766         .mac_ops                = &e82571_mac_ops,
1767         .phy_ops                = &e82_phy_ops_igp,
1768         .nvm_ops                = &e82571_nvm_ops,
1769 };
1770
1771 struct e1000_info e1000_82573_info = {
1772         .mac                    = e1000_82573,
1773         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1774                                   | FLAG_HAS_JUMBO_FRAMES
1775                                   | FLAG_HAS_WOL
1776                                   | FLAG_APME_IN_CTRL3
1777                                   | FLAG_RX_CSUM_ENABLED
1778                                   | FLAG_HAS_SMART_POWER_DOWN
1779                                   | FLAG_HAS_AMT
1780                                   | FLAG_HAS_ERT
1781                                   | FLAG_HAS_SWSM_ON_LOAD,
1782         .pba                    = 20,
1783         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1784         .get_variants           = e1000_get_variants_82571,
1785         .mac_ops                = &e82571_mac_ops,
1786         .phy_ops                = &e82_phy_ops_m88,
1787         .nvm_ops                = &e82571_nvm_ops,
1788 };
1789
1790 struct e1000_info e1000_82574_info = {
1791         .mac                    = e1000_82574,
1792         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1793                                   | FLAG_HAS_MSIX
1794                                   | FLAG_HAS_JUMBO_FRAMES
1795                                   | FLAG_HAS_WOL
1796                                   | FLAG_APME_IN_CTRL3
1797                                   | FLAG_RX_CSUM_ENABLED
1798                                   | FLAG_HAS_SMART_POWER_DOWN
1799                                   | FLAG_HAS_AMT
1800                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1801         .pba                    = 20,
1802         .max_hw_frame_size      = DEFAULT_JUMBO,
1803         .get_variants           = e1000_get_variants_82571,
1804         .mac_ops                = &e82571_mac_ops,
1805         .phy_ops                = &e82_phy_ops_bm,
1806         .nvm_ops                = &e82571_nvm_ops,
1807 };
1808
1809 struct e1000_info e1000_82583_info = {
1810         .mac                    = e1000_82583,
1811         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1812                                   | FLAG_HAS_WOL
1813                                   | FLAG_APME_IN_CTRL3
1814                                   | FLAG_RX_CSUM_ENABLED
1815                                   | FLAG_HAS_SMART_POWER_DOWN
1816                                   | FLAG_HAS_AMT
1817                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1818         .pba                    = 20,
1819         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1820         .get_variants           = e1000_get_variants_82571,
1821         .mac_ops                = &e82571_mac_ops,
1822         .phy_ops                = &e82_phy_ops_bm,
1823         .nvm_ops                = &e82571_nvm_ops,
1824 };
1825