0e8aa3441b977755ed85d2b7be2f7e718f93f674
[linux-2.6.git] / drivers / net / e1000e / 82571.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 82571EB Gigabit Ethernet Controller
31  * 82571EB Gigabit Ethernet Controller (Copper)
32  * 82571EB Gigabit Ethernet Controller (Fiber)
33  * 82571EB Dual Port Gigabit Mezzanine Adapter
34  * 82571EB Quad Port Gigabit Mezzanine Adapter
35  * 82571PT Gigabit PT Quad Port Server ExpressModule
36  * 82572EI Gigabit Ethernet Controller (Copper)
37  * 82572EI Gigabit Ethernet Controller (Fiber)
38  * 82572EI Gigabit Ethernet Controller
39  * 82573V Gigabit Ethernet Controller (Copper)
40  * 82573E Gigabit Ethernet Controller (Copper)
41  * 82573L Gigabit Ethernet Controller
42  * 82574L Gigabit Network Connection
43  * 82583V Gigabit Network Connection
44  */
45
46 #include "e1000.h"
47
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50                               (ID_LED_OFF1_ON2  <<  8) | \
51                               (ID_LED_DEF1_DEF2 <<  4) | \
52                               (ID_LED_DEF1_DEF2))
53
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
55
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
57
58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
63                                       u16 words, u16 *data);
64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
68 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
69 static s32 e1000_led_on_82574(struct e1000_hw *hw);
70 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
71
72 /**
73  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
74  *  @hw: pointer to the HW structure
75  **/
76 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
77 {
78         struct e1000_phy_info *phy = &hw->phy;
79         s32 ret_val;
80
81         if (hw->phy.media_type != e1000_media_type_copper) {
82                 phy->type = e1000_phy_none;
83                 return 0;
84         }
85
86         phy->addr                        = 1;
87         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
88         phy->reset_delay_us              = 100;
89
90         switch (hw->mac.type) {
91         case e1000_82571:
92         case e1000_82572:
93                 phy->type                = e1000_phy_igp_2;
94                 break;
95         case e1000_82573:
96                 phy->type                = e1000_phy_m88;
97                 break;
98         case e1000_82574:
99         case e1000_82583:
100                 phy->type                = e1000_phy_bm;
101                 break;
102         default:
103                 return -E1000_ERR_PHY;
104                 break;
105         }
106
107         /* This can only be done after all function pointers are setup. */
108         ret_val = e1000_get_phy_id_82571(hw);
109
110         /* Verify phy id */
111         switch (hw->mac.type) {
112         case e1000_82571:
113         case e1000_82572:
114                 if (phy->id != IGP01E1000_I_PHY_ID)
115                         return -E1000_ERR_PHY;
116                 break;
117         case e1000_82573:
118                 if (phy->id != M88E1111_I_PHY_ID)
119                         return -E1000_ERR_PHY;
120                 break;
121         case e1000_82574:
122         case e1000_82583:
123                 if (phy->id != BME1000_E_PHY_ID_R2)
124                         return -E1000_ERR_PHY;
125                 break;
126         default:
127                 return -E1000_ERR_PHY;
128                 break;
129         }
130
131         return 0;
132 }
133
134 /**
135  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
136  *  @hw: pointer to the HW structure
137  **/
138 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
139 {
140         struct e1000_nvm_info *nvm = &hw->nvm;
141         u32 eecd = er32(EECD);
142         u16 size;
143
144         nvm->opcode_bits = 8;
145         nvm->delay_usec = 1;
146         switch (nvm->override) {
147         case e1000_nvm_override_spi_large:
148                 nvm->page_size = 32;
149                 nvm->address_bits = 16;
150                 break;
151         case e1000_nvm_override_spi_small:
152                 nvm->page_size = 8;
153                 nvm->address_bits = 8;
154                 break;
155         default:
156                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
157                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
158                 break;
159         }
160
161         switch (hw->mac.type) {
162         case e1000_82573:
163         case e1000_82574:
164         case e1000_82583:
165                 if (((eecd >> 15) & 0x3) == 0x3) {
166                         nvm->type = e1000_nvm_flash_hw;
167                         nvm->word_size = 2048;
168                         /*
169                          * Autonomous Flash update bit must be cleared due
170                          * to Flash update issue.
171                          */
172                         eecd &= ~E1000_EECD_AUPDEN;
173                         ew32(EECD, eecd);
174                         break;
175                 }
176                 /* Fall Through */
177         default:
178                 nvm->type = e1000_nvm_eeprom_spi;
179                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
180                                   E1000_EECD_SIZE_EX_SHIFT);
181                 /*
182                  * Added to a constant, "size" becomes the left-shift value
183                  * for setting word_size.
184                  */
185                 size += NVM_WORD_SIZE_BASE_SHIFT;
186
187                 /* EEPROM access above 16k is unsupported */
188                 if (size > 14)
189                         size = 14;
190                 nvm->word_size  = 1 << size;
191                 break;
192         }
193
194         return 0;
195 }
196
197 /**
198  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
199  *  @hw: pointer to the HW structure
200  **/
201 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
202 {
203         struct e1000_hw *hw = &adapter->hw;
204         struct e1000_mac_info *mac = &hw->mac;
205         struct e1000_mac_operations *func = &mac->ops;
206         u32 swsm = 0;
207         u32 swsm2 = 0;
208         bool force_clear_smbi = false;
209
210         /* Set media type */
211         switch (adapter->pdev->device) {
212         case E1000_DEV_ID_82571EB_FIBER:
213         case E1000_DEV_ID_82572EI_FIBER:
214         case E1000_DEV_ID_82571EB_QUAD_FIBER:
215                 hw->phy.media_type = e1000_media_type_fiber;
216                 break;
217         case E1000_DEV_ID_82571EB_SERDES:
218         case E1000_DEV_ID_82572EI_SERDES:
219         case E1000_DEV_ID_82571EB_SERDES_DUAL:
220         case E1000_DEV_ID_82571EB_SERDES_QUAD:
221                 hw->phy.media_type = e1000_media_type_internal_serdes;
222                 break;
223         default:
224                 hw->phy.media_type = e1000_media_type_copper;
225                 break;
226         }
227
228         /* Set mta register count */
229         mac->mta_reg_count = 128;
230         /* Set rar entry count */
231         mac->rar_entry_count = E1000_RAR_ENTRIES;
232         /* Set if manageability features are enabled. */
233         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
234
235         /* check for link */
236         switch (hw->phy.media_type) {
237         case e1000_media_type_copper:
238                 func->setup_physical_interface = e1000_setup_copper_link_82571;
239                 func->check_for_link = e1000e_check_for_copper_link;
240                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
241                 break;
242         case e1000_media_type_fiber:
243                 func->setup_physical_interface =
244                         e1000_setup_fiber_serdes_link_82571;
245                 func->check_for_link = e1000e_check_for_fiber_link;
246                 func->get_link_up_info =
247                         e1000e_get_speed_and_duplex_fiber_serdes;
248                 break;
249         case e1000_media_type_internal_serdes:
250                 func->setup_physical_interface =
251                         e1000_setup_fiber_serdes_link_82571;
252                 func->check_for_link = e1000_check_for_serdes_link_82571;
253                 func->get_link_up_info =
254                         e1000e_get_speed_and_duplex_fiber_serdes;
255                 break;
256         default:
257                 return -E1000_ERR_CONFIG;
258                 break;
259         }
260
261         switch (hw->mac.type) {
262         case e1000_82574:
263         case e1000_82583:
264                 func->check_mng_mode = e1000_check_mng_mode_82574;
265                 func->led_on = e1000_led_on_82574;
266                 break;
267         default:
268                 func->check_mng_mode = e1000e_check_mng_mode_generic;
269                 func->led_on = e1000e_led_on_generic;
270                 break;
271         }
272
273         /*
274          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
275          * first NVM or PHY acess. This should be done for single-port
276          * devices, and for one port only on dual-port devices so that
277          * for those devices we can still use the SMBI lock to synchronize
278          * inter-port accesses to the PHY & NVM.
279          */
280         switch (hw->mac.type) {
281         case e1000_82571:
282         case e1000_82572:
283                 swsm2 = er32(SWSM2);
284
285                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
286                         /* Only do this for the first interface on this card */
287                         ew32(SWSM2,
288                             swsm2 | E1000_SWSM2_LOCK);
289                         force_clear_smbi = true;
290                 } else
291                         force_clear_smbi = false;
292                 break;
293         default:
294                 force_clear_smbi = true;
295                 break;
296         }
297
298         if (force_clear_smbi) {
299                 /* Make sure SWSM.SMBI is clear */
300                 swsm = er32(SWSM);
301                 if (swsm & E1000_SWSM_SMBI) {
302                         /* This bit should not be set on a first interface, and
303                          * indicates that the bootagent or EFI code has
304                          * improperly left this bit enabled
305                          */
306                         e_dbg("Please update your 82571 Bootagent\n");
307                 }
308                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
309         }
310
311         /*
312          * Initialze device specific counter of SMBI acquisition
313          * timeouts.
314          */
315          hw->dev_spec.e82571.smb_counter = 0;
316
317         return 0;
318 }
319
320 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
321 {
322         struct e1000_hw *hw = &adapter->hw;
323         static int global_quad_port_a; /* global port a indication */
324         struct pci_dev *pdev = adapter->pdev;
325         u16 eeprom_data = 0;
326         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
327         s32 rc;
328
329         rc = e1000_init_mac_params_82571(adapter);
330         if (rc)
331                 return rc;
332
333         rc = e1000_init_nvm_params_82571(hw);
334         if (rc)
335                 return rc;
336
337         rc = e1000_init_phy_params_82571(hw);
338         if (rc)
339                 return rc;
340
341         /* tag quad port adapters first, it's used below */
342         switch (pdev->device) {
343         case E1000_DEV_ID_82571EB_QUAD_COPPER:
344         case E1000_DEV_ID_82571EB_QUAD_FIBER:
345         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
346         case E1000_DEV_ID_82571PT_QUAD_COPPER:
347                 adapter->flags |= FLAG_IS_QUAD_PORT;
348                 /* mark the first port */
349                 if (global_quad_port_a == 0)
350                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
351                 /* Reset for multiple quad port adapters */
352                 global_quad_port_a++;
353                 if (global_quad_port_a == 4)
354                         global_quad_port_a = 0;
355                 break;
356         default:
357                 break;
358         }
359
360         switch (adapter->hw.mac.type) {
361         case e1000_82571:
362                 /* these dual ports don't have WoL on port B at all */
363                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
364                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
365                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
366                     (is_port_b))
367                         adapter->flags &= ~FLAG_HAS_WOL;
368                 /* quad ports only support WoL on port A */
369                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
370                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
371                         adapter->flags &= ~FLAG_HAS_WOL;
372                 /* Does not support WoL on any port */
373                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
374                         adapter->flags &= ~FLAG_HAS_WOL;
375                 break;
376
377         case e1000_82573:
378                 if (pdev->device == E1000_DEV_ID_82573L) {
379                         if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
380                                        &eeprom_data) < 0)
381                                 break;
382                         if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
383                                 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
384                                 adapter->max_hw_frame_size = DEFAULT_JUMBO;
385                         }
386                 }
387                 break;
388         default:
389                 break;
390         }
391
392         return 0;
393 }
394
395 /**
396  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
397  *  @hw: pointer to the HW structure
398  *
399  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
400  *  revision in the hardware structure.
401  **/
402 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
403 {
404         struct e1000_phy_info *phy = &hw->phy;
405         s32 ret_val;
406         u16 phy_id = 0;
407
408         switch (hw->mac.type) {
409         case e1000_82571:
410         case e1000_82572:
411                 /*
412                  * The 82571 firmware may still be configuring the PHY.
413                  * In this case, we cannot access the PHY until the
414                  * configuration is done.  So we explicitly set the
415                  * PHY ID.
416                  */
417                 phy->id = IGP01E1000_I_PHY_ID;
418                 break;
419         case e1000_82573:
420                 return e1000e_get_phy_id(hw);
421                 break;
422         case e1000_82574:
423         case e1000_82583:
424                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
425                 if (ret_val)
426                         return ret_val;
427
428                 phy->id = (u32)(phy_id << 16);
429                 udelay(20);
430                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
431                 if (ret_val)
432                         return ret_val;
433
434                 phy->id |= (u32)(phy_id);
435                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
436                 break;
437         default:
438                 return -E1000_ERR_PHY;
439                 break;
440         }
441
442         return 0;
443 }
444
445 /**
446  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
447  *  @hw: pointer to the HW structure
448  *
449  *  Acquire the HW semaphore to access the PHY or NVM
450  **/
451 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
452 {
453         u32 swsm;
454         s32 sw_timeout = hw->nvm.word_size + 1;
455         s32 fw_timeout = hw->nvm.word_size + 1;
456         s32 i = 0;
457
458         /*
459          * If we have timedout 3 times on trying to acquire
460          * the inter-port SMBI semaphore, there is old code
461          * operating on the other port, and it is not
462          * releasing SMBI. Modify the number of times that
463          * we try for the semaphore to interwork with this
464          * older code.
465          */
466         if (hw->dev_spec.e82571.smb_counter > 2)
467                 sw_timeout = 1;
468
469         /* Get the SW semaphore */
470         while (i < sw_timeout) {
471                 swsm = er32(SWSM);
472                 if (!(swsm & E1000_SWSM_SMBI))
473                         break;
474
475                 udelay(50);
476                 i++;
477         }
478
479         if (i == sw_timeout) {
480                 e_dbg("Driver can't access device - SMBI bit is set.\n");
481                 hw->dev_spec.e82571.smb_counter++;
482         }
483         /* Get the FW semaphore. */
484         for (i = 0; i < fw_timeout; i++) {
485                 swsm = er32(SWSM);
486                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
487
488                 /* Semaphore acquired if bit latched */
489                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
490                         break;
491
492                 udelay(50);
493         }
494
495         if (i == fw_timeout) {
496                 /* Release semaphores */
497                 e1000_put_hw_semaphore_82571(hw);
498                 e_dbg("Driver can't access the NVM\n");
499                 return -E1000_ERR_NVM;
500         }
501
502         return 0;
503 }
504
505 /**
506  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
507  *  @hw: pointer to the HW structure
508  *
509  *  Release hardware semaphore used to access the PHY or NVM
510  **/
511 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
512 {
513         u32 swsm;
514
515         swsm = er32(SWSM);
516         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
517         ew32(SWSM, swsm);
518 }
519
520 /**
521  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
522  *  @hw: pointer to the HW structure
523  *
524  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
525  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
526  *  for EEPROM access grant bit.  If the access grant bit is not set, release
527  *  hardware semaphore.
528  **/
529 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
530 {
531         s32 ret_val;
532
533         ret_val = e1000_get_hw_semaphore_82571(hw);
534         if (ret_val)
535                 return ret_val;
536
537         switch (hw->mac.type) {
538         case e1000_82573:
539         case e1000_82574:
540         case e1000_82583:
541                 break;
542         default:
543                 ret_val = e1000e_acquire_nvm(hw);
544                 break;
545         }
546
547         if (ret_val)
548                 e1000_put_hw_semaphore_82571(hw);
549
550         return ret_val;
551 }
552
553 /**
554  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
555  *  @hw: pointer to the HW structure
556  *
557  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
558  **/
559 static void e1000_release_nvm_82571(struct e1000_hw *hw)
560 {
561         e1000e_release_nvm(hw);
562         e1000_put_hw_semaphore_82571(hw);
563 }
564
565 /**
566  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
567  *  @hw: pointer to the HW structure
568  *  @offset: offset within the EEPROM to be written to
569  *  @words: number of words to write
570  *  @data: 16 bit word(s) to be written to the EEPROM
571  *
572  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
573  *
574  *  If e1000e_update_nvm_checksum is not called after this function, the
575  *  EEPROM will most likely contain an invalid checksum.
576  **/
577 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
578                                  u16 *data)
579 {
580         s32 ret_val;
581
582         switch (hw->mac.type) {
583         case e1000_82573:
584         case e1000_82574:
585         case e1000_82583:
586                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
587                 break;
588         case e1000_82571:
589         case e1000_82572:
590                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
591                 break;
592         default:
593                 ret_val = -E1000_ERR_NVM;
594                 break;
595         }
596
597         return ret_val;
598 }
599
600 /**
601  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
602  *  @hw: pointer to the HW structure
603  *
604  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
605  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
606  *  value to the EEPROM.
607  **/
608 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
609 {
610         u32 eecd;
611         s32 ret_val;
612         u16 i;
613
614         ret_val = e1000e_update_nvm_checksum_generic(hw);
615         if (ret_val)
616                 return ret_val;
617
618         /*
619          * If our nvm is an EEPROM, then we're done
620          * otherwise, commit the checksum to the flash NVM.
621          */
622         if (hw->nvm.type != e1000_nvm_flash_hw)
623                 return ret_val;
624
625         /* Check for pending operations. */
626         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
627                 msleep(1);
628                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
629                         break;
630         }
631
632         if (i == E1000_FLASH_UPDATES)
633                 return -E1000_ERR_NVM;
634
635         /* Reset the firmware if using STM opcode. */
636         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
637                 /*
638                  * The enabling of and the actual reset must be done
639                  * in two write cycles.
640                  */
641                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
642                 e1e_flush();
643                 ew32(HICR, E1000_HICR_FW_RESET);
644         }
645
646         /* Commit the write to flash */
647         eecd = er32(EECD) | E1000_EECD_FLUPD;
648         ew32(EECD, eecd);
649
650         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
651                 msleep(1);
652                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
653                         break;
654         }
655
656         if (i == E1000_FLASH_UPDATES)
657                 return -E1000_ERR_NVM;
658
659         return 0;
660 }
661
662 /**
663  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
664  *  @hw: pointer to the HW structure
665  *
666  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
667  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
668  **/
669 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
670 {
671         if (hw->nvm.type == e1000_nvm_flash_hw)
672                 e1000_fix_nvm_checksum_82571(hw);
673
674         return e1000e_validate_nvm_checksum_generic(hw);
675 }
676
677 /**
678  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
679  *  @hw: pointer to the HW structure
680  *  @offset: offset within the EEPROM to be written to
681  *  @words: number of words to write
682  *  @data: 16 bit word(s) to be written to the EEPROM
683  *
684  *  After checking for invalid values, poll the EEPROM to ensure the previous
685  *  command has completed before trying to write the next word.  After write
686  *  poll for completion.
687  *
688  *  If e1000e_update_nvm_checksum is not called after this function, the
689  *  EEPROM will most likely contain an invalid checksum.
690  **/
691 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
692                                       u16 words, u16 *data)
693 {
694         struct e1000_nvm_info *nvm = &hw->nvm;
695         u32 i;
696         u32 eewr = 0;
697         s32 ret_val = 0;
698
699         /*
700          * A check for invalid values:  offset too large, too many words,
701          * and not enough words.
702          */
703         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
704             (words == 0)) {
705                 e_dbg("nvm parameter(s) out of bounds\n");
706                 return -E1000_ERR_NVM;
707         }
708
709         for (i = 0; i < words; i++) {
710                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
711                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
712                        E1000_NVM_RW_REG_START;
713
714                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
715                 if (ret_val)
716                         break;
717
718                 ew32(EEWR, eewr);
719
720                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
721                 if (ret_val)
722                         break;
723         }
724
725         return ret_val;
726 }
727
728 /**
729  *  e1000_get_cfg_done_82571 - Poll for configuration done
730  *  @hw: pointer to the HW structure
731  *
732  *  Reads the management control register for the config done bit to be set.
733  **/
734 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
735 {
736         s32 timeout = PHY_CFG_TIMEOUT;
737
738         while (timeout) {
739                 if (er32(EEMNGCTL) &
740                     E1000_NVM_CFG_DONE_PORT_0)
741                         break;
742                 msleep(1);
743                 timeout--;
744         }
745         if (!timeout) {
746                 e_dbg("MNG configuration cycle has not completed.\n");
747                 return -E1000_ERR_RESET;
748         }
749
750         return 0;
751 }
752
753 /**
754  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
755  *  @hw: pointer to the HW structure
756  *  @active: TRUE to enable LPLU, FALSE to disable
757  *
758  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
759  *  this function also disables smart speed and vice versa.  LPLU will not be
760  *  activated unless the device autonegotiation advertisement meets standards
761  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
762  *  pointer entry point only called by PHY setup routines.
763  **/
764 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
765 {
766         struct e1000_phy_info *phy = &hw->phy;
767         s32 ret_val;
768         u16 data;
769
770         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
771         if (ret_val)
772                 return ret_val;
773
774         if (active) {
775                 data |= IGP02E1000_PM_D0_LPLU;
776                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
777                 if (ret_val)
778                         return ret_val;
779
780                 /* When LPLU is enabled, we should disable SmartSpeed */
781                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
782                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
783                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
784                 if (ret_val)
785                         return ret_val;
786         } else {
787                 data &= ~IGP02E1000_PM_D0_LPLU;
788                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
789                 /*
790                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
791                  * during Dx states where the power conservation is most
792                  * important.  During driver activity we should enable
793                  * SmartSpeed, so performance is maintained.
794                  */
795                 if (phy->smart_speed == e1000_smart_speed_on) {
796                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
797                                            &data);
798                         if (ret_val)
799                                 return ret_val;
800
801                         data |= IGP01E1000_PSCFR_SMART_SPEED;
802                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
803                                            data);
804                         if (ret_val)
805                                 return ret_val;
806                 } else if (phy->smart_speed == e1000_smart_speed_off) {
807                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
808                                            &data);
809                         if (ret_val)
810                                 return ret_val;
811
812                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
813                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
814                                            data);
815                         if (ret_val)
816                                 return ret_val;
817                 }
818         }
819
820         return 0;
821 }
822
823 /**
824  *  e1000_reset_hw_82571 - Reset hardware
825  *  @hw: pointer to the HW structure
826  *
827  *  This resets the hardware into a known state.
828  **/
829 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
830 {
831         u32 ctrl;
832         u32 extcnf_ctrl;
833         u32 ctrl_ext;
834         u32 icr;
835         s32 ret_val;
836         u16 i = 0;
837
838         /*
839          * Prevent the PCI-E bus from sticking if there is no TLP connection
840          * on the last TLP read/write transaction when MAC is reset.
841          */
842         ret_val = e1000e_disable_pcie_master(hw);
843         if (ret_val)
844                 e_dbg("PCI-E Master disable polling has failed.\n");
845
846         e_dbg("Masking off all interrupts\n");
847         ew32(IMC, 0xffffffff);
848
849         ew32(RCTL, 0);
850         ew32(TCTL, E1000_TCTL_PSP);
851         e1e_flush();
852
853         msleep(10);
854
855         /*
856          * Must acquire the MDIO ownership before MAC reset.
857          * Ownership defaults to firmware after a reset.
858          */
859         switch (hw->mac.type) {
860         case e1000_82573:
861         case e1000_82574:
862         case e1000_82583:
863                 extcnf_ctrl = er32(EXTCNF_CTRL);
864                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
865
866                 do {
867                         ew32(EXTCNF_CTRL, extcnf_ctrl);
868                         extcnf_ctrl = er32(EXTCNF_CTRL);
869
870                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
871                                 break;
872
873                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
874
875                         msleep(2);
876                         i++;
877                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
878                 break;
879         default:
880                 break;
881         }
882
883         ctrl = er32(CTRL);
884
885         e_dbg("Issuing a global reset to MAC\n");
886         ew32(CTRL, ctrl | E1000_CTRL_RST);
887
888         if (hw->nvm.type == e1000_nvm_flash_hw) {
889                 udelay(10);
890                 ctrl_ext = er32(CTRL_EXT);
891                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
892                 ew32(CTRL_EXT, ctrl_ext);
893                 e1e_flush();
894         }
895
896         ret_val = e1000e_get_auto_rd_done(hw);
897         if (ret_val)
898                 /* We don't want to continue accessing MAC registers. */
899                 return ret_val;
900
901         /*
902          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
903          * Need to wait for Phy configuration completion before accessing
904          * NVM and Phy.
905          */
906
907         switch (hw->mac.type) {
908         case e1000_82573:
909         case e1000_82574:
910         case e1000_82583:
911                 msleep(25);
912                 break;
913         default:
914                 break;
915         }
916
917         /* Clear any pending interrupt events. */
918         ew32(IMC, 0xffffffff);
919         icr = er32(ICR);
920
921         if (hw->mac.type == e1000_82571 &&
922                 hw->dev_spec.e82571.alt_mac_addr_is_present)
923                         e1000e_set_laa_state_82571(hw, true);
924
925         /* Reinitialize the 82571 serdes link state machine */
926         if (hw->phy.media_type == e1000_media_type_internal_serdes)
927                 hw->mac.serdes_link_state = e1000_serdes_link_down;
928
929         return 0;
930 }
931
932 /**
933  *  e1000_init_hw_82571 - Initialize hardware
934  *  @hw: pointer to the HW structure
935  *
936  *  This inits the hardware readying it for operation.
937  **/
938 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
939 {
940         struct e1000_mac_info *mac = &hw->mac;
941         u32 reg_data;
942         s32 ret_val;
943         u16 i;
944         u16 rar_count = mac->rar_entry_count;
945
946         e1000_initialize_hw_bits_82571(hw);
947
948         /* Initialize identification LED */
949         ret_val = e1000e_id_led_init(hw);
950         if (ret_val) {
951                 e_dbg("Error initializing identification LED\n");
952                 return ret_val;
953         }
954
955         /* Disabling VLAN filtering */
956         e_dbg("Initializing the IEEE VLAN\n");
957         e1000e_clear_vfta(hw);
958
959         /* Setup the receive address. */
960         /*
961          * If, however, a locally administered address was assigned to the
962          * 82571, we must reserve a RAR for it to work around an issue where
963          * resetting one port will reload the MAC on the other port.
964          */
965         if (e1000e_get_laa_state_82571(hw))
966                 rar_count--;
967         e1000e_init_rx_addrs(hw, rar_count);
968
969         /* Zero out the Multicast HASH table */
970         e_dbg("Zeroing the MTA\n");
971         for (i = 0; i < mac->mta_reg_count; i++)
972                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
973
974         /* Setup link and flow control */
975         ret_val = e1000_setup_link_82571(hw);
976
977         /* Set the transmit descriptor write-back policy */
978         reg_data = er32(TXDCTL(0));
979         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
980                    E1000_TXDCTL_FULL_TX_DESC_WB |
981                    E1000_TXDCTL_COUNT_DESC;
982         ew32(TXDCTL(0), reg_data);
983
984         /* ...for both queues. */
985         switch (mac->type) {
986         case e1000_82573:
987         case e1000_82574:
988         case e1000_82583:
989                 e1000e_enable_tx_pkt_filtering(hw);
990                 reg_data = er32(GCR);
991                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
992                 ew32(GCR, reg_data);
993                 break;
994         default:
995                 reg_data = er32(TXDCTL(1));
996                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
997                            E1000_TXDCTL_FULL_TX_DESC_WB |
998                            E1000_TXDCTL_COUNT_DESC;
999                 ew32(TXDCTL(1), reg_data);
1000                 break;
1001         }
1002
1003         /*
1004          * Clear all of the statistics registers (clear on read).  It is
1005          * important that we do this after we have tried to establish link
1006          * because the symbol error count will increment wildly if there
1007          * is no link.
1008          */
1009         e1000_clear_hw_cntrs_82571(hw);
1010
1011         return ret_val;
1012 }
1013
1014 /**
1015  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1016  *  @hw: pointer to the HW structure
1017  *
1018  *  Initializes required hardware-dependent bits needed for normal operation.
1019  **/
1020 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1021 {
1022         u32 reg;
1023
1024         /* Transmit Descriptor Control 0 */
1025         reg = er32(TXDCTL(0));
1026         reg |= (1 << 22);
1027         ew32(TXDCTL(0), reg);
1028
1029         /* Transmit Descriptor Control 1 */
1030         reg = er32(TXDCTL(1));
1031         reg |= (1 << 22);
1032         ew32(TXDCTL(1), reg);
1033
1034         /* Transmit Arbitration Control 0 */
1035         reg = er32(TARC(0));
1036         reg &= ~(0xF << 27); /* 30:27 */
1037         switch (hw->mac.type) {
1038         case e1000_82571:
1039         case e1000_82572:
1040                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1041                 break;
1042         default:
1043                 break;
1044         }
1045         ew32(TARC(0), reg);
1046
1047         /* Transmit Arbitration Control 1 */
1048         reg = er32(TARC(1));
1049         switch (hw->mac.type) {
1050         case e1000_82571:
1051         case e1000_82572:
1052                 reg &= ~((1 << 29) | (1 << 30));
1053                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1054                 if (er32(TCTL) & E1000_TCTL_MULR)
1055                         reg &= ~(1 << 28);
1056                 else
1057                         reg |= (1 << 28);
1058                 ew32(TARC(1), reg);
1059                 break;
1060         default:
1061                 break;
1062         }
1063
1064         /* Device Control */
1065         switch (hw->mac.type) {
1066         case e1000_82573:
1067         case e1000_82574:
1068         case e1000_82583:
1069                 reg = er32(CTRL);
1070                 reg &= ~(1 << 29);
1071                 ew32(CTRL, reg);
1072                 break;
1073         default:
1074                 break;
1075         }
1076
1077         /* Extended Device Control */
1078         switch (hw->mac.type) {
1079         case e1000_82573:
1080         case e1000_82574:
1081         case e1000_82583:
1082                 reg = er32(CTRL_EXT);
1083                 reg &= ~(1 << 23);
1084                 reg |= (1 << 22);
1085                 ew32(CTRL_EXT, reg);
1086                 break;
1087         default:
1088                 break;
1089         }
1090
1091         if (hw->mac.type == e1000_82571) {
1092                 reg = er32(PBA_ECC);
1093                 reg |= E1000_PBA_ECC_CORR_EN;
1094                 ew32(PBA_ECC, reg);
1095         }
1096         /*
1097          * Workaround for hardware errata.
1098          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1099          */
1100
1101         if ((hw->mac.type == e1000_82571) ||
1102            (hw->mac.type == e1000_82572)) {
1103                 reg = er32(CTRL_EXT);
1104                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1105                 ew32(CTRL_EXT, reg);
1106         }
1107
1108
1109         /* PCI-Ex Control Registers */
1110         switch (hw->mac.type) {
1111         case e1000_82574:
1112         case e1000_82583:
1113                 reg = er32(GCR);
1114                 reg |= (1 << 22);
1115                 ew32(GCR, reg);
1116
1117                 /*
1118                  * Workaround for hardware errata.
1119                  * apply workaround for hardware errata documented in errata
1120                  * docs Fixes issue where some error prone or unreliable PCIe
1121                  * completions are occurring, particularly with ASPM enabled.
1122                  * Without fix, issue can cause tx timeouts.
1123                  */
1124                 reg = er32(GCR2);
1125                 reg |= 1;
1126                 ew32(GCR2, reg);
1127                 break;
1128         default:
1129                 break;
1130         }
1131
1132         return;
1133 }
1134
1135 /**
1136  *  e1000e_clear_vfta - Clear VLAN filter table
1137  *  @hw: pointer to the HW structure
1138  *
1139  *  Clears the register array which contains the VLAN filter table by
1140  *  setting all the values to 0.
1141  **/
1142 void e1000e_clear_vfta(struct e1000_hw *hw)
1143 {
1144         u32 offset;
1145         u32 vfta_value = 0;
1146         u32 vfta_offset = 0;
1147         u32 vfta_bit_in_reg = 0;
1148
1149         switch (hw->mac.type) {
1150         case e1000_82573:
1151         case e1000_82574:
1152         case e1000_82583:
1153                 if (hw->mng_cookie.vlan_id != 0) {
1154                         /*
1155                          * The VFTA is a 4096b bit-field, each identifying
1156                          * a single VLAN ID.  The following operations
1157                          * determine which 32b entry (i.e. offset) into the
1158                          * array we want to set the VLAN ID (i.e. bit) of
1159                          * the manageability unit.
1160                          */
1161                         vfta_offset = (hw->mng_cookie.vlan_id >>
1162                                        E1000_VFTA_ENTRY_SHIFT) &
1163                                       E1000_VFTA_ENTRY_MASK;
1164                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1165                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1166                 }
1167                 break;
1168         default:
1169                 break;
1170         }
1171         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1172                 /*
1173                  * If the offset we want to clear is the same offset of the
1174                  * manageability VLAN ID, then clear all bits except that of
1175                  * the manageability unit.
1176                  */
1177                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1178                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1179                 e1e_flush();
1180         }
1181 }
1182
1183 /**
1184  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1185  *  @hw: pointer to the HW structure
1186  *
1187  *  Reads the NVM Initialization Control Word 2 and returns true
1188  *  (>0) if any manageability is enabled, else false (0).
1189  **/
1190 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1191 {
1192         u16 data;
1193
1194         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1195         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1196 }
1197
1198 /**
1199  *  e1000_led_on_82574 - Turn LED on
1200  *  @hw: pointer to the HW structure
1201  *
1202  *  Turn LED on.
1203  **/
1204 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1205 {
1206         u32 ctrl;
1207         u32 i;
1208
1209         ctrl = hw->mac.ledctl_mode2;
1210         if (!(E1000_STATUS_LU & er32(STATUS))) {
1211                 /*
1212                  * If no link, then turn LED on by setting the invert bit
1213                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1214                  */
1215                 for (i = 0; i < 4; i++)
1216                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1217                             E1000_LEDCTL_MODE_LED_ON)
1218                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1219         }
1220         ew32(LEDCTL, ctrl);
1221
1222         return 0;
1223 }
1224
1225 /**
1226  *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
1227  *  @hw: pointer to the HW structure
1228  *  @mc_addr_list: array of multicast addresses to program
1229  *  @mc_addr_count: number of multicast addresses to program
1230  *  @rar_used_count: the first RAR register free to program
1231  *  @rar_count: total number of supported Receive Address Registers
1232  *
1233  *  Updates the Receive Address Registers and Multicast Table Array.
1234  *  The caller must have a packed mc_addr_list of multicast addresses.
1235  *  The parameter rar_count will usually be hw->mac.rar_entry_count
1236  *  unless there are workarounds that change this.
1237  **/
1238 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1239                                             u8 *mc_addr_list,
1240                                             u32 mc_addr_count,
1241                                             u32 rar_used_count,
1242                                             u32 rar_count)
1243 {
1244         if (e1000e_get_laa_state_82571(hw))
1245                 rar_count--;
1246
1247         e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1248                                            rar_used_count, rar_count);
1249 }
1250
1251 /**
1252  *  e1000_setup_link_82571 - Setup flow control and link settings
1253  *  @hw: pointer to the HW structure
1254  *
1255  *  Determines which flow control settings to use, then configures flow
1256  *  control.  Calls the appropriate media-specific link configuration
1257  *  function.  Assuming the adapter has a valid link partner, a valid link
1258  *  should be established.  Assumes the hardware has previously been reset
1259  *  and the transmitter and receiver are not enabled.
1260  **/
1261 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1262 {
1263         /*
1264          * 82573 does not have a word in the NVM to determine
1265          * the default flow control setting, so we explicitly
1266          * set it to full.
1267          */
1268         switch (hw->mac.type) {
1269         case e1000_82573:
1270         case e1000_82574:
1271         case e1000_82583:
1272                 if (hw->fc.requested_mode == e1000_fc_default)
1273                         hw->fc.requested_mode = e1000_fc_full;
1274                 break;
1275         default:
1276                 break;
1277         }
1278
1279         return e1000e_setup_link(hw);
1280 }
1281
1282 /**
1283  *  e1000_setup_copper_link_82571 - Configure copper link settings
1284  *  @hw: pointer to the HW structure
1285  *
1286  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1287  *  for link, once link is established calls to configure collision distance
1288  *  and flow control are called.
1289  **/
1290 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1291 {
1292         u32 ctrl;
1293         u32 led_ctrl;
1294         s32 ret_val;
1295
1296         ctrl = er32(CTRL);
1297         ctrl |= E1000_CTRL_SLU;
1298         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1299         ew32(CTRL, ctrl);
1300
1301         switch (hw->phy.type) {
1302         case e1000_phy_m88:
1303         case e1000_phy_bm:
1304                 ret_val = e1000e_copper_link_setup_m88(hw);
1305                 break;
1306         case e1000_phy_igp_2:
1307                 ret_val = e1000e_copper_link_setup_igp(hw);
1308                 /* Setup activity LED */
1309                 led_ctrl = er32(LEDCTL);
1310                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1311                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1312                 ew32(LEDCTL, led_ctrl);
1313                 break;
1314         default:
1315                 return -E1000_ERR_PHY;
1316                 break;
1317         }
1318
1319         if (ret_val)
1320                 return ret_val;
1321
1322         ret_val = e1000e_setup_copper_link(hw);
1323
1324         return ret_val;
1325 }
1326
1327 /**
1328  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1329  *  @hw: pointer to the HW structure
1330  *
1331  *  Configures collision distance and flow control for fiber and serdes links.
1332  *  Upon successful setup, poll for link.
1333  **/
1334 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1335 {
1336         switch (hw->mac.type) {
1337         case e1000_82571:
1338         case e1000_82572:
1339                 /*
1340                  * If SerDes loopback mode is entered, there is no form
1341                  * of reset to take the adapter out of that mode.  So we
1342                  * have to explicitly take the adapter out of loopback
1343                  * mode.  This prevents drivers from twiddling their thumbs
1344                  * if another tool failed to take it out of loopback mode.
1345                  */
1346                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1347                 break;
1348         default:
1349                 break;
1350         }
1351
1352         return e1000e_setup_fiber_serdes_link(hw);
1353 }
1354
1355 /**
1356  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1357  *  @hw: pointer to the HW structure
1358  *
1359  *  Checks for link up on the hardware.  If link is not up and we have
1360  *  a signal, then we need to force link up.
1361  **/
1362 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1363 {
1364         struct e1000_mac_info *mac = &hw->mac;
1365         u32 rxcw;
1366         u32 ctrl;
1367         u32 status;
1368         s32 ret_val = 0;
1369
1370         ctrl = er32(CTRL);
1371         status = er32(STATUS);
1372         rxcw = er32(RXCW);
1373
1374         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1375
1376                 /* Receiver is synchronized with no invalid bits.  */
1377                 switch (mac->serdes_link_state) {
1378                 case e1000_serdes_link_autoneg_complete:
1379                         if (!(status & E1000_STATUS_LU)) {
1380                                 /*
1381                                  * We have lost link, retry autoneg before
1382                                  * reporting link failure
1383                                  */
1384                                 mac->serdes_link_state =
1385                                     e1000_serdes_link_autoneg_progress;
1386                                 e_dbg("AN_UP     -> AN_PROG\n");
1387                         }
1388                 break;
1389
1390                 case e1000_serdes_link_forced_up:
1391                         /*
1392                          * If we are receiving /C/ ordered sets, re-enable
1393                          * auto-negotiation in the TXCW register and disable
1394                          * forced link in the Device Control register in an
1395                          * attempt to auto-negotiate with our link partner.
1396                          */
1397                         if (rxcw & E1000_RXCW_C) {
1398                                 /* Enable autoneg, and unforce link up */
1399                                 ew32(TXCW, mac->txcw);
1400                                 ew32(CTRL,
1401                                     (ctrl & ~E1000_CTRL_SLU));
1402                                 mac->serdes_link_state =
1403                                     e1000_serdes_link_autoneg_progress;
1404                                 e_dbg("FORCED_UP -> AN_PROG\n");
1405                         }
1406                         break;
1407
1408                 case e1000_serdes_link_autoneg_progress:
1409                         /*
1410                          * If the LU bit is set in the STATUS register,
1411                          * autoneg has completed sucessfully. If not,
1412                          * try foring the link because the far end may be
1413                          * available but not capable of autonegotiation.
1414                          */
1415                         if (status & E1000_STATUS_LU)  {
1416                                 mac->serdes_link_state =
1417                                     e1000_serdes_link_autoneg_complete;
1418                                 e_dbg("AN_PROG   -> AN_UP\n");
1419                         } else {
1420                                 /*
1421                                  * Disable autoneg, force link up and
1422                                  * full duplex, and change state to forced
1423                                  */
1424                                 ew32(TXCW,
1425                                     (mac->txcw & ~E1000_TXCW_ANE));
1426                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1427                                 ew32(CTRL, ctrl);
1428
1429                                 /* Configure Flow Control after link up. */
1430                                 ret_val =
1431                                     e1000e_config_fc_after_link_up(hw);
1432                                 if (ret_val) {
1433                                         e_dbg("Error config flow control\n");
1434                                         break;
1435                                 }
1436                                 mac->serdes_link_state =
1437                                     e1000_serdes_link_forced_up;
1438                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1439                         }
1440                         mac->serdes_has_link = true;
1441                         break;
1442
1443                 case e1000_serdes_link_down:
1444                 default:
1445                         /* The link was down but the receiver has now gained
1446                          * valid sync, so lets see if we can bring the link
1447                          * up. */
1448                         ew32(TXCW, mac->txcw);
1449                         ew32(CTRL,
1450                             (ctrl & ~E1000_CTRL_SLU));
1451                         mac->serdes_link_state =
1452                             e1000_serdes_link_autoneg_progress;
1453                         e_dbg("DOWN      -> AN_PROG\n");
1454                         break;
1455                 }
1456         } else {
1457                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1458                         mac->serdes_has_link = false;
1459                         mac->serdes_link_state = e1000_serdes_link_down;
1460                         e_dbg("ANYSTATE  -> DOWN\n");
1461                 } else {
1462                         /*
1463                          * We have sync, and can tolerate one
1464                          * invalid (IV) codeword before declaring
1465                          * link down, so reread to look again
1466                          */
1467                         udelay(10);
1468                         rxcw = er32(RXCW);
1469                         if (rxcw & E1000_RXCW_IV) {
1470                                 mac->serdes_link_state = e1000_serdes_link_down;
1471                                 mac->serdes_has_link = false;
1472                                 e_dbg("ANYSTATE  -> DOWN\n");
1473                         }
1474                 }
1475         }
1476
1477         return ret_val;
1478 }
1479
1480 /**
1481  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1482  *  @hw: pointer to the HW structure
1483  *  @data: pointer to the NVM (EEPROM)
1484  *
1485  *  Read the EEPROM for the current default LED configuration.  If the
1486  *  LED configuration is not valid, set to a valid LED configuration.
1487  **/
1488 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1489 {
1490         s32 ret_val;
1491
1492         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1493         if (ret_val) {
1494                 e_dbg("NVM Read Error\n");
1495                 return ret_val;
1496         }
1497
1498         switch (hw->mac.type) {
1499         case e1000_82573:
1500         case e1000_82574:
1501         case e1000_82583:
1502                 if (*data == ID_LED_RESERVED_F746)
1503                         *data = ID_LED_DEFAULT_82573;
1504                 break;
1505         default:
1506                 if (*data == ID_LED_RESERVED_0000 ||
1507                     *data == ID_LED_RESERVED_FFFF)
1508                         *data = ID_LED_DEFAULT;
1509                 break;
1510         }
1511
1512         return 0;
1513 }
1514
1515 /**
1516  *  e1000e_get_laa_state_82571 - Get locally administered address state
1517  *  @hw: pointer to the HW structure
1518  *
1519  *  Retrieve and return the current locally administered address state.
1520  **/
1521 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1522 {
1523         if (hw->mac.type != e1000_82571)
1524                 return 0;
1525
1526         return hw->dev_spec.e82571.laa_is_present;
1527 }
1528
1529 /**
1530  *  e1000e_set_laa_state_82571 - Set locally administered address state
1531  *  @hw: pointer to the HW structure
1532  *  @state: enable/disable locally administered address
1533  *
1534  *  Enable/Disable the current locally administers address state.
1535  **/
1536 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1537 {
1538         if (hw->mac.type != e1000_82571)
1539                 return;
1540
1541         hw->dev_spec.e82571.laa_is_present = state;
1542
1543         /* If workaround is activated... */
1544         if (state)
1545                 /*
1546                  * Hold a copy of the LAA in RAR[14] This is done so that
1547                  * between the time RAR[0] gets clobbered and the time it
1548                  * gets fixed, the actual LAA is in one of the RARs and no
1549                  * incoming packets directed to this port are dropped.
1550                  * Eventually the LAA will be in RAR[0] and RAR[14].
1551                  */
1552                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1553 }
1554
1555 /**
1556  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1557  *  @hw: pointer to the HW structure
1558  *
1559  *  Verifies that the EEPROM has completed the update.  After updating the
1560  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1561  *  the checksum fix is not implemented, we need to set the bit and update
1562  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1563  *  we need to return bad checksum.
1564  **/
1565 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1566 {
1567         struct e1000_nvm_info *nvm = &hw->nvm;
1568         s32 ret_val;
1569         u16 data;
1570
1571         if (nvm->type != e1000_nvm_flash_hw)
1572                 return 0;
1573
1574         /*
1575          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1576          * 10h-12h.  Checksum may need to be fixed.
1577          */
1578         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1579         if (ret_val)
1580                 return ret_val;
1581
1582         if (!(data & 0x10)) {
1583                 /*
1584                  * Read 0x23 and check bit 15.  This bit is a 1
1585                  * when the checksum has already been fixed.  If
1586                  * the checksum is still wrong and this bit is a
1587                  * 1, we need to return bad checksum.  Otherwise,
1588                  * we need to set this bit to a 1 and update the
1589                  * checksum.
1590                  */
1591                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1592                 if (ret_val)
1593                         return ret_val;
1594
1595                 if (!(data & 0x8000)) {
1596                         data |= 0x8000;
1597                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1598                         if (ret_val)
1599                                 return ret_val;
1600                         ret_val = e1000e_update_nvm_checksum(hw);
1601                 }
1602         }
1603
1604         return 0;
1605 }
1606
1607 /**
1608  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1609  *  @hw: pointer to the HW structure
1610  *
1611  *  Clears the hardware counters by reading the counter registers.
1612  **/
1613 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1614 {
1615         u32 temp;
1616
1617         e1000e_clear_hw_cntrs_base(hw);
1618
1619         temp = er32(PRC64);
1620         temp = er32(PRC127);
1621         temp = er32(PRC255);
1622         temp = er32(PRC511);
1623         temp = er32(PRC1023);
1624         temp = er32(PRC1522);
1625         temp = er32(PTC64);
1626         temp = er32(PTC127);
1627         temp = er32(PTC255);
1628         temp = er32(PTC511);
1629         temp = er32(PTC1023);
1630         temp = er32(PTC1522);
1631
1632         temp = er32(ALGNERRC);
1633         temp = er32(RXERRC);
1634         temp = er32(TNCRS);
1635         temp = er32(CEXTERR);
1636         temp = er32(TSCTC);
1637         temp = er32(TSCTFC);
1638
1639         temp = er32(MGTPRC);
1640         temp = er32(MGTPDC);
1641         temp = er32(MGTPTC);
1642
1643         temp = er32(IAC);
1644         temp = er32(ICRXOC);
1645
1646         temp = er32(ICRXPTC);
1647         temp = er32(ICRXATC);
1648         temp = er32(ICTXPTC);
1649         temp = er32(ICTXATC);
1650         temp = er32(ICTXQEC);
1651         temp = er32(ICTXQMTC);
1652         temp = er32(ICRXDMTC);
1653 }
1654
1655 static struct e1000_mac_operations e82571_mac_ops = {
1656         /* .check_mng_mode: mac type dependent */
1657         /* .check_for_link: media type dependent */
1658         .id_led_init            = e1000e_id_led_init,
1659         .cleanup_led            = e1000e_cleanup_led_generic,
1660         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1661         .get_bus_info           = e1000e_get_bus_info_pcie,
1662         /* .get_link_up_info: media type dependent */
1663         /* .led_on: mac type dependent */
1664         .led_off                = e1000e_led_off_generic,
1665         .update_mc_addr_list    = e1000_update_mc_addr_list_82571,
1666         .reset_hw               = e1000_reset_hw_82571,
1667         .init_hw                = e1000_init_hw_82571,
1668         .setup_link             = e1000_setup_link_82571,
1669         /* .setup_physical_interface: media type dependent */
1670         .setup_led              = e1000e_setup_led_generic,
1671 };
1672
1673 static struct e1000_phy_operations e82_phy_ops_igp = {
1674         .acquire                = e1000_get_hw_semaphore_82571,
1675         .check_reset_block      = e1000e_check_reset_block_generic,
1676         .commit                 = NULL,
1677         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1678         .get_cfg_done           = e1000_get_cfg_done_82571,
1679         .get_cable_length       = e1000e_get_cable_length_igp_2,
1680         .get_info               = e1000e_get_phy_info_igp,
1681         .read_reg               = e1000e_read_phy_reg_igp,
1682         .release                = e1000_put_hw_semaphore_82571,
1683         .reset                  = e1000e_phy_hw_reset_generic,
1684         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1685         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1686         .write_reg              = e1000e_write_phy_reg_igp,
1687         .cfg_on_link_up         = NULL,
1688 };
1689
1690 static struct e1000_phy_operations e82_phy_ops_m88 = {
1691         .acquire                = e1000_get_hw_semaphore_82571,
1692         .check_reset_block      = e1000e_check_reset_block_generic,
1693         .commit                 = e1000e_phy_sw_reset,
1694         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1695         .get_cfg_done           = e1000e_get_cfg_done,
1696         .get_cable_length       = e1000e_get_cable_length_m88,
1697         .get_info               = e1000e_get_phy_info_m88,
1698         .read_reg               = e1000e_read_phy_reg_m88,
1699         .release                = e1000_put_hw_semaphore_82571,
1700         .reset                  = e1000e_phy_hw_reset_generic,
1701         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1702         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1703         .write_reg              = e1000e_write_phy_reg_m88,
1704         .cfg_on_link_up         = NULL,
1705 };
1706
1707 static struct e1000_phy_operations e82_phy_ops_bm = {
1708         .acquire                = e1000_get_hw_semaphore_82571,
1709         .check_reset_block      = e1000e_check_reset_block_generic,
1710         .commit                 = e1000e_phy_sw_reset,
1711         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1712         .get_cfg_done           = e1000e_get_cfg_done,
1713         .get_cable_length       = e1000e_get_cable_length_m88,
1714         .get_info               = e1000e_get_phy_info_m88,
1715         .read_reg               = e1000e_read_phy_reg_bm2,
1716         .release                = e1000_put_hw_semaphore_82571,
1717         .reset                  = e1000e_phy_hw_reset_generic,
1718         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1719         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1720         .write_reg              = e1000e_write_phy_reg_bm2,
1721         .cfg_on_link_up         = NULL,
1722 };
1723
1724 static struct e1000_nvm_operations e82571_nvm_ops = {
1725         .acquire                = e1000_acquire_nvm_82571,
1726         .read                   = e1000e_read_nvm_eerd,
1727         .release                = e1000_release_nvm_82571,
1728         .update                 = e1000_update_nvm_checksum_82571,
1729         .valid_led_default      = e1000_valid_led_default_82571,
1730         .validate               = e1000_validate_nvm_checksum_82571,
1731         .write                  = e1000_write_nvm_82571,
1732 };
1733
1734 struct e1000_info e1000_82571_info = {
1735         .mac                    = e1000_82571,
1736         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1737                                   | FLAG_HAS_JUMBO_FRAMES
1738                                   | FLAG_HAS_WOL
1739                                   | FLAG_APME_IN_CTRL3
1740                                   | FLAG_RX_CSUM_ENABLED
1741                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1742                                   | FLAG_HAS_SMART_POWER_DOWN
1743                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1744                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1745                                   | FLAG_APME_CHECK_PORT_B,
1746         .pba                    = 38,
1747         .max_hw_frame_size      = DEFAULT_JUMBO,
1748         .get_variants           = e1000_get_variants_82571,
1749         .mac_ops                = &e82571_mac_ops,
1750         .phy_ops                = &e82_phy_ops_igp,
1751         .nvm_ops                = &e82571_nvm_ops,
1752 };
1753
1754 struct e1000_info e1000_82572_info = {
1755         .mac                    = e1000_82572,
1756         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1757                                   | FLAG_HAS_JUMBO_FRAMES
1758                                   | FLAG_HAS_WOL
1759                                   | FLAG_APME_IN_CTRL3
1760                                   | FLAG_RX_CSUM_ENABLED
1761                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1762                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1763         .pba                    = 38,
1764         .max_hw_frame_size      = DEFAULT_JUMBO,
1765         .get_variants           = e1000_get_variants_82571,
1766         .mac_ops                = &e82571_mac_ops,
1767         .phy_ops                = &e82_phy_ops_igp,
1768         .nvm_ops                = &e82571_nvm_ops,
1769 };
1770
1771 struct e1000_info e1000_82573_info = {
1772         .mac                    = e1000_82573,
1773         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1774                                   | FLAG_HAS_JUMBO_FRAMES
1775                                   | FLAG_HAS_WOL
1776                                   | FLAG_APME_IN_CTRL3
1777                                   | FLAG_RX_CSUM_ENABLED
1778                                   | FLAG_HAS_SMART_POWER_DOWN
1779                                   | FLAG_HAS_AMT
1780                                   | FLAG_HAS_ERT
1781                                   | FLAG_HAS_SWSM_ON_LOAD,
1782         .pba                    = 20,
1783         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1784         .get_variants           = e1000_get_variants_82571,
1785         .mac_ops                = &e82571_mac_ops,
1786         .phy_ops                = &e82_phy_ops_m88,
1787         .nvm_ops                = &e82571_nvm_ops,
1788 };
1789
1790 struct e1000_info e1000_82574_info = {
1791         .mac                    = e1000_82574,
1792         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1793                                   | FLAG_HAS_MSIX
1794                                   | FLAG_HAS_JUMBO_FRAMES
1795                                   | FLAG_HAS_WOL
1796                                   | FLAG_APME_IN_CTRL3
1797                                   | FLAG_RX_CSUM_ENABLED
1798                                   | FLAG_HAS_SMART_POWER_DOWN
1799                                   | FLAG_HAS_AMT
1800                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1801         .pba                    = 20,
1802         .max_hw_frame_size      = DEFAULT_JUMBO,
1803         .get_variants           = e1000_get_variants_82571,
1804         .mac_ops                = &e82571_mac_ops,
1805         .phy_ops                = &e82_phy_ops_bm,
1806         .nvm_ops                = &e82571_nvm_ops,
1807 };
1808
1809 struct e1000_info e1000_82583_info = {
1810         .mac                    = e1000_82583,
1811         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1812                                   | FLAG_HAS_WOL
1813                                   | FLAG_APME_IN_CTRL3
1814                                   | FLAG_RX_CSUM_ENABLED
1815                                   | FLAG_HAS_SMART_POWER_DOWN
1816                                   | FLAG_HAS_AMT
1817                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1818         .pba                    = 20,
1819         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1820         .get_variants           = e1000_get_variants_82571,
1821         .mac_ops                = &e82571_mac_ops,
1822         .phy_ops                = &e82_phy_ops_bm,
1823         .nvm_ops                = &e82571_nvm_ops,
1824 };
1825