ramoops: move dump_oops into platform data
[linux-2.6.git] / drivers / net / davinci_cpdma.h
1 /*
2  * Texas Instruments CPDMA Driver
3  *
4  * Copyright (C) 2010 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #ifndef __DAVINCI_CPDMA_H__
16 #define __DAVINCI_CPDMA_H__
17
18 #define CPDMA_MAX_CHANNELS      BITS_PER_LONG
19
20 #define tx_chan_num(chan)       (chan)
21 #define rx_chan_num(chan)       ((chan) + CPDMA_MAX_CHANNELS)
22 #define is_rx_chan(chan)        ((chan)->chan_num >= CPDMA_MAX_CHANNELS)
23 #define is_tx_chan(chan)        (!is_rx_chan(chan))
24 #define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1))
25 #define chan_linear(chan)       __chan_linear((chan)->chan_num)
26
27 struct cpdma_params {
28         struct device           *dev;
29         void __iomem            *dmaregs;
30         void __iomem            *txhdp, *rxhdp, *txcp, *rxcp;
31         void __iomem            *rxthresh, *rxfree;
32         int                     num_chan;
33         bool                    has_soft_reset;
34         int                     min_packet_size;
35         u32                     desc_mem_phys;
36         u32                     desc_hw_addr;
37         int                     desc_mem_size;
38         int                     desc_align;
39
40         /*
41          * Some instances of embedded cpdma controllers have extra control and
42          * status registers.  The following flag enables access to these
43          * "extended" registers.
44          */
45         bool                    has_ext_regs;
46 };
47
48 struct cpdma_chan_stats {
49         u32                     head_enqueue;
50         u32                     tail_enqueue;
51         u32                     pad_enqueue;
52         u32                     misqueued;
53         u32                     desc_alloc_fail;
54         u32                     pad_alloc_fail;
55         u32                     runt_receive_buff;
56         u32                     runt_transmit_buff;
57         u32                     empty_dequeue;
58         u32                     busy_dequeue;
59         u32                     good_dequeue;
60         u32                     requeue;
61         u32                     teardown_dequeue;
62 };
63
64 struct cpdma_ctlr;
65 struct cpdma_chan;
66
67 typedef void (*cpdma_handler_fn)(void *token, int len, int status);
68
69 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
70 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
71 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
72 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
73 int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr);
74
75 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
76                                      cpdma_handler_fn handler);
77 int cpdma_chan_destroy(struct cpdma_chan *chan);
78 int cpdma_chan_start(struct cpdma_chan *chan);
79 int cpdma_chan_stop(struct cpdma_chan *chan);
80 int cpdma_chan_dump(struct cpdma_chan *chan);
81
82 int cpdma_chan_get_stats(struct cpdma_chan *chan,
83                          struct cpdma_chan_stats *stats);
84 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
85                       int len, gfp_t gfp_mask);
86 int cpdma_chan_process(struct cpdma_chan *chan, int quota);
87
88 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
89 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr);
90 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
91
92 enum cpdma_control {
93         CPDMA_CMD_IDLE,                 /* write-only */
94         CPDMA_COPY_ERROR_FRAMES,        /* read-write */
95         CPDMA_RX_OFF_LEN_UPDATE,        /* read-write */
96         CPDMA_RX_OWNERSHIP_FLIP,        /* read-write */
97         CPDMA_TX_PRIO_FIXED,            /* read-write */
98         CPDMA_STAT_IDLE,                /* read-only */
99         CPDMA_STAT_TX_ERR_CHAN,         /* read-only */
100         CPDMA_STAT_TX_ERR_CODE,         /* read-only */
101         CPDMA_STAT_RX_ERR_CHAN,         /* read-only */
102         CPDMA_STAT_RX_ERR_CODE,         /* read-only */
103         CPDMA_RX_BUFFER_OFFSET,         /* read-write */
104 };
105
106 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
107 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
108
109 #endif