Add support the Korina (IDT RC32434) Ethernet MAC
[linux-2.6.git] / drivers / net / cpmac.c
1 /*
2  * Copyright (C) 2006, 2007 Eugene Konev
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
17  */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/phy_fixed.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/gpio.h>
41
42 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
44 MODULE_LICENSE("GPL");
45
46 static int debug_level = 8;
47 static int dumb_switch;
48
49 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
50 module_param(debug_level, int, 0444);
51 module_param(dumb_switch, int, 0444);
52
53 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
54 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
55
56 #define CPMAC_VERSION "0.5.0"
57 /* frame size + 802.1q tag */
58 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + 4)
59 #define CPMAC_QUEUES    8
60
61 /* Ethernet registers */
62 #define CPMAC_TX_CONTROL                0x0004
63 #define CPMAC_TX_TEARDOWN               0x0008
64 #define CPMAC_RX_CONTROL                0x0014
65 #define CPMAC_RX_TEARDOWN               0x0018
66 #define CPMAC_MBP                       0x0100
67 # define MBP_RXPASSCRC                  0x40000000
68 # define MBP_RXQOS                      0x20000000
69 # define MBP_RXNOCHAIN                  0x10000000
70 # define MBP_RXCMF                      0x01000000
71 # define MBP_RXSHORT                    0x00800000
72 # define MBP_RXCEF                      0x00400000
73 # define MBP_RXPROMISC                  0x00200000
74 # define MBP_PROMISCCHAN(channel)       (((channel) & 0x7) << 16)
75 # define MBP_RXBCAST                    0x00002000
76 # define MBP_BCASTCHAN(channel)         (((channel) & 0x7) << 8)
77 # define MBP_RXMCAST                    0x00000020
78 # define MBP_MCASTCHAN(channel)         ((channel) & 0x7)
79 #define CPMAC_UNICAST_ENABLE            0x0104
80 #define CPMAC_UNICAST_CLEAR             0x0108
81 #define CPMAC_MAX_LENGTH                0x010c
82 #define CPMAC_BUFFER_OFFSET             0x0110
83 #define CPMAC_MAC_CONTROL               0x0160
84 # define MAC_TXPTYPE                    0x00000200
85 # define MAC_TXPACE                     0x00000040
86 # define MAC_MII                        0x00000020
87 # define MAC_TXFLOW                     0x00000010
88 # define MAC_RXFLOW                     0x00000008
89 # define MAC_MTEST                      0x00000004
90 # define MAC_LOOPBACK                   0x00000002
91 # define MAC_FDX                        0x00000001
92 #define CPMAC_MAC_STATUS                0x0164
93 # define MAC_STATUS_QOS                 0x00000004
94 # define MAC_STATUS_RXFLOW              0x00000002
95 # define MAC_STATUS_TXFLOW              0x00000001
96 #define CPMAC_TX_INT_ENABLE             0x0178
97 #define CPMAC_TX_INT_CLEAR              0x017c
98 #define CPMAC_MAC_INT_VECTOR            0x0180
99 # define MAC_INT_STATUS                 0x00080000
100 # define MAC_INT_HOST                   0x00040000
101 # define MAC_INT_RX                     0x00020000
102 # define MAC_INT_TX                     0x00010000
103 #define CPMAC_MAC_EOI_VECTOR            0x0184
104 #define CPMAC_RX_INT_ENABLE             0x0198
105 #define CPMAC_RX_INT_CLEAR              0x019c
106 #define CPMAC_MAC_INT_ENABLE            0x01a8
107 #define CPMAC_MAC_INT_CLEAR             0x01ac
108 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
109 #define CPMAC_MAC_ADDR_MID              0x01d0
110 #define CPMAC_MAC_ADDR_HI               0x01d4
111 #define CPMAC_MAC_HASH_LO               0x01d8
112 #define CPMAC_MAC_HASH_HI               0x01dc
113 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
114 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
115 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
116 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
117 #define CPMAC_REG_END                   0x0680
118 /*
119  * Rx/Tx statistics
120  * TODO: use some of them to fill stats in cpmac_stats()
121  */
122 #define CPMAC_STATS_RX_GOOD             0x0200
123 #define CPMAC_STATS_RX_BCAST            0x0204
124 #define CPMAC_STATS_RX_MCAST            0x0208
125 #define CPMAC_STATS_RX_PAUSE            0x020c
126 #define CPMAC_STATS_RX_CRC              0x0210
127 #define CPMAC_STATS_RX_ALIGN            0x0214
128 #define CPMAC_STATS_RX_OVER             0x0218
129 #define CPMAC_STATS_RX_JABBER           0x021c
130 #define CPMAC_STATS_RX_UNDER            0x0220
131 #define CPMAC_STATS_RX_FRAG             0x0224
132 #define CPMAC_STATS_RX_FILTER           0x0228
133 #define CPMAC_STATS_RX_QOSFILTER        0x022c
134 #define CPMAC_STATS_RX_OCTETS           0x0230
135
136 #define CPMAC_STATS_TX_GOOD             0x0234
137 #define CPMAC_STATS_TX_BCAST            0x0238
138 #define CPMAC_STATS_TX_MCAST            0x023c
139 #define CPMAC_STATS_TX_PAUSE            0x0240
140 #define CPMAC_STATS_TX_DEFER            0x0244
141 #define CPMAC_STATS_TX_COLLISION        0x0248
142 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
143 #define CPMAC_STATS_TX_MULTICOLL        0x0250
144 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
145 #define CPMAC_STATS_TX_LATECOLL         0x0258
146 #define CPMAC_STATS_TX_UNDERRUN         0x025c
147 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
148 #define CPMAC_STATS_TX_OCTETS           0x0264
149
150 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
151 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
152                                                 (reg)))
153
154 /* MDIO bus */
155 #define CPMAC_MDIO_VERSION              0x0000
156 #define CPMAC_MDIO_CONTROL              0x0004
157 # define MDIOC_IDLE                     0x80000000
158 # define MDIOC_ENABLE                   0x40000000
159 # define MDIOC_PREAMBLE                 0x00100000
160 # define MDIOC_FAULT                    0x00080000
161 # define MDIOC_FAULTDETECT              0x00040000
162 # define MDIOC_INTTEST                  0x00020000
163 # define MDIOC_CLKDIV(div)              ((div) & 0xff)
164 #define CPMAC_MDIO_ALIVE                0x0008
165 #define CPMAC_MDIO_LINK                 0x000c
166 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
167 # define MDIO_BUSY                      0x80000000
168 # define MDIO_WRITE                     0x40000000
169 # define MDIO_REG(reg)                  (((reg) & 0x1f) << 21)
170 # define MDIO_PHY(phy)                  (((phy) & 0x1f) << 16)
171 # define MDIO_DATA(data)                ((data) & 0xffff)
172 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
173 # define PHYSEL_LINKSEL                 0x00000040
174 # define PHYSEL_LINKINT                 0x00000020
175
176 struct cpmac_desc {
177         u32 hw_next;
178         u32 hw_data;
179         u16 buflen;
180         u16 bufflags;
181         u16 datalen;
182         u16 dataflags;
183 #define CPMAC_SOP                       0x8000
184 #define CPMAC_EOP                       0x4000
185 #define CPMAC_OWN                       0x2000
186 #define CPMAC_EOQ                       0x1000
187         struct sk_buff *skb;
188         struct cpmac_desc *next;
189         dma_addr_t mapping;
190         dma_addr_t data_mapping;
191 };
192
193 struct cpmac_priv {
194         spinlock_t lock;
195         spinlock_t rx_lock;
196         struct cpmac_desc *rx_head;
197         int ring_size;
198         struct cpmac_desc *desc_ring;
199         dma_addr_t dma_ring;
200         void __iomem *regs;
201         struct mii_bus *mii_bus;
202         struct phy_device *phy;
203         char phy_name[BUS_ID_SIZE];
204         int oldlink, oldspeed, oldduplex;
205         u32 msg_enable;
206         struct net_device *dev;
207         struct work_struct reset_work;
208         struct platform_device *pdev;
209         struct napi_struct napi;
210 };
211
212 static irqreturn_t cpmac_irq(int, void *);
213 static void cpmac_hw_start(struct net_device *dev);
214 static void cpmac_hw_stop(struct net_device *dev);
215 static int cpmac_stop(struct net_device *dev);
216 static int cpmac_open(struct net_device *dev);
217
218 static void cpmac_dump_regs(struct net_device *dev)
219 {
220         int i;
221         struct cpmac_priv *priv = netdev_priv(dev);
222         for (i = 0; i < CPMAC_REG_END; i += 4) {
223                 if (i % 16 == 0) {
224                         if (i)
225                                 printk("\n");
226                         printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
227                                priv->regs + i);
228                 }
229                 printk(" %08x", cpmac_read(priv->regs, i));
230         }
231         printk("\n");
232 }
233
234 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
235 {
236         int i;
237         printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
238         for (i = 0; i < sizeof(*desc) / 4; i++)
239                 printk(" %08x", ((u32 *)desc)[i]);
240         printk("\n");
241 }
242
243 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
244 {
245         int i;
246         printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
247         for (i = 0; i < skb->len; i++) {
248                 if (i % 16 == 0) {
249                         if (i)
250                                 printk("\n");
251                         printk(KERN_DEBUG "%s: data[%p]:", dev->name,
252                                skb->data + i);
253                 }
254                 printk(" %02x", ((u8 *)skb->data)[i]);
255         }
256         printk("\n");
257 }
258
259 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
260 {
261         u32 val;
262
263         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
264                 cpu_relax();
265         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
266                     MDIO_PHY(phy_id));
267         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
268                 cpu_relax();
269         return MDIO_DATA(val);
270 }
271
272 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
273                             int reg, u16 val)
274 {
275         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
276                 cpu_relax();
277         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
278                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
279         return 0;
280 }
281
282 static int cpmac_mdio_reset(struct mii_bus *bus)
283 {
284         ar7_device_reset(AR7_RESET_BIT_MDIO);
285         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
286                     MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
287         return 0;
288 }
289
290 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
291
292 static struct mii_bus cpmac_mii = {
293         .name = "cpmac-mii",
294         .read = cpmac_mdio_read,
295         .write = cpmac_mdio_write,
296         .reset = cpmac_mdio_reset,
297         .irq = mii_irqs,
298 };
299
300 static int cpmac_config(struct net_device *dev, struct ifmap *map)
301 {
302         if (dev->flags & IFF_UP)
303                 return -EBUSY;
304
305         /* Don't allow changing the I/O address */
306         if (map->base_addr != dev->base_addr)
307                 return -EOPNOTSUPP;
308
309         /* ignore other fields */
310         return 0;
311 }
312
313 static void cpmac_set_multicast_list(struct net_device *dev)
314 {
315         struct dev_mc_list *iter;
316         int i;
317         u8 tmp;
318         u32 mbp, bit, hash[2] = { 0, };
319         struct cpmac_priv *priv = netdev_priv(dev);
320
321         mbp = cpmac_read(priv->regs, CPMAC_MBP);
322         if (dev->flags & IFF_PROMISC) {
323                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
324                             MBP_RXPROMISC);
325         } else {
326                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
327                 if (dev->flags & IFF_ALLMULTI) {
328                         /* enable all multicast mode */
329                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
330                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
331                 } else {
332                         /*
333                          * cpmac uses some strange mac address hashing
334                          * (not crc32)
335                          */
336                         for (i = 0, iter = dev->mc_list; i < dev->mc_count;
337                              i++, iter = iter->next) {
338                                 bit = 0;
339                                 tmp = iter->dmi_addr[0];
340                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
341                                 tmp = iter->dmi_addr[1];
342                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
343                                 tmp = iter->dmi_addr[2];
344                                 bit  ^= (tmp >> 6) ^ tmp;
345                                 tmp = iter->dmi_addr[3];
346                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
347                                 tmp = iter->dmi_addr[4];
348                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
349                                 tmp = iter->dmi_addr[5];
350                                 bit  ^= (tmp >> 6) ^ tmp;
351                                 bit &= 0x3f;
352                                 hash[bit / 32] |= 1 << (bit % 32);
353                         }
354
355                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
356                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
357                 }
358         }
359 }
360
361 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
362                                     struct cpmac_desc *desc)
363 {
364         struct sk_buff *skb, *result = NULL;
365
366         if (unlikely(netif_msg_hw(priv)))
367                 cpmac_dump_desc(priv->dev, desc);
368         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
369         if (unlikely(!desc->datalen)) {
370                 if (netif_msg_rx_err(priv) && net_ratelimit())
371                         printk(KERN_WARNING "%s: rx: spurious interrupt\n",
372                                priv->dev->name);
373                 return NULL;
374         }
375
376         skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
377         if (likely(skb)) {
378                 skb_reserve(skb, 2);
379                 skb_put(desc->skb, desc->datalen);
380                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
381                 desc->skb->ip_summed = CHECKSUM_NONE;
382                 priv->dev->stats.rx_packets++;
383                 priv->dev->stats.rx_bytes += desc->datalen;
384                 result = desc->skb;
385                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
386                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
387                 desc->skb = skb;
388                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
389                                                     CPMAC_SKB_SIZE,
390                                                     DMA_FROM_DEVICE);
391                 desc->hw_data = (u32)desc->data_mapping;
392                 if (unlikely(netif_msg_pktdata(priv))) {
393                         printk(KERN_DEBUG "%s: received packet:\n",
394                                priv->dev->name);
395                         cpmac_dump_skb(priv->dev, result);
396                 }
397         } else {
398                 if (netif_msg_rx_err(priv) && net_ratelimit())
399                         printk(KERN_WARNING
400                                "%s: low on skbs, dropping packet\n",
401                                priv->dev->name);
402                 priv->dev->stats.rx_dropped++;
403         }
404
405         desc->buflen = CPMAC_SKB_SIZE;
406         desc->dataflags = CPMAC_OWN;
407
408         return result;
409 }
410
411 static int cpmac_poll(struct napi_struct *napi, int budget)
412 {
413         struct sk_buff *skb;
414         struct cpmac_desc *desc;
415         int received = 0;
416         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
417
418         spin_lock(&priv->rx_lock);
419         if (unlikely(!priv->rx_head)) {
420                 if (netif_msg_rx_err(priv) && net_ratelimit())
421                         printk(KERN_WARNING "%s: rx: polling, but no queue\n",
422                                priv->dev->name);
423                 netif_rx_complete(priv->dev, napi);
424                 return 0;
425         }
426
427         desc = priv->rx_head;
428         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
429                 skb = cpmac_rx_one(priv, desc);
430                 if (likely(skb)) {
431                         netif_receive_skb(skb);
432                         received++;
433                 }
434                 desc = desc->next;
435         }
436
437         priv->rx_head = desc;
438         spin_unlock(&priv->rx_lock);
439         if (unlikely(netif_msg_rx_status(priv)))
440                 printk(KERN_DEBUG "%s: poll processed %d packets\n",
441                        priv->dev->name, received);
442         if (desc->dataflags & CPMAC_OWN) {
443                 netif_rx_complete(priv->dev, napi);
444                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
445                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
446                 return 0;
447         }
448
449         return 1;
450 }
451
452 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
453 {
454         int queue, len;
455         struct cpmac_desc *desc;
456         struct cpmac_priv *priv = netdev_priv(dev);
457
458         if (unlikely(skb_padto(skb, ETH_ZLEN)))
459                 return NETDEV_TX_OK;
460
461         len = max(skb->len, ETH_ZLEN);
462         queue = skb_get_queue_mapping(skb);
463 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
464         netif_stop_subqueue(dev, queue);
465 #else
466         netif_stop_queue(dev);
467 #endif
468
469         desc = &priv->desc_ring[queue];
470         if (unlikely(desc->dataflags & CPMAC_OWN)) {
471                 if (netif_msg_tx_err(priv) && net_ratelimit())
472                         printk(KERN_WARNING "%s: tx dma ring full\n",
473                                dev->name);
474                 return NETDEV_TX_BUSY;
475         }
476
477         spin_lock(&priv->lock);
478         dev->trans_start = jiffies;
479         spin_unlock(&priv->lock);
480         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
481         desc->skb = skb;
482         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
483                                             DMA_TO_DEVICE);
484         desc->hw_data = (u32)desc->data_mapping;
485         desc->datalen = len;
486         desc->buflen = len;
487         if (unlikely(netif_msg_tx_queued(priv)))
488                 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
489                        skb->len);
490         if (unlikely(netif_msg_hw(priv)))
491                 cpmac_dump_desc(dev, desc);
492         if (unlikely(netif_msg_pktdata(priv)))
493                 cpmac_dump_skb(dev, skb);
494         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
495
496         return NETDEV_TX_OK;
497 }
498
499 static void cpmac_end_xmit(struct net_device *dev, int queue)
500 {
501         struct cpmac_desc *desc;
502         struct cpmac_priv *priv = netdev_priv(dev);
503
504         desc = &priv->desc_ring[queue];
505         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
506         if (likely(desc->skb)) {
507                 spin_lock(&priv->lock);
508                 dev->stats.tx_packets++;
509                 dev->stats.tx_bytes += desc->skb->len;
510                 spin_unlock(&priv->lock);
511                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
512                                  DMA_TO_DEVICE);
513
514                 if (unlikely(netif_msg_tx_done(priv)))
515                         printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
516                                desc->skb, desc->skb->len);
517
518                 dev_kfree_skb_irq(desc->skb);
519                 desc->skb = NULL;
520 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
521                 if (netif_subqueue_stopped(dev, queue))
522                         netif_wake_subqueue(dev, queue);
523 #else
524                 if (netif_queue_stopped(dev))
525                         netif_wake_queue(dev);
526 #endif
527         } else {
528                 if (netif_msg_tx_err(priv) && net_ratelimit())
529                         printk(KERN_WARNING
530                                "%s: end_xmit: spurious interrupt\n", dev->name);
531 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
532                 if (netif_subqueue_stopped(dev, queue))
533                         netif_wake_subqueue(dev, queue);
534 #else
535                 if (netif_queue_stopped(dev))
536                         netif_wake_queue(dev);
537 #endif
538         }
539 }
540
541 static void cpmac_hw_stop(struct net_device *dev)
542 {
543         int i;
544         struct cpmac_priv *priv = netdev_priv(dev);
545         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
546
547         ar7_device_reset(pdata->reset_bit);
548         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
549                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
550         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
551                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
552         for (i = 0; i < 8; i++) {
553                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
554                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
555         }
556         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
557         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
558         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
559         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
560         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
561                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
562 }
563
564 static void cpmac_hw_start(struct net_device *dev)
565 {
566         int i;
567         struct cpmac_priv *priv = netdev_priv(dev);
568         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
569
570         ar7_device_reset(pdata->reset_bit);
571         for (i = 0; i < 8; i++) {
572                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
573                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
574         }
575         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
576
577         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
578                     MBP_RXMCAST);
579         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
580         for (i = 0; i < 8; i++)
581                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
582         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
583         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
584                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
585                     (dev->dev_addr[3] << 24));
586         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
587         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
588         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
589         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
590         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
591         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
592         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
593         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
594         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
595
596         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
597                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
598         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
599                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
600         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
601                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
602                     MAC_FDX);
603 }
604
605 static void cpmac_clear_rx(struct net_device *dev)
606 {
607         struct cpmac_priv *priv = netdev_priv(dev);
608         struct cpmac_desc *desc;
609         int i;
610         if (unlikely(!priv->rx_head))
611                 return;
612         desc = priv->rx_head;
613         for (i = 0; i < priv->ring_size; i++) {
614                 if ((desc->dataflags & CPMAC_OWN) == 0) {
615                         if (netif_msg_rx_err(priv) && net_ratelimit())
616                                 printk(KERN_WARNING "%s: packet dropped\n",
617                                        dev->name);
618                         if (unlikely(netif_msg_hw(priv)))
619                                 cpmac_dump_desc(dev, desc);
620                         desc->dataflags = CPMAC_OWN;
621                         dev->stats.rx_dropped++;
622                 }
623                 desc = desc->next;
624         }
625 }
626
627 static void cpmac_clear_tx(struct net_device *dev)
628 {
629         struct cpmac_priv *priv = netdev_priv(dev);
630         int i;
631         if (unlikely(!priv->desc_ring))
632                 return;
633         for (i = 0; i < CPMAC_QUEUES; i++) {
634                 priv->desc_ring[i].dataflags = 0;
635                 if (priv->desc_ring[i].skb) {
636                         dev_kfree_skb_any(priv->desc_ring[i].skb);
637                         if (netif_subqueue_stopped(dev, i))
638                             netif_wake_subqueue(dev, i);
639                 }
640         }
641 }
642
643 static void cpmac_hw_error(struct work_struct *work)
644 {
645         struct cpmac_priv *priv =
646                 container_of(work, struct cpmac_priv, reset_work);
647
648         spin_lock(&priv->rx_lock);
649         cpmac_clear_rx(priv->dev);
650         spin_unlock(&priv->rx_lock);
651         cpmac_clear_tx(priv->dev);
652         cpmac_hw_start(priv->dev);
653         napi_enable(&priv->napi);
654         netif_start_queue(priv->dev);
655 }
656
657 static irqreturn_t cpmac_irq(int irq, void *dev_id)
658 {
659         struct net_device *dev = dev_id;
660         struct cpmac_priv *priv;
661         int queue;
662         u32 status;
663
664         priv = netdev_priv(dev);
665
666         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
667
668         if (unlikely(netif_msg_intr(priv)))
669                 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
670                        status);
671
672         if (status & MAC_INT_TX)
673                 cpmac_end_xmit(dev, (status & 7));
674
675         if (status & MAC_INT_RX) {
676                 queue = (status >> 8) & 7;
677                 if (netif_rx_schedule_prep(dev, &priv->napi)) {
678                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
679                         __netif_rx_schedule(dev, &priv->napi);
680                 }
681         }
682
683         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
684
685         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
686                 if (netif_msg_drv(priv) && net_ratelimit())
687                         printk(KERN_ERR "%s: hw error, resetting...\n",
688                                dev->name);
689                 netif_stop_queue(dev);
690                 napi_disable(&priv->napi);
691                 cpmac_hw_stop(dev);
692                 schedule_work(&priv->reset_work);
693                 if (unlikely(netif_msg_hw(priv)))
694                         cpmac_dump_regs(dev);
695         }
696
697         return IRQ_HANDLED;
698 }
699
700 static void cpmac_tx_timeout(struct net_device *dev)
701 {
702         struct cpmac_priv *priv = netdev_priv(dev);
703         int i;
704
705         spin_lock(&priv->lock);
706         dev->stats.tx_errors++;
707         spin_unlock(&priv->lock);
708         if (netif_msg_tx_err(priv) && net_ratelimit())
709                 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
710         /* 
711          * FIXME: waking up random queue is not the best thing to
712          * do... on the other hand why we got here at all?
713          */
714 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
715         for (i = 0; i < CPMAC_QUEUES; i++)
716                 if (priv->desc_ring[i].skb) {
717                         priv->desc_ring[i].dataflags = 0;
718                         dev_kfree_skb_any(priv->desc_ring[i].skb);
719                         netif_wake_subqueue(dev, i);
720                         break;
721                 }
722 #else
723         priv->desc_ring[0].dataflags = 0;
724         if (priv->desc_ring[0].skb)
725                 dev_kfree_skb_any(priv->desc_ring[0].skb);
726         netif_wake_queue(dev);
727 #endif
728 }
729
730 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
731 {
732         struct cpmac_priv *priv = netdev_priv(dev);
733         if (!(netif_running(dev)))
734                 return -EINVAL;
735         if (!priv->phy)
736                 return -EINVAL;
737         if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
738             (cmd == SIOCSMIIREG))
739                 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
740
741         return -EOPNOTSUPP;
742 }
743
744 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
745 {
746         struct cpmac_priv *priv = netdev_priv(dev);
747
748         if (priv->phy)
749                 return phy_ethtool_gset(priv->phy, cmd);
750
751         return -EINVAL;
752 }
753
754 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
755 {
756         struct cpmac_priv *priv = netdev_priv(dev);
757
758         if (!capable(CAP_NET_ADMIN))
759                 return -EPERM;
760
761         if (priv->phy)
762                 return phy_ethtool_sset(priv->phy, cmd);
763
764         return -EINVAL;
765 }
766
767 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
768 {
769         struct cpmac_priv *priv = netdev_priv(dev);
770
771         ring->rx_max_pending = 1024;
772         ring->rx_mini_max_pending = 1;
773         ring->rx_jumbo_max_pending = 1;
774         ring->tx_max_pending = 1;
775
776         ring->rx_pending = priv->ring_size;
777         ring->rx_mini_pending = 1;
778         ring->rx_jumbo_pending = 1;
779         ring->tx_pending = 1;
780 }
781
782 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
783 {
784         struct cpmac_priv *priv = netdev_priv(dev);
785
786         if (netif_running(dev))
787                 return -EBUSY;
788         priv->ring_size = ring->rx_pending;
789         return 0;
790 }
791
792 static void cpmac_get_drvinfo(struct net_device *dev,
793                               struct ethtool_drvinfo *info)
794 {
795         strcpy(info->driver, "cpmac");
796         strcpy(info->version, CPMAC_VERSION);
797         info->fw_version[0] = '\0';
798         sprintf(info->bus_info, "%s", "cpmac");
799         info->regdump_len = 0;
800 }
801
802 static const struct ethtool_ops cpmac_ethtool_ops = {
803         .get_settings = cpmac_get_settings,
804         .set_settings = cpmac_set_settings,
805         .get_drvinfo = cpmac_get_drvinfo,
806         .get_link = ethtool_op_get_link,
807         .get_ringparam = cpmac_get_ringparam,
808         .set_ringparam = cpmac_set_ringparam,
809 };
810
811 static void cpmac_adjust_link(struct net_device *dev)
812 {
813         struct cpmac_priv *priv = netdev_priv(dev);
814         int new_state = 0;
815
816         spin_lock(&priv->lock);
817         if (priv->phy->link) {
818                 netif_start_queue(dev);
819                 if (priv->phy->duplex != priv->oldduplex) {
820                         new_state = 1;
821                         priv->oldduplex = priv->phy->duplex;
822                 }
823
824                 if (priv->phy->speed != priv->oldspeed) {
825                         new_state = 1;
826                         priv->oldspeed = priv->phy->speed;
827                 }
828
829                 if (!priv->oldlink) {
830                         new_state = 1;
831                         priv->oldlink = 1;
832                         netif_schedule(dev);
833                 }
834         } else if (priv->oldlink) {
835                 netif_stop_queue(dev);
836                 new_state = 1;
837                 priv->oldlink = 0;
838                 priv->oldspeed = 0;
839                 priv->oldduplex = -1;
840         }
841
842         if (new_state && netif_msg_link(priv) && net_ratelimit())
843                 phy_print_status(priv->phy);
844
845         spin_unlock(&priv->lock);
846 }
847
848 static int cpmac_open(struct net_device *dev)
849 {
850         int i, size, res;
851         struct cpmac_priv *priv = netdev_priv(dev);
852         struct resource *mem;
853         struct cpmac_desc *desc;
854         struct sk_buff *skb;
855
856         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
857         if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
858                 if (netif_msg_drv(priv))
859                         printk(KERN_ERR "%s: failed to request registers\n",
860                                dev->name);
861                 res = -ENXIO;
862                 goto fail_reserve;
863         }
864
865         priv->regs = ioremap(mem->start, mem->end - mem->start);
866         if (!priv->regs) {
867                 if (netif_msg_drv(priv))
868                         printk(KERN_ERR "%s: failed to remap registers\n",
869                                dev->name);
870                 res = -ENXIO;
871                 goto fail_remap;
872         }
873
874         size = priv->ring_size + CPMAC_QUEUES;
875         priv->desc_ring = dma_alloc_coherent(&dev->dev,
876                                              sizeof(struct cpmac_desc) * size,
877                                              &priv->dma_ring,
878                                              GFP_KERNEL);
879         if (!priv->desc_ring) {
880                 res = -ENOMEM;
881                 goto fail_alloc;
882         }
883
884         for (i = 0; i < size; i++)
885                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
886
887         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
888         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
889                 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
890                 if (unlikely(!skb)) {
891                         res = -ENOMEM;
892                         goto fail_desc;
893                 }
894                 skb_reserve(skb, 2);
895                 desc->skb = skb;
896                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
897                                                     CPMAC_SKB_SIZE,
898                                                     DMA_FROM_DEVICE);
899                 desc->hw_data = (u32)desc->data_mapping;
900                 desc->buflen = CPMAC_SKB_SIZE;
901                 desc->dataflags = CPMAC_OWN;
902                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
903                 desc->hw_next = (u32)desc->next->mapping;
904         }
905
906         if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
907                                dev->name, dev))) {
908                 if (netif_msg_drv(priv))
909                         printk(KERN_ERR "%s: failed to obtain irq\n",
910                                dev->name);
911                 goto fail_irq;
912         }
913
914         INIT_WORK(&priv->reset_work, cpmac_hw_error);
915         cpmac_hw_start(dev);
916
917         napi_enable(&priv->napi);
918         priv->phy->state = PHY_CHANGELINK;
919         phy_start(priv->phy);
920
921         return 0;
922
923 fail_irq:
924 fail_desc:
925         for (i = 0; i < priv->ring_size; i++) {
926                 if (priv->rx_head[i].skb) {
927                         dma_unmap_single(&dev->dev,
928                                          priv->rx_head[i].data_mapping,
929                                          CPMAC_SKB_SIZE,
930                                          DMA_FROM_DEVICE);
931                         kfree_skb(priv->rx_head[i].skb);
932                 }
933         }
934 fail_alloc:
935         kfree(priv->desc_ring);
936         iounmap(priv->regs);
937
938 fail_remap:
939         release_mem_region(mem->start, mem->end - mem->start);
940
941 fail_reserve:
942         return res;
943 }
944
945 static int cpmac_stop(struct net_device *dev)
946 {
947         int i;
948         struct cpmac_priv *priv = netdev_priv(dev);
949         struct resource *mem;
950
951         netif_stop_queue(dev);
952
953         cancel_work_sync(&priv->reset_work);
954         napi_disable(&priv->napi);
955         phy_stop(priv->phy);
956
957         cpmac_hw_stop(dev);
958
959         for (i = 0; i < 8; i++)
960                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
961         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
962         cpmac_write(priv->regs, CPMAC_MBP, 0);
963
964         free_irq(dev->irq, dev);
965         iounmap(priv->regs);
966         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
967         release_mem_region(mem->start, mem->end - mem->start);
968         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
969         for (i = 0; i < priv->ring_size; i++) {
970                 if (priv->rx_head[i].skb) {
971                         dma_unmap_single(&dev->dev,
972                                          priv->rx_head[i].data_mapping,
973                                          CPMAC_SKB_SIZE,
974                                          DMA_FROM_DEVICE);
975                         kfree_skb(priv->rx_head[i].skb);
976                 }
977         }
978
979         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
980                           (CPMAC_QUEUES + priv->ring_size),
981                           priv->desc_ring, priv->dma_ring);
982         return 0;
983 }
984
985 static int external_switch;
986
987 static int __devinit cpmac_probe(struct platform_device *pdev)
988 {
989         int rc, phy_id, i;
990         int mdio_bus_id = cpmac_mii.id;
991         struct resource *mem;
992         struct cpmac_priv *priv;
993         struct net_device *dev;
994         struct plat_cpmac_data *pdata;
995         DECLARE_MAC_BUF(mac);
996
997         pdata = pdev->dev.platform_data;
998
999         for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1000                 if (!(pdata->phy_mask & (1 << phy_id)))
1001                         continue;
1002                 if (!cpmac_mii.phy_map[phy_id])
1003                         continue;
1004                 break;
1005         }
1006
1007         if (phy_id == PHY_MAX_ADDR) {
1008                 if (external_switch || dumb_switch) {
1009                         struct fixed_phy_status status = {};
1010
1011                         mdio_bus_id = 0;
1012
1013                         /*
1014                          * FIXME: this should be in the platform code!
1015                          * Since there is not platform code at all (that is,
1016                          * no mainline users of that driver), place it here
1017                          * for now.
1018                          */
1019                         phy_id = 0;
1020                         status.link = 1;
1021                         status.duplex = 1;
1022                         status.speed = 100;
1023                         fixed_phy_add(PHY_POLL, phy_id, &status);
1024                 } else {
1025                         printk(KERN_ERR "cpmac: no PHY present\n");
1026                         return -ENODEV;
1027                 }
1028         }
1029
1030         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1031
1032         if (!dev) {
1033                 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1034                 return -ENOMEM;
1035         }
1036
1037         platform_set_drvdata(pdev, dev);
1038         priv = netdev_priv(dev);
1039
1040         priv->pdev = pdev;
1041         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1042         if (!mem) {
1043                 rc = -ENODEV;
1044                 goto fail;
1045         }
1046
1047         dev->irq = platform_get_irq_byname(pdev, "irq");
1048
1049         dev->open               = cpmac_open;
1050         dev->stop               = cpmac_stop;
1051         dev->set_config         = cpmac_config;
1052         dev->hard_start_xmit    = cpmac_start_xmit;
1053         dev->do_ioctl           = cpmac_ioctl;
1054         dev->set_multicast_list = cpmac_set_multicast_list;
1055         dev->tx_timeout         = cpmac_tx_timeout;
1056         dev->ethtool_ops        = &cpmac_ethtool_ops;
1057         dev->features |= NETIF_F_MULTI_QUEUE;
1058
1059         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1060
1061         spin_lock_init(&priv->lock);
1062         spin_lock_init(&priv->rx_lock);
1063         priv->dev = dev;
1064         priv->ring_size = 64;
1065         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1066         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1067
1068         snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
1069
1070         priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
1071                                 PHY_INTERFACE_MODE_MII);
1072         if (IS_ERR(priv->phy)) {
1073                 if (netif_msg_drv(priv))
1074                         printk(KERN_ERR "%s: Could not attach to PHY\n",
1075                                dev->name);
1076                 return PTR_ERR(priv->phy);
1077         }
1078
1079         if ((rc = register_netdev(dev))) {
1080                 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1081                        dev->name);
1082                 goto fail;
1083         }
1084
1085         if (netif_msg_probe(priv)) {
1086                 printk(KERN_INFO
1087                        "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1088                        "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1089                        priv->phy_name, print_mac(mac, dev->dev_addr));
1090         }
1091         return 0;
1092
1093 fail:
1094         free_netdev(dev);
1095         return rc;
1096 }
1097
1098 static int __devexit cpmac_remove(struct platform_device *pdev)
1099 {
1100         struct net_device *dev = platform_get_drvdata(pdev);
1101         unregister_netdev(dev);
1102         free_netdev(dev);
1103         return 0;
1104 }
1105
1106 static struct platform_driver cpmac_driver = {
1107         .driver.name = "cpmac",
1108         .probe = cpmac_probe,
1109         .remove = __devexit_p(cpmac_remove),
1110 };
1111
1112 int __devinit cpmac_init(void)
1113 {
1114         u32 mask;
1115         int i, res;
1116
1117         cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1118
1119         if (!cpmac_mii.priv) {
1120                 printk(KERN_ERR "Can't ioremap mdio registers\n");
1121                 return -ENXIO;
1122         }
1123
1124 #warning FIXME: unhardcode gpio&reset bits
1125         ar7_gpio_disable(26);
1126         ar7_gpio_disable(27);
1127         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1128         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1129         ar7_device_reset(AR7_RESET_BIT_EPHY);
1130
1131         cpmac_mii.reset(&cpmac_mii);
1132
1133         for (i = 0; i < 300000; i++)
1134                 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1135                         break;
1136                 else
1137                         cpu_relax();
1138
1139         mask &= 0x7fffffff;
1140         if (mask & (mask - 1)) {
1141                 external_switch = 1;
1142                 mask = 0;
1143         }
1144
1145         cpmac_mii.phy_mask = ~(mask | 0x80000000);
1146
1147         res = mdiobus_register(&cpmac_mii);
1148         if (res)
1149                 goto fail_mii;
1150
1151         res = platform_driver_register(&cpmac_driver);
1152         if (res)
1153                 goto fail_cpmac;
1154
1155         return 0;
1156
1157 fail_cpmac:
1158         mdiobus_unregister(&cpmac_mii);
1159
1160 fail_mii:
1161         iounmap(cpmac_mii.priv);
1162
1163         return res;
1164 }
1165
1166 void __devexit cpmac_exit(void)
1167 {
1168         platform_driver_unregister(&cpmac_driver);
1169         mdiobus_unregister(&cpmac_mii);
1170         iounmap(cpmac_mii.priv);
1171 }
1172
1173 module_init(cpmac_init);
1174 module_exit(cpmac_exit);