net:wireless:bcmdhd: rename bcmsdh_remove & bcmsdh_probe
[linux-2.6.git] / drivers / net / cnic_defs.h
1
2 /* cnic.c: Broadcom CNIC core network driver.
3  *
4  * Copyright (c) 2006-2009 Broadcom Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  *
10  */
11
12 #ifndef CNIC_DEFS_H
13 #define CNIC_DEFS_H
14
15 /* KWQ (kernel work queue) request op codes */
16 #define L2_KWQE_OPCODE_VALUE_FLUSH                  (4)
17 #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE       (8)
18
19 #define L4_KWQE_OPCODE_VALUE_CONNECT1               (50)
20 #define L4_KWQE_OPCODE_VALUE_CONNECT2               (51)
21 #define L4_KWQE_OPCODE_VALUE_CONNECT3               (52)
22 #define L4_KWQE_OPCODE_VALUE_RESET                  (53)
23 #define L4_KWQE_OPCODE_VALUE_CLOSE                  (54)
24 #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET          (60)
25 #define L4_KWQE_OPCODE_VALUE_INIT_ULP               (61)
26
27 #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG             (1)
28 #define L4_KWQE_OPCODE_VALUE_UPDATE_PG              (9)
29 #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG              (14)
30
31 #define L5CM_RAMROD_CMD_ID_BASE                 (0x80)
32 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT          (L5CM_RAMROD_CMD_ID_BASE + 3)
33 #define L5CM_RAMROD_CMD_ID_CLOSE                (L5CM_RAMROD_CMD_ID_BASE + 12)
34 #define L5CM_RAMROD_CMD_ID_ABORT                (L5CM_RAMROD_CMD_ID_BASE + 13)
35 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE      (L5CM_RAMROD_CMD_ID_BASE + 14)
36 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD    (L5CM_RAMROD_CMD_ID_BASE + 15)
37
38 #define FCOE_KCQE_OPCODE_INIT_FUNC                      (0x10)
39 #define FCOE_KCQE_OPCODE_DESTROY_FUNC                   (0x11)
40 #define FCOE_KCQE_OPCODE_STAT_FUNC                      (0x12)
41 #define FCOE_KCQE_OPCODE_OFFLOAD_CONN                   (0x15)
42 #define FCOE_KCQE_OPCODE_ENABLE_CONN                    (0x16)
43 #define FCOE_KCQE_OPCODE_DISABLE_CONN                   (0x17)
44 #define FCOE_KCQE_OPCODE_DESTROY_CONN                   (0x18)
45 #define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION  (0x20)
46 #define FCOE_KCQE_OPCODE_FCOE_ERROR                             (0x21)
47
48 #define FCOE_RAMROD_CMD_ID_INIT_FUNC            (FCOE_KCQE_OPCODE_INIT_FUNC)
49 #define FCOE_RAMROD_CMD_ID_DESTROY_FUNC         (FCOE_KCQE_OPCODE_DESTROY_FUNC)
50 #define FCOE_RAMROD_CMD_ID_STAT_FUNC            (FCOE_KCQE_OPCODE_STAT_FUNC)
51 #define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN         (FCOE_KCQE_OPCODE_OFFLOAD_CONN)
52 #define FCOE_RAMROD_CMD_ID_ENABLE_CONN          (FCOE_KCQE_OPCODE_ENABLE_CONN)
53 #define FCOE_RAMROD_CMD_ID_DISABLE_CONN         (FCOE_KCQE_OPCODE_DISABLE_CONN)
54 #define FCOE_RAMROD_CMD_ID_DESTROY_CONN         (FCOE_KCQE_OPCODE_DESTROY_CONN)
55 #define FCOE_RAMROD_CMD_ID_TERMINATE_CONN       (0x81)
56
57 #define FCOE_KWQE_OPCODE_INIT1                  (0)
58 #define FCOE_KWQE_OPCODE_INIT2                  (1)
59 #define FCOE_KWQE_OPCODE_INIT3                  (2)
60 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN1  (3)
61 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN2  (4)
62 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN3  (5)
63 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN4  (6)
64 #define FCOE_KWQE_OPCODE_ENABLE_CONN    (7)
65 #define FCOE_KWQE_OPCODE_DISABLE_CONN   (8)
66 #define FCOE_KWQE_OPCODE_DESTROY_CONN   (9)
67 #define FCOE_KWQE_OPCODE_DESTROY                (10)
68 #define FCOE_KWQE_OPCODE_STAT                   (11)
69
70 #define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE   (0x3)
71
72 /* KCQ (kernel completion queue) response op codes */
73 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP             (53)
74 #define L4_KCQE_OPCODE_VALUE_RESET_COMP             (54)
75 #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE          (55)
76 #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE       (56)
77 #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED         (57)
78 #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED         (58)
79 #define L4_KCQE_OPCODE_VALUE_INIT_ULP               (61)
80
81 #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG             (1)
82 #define L4_KCQE_OPCODE_VALUE_UPDATE_PG              (9)
83 #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG              (14)
84
85 /* KCQ (kernel completion queue) completion status */
86 #define L4_KCQE_COMPLETION_STATUS_SUCCESS           (0)
87 #define L4_KCQE_COMPLETION_STATUS_TIMEOUT           (0x93)
88
89 #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL    (0x83)
90 #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG      (0x89)
91
92 #define L4_KCQE_OPCODE_VALUE_OOO_EVENT_NOTIFICATION (0xa0)
93 #define L4_KCQE_OPCODE_VALUE_OOO_FLUSH              (0xa1)
94
95 #define L4_LAYER_CODE (4)
96 #define L2_LAYER_CODE (2)
97
98 /*
99  * L4 KCQ CQE
100  */
101 struct l4_kcq {
102         u32 cid;
103         u32 pg_cid;
104         u32 conn_id;
105         u32 pg_host_opaque;
106 #if defined(__BIG_ENDIAN)
107         u16 status;
108         u16 reserved1;
109 #elif defined(__LITTLE_ENDIAN)
110         u16 reserved1;
111         u16 status;
112 #endif
113         u32 reserved2[2];
114 #if defined(__BIG_ENDIAN)
115         u8 flags;
116 #define L4_KCQ_RESERVED3 (0x7<<0)
117 #define L4_KCQ_RESERVED3_SHIFT 0
118 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
119 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
120 #define L4_KCQ_LAYER_CODE (0x7<<4)
121 #define L4_KCQ_LAYER_CODE_SHIFT 4
122 #define L4_KCQ_RESERVED4 (0x1<<7)
123 #define L4_KCQ_RESERVED4_SHIFT 7
124         u8 op_code;
125         u16 qe_self_seq;
126 #elif defined(__LITTLE_ENDIAN)
127         u16 qe_self_seq;
128         u8 op_code;
129         u8 flags;
130 #define L4_KCQ_RESERVED3 (0xF<<0)
131 #define L4_KCQ_RESERVED3_SHIFT 0
132 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
133 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
134 #define L4_KCQ_LAYER_CODE (0x7<<4)
135 #define L4_KCQ_LAYER_CODE_SHIFT 4
136 #define L4_KCQ_RESERVED4 (0x1<<7)
137 #define L4_KCQ_RESERVED4_SHIFT 7
138 #endif
139 };
140
141
142 /*
143  * L4 KCQ CQE PG upload
144  */
145 struct l4_kcq_upload_pg {
146         u32 pg_cid;
147 #if defined(__BIG_ENDIAN)
148         u16 pg_status;
149         u16 pg_ipid_count;
150 #elif defined(__LITTLE_ENDIAN)
151         u16 pg_ipid_count;
152         u16 pg_status;
153 #endif
154         u32 reserved1[5];
155 #if defined(__BIG_ENDIAN)
156         u8 flags;
157 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0)
158 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0
159 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
160 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
161 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7)
162 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7
163         u8 op_code;
164         u16 qe_self_seq;
165 #elif defined(__LITTLE_ENDIAN)
166         u16 qe_self_seq;
167         u8 op_code;
168         u8 flags;
169 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0)
170 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0
171 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
172 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
173 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7)
174 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7
175 #endif
176 };
177
178
179 /*
180  * Gracefully close the connection request
181  */
182 struct l4_kwq_close_req {
183 #if defined(__BIG_ENDIAN)
184         u8 flags;
185 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0)
186 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0
187 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4)
188 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4
189 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7)
190 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7
191         u8 op_code;
192         u16 reserved0;
193 #elif defined(__LITTLE_ENDIAN)
194         u16 reserved0;
195         u8 op_code;
196         u8 flags;
197 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0)
198 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0
199 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4)
200 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4
201 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7)
202 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7
203 #endif
204         u32 cid;
205         u32 reserved2[6];
206 };
207
208
209 /*
210  * The first request to be passed in order to establish connection in option2
211  */
212 struct l4_kwq_connect_req1 {
213 #if defined(__BIG_ENDIAN)
214         u8 flags;
215 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0)
216 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0
217 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4)
218 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4
219 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7)
220 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7
221         u8 op_code;
222         u8 reserved0;
223         u8 conn_flags;
224 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0)
225 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0
226 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1)
227 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1
228 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2)
229 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2
230 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
231 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
232 #elif defined(__LITTLE_ENDIAN)
233         u8 conn_flags;
234 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0)
235 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0
236 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1)
237 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1
238 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2)
239 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2
240 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
241 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
242         u8 reserved0;
243         u8 op_code;
244         u8 flags;
245 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0)
246 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0
247 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4)
248 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4
249 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7)
250 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7
251 #endif
252         u32 cid;
253         u32 pg_cid;
254         u32 src_ip;
255         u32 dst_ip;
256 #if defined(__BIG_ENDIAN)
257         u16 dst_port;
258         u16 src_port;
259 #elif defined(__LITTLE_ENDIAN)
260         u16 src_port;
261         u16 dst_port;
262 #endif
263 #if defined(__BIG_ENDIAN)
264         u8 rsrv1[3];
265         u8 tcp_flags;
266 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0)
267 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0
268 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1)
269 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1
270 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2)
271 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2
272 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3)
273 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3
274 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4)
275 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4
276 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5)
277 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5
278 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6)
279 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6
280 #elif defined(__LITTLE_ENDIAN)
281         u8 tcp_flags;
282 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0)
283 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0
284 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1)
285 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1
286 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2)
287 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2
288 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3)
289 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3
290 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4)
291 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4
292 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5)
293 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5
294 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6)
295 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6
296         u8 rsrv1[3];
297 #endif
298         u32 rsrv2;
299 };
300
301
302 /*
303  * The second ( optional )request to be passed in order to establish
304  * connection in option2 - for IPv6 only
305  */
306 struct l4_kwq_connect_req2 {
307 #if defined(__BIG_ENDIAN)
308         u8 flags;
309 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0)
310 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0
311 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4)
312 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4
313 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7)
314 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7
315         u8 op_code;
316         u8 reserved0;
317         u8 rsrv;
318 #elif defined(__LITTLE_ENDIAN)
319         u8 rsrv;
320         u8 reserved0;
321         u8 op_code;
322         u8 flags;
323 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0)
324 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0
325 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4)
326 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4
327 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7)
328 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7
329 #endif
330         u32 reserved2;
331         u32 src_ip_v6_2;
332         u32 src_ip_v6_3;
333         u32 src_ip_v6_4;
334         u32 dst_ip_v6_2;
335         u32 dst_ip_v6_3;
336         u32 dst_ip_v6_4;
337 };
338
339
340 /*
341  * The third ( and last )request to be passed in order to establish
342  * connection in option2
343  */
344 struct l4_kwq_connect_req3 {
345 #if defined(__BIG_ENDIAN)
346         u8 flags;
347 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0)
348 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0
349 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4)
350 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4
351 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7)
352 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7
353         u8 op_code;
354         u16 reserved0;
355 #elif defined(__LITTLE_ENDIAN)
356         u16 reserved0;
357         u8 op_code;
358         u8 flags;
359 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0)
360 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0
361 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4)
362 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4
363 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7)
364 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7
365 #endif
366         u32 ka_timeout;
367         u32 ka_interval ;
368 #if defined(__BIG_ENDIAN)
369         u8 snd_seq_scale;
370         u8 ttl;
371         u8 tos;
372         u8 ka_max_probe_count;
373 #elif defined(__LITTLE_ENDIAN)
374         u8 ka_max_probe_count;
375         u8 tos;
376         u8 ttl;
377         u8 snd_seq_scale;
378 #endif
379 #if defined(__BIG_ENDIAN)
380         u16 pmtu;
381         u16 mss;
382 #elif defined(__LITTLE_ENDIAN)
383         u16 mss;
384         u16 pmtu;
385 #endif
386         u32 rcv_buf;
387         u32 snd_buf;
388         u32 seed;
389 };
390
391
392 /*
393  * a KWQE request to offload a PG connection
394  */
395 struct l4_kwq_offload_pg {
396 #if defined(__BIG_ENDIAN)
397         u8 flags;
398 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0)
399 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0
400 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4)
401 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4
402 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7)
403 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7
404         u8 op_code;
405         u16 reserved0;
406 #elif defined(__LITTLE_ENDIAN)
407         u16 reserved0;
408         u8 op_code;
409         u8 flags;
410 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0)
411 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0
412 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4)
413 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4
414 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7)
415 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7
416 #endif
417 #if defined(__BIG_ENDIAN)
418         u8 l2hdr_nbytes;
419         u8 pg_flags;
420 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0)
421 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0
422 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1)
423 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1
424 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2)
425 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2
426         u8 da0;
427         u8 da1;
428 #elif defined(__LITTLE_ENDIAN)
429         u8 da1;
430         u8 da0;
431         u8 pg_flags;
432 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0)
433 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0
434 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1)
435 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1
436 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2)
437 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2
438         u8 l2hdr_nbytes;
439 #endif
440 #if defined(__BIG_ENDIAN)
441         u8 da2;
442         u8 da3;
443         u8 da4;
444         u8 da5;
445 #elif defined(__LITTLE_ENDIAN)
446         u8 da5;
447         u8 da4;
448         u8 da3;
449         u8 da2;
450 #endif
451 #if defined(__BIG_ENDIAN)
452         u8 sa0;
453         u8 sa1;
454         u8 sa2;
455         u8 sa3;
456 #elif defined(__LITTLE_ENDIAN)
457         u8 sa3;
458         u8 sa2;
459         u8 sa1;
460         u8 sa0;
461 #endif
462 #if defined(__BIG_ENDIAN)
463         u8 sa4;
464         u8 sa5;
465         u16 etype;
466 #elif defined(__LITTLE_ENDIAN)
467         u16 etype;
468         u8 sa5;
469         u8 sa4;
470 #endif
471 #if defined(__BIG_ENDIAN)
472         u16 vlan_tag;
473         u16 ipid_start;
474 #elif defined(__LITTLE_ENDIAN)
475         u16 ipid_start;
476         u16 vlan_tag;
477 #endif
478 #if defined(__BIG_ENDIAN)
479         u16 ipid_count;
480         u16 reserved3;
481 #elif defined(__LITTLE_ENDIAN)
482         u16 reserved3;
483         u16 ipid_count;
484 #endif
485         u32 host_opaque;
486 };
487
488
489 /*
490  * Abortively close the connection request
491  */
492 struct l4_kwq_reset_req {
493 #if defined(__BIG_ENDIAN)
494         u8 flags;
495 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0)
496 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0
497 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4)
498 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4
499 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7)
500 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7
501         u8 op_code;
502         u16 reserved0;
503 #elif defined(__LITTLE_ENDIAN)
504         u16 reserved0;
505         u8 op_code;
506         u8 flags;
507 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0)
508 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0
509 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4)
510 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4
511 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7)
512 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7
513 #endif
514         u32 cid;
515         u32 reserved2[6];
516 };
517
518
519 /*
520  * a KWQE request to update a PG connection
521  */
522 struct l4_kwq_update_pg {
523 #if defined(__BIG_ENDIAN)
524         u8 flags;
525 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0)
526 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0
527 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4)
528 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4
529 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7)
530 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7
531         u8 opcode;
532         u16 oper16;
533 #elif defined(__LITTLE_ENDIAN)
534         u16 oper16;
535         u8 opcode;
536         u8 flags;
537 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0)
538 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0
539 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4)
540 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4
541 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7)
542 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7
543 #endif
544         u32 pg_cid;
545         u32 pg_host_opaque;
546 #if defined(__BIG_ENDIAN)
547         u8 pg_valids;
548 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0)
549 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0
550 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1)
551 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1
552 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2)
553 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2
554         u8 pg_unused_a;
555         u16 pg_ipid_count;
556 #elif defined(__LITTLE_ENDIAN)
557         u16 pg_ipid_count;
558         u8 pg_unused_a;
559         u8 pg_valids;
560 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0)
561 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0
562 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1)
563 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1
564 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2)
565 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2
566 #endif
567 #if defined(__BIG_ENDIAN)
568         u16 reserverd3;
569         u8 da0;
570         u8 da1;
571 #elif defined(__LITTLE_ENDIAN)
572         u8 da1;
573         u8 da0;
574         u16 reserverd3;
575 #endif
576 #if defined(__BIG_ENDIAN)
577         u8 da2;
578         u8 da3;
579         u8 da4;
580         u8 da5;
581 #elif defined(__LITTLE_ENDIAN)
582         u8 da5;
583         u8 da4;
584         u8 da3;
585         u8 da2;
586 #endif
587         u32 reserved4;
588         u32 reserved5;
589 };
590
591
592 /*
593  * a KWQE request to upload a PG or L4 context
594  */
595 struct l4_kwq_upload {
596 #if defined(__BIG_ENDIAN)
597         u8 flags;
598 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0)
599 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0
600 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4)
601 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4
602 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7)
603 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7
604         u8 opcode;
605         u16 oper16;
606 #elif defined(__LITTLE_ENDIAN)
607         u16 oper16;
608         u8 opcode;
609         u8 flags;
610 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0)
611 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0
612 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4)
613 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4
614 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7)
615 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7
616 #endif
617         u32 cid;
618         u32 reserved2[6];
619 };
620
621 /*
622  * bnx2x structures
623  */
624
625 /*
626  * The iscsi aggregative context of Cstorm
627  */
628 struct cstorm_iscsi_ag_context {
629         u32 agg_vars1;
630 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0)
631 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
632 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8)
633 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8
634 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9)
635 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9
636 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10)
637 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10
638 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11)
639 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11
640 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12)
641 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12
642 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13)
643 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13
644 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14)
645 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14
646 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16)
647 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16
648 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18)
649 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18
650 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19)
651 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19
652 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20)
653 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20
654 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21)
655 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21
656 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22)
657 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22
658 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23)
659 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23
660 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26)
661 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26
662 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28)
663 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28
664 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30)
665 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30
666 #if defined(__BIG_ENDIAN)
667         u8 __aux1_th;
668         u8 __aux1_val;
669         u16 __agg_vars2;
670 #elif defined(__LITTLE_ENDIAN)
671         u16 __agg_vars2;
672         u8 __aux1_val;
673         u8 __aux1_th;
674 #endif
675         u32 rel_seq;
676         u32 rel_seq_th;
677 #if defined(__BIG_ENDIAN)
678         u16 hq_cons;
679         u16 hq_prod;
680 #elif defined(__LITTLE_ENDIAN)
681         u16 hq_prod;
682         u16 hq_cons;
683 #endif
684 #if defined(__BIG_ENDIAN)
685         u8 __reserved62;
686         u8 __reserved61;
687         u8 __reserved60;
688         u8 __reserved59;
689 #elif defined(__LITTLE_ENDIAN)
690         u8 __reserved59;
691         u8 __reserved60;
692         u8 __reserved61;
693         u8 __reserved62;
694 #endif
695 #if defined(__BIG_ENDIAN)
696         u16 __reserved64;
697         u16 cq_u_prod;
698 #elif defined(__LITTLE_ENDIAN)
699         u16 cq_u_prod;
700         u16 __reserved64;
701 #endif
702         u32 __cq_u_prod1;
703 #if defined(__BIG_ENDIAN)
704         u16 __agg_vars3;
705         u16 cq_u_pend;
706 #elif defined(__LITTLE_ENDIAN)
707         u16 cq_u_pend;
708         u16 __agg_vars3;
709 #endif
710 #if defined(__BIG_ENDIAN)
711         u16 __aux2_th;
712         u16 aux2_val;
713 #elif defined(__LITTLE_ENDIAN)
714         u16 aux2_val;
715         u16 __aux2_th;
716 #endif
717 };
718
719 /*
720  * The fcoe extra aggregative context section of Tstorm
721  */
722 struct tstorm_fcoe_extra_ag_context_section {
723         u32 __agg_val1;
724 #if defined(__BIG_ENDIAN)
725         u8 __tcp_agg_vars2;
726         u8 __agg_val3;
727         u16 __agg_val2;
728 #elif defined(__LITTLE_ENDIAN)
729         u16 __agg_val2;
730         u8 __agg_val3;
731         u8 __tcp_agg_vars2;
732 #endif
733 #if defined(__BIG_ENDIAN)
734         u16 __agg_val5;
735         u8 __agg_val6;
736         u8 __tcp_agg_vars3;
737 #elif defined(__LITTLE_ENDIAN)
738         u8 __tcp_agg_vars3;
739         u8 __agg_val6;
740         u16 __agg_val5;
741 #endif
742         u32 __lcq_prod;
743         u32 rtt_seq;
744         u32 rtt_time;
745         u32 __reserved66;
746         u32 wnd_right_edge;
747         u32 tcp_agg_vars1;
748 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
749 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
750 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
751 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
752 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
753 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
754 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
755 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
756 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
757 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
758 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
759 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
760 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
761 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
762 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
763 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
764 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
765 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
766 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
767 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
768 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
769 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
770 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
771 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
772 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
773 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
774 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
775 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
776 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
777 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
778 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
779 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
780 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
781 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
782 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
783 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
784 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
785 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
786 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
787 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
788 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
789 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
790         u32 snd_max;
791         u32 __lcq_cons;
792         u32 __reserved2;
793 };
794
795 /*
796  * The fcoe aggregative context of Tstorm
797  */
798 struct tstorm_fcoe_ag_context {
799 #if defined(__BIG_ENDIAN)
800         u16 ulp_credit;
801         u8 agg_vars1;
802 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
803 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
804 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
805 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
806 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
807 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
808 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
809 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
810 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
811 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
812 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
813 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
814 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
815 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
816         u8 state;
817 #elif defined(__LITTLE_ENDIAN)
818         u8 state;
819         u8 agg_vars1;
820 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
821 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
822 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
823 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
824 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
825 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
826 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
827 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
828 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
829 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
830 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
831 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
832 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
833 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
834         u16 ulp_credit;
835 #endif
836 #if defined(__BIG_ENDIAN)
837         u16 __agg_val4;
838         u16 agg_vars2;
839 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
840 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
841 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
842 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
843 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
844 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
845 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
846 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
847 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
848 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
849 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
850 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
851 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
852 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
853 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
854 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
855 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
856 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
857 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
858 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
859 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
860 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
861 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
862 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
863 #elif defined(__LITTLE_ENDIAN)
864         u16 agg_vars2;
865 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
866 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
867 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
868 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
869 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
870 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
871 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
872 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
873 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
874 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
875 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
876 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
877 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
878 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
879 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
880 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
881 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
882 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
883 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
884 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
885 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
886 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
887 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
888 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
889         u16 __agg_val4;
890 #endif
891         struct tstorm_fcoe_extra_ag_context_section __extra_section;
892 };
893
894
895
896 /*
897  * The tcp aggregative context section of Tstorm
898  */
899 struct tstorm_tcp_tcp_ag_context_section {
900         u32 __agg_val1;
901 #if defined(__BIG_ENDIAN)
902         u8 __tcp_agg_vars2;
903         u8 __agg_val3;
904         u16 __agg_val2;
905 #elif defined(__LITTLE_ENDIAN)
906         u16 __agg_val2;
907         u8 __agg_val3;
908         u8 __tcp_agg_vars2;
909 #endif
910 #if defined(__BIG_ENDIAN)
911         u16 __agg_val5;
912         u8 __agg_val6;
913         u8 __tcp_agg_vars3;
914 #elif defined(__LITTLE_ENDIAN)
915         u8 __tcp_agg_vars3;
916         u8 __agg_val6;
917         u16 __agg_val5;
918 #endif
919         u32 snd_nxt;
920         u32 rtt_seq;
921         u32 rtt_time;
922         u32 __reserved66;
923         u32 wnd_right_edge;
924         u32 tcp_agg_vars1;
925 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
926 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
927 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
928 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
929 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
930 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
931 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
932 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
933 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
934 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
935 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
936 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
937 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
938 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
939 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
940 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
941 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
942 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
943 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
944 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
945 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
946 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
947 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
948 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
949 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
950 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
951 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
952 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
953 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
954 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
955 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
956 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
957 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
958 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
959 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
960 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
961 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
962 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
963 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
964 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
965 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
966 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
967         u32 snd_max;
968         u32 snd_una;
969         u32 __reserved2;
970 };
971
972 /*
973  * The iscsi aggregative context of Tstorm
974  */
975 struct tstorm_iscsi_ag_context {
976 #if defined(__BIG_ENDIAN)
977         u16 ulp_credit;
978         u8 agg_vars1;
979 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
980 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
981 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
982 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
983 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
984 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
985 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
986 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
987 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
988 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
989 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
990 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
991 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
992 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
993         u8 state;
994 #elif defined(__LITTLE_ENDIAN)
995         u8 state;
996         u8 agg_vars1;
997 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
998 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
999 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1000 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1001 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1002 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1003 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1004 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1005 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
1006 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
1007 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
1008 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
1009 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
1010 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
1011         u16 ulp_credit;
1012 #endif
1013 #if defined(__BIG_ENDIAN)
1014         u16 __agg_val4;
1015         u16 agg_vars2;
1016 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
1017 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
1018 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
1019 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
1020 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
1021 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
1022 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
1023 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
1024 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
1025 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
1026 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
1027 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
1028 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1029 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1030 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
1031 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
1032 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
1033 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
1034 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
1035 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
1036 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1037 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1038 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1039 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1040 #elif defined(__LITTLE_ENDIAN)
1041         u16 agg_vars2;
1042 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
1043 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
1044 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
1045 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
1046 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
1047 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
1048 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
1049 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
1050 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
1051 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
1052 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
1053 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
1054 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1055 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1056 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
1057 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
1058 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
1059 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
1060 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
1061 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
1062 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1063 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1064 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1065 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1066         u16 __agg_val4;
1067 #endif
1068         struct tstorm_tcp_tcp_ag_context_section tcp;
1069 };
1070
1071
1072
1073 /*
1074  * The fcoe aggregative context of Ustorm
1075  */
1076 struct ustorm_fcoe_ag_context {
1077 #if defined(__BIG_ENDIAN)
1078         u8 __aux_counter_flags;
1079         u8 agg_vars2;
1080 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1081 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1082 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1083 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1084 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1085 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1086 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1087 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1088         u8 agg_vars1;
1089 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1090 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1091 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1092 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1093 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1094 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1095 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1096 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1097 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1098 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1099 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1100 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1101         u8 state;
1102 #elif defined(__LITTLE_ENDIAN)
1103         u8 state;
1104         u8 agg_vars1;
1105 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1106 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1107 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1108 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1109 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1110 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1111 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1112 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1113 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1114 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1115 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1116 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1117         u8 agg_vars2;
1118 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1119 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1120 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1121 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1122 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1123 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1124 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1125 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1126         u8 __aux_counter_flags;
1127 #endif
1128 #if defined(__BIG_ENDIAN)
1129         u8 cdu_usage;
1130         u8 agg_misc2;
1131         u16 pbf_tx_seq_ack;
1132 #elif defined(__LITTLE_ENDIAN)
1133         u16 pbf_tx_seq_ack;
1134         u8 agg_misc2;
1135         u8 cdu_usage;
1136 #endif
1137         u32 agg_misc4;
1138 #if defined(__BIG_ENDIAN)
1139         u8 agg_val3_th;
1140         u8 agg_val3;
1141         u16 agg_misc3;
1142 #elif defined(__LITTLE_ENDIAN)
1143         u16 agg_misc3;
1144         u8 agg_val3;
1145         u8 agg_val3_th;
1146 #endif
1147         u32 expired_task_id;
1148         u32 agg_misc4_th;
1149 #if defined(__BIG_ENDIAN)
1150         u16 cq_prod;
1151         u16 cq_cons;
1152 #elif defined(__LITTLE_ENDIAN)
1153         u16 cq_cons;
1154         u16 cq_prod;
1155 #endif
1156 #if defined(__BIG_ENDIAN)
1157         u16 __reserved2;
1158         u8 decision_rules;
1159 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1160 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1161 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1162 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1163 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1164 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1165 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1166 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1167         u8 decision_rule_enable_bits;
1168 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1169 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1170 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1171 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1172 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1173 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1174 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1175 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1176 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1177 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1178 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1179 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1180 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1181 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1182 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1183 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1184 #elif defined(__LITTLE_ENDIAN)
1185         u8 decision_rule_enable_bits;
1186 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1187 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1188 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1189 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1190 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1191 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1192 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1193 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1194 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1195 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1196 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1197 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1198 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1199 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1200 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1201 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1202         u8 decision_rules;
1203 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1204 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1205 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1206 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1207 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1208 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1209 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1210 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1211         u16 __reserved2;
1212 #endif
1213 };
1214
1215
1216 /*
1217  * The iscsi aggregative context of Ustorm
1218  */
1219 struct ustorm_iscsi_ag_context {
1220 #if defined(__BIG_ENDIAN)
1221         u8 __aux_counter_flags;
1222         u8 agg_vars2;
1223 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
1224 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
1225 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
1226 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
1227 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1228 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1229 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1230 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1231         u8 agg_vars1;
1232 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1233 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1234 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1235 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1236 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1237 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1238 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1239 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1240 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
1241 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
1242 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1243 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1244         u8 state;
1245 #elif defined(__LITTLE_ENDIAN)
1246         u8 state;
1247         u8 agg_vars1;
1248 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1249 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1250 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1251 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1252 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1253 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1254 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1255 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1256 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
1257 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
1258 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1259 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1260         u8 agg_vars2;
1261 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
1262 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
1263 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
1264 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
1265 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1266 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1267 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1268 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1269         u8 __aux_counter_flags;
1270 #endif
1271 #if defined(__BIG_ENDIAN)
1272         u8 cdu_usage;
1273         u8 agg_misc2;
1274         u16 __cq_local_comp_itt_val;
1275 #elif defined(__LITTLE_ENDIAN)
1276         u16 __cq_local_comp_itt_val;
1277         u8 agg_misc2;
1278         u8 cdu_usage;
1279 #endif
1280         u32 agg_misc4;
1281 #if defined(__BIG_ENDIAN)
1282         u8 agg_val3_th;
1283         u8 agg_val3;
1284         u16 agg_misc3;
1285 #elif defined(__LITTLE_ENDIAN)
1286         u16 agg_misc3;
1287         u8 agg_val3;
1288         u8 agg_val3_th;
1289 #endif
1290         u32 agg_val1;
1291         u32 agg_misc4_th;
1292 #if defined(__BIG_ENDIAN)
1293         u16 agg_val2_th;
1294         u16 agg_val2;
1295 #elif defined(__LITTLE_ENDIAN)
1296         u16 agg_val2;
1297         u16 agg_val2_th;
1298 #endif
1299 #if defined(__BIG_ENDIAN)
1300         u16 __reserved2;
1301         u8 decision_rules;
1302 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
1303 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
1304 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1305 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1306 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
1307 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
1308 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
1309 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
1310         u8 decision_rule_enable_bits;
1311 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
1312 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
1313 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1314 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1315 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
1316 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
1317 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1318 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1319 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
1320 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
1321 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
1322 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
1323 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1324 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1325 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1326 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1327 #elif defined(__LITTLE_ENDIAN)
1328         u8 decision_rule_enable_bits;
1329 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
1330 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
1331 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1332 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1333 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
1334 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
1335 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1336 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1337 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
1338 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
1339 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
1340 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
1341 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1342 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1343 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1344 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1345         u8 decision_rules;
1346 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
1347 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
1348 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1349 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1350 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
1351 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
1352 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
1353 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
1354         u16 __reserved2;
1355 #endif
1356 };
1357
1358
1359 /*
1360  * The fcoe aggregative context section of Xstorm
1361  */
1362 struct xstorm_fcoe_extra_ag_context_section {
1363 #if defined(__BIG_ENDIAN)
1364         u8 tcp_agg_vars1;
1365 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1366 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1367 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1368 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1369 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1370 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1371 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1372 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1373 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1374 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1375         u8 __reserved_da_cnt;
1376         u16 __mtu;
1377 #elif defined(__LITTLE_ENDIAN)
1378         u16 __mtu;
1379         u8 __reserved_da_cnt;
1380         u8 tcp_agg_vars1;
1381 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1382 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1383 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1384 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1385 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1386 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1387 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1388 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1389 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1390 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1391 #endif
1392         u32 snd_nxt;
1393         u32 tx_wnd;
1394         u32 __reserved55;
1395         u32 local_adv_wnd;
1396 #if defined(__BIG_ENDIAN)
1397         u8 __agg_val8_th;
1398         u8 __tx_dest;
1399         u16 tcp_agg_vars2;
1400 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1401 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1402 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1407 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1408 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1409 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1410 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1411 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1414 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1415 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1416 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1417 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1418 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1423 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1424 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1425 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1426 #elif defined(__LITTLE_ENDIAN)
1427         u16 tcp_agg_vars2;
1428 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1429 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1430 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1431 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1442 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1443 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1444 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1445 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1446 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1447 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1454         u8 __tx_dest;
1455         u8 __agg_val8_th;
1456 #endif
1457         u32 __sq_base_addr_lo;
1458         u32 __sq_base_addr_hi;
1459         u32 __xfrq_base_addr_lo;
1460         u32 __xfrq_base_addr_hi;
1461 #if defined(__BIG_ENDIAN)
1462         u16 __xfrq_cons;
1463         u16 __xfrq_prod;
1464 #elif defined(__LITTLE_ENDIAN)
1465         u16 __xfrq_prod;
1466         u16 __xfrq_cons;
1467 #endif
1468 #if defined(__BIG_ENDIAN)
1469         u8 __tcp_agg_vars5;
1470         u8 __tcp_agg_vars4;
1471         u8 __tcp_agg_vars3;
1472         u8 __reserved_force_pure_ack_cnt;
1473 #elif defined(__LITTLE_ENDIAN)
1474         u8 __reserved_force_pure_ack_cnt;
1475         u8 __tcp_agg_vars3;
1476         u8 __tcp_agg_vars4;
1477         u8 __tcp_agg_vars5;
1478 #endif
1479         u32 __tcp_agg_vars6;
1480 #if defined(__BIG_ENDIAN)
1481         u16 __agg_misc6;
1482         u16 __tcp_agg_vars7;
1483 #elif defined(__LITTLE_ENDIAN)
1484         u16 __tcp_agg_vars7;
1485         u16 __agg_misc6;
1486 #endif
1487         u32 __agg_val10;
1488         u32 __agg_val10_th;
1489 #if defined(__BIG_ENDIAN)
1490         u16 __reserved3;
1491         u8 __reserved2;
1492         u8 __da_only_cnt;
1493 #elif defined(__LITTLE_ENDIAN)
1494         u8 __da_only_cnt;
1495         u8 __reserved2;
1496         u16 __reserved3;
1497 #endif
1498 };
1499
1500 /*
1501  * The fcoe aggregative context of Xstorm
1502  */
1503 struct xstorm_fcoe_ag_context {
1504 #if defined(__BIG_ENDIAN)
1505         u16 agg_val1;
1506         u8 agg_vars1;
1507 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1508 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1509 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1510 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1511 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1512 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1513 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1514 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1515 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1516 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1517 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1518 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1519 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1520 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1521 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1522 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1523         u8 __state;
1524 #elif defined(__LITTLE_ENDIAN)
1525         u8 __state;
1526         u8 agg_vars1;
1527 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1528 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1529 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1530 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1531 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1532 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1533 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1534 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1535 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1536 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1537 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1538 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1539 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1540 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1541 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1542 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1543         u16 agg_val1;
1544 #endif
1545 #if defined(__BIG_ENDIAN)
1546         u8 cdu_reserved;
1547         u8 __agg_vars4;
1548         u8 agg_vars3;
1549 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1550 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1551 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1552 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1553         u8 agg_vars2;
1554 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1555 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1556 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1557 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1558 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1559 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1560 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1561 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1562 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1563 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1564 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1565 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1566 #elif defined(__LITTLE_ENDIAN)
1567         u8 agg_vars2;
1568 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1569 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1570 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1571 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1572 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1573 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1574 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1575 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1576 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1577 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1578 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1579 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1580         u8 agg_vars3;
1581 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1582 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1583 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1584 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1585         u8 __agg_vars4;
1586         u8 cdu_reserved;
1587 #endif
1588         u32 more_to_send;
1589 #if defined(__BIG_ENDIAN)
1590         u16 agg_vars5;
1591 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1592 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1593 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1594 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1595 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1596 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1597 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1598 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1599         u16 sq_cons;
1600 #elif defined(__LITTLE_ENDIAN)
1601         u16 sq_cons;
1602         u16 agg_vars5;
1603 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1604 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1605 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1606 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1607 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1608 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1609 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1610 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1611 #endif
1612         struct xstorm_fcoe_extra_ag_context_section __extra_section;
1613 #if defined(__BIG_ENDIAN)
1614         u16 agg_vars7;
1615 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1616 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1617 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1618 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1619 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1620 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1621 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1622 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1623 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1624 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1625 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1626 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1627 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1628 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1629 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1630 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1631 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1632 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1633 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1634 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1635 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1636 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1637         u8 agg_val3_th;
1638         u8 agg_vars6;
1639 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1640 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1641 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1642 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1643 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1644 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1645 #elif defined(__LITTLE_ENDIAN)
1646         u8 agg_vars6;
1647 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1648 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1649 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1650 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1651 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1652 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1653         u8 agg_val3_th;
1654         u16 agg_vars7;
1655 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1656 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1657 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1658 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1659 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1660 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1661 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1662 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1663 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1664 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1665 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1666 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1667 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1668 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1669 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1670 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1671 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1672 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1673 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1674 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1675 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1676 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1677 #endif
1678 #if defined(__BIG_ENDIAN)
1679         u16 __agg_val11_th;
1680         u16 __agg_val11;
1681 #elif defined(__LITTLE_ENDIAN)
1682         u16 __agg_val11;
1683         u16 __agg_val11_th;
1684 #endif
1685 #if defined(__BIG_ENDIAN)
1686         u8 __reserved1;
1687         u8 __agg_val6_th;
1688         u16 __agg_val9;
1689 #elif defined(__LITTLE_ENDIAN)
1690         u16 __agg_val9;
1691         u8 __agg_val6_th;
1692         u8 __reserved1;
1693 #endif
1694 #if defined(__BIG_ENDIAN)
1695         u16 confq_cons;
1696         u16 confq_prod;
1697 #elif defined(__LITTLE_ENDIAN)
1698         u16 confq_prod;
1699         u16 confq_cons;
1700 #endif
1701         u32 agg_vars8;
1702 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
1703 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
1704 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
1705 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
1706 #if defined(__BIG_ENDIAN)
1707         u16 agg_misc0;
1708         u16 sq_prod;
1709 #elif defined(__LITTLE_ENDIAN)
1710         u16 sq_prod;
1711         u16 agg_misc0;
1712 #endif
1713 #if defined(__BIG_ENDIAN)
1714         u8 agg_val3;
1715         u8 agg_val6;
1716         u8 agg_val5_th;
1717         u8 agg_val5;
1718 #elif defined(__LITTLE_ENDIAN)
1719         u8 agg_val5;
1720         u8 agg_val5_th;
1721         u8 agg_val6;
1722         u8 agg_val3;
1723 #endif
1724 #if defined(__BIG_ENDIAN)
1725         u16 __agg_misc1;
1726         u16 agg_limit1;
1727 #elif defined(__LITTLE_ENDIAN)
1728         u16 agg_limit1;
1729         u16 __agg_misc1;
1730 #endif
1731         u32 completion_seq;
1732         u32 confq_pbl_base_lo;
1733         u32 confq_pbl_base_hi;
1734 };
1735
1736
1737
1738 /*
1739  * The tcp aggregative context section of Xstorm
1740  */
1741 struct xstorm_tcp_tcp_ag_context_section {
1742 #if defined(__BIG_ENDIAN)
1743         u8 tcp_agg_vars1;
1744 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
1745 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
1746 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1747 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1748 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1749 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1750 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
1751 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
1752 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
1753 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
1754         u8 __da_cnt;
1755         u16 mss;
1756 #elif defined(__LITTLE_ENDIAN)
1757         u16 mss;
1758         u8 __da_cnt;
1759         u8 tcp_agg_vars1;
1760 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
1761 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
1762 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1763 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1764 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1765 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1766 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
1767 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
1768 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
1769 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
1770 #endif
1771         u32 snd_nxt;
1772         u32 tx_wnd;
1773         u32 snd_una;
1774         u32 local_adv_wnd;
1775 #if defined(__BIG_ENDIAN)
1776         u8 __agg_val8_th;
1777         u8 __tx_dest;
1778         u16 tcp_agg_vars2;
1779 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
1780 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
1781 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
1782 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
1783 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
1784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
1785 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1787 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1788 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1789 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
1790 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
1791 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
1792 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
1793 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1794 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1795 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
1796 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
1797 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1798 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1803 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1804 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1805 #elif defined(__LITTLE_ENDIAN)
1806         u16 tcp_agg_vars2;
1807 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
1808 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
1809 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
1810 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
1811 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
1812 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
1813 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1817 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
1818 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
1819 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
1820 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
1821 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1822 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1823 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
1824 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
1825 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1826 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1827 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1833         u8 __tx_dest;
1834         u8 __agg_val8_th;
1835 #endif
1836         u32 ack_to_far_end;
1837         u32 rto_timer;
1838         u32 ka_timer;
1839         u32 ts_to_echo;
1840 #if defined(__BIG_ENDIAN)
1841         u16 __agg_val7_th;
1842         u16 __agg_val7;
1843 #elif defined(__LITTLE_ENDIAN)
1844         u16 __agg_val7;
1845         u16 __agg_val7_th;
1846 #endif
1847 #if defined(__BIG_ENDIAN)
1848         u8 __tcp_agg_vars5;
1849         u8 __tcp_agg_vars4;
1850         u8 __tcp_agg_vars3;
1851         u8 __force_pure_ack_cnt;
1852 #elif defined(__LITTLE_ENDIAN)
1853         u8 __force_pure_ack_cnt;
1854         u8 __tcp_agg_vars3;
1855         u8 __tcp_agg_vars4;
1856         u8 __tcp_agg_vars5;
1857 #endif
1858         u32 tcp_agg_vars6;
1859 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
1860 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
1861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
1862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
1863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
1864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
1865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
1866 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
1867 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
1868 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
1869 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
1870 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
1871 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
1872 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
1873 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
1874 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
1875 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
1876 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
1877 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
1878 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
1879 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
1880 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
1881 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
1882 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
1883 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
1884 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
1885 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
1886 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
1887 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
1888 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
1889 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
1890 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
1891 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
1892 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
1893 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
1894 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
1895 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
1896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
1897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
1898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
1899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
1900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
1901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
1902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
1903 #if defined(__BIG_ENDIAN)
1904         u16 __agg_misc6;
1905         u16 __tcp_agg_vars7;
1906 #elif defined(__LITTLE_ENDIAN)
1907         u16 __tcp_agg_vars7;
1908         u16 __agg_misc6;
1909 #endif
1910         u32 __agg_val10;
1911         u32 __agg_val10_th;
1912 #if defined(__BIG_ENDIAN)
1913         u16 __reserved3;
1914         u8 __reserved2;
1915         u8 __da_only_cnt;
1916 #elif defined(__LITTLE_ENDIAN)
1917         u8 __da_only_cnt;
1918         u8 __reserved2;
1919         u16 __reserved3;
1920 #endif
1921 };
1922
1923 /*
1924  * The iscsi aggregative context of Xstorm
1925  */
1926 struct xstorm_iscsi_ag_context {
1927 #if defined(__BIG_ENDIAN)
1928         u16 agg_val1;
1929         u8 agg_vars1;
1930 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1931 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1932 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1933 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1934 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1935 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1936 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1937 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1938 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1939 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1940 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
1941 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
1942 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1943 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1944 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
1945 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
1946         u8 state;
1947 #elif defined(__LITTLE_ENDIAN)
1948         u8 state;
1949         u8 agg_vars1;
1950 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1951 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1952 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1953 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1954 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1955 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1956 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1957 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1958 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1959 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1960 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
1961 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
1962 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1963 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1964 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
1965 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
1966         u16 agg_val1;
1967 #endif
1968 #if defined(__BIG_ENDIAN)
1969         u8 cdu_reserved;
1970         u8 __agg_vars4;
1971         u8 agg_vars3;
1972 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1973 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1974 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
1975 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
1976         u8 agg_vars2;
1977 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
1978 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
1979 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1980 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1981 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1982 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1983 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1984 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1985 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1986 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1987 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1988 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1989 #elif defined(__LITTLE_ENDIAN)
1990         u8 agg_vars2;
1991 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
1992 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
1993 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1994 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1995 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1996 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1997 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1998 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1999 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2000 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2001 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
2002 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
2003         u8 agg_vars3;
2004 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2005 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2006 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2007 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2008         u8 __agg_vars4;
2009         u8 cdu_reserved;
2010 #endif
2011         u32 more_to_send;
2012 #if defined(__BIG_ENDIAN)
2013         u16 agg_vars5;
2014 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2015 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2016 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2017 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2018 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2019 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2020 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2021 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2022         u16 sq_cons;
2023 #elif defined(__LITTLE_ENDIAN)
2024         u16 sq_cons;
2025         u16 agg_vars5;
2026 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2027 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2028 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2029 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2030 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2031 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2032 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2033 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2034 #endif
2035         struct xstorm_tcp_tcp_ag_context_section tcp;
2036 #if defined(__BIG_ENDIAN)
2037         u16 agg_vars7;
2038 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2039 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2040 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2041 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2042 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2043 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2044 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2045 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2046 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
2047 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
2048 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2049 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2050 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2051 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2052 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2053 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2054 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2055 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2056 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2057 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2058 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2059 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2060         u8 agg_val3_th;
2061         u8 agg_vars6;
2062 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2063 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2064 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2065 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2066 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2067 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2068 #elif defined(__LITTLE_ENDIAN)
2069         u8 agg_vars6;
2070 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2071 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2072 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2073 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2074 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2075 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2076         u8 agg_val3_th;
2077         u16 agg_vars7;
2078 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2079 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2080 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2081 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2082 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2083 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2084 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2085 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2086 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
2087 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
2088 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2089 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2090 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2091 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2092 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2093 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2094 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2095 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2096 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2097 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2098 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2099 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2100 #endif
2101 #if defined(__BIG_ENDIAN)
2102         u16 __agg_val11_th;
2103         u16 __gen_data;
2104 #elif defined(__LITTLE_ENDIAN)
2105         u16 __gen_data;
2106         u16 __agg_val11_th;
2107 #endif
2108 #if defined(__BIG_ENDIAN)
2109         u8 __reserved1;
2110         u8 __agg_val6_th;
2111         u16 __agg_val9;
2112 #elif defined(__LITTLE_ENDIAN)
2113         u16 __agg_val9;
2114         u8 __agg_val6_th;
2115         u8 __reserved1;
2116 #endif
2117 #if defined(__BIG_ENDIAN)
2118         u16 hq_prod;
2119         u16 hq_cons;
2120 #elif defined(__LITTLE_ENDIAN)
2121         u16 hq_cons;
2122         u16 hq_prod;
2123 #endif
2124         u32 agg_vars8;
2125 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
2126 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
2127 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
2128 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24
2129 #if defined(__BIG_ENDIAN)
2130         u16 r2tq_prod;
2131         u16 sq_prod;
2132 #elif defined(__LITTLE_ENDIAN)
2133         u16 sq_prod;
2134         u16 r2tq_prod;
2135 #endif
2136 #if defined(__BIG_ENDIAN)
2137         u8 agg_val3;
2138         u8 agg_val6;
2139         u8 agg_val5_th;
2140         u8 agg_val5;
2141 #elif defined(__LITTLE_ENDIAN)
2142         u8 agg_val5;
2143         u8 agg_val5_th;
2144         u8 agg_val6;
2145         u8 agg_val3;
2146 #endif
2147 #if defined(__BIG_ENDIAN)
2148         u16 __agg_misc1;
2149         u16 agg_limit1;
2150 #elif defined(__LITTLE_ENDIAN)
2151         u16 agg_limit1;
2152         u16 __agg_misc1;
2153 #endif
2154         u32 hq_cons_tcp_seq;
2155         u32 exp_stat_sn;
2156         u32 rst_seq_num;
2157 };
2158
2159
2160 /*
2161  * The L5cm aggregative context of XStorm
2162  */
2163 struct xstorm_l5cm_ag_context {
2164 #if defined(__BIG_ENDIAN)
2165         u16 agg_val1;
2166         u8 agg_vars1;
2167 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
2168 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
2169 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
2170 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
2171 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
2172 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
2173 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
2174 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
2175 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
2176 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
2177 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5)
2178 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5
2179 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
2180 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
2181 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
2182 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
2183         u8 state;
2184 #elif defined(__LITTLE_ENDIAN)
2185         u8 state;
2186         u8 agg_vars1;
2187 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
2188 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
2189 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
2190 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
2191 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
2192 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
2193 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
2194 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
2195 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
2196 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
2197 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5)
2198 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5
2199 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
2200 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
2201 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
2202 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
2203         u16 agg_val1;
2204 #endif
2205 #if defined(__BIG_ENDIAN)
2206         u8 cdu_reserved;
2207         u8 __agg_vars4;
2208         u8 agg_vars3;
2209 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2210 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2211 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2212 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2213         u8 agg_vars2;
2214 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0)
2215 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0
2216 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
2217 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
2218 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3)
2219 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3
2220 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2221 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2222 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2223 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2224 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7)
2225 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7
2226 #elif defined(__LITTLE_ENDIAN)
2227         u8 agg_vars2;
2228 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0)
2229 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0
2230 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
2231 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
2232 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3)
2233 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3
2234 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2235 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2236 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2237 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2238 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7)
2239 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7
2240         u8 agg_vars3;
2241 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2242 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2243 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2244 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2245         u8 __agg_vars4;
2246         u8 cdu_reserved;
2247 #endif
2248         u32 more_to_send;
2249 #if defined(__BIG_ENDIAN)
2250         u16 agg_vars5;
2251 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2252 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2253 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2254 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2255 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2256 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2257 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2258 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2259         u16 agg_val4_th;
2260 #elif defined(__LITTLE_ENDIAN)
2261         u16 agg_val4_th;
2262         u16 agg_vars5;
2263 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2264 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2265 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2266 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2267 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2268 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2269 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2270 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2271 #endif
2272         struct xstorm_tcp_tcp_ag_context_section tcp;
2273 #if defined(__BIG_ENDIAN)
2274         u16 agg_vars7;
2275 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2276 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2277 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2278 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2279 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2280 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2281 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2282 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2283 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8)
2284 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8
2285 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2286 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2287 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2288 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2289 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2290 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2291 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2292 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2293 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2294 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2295 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2296 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2297         u8 agg_val3_th;
2298         u8 agg_vars6;
2299 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2300 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2301 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2302 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2303 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2304 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2305 #elif defined(__LITTLE_ENDIAN)
2306         u8 agg_vars6;
2307 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2308 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2309 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2310 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2311 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2312 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2313         u8 agg_val3_th;
2314         u16 agg_vars7;
2315 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2316 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2317 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2318 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2319 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2320 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2321 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2322 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2323 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8)
2324 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8
2325 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2326 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2327 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2328 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2329 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2330 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2331 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2332 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2333 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2334 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2335 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2336 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2337 #endif
2338 #if defined(__BIG_ENDIAN)
2339         u16 __agg_val11_th;
2340         u16 __gen_data;
2341 #elif defined(__LITTLE_ENDIAN)
2342         u16 __gen_data;
2343         u16 __agg_val11_th;
2344 #endif
2345 #if defined(__BIG_ENDIAN)
2346         u8 __reserved1;
2347         u8 __agg_val6_th;
2348         u16 __agg_val9;
2349 #elif defined(__LITTLE_ENDIAN)
2350         u16 __agg_val9;
2351         u8 __agg_val6_th;
2352         u8 __reserved1;
2353 #endif
2354 #if defined(__BIG_ENDIAN)
2355         u16 agg_val2_th;
2356         u16 agg_val2;
2357 #elif defined(__LITTLE_ENDIAN)
2358         u16 agg_val2;
2359         u16 agg_val2_th;
2360 #endif
2361         u32 agg_vars8;
2362 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
2363 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2_SHIFT 0
2364 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
2365 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3_SHIFT 24
2366 #if defined(__BIG_ENDIAN)
2367         u16 agg_misc0;
2368         u16 agg_val4;
2369 #elif defined(__LITTLE_ENDIAN)
2370         u16 agg_val4;
2371         u16 agg_misc0;
2372 #endif
2373 #if defined(__BIG_ENDIAN)
2374         u8 agg_val3;
2375         u8 agg_val6;
2376         u8 agg_val5_th;
2377         u8 agg_val5;
2378 #elif defined(__LITTLE_ENDIAN)
2379         u8 agg_val5;
2380         u8 agg_val5_th;
2381         u8 agg_val6;
2382         u8 agg_val3;
2383 #endif
2384 #if defined(__BIG_ENDIAN)
2385         u16 __agg_misc1;
2386         u16 agg_limit1;
2387 #elif defined(__LITTLE_ENDIAN)
2388         u16 agg_limit1;
2389         u16 __agg_misc1;
2390 #endif
2391         u32 completion_seq;
2392         u32 agg_misc4;
2393         u32 rst_seq_num;
2394 };
2395
2396 /*
2397  * ABTS info $$KEEP_ENDIANNESS$$
2398  */
2399 struct fcoe_abts_info {
2400         __le16 aborted_task_id;
2401         __le16 reserved0;
2402         __le32 reserved1;
2403 };
2404
2405
2406 /*
2407  * Fixed size structure in order to plant it in Union structure
2408  * $$KEEP_ENDIANNESS$$
2409  */
2410 struct fcoe_abts_rsp_union {
2411         u8 r_ctl;
2412         u8 rsrv[3];
2413         __le32 abts_rsp_payload[7];
2414 };
2415
2416
2417 /*
2418  * 4 regs size $$KEEP_ENDIANNESS$$
2419  */
2420 struct fcoe_bd_ctx {
2421         __le32 buf_addr_hi;
2422         __le32 buf_addr_lo;
2423         __le16 buf_len;
2424         __le16 rsrv0;
2425         __le16 flags;
2426         __le16 rsrv1;
2427 };
2428
2429
2430 /*
2431  * FCoE cached sges context $$KEEP_ENDIANNESS$$
2432  */
2433 struct fcoe_cached_sge_ctx {
2434         struct regpair cur_buf_addr;
2435         __le16 cur_buf_rem;
2436         __le16 second_buf_rem;
2437         struct regpair second_buf_addr;
2438 };
2439
2440
2441 /*
2442  * Cleanup info $$KEEP_ENDIANNESS$$
2443  */
2444 struct fcoe_cleanup_info {
2445         __le16 cleaned_task_id;
2446         __le16 rolled_tx_seq_cnt;
2447         __le32 rolled_tx_data_offset;
2448 };
2449
2450
2451 /*
2452  * Fcp RSP flags $$KEEP_ENDIANNESS$$
2453  */
2454 struct fcoe_fcp_rsp_flags {
2455         u8 flags;
2456 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
2457 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
2458 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
2459 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
2460 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
2461 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
2462 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
2463 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
2464 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
2465 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
2466 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
2467 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
2468 };
2469
2470 /*
2471  * Fcp RSP payload $$KEEP_ENDIANNESS$$
2472  */
2473 struct fcoe_fcp_rsp_payload {
2474         struct regpair reserved0;
2475         __le32 fcp_resid;
2476         u8 scsi_status_code;
2477         struct fcoe_fcp_rsp_flags fcp_flags;
2478         __le16 retry_delay_timer;
2479         __le32 fcp_rsp_len;
2480         __le32 fcp_sns_len;
2481 };
2482
2483 /*
2484  * Fixed size structure in order to plant it in Union structure
2485  * $$KEEP_ENDIANNESS$$
2486  */
2487 struct fcoe_fcp_rsp_union {
2488         struct fcoe_fcp_rsp_payload payload;
2489         struct regpair reserved0;
2490 };
2491
2492 /*
2493  * FC header $$KEEP_ENDIANNESS$$
2494  */
2495 struct fcoe_fc_hdr {
2496         u8 s_id[3];
2497         u8 cs_ctl;
2498         u8 d_id[3];
2499         u8 r_ctl;
2500         __le16 seq_cnt;
2501         u8 df_ctl;
2502         u8 seq_id;
2503         u8 f_ctl[3];
2504         u8 type;
2505         __le32 parameters;
2506         __le16 rx_id;
2507         __le16 ox_id;
2508 };
2509
2510 /*
2511  * FC header union $$KEEP_ENDIANNESS$$
2512  */
2513 struct fcoe_mp_rsp_union {
2514         struct fcoe_fc_hdr fc_hdr;
2515         __le32 mp_payload_len;
2516         __le32 rsrv;
2517 };
2518
2519 /*
2520  * Completion information $$KEEP_ENDIANNESS$$
2521  */
2522 union fcoe_comp_flow_info {
2523         struct fcoe_fcp_rsp_union fcp_rsp;
2524         struct fcoe_abts_rsp_union abts_rsp;
2525         struct fcoe_mp_rsp_union mp_rsp;
2526         __le32 opaque[8];
2527 };
2528
2529
2530 /*
2531  * External ABTS info $$KEEP_ENDIANNESS$$
2532  */
2533 struct fcoe_ext_abts_info {
2534         __le32 rsrv0[6];
2535         struct fcoe_abts_info ctx;
2536 };
2537
2538
2539 /*
2540  * External cleanup info $$KEEP_ENDIANNESS$$
2541  */
2542 struct fcoe_ext_cleanup_info {
2543         __le32 rsrv0[6];
2544         struct fcoe_cleanup_info ctx;
2545 };
2546
2547
2548 /*
2549  * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
2550  */
2551 struct fcoe_fw_tx_seq_ctx {
2552         __le32 data_offset;
2553         __le16 seq_cnt;
2554         __le16 rsrv0;
2555 };
2556
2557 /*
2558  * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
2559  */
2560 struct fcoe_ext_fw_tx_seq_ctx {
2561         __le32 rsrv0[6];
2562         struct fcoe_fw_tx_seq_ctx ctx;
2563 };
2564
2565
2566 /*
2567  * FCoE multiple sges context $$KEEP_ENDIANNESS$$
2568  */
2569 struct fcoe_mul_sges_ctx {
2570         struct regpair cur_sge_addr;
2571         __le16 cur_sge_off;
2572         u8 cur_sge_idx;
2573         u8 sgl_size;
2574 };
2575
2576 /*
2577  * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
2578  */
2579 struct fcoe_ext_mul_sges_ctx {
2580         struct fcoe_mul_sges_ctx mul_sgl;
2581         struct regpair rsrv0;
2582 };
2583
2584
2585 /*
2586  * FCP CMD payload $$KEEP_ENDIANNESS$$
2587  */
2588 struct fcoe_fcp_cmd_payload {
2589         __le32 opaque[8];
2590 };
2591
2592
2593
2594
2595
2596 /*
2597  * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
2598  */
2599 struct fcoe_fcp_xfr_rdy_payload {
2600         __le32 burst_len;
2601         __le32 data_ro;
2602 };
2603
2604
2605 /*
2606  * FC frame $$KEEP_ENDIANNESS$$
2607  */
2608 struct fcoe_fc_frame {
2609         struct fcoe_fc_hdr fc_hdr;
2610         __le32 reserved0[2];
2611 };
2612
2613
2614
2615
2616 /*
2617  * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
2618  */
2619 union fcoe_kcqe_params {
2620         __le32 reserved0[4];
2621 };
2622
2623 /*
2624  * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
2625  */
2626 struct fcoe_kcqe {
2627         __le32 fcoe_conn_id;
2628         __le32 completion_status;
2629         __le32 fcoe_conn_context_id;
2630         union fcoe_kcqe_params params;
2631         __le16 qe_self_seq;
2632         u8 op_code;
2633         u8 flags;
2634 #define FCOE_KCQE_RESERVED0 (0x7<<0)
2635 #define FCOE_KCQE_RESERVED0_SHIFT 0
2636 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
2637 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
2638 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
2639 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
2640 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
2641 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
2642 };
2643
2644
2645
2646 /*
2647  * FCoE KWQE header $$KEEP_ENDIANNESS$$
2648  */
2649 struct fcoe_kwqe_header {
2650         u8 op_code;
2651         u8 flags;
2652 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
2653 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
2654 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
2655 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
2656 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
2657 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
2658 };
2659
2660 /*
2661  * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
2662  */
2663 struct fcoe_kwqe_init1 {
2664         __le16 num_tasks;
2665         struct fcoe_kwqe_header hdr;
2666         __le32 task_list_pbl_addr_lo;
2667         __le32 task_list_pbl_addr_hi;
2668         __le32 dummy_buffer_addr_lo;
2669         __le32 dummy_buffer_addr_hi;
2670         __le16 sq_num_wqes;
2671         __le16 rq_num_wqes;
2672         __le16 rq_buffer_log_size;
2673         __le16 cq_num_wqes;
2674         __le16 mtu;
2675         u8 num_sessions_log;
2676         u8 flags;
2677 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
2678 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
2679 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
2680 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
2681 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
2682 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
2683 };
2684
2685 /*
2686  * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
2687  */
2688 struct fcoe_kwqe_init2 {
2689         u8 hsi_major_version;
2690         u8 hsi_minor_version;
2691         struct fcoe_kwqe_header hdr;
2692         __le32 hash_tbl_pbl_addr_lo;
2693         __le32 hash_tbl_pbl_addr_hi;
2694         __le32 t2_hash_tbl_addr_lo;
2695         __le32 t2_hash_tbl_addr_hi;
2696         __le32 t2_ptr_hash_tbl_addr_lo;
2697         __le32 t2_ptr_hash_tbl_addr_hi;
2698         __le32 free_list_count;
2699 };
2700
2701 /*
2702  * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
2703  */
2704 struct fcoe_kwqe_init3 {
2705         __le16 reserved0;
2706         struct fcoe_kwqe_header hdr;
2707         __le32 error_bit_map_lo;
2708         __le32 error_bit_map_hi;
2709         u8 perf_config;
2710         u8 reserved21[3];
2711         __le32 reserved2[4];
2712 };
2713
2714 /*
2715  * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
2716  */
2717 struct fcoe_kwqe_conn_offload1 {
2718         __le16 fcoe_conn_id;
2719         struct fcoe_kwqe_header hdr;
2720         __le32 sq_addr_lo;
2721         __le32 sq_addr_hi;
2722         __le32 rq_pbl_addr_lo;
2723         __le32 rq_pbl_addr_hi;
2724         __le32 rq_first_pbe_addr_lo;
2725         __le32 rq_first_pbe_addr_hi;
2726         __le16 rq_prod;
2727         __le16 reserved0;
2728 };
2729
2730 /*
2731  * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
2732  */
2733 struct fcoe_kwqe_conn_offload2 {
2734         __le16 tx_max_fc_pay_len;
2735         struct fcoe_kwqe_header hdr;
2736         __le32 cq_addr_lo;
2737         __le32 cq_addr_hi;
2738         __le32 xferq_addr_lo;
2739         __le32 xferq_addr_hi;
2740         __le32 conn_db_addr_lo;
2741         __le32 conn_db_addr_hi;
2742         __le32 reserved1;
2743 };
2744
2745 /*
2746  * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
2747  */
2748 struct fcoe_kwqe_conn_offload3 {
2749         __le16 vlan_tag;
2750 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
2751 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
2752 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
2753 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
2754 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
2755 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
2756         struct fcoe_kwqe_header hdr;
2757         u8 s_id[3];
2758         u8 tx_max_conc_seqs_c3;
2759         u8 d_id[3];
2760         u8 flags;
2761 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
2762 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
2763 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
2764 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
2765 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
2766 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
2767 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
2768 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
2769 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
2770 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
2771 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
2772 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
2773 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
2774 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
2775 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
2776 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
2777         __le32 reserved;
2778         __le32 confq_first_pbe_addr_lo;
2779         __le32 confq_first_pbe_addr_hi;
2780         __le16 tx_total_conc_seqs;
2781         __le16 rx_max_fc_pay_len;
2782         __le16 rx_total_conc_seqs;
2783         u8 rx_max_conc_seqs_c3;
2784         u8 rx_open_seqs_exch_c3;
2785 };
2786
2787 /*
2788  * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
2789  */
2790 struct fcoe_kwqe_conn_offload4 {
2791         u8 e_d_tov_timer_val;
2792         u8 reserved2;
2793         struct fcoe_kwqe_header hdr;
2794         u8 src_mac_addr_lo[2];
2795         u8 src_mac_addr_mid[2];
2796         u8 src_mac_addr_hi[2];
2797         u8 dst_mac_addr_hi[2];
2798         u8 dst_mac_addr_lo[2];
2799         u8 dst_mac_addr_mid[2];
2800         __le32 lcq_addr_lo;
2801         __le32 lcq_addr_hi;
2802         __le32 confq_pbl_base_addr_lo;
2803         __le32 confq_pbl_base_addr_hi;
2804 };
2805
2806 /*
2807  * FCoE connection enable request $$KEEP_ENDIANNESS$$
2808  */
2809 struct fcoe_kwqe_conn_enable_disable {
2810         __le16 reserved0;
2811         struct fcoe_kwqe_header hdr;
2812         u8 src_mac_addr_lo[2];
2813         u8 src_mac_addr_mid[2];
2814         u8 src_mac_addr_hi[2];
2815         u16 vlan_tag;
2816 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
2817 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
2818 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
2819 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
2820 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
2821 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
2822         u8 dst_mac_addr_lo[2];
2823         u8 dst_mac_addr_mid[2];
2824         u8 dst_mac_addr_hi[2];
2825         __le16 reserved1;
2826         u8 s_id[3];
2827         u8 vlan_flag;
2828         u8 d_id[3];
2829         u8 reserved3;
2830         __le32 context_id;
2831         __le32 conn_id;
2832         __le32 reserved4;
2833 };
2834
2835 /*
2836  * FCoE connection destroy request $$KEEP_ENDIANNESS$$
2837  */
2838 struct fcoe_kwqe_conn_destroy {
2839         __le16 reserved0;
2840         struct fcoe_kwqe_header hdr;
2841         __le32 context_id;
2842         __le32 conn_id;
2843         __le32 reserved1[5];
2844 };
2845
2846 /*
2847  * FCoe destroy request $$KEEP_ENDIANNESS$$
2848  */
2849 struct fcoe_kwqe_destroy {
2850         __le16 reserved0;
2851         struct fcoe_kwqe_header hdr;
2852         __le32 reserved1[7];
2853 };
2854
2855 /*
2856  * FCoe statistics request $$KEEP_ENDIANNESS$$
2857  */
2858 struct fcoe_kwqe_stat {
2859         __le16 reserved0;
2860         struct fcoe_kwqe_header hdr;
2861         __le32 stat_params_addr_lo;
2862         __le32 stat_params_addr_hi;
2863         __le32 reserved1[5];
2864 };
2865
2866 /*
2867  * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
2868  */
2869 union fcoe_kwqe {
2870         struct fcoe_kwqe_init1 init1;
2871         struct fcoe_kwqe_init2 init2;
2872         struct fcoe_kwqe_init3 init3;
2873         struct fcoe_kwqe_conn_offload1 conn_offload1;
2874         struct fcoe_kwqe_conn_offload2 conn_offload2;
2875         struct fcoe_kwqe_conn_offload3 conn_offload3;
2876         struct fcoe_kwqe_conn_offload4 conn_offload4;
2877         struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
2878         struct fcoe_kwqe_conn_destroy conn_destroy;
2879         struct fcoe_kwqe_destroy destroy;
2880         struct fcoe_kwqe_stat statistics;
2881 };
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898 /*
2899  * TX SGL context $$KEEP_ENDIANNESS$$
2900  */
2901 union fcoe_sgl_union_ctx {
2902         struct fcoe_cached_sge_ctx cached_sge;
2903         struct fcoe_ext_mul_sges_ctx sgl;
2904         __le32 opaque[5];
2905 };
2906
2907 /*
2908  * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
2909  */
2910 struct fcoe_read_flow_info {
2911         union fcoe_sgl_union_ctx sgl_ctx;
2912         __le32 rsrv0[3];
2913 };
2914
2915
2916 /*
2917  * Fcoe stat context $$KEEP_ENDIANNESS$$
2918  */
2919 struct fcoe_s_stat_ctx {
2920         u8 flags;
2921 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
2922 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
2923 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
2924 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
2925 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
2926 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
2927 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
2928 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
2929 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
2930 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
2931 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
2932 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
2933 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
2934 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
2935 };
2936
2937 /*
2938  * Fcoe rx seq context $$KEEP_ENDIANNESS$$
2939  */
2940 struct fcoe_rx_seq_ctx {
2941         u8 seq_id;
2942         struct fcoe_s_stat_ctx s_stat;
2943         __le16 seq_cnt;
2944         __le32 low_exp_ro;
2945         __le32 high_exp_ro;
2946 };
2947
2948
2949 /*
2950  * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
2951  */
2952 union fcoe_rx_wr_union_ctx {
2953         struct fcoe_read_flow_info read_info;
2954         union fcoe_comp_flow_info comp_info;
2955         __le32 opaque[8];
2956 };
2957
2958
2959
2960 /*
2961  * FCoE SQ element $$KEEP_ENDIANNESS$$
2962  */
2963 struct fcoe_sqe {
2964         __le16 wqe;
2965 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
2966 #define FCOE_SQE_TASK_ID_SHIFT 0
2967 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
2968 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
2969 };
2970
2971
2972
2973 /*
2974  * 14 regs $$KEEP_ENDIANNESS$$
2975  */
2976 struct fcoe_tce_tx_only {
2977         union fcoe_sgl_union_ctx sgl_ctx;
2978         __le32 rsrv0;
2979 };
2980
2981 /*
2982  * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
2983  */
2984 union fcoe_tx_wr_rx_rd_union_ctx {
2985         struct fcoe_fc_frame tx_frame;
2986         struct fcoe_fcp_cmd_payload fcp_cmd;
2987         struct fcoe_ext_cleanup_info cleanup;
2988         struct fcoe_ext_abts_info abts;
2989         struct fcoe_ext_fw_tx_seq_ctx tx_seq;
2990         __le32 opaque[8];
2991 };
2992
2993 /*
2994  * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
2995  */
2996 struct fcoe_tce_tx_wr_rx_rd_const {
2997         u8 init_flags;
2998 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
2999 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
3000 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
3001 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
3002 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
3003 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
3004 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
3005 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
3006 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
3007 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
3008         u8 tx_flags;
3009 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
3010 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
3011 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
3012 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
3013 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
3014 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
3015 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
3016 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
3017 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
3018 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
3019         __le16 rsrv3;
3020         __le32 verify_tx_seq;
3021 };
3022
3023 /*
3024  * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
3025  */
3026 struct fcoe_tce_tx_wr_rx_rd {
3027         union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
3028         struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
3029 };
3030
3031 /*
3032  * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
3033  */
3034 struct fcoe_tce_rx_wr_tx_rd_const {
3035         __le32 data_2_trns;
3036         __le32 init_flags;
3037 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
3038 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
3039 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
3040 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
3041 };
3042
3043 /*
3044  * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
3045  */
3046 struct fcoe_tce_rx_wr_tx_rd_var {
3047         __le16 rx_flags;
3048 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
3049 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
3050 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
3051 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
3052 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
3053 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
3054 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
3055 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
3056 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
3057 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
3058 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
3059 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
3060 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
3061 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
3062 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
3063 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
3064         __le16 rx_id;
3065         struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
3066 };
3067
3068 /*
3069  * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
3070  */
3071 struct fcoe_tce_rx_wr_tx_rd {
3072         struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
3073         struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
3074 };
3075
3076 /*
3077  * tce_rx_only $$KEEP_ENDIANNESS$$
3078  */
3079 struct fcoe_tce_rx_only {
3080         struct fcoe_rx_seq_ctx rx_seq_ctx;
3081         union fcoe_rx_wr_union_ctx union_ctx;
3082 };
3083
3084 /*
3085  * task_ctx_entry $$KEEP_ENDIANNESS$$
3086  */
3087 struct fcoe_task_ctx_entry {
3088         struct fcoe_tce_tx_only txwr_only;
3089         struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
3090         struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
3091         struct fcoe_tce_rx_only rxwr_only;
3092 };
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103 /*
3104  * FCoE XFRQ element $$KEEP_ENDIANNESS$$
3105  */
3106 struct fcoe_xfrqe {
3107         __le16 wqe;
3108 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
3109 #define FCOE_XFRQE_TASK_ID_SHIFT 0
3110 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
3111 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
3112 };
3113
3114
3115 /*
3116  * Cached SGEs $$KEEP_ENDIANNESS$$
3117  */
3118 struct common_fcoe_sgl {
3119         struct fcoe_bd_ctx sge[3];
3120 };
3121
3122
3123 /*
3124  * FCoE SQ\XFRQ element
3125  */
3126 struct fcoe_cached_wqe {
3127         struct fcoe_sqe sqe;
3128         struct fcoe_xfrqe xfrqe;
3129 };
3130
3131
3132 /*
3133  * FCoE connection enable\disable params passed by driver to FW in FCoE enable
3134  * ramrod $$KEEP_ENDIANNESS$$
3135  */
3136 struct fcoe_conn_enable_disable_ramrod_params {
3137         struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
3138 };
3139
3140
3141 /*
3142  * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
3143  * $$KEEP_ENDIANNESS$$
3144  */
3145 struct fcoe_conn_offload_ramrod_params {
3146         struct fcoe_kwqe_conn_offload1 offload_kwqe1;
3147         struct fcoe_kwqe_conn_offload2 offload_kwqe2;
3148         struct fcoe_kwqe_conn_offload3 offload_kwqe3;
3149         struct fcoe_kwqe_conn_offload4 offload_kwqe4;
3150 };
3151
3152
3153 struct ustorm_fcoe_mng_ctx {
3154 #if defined(__BIG_ENDIAN)
3155         u8 mid_seq_proc_flag;
3156         u8 tce_in_cam_flag;
3157         u8 tce_on_ior_flag;
3158         u8 en_cached_tce_flag;
3159 #elif defined(__LITTLE_ENDIAN)
3160         u8 en_cached_tce_flag;
3161         u8 tce_on_ior_flag;
3162         u8 tce_in_cam_flag;
3163         u8 mid_seq_proc_flag;
3164 #endif
3165 #if defined(__BIG_ENDIAN)
3166         u8 tce_cam_addr;
3167         u8 cached_conn_flag;
3168         u16 rsrv0;
3169 #elif defined(__LITTLE_ENDIAN)
3170         u16 rsrv0;
3171         u8 cached_conn_flag;
3172         u8 tce_cam_addr;
3173 #endif
3174 #if defined(__BIG_ENDIAN)
3175         u16 dma_tce_ram_addr;
3176         u16 tce_ram_addr;
3177 #elif defined(__LITTLE_ENDIAN)
3178         u16 tce_ram_addr;
3179         u16 dma_tce_ram_addr;
3180 #endif
3181 #if defined(__BIG_ENDIAN)
3182         u16 ox_id;
3183         u16 wr_done_seq;
3184 #elif defined(__LITTLE_ENDIAN)
3185         u16 wr_done_seq;
3186         u16 ox_id;
3187 #endif
3188         struct regpair task_addr;
3189 };
3190
3191 /*
3192  * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and
3193  * used in FCoE context section
3194  */
3195 struct ustorm_fcoe_params {
3196 #if defined(__BIG_ENDIAN)
3197         u16 fcoe_conn_id;
3198         u16 flags;
3199 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
3200 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
3201 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
3202 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
3203 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
3204 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
3205 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
3206 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
3207 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
3208 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
3209 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
3210 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
3211 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
3212 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
3213 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7)
3214 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7
3215 #elif defined(__LITTLE_ENDIAN)
3216         u16 flags;
3217 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
3218 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
3219 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
3220 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
3221 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
3222 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
3223 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
3224 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
3225 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
3226 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
3227 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
3228 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
3229 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
3230 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
3231 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7)
3232 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7
3233         u16 fcoe_conn_id;
3234 #endif
3235 #if defined(__BIG_ENDIAN)
3236         u8 hc_csdm_byte_en;
3237         u8 func_id;
3238         u8 port_id;
3239         u8 vnic_id;
3240 #elif defined(__LITTLE_ENDIAN)
3241         u8 vnic_id;
3242         u8 port_id;
3243         u8 func_id;
3244         u8 hc_csdm_byte_en;
3245 #endif
3246 #if defined(__BIG_ENDIAN)
3247         u16 rx_total_conc_seqs;
3248         u16 rx_max_fc_pay_len;
3249 #elif defined(__LITTLE_ENDIAN)
3250         u16 rx_max_fc_pay_len;
3251         u16 rx_total_conc_seqs;
3252 #endif
3253 #if defined(__BIG_ENDIAN)
3254         u8 task_pbe_idx_off;
3255         u8 task_in_page_log_size;
3256         u16 rx_max_conc_seqs;
3257 #elif defined(__LITTLE_ENDIAN)
3258         u16 rx_max_conc_seqs;
3259         u8 task_in_page_log_size;
3260         u8 task_pbe_idx_off;
3261 #endif
3262 };
3263
3264 /*
3265  * FCoE 16-bits index structure
3266  */
3267 struct fcoe_idx16_fields {
3268         u16 fields;
3269 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
3270 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0
3271 #define FCOE_IDX16_FIELDS_MSB (0x1<<15)
3272 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15
3273 };
3274
3275 /*
3276  * FCoE 16-bits index union
3277  */
3278 union fcoe_idx16_field_union {
3279         struct fcoe_idx16_fields fields;
3280         u16 val;
3281 };
3282
3283 /*
3284  * Parameters required for placement according to SGL
3285  */
3286 struct ustorm_fcoe_data_place_mng {
3287 #if defined(__BIG_ENDIAN)
3288         u16 sge_off;
3289         u8 num_sges;
3290         u8 sge_idx;
3291 #elif defined(__LITTLE_ENDIAN)
3292         u8 sge_idx;
3293         u8 num_sges;
3294         u16 sge_off;
3295 #endif
3296 };
3297
3298 /*
3299  * Parameters required for placement according to SGL
3300  */
3301 struct ustorm_fcoe_data_place {
3302         struct ustorm_fcoe_data_place_mng cached_mng;
3303         struct fcoe_bd_ctx cached_sge[2];
3304 };
3305
3306 /*
3307  * TX processing shall write and RX processing shall read from this section
3308  */
3309 union fcoe_u_tce_tx_wr_rx_rd_union {
3310         struct fcoe_abts_info abts;
3311         struct fcoe_cleanup_info cleanup;
3312         struct fcoe_fw_tx_seq_ctx tx_seq_ctx;
3313         u32 opaque[2];
3314 };
3315
3316 /*
3317  * TX processing shall write and RX processing shall read from this section
3318  */
3319 struct fcoe_u_tce_tx_wr_rx_rd {
3320         union fcoe_u_tce_tx_wr_rx_rd_union union_ctx;
3321         struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
3322 };
3323
3324 struct ustorm_fcoe_tce {
3325         struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd;
3326         struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
3327         struct fcoe_tce_rx_only rxwr;
3328 };
3329
3330 struct ustorm_fcoe_cache_ctx {
3331         u32 rsrv0;
3332         struct ustorm_fcoe_data_place data_place;
3333         struct ustorm_fcoe_tce tce;
3334 };
3335
3336 /*
3337  * Ustorm FCoE Storm Context
3338  */
3339 struct ustorm_fcoe_st_context {
3340         struct ustorm_fcoe_mng_ctx mng_ctx;
3341         struct ustorm_fcoe_params fcoe_params;
3342         struct regpair cq_base_addr;
3343         struct regpair rq_pbl_base;
3344         struct regpair rq_cur_page_addr;
3345         struct regpair confq_pbl_base_addr;
3346         struct regpair conn_db_base;
3347         struct regpair xfrq_base_addr;
3348         struct regpair lcq_base_addr;
3349 #if defined(__BIG_ENDIAN)
3350         union fcoe_idx16_field_union rq_cons;
3351         union fcoe_idx16_field_union rq_prod;
3352 #elif defined(__LITTLE_ENDIAN)
3353         union fcoe_idx16_field_union rq_prod;
3354         union fcoe_idx16_field_union rq_cons;
3355 #endif
3356 #if defined(__BIG_ENDIAN)
3357         u16 xfrq_prod;
3358         u16 cq_cons;
3359 #elif defined(__LITTLE_ENDIAN)
3360         u16 cq_cons;
3361         u16 xfrq_prod;
3362 #endif
3363 #if defined(__BIG_ENDIAN)
3364         u16 lcq_cons;
3365         u16 hc_cram_address;
3366 #elif defined(__LITTLE_ENDIAN)
3367         u16 hc_cram_address;
3368         u16 lcq_cons;
3369 #endif
3370 #if defined(__BIG_ENDIAN)
3371         u16 sq_xfrq_lcq_confq_size;
3372         u16 confq_prod;
3373 #elif defined(__LITTLE_ENDIAN)
3374         u16 confq_prod;
3375         u16 sq_xfrq_lcq_confq_size;
3376 #endif
3377 #if defined(__BIG_ENDIAN)
3378         u8 hc_csdm_agg_int;
3379         u8 rsrv2;
3380         u8 available_rqes;
3381         u8 sp_q_flush_cnt;
3382 #elif defined(__LITTLE_ENDIAN)
3383         u8 sp_q_flush_cnt;
3384         u8 available_rqes;
3385         u8 rsrv2;
3386         u8 hc_csdm_agg_int;
3387 #endif
3388 #if defined(__BIG_ENDIAN)
3389         u16 num_pend_tasks;
3390         u16 pbf_ack_ram_addr;
3391 #elif defined(__LITTLE_ENDIAN)
3392         u16 pbf_ack_ram_addr;
3393         u16 num_pend_tasks;
3394 #endif
3395         struct ustorm_fcoe_cache_ctx cache_ctx;
3396 };
3397
3398 /*
3399  * The FCoE non-aggregative context of Tstorm
3400  */
3401 struct tstorm_fcoe_st_context {
3402         struct regpair reserved0;
3403         struct regpair reserved1;
3404 };
3405
3406 /*
3407  * Ethernet context section
3408  */
3409 struct xstorm_fcoe_eth_context_section {
3410 #if defined(__BIG_ENDIAN)
3411         u8 remote_addr_4;
3412         u8 remote_addr_5;
3413         u8 local_addr_0;
3414         u8 local_addr_1;
3415 #elif defined(__LITTLE_ENDIAN)
3416         u8 local_addr_1;
3417         u8 local_addr_0;
3418         u8 remote_addr_5;
3419         u8 remote_addr_4;
3420 #endif
3421 #if defined(__BIG_ENDIAN)
3422         u8 remote_addr_0;
3423         u8 remote_addr_1;
3424         u8 remote_addr_2;
3425         u8 remote_addr_3;
3426 #elif defined(__LITTLE_ENDIAN)
3427         u8 remote_addr_3;
3428         u8 remote_addr_2;
3429         u8 remote_addr_1;
3430         u8 remote_addr_0;
3431 #endif
3432 #if defined(__BIG_ENDIAN)
3433         u16 reserved_vlan_type;
3434         u16 params;
3435 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
3436 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
3437 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
3438 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
3439 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
3440 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
3441 #elif defined(__LITTLE_ENDIAN)
3442         u16 params;
3443 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
3444 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
3445 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
3446 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
3447 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
3448 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
3449         u16 reserved_vlan_type;
3450 #endif
3451 #if defined(__BIG_ENDIAN)
3452         u8 local_addr_2;
3453         u8 local_addr_3;
3454         u8 local_addr_4;
3455         u8 local_addr_5;
3456 #elif defined(__LITTLE_ENDIAN)
3457         u8 local_addr_5;
3458         u8 local_addr_4;
3459         u8 local_addr_3;
3460         u8 local_addr_2;
3461 #endif
3462 };
3463
3464 /*
3465  * Flags used in FCoE context section - 1 byte
3466  */
3467 struct xstorm_fcoe_context_flags {
3468         u8 flags;
3469 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
3470 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
3471 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
3472 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
3473 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3)
3474 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3
3475 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
3476 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
3477 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
3478 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
3479 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
3480 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
3481 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7)
3482 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7
3483 };
3484
3485 struct xstorm_fcoe_tce {
3486         struct fcoe_tce_tx_only txwr;
3487         struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
3488 };
3489
3490 /*
3491  * FCP_DATA parameters required for transmission
3492  */
3493 struct xstorm_fcoe_fcp_data {
3494         u32 io_rem;
3495 #if defined(__BIG_ENDIAN)
3496         u16 cached_sge_off;
3497         u8 cached_num_sges;
3498         u8 cached_sge_idx;
3499 #elif defined(__LITTLE_ENDIAN)
3500         u8 cached_sge_idx;
3501         u8 cached_num_sges;
3502         u16 cached_sge_off;
3503 #endif
3504         u32 buf_addr_hi_0;
3505         u32 buf_addr_lo_0;
3506 #if defined(__BIG_ENDIAN)
3507         u16 num_of_pending_tasks;
3508         u16 buf_len_0;
3509 #elif defined(__LITTLE_ENDIAN)
3510         u16 buf_len_0;
3511         u16 num_of_pending_tasks;
3512 #endif
3513         u32 buf_addr_hi_1;
3514         u32 buf_addr_lo_1;
3515 #if defined(__BIG_ENDIAN)
3516         u16 task_pbe_idx_off;
3517         u16 buf_len_1;
3518 #elif defined(__LITTLE_ENDIAN)
3519         u16 buf_len_1;
3520         u16 task_pbe_idx_off;
3521 #endif
3522         u32 buf_addr_hi_2;
3523         u32 buf_addr_lo_2;
3524 #if defined(__BIG_ENDIAN)
3525         u16 ox_id;
3526         u16 buf_len_2;
3527 #elif defined(__LITTLE_ENDIAN)
3528         u16 buf_len_2;
3529         u16 ox_id;
3530 #endif
3531 };
3532
3533 /*
3534  * vlan configuration
3535  */
3536 struct xstorm_fcoe_vlan_conf {
3537         u8 vlan_conf;
3538 #define XSTORM_FCOE_VLAN_CONF_PRIORITY (0x7<<0)
3539 #define XSTORM_FCOE_VLAN_CONF_PRIORITY_SHIFT 0
3540 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3)
3541 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3
3542 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0xF<<4)
3543 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 4
3544 };
3545
3546 /*
3547  * FCoE 16-bits vlan structure
3548  */
3549 struct fcoe_vlan_fields {
3550         u16 fields;
3551 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
3552 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
3553 #define FCOE_VLAN_FIELDS_CLI (0x1<<12)
3554 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
3555 #define FCOE_VLAN_FIELDS_PRI (0x7<<13)
3556 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
3557 };
3558
3559 /*
3560  * FCoE 16-bits vlan union
3561  */
3562 union fcoe_vlan_field_union {
3563         struct fcoe_vlan_fields fields;
3564         u16 val;
3565 };
3566
3567 /*
3568  * FCoE 16-bits vlan, vif union
3569  */
3570 union fcoe_vlan_vif_field_union {
3571         union fcoe_vlan_field_union vlan;
3572         u16 vif;
3573 };
3574
3575 /*
3576  * FCoE context section
3577  */
3578 struct xstorm_fcoe_context_section {
3579 #if defined(__BIG_ENDIAN)
3580         u8 cs_ctl;
3581         u8 s_id[3];
3582 #elif defined(__LITTLE_ENDIAN)
3583         u8 s_id[3];
3584         u8 cs_ctl;
3585 #endif
3586 #if defined(__BIG_ENDIAN)
3587         u8 rctl;
3588         u8 d_id[3];
3589 #elif defined(__LITTLE_ENDIAN)
3590         u8 d_id[3];
3591         u8 rctl;
3592 #endif
3593 #if defined(__BIG_ENDIAN)
3594         u16 sq_xfrq_lcq_confq_size;
3595         u16 tx_max_fc_pay_len;
3596 #elif defined(__LITTLE_ENDIAN)
3597         u16 tx_max_fc_pay_len;
3598         u16 sq_xfrq_lcq_confq_size;
3599 #endif
3600         u32 lcq_prod;
3601 #if defined(__BIG_ENDIAN)
3602         u8 port_id;
3603         u8 func_id;
3604         u8 seq_id;
3605         struct xstorm_fcoe_context_flags tx_flags;
3606 #elif defined(__LITTLE_ENDIAN)
3607         struct xstorm_fcoe_context_flags tx_flags;
3608         u8 seq_id;
3609         u8 func_id;
3610         u8 port_id;
3611 #endif
3612 #if defined(__BIG_ENDIAN)
3613         u16 mtu;
3614         u8 func_mode;
3615         u8 vnic_id;
3616 #elif defined(__LITTLE_ENDIAN)
3617         u8 vnic_id;
3618         u8 func_mode;
3619         u16 mtu;
3620 #endif
3621         struct regpair confq_curr_page_addr;
3622         struct fcoe_cached_wqe cached_wqe[8];
3623         struct regpair lcq_base_addr;
3624         struct xstorm_fcoe_tce tce;
3625         struct xstorm_fcoe_fcp_data fcp_data;
3626 #if defined(__BIG_ENDIAN)
3627         u8 tx_max_conc_seqs_c3;
3628         u8 vlan_flag;
3629         u8 dcb_val;
3630         u8 data_pb_cmd_size;
3631 #elif defined(__LITTLE_ENDIAN)
3632         u8 data_pb_cmd_size;
3633         u8 dcb_val;
3634         u8 vlan_flag;
3635         u8 tx_max_conc_seqs_c3;
3636 #endif
3637 #if defined(__BIG_ENDIAN)
3638         u16 fcoe_tx_stat_params_ram_addr;
3639         u16 fcoe_tx_fc_seq_ram_addr;
3640 #elif defined(__LITTLE_ENDIAN)
3641         u16 fcoe_tx_fc_seq_ram_addr;
3642         u16 fcoe_tx_stat_params_ram_addr;
3643 #endif
3644 #if defined(__BIG_ENDIAN)
3645         u8 fcp_cmd_line_credit;
3646         u8 eth_hdr_size;
3647         u16 pbf_addr;
3648 #elif defined(__LITTLE_ENDIAN)
3649         u16 pbf_addr;
3650         u8 eth_hdr_size;
3651         u8 fcp_cmd_line_credit;
3652 #endif
3653 #if defined(__BIG_ENDIAN)
3654         union fcoe_vlan_vif_field_union multi_func_val;
3655         u8 page_log_size;
3656         struct xstorm_fcoe_vlan_conf orig_vlan_conf;
3657 #elif defined(__LITTLE_ENDIAN)
3658         struct xstorm_fcoe_vlan_conf orig_vlan_conf;
3659         u8 page_log_size;
3660         union fcoe_vlan_vif_field_union multi_func_val;
3661 #endif
3662 #if defined(__BIG_ENDIAN)
3663         u16 fcp_cmd_frame_size;
3664         u16 pbf_addr_ff;
3665 #elif defined(__LITTLE_ENDIAN)
3666         u16 pbf_addr_ff;
3667         u16 fcp_cmd_frame_size;
3668 #endif
3669 #if defined(__BIG_ENDIAN)
3670         u8 vlan_num;
3671         u8 cos;
3672         u8 cache_xfrq_cons;
3673         u8 cache_sq_cons;
3674 #elif defined(__LITTLE_ENDIAN)
3675         u8 cache_sq_cons;
3676         u8 cache_xfrq_cons;
3677         u8 cos;
3678         u8 vlan_num;
3679 #endif
3680         u32 verify_tx_seq;
3681 };
3682
3683 /*
3684  * Xstorm FCoE Storm Context
3685  */
3686 struct xstorm_fcoe_st_context {
3687         struct xstorm_fcoe_eth_context_section eth;
3688         struct xstorm_fcoe_context_section fcoe;
3689 };
3690
3691 /*
3692  * Fcoe connection context
3693  */
3694 struct fcoe_context {
3695         struct ustorm_fcoe_st_context ustorm_st_context;
3696         struct tstorm_fcoe_st_context tstorm_st_context;
3697         struct xstorm_fcoe_ag_context xstorm_ag_context;
3698         struct tstorm_fcoe_ag_context tstorm_ag_context;
3699         struct ustorm_fcoe_ag_context ustorm_ag_context;
3700         struct timers_block_context timers_context;
3701         struct xstorm_fcoe_st_context xstorm_st_context;
3702 };
3703
3704 /*
3705  * FCoE init params passed by driver to FW in FCoE init ramrod
3706  * $$KEEP_ENDIANNESS$$
3707  */
3708 struct fcoe_init_ramrod_params {
3709         struct fcoe_kwqe_init1 init_kwqe1;
3710         struct fcoe_kwqe_init2 init_kwqe2;
3711         struct fcoe_kwqe_init3 init_kwqe3;
3712         struct regpair eq_pbl_base;
3713         __le32 eq_pbl_size;
3714         __le32 reserved2;
3715         __le16 eq_prod;
3716         __le16 sb_num;
3717         u8 sb_id;
3718         u8 reserved0;
3719         __le16 reserved1;
3720 };
3721
3722 /*
3723  * FCoE statistics params buffer passed by driver to FW in FCoE statistics
3724  * ramrod $$KEEP_ENDIANNESS$$
3725  */
3726 struct fcoe_stat_ramrod_params {
3727         struct fcoe_kwqe_stat stat_kwqe;
3728 };
3729
3730 /*
3731  * CQ DB CQ producer and pending completion counter
3732  */
3733 struct iscsi_cq_db_prod_pnd_cmpltn_cnt {
3734 #if defined(__BIG_ENDIAN)
3735         u16 cntr;
3736         u16 prod;
3737 #elif defined(__LITTLE_ENDIAN)
3738         u16 prod;
3739         u16 cntr;
3740 #endif
3741 };
3742
3743 /*
3744  * CQ DB pending completion ITT array
3745  */
3746 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr {
3747         struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8];
3748 };
3749
3750 /*
3751  * Cstorm CQ sequence to notify array, updated by driver
3752  */
3753 struct iscsi_cq_db_sqn_2_notify_arr {
3754         u16 sqn[8];
3755 };
3756
3757 /*
3758  * Cstorm iSCSI Storm Context
3759  */
3760 struct cstorm_iscsi_st_context {
3761         struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr;
3762         struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr;
3763         struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr;
3764         struct regpair hq_pbl_base;
3765         struct regpair hq_curr_pbe;
3766         struct regpair task_pbl_base;
3767         struct regpair cq_db_base;
3768 #if defined(__BIG_ENDIAN)
3769         u16 hq_bd_itt;
3770         u16 iscsi_conn_id;
3771 #elif defined(__LITTLE_ENDIAN)
3772         u16 iscsi_conn_id;
3773         u16 hq_bd_itt;
3774 #endif
3775         u32 hq_bd_data_segment_len;
3776         u32 hq_bd_buffer_offset;
3777 #if defined(__BIG_ENDIAN)
3778         u8 rsrv;
3779         u8 cq_proc_en_bit_map;
3780         u8 cq_pend_comp_itt_valid_bit_map;
3781         u8 hq_bd_opcode;
3782 #elif defined(__LITTLE_ENDIAN)
3783         u8 hq_bd_opcode;
3784         u8 cq_pend_comp_itt_valid_bit_map;
3785         u8 cq_proc_en_bit_map;
3786         u8 rsrv;
3787 #endif
3788         u32 hq_tcp_seq;
3789 #if defined(__BIG_ENDIAN)
3790         u16 flags;
3791 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
3792 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
3793 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
3794 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
3795 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
3796 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
3797 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
3798 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
3799 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
3800 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
3801 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
3802 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
3803         u16 hq_cons;
3804 #elif defined(__LITTLE_ENDIAN)
3805         u16 hq_cons;
3806         u16 flags;
3807 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
3808 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
3809 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
3810 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
3811 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
3812 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
3813 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
3814 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
3815 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
3816 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
3817 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
3818 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
3819 #endif
3820         struct regpair rsrv1;
3821 };
3822
3823
3824 /*
3825  * SCSI read/write SQ WQE
3826  */
3827 struct iscsi_cmd_pdu_hdr_little_endian {
3828 #if defined(__BIG_ENDIAN)
3829         u8 opcode;
3830         u8 op_attr;
3831 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
3832 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
3833 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
3834 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
3835 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
3836 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
3837 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
3838 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
3839 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
3840 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
3841         u16 rsrv0;
3842 #elif defined(__LITTLE_ENDIAN)
3843         u16 rsrv0;
3844         u8 op_attr;
3845 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
3846 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
3847 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
3848 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
3849 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
3850 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
3851 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
3852 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
3853 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
3854 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
3855         u8 opcode;
3856 #endif
3857         u32 data_fields;
3858 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
3859 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
3860 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
3861 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
3862         struct regpair lun;
3863         u32 itt;
3864         u32 expected_data_transfer_length;
3865         u32 cmd_sn;
3866         u32 exp_stat_sn;
3867         u32 scsi_command_block[4];
3868 };
3869
3870
3871 /*
3872  * Buffer per connection, used in Tstorm
3873  */
3874 struct iscsi_conn_buf {
3875         struct regpair reserved[8];
3876 };
3877
3878
3879 /*
3880  * iSCSI context region, used only in iSCSI
3881  */
3882 struct ustorm_iscsi_rq_db {
3883         struct regpair pbl_base;
3884         struct regpair curr_pbe;
3885 };
3886
3887 /*
3888  * iSCSI context region, used only in iSCSI
3889  */
3890 struct ustorm_iscsi_r2tq_db {
3891         struct regpair pbl_base;
3892         struct regpair curr_pbe;
3893 };
3894
3895 /*
3896  * iSCSI context region, used only in iSCSI
3897  */
3898 struct ustorm_iscsi_cq_db {
3899 #if defined(__BIG_ENDIAN)
3900         u16 cq_sn;
3901         u16 prod;
3902 #elif defined(__LITTLE_ENDIAN)
3903         u16 prod;
3904         u16 cq_sn;
3905 #endif
3906         struct regpair curr_pbe;
3907 };
3908
3909 /*
3910  * iSCSI context region, used only in iSCSI
3911  */
3912 struct rings_db {
3913         struct ustorm_iscsi_rq_db rq;
3914         struct ustorm_iscsi_r2tq_db r2tq;
3915         struct ustorm_iscsi_cq_db cq[8];
3916 #if defined(__BIG_ENDIAN)
3917         u16 rq_prod;
3918         u16 r2tq_prod;
3919 #elif defined(__LITTLE_ENDIAN)
3920         u16 r2tq_prod;
3921         u16 rq_prod;
3922 #endif
3923         struct regpair cq_pbl_base;
3924 };
3925
3926 /*
3927  * iSCSI context region, used only in iSCSI
3928  */
3929 struct ustorm_iscsi_placement_db {
3930         u32 sgl_base_lo;
3931         u32 sgl_base_hi;
3932         u32 local_sge_0_address_hi;
3933         u32 local_sge_0_address_lo;
3934 #if defined(__BIG_ENDIAN)
3935         u16 curr_sge_offset;
3936         u16 local_sge_0_size;
3937 #elif defined(__LITTLE_ENDIAN)
3938         u16 local_sge_0_size;
3939         u16 curr_sge_offset;
3940 #endif
3941         u32 local_sge_1_address_hi;
3942         u32 local_sge_1_address_lo;
3943 #if defined(__BIG_ENDIAN)
3944         u8 exp_padding_2b;
3945         u8 nal_len_3b;
3946         u16 local_sge_1_size;
3947 #elif defined(__LITTLE_ENDIAN)
3948         u16 local_sge_1_size;
3949         u8 nal_len_3b;
3950         u8 exp_padding_2b;
3951 #endif
3952 #if defined(__BIG_ENDIAN)
3953         u8 sgl_size;
3954         u8 local_sge_index_2b;
3955         u16 reserved7;
3956 #elif defined(__LITTLE_ENDIAN)
3957         u16 reserved7;
3958         u8 local_sge_index_2b;
3959         u8 sgl_size;
3960 #endif
3961         u32 rem_pdu;
3962         u32 place_db_bitfield_1;
3963 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0)
3964 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
3965 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24)
3966 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24
3967         u32 place_db_bitfield_2;
3968 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0)
3969 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
3970 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24)
3971 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24
3972         u32 nal;
3973 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0)
3974 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
3975 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24)
3976 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24
3977 };
3978
3979 /*
3980  * Ustorm iSCSI Storm Context
3981  */
3982 struct ustorm_iscsi_st_context {
3983         u32 exp_stat_sn;
3984         u32 exp_data_sn;
3985         struct rings_db ring;
3986         struct regpair task_pbl_base;
3987         struct regpair tce_phy_addr;
3988         struct ustorm_iscsi_placement_db place_db;
3989         u32 reserved8;
3990         u32 rem_rcv_len;
3991 #if defined(__BIG_ENDIAN)
3992         u16 hdr_itt;
3993         u16 iscsi_conn_id;
3994 #elif defined(__LITTLE_ENDIAN)
3995         u16 iscsi_conn_id;
3996         u16 hdr_itt;
3997 #endif
3998         u32 nal_bytes;
3999 #if defined(__BIG_ENDIAN)
4000         u8 hdr_second_byte_union;
4001         u8 bitfield_0;
4002 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
4003 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
4004 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
4005 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
4006 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
4007 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
4008 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
4009 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
4010         u8 task_pdu_cache_index;
4011         u8 task_pbe_cache_index;
4012 #elif defined(__LITTLE_ENDIAN)
4013         u8 task_pbe_cache_index;
4014         u8 task_pdu_cache_index;
4015         u8 bitfield_0;
4016 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
4017 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
4018 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
4019 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
4020 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
4021 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
4022 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
4023 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
4024         u8 hdr_second_byte_union;
4025 #endif
4026 #if defined(__BIG_ENDIAN)
4027         u16 reserved3;
4028         u8 reserved2;
4029         u8 acDecrement;
4030 #elif defined(__LITTLE_ENDIAN)
4031         u8 acDecrement;
4032         u8 reserved2;
4033         u16 reserved3;
4034 #endif
4035         u32 task_stat;
4036 #if defined(__BIG_ENDIAN)
4037         u8 hdr_opcode;
4038         u8 num_cqs;
4039         u16 reserved5;
4040 #elif defined(__LITTLE_ENDIAN)
4041         u16 reserved5;
4042         u8 num_cqs;
4043         u8 hdr_opcode;
4044 #endif
4045         u32 negotiated_rx;
4046 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0)
4047 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
4048 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24)
4049 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24
4050         u32 negotiated_rx_and_flags;
4051 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0)
4052 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
4053 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24)
4054 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24
4055 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25)
4056 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25
4057 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26)
4058 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26
4059 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27)
4060 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27
4061 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28)
4062 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28
4063 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29)
4064 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29
4065 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31)
4066 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31
4067 };
4068
4069 /*
4070  * TCP context region, shared in TOE, RDMA and ISCSI
4071  */
4072 struct tstorm_tcp_st_context_section {
4073         u32 flags1;
4074 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0)
4075 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
4076 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24)
4077 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24
4078 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25)
4079 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25
4080 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26)
4081 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26
4082 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27)
4083 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27
4084 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28)
4085 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28
4086 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29)
4087 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29
4088 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30)
4089 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30
4090 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31)
4091 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31
4092         u32 flags2;
4093 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0)
4094 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
4095 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24)
4096 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24
4097 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25)
4098 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25
4099 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26)
4100 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26
4101 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27)
4102 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27
4103 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28)
4104 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28
4105 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29)
4106 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29
4107 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30)
4108 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30
4109 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31)
4110 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31
4111 #if defined(__BIG_ENDIAN)
4112         u16 mss;
4113         u8 tcp_sm_state;
4114         u8 rto_exp;
4115 #elif defined(__LITTLE_ENDIAN)
4116         u8 rto_exp;
4117         u8 tcp_sm_state;
4118         u16 mss;
4119 #endif
4120         u32 rcv_nxt;
4121         u32 timestamp_recent;
4122         u32 timestamp_recent_time;
4123         u32 cwnd;
4124         u32 ss_thresh;
4125         u32 cwnd_accum;
4126         u32 prev_seg_seq;
4127         u32 expected_rel_seq;
4128         u32 recover;
4129 #if defined(__BIG_ENDIAN)
4130         u8 retransmit_count;
4131         u8 ka_max_probe_count;
4132         u8 persist_probe_count;
4133         u8 ka_probe_count;
4134 #elif defined(__LITTLE_ENDIAN)
4135         u8 ka_probe_count;
4136         u8 persist_probe_count;
4137         u8 ka_max_probe_count;
4138         u8 retransmit_count;
4139 #endif
4140 #if defined(__BIG_ENDIAN)
4141         u8 statistics_counter_id;
4142         u8 ooo_support_mode;
4143         u8 snd_wnd_scale;
4144         u8 dup_ack_count;
4145 #elif defined(__LITTLE_ENDIAN)
4146         u8 dup_ack_count;
4147         u8 snd_wnd_scale;
4148         u8 ooo_support_mode;
4149         u8 statistics_counter_id;
4150 #endif
4151         u32 retransmit_start_time;
4152         u32 ka_timeout;
4153         u32 ka_interval;
4154         u32 isle_start_seq;
4155         u32 isle_end_seq;
4156 #if defined(__BIG_ENDIAN)
4157         u16 second_isle_address;
4158         u16 recent_seg_wnd;
4159 #elif defined(__LITTLE_ENDIAN)
4160         u16 recent_seg_wnd;
4161         u16 second_isle_address;
4162 #endif
4163 #if defined(__BIG_ENDIAN)
4164         u8 max_isles_ever_happened;
4165         u8 isles_number;
4166         u16 last_isle_address;
4167 #elif defined(__LITTLE_ENDIAN)
4168         u16 last_isle_address;
4169         u8 isles_number;
4170         u8 max_isles_ever_happened;
4171 #endif
4172         u32 max_rt_time;
4173 #if defined(__BIG_ENDIAN)
4174         u16 lsb_mac_address;
4175         u16 vlan_id;
4176 #elif defined(__LITTLE_ENDIAN)
4177         u16 vlan_id;
4178         u16 lsb_mac_address;
4179 #endif
4180 #if defined(__BIG_ENDIAN)
4181         u16 msb_mac_address;
4182         u16 mid_mac_address;
4183 #elif defined(__LITTLE_ENDIAN)
4184         u16 mid_mac_address;
4185         u16 msb_mac_address;
4186 #endif
4187         u32 rightmost_received_seq;
4188 };
4189
4190 /*
4191  * Termination variables
4192  */
4193 struct iscsi_term_vars {
4194         u8 BitMap;
4195 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0)
4196 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
4197 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
4198 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
4199 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
4200 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
4201 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6)
4202 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6
4203 #define ISCSI_TERM_VARS_RSRV (0x1<<7)
4204 #define ISCSI_TERM_VARS_RSRV_SHIFT 7
4205 };
4206
4207 /*
4208  * iSCSI context region, used only in iSCSI
4209  */
4210 struct tstorm_iscsi_st_context_section {
4211         u32 nalPayload;
4212         u32 b2nh;
4213 #if defined(__BIG_ENDIAN)
4214         u16 rq_cons;
4215         u8 flags;
4216 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
4217 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
4218 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
4219 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
4220 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
4221 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
4222 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
4223 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
4224 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
4225 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
4226 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
4227 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
4228 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
4229 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
4230         u8 hdr_bytes_2_fetch;
4231 #elif defined(__LITTLE_ENDIAN)
4232         u8 hdr_bytes_2_fetch;
4233         u8 flags;
4234 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
4235 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
4236 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
4237 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
4238 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
4239 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
4240 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
4241 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
4242 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
4243 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
4244 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
4245 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
4246 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
4247 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
4248         u16 rq_cons;
4249 #endif
4250         struct regpair rq_db_phy_addr;
4251 #if defined(__BIG_ENDIAN)
4252         struct iscsi_term_vars term_vars;
4253         u8 rsrv1;
4254         u16 iscsi_conn_id;
4255 #elif defined(__LITTLE_ENDIAN)
4256         u16 iscsi_conn_id;
4257         u8 rsrv1;
4258         struct iscsi_term_vars term_vars;
4259 #endif
4260         u32 process_nxt;
4261 };
4262
4263 /*
4264  * The iSCSI non-aggregative context of Tstorm
4265  */
4266 struct tstorm_iscsi_st_context {
4267         struct tstorm_tcp_st_context_section tcp;
4268         struct tstorm_iscsi_st_context_section iscsi;
4269 };
4270
4271 /*
4272  * Ethernet context section, shared in TOE, RDMA and ISCSI
4273  */
4274 struct xstorm_eth_context_section {
4275 #if defined(__BIG_ENDIAN)
4276         u8 remote_addr_4;
4277         u8 remote_addr_5;
4278         u8 local_addr_0;
4279         u8 local_addr_1;
4280 #elif defined(__LITTLE_ENDIAN)
4281         u8 local_addr_1;
4282         u8 local_addr_0;
4283         u8 remote_addr_5;
4284         u8 remote_addr_4;
4285 #endif
4286 #if defined(__BIG_ENDIAN)
4287         u8 remote_addr_0;
4288         u8 remote_addr_1;
4289         u8 remote_addr_2;
4290         u8 remote_addr_3;
4291 #elif defined(__LITTLE_ENDIAN)
4292         u8 remote_addr_3;
4293         u8 remote_addr_2;
4294         u8 remote_addr_1;
4295         u8 remote_addr_0;
4296 #endif
4297 #if defined(__BIG_ENDIAN)
4298         u16 reserved_vlan_type;
4299         u16 params;
4300 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
4301 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
4302 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
4303 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
4304 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
4305 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
4306 #elif defined(__LITTLE_ENDIAN)
4307         u16 params;
4308 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
4309 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
4310 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
4311 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
4312 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
4313 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
4314         u16 reserved_vlan_type;
4315 #endif
4316 #if defined(__BIG_ENDIAN)
4317         u8 local_addr_2;
4318         u8 local_addr_3;
4319         u8 local_addr_4;
4320         u8 local_addr_5;
4321 #elif defined(__LITTLE_ENDIAN)
4322         u8 local_addr_5;
4323         u8 local_addr_4;
4324         u8 local_addr_3;
4325         u8 local_addr_2;
4326 #endif
4327 };
4328
4329 /*
4330  * IpV4 context section, shared in TOE, RDMA and ISCSI
4331  */
4332 struct xstorm_ip_v4_context_section {
4333 #if defined(__BIG_ENDIAN)
4334         u16 __pbf_hdr_cmd_rsvd_id;
4335         u16 __pbf_hdr_cmd_rsvd_flags_offset;
4336 #elif defined(__LITTLE_ENDIAN)
4337         u16 __pbf_hdr_cmd_rsvd_flags_offset;
4338         u16 __pbf_hdr_cmd_rsvd_id;
4339 #endif
4340 #if defined(__BIG_ENDIAN)
4341         u8 __pbf_hdr_cmd_rsvd_ver_ihl;
4342         u8 tos;
4343         u16 __pbf_hdr_cmd_rsvd_length;
4344 #elif defined(__LITTLE_ENDIAN)
4345         u16 __pbf_hdr_cmd_rsvd_length;
4346         u8 tos;
4347         u8 __pbf_hdr_cmd_rsvd_ver_ihl;
4348 #endif
4349         u32 ip_local_addr;
4350 #if defined(__BIG_ENDIAN)
4351         u8 ttl;
4352         u8 __pbf_hdr_cmd_rsvd_protocol;
4353         u16 __pbf_hdr_cmd_rsvd_csum;
4354 #elif defined(__LITTLE_ENDIAN)
4355         u16 __pbf_hdr_cmd_rsvd_csum;
4356         u8 __pbf_hdr_cmd_rsvd_protocol;
4357         u8 ttl;
4358 #endif
4359         u32 __pbf_hdr_cmd_rsvd_1;
4360         u32 ip_remote_addr;
4361 };
4362
4363 /*
4364  * context section, shared in TOE, RDMA and ISCSI
4365  */
4366 struct xstorm_padded_ip_v4_context_section {
4367         struct xstorm_ip_v4_context_section ip_v4;
4368         u32 reserved1[4];
4369 };
4370
4371 /*
4372  * IpV6 context section, shared in TOE, RDMA and ISCSI
4373  */
4374 struct xstorm_ip_v6_context_section {
4375 #if defined(__BIG_ENDIAN)
4376         u16 pbf_hdr_cmd_rsvd_payload_len;
4377         u8 pbf_hdr_cmd_rsvd_nxt_hdr;
4378         u8 hop_limit;
4379 #elif defined(__LITTLE_ENDIAN)
4380         u8 hop_limit;
4381         u8 pbf_hdr_cmd_rsvd_nxt_hdr;
4382         u16 pbf_hdr_cmd_rsvd_payload_len;
4383 #endif
4384         u32 priority_flow_label;
4385 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0)
4386 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
4387 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20)
4388 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20
4389 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28)
4390 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28
4391         u32 ip_local_addr_lo_hi;
4392         u32 ip_local_addr_lo_lo;
4393         u32 ip_local_addr_hi_hi;
4394         u32 ip_local_addr_hi_lo;
4395         u32 ip_remote_addr_lo_hi;
4396         u32 ip_remote_addr_lo_lo;
4397         u32 ip_remote_addr_hi_hi;
4398         u32 ip_remote_addr_hi_lo;
4399 };
4400
4401 union xstorm_ip_context_section_types {
4402         struct xstorm_padded_ip_v4_context_section padded_ip_v4;
4403         struct xstorm_ip_v6_context_section ip_v6;
4404 };
4405
4406 /*
4407  * TCP context section, shared in TOE, RDMA and ISCSI
4408  */
4409 struct xstorm_tcp_context_section {
4410         u32 snd_max;
4411 #if defined(__BIG_ENDIAN)
4412         u16 remote_port;
4413         u16 local_port;
4414 #elif defined(__LITTLE_ENDIAN)
4415         u16 local_port;
4416         u16 remote_port;
4417 #endif
4418 #if defined(__BIG_ENDIAN)
4419         u8 original_nagle_1b;
4420         u8 ts_enabled;
4421         u16 tcp_params;
4422 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
4423 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
4424 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
4425 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
4426 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
4427 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
4428 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
4429 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
4430 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
4431 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
4432 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
4433 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
4434 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
4435 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
4436 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
4437 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
4438 #elif defined(__LITTLE_ENDIAN)
4439         u16 tcp_params;
4440 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
4441 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
4442 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
4443 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
4444 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
4445 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
4446 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
4447 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
4448 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
4449 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
4450 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
4451 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
4452 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
4453 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
4454 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
4455 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
4456         u8 ts_enabled;
4457         u8 original_nagle_1b;
4458 #endif
4459 #if defined(__BIG_ENDIAN)
4460         u16 pseudo_csum;
4461         u16 window_scaling_factor;
4462 #elif defined(__LITTLE_ENDIAN)
4463         u16 window_scaling_factor;
4464         u16 pseudo_csum;
4465 #endif
4466 #if defined(__BIG_ENDIAN)
4467         u16 reserved2;
4468         u8 statistics_counter_id;
4469         u8 statistics_params;
4470 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
4471 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
4472 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
4473 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
4474 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
4475 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
4476 #elif defined(__LITTLE_ENDIAN)
4477         u8 statistics_params;
4478 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
4479 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
4480 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
4481 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
4482 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
4483 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
4484         u8 statistics_counter_id;
4485         u16 reserved2;
4486 #endif
4487         u32 ts_time_diff;
4488         u32 __next_timer_expir;
4489 };
4490
4491 /*
4492  * Common context section, shared in TOE, RDMA and ISCSI
4493  */
4494 struct xstorm_common_context_section {
4495         struct xstorm_eth_context_section ethernet;
4496         union xstorm_ip_context_section_types ip_union;
4497         struct xstorm_tcp_context_section tcp;
4498 #if defined(__BIG_ENDIAN)
4499         u8 __dcb_val;
4500         u8 flags;
4501 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
4502 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
4503 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
4504 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
4505 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
4506 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
4507 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
4508 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
4509         u8 reserved;
4510         u8 ip_version_1b;
4511 #elif defined(__LITTLE_ENDIAN)
4512         u8 ip_version_1b;
4513         u8 reserved;
4514         u8 flags;
4515 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
4516 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
4517 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
4518 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
4519 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
4520 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
4521 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
4522 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
4523         u8 __dcb_val;
4524 #endif
4525 };
4526
4527 /*
4528  * Flags used in ISCSI context section
4529  */
4530 struct xstorm_iscsi_context_flags {
4531         u8 flags;
4532 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0)
4533 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
4534 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1)
4535 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1
4536 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2)
4537 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2
4538 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3)
4539 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3
4540 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4)
4541 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4
4542 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5)
4543 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5
4544 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6)
4545 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6
4546 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7)
4547 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7
4548 };
4549
4550 struct iscsi_task_context_entry_x {
4551         u32 data_out_buffer_offset;
4552         u32 itt;
4553         u32 data_sn;
4554 };
4555
4556 struct iscsi_task_context_entry_xuc_x_write_only {
4557         u32 tx_r2t_sn;
4558 };
4559
4560 struct iscsi_task_context_entry_xuc_xu_write_both {
4561         u32 sgl_base_lo;
4562         u32 sgl_base_hi;
4563 #if defined(__BIG_ENDIAN)
4564         u8 sgl_size;
4565         u8 sge_index;
4566         u16 sge_offset;
4567 #elif defined(__LITTLE_ENDIAN)
4568         u16 sge_offset;
4569         u8 sge_index;
4570         u8 sgl_size;
4571 #endif
4572 };
4573
4574 /*
4575  * iSCSI context section
4576  */
4577 struct xstorm_iscsi_context_section {
4578         u32 first_burst_length;
4579         u32 max_send_pdu_length;
4580         struct regpair sq_pbl_base;
4581         struct regpair sq_curr_pbe;
4582         struct regpair hq_pbl_base;
4583         struct regpair hq_curr_pbe_base;
4584         struct regpair r2tq_pbl_base;
4585         struct regpair r2tq_curr_pbe_base;
4586         struct regpair task_pbl_base;
4587 #if defined(__BIG_ENDIAN)
4588         u16 data_out_count;
4589         struct xstorm_iscsi_context_flags flags;
4590         u8 task_pbl_cache_idx;
4591 #elif defined(__LITTLE_ENDIAN)
4592         u8 task_pbl_cache_idx;
4593         struct xstorm_iscsi_context_flags flags;
4594         u16 data_out_count;
4595 #endif
4596         u32 seq_more_2_send;
4597         u32 pdu_more_2_send;
4598         struct iscsi_task_context_entry_x temp_tce_x;
4599         struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr;
4600         struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr;
4601         struct regpair lun;
4602         u32 exp_data_transfer_len_ttt;
4603         u32 pdu_data_2_rxmit;
4604         u32 rxmit_bytes_2_dr;
4605 #if defined(__BIG_ENDIAN)
4606         u16 rxmit_sge_offset;
4607         u16 hq_rxmit_cons;
4608 #elif defined(__LITTLE_ENDIAN)
4609         u16 hq_rxmit_cons;
4610         u16 rxmit_sge_offset;
4611 #endif
4612 #if defined(__BIG_ENDIAN)
4613         u16 r2tq_cons;
4614         u8 rxmit_flags;
4615 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
4616 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
4617 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
4618 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
4619 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
4620 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
4621 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
4622 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
4623 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
4624 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
4625 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
4626 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
4627 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
4628 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
4629         u8 rxmit_sge_idx;
4630 #elif defined(__LITTLE_ENDIAN)
4631         u8 rxmit_sge_idx;
4632         u8 rxmit_flags;
4633 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
4634 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
4635 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
4636 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
4637 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
4638 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
4639 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
4640 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
4641 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
4642 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
4643 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
4644 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
4645 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
4646 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
4647         u16 r2tq_cons;
4648 #endif
4649         u32 hq_rxmit_tcp_seq;
4650 };
4651
4652 /*
4653  * Xstorm iSCSI Storm Context
4654  */
4655 struct xstorm_iscsi_st_context {
4656         struct xstorm_common_context_section common;
4657         struct xstorm_iscsi_context_section iscsi;
4658 };
4659
4660 /*
4661  * Iscsi connection context
4662  */
4663 struct iscsi_context {
4664         struct ustorm_iscsi_st_context ustorm_st_context;
4665         struct tstorm_iscsi_st_context tstorm_st_context;
4666         struct xstorm_iscsi_ag_context xstorm_ag_context;
4667         struct tstorm_iscsi_ag_context tstorm_ag_context;
4668         struct cstorm_iscsi_ag_context cstorm_ag_context;
4669         struct ustorm_iscsi_ag_context ustorm_ag_context;
4670         struct timers_block_context timers_context;
4671         struct regpair upb_context;
4672         struct xstorm_iscsi_st_context xstorm_st_context;
4673         struct regpair xpb_context;
4674         struct cstorm_iscsi_st_context cstorm_st_context;
4675 };
4676
4677
4678 /*
4679  * PDU header of an iSCSI DATA-OUT
4680  */
4681 struct iscsi_data_pdu_hdr_little_endian {
4682 #if defined(__BIG_ENDIAN)
4683         u8 opcode;
4684         u8 op_attr;
4685 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4686 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4687 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
4688 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
4689         u16 rsrv0;
4690 #elif defined(__LITTLE_ENDIAN)
4691         u16 rsrv0;
4692         u8 op_attr;
4693 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4694 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4695 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
4696 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
4697         u8 opcode;
4698 #endif
4699         u32 data_fields;
4700 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4701 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4702 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4703 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4704         struct regpair lun;
4705         u32 itt;
4706         u32 ttt;
4707         u32 rsrv2;
4708         u32 exp_stat_sn;
4709         u32 rsrv3;
4710         u32 data_sn;
4711         u32 buffer_offset;
4712         u32 rsrv4;
4713 };
4714
4715
4716 /*
4717  * PDU header of an iSCSI login request
4718  */
4719 struct iscsi_login_req_hdr_little_endian {
4720 #if defined(__BIG_ENDIAN)
4721         u8 opcode;
4722         u8 op_attr;
4723 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
4724 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
4725 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
4726 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
4727 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
4728 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
4729 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4730 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4731 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
4732 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
4733         u8 version_max;
4734         u8 version_min;
4735 #elif defined(__LITTLE_ENDIAN)
4736         u8 version_min;
4737         u8 version_max;
4738         u8 op_attr;
4739 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
4740 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
4741 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
4742 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
4743 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
4744 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
4745 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4746 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4747 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
4748 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
4749         u8 opcode;
4750 #endif
4751         u32 data_fields;
4752 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4753 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4754 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4755 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4756         u32 isid_lo;
4757 #if defined(__BIG_ENDIAN)
4758         u16 isid_hi;
4759         u16 tsih;
4760 #elif defined(__LITTLE_ENDIAN)
4761         u16 tsih;
4762         u16 isid_hi;
4763 #endif
4764         u32 itt;
4765 #if defined(__BIG_ENDIAN)
4766         u16 cid;
4767         u16 rsrv1;
4768 #elif defined(__LITTLE_ENDIAN)
4769         u16 rsrv1;
4770         u16 cid;
4771 #endif
4772         u32 cmd_sn;
4773         u32 exp_stat_sn;
4774         u32 rsrv2[4];
4775 };
4776
4777 /*
4778  * PDU header of an iSCSI logout request
4779  */
4780 struct iscsi_logout_req_hdr_little_endian {
4781 #if defined(__BIG_ENDIAN)
4782         u8 opcode;
4783         u8 op_attr;
4784 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
4785 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
4786 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4787 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4788         u16 rsrv0;
4789 #elif defined(__LITTLE_ENDIAN)
4790         u16 rsrv0;
4791         u8 op_attr;
4792 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
4793 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
4794 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4795 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4796         u8 opcode;
4797 #endif
4798         u32 data_fields;
4799 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4800 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4801 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4802 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4803         u32 rsrv2[2];
4804         u32 itt;
4805 #if defined(__BIG_ENDIAN)
4806         u16 cid;
4807         u16 rsrv1;
4808 #elif defined(__LITTLE_ENDIAN)
4809         u16 rsrv1;
4810         u16 cid;
4811 #endif
4812         u32 cmd_sn;
4813         u32 exp_stat_sn;
4814         u32 rsrv3[4];
4815 };
4816
4817 /*
4818  * PDU header of an iSCSI TMF request
4819  */
4820 struct iscsi_tmf_req_hdr_little_endian {
4821 #if defined(__BIG_ENDIAN)
4822         u8 opcode;
4823         u8 op_attr;
4824 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
4825 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
4826 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4827 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4828         u16 rsrv0;
4829 #elif defined(__LITTLE_ENDIAN)
4830         u16 rsrv0;
4831         u8 op_attr;
4832 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
4833 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
4834 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4835 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4836         u8 opcode;
4837 #endif
4838         u32 data_fields;
4839 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4840 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4841 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4842 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4843         struct regpair lun;
4844         u32 itt;
4845         u32 referenced_task_tag;
4846         u32 cmd_sn;
4847         u32 exp_stat_sn;
4848         u32 ref_cmd_sn;
4849         u32 exp_data_sn;
4850         u32 rsrv2[2];
4851 };
4852
4853 /*
4854  * PDU header of an iSCSI Text request
4855  */
4856 struct iscsi_text_req_hdr_little_endian {
4857 #if defined(__BIG_ENDIAN)
4858         u8 opcode;
4859         u8 op_attr;
4860 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
4861 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4862 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4863 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4864 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
4865 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
4866         u16 rsrv0;
4867 #elif defined(__LITTLE_ENDIAN)
4868         u16 rsrv0;
4869         u8 op_attr;
4870 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
4871 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4872 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4873 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4874 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
4875 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
4876         u8 opcode;
4877 #endif
4878         u32 data_fields;
4879 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4880 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4881 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4882 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4883         struct regpair lun;
4884         u32 itt;
4885         u32 ttt;
4886         u32 cmd_sn;
4887         u32 exp_stat_sn;
4888         u32 rsrv3[4];
4889 };
4890
4891 /*
4892  * PDU header of an iSCSI Nop-Out
4893  */
4894 struct iscsi_nop_out_hdr_little_endian {
4895 #if defined(__BIG_ENDIAN)
4896         u8 opcode;
4897         u8 op_attr;
4898 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4899 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4900 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
4901 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
4902         u16 rsrv0;
4903 #elif defined(__LITTLE_ENDIAN)
4904         u16 rsrv0;
4905         u8 op_attr;
4906 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4907 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4908 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
4909 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
4910         u8 opcode;
4911 #endif
4912         u32 data_fields;
4913 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4914 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4915 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4916 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4917         struct regpair lun;
4918         u32 itt;
4919         u32 ttt;
4920         u32 cmd_sn;
4921         u32 exp_stat_sn;
4922         u32 rsrv3[4];
4923 };
4924
4925 /*
4926  * iscsi pdu headers in little endian form.
4927  */
4928 union iscsi_pdu_headers_little_endian {
4929         u32 fullHeaderSize[12];
4930         struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr;
4931         struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr;
4932         struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr;
4933         struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr;
4934         struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr;
4935         struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr;
4936         struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr;
4937 };
4938
4939 struct iscsi_hq_bd {
4940         union iscsi_pdu_headers_little_endian pdu_header;
4941 #if defined(__BIG_ENDIAN)
4942         u16 reserved1;
4943         u16 lcl_cmp_flg;
4944 #elif defined(__LITTLE_ENDIAN)
4945         u16 lcl_cmp_flg;
4946         u16 reserved1;
4947 #endif
4948         u32 sgl_base_lo;
4949         u32 sgl_base_hi;
4950 #if defined(__BIG_ENDIAN)
4951         u8 sgl_size;
4952         u8 sge_index;
4953         u16 sge_offset;
4954 #elif defined(__LITTLE_ENDIAN)
4955         u16 sge_offset;
4956         u8 sge_index;
4957         u8 sgl_size;
4958 #endif
4959 };
4960
4961
4962 /*
4963  * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$
4964  */
4965 struct iscsi_l2_ooo_data {
4966         __le32 iscsi_cid;
4967         u8 drop_isle;
4968         u8 drop_size;
4969         u8 ooo_opcode;
4970         u8 ooo_isle;
4971         u8 reserved[8];
4972 };
4973
4974
4975
4976
4977
4978
4979 struct iscsi_task_context_entry_xuc_c_write_only {
4980         u32 total_data_acked;
4981 };
4982
4983 struct iscsi_task_context_r2t_table_entry {
4984         u32 ttt;
4985         u32 desired_data_len;
4986 };
4987
4988 struct iscsi_task_context_entry_xuc_u_write_only {
4989         u32 exp_r2t_sn;
4990         struct iscsi_task_context_r2t_table_entry r2t_table[4];
4991 #if defined(__BIG_ENDIAN)
4992         u16 data_in_count;
4993         u8 cq_id;
4994         u8 valid_1b;
4995 #elif defined(__LITTLE_ENDIAN)
4996         u8 valid_1b;
4997         u8 cq_id;
4998         u16 data_in_count;
4999 #endif
5000 };
5001
5002 struct iscsi_task_context_entry_xuc {
5003         struct iscsi_task_context_entry_xuc_c_write_only write_c;
5004         u32 exp_data_transfer_len;
5005         struct iscsi_task_context_entry_xuc_x_write_only write_x;
5006         u32 lun_lo;
5007         struct iscsi_task_context_entry_xuc_xu_write_both write_xu;
5008         u32 lun_hi;
5009         struct iscsi_task_context_entry_xuc_u_write_only write_u;
5010 };
5011
5012 struct iscsi_task_context_entry_u {
5013         u32 exp_r2t_buff_offset;
5014         u32 rem_rcv_len;
5015         u32 exp_data_sn;
5016 };
5017
5018 struct iscsi_task_context_entry {
5019         struct iscsi_task_context_entry_x tce_x;
5020 #if defined(__BIG_ENDIAN)
5021         u16 data_out_count;
5022         u16 rsrv0;
5023 #elif defined(__LITTLE_ENDIAN)
5024         u16 rsrv0;
5025         u16 data_out_count;
5026 #endif
5027         struct iscsi_task_context_entry_xuc tce_xuc;
5028         struct iscsi_task_context_entry_u tce_u;
5029         u32 rsrv1[7];
5030 };
5031
5032
5033
5034
5035
5036
5037
5038
5039 struct iscsi_task_context_entry_xuc_x_init_only {
5040         struct regpair lun;
5041         u32 exp_data_transfer_len;
5042 };
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060 /*
5061  * ipv6 structure
5062  */
5063 struct ip_v6_addr {
5064         u32 ip_addr_lo_lo;
5065         u32 ip_addr_lo_hi;
5066         u32 ip_addr_hi_lo;
5067         u32 ip_addr_hi_hi;
5068 };
5069
5070
5071
5072 /*
5073  * l5cm- connection identification params
5074  */
5075 struct l5cm_conn_addr_params {
5076         u32 pmtu;
5077 #if defined(__BIG_ENDIAN)
5078         u8 remote_addr_3;
5079         u8 remote_addr_2;
5080         u8 remote_addr_1;
5081         u8 remote_addr_0;
5082 #elif defined(__LITTLE_ENDIAN)
5083         u8 remote_addr_0;
5084         u8 remote_addr_1;
5085         u8 remote_addr_2;
5086         u8 remote_addr_3;
5087 #endif
5088 #if defined(__BIG_ENDIAN)
5089         u16 params;
5090 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0)
5091 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0
5092 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1)
5093 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1
5094         u8 remote_addr_5;
5095         u8 remote_addr_4;
5096 #elif defined(__LITTLE_ENDIAN)
5097         u8 remote_addr_4;
5098         u8 remote_addr_5;
5099         u16 params;
5100 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0)
5101 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0
5102 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1)
5103 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1
5104 #endif
5105         struct ip_v6_addr local_ip_addr;
5106         struct ip_v6_addr remote_ip_addr;
5107         u32 ipv6_flow_label_20b;
5108         u32 reserved1;
5109 #if defined(__BIG_ENDIAN)
5110         u16 remote_tcp_port;
5111         u16 local_tcp_port;
5112 #elif defined(__LITTLE_ENDIAN)
5113         u16 local_tcp_port;
5114         u16 remote_tcp_port;
5115 #endif
5116 };
5117
5118 /*
5119  * l5cm-xstorm connection buffer
5120  */
5121 struct l5cm_xstorm_conn_buffer {
5122 #if defined(__BIG_ENDIAN)
5123         u16 rsrv1;
5124         u16 params;
5125 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0)
5126 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0
5127 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5128 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1
5129 #elif defined(__LITTLE_ENDIAN)
5130         u16 params;
5131 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0)
5132 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0
5133 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5134 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1
5135         u16 rsrv1;
5136 #endif
5137 #if defined(__BIG_ENDIAN)
5138         u16 mss;
5139         u16 pseudo_header_checksum;
5140 #elif defined(__LITTLE_ENDIAN)
5141         u16 pseudo_header_checksum;
5142         u16 mss;
5143 #endif
5144         u32 rcv_buf;
5145         u32 rsrv2;
5146         struct regpair context_addr;
5147 };
5148
5149 /*
5150  * l5cm-tstorm connection buffer
5151  */
5152 struct l5cm_tstorm_conn_buffer {
5153         u32 rsrv1[2];
5154 #if defined(__BIG_ENDIAN)
5155         u16 params;
5156 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0)
5157 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0
5158 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5159 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1
5160         u8 ka_max_probe_count;
5161         u8 ka_enable;
5162 #elif defined(__LITTLE_ENDIAN)
5163         u8 ka_enable;
5164         u8 ka_max_probe_count;
5165         u16 params;
5166 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0)
5167 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0
5168 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5169 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1
5170 #endif
5171         u32 ka_timeout;
5172         u32 ka_interval;
5173         u32 max_rt_time;
5174 };
5175
5176 /*
5177  * l5cm connection buffer for active side
5178  */
5179 struct l5cm_active_conn_buffer {
5180         struct l5cm_conn_addr_params conn_addr_buf;
5181         struct l5cm_xstorm_conn_buffer xstorm_conn_buffer;
5182         struct l5cm_tstorm_conn_buffer tstorm_conn_buffer;
5183 };
5184
5185
5186
5187 /*
5188  * The l5cm opaque buffer passed in add new connection ramrod passive side
5189  */
5190 struct l5cm_hash_input_string {
5191         u32 __opaque1;
5192 #if defined(__BIG_ENDIAN)
5193         u16 __opaque3;
5194         u16 __opaque2;
5195 #elif defined(__LITTLE_ENDIAN)
5196         u16 __opaque2;
5197         u16 __opaque3;
5198 #endif
5199         struct ip_v6_addr __opaque4;
5200         struct ip_v6_addr __opaque5;
5201         u32 __opaque6;
5202         u32 __opaque7[5];
5203 };
5204
5205
5206 /*
5207  * syn cookie component
5208  */
5209 struct l5cm_syn_cookie_comp {
5210         u32 __opaque;
5211 };
5212
5213 /*
5214  * data related to listeners of a TCP port
5215  */
5216 struct l5cm_port_listener_data {
5217         u8 params;
5218 #define L5CM_PORT_LISTENER_DATA_ENABLE (0x1<<0)
5219 #define L5CM_PORT_LISTENER_DATA_ENABLE_SHIFT 0
5220 #define L5CM_PORT_LISTENER_DATA_IP_INDEX (0xF<<1)
5221 #define L5CM_PORT_LISTENER_DATA_IP_INDEX_SHIFT 1
5222 #define L5CM_PORT_LISTENER_DATA_NET_FILTER (0x1<<5)
5223 #define L5CM_PORT_LISTENER_DATA_NET_FILTER_SHIFT 5
5224 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE (0x1<<6)
5225 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE_SHIFT 6
5226 #define L5CM_PORT_LISTENER_DATA_MPA_MODE (0x1<<7)
5227 #define L5CM_PORT_LISTENER_DATA_MPA_MODE_SHIFT 7
5228 };
5229
5230 /*
5231  * Opaque structure passed from U to X when final ack arrives
5232  */
5233 struct l5cm_opaque_buf {
5234         u32 __opaque1;
5235         u32 __opaque2;
5236         u32 __opaque3;
5237         u32 __opaque4;
5238         struct l5cm_syn_cookie_comp __opaque5;
5239 #if defined(__BIG_ENDIAN)
5240         u16 rsrv2;
5241         u8 rsrv;
5242         struct l5cm_port_listener_data __opaque6;
5243 #elif defined(__LITTLE_ENDIAN)
5244         struct l5cm_port_listener_data __opaque6;
5245         u8 rsrv;
5246         u16 rsrv2;
5247 #endif
5248 };
5249
5250
5251 /*
5252  * l5cm slow path element
5253  */
5254 struct l5cm_packet_size {
5255         u32 size;
5256         u32 rsrv;
5257 };
5258
5259
5260 /*
5261  * The final-ack union structure in PCS entry after final ack arrived
5262  */
5263 struct l5cm_pcse_ack {
5264         struct l5cm_xstorm_conn_buffer tx_socket_params;
5265         struct l5cm_opaque_buf opaque_buf;
5266         struct l5cm_tstorm_conn_buffer rx_socket_params;
5267 };
5268
5269
5270 /*
5271  * The syn union structure in PCS entry after syn arrived
5272  */
5273 struct l5cm_pcse_syn {
5274         struct l5cm_opaque_buf opaque_buf;
5275         u32 rsrv[12];
5276 };
5277
5278
5279 /*
5280  * pcs entry data for passive connections
5281  */
5282 struct l5cm_pcs_attributes {
5283 #if defined(__BIG_ENDIAN)
5284         u16 pcs_id;
5285         u8 status;
5286         u8 flags;
5287 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0)
5288 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0
5289 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1)
5290 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1
5291 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2)
5292 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2
5293 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3)
5294 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3
5295 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4)
5296 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4
5297 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5)
5298 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5
5299 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6)
5300 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6
5301 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7)
5302 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7
5303 #elif defined(__LITTLE_ENDIAN)
5304         u8 flags;
5305 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0)
5306 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0
5307 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1)
5308 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1
5309 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2)
5310 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2
5311 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3)
5312 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3
5313 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4)
5314 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4
5315 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5)
5316 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5
5317 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6)
5318 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6
5319 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7)
5320 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7
5321         u8 status;
5322         u16 pcs_id;
5323 #endif
5324 };
5325
5326
5327 union l5cm_seg_params {
5328         struct l5cm_pcse_syn syn_seg_params;
5329         struct l5cm_pcse_ack ack_seg_params;
5330 };
5331
5332 /*
5333  * pcs entry data for passive connections
5334  */
5335 struct l5cm_pcs_hdr {
5336         struct l5cm_hash_input_string hash_input_string;
5337         struct l5cm_conn_addr_params conn_addr_buf;
5338         u32 cid;
5339         u32 hash_result;
5340         union l5cm_seg_params seg_params;
5341         struct l5cm_pcs_attributes att;
5342 #if defined(__BIG_ENDIAN)
5343         u16 rsrv;
5344         u16 rx_seg_size;
5345 #elif defined(__LITTLE_ENDIAN)
5346         u16 rx_seg_size;
5347         u16 rsrv;
5348 #endif
5349 };
5350
5351 /*
5352  * pcs entry for passive connections
5353  */
5354 struct l5cm_pcs_entry {
5355         struct l5cm_pcs_hdr hdr;
5356         u8 rx_segment[1516];
5357 };
5358
5359
5360
5361
5362 /*
5363  * l5cm connection parameters
5364  */
5365 union l5cm_reduce_param_union {
5366         u32 opaque1;
5367         u32 opaque2;
5368 };
5369
5370 /*
5371  * l5cm connection parameters
5372  */
5373 struct l5cm_reduce_conn {
5374         union l5cm_reduce_param_union opaque1;
5375         u32 opaque2;
5376 };
5377
5378 /*
5379  * l5cm slow path element
5380  */
5381 union l5cm_specific_data {
5382         u8 protocol_data[8];
5383         struct regpair phy_address;
5384         struct l5cm_packet_size packet_size;
5385         struct l5cm_reduce_conn reduced_conn;
5386 };
5387
5388 /*
5389  * l5 slow path element
5390  */
5391 struct l5cm_spe {
5392         struct spe_hdr hdr;
5393         union l5cm_specific_data data;
5394 };
5395
5396
5397
5398
5399 /*
5400  * Termination variables
5401  */
5402 struct l5cm_term_vars {
5403         u8 BitMap;
5404 #define L5CM_TERM_VARS_TCP_STATE (0xF<<0)
5405 #define L5CM_TERM_VARS_TCP_STATE_SHIFT 0
5406 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
5407 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
5408 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
5409 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
5410 #define L5CM_TERM_VARS_TERM_ON_CHIP (0x1<<6)
5411 #define L5CM_TERM_VARS_TERM_ON_CHIP_SHIFT 6
5412 #define L5CM_TERM_VARS_RSRV (0x1<<7)
5413 #define L5CM_TERM_VARS_RSRV_SHIFT 7
5414 };
5415
5416
5417
5418
5419 /*
5420  * Tstorm Tcp flags
5421  */
5422 struct tstorm_l5cm_tcp_flags {
5423         u16 flags;
5424 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0)
5425 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
5426 #define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12)
5427 #define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12
5428 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13)
5429 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13
5430 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14)
5431 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14
5432 };
5433
5434
5435 /*
5436  * Xstorm Tcp flags
5437  */
5438 struct xstorm_l5cm_tcp_flags {
5439         u8 flags;
5440 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0)
5441 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0
5442 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1)
5443 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1
5444 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2)
5445 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2
5446 #define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3)
5447 #define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3
5448 };
5449
5450
5451
5452 /*
5453  * Out-of-order states
5454  */
5455 enum tcp_ooo_event {
5456         TCP_EVENT_ADD_PEN = 0,
5457         TCP_EVENT_ADD_NEW_ISLE = 1,
5458         TCP_EVENT_ADD_ISLE_RIGHT = 2,
5459         TCP_EVENT_ADD_ISLE_LEFT = 3,
5460         TCP_EVENT_JOIN = 4,
5461         TCP_EVENT_NOP = 5,
5462         MAX_TCP_OOO_EVENT
5463 };
5464
5465
5466 /*
5467  * OOO support modes
5468  */
5469 enum tcp_tstorm_ooo {
5470         TCP_TSTORM_OOO_DROP_AND_PROC_ACK = 0,
5471         TCP_TSTORM_OOO_SEND_PURE_ACK = 1,
5472         TCP_TSTORM_OOO_SUPPORTED = 2,
5473         MAX_TCP_TSTORM_OOO
5474 };
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484 #endif /* __5710_HSI_CNIC_LE__ */