599d178df62ddd0e1289369802c04c18921a1583
[linux-2.6.git] / drivers / net / chelsio / subr.c
1 /*****************************************************************************
2  *                                                                           *
3  * File: subr.c                                                              *
4  * $Revision: 1.27 $                                                         *
5  * $Date: 2005/06/22 01:08:36 $                                              *
6  * Description:                                                              *
7  *  Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  * This program is free software; you can redistribute it and/or modify      *
11  * it under the terms of the GNU General Public License, version 2, as       *
12  * published by the Free Software Foundation.                                *
13  *                                                                           *
14  * You should have received a copy of the GNU General Public License along   *
15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
17  *                                                                           *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
21  *                                                                           *
22  * http://www.chelsio.com                                                    *
23  *                                                                           *
24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
25  * All rights reserved.                                                      *
26  *                                                                           *
27  * Maintainers: maintainers@chelsio.com                                      *
28  *                                                                           *
29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
30  *          Tina Yang               <tainay@chelsio.com>                     *
31  *          Felix Marti             <felix@chelsio.com>                      *
32  *          Scott Bardone           <sbardone@chelsio.com>                   *
33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
34  *          Frank DiMambro          <frank@chelsio.com>                      *
35  *                                                                           *
36  * History:                                                                  *
37  *                                                                           *
38  ****************************************************************************/
39
40 #include "common.h"
41 #include "elmer0.h"
42 #include "regs.h"
43 #include "gmac.h"
44 #include "cphy.h"
45 #include "sge.h"
46 #include "tp.h"
47 #include "espi.h"
48
49 /**
50  *      t1_wait_op_done - wait until an operation is completed
51  *      @adapter: the adapter performing the operation
52  *      @reg: the register to check for completion
53  *      @mask: a single-bit field within @reg that indicates completion
54  *      @polarity: the value of the field when the operation is completed
55  *      @attempts: number of check iterations
56  *      @delay: delay in usecs between iterations
57  *
58  *      Wait until an operation is completed by checking a bit in a register
59  *      up to @attempts times.  Returns %0 if the operation completes and %1
60  *      otherwise.
61  */
62 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
63                            int attempts, int delay)
64 {
65         while (1) {
66                 u32 val = readl(adapter->regs + reg) & mask;
67
68                 if (!!val == polarity)
69                         return 0;
70                 if (--attempts == 0)
71                         return 1;
72                 if (delay)
73                         udelay(delay);
74         }
75 }
76
77 #define TPI_ATTEMPTS 50
78
79 /*
80  * Write a register over the TPI interface (unlocked and locked versions).
81  */
82 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
83 {
84         int tpi_busy;
85
86         writel(addr, adapter->regs + A_TPI_ADDR);
87         writel(value, adapter->regs + A_TPI_WR_DATA);
88         writel(F_TPIWR, adapter->regs + A_TPI_CSR);
89
90         tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
91                                    TPI_ATTEMPTS, 3);
92         if (tpi_busy)
93                 pr_alert("%s: TPI write to 0x%x failed\n",
94                          adapter->name, addr);
95         return tpi_busy;
96 }
97
98 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
99 {
100         int ret;
101
102         spin_lock(&adapter->tpi_lock);
103         ret = __t1_tpi_write(adapter, addr, value);
104         spin_unlock(&adapter->tpi_lock);
105         return ret;
106 }
107
108 /*
109  * Read a register over the TPI interface (unlocked and locked versions).
110  */
111 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
112 {
113         int tpi_busy;
114
115         writel(addr, adapter->regs + A_TPI_ADDR);
116         writel(0, adapter->regs + A_TPI_CSR);
117
118         tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
119                                    TPI_ATTEMPTS, 3);
120         if (tpi_busy)
121                 pr_alert("%s: TPI read from 0x%x failed\n",
122                          adapter->name, addr);
123         else
124                 *valp = readl(adapter->regs + A_TPI_RD_DATA);
125         return tpi_busy;
126 }
127
128 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
129 {
130         int ret;
131
132         spin_lock(&adapter->tpi_lock);
133         ret = __t1_tpi_read(adapter, addr, valp);
134         spin_unlock(&adapter->tpi_lock);
135         return ret;
136 }
137
138 /*
139  * Set a TPI parameter.
140  */
141 static void t1_tpi_par(adapter_t *adapter, u32 value)
142 {
143         writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144 }
145
146 /*
147  * Called when a port's link settings change to propagate the new values to the
148  * associated PHY and MAC.  After performing the common tasks it invokes an
149  * OS-specific handler.
150  */
151 void t1_link_changed(adapter_t *adapter, int port_id)
152 {
153         int link_ok, speed, duplex, fc;
154         struct cphy *phy = adapter->port[port_id].phy;
155         struct link_config *lc = &adapter->port[port_id].link_config;
156
157         phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
158
159         lc->speed = speed < 0 ? SPEED_INVALID : speed;
160         lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
161         if (!(lc->requested_fc & PAUSE_AUTONEG))
162                 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
163
164         if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
165                 /* Set MAC speed, duplex, and flow control to match PHY. */
166                 struct cmac *mac = adapter->port[port_id].mac;
167
168                 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
169                 lc->fc = (unsigned char)fc;
170         }
171         t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
172 }
173
174 static int t1_pci_intr_handler(adapter_t *adapter)
175 {
176         u32 pcix_cause;
177
178         pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
179
180         if (pcix_cause) {
181                 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
182                                        pcix_cause);
183                 t1_fatal_err(adapter);    /* PCI errors are fatal */
184         }
185         return 0;
186 }
187
188 #ifdef CONFIG_CHELSIO_T1_1G
189 #include "fpga_defs.h"
190
191 /*
192  * PHY interrupt handler for FPGA boards.
193  */
194 static int fpga_phy_intr_handler(adapter_t *adapter)
195 {
196         int p;
197         u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
198
199         for_each_port(adapter, p)
200                 if (cause & (1 << p)) {
201                         struct cphy *phy = adapter->port[p].phy;
202                         int phy_cause = phy->ops->interrupt_handler(phy);
203
204                         if (phy_cause & cphy_cause_link_change)
205                                 t1_link_changed(adapter, p);
206                 }
207         writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
208         return 0;
209 }
210
211 /*
212  * Slow path interrupt handler for FPGAs.
213  */
214 static int fpga_slow_intr(adapter_t *adapter)
215 {
216         u32 cause = readl(adapter->regs + A_PL_CAUSE);
217
218         cause &= ~F_PL_INTR_SGE_DATA;
219         if (cause & F_PL_INTR_SGE_ERR)
220                 t1_sge_intr_error_handler(adapter->sge);
221
222         if (cause & FPGA_PCIX_INTERRUPT_GMAC)
223                 fpga_phy_intr_handler(adapter);
224
225         if (cause & FPGA_PCIX_INTERRUPT_TP) {
226                 /*
227                  * FPGA doesn't support MC4 interrupts and it requires
228                  * this odd layer of indirection for MC5.
229                  */
230                 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
231
232                 /* Clear TP interrupt */
233                 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234         }
235         if (cause & FPGA_PCIX_INTERRUPT_PCIX)
236                 t1_pci_intr_handler(adapter);
237
238         /* Clear the interrupts just processed. */
239         if (cause)
240                 writel(cause, adapter->regs + A_PL_CAUSE);
241
242         return cause != 0;
243 }
244 #endif
245
246 /*
247  * Wait until Elmer's MI1 interface is ready for new operations.
248  */
249 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
250 {
251         int attempts = 100, busy;
252
253         do {
254                 u32 val;
255
256                 __t1_tpi_read(adapter, mi1_reg, &val);
257                 busy = val & F_MI1_OP_BUSY;
258                 if (busy)
259                         udelay(10);
260         } while (busy && --attempts);
261         if (busy)
262                 pr_alert("%s: MDIO operation timed out\n", adapter->name);
263         return busy;
264 }
265
266 /*
267  * MI1 MDIO initialization.
268  */
269 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
270 {
271         u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
272         u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
273                 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
274
275         if (!(bi->caps & SUPPORTED_10000baseT_Full))
276                 val |= V_MI1_SOF(1);
277         t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
278 }
279
280 #if defined(CONFIG_CHELSIO_T1_1G)
281 /*
282  * Elmer MI1 MDIO read/write operations.
283  */
284 static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr,
285                          u16 reg_addr)
286 {
287         struct adapter *adapter = dev->ml_priv;
288         u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
289         unsigned int val;
290
291         spin_lock(&adapter->tpi_lock);
292         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
293         __t1_tpi_write(adapter,
294                         A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
295         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
296         __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
297         spin_unlock(&adapter->tpi_lock);
298         return val;
299 }
300
301 static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr,
302                           u16 reg_addr, u16 val)
303 {
304         struct adapter *adapter = dev->ml_priv;
305         u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
306
307         spin_lock(&adapter->tpi_lock);
308         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
309         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
310         __t1_tpi_write(adapter,
311                         A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
312         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
313         spin_unlock(&adapter->tpi_lock);
314         return 0;
315 }
316
317 #if defined(CONFIG_CHELSIO_T1_1G)
318 static const struct mdio_ops mi1_mdio_ops = {
319         .init = mi1_mdio_init,
320         .read = mi1_mdio_read,
321         .write = mi1_mdio_write,
322         .mode_support = MDIO_SUPPORTS_C22
323 };
324 #endif
325
326 #endif
327
328 static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
329                              u16 reg_addr)
330 {
331         struct adapter *adapter = dev->ml_priv;
332         u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
333         unsigned int val;
334
335         spin_lock(&adapter->tpi_lock);
336
337         /* Write the address we want. */
338         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
339         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
340         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
341                        MI1_OP_INDIRECT_ADDRESS);
342         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
343
344         /* Write the operation we want. */
345         __t1_tpi_write(adapter,
346                         A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
347         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
348
349         /* Read the data. */
350         __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
351         spin_unlock(&adapter->tpi_lock);
352         return val;
353 }
354
355 static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr,
356                               int mmd_addr, u16 reg_addr, u16 val)
357 {
358         struct adapter *adapter = dev->ml_priv;
359         u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
360
361         spin_lock(&adapter->tpi_lock);
362
363         /* Write the address we want. */
364         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
365         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
366         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
367                        MI1_OP_INDIRECT_ADDRESS);
368         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
369
370         /* Write the data. */
371         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
372         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
373         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
374         spin_unlock(&adapter->tpi_lock);
375         return 0;
376 }
377
378 static const struct mdio_ops mi1_mdio_ext_ops = {
379         .init = mi1_mdio_init,
380         .read = mi1_mdio_ext_read,
381         .write = mi1_mdio_ext_write,
382         .mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
383 };
384
385 enum {
386         CH_BRD_T110_1CU,
387         CH_BRD_N110_1F,
388         CH_BRD_N210_1F,
389         CH_BRD_T210_1F,
390         CH_BRD_T210_1CU,
391         CH_BRD_N204_4CU,
392 };
393
394 static const struct board_info t1_board[] = {
395         {
396                 .board          = CHBT_BOARD_CHT110,
397                 .port_number    = 1,
398                 .caps           = SUPPORTED_10000baseT_Full,
399                 .chip_term      = CHBT_TERM_T1,
400                 .chip_mac       = CHBT_MAC_PM3393,
401                 .chip_phy       = CHBT_PHY_MY3126,
402                 .clock_core     = 125000000,
403                 .clock_mc3      = 150000000,
404                 .clock_mc4      = 125000000,
405                 .espi_nports    = 1,
406                 .clock_elmer0   = 44,
407                 .mdio_mdien     = 1,
408                 .mdio_mdiinv    = 1,
409                 .mdio_mdc       = 1,
410                 .mdio_phybaseaddr = 1,
411                 .gmac           = &t1_pm3393_ops,
412                 .gphy           = &t1_my3126_ops,
413                 .mdio_ops       = &mi1_mdio_ext_ops,
414                 .desc           = "Chelsio T110 1x10GBase-CX4 TOE",
415         },
416
417         {
418                 .board          = CHBT_BOARD_N110,
419                 .port_number    = 1,
420                 .caps           = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
421                 .chip_term      = CHBT_TERM_T1,
422                 .chip_mac       = CHBT_MAC_PM3393,
423                 .chip_phy       = CHBT_PHY_88X2010,
424                 .clock_core     = 125000000,
425                 .espi_nports    = 1,
426                 .clock_elmer0   = 44,
427                 .mdio_mdien     = 0,
428                 .mdio_mdiinv    = 0,
429                 .mdio_mdc       = 1,
430                 .mdio_phybaseaddr = 0,
431                 .gmac           = &t1_pm3393_ops,
432                 .gphy           = &t1_mv88x201x_ops,
433                 .mdio_ops       = &mi1_mdio_ext_ops,
434                 .desc           = "Chelsio N110 1x10GBaseX NIC",
435         },
436
437         {
438                 .board          = CHBT_BOARD_N210,
439                 .port_number    = 1,
440                 .caps           = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
441                 .chip_term      = CHBT_TERM_T2,
442                 .chip_mac       = CHBT_MAC_PM3393,
443                 .chip_phy       = CHBT_PHY_88X2010,
444                 .clock_core     = 125000000,
445                 .espi_nports    = 1,
446                 .clock_elmer0   = 44,
447                 .mdio_mdien     = 0,
448                 .mdio_mdiinv    = 0,
449                 .mdio_mdc       = 1,
450                 .mdio_phybaseaddr = 0,
451                 .gmac           = &t1_pm3393_ops,
452                 .gphy           = &t1_mv88x201x_ops,
453                 .mdio_ops       = &mi1_mdio_ext_ops,
454                 .desc           = "Chelsio N210 1x10GBaseX NIC",
455         },
456
457         {
458                 .board          = CHBT_BOARD_CHT210,
459                 .port_number    = 1,
460                 .caps           = SUPPORTED_10000baseT_Full,
461                 .chip_term      = CHBT_TERM_T2,
462                 .chip_mac       = CHBT_MAC_PM3393,
463                 .chip_phy       = CHBT_PHY_88X2010,
464                 .clock_core     = 125000000,
465                 .clock_mc3      = 133000000,
466                 .clock_mc4      = 125000000,
467                 .espi_nports    = 1,
468                 .clock_elmer0   = 44,
469                 .mdio_mdien     = 0,
470                 .mdio_mdiinv    = 0,
471                 .mdio_mdc       = 1,
472                 .mdio_phybaseaddr = 0,
473                 .gmac           = &t1_pm3393_ops,
474                 .gphy           = &t1_mv88x201x_ops,
475                 .mdio_ops       = &mi1_mdio_ext_ops,
476                 .desc           = "Chelsio T210 1x10GBaseX TOE",
477         },
478
479         {
480                 .board          = CHBT_BOARD_CHT210,
481                 .port_number    = 1,
482                 .caps           = SUPPORTED_10000baseT_Full,
483                 .chip_term      = CHBT_TERM_T2,
484                 .chip_mac       = CHBT_MAC_PM3393,
485                 .chip_phy       = CHBT_PHY_MY3126,
486                 .clock_core     = 125000000,
487                 .clock_mc3      = 133000000,
488                 .clock_mc4      = 125000000,
489                 .espi_nports    = 1,
490                 .clock_elmer0   = 44,
491                 .mdio_mdien     = 1,
492                 .mdio_mdiinv    = 1,
493                 .mdio_mdc       = 1,
494                 .mdio_phybaseaddr = 1,
495                 .gmac           = &t1_pm3393_ops,
496                 .gphy           = &t1_my3126_ops,
497                 .mdio_ops       = &mi1_mdio_ext_ops,
498                 .desc           = "Chelsio T210 1x10GBase-CX4 TOE",
499         },
500
501 #ifdef CONFIG_CHELSIO_T1_1G
502         {
503                 .board          = CHBT_BOARD_CHN204,
504                 .port_number    = 4,
505                 .caps           = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
506                                 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
507                                 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
508                                   SUPPORTED_PAUSE | SUPPORTED_TP,
509                 .chip_term      = CHBT_TERM_T2,
510                 .chip_mac       = CHBT_MAC_VSC7321,
511                 .chip_phy       = CHBT_PHY_88E1111,
512                 .clock_core     = 100000000,
513                 .espi_nports    = 4,
514                 .clock_elmer0   = 44,
515                 .mdio_mdien     = 0,
516                 .mdio_mdiinv    = 0,
517                 .mdio_mdc       = 0,
518                 .mdio_phybaseaddr = 4,
519                 .gmac           = &t1_vsc7326_ops,
520                 .gphy           = &t1_mv88e1xxx_ops,
521                 .mdio_ops       = &mi1_mdio_ops,
522                 .desc           = "Chelsio N204 4x100/1000BaseT NIC",
523         },
524 #endif
525
526 };
527
528 DEFINE_PCI_DEVICE_TABLE(t1_pci_tbl) = {
529         CH_DEVICE(8, 0, CH_BRD_T110_1CU),
530         CH_DEVICE(8, 1, CH_BRD_T110_1CU),
531         CH_DEVICE(7, 0, CH_BRD_N110_1F),
532         CH_DEVICE(10, 1, CH_BRD_N210_1F),
533         CH_DEVICE(11, 1, CH_BRD_T210_1F),
534         CH_DEVICE(14, 1, CH_BRD_T210_1CU),
535         CH_DEVICE(16, 1, CH_BRD_N204_4CU),
536         { 0 }
537 };
538
539 MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
540
541 /*
542  * Return the board_info structure with a given index.  Out-of-range indices
543  * return NULL.
544  */
545 const struct board_info *t1_get_board_info(unsigned int board_id)
546 {
547         return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
548 }
549
550 struct chelsio_vpd_t {
551         u32 format_version;
552         u8 serial_number[16];
553         u8 mac_base_address[6];
554         u8 pad[2];           /* make multiple-of-4 size requirement explicit */
555 };
556
557 #define EEPROMSIZE        (8 * 1024)
558 #define EEPROM_MAX_POLL   4
559
560 /*
561  * Read SEEPROM. A zero is written to the flag register when the addres is
562  * written to the Control register. The hardware device will set the flag to a
563  * one when 4B have been transferred to the Data register.
564  */
565 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
566 {
567         int i = EEPROM_MAX_POLL;
568         u16 val;
569         u32 v;
570
571         if (addr >= EEPROMSIZE || (addr & 3))
572                 return -EINVAL;
573
574         pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
575         do {
576                 udelay(50);
577                 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
578         } while (!(val & F_VPD_OP_FLAG) && --i);
579
580         if (!(val & F_VPD_OP_FLAG)) {
581                 pr_err("%s: reading EEPROM address 0x%x failed\n",
582                        adapter->name, addr);
583                 return -EIO;
584         }
585         pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
586         *data = cpu_to_le32(v);
587         return 0;
588 }
589
590 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
591 {
592         int addr, ret = 0;
593
594         for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
595                 ret = t1_seeprom_read(adapter, addr,
596                                       (__le32 *)((u8 *)vpd + addr));
597
598         return ret;
599 }
600
601 /*
602  * Read a port's MAC address from the VPD ROM.
603  */
604 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
605 {
606         struct chelsio_vpd_t vpd;
607
608         if (t1_eeprom_vpd_get(adapter, &vpd))
609                 return 1;
610         memcpy(mac_addr, vpd.mac_base_address, 5);
611         mac_addr[5] = vpd.mac_base_address[5] + index;
612         return 0;
613 }
614
615 /*
616  * Set up the MAC/PHY according to the requested link settings.
617  *
618  * If the PHY can auto-negotiate first decide what to advertise, then
619  * enable/disable auto-negotiation as desired and reset.
620  *
621  * If the PHY does not auto-negotiate we just reset it.
622  *
623  * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
624  * otherwise do it later based on the outcome of auto-negotiation.
625  */
626 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
627 {
628         unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
629
630         if (lc->supported & SUPPORTED_Autoneg) {
631                 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
632                 if (fc) {
633                         if (fc == ((PAUSE_RX | PAUSE_TX) &
634                                    (mac->adapter->params.nports < 2)))
635                                 lc->advertising |= ADVERTISED_PAUSE;
636                         else {
637                                 lc->advertising |= ADVERTISED_ASYM_PAUSE;
638                                 if (fc == PAUSE_RX)
639                                         lc->advertising |= ADVERTISED_PAUSE;
640                         }
641                 }
642                 phy->ops->advertise(phy, lc->advertising);
643
644                 if (lc->autoneg == AUTONEG_DISABLE) {
645                         lc->speed = lc->requested_speed;
646                         lc->duplex = lc->requested_duplex;
647                         lc->fc = (unsigned char)fc;
648                         mac->ops->set_speed_duplex_fc(mac, lc->speed,
649                                                       lc->duplex, fc);
650                         /* Also disables autoneg */
651                         phy->state = PHY_AUTONEG_RDY;
652                         phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
653                         phy->ops->reset(phy, 0);
654                 } else {
655                         phy->state = PHY_AUTONEG_EN;
656                         phy->ops->autoneg_enable(phy); /* also resets PHY */
657                 }
658         } else {
659                 phy->state = PHY_AUTONEG_RDY;
660                 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
661                 lc->fc = (unsigned char)fc;
662                 phy->ops->reset(phy, 0);
663         }
664         return 0;
665 }
666
667 /*
668  * External interrupt handler for boards using elmer0.
669  */
670 int t1_elmer0_ext_intr_handler(adapter_t *adapter)
671 {
672         struct cphy *phy;
673         int phy_cause;
674         u32 cause;
675
676         t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
677
678         switch (board_info(adapter)->board) {
679 #ifdef CONFIG_CHELSIO_T1_1G
680         case CHBT_BOARD_CHT204:
681         case CHBT_BOARD_CHT204E:
682         case CHBT_BOARD_CHN204:
683         case CHBT_BOARD_CHT204V: {
684                 int i, port_bit;
685                 for_each_port(adapter, i) {
686                         port_bit = i + 1;
687                         if (!(cause & (1 << port_bit)))
688                                 continue;
689
690                         phy = adapter->port[i].phy;
691                         phy_cause = phy->ops->interrupt_handler(phy);
692                         if (phy_cause & cphy_cause_link_change)
693                                 t1_link_changed(adapter, i);
694                 }
695                 break;
696         }
697         case CHBT_BOARD_CHT101:
698                 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
699                         phy = adapter->port[0].phy;
700                         phy_cause = phy->ops->interrupt_handler(phy);
701                         if (phy_cause & cphy_cause_link_change)
702                                 t1_link_changed(adapter, 0);
703                 }
704                 break;
705         case CHBT_BOARD_7500: {
706                 int p;
707                 /*
708                  * Elmer0's interrupt cause isn't useful here because there is
709                  * only one bit that can be set for all 4 ports.  This means
710                  * we are forced to check every PHY's interrupt status
711                  * register to see who initiated the interrupt.
712                  */
713                 for_each_port(adapter, p) {
714                         phy = adapter->port[p].phy;
715                         phy_cause = phy->ops->interrupt_handler(phy);
716                         if (phy_cause & cphy_cause_link_change)
717                             t1_link_changed(adapter, p);
718                 }
719                 break;
720         }
721 #endif
722         case CHBT_BOARD_CHT210:
723         case CHBT_BOARD_N210:
724         case CHBT_BOARD_N110:
725                 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
726                         phy = adapter->port[0].phy;
727                         phy_cause = phy->ops->interrupt_handler(phy);
728                         if (phy_cause & cphy_cause_link_change)
729                                 t1_link_changed(adapter, 0);
730                 }
731                 break;
732         case CHBT_BOARD_8000:
733         case CHBT_BOARD_CHT110:
734                 if (netif_msg_intr(adapter))
735                         dev_dbg(&adapter->pdev->dev,
736                                 "External interrupt cause 0x%x\n", cause);
737                 if (cause & ELMER0_GP_BIT1) {        /* PMC3393 INTB */
738                         struct cmac *mac = adapter->port[0].mac;
739
740                         mac->ops->interrupt_handler(mac);
741                 }
742                 if (cause & ELMER0_GP_BIT5) {        /* XPAK MOD_DETECT */
743                         u32 mod_detect;
744
745                         t1_tpi_read(adapter,
746                                         A_ELMER0_GPI_STAT, &mod_detect);
747                         if (netif_msg_link(adapter))
748                                 dev_info(&adapter->pdev->dev, "XPAK %s\n",
749                                          mod_detect ? "removed" : "inserted");
750                 }
751                 break;
752         }
753         t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
754         return 0;
755 }
756
757 /* Enables all interrupts. */
758 void t1_interrupts_enable(adapter_t *adapter)
759 {
760         unsigned int i;
761
762         adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
763
764         t1_sge_intr_enable(adapter->sge);
765         t1_tp_intr_enable(adapter->tp);
766         if (adapter->espi) {
767                 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
768                 t1_espi_intr_enable(adapter->espi);
769         }
770
771         /* Enable MAC/PHY interrupts for each port. */
772         for_each_port(adapter, i) {
773                 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
774                 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
775         }
776
777         /* Enable PCIX & external chip interrupts on ASIC boards. */
778         if (t1_is_asic(adapter)) {
779                 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
780
781                 /* PCI-X interrupts */
782                 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
783                                        0xffffffff);
784
785                 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
786                 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
787                 writel(pl_intr, adapter->regs + A_PL_ENABLE);
788         }
789 }
790
791 /* Disables all interrupts. */
792 void t1_interrupts_disable(adapter_t* adapter)
793 {
794         unsigned int i;
795
796         t1_sge_intr_disable(adapter->sge);
797         t1_tp_intr_disable(adapter->tp);
798         if (adapter->espi)
799                 t1_espi_intr_disable(adapter->espi);
800
801         /* Disable MAC/PHY interrupts for each port. */
802         for_each_port(adapter, i) {
803                 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
804                 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
805         }
806
807         /* Disable PCIX & external chip interrupts. */
808         if (t1_is_asic(adapter))
809                 writel(0, adapter->regs + A_PL_ENABLE);
810
811         /* PCI-X interrupts */
812         pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
813
814         adapter->slow_intr_mask = 0;
815 }
816
817 /* Clears all interrupts */
818 void t1_interrupts_clear(adapter_t* adapter)
819 {
820         unsigned int i;
821
822         t1_sge_intr_clear(adapter->sge);
823         t1_tp_intr_clear(adapter->tp);
824         if (adapter->espi)
825                 t1_espi_intr_clear(adapter->espi);
826
827         /* Clear MAC/PHY interrupts for each port. */
828         for_each_port(adapter, i) {
829                 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
830                 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
831         }
832
833         /* Enable interrupts for external devices. */
834         if (t1_is_asic(adapter)) {
835                 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
836
837                 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
838                        adapter->regs + A_PL_CAUSE);
839         }
840
841         /* PCI-X interrupts */
842         pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
843 }
844
845 /*
846  * Slow path interrupt handler for ASICs.
847  */
848 static int asic_slow_intr(adapter_t *adapter)
849 {
850         u32 cause = readl(adapter->regs + A_PL_CAUSE);
851
852         cause &= adapter->slow_intr_mask;
853         if (!cause)
854                 return 0;
855         if (cause & F_PL_INTR_SGE_ERR)
856                 t1_sge_intr_error_handler(adapter->sge);
857         if (cause & F_PL_INTR_TP)
858                 t1_tp_intr_handler(adapter->tp);
859         if (cause & F_PL_INTR_ESPI)
860                 t1_espi_intr_handler(adapter->espi);
861         if (cause & F_PL_INTR_PCIX)
862                 t1_pci_intr_handler(adapter);
863         if (cause & F_PL_INTR_EXT)
864                 t1_elmer0_ext_intr(adapter);
865
866         /* Clear the interrupts just processed. */
867         writel(cause, adapter->regs + A_PL_CAUSE);
868         readl(adapter->regs + A_PL_CAUSE); /* flush writes */
869         return 1;
870 }
871
872 int t1_slow_intr_handler(adapter_t *adapter)
873 {
874 #ifdef CONFIG_CHELSIO_T1_1G
875         if (!t1_is_asic(adapter))
876                 return fpga_slow_intr(adapter);
877 #endif
878         return asic_slow_intr(adapter);
879 }
880
881 /* Power sequencing is a work-around for Intel's XPAKs. */
882 static void power_sequence_xpak(adapter_t* adapter)
883 {
884         u32 mod_detect;
885         u32 gpo;
886
887         /* Check for XPAK */
888         t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
889         if (!(ELMER0_GP_BIT5 & mod_detect)) {
890                 /* XPAK is present */
891                 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
892                 gpo |= ELMER0_GP_BIT18;
893                 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
894         }
895 }
896
897 int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
898                                struct adapter_params *p)
899 {
900         p->chip_version = bi->chip_term;
901         p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
902         if (p->chip_version == CHBT_TERM_T1 ||
903             p->chip_version == CHBT_TERM_T2 ||
904             p->chip_version == CHBT_TERM_FPGA) {
905                 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
906
907                 val = G_TP_PC_REV(val);
908                 if (val == 2)
909                         p->chip_revision = TERM_T1B;
910                 else if (val == 3)
911                         p->chip_revision = TERM_T2;
912                 else
913                         return -1;
914         } else
915                 return -1;
916         return 0;
917 }
918
919 /*
920  * Enable board components other than the Chelsio chip, such as external MAC
921  * and PHY.
922  */
923 static int board_init(adapter_t *adapter, const struct board_info *bi)
924 {
925         switch (bi->board) {
926         case CHBT_BOARD_8000:
927         case CHBT_BOARD_N110:
928         case CHBT_BOARD_N210:
929         case CHBT_BOARD_CHT210:
930                 t1_tpi_par(adapter, 0xf);
931                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
932                 break;
933         case CHBT_BOARD_CHT110:
934                 t1_tpi_par(adapter, 0xf);
935                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
936
937                 /* TBD XXX Might not need.  This fixes a problem
938                  *         described in the Intel SR XPAK errata.
939                  */
940                 power_sequence_xpak(adapter);
941                 break;
942 #ifdef CONFIG_CHELSIO_T1_1G
943         case CHBT_BOARD_CHT204E:
944                 /* add config space write here */
945         case CHBT_BOARD_CHT204:
946         case CHBT_BOARD_CHT204V:
947         case CHBT_BOARD_CHN204:
948                 t1_tpi_par(adapter, 0xf);
949                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
950                 break;
951         case CHBT_BOARD_CHT101:
952         case CHBT_BOARD_7500:
953                 t1_tpi_par(adapter, 0xf);
954                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
955                 break;
956 #endif
957         }
958         return 0;
959 }
960
961 /*
962  * Initialize and configure the Terminator HW modules.  Note that external
963  * MAC and PHYs are initialized separately.
964  */
965 int t1_init_hw_modules(adapter_t *adapter)
966 {
967         int err = -EIO;
968         const struct board_info *bi = board_info(adapter);
969
970         if (!bi->clock_mc4) {
971                 u32 val = readl(adapter->regs + A_MC4_CFG);
972
973                 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
974                 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
975                        adapter->regs + A_MC5_CONFIG);
976         }
977
978         if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
979                                           bi->espi_nports))
980                 goto out_err;
981
982         if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
983                 goto out_err;
984
985         err = t1_sge_configure(adapter->sge, &adapter->params.sge);
986         if (err)
987                 goto out_err;
988
989         err = 0;
990 out_err:
991         return err;
992 }
993
994 /*
995  * Determine a card's PCI mode.
996  */
997 static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
998 {
999         static const unsigned short speed_map[] = { 33, 66, 100, 133 };
1000         u32 pci_mode;
1001
1002         pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1003         p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
1004         p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
1005         p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
1006 }
1007
1008 /*
1009  * Release the structures holding the SW per-Terminator-HW-module state.
1010  */
1011 void t1_free_sw_modules(adapter_t *adapter)
1012 {
1013         unsigned int i;
1014
1015         for_each_port(adapter, i) {
1016                 struct cmac *mac = adapter->port[i].mac;
1017                 struct cphy *phy = adapter->port[i].phy;
1018
1019                 if (mac)
1020                         mac->ops->destroy(mac);
1021                 if (phy)
1022                         phy->ops->destroy(phy);
1023         }
1024
1025         if (adapter->sge)
1026                 t1_sge_destroy(adapter->sge);
1027         if (adapter->tp)
1028                 t1_tp_destroy(adapter->tp);
1029         if (adapter->espi)
1030                 t1_espi_destroy(adapter->espi);
1031 }
1032
1033 static void __devinit init_link_config(struct link_config *lc,
1034                                        const struct board_info *bi)
1035 {
1036         lc->supported = bi->caps;
1037         lc->requested_speed = lc->speed = SPEED_INVALID;
1038         lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
1039         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1040         if (lc->supported & SUPPORTED_Autoneg) {
1041                 lc->advertising = lc->supported;
1042                 lc->autoneg = AUTONEG_ENABLE;
1043                 lc->requested_fc |= PAUSE_AUTONEG;
1044         } else {
1045                 lc->advertising = 0;
1046                 lc->autoneg = AUTONEG_DISABLE;
1047         }
1048 }
1049
1050 /*
1051  * Allocate and initialize the data structures that hold the SW state of
1052  * the Terminator HW modules.
1053  */
1054 int __devinit t1_init_sw_modules(adapter_t *adapter,
1055                                  const struct board_info *bi)
1056 {
1057         unsigned int i;
1058
1059         adapter->params.brd_info = bi;
1060         adapter->params.nports = bi->port_number;
1061         adapter->params.stats_update_period = bi->gmac->stats_update_period;
1062
1063         adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1064         if (!adapter->sge) {
1065                 pr_err("%s: SGE initialization failed\n",
1066                        adapter->name);
1067                 goto error;
1068         }
1069
1070         if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1071                 pr_err("%s: ESPI initialization failed\n",
1072                        adapter->name);
1073                 goto error;
1074         }
1075
1076         adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1077         if (!adapter->tp) {
1078                 pr_err("%s: TP initialization failed\n",
1079                        adapter->name);
1080                 goto error;
1081         }
1082
1083         board_init(adapter, bi);
1084         bi->mdio_ops->init(adapter, bi);
1085         if (bi->gphy->reset)
1086                 bi->gphy->reset(adapter);
1087         if (bi->gmac->reset)
1088                 bi->gmac->reset(adapter);
1089
1090         for_each_port(adapter, i) {
1091                 u8 hw_addr[6];
1092                 struct cmac *mac;
1093                 int phy_addr = bi->mdio_phybaseaddr + i;
1094
1095                 adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
1096                                                         phy_addr, bi->mdio_ops);
1097                 if (!adapter->port[i].phy) {
1098                         pr_err("%s: PHY %d initialization failed\n",
1099                                adapter->name, i);
1100                         goto error;
1101                 }
1102
1103                 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1104                 if (!mac) {
1105                         pr_err("%s: MAC %d initialization failed\n",
1106                                adapter->name, i);
1107                         goto error;
1108                 }
1109
1110                 /*
1111                  * Get the port's MAC addresses either from the EEPROM if one
1112                  * exists or the one hardcoded in the MAC.
1113                  */
1114                 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1115                         mac->ops->macaddress_get(mac, hw_addr);
1116                 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1117                         pr_err("%s: could not read MAC address from VPD ROM\n",
1118                                adapter->port[i].dev->name);
1119                         goto error;
1120                 }
1121                 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1122                 init_link_config(&adapter->port[i].link_config, bi);
1123         }
1124
1125         get_pci_mode(adapter, &adapter->params.pci);
1126         t1_interrupts_clear(adapter);
1127         return 0;
1128
1129 error:
1130         t1_free_sw_modules(adapter);
1131         return -1;
1132 }