5e97a1a71d887a92817d180aa8111f5a5034e098
[linux-2.6.git] / drivers / net / chelsio / sge.c
1 /*****************************************************************************
2  *                                                                           *
3  * File: sge.c                                                               *
4  * $Revision: 1.26 $                                                         *
5  * $Date: 2005/06/21 18:29:48 $                                              *
6  * Description:                                                              *
7  *  DMA engine.                                                              *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  * This program is free software; you can redistribute it and/or modify      *
11  * it under the terms of the GNU General Public License, version 2, as       *
12  * published by the Free Software Foundation.                                *
13  *                                                                           *
14  * You should have received a copy of the GNU General Public License along   *
15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
17  *                                                                           *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
21  *                                                                           *
22  * http://www.chelsio.com                                                    *
23  *                                                                           *
24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
25  * All rights reserved.                                                      *
26  *                                                                           *
27  * Maintainers: maintainers@chelsio.com                                      *
28  *                                                                           *
29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
30  *          Tina Yang               <tainay@chelsio.com>                     *
31  *          Felix Marti             <felix@chelsio.com>                      *
32  *          Scott Bardone           <sbardone@chelsio.com>                   *
33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
34  *          Frank DiMambro          <frank@chelsio.com>                      *
35  *                                                                           *
36  * History:                                                                  *
37  *                                                                           *
38  ****************************************************************************/
39
40 #include "common.h"
41
42 #include <linux/types.h>
43 #include <linux/errno.h>
44 #include <linux/pci.h>
45 #include <linux/ktime.h>
46 #include <linux/netdevice.h>
47 #include <linux/etherdevice.h>
48 #include <linux/if_vlan.h>
49 #include <linux/skbuff.h>
50 #include <linux/init.h>
51 #include <linux/mm.h>
52 #include <linux/tcp.h>
53 #include <linux/ip.h>
54 #include <linux/in.h>
55 #include <linux/if_arp.h>
56
57 #include "cpl5_cmd.h"
58 #include "sge.h"
59 #include "regs.h"
60 #include "espi.h"
61
62 /* This belongs in if_ether.h */
63 #define ETH_P_CPL5 0xf
64
65 #define SGE_CMDQ_N              2
66 #define SGE_FREELQ_N            2
67 #define SGE_CMDQ0_E_N           1024
68 #define SGE_CMDQ1_E_N           128
69 #define SGE_FREEL_SIZE          4096
70 #define SGE_JUMBO_FREEL_SIZE    512
71 #define SGE_FREEL_REFILL_THRESH 16
72 #define SGE_RESPQ_E_N           1024
73 #define SGE_INTRTIMER_NRES      1000
74 #define SGE_RX_SM_BUF_SIZE      1536
75 #define SGE_TX_DESC_MAX_PLEN    16384
76
77 #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
78
79 /*
80  * Period of the TX buffer reclaim timer.  This timer does not need to run
81  * frequently as TX buffers are usually reclaimed by new TX packets.
82  */
83 #define TX_RECLAIM_PERIOD (HZ / 4)
84
85 #define M_CMD_LEN       0x7fffffff
86 #define V_CMD_LEN(v)    (v)
87 #define G_CMD_LEN(v)    ((v) & M_CMD_LEN)
88 #define V_CMD_GEN1(v)   ((v) << 31)
89 #define V_CMD_GEN2(v)   (v)
90 #define F_CMD_DATAVALID (1 << 1)
91 #define F_CMD_SOP       (1 << 2)
92 #define V_CMD_EOP(v)    ((v) << 3)
93
94 /*
95  * Command queue, receive buffer list, and response queue descriptors.
96  */
97 #if defined(__BIG_ENDIAN_BITFIELD)
98 struct cmdQ_e {
99         u32 addr_lo;
100         u32 len_gen;
101         u32 flags;
102         u32 addr_hi;
103 };
104
105 struct freelQ_e {
106         u32 addr_lo;
107         u32 len_gen;
108         u32 gen2;
109         u32 addr_hi;
110 };
111
112 struct respQ_e {
113         u32 Qsleeping           : 4;
114         u32 Cmdq1CreditReturn   : 5;
115         u32 Cmdq1DmaComplete    : 5;
116         u32 Cmdq0CreditReturn   : 5;
117         u32 Cmdq0DmaComplete    : 5;
118         u32 FreelistQid         : 2;
119         u32 CreditValid         : 1;
120         u32 DataValid           : 1;
121         u32 Offload             : 1;
122         u32 Eop                 : 1;
123         u32 Sop                 : 1;
124         u32 GenerationBit       : 1;
125         u32 BufferLength;
126 };
127 #elif defined(__LITTLE_ENDIAN_BITFIELD)
128 struct cmdQ_e {
129         u32 len_gen;
130         u32 addr_lo;
131         u32 addr_hi;
132         u32 flags;
133 };
134
135 struct freelQ_e {
136         u32 len_gen;
137         u32 addr_lo;
138         u32 addr_hi;
139         u32 gen2;
140 };
141
142 struct respQ_e {
143         u32 BufferLength;
144         u32 GenerationBit       : 1;
145         u32 Sop                 : 1;
146         u32 Eop                 : 1;
147         u32 Offload             : 1;
148         u32 DataValid           : 1;
149         u32 CreditValid         : 1;
150         u32 FreelistQid         : 2;
151         u32 Cmdq0DmaComplete    : 5;
152         u32 Cmdq0CreditReturn   : 5;
153         u32 Cmdq1DmaComplete    : 5;
154         u32 Cmdq1CreditReturn   : 5;
155         u32 Qsleeping           : 4;
156 } ;
157 #endif
158
159 /*
160  * SW Context Command and Freelist Queue Descriptors
161  */
162 struct cmdQ_ce {
163         struct sk_buff *skb;
164         DECLARE_PCI_UNMAP_ADDR(dma_addr);
165         DECLARE_PCI_UNMAP_LEN(dma_len);
166 };
167
168 struct freelQ_ce {
169         struct sk_buff *skb;
170         DECLARE_PCI_UNMAP_ADDR(dma_addr);
171         DECLARE_PCI_UNMAP_LEN(dma_len);
172 };
173
174 /*
175  * SW command, freelist and response rings
176  */
177 struct cmdQ {
178         unsigned long   status;         /* HW DMA fetch status */
179         unsigned int    in_use;         /* # of in-use command descriptors */
180         unsigned int    size;           /* # of descriptors */
181         unsigned int    processed;      /* total # of descs HW has processed */
182         unsigned int    cleaned;        /* total # of descs SW has reclaimed */
183         unsigned int    stop_thres;     /* SW TX queue suspend threshold */
184         u16             pidx;           /* producer index (SW) */
185         u16             cidx;           /* consumer index (HW) */
186         u8              genbit;         /* current generation (=valid) bit */
187         u8              sop;            /* is next entry start of packet? */
188         struct cmdQ_e  *entries;        /* HW command descriptor Q */
189         struct cmdQ_ce *centries;       /* SW command context descriptor Q */
190         dma_addr_t      dma_addr;       /* DMA addr HW command descriptor Q */
191         spinlock_t      lock;           /* Lock to protect cmdQ enqueuing */
192 };
193
194 struct freelQ {
195         unsigned int    credits;        /* # of available RX buffers */
196         unsigned int    size;           /* free list capacity */
197         u16             pidx;           /* producer index (SW) */
198         u16             cidx;           /* consumer index (HW) */
199         u16             rx_buffer_size; /* Buffer size on this free list */
200         u16             dma_offset;     /* DMA offset to align IP headers */
201         u16             recycleq_idx;   /* skb recycle q to use */
202         u8              genbit;         /* current generation (=valid) bit */
203         struct freelQ_e *entries;       /* HW freelist descriptor Q */
204         struct freelQ_ce *centries;     /* SW freelist context descriptor Q */
205         dma_addr_t      dma_addr;       /* DMA addr HW freelist descriptor Q */
206 };
207
208 struct respQ {
209         unsigned int    credits;        /* credits to be returned to SGE */
210         unsigned int    size;           /* # of response Q descriptors */
211         u16             cidx;           /* consumer index (SW) */
212         u8              genbit;         /* current generation(=valid) bit */
213         struct respQ_e *entries;        /* HW response descriptor Q */
214         dma_addr_t      dma_addr;       /* DMA addr HW response descriptor Q */
215 };
216
217 /* Bit flags for cmdQ.status */
218 enum {
219         CMDQ_STAT_RUNNING = 1,          /* fetch engine is running */
220         CMDQ_STAT_LAST_PKT_DB = 2       /* last packet rung the doorbell */
221 };
222
223 /* T204 TX SW scheduler */
224
225 /* Per T204 TX port */
226 struct sched_port {
227         unsigned int    avail;          /* available bits - quota */
228         unsigned int    drain_bits_per_1024ns; /* drain rate */
229         unsigned int    speed;          /* drain rate, mbps */
230         unsigned int    mtu;            /* mtu size */
231         struct sk_buff_head skbq;       /* pending skbs */
232 };
233
234 /* Per T204 device */
235 struct sched {
236         ktime_t         last_updated;   /* last time quotas were computed */
237         unsigned int    max_avail;      /* max bits to be sent to any port */
238         unsigned int    port;           /* port index (round robin ports) */
239         unsigned int    num;            /* num skbs in per port queues */
240         struct sched_port p[MAX_NPORTS];
241         struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
242 };
243 static void restart_sched(unsigned long);
244
245
246 /*
247  * Main SGE data structure
248  *
249  * Interrupts are handled by a single CPU and it is likely that on a MP system
250  * the application is migrated to another CPU. In that scenario, we try to
251  * seperate the RX(in irq context) and TX state in order to decrease memory
252  * contention.
253  */
254 struct sge {
255         struct adapter *adapter;        /* adapter backpointer */
256         struct net_device *netdev;      /* netdevice backpointer */
257         struct freelQ   freelQ[SGE_FREELQ_N]; /* buffer free lists */
258         struct respQ    respQ;          /* response Q */
259         unsigned long   stopped_tx_queues; /* bitmap of suspended Tx queues */
260         unsigned int    rx_pkt_pad;     /* RX padding for L2 packets */
261         unsigned int    jumbo_fl;       /* jumbo freelist Q index */
262         unsigned int    intrtimer_nres; /* no-resource interrupt timer */
263         unsigned int    fixed_intrtimer;/* non-adaptive interrupt timer */
264         struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
265         struct timer_list espibug_timer;
266         unsigned long   espibug_timeout;
267         struct sk_buff  *espibug_skb[MAX_NPORTS];
268         u32             sge_control;    /* shadow value of sge control reg */
269         struct sge_intr_counts stats;
270         struct sge_port_stats *port_stats[MAX_NPORTS];
271         struct sched    *tx_sched;
272         struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
273 };
274
275 /*
276  * stop tasklet and free all pending skb's
277  */
278 static void tx_sched_stop(struct sge *sge)
279 {
280         struct sched *s = sge->tx_sched;
281         int i;
282
283         tasklet_kill(&s->sched_tsk);
284
285         for (i = 0; i < MAX_NPORTS; i++)
286                 __skb_queue_purge(&s->p[s->port].skbq);
287 }
288
289 /*
290  * t1_sched_update_parms() is called when the MTU or link speed changes. It
291  * re-computes scheduler parameters to scope with the change.
292  */
293 unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
294                                    unsigned int mtu, unsigned int speed)
295 {
296         struct sched *s = sge->tx_sched;
297         struct sched_port *p = &s->p[port];
298         unsigned int max_avail_segs;
299
300         pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
301         if (speed)
302                 p->speed = speed;
303         if (mtu)
304                 p->mtu = mtu;
305
306         if (speed || mtu) {
307                 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
308                 do_div(drain, (p->mtu + 50) * 1000);
309                 p->drain_bits_per_1024ns = (unsigned int) drain;
310
311                 if (p->speed < 1000)
312                         p->drain_bits_per_1024ns =
313                                 90 * p->drain_bits_per_1024ns / 100;
314         }
315
316         if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
317                 p->drain_bits_per_1024ns -= 16;
318                 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
319                 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
320         } else {
321                 s->max_avail = 16384;
322                 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
323         }
324
325         pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
326                  "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
327                  p->speed, s->max_avail, max_avail_segs,
328                  p->drain_bits_per_1024ns);
329
330         return max_avail_segs * (p->mtu - 40);
331 }
332
333 #if 0
334
335 /*
336  * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
337  * data that can be pushed per port.
338  */
339 void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
340 {
341         struct sched *s = sge->tx_sched;
342         unsigned int i;
343
344         s->max_avail = val;
345         for (i = 0; i < MAX_NPORTS; i++)
346                 t1_sched_update_parms(sge, i, 0, 0);
347 }
348
349 /*
350  * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
351  * is draining.
352  */
353 void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
354                                          unsigned int val)
355 {
356         struct sched *s = sge->tx_sched;
357         struct sched_port *p = &s->p[port];
358         p->drain_bits_per_1024ns = val * 1024 / 1000;
359         t1_sched_update_parms(sge, port, 0, 0);
360 }
361
362 #endif  /*  0  */
363
364
365 /*
366  * get_clock() implements a ns clock (see ktime_get)
367  */
368 static inline ktime_t get_clock(void)
369 {
370         struct timespec ts;
371
372         ktime_get_ts(&ts);
373         return timespec_to_ktime(ts);
374 }
375
376 /*
377  * tx_sched_init() allocates resources and does basic initialization.
378  */
379 static int tx_sched_init(struct sge *sge)
380 {
381         struct sched *s;
382         int i;
383
384         s = kzalloc(sizeof (struct sched), GFP_KERNEL);
385         if (!s)
386                 return -ENOMEM;
387
388         pr_debug("tx_sched_init\n");
389         tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
390         sge->tx_sched = s;
391
392         for (i = 0; i < MAX_NPORTS; i++) {
393                 skb_queue_head_init(&s->p[i].skbq);
394                 t1_sched_update_parms(sge, i, 1500, 1000);
395         }
396
397         return 0;
398 }
399
400 /*
401  * sched_update_avail() computes the delta since the last time it was called
402  * and updates the per port quota (number of bits that can be sent to the any
403  * port).
404  */
405 static inline int sched_update_avail(struct sge *sge)
406 {
407         struct sched *s = sge->tx_sched;
408         ktime_t now = get_clock();
409         unsigned int i;
410         long long delta_time_ns;
411
412         delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
413
414         pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
415         if (delta_time_ns < 15000)
416                 return 0;
417
418         for (i = 0; i < MAX_NPORTS; i++) {
419                 struct sched_port *p = &s->p[i];
420                 unsigned int delta_avail;
421
422                 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
423                 p->avail = min(p->avail + delta_avail, s->max_avail);
424         }
425
426         s->last_updated = now;
427
428         return 1;
429 }
430
431 /*
432  * sched_skb() is called from two different places. In the tx path, any
433  * packet generating load on an output port will call sched_skb()
434  * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
435  * context (skb == NULL).
436  * The scheduler only returns a skb (which will then be sent) if the
437  * length of the skb is <= the current quota of the output port.
438  */
439 static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
440                                 unsigned int credits)
441 {
442         struct sched *s = sge->tx_sched;
443         struct sk_buff_head *skbq;
444         unsigned int i, len, update = 1;
445
446         pr_debug("sched_skb %p\n", skb);
447         if (!skb) {
448                 if (!s->num)
449                         return NULL;
450         } else {
451                 skbq = &s->p[skb->dev->if_port].skbq;
452                 __skb_queue_tail(skbq, skb);
453                 s->num++;
454                 skb = NULL;
455         }
456
457         if (credits < MAX_SKB_FRAGS + 1)
458                 goto out;
459
460 again:
461         for (i = 0; i < MAX_NPORTS; i++) {
462                 s->port = ++s->port & (MAX_NPORTS - 1);
463                 skbq = &s->p[s->port].skbq;
464
465                 skb = skb_peek(skbq);
466
467                 if (!skb)
468                         continue;
469
470                 len = skb->len;
471                 if (len <= s->p[s->port].avail) {
472                         s->p[s->port].avail -= len;
473                         s->num--;
474                         __skb_unlink(skb, skbq);
475                         goto out;
476                 }
477                 skb = NULL;
478         }
479
480         if (update-- && sched_update_avail(sge))
481                 goto again;
482
483 out:
484         /* If there are more pending skbs, we use the hardware to schedule us
485          * again.
486          */
487         if (s->num && !skb) {
488                 struct cmdQ *q = &sge->cmdQ[0];
489                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
490                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
491                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
492                         writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
493                 }
494         }
495         pr_debug("sched_skb ret %p\n", skb);
496
497         return skb;
498 }
499
500 /*
501  * PIO to indicate that memory mapped Q contains valid descriptor(s).
502  */
503 static inline void doorbell_pio(struct adapter *adapter, u32 val)
504 {
505         wmb();
506         writel(val, adapter->regs + A_SG_DOORBELL);
507 }
508
509 /*
510  * Frees all RX buffers on the freelist Q. The caller must make sure that
511  * the SGE is turned off before calling this function.
512  */
513 static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
514 {
515         unsigned int cidx = q->cidx;
516
517         while (q->credits--) {
518                 struct freelQ_ce *ce = &q->centries[cidx];
519
520                 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
521                                  pci_unmap_len(ce, dma_len),
522                                  PCI_DMA_FROMDEVICE);
523                 dev_kfree_skb(ce->skb);
524                 ce->skb = NULL;
525                 if (++cidx == q->size)
526                         cidx = 0;
527         }
528 }
529
530 /*
531  * Free RX free list and response queue resources.
532  */
533 static void free_rx_resources(struct sge *sge)
534 {
535         struct pci_dev *pdev = sge->adapter->pdev;
536         unsigned int size, i;
537
538         if (sge->respQ.entries) {
539                 size = sizeof(struct respQ_e) * sge->respQ.size;
540                 pci_free_consistent(pdev, size, sge->respQ.entries,
541                                     sge->respQ.dma_addr);
542         }
543
544         for (i = 0; i < SGE_FREELQ_N; i++) {
545                 struct freelQ *q = &sge->freelQ[i];
546
547                 if (q->centries) {
548                         free_freelQ_buffers(pdev, q);
549                         kfree(q->centries);
550                 }
551                 if (q->entries) {
552                         size = sizeof(struct freelQ_e) * q->size;
553                         pci_free_consistent(pdev, size, q->entries,
554                                             q->dma_addr);
555                 }
556         }
557 }
558
559 /*
560  * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
561  * response queue.
562  */
563 static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
564 {
565         struct pci_dev *pdev = sge->adapter->pdev;
566         unsigned int size, i;
567
568         for (i = 0; i < SGE_FREELQ_N; i++) {
569                 struct freelQ *q = &sge->freelQ[i];
570
571                 q->genbit = 1;
572                 q->size = p->freelQ_size[i];
573                 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
574                 size = sizeof(struct freelQ_e) * q->size;
575                 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
576                 if (!q->entries)
577                         goto err_no_mem;
578
579                 size = sizeof(struct freelQ_ce) * q->size;
580                 q->centries = kzalloc(size, GFP_KERNEL);
581                 if (!q->centries)
582                         goto err_no_mem;
583         }
584
585         /*
586          * Calculate the buffer sizes for the two free lists.  FL0 accommodates
587          * regular sized Ethernet frames, FL1 is sized not to exceed 16K,
588          * including all the sk_buff overhead.
589          *
590          * Note: For T2 FL0 and FL1 are reversed.
591          */
592         sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
593                 sizeof(struct cpl_rx_data) +
594                 sge->freelQ[!sge->jumbo_fl].dma_offset;
595
596                 size = (16 * 1024) -
597                     SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
598
599         sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
600
601         /*
602          * Setup which skb recycle Q should be used when recycling buffers from
603          * each free list.
604          */
605         sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
606         sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
607
608         sge->respQ.genbit = 1;
609         sge->respQ.size = SGE_RESPQ_E_N;
610         sge->respQ.credits = 0;
611         size = sizeof(struct respQ_e) * sge->respQ.size;
612         sge->respQ.entries =
613                 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
614         if (!sge->respQ.entries)
615                 goto err_no_mem;
616         return 0;
617
618 err_no_mem:
619         free_rx_resources(sge);
620         return -ENOMEM;
621 }
622
623 /*
624  * Reclaims n TX descriptors and frees the buffers associated with them.
625  */
626 static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
627 {
628         struct cmdQ_ce *ce;
629         struct pci_dev *pdev = sge->adapter->pdev;
630         unsigned int cidx = q->cidx;
631
632         q->in_use -= n;
633         ce = &q->centries[cidx];
634         while (n--) {
635                 if (likely(pci_unmap_len(ce, dma_len))) {
636                         pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
637                                          pci_unmap_len(ce, dma_len),
638                                          PCI_DMA_TODEVICE);
639                         if (q->sop)
640                                 q->sop = 0;
641                 }
642                 if (ce->skb) {
643                         dev_kfree_skb_any(ce->skb);
644                         q->sop = 1;
645                 }
646                 ce++;
647                 if (++cidx == q->size) {
648                         cidx = 0;
649                         ce = q->centries;
650                 }
651         }
652         q->cidx = cidx;
653 }
654
655 /*
656  * Free TX resources.
657  *
658  * Assumes that SGE is stopped and all interrupts are disabled.
659  */
660 static void free_tx_resources(struct sge *sge)
661 {
662         struct pci_dev *pdev = sge->adapter->pdev;
663         unsigned int size, i;
664
665         for (i = 0; i < SGE_CMDQ_N; i++) {
666                 struct cmdQ *q = &sge->cmdQ[i];
667
668                 if (q->centries) {
669                         if (q->in_use)
670                                 free_cmdQ_buffers(sge, q, q->in_use);
671                         kfree(q->centries);
672                 }
673                 if (q->entries) {
674                         size = sizeof(struct cmdQ_e) * q->size;
675                         pci_free_consistent(pdev, size, q->entries,
676                                             q->dma_addr);
677                 }
678         }
679 }
680
681 /*
682  * Allocates basic TX resources, consisting of memory mapped command Qs.
683  */
684 static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
685 {
686         struct pci_dev *pdev = sge->adapter->pdev;
687         unsigned int size, i;
688
689         for (i = 0; i < SGE_CMDQ_N; i++) {
690                 struct cmdQ *q = &sge->cmdQ[i];
691
692                 q->genbit = 1;
693                 q->sop = 1;
694                 q->size = p->cmdQ_size[i];
695                 q->in_use = 0;
696                 q->status = 0;
697                 q->processed = q->cleaned = 0;
698                 q->stop_thres = 0;
699                 spin_lock_init(&q->lock);
700                 size = sizeof(struct cmdQ_e) * q->size;
701                 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
702                 if (!q->entries)
703                         goto err_no_mem;
704
705                 size = sizeof(struct cmdQ_ce) * q->size;
706                 q->centries = kzalloc(size, GFP_KERNEL);
707                 if (!q->centries)
708                         goto err_no_mem;
709         }
710
711         /*
712          * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
713          * only.  For queue 0 set the stop threshold so we can handle one more
714          * packet from each port, plus reserve an additional 24 entries for
715          * Ethernet packets only.  Queue 1 never suspends nor do we reserve
716          * space for Ethernet packets.
717          */
718         sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
719                 (MAX_SKB_FRAGS + 1);
720         return 0;
721
722 err_no_mem:
723         free_tx_resources(sge);
724         return -ENOMEM;
725 }
726
727 static inline void setup_ring_params(struct adapter *adapter, u64 addr,
728                                      u32 size, int base_reg_lo,
729                                      int base_reg_hi, int size_reg)
730 {
731         writel((u32)addr, adapter->regs + base_reg_lo);
732         writel(addr >> 32, adapter->regs + base_reg_hi);
733         writel(size, adapter->regs + size_reg);
734 }
735
736 /*
737  * Enable/disable VLAN acceleration.
738  */
739 void t1_set_vlan_accel(struct adapter *adapter, int on_off)
740 {
741         struct sge *sge = adapter->sge;
742
743         sge->sge_control &= ~F_VLAN_XTRACT;
744         if (on_off)
745                 sge->sge_control |= F_VLAN_XTRACT;
746         if (adapter->open_device_map) {
747                 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
748                 readl(adapter->regs + A_SG_CONTROL);   /* flush */
749         }
750 }
751
752 /*
753  * Programs the various SGE registers. However, the engine is not yet enabled,
754  * but sge->sge_control is setup and ready to go.
755  */
756 static void configure_sge(struct sge *sge, struct sge_params *p)
757 {
758         struct adapter *ap = sge->adapter;
759
760         writel(0, ap->regs + A_SG_CONTROL);
761         setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
762                           A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
763         setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
764                           A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
765         setup_ring_params(ap, sge->freelQ[0].dma_addr,
766                           sge->freelQ[0].size, A_SG_FL0BASELWR,
767                           A_SG_FL0BASEUPR, A_SG_FL0SIZE);
768         setup_ring_params(ap, sge->freelQ[1].dma_addr,
769                           sge->freelQ[1].size, A_SG_FL1BASELWR,
770                           A_SG_FL1BASEUPR, A_SG_FL1SIZE);
771
772         /* The threshold comparison uses <. */
773         writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
774
775         setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
776                           A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
777         writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
778
779         sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
780                 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
781                 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
782                 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
783
784 #if defined(__BIG_ENDIAN_BITFIELD)
785         sge->sge_control |= F_ENABLE_BIG_ENDIAN;
786 #endif
787
788         /* Initialize no-resource timer */
789         sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
790
791         t1_sge_set_coalesce_params(sge, p);
792 }
793
794 /*
795  * Return the payload capacity of the jumbo free-list buffers.
796  */
797 static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
798 {
799         return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
800                 sge->freelQ[sge->jumbo_fl].dma_offset -
801                 sizeof(struct cpl_rx_data);
802 }
803
804 /*
805  * Frees all SGE related resources and the sge structure itself
806  */
807 void t1_sge_destroy(struct sge *sge)
808 {
809         int i;
810
811         for_each_port(sge->adapter, i)
812                 free_percpu(sge->port_stats[i]);
813
814         kfree(sge->tx_sched);
815         free_tx_resources(sge);
816         free_rx_resources(sge);
817         kfree(sge);
818 }
819
820 /*
821  * Allocates new RX buffers on the freelist Q (and tracks them on the freelist
822  * context Q) until the Q is full or alloc_skb fails.
823  *
824  * It is possible that the generation bits already match, indicating that the
825  * buffer is already valid and nothing needs to be done. This happens when we
826  * copied a received buffer into a new sk_buff during the interrupt processing.
827  *
828  * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
829  * we specify a RX_OFFSET in order to make sure that the IP header is 4B
830  * aligned.
831  */
832 static void refill_free_list(struct sge *sge, struct freelQ *q)
833 {
834         struct pci_dev *pdev = sge->adapter->pdev;
835         struct freelQ_ce *ce = &q->centries[q->pidx];
836         struct freelQ_e *e = &q->entries[q->pidx];
837         unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
838
839         while (q->credits < q->size) {
840                 struct sk_buff *skb;
841                 dma_addr_t mapping;
842
843                 skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
844                 if (!skb)
845                         break;
846
847                 skb_reserve(skb, q->dma_offset);
848                 mapping = pci_map_single(pdev, skb->data, dma_len,
849                                          PCI_DMA_FROMDEVICE);
850                 skb_reserve(skb, sge->rx_pkt_pad);
851
852                 ce->skb = skb;
853                 pci_unmap_addr_set(ce, dma_addr, mapping);
854                 pci_unmap_len_set(ce, dma_len, dma_len);
855                 e->addr_lo = (u32)mapping;
856                 e->addr_hi = (u64)mapping >> 32;
857                 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
858                 wmb();
859                 e->gen2 = V_CMD_GEN2(q->genbit);
860
861                 e++;
862                 ce++;
863                 if (++q->pidx == q->size) {
864                         q->pidx = 0;
865                         q->genbit ^= 1;
866                         ce = q->centries;
867                         e = q->entries;
868                 }
869                 q->credits++;
870         }
871 }
872
873 /*
874  * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
875  * of both rings, we go into 'few interrupt mode' in order to give the system
876  * time to free up resources.
877  */
878 static void freelQs_empty(struct sge *sge)
879 {
880         struct adapter *adapter = sge->adapter;
881         u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
882         u32 irqholdoff_reg;
883
884         refill_free_list(sge, &sge->freelQ[0]);
885         refill_free_list(sge, &sge->freelQ[1]);
886
887         if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
888             sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
889                 irq_reg |= F_FL_EXHAUSTED;
890                 irqholdoff_reg = sge->fixed_intrtimer;
891         } else {
892                 /* Clear the F_FL_EXHAUSTED interrupts for now */
893                 irq_reg &= ~F_FL_EXHAUSTED;
894                 irqholdoff_reg = sge->intrtimer_nres;
895         }
896         writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
897         writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
898
899         /* We reenable the Qs to force a freelist GTS interrupt later */
900         doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
901 }
902
903 #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
904 #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
905 #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \
906                         F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
907
908 /*
909  * Disable SGE Interrupts
910  */
911 void t1_sge_intr_disable(struct sge *sge)
912 {
913         u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
914
915         writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
916         writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
917 }
918
919 /*
920  * Enable SGE interrupts.
921  */
922 void t1_sge_intr_enable(struct sge *sge)
923 {
924         u32 en = SGE_INT_ENABLE;
925         u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
926
927         if (sge->adapter->flags & TSO_CAPABLE)
928                 en &= ~F_PACKET_TOO_BIG;
929         writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
930         writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
931 }
932
933 /*
934  * Clear SGE interrupts.
935  */
936 void t1_sge_intr_clear(struct sge *sge)
937 {
938         writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
939         writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
940 }
941
942 /*
943  * SGE 'Error' interrupt handler
944  */
945 int t1_sge_intr_error_handler(struct sge *sge)
946 {
947         struct adapter *adapter = sge->adapter;
948         u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
949
950         if (adapter->flags & TSO_CAPABLE)
951                 cause &= ~F_PACKET_TOO_BIG;
952         if (cause & F_RESPQ_EXHAUSTED)
953                 sge->stats.respQ_empty++;
954         if (cause & F_RESPQ_OVERFLOW) {
955                 sge->stats.respQ_overflow++;
956                 CH_ALERT("%s: SGE response queue overflow\n",
957                          adapter->name);
958         }
959         if (cause & F_FL_EXHAUSTED) {
960                 sge->stats.freelistQ_empty++;
961                 freelQs_empty(sge);
962         }
963         if (cause & F_PACKET_TOO_BIG) {
964                 sge->stats.pkt_too_big++;
965                 CH_ALERT("%s: SGE max packet size exceeded\n",
966                          adapter->name);
967         }
968         if (cause & F_PACKET_MISMATCH) {
969                 sge->stats.pkt_mismatch++;
970                 CH_ALERT("%s: SGE packet mismatch\n", adapter->name);
971         }
972         if (cause & SGE_INT_FATAL)
973                 t1_fatal_err(adapter);
974
975         writel(cause, adapter->regs + A_SG_INT_CAUSE);
976         return 0;
977 }
978
979 const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
980 {
981         return &sge->stats;
982 }
983
984 void t1_sge_get_port_stats(const struct sge *sge, int port,
985                            struct sge_port_stats *ss)
986 {
987         int cpu;
988
989         memset(ss, 0, sizeof(*ss));
990         for_each_possible_cpu(cpu) {
991                 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
992
993                 ss->rx_cso_good += st->rx_cso_good;
994                 ss->tx_cso += st->tx_cso;
995                 ss->tx_tso += st->tx_tso;
996                 ss->tx_need_hdrroom += st->tx_need_hdrroom;
997                 ss->vlan_xtract += st->vlan_xtract;
998                 ss->vlan_insert += st->vlan_insert;
999         }
1000 }
1001
1002 /**
1003  *      recycle_fl_buf - recycle a free list buffer
1004  *      @fl: the free list
1005  *      @idx: index of buffer to recycle
1006  *
1007  *      Recycles the specified buffer on the given free list by adding it at
1008  *      the next available slot on the list.
1009  */
1010 static void recycle_fl_buf(struct freelQ *fl, int idx)
1011 {
1012         struct freelQ_e *from = &fl->entries[idx];
1013         struct freelQ_e *to = &fl->entries[fl->pidx];
1014
1015         fl->centries[fl->pidx] = fl->centries[idx];
1016         to->addr_lo = from->addr_lo;
1017         to->addr_hi = from->addr_hi;
1018         to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
1019         wmb();
1020         to->gen2 = V_CMD_GEN2(fl->genbit);
1021         fl->credits++;
1022
1023         if (++fl->pidx == fl->size) {
1024                 fl->pidx = 0;
1025                 fl->genbit ^= 1;
1026         }
1027 }
1028
1029 static int copybreak __read_mostly = 256;
1030 module_param(copybreak, int, 0);
1031 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
1032
1033 /**
1034  *      get_packet - return the next ingress packet buffer
1035  *      @pdev: the PCI device that received the packet
1036  *      @fl: the SGE free list holding the packet
1037  *      @len: the actual packet length, excluding any SGE padding
1038  *
1039  *      Get the next packet from a free list and complete setup of the
1040  *      sk_buff.  If the packet is small we make a copy and recycle the
1041  *      original buffer, otherwise we use the original buffer itself.  If a
1042  *      positive drop threshold is supplied packets are dropped and their
1043  *      buffers recycled if (a) the number of remaining buffers is under the
1044  *      threshold and the packet is too big to copy, or (b) the packet should
1045  *      be copied but there is no memory for the copy.
1046  */
1047 static inline struct sk_buff *get_packet(struct pci_dev *pdev,
1048                                          struct freelQ *fl, unsigned int len)
1049 {
1050         struct sk_buff *skb;
1051         const struct freelQ_ce *ce = &fl->centries[fl->cidx];
1052
1053         if (len < copybreak) {
1054                 skb = alloc_skb(len + 2, GFP_ATOMIC);
1055                 if (!skb)
1056                         goto use_orig_buf;
1057
1058                 skb_reserve(skb, 2);    /* align IP header */
1059                 skb_put(skb, len);
1060                 pci_dma_sync_single_for_cpu(pdev,
1061                                             pci_unmap_addr(ce, dma_addr),
1062                                             pci_unmap_len(ce, dma_len),
1063                                             PCI_DMA_FROMDEVICE);
1064                 skb_copy_from_linear_data(ce->skb, skb->data, len);
1065                 pci_dma_sync_single_for_device(pdev,
1066                                                pci_unmap_addr(ce, dma_addr),
1067                                                pci_unmap_len(ce, dma_len),
1068                                                PCI_DMA_FROMDEVICE);
1069                 recycle_fl_buf(fl, fl->cidx);
1070                 return skb;
1071         }
1072
1073 use_orig_buf:
1074         if (fl->credits < 2) {
1075                 recycle_fl_buf(fl, fl->cidx);
1076                 return NULL;
1077         }
1078
1079         pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
1080                          pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1081         skb = ce->skb;
1082         prefetch(skb->data);
1083
1084         skb_put(skb, len);
1085         return skb;
1086 }
1087
1088 /**
1089  *      unexpected_offload - handle an unexpected offload packet
1090  *      @adapter: the adapter
1091  *      @fl: the free list that received the packet
1092  *
1093  *      Called when we receive an unexpected offload packet (e.g., the TOE
1094  *      function is disabled or the card is a NIC).  Prints a message and
1095  *      recycles the buffer.
1096  */
1097 static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
1098 {
1099         struct freelQ_ce *ce = &fl->centries[fl->cidx];
1100         struct sk_buff *skb = ce->skb;
1101
1102         pci_dma_sync_single_for_cpu(adapter->pdev, pci_unmap_addr(ce, dma_addr),
1103                             pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1104         CH_ERR("%s: unexpected offload packet, cmd %u\n",
1105                adapter->name, *skb->data);
1106         recycle_fl_buf(fl, fl->cidx);
1107 }
1108
1109 /*
1110  * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1111  * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1112  * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1113  * Note that the *_large_page_tx_descs stuff will be optimized out when
1114  * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1115  *
1116  * compute_large_page_descs() computes how many additional descriptors are
1117  * required to break down the stack's request.
1118  */
1119 static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1120 {
1121         unsigned int count = 0;
1122
1123         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1124                 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1125                 unsigned int i, len = skb->len - skb->data_len;
1126                 while (len > SGE_TX_DESC_MAX_PLEN) {
1127                         count++;
1128                         len -= SGE_TX_DESC_MAX_PLEN;
1129                 }
1130                 for (i = 0; nfrags--; i++) {
1131                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1132                         len = frag->size;
1133                         while (len > SGE_TX_DESC_MAX_PLEN) {
1134                                 count++;
1135                                 len -= SGE_TX_DESC_MAX_PLEN;
1136                         }
1137                 }
1138         }
1139         return count;
1140 }
1141
1142 /*
1143  * Write a cmdQ entry.
1144  *
1145  * Since this function writes the 'flags' field, it must not be used to
1146  * write the first cmdQ entry.
1147  */
1148 static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1149                                  unsigned int len, unsigned int gen,
1150                                  unsigned int eop)
1151 {
1152         BUG_ON(len > SGE_TX_DESC_MAX_PLEN);
1153
1154         e->addr_lo = (u32)mapping;
1155         e->addr_hi = (u64)mapping >> 32;
1156         e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1157         e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1158 }
1159
1160 /*
1161  * See comment for previous function.
1162  *
1163  * write_tx_descs_large_page() writes additional SGE tx descriptors if
1164  * *desc_len exceeds HW's capability.
1165  */
1166 static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1167                                                      struct cmdQ_e **e,
1168                                                      struct cmdQ_ce **ce,
1169                                                      unsigned int *gen,
1170                                                      dma_addr_t *desc_mapping,
1171                                                      unsigned int *desc_len,
1172                                                      unsigned int nfrags,
1173                                                      struct cmdQ *q)
1174 {
1175         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1176                 struct cmdQ_e *e1 = *e;
1177                 struct cmdQ_ce *ce1 = *ce;
1178
1179                 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1180                         *desc_len -= SGE_TX_DESC_MAX_PLEN;
1181                         write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1182                                       *gen, nfrags == 0 && *desc_len == 0);
1183                         ce1->skb = NULL;
1184                         pci_unmap_len_set(ce1, dma_len, 0);
1185                         *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1186                         if (*desc_len) {
1187                                 ce1++;
1188                                 e1++;
1189                                 if (++pidx == q->size) {
1190                                         pidx = 0;
1191                                         *gen ^= 1;
1192                                         ce1 = q->centries;
1193                                         e1 = q->entries;
1194                                 }
1195                         }
1196                 }
1197                 *e = e1;
1198                 *ce = ce1;
1199         }
1200         return pidx;
1201 }
1202
1203 /*
1204  * Write the command descriptors to transmit the given skb starting at
1205  * descriptor pidx with the given generation.
1206  */
1207 static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
1208                                   unsigned int pidx, unsigned int gen,
1209                                   struct cmdQ *q)
1210 {
1211         dma_addr_t mapping, desc_mapping;
1212         struct cmdQ_e *e, *e1;
1213         struct cmdQ_ce *ce;
1214         unsigned int i, flags, first_desc_len, desc_len,
1215             nfrags = skb_shinfo(skb)->nr_frags;
1216
1217         e = e1 = &q->entries[pidx];
1218         ce = &q->centries[pidx];
1219
1220         mapping = pci_map_single(adapter->pdev, skb->data,
1221                                 skb->len - skb->data_len, PCI_DMA_TODEVICE);
1222
1223         desc_mapping = mapping;
1224         desc_len = skb->len - skb->data_len;
1225
1226         flags = F_CMD_DATAVALID | F_CMD_SOP |
1227             V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1228             V_CMD_GEN2(gen);
1229         first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1230             desc_len : SGE_TX_DESC_MAX_PLEN;
1231         e->addr_lo = (u32)desc_mapping;
1232         e->addr_hi = (u64)desc_mapping >> 32;
1233         e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1234         ce->skb = NULL;
1235         pci_unmap_len_set(ce, dma_len, 0);
1236
1237         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1238             desc_len > SGE_TX_DESC_MAX_PLEN) {
1239                 desc_mapping += first_desc_len;
1240                 desc_len -= first_desc_len;
1241                 e1++;
1242                 ce++;
1243                 if (++pidx == q->size) {
1244                         pidx = 0;
1245                         gen ^= 1;
1246                         e1 = q->entries;
1247                         ce = q->centries;
1248                 }
1249                 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1250                                                  &desc_mapping, &desc_len,
1251                                                  nfrags, q);
1252
1253                 if (likely(desc_len))
1254                         write_tx_desc(e1, desc_mapping, desc_len, gen,
1255                                       nfrags == 0);
1256         }
1257
1258         ce->skb = NULL;
1259         pci_unmap_addr_set(ce, dma_addr, mapping);
1260         pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len);
1261
1262         for (i = 0; nfrags--; i++) {
1263                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1264                 e1++;
1265                 ce++;
1266                 if (++pidx == q->size) {
1267                         pidx = 0;
1268                         gen ^= 1;
1269                         e1 = q->entries;
1270                         ce = q->centries;
1271                 }
1272
1273                 mapping = pci_map_page(adapter->pdev, frag->page,
1274                                        frag->page_offset, frag->size,
1275                                        PCI_DMA_TODEVICE);
1276                 desc_mapping = mapping;
1277                 desc_len = frag->size;
1278
1279                 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1280                                                  &desc_mapping, &desc_len,
1281                                                  nfrags, q);
1282                 if (likely(desc_len))
1283                         write_tx_desc(e1, desc_mapping, desc_len, gen,
1284                                       nfrags == 0);
1285                 ce->skb = NULL;
1286                 pci_unmap_addr_set(ce, dma_addr, mapping);
1287                 pci_unmap_len_set(ce, dma_len, frag->size);
1288         }
1289         ce->skb = skb;
1290         wmb();
1291         e->flags = flags;
1292 }
1293
1294 /*
1295  * Clean up completed Tx buffers.
1296  */
1297 static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
1298 {
1299         unsigned int reclaim = q->processed - q->cleaned;
1300
1301         if (reclaim) {
1302                 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1303                          q->processed, q->cleaned);
1304                 free_cmdQ_buffers(sge, q, reclaim);
1305                 q->cleaned += reclaim;
1306         }
1307 }
1308
1309 /*
1310  * Called from tasklet. Checks the scheduler for any
1311  * pending skbs that can be sent.
1312  */
1313 static void restart_sched(unsigned long arg)
1314 {
1315         struct sge *sge = (struct sge *) arg;
1316         struct adapter *adapter = sge->adapter;
1317         struct cmdQ *q = &sge->cmdQ[0];
1318         struct sk_buff *skb;
1319         unsigned int credits, queued_skb = 0;
1320
1321         spin_lock(&q->lock);
1322         reclaim_completed_tx(sge, q);
1323
1324         credits = q->size - q->in_use;
1325         pr_debug("restart_sched credits=%d\n", credits);
1326         while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1327                 unsigned int genbit, pidx, count;
1328                 count = 1 + skb_shinfo(skb)->nr_frags;
1329                 count += compute_large_page_tx_descs(skb);
1330                 q->in_use += count;
1331                 genbit = q->genbit;
1332                 pidx = q->pidx;
1333                 q->pidx += count;
1334                 if (q->pidx >= q->size) {
1335                         q->pidx -= q->size;
1336                         q->genbit ^= 1;
1337                 }
1338                 write_tx_descs(adapter, skb, pidx, genbit, q);
1339                 credits = q->size - q->in_use;
1340                 queued_skb = 1;
1341         }
1342
1343         if (queued_skb) {
1344                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1345                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1346                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1347                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1348                 }
1349         }
1350         spin_unlock(&q->lock);
1351 }
1352
1353 /**
1354  *      sge_rx - process an ingress ethernet packet
1355  *      @sge: the sge structure
1356  *      @fl: the free list that contains the packet buffer
1357  *      @len: the packet length
1358  *
1359  *      Process an ingress ethernet pakcet and deliver it to the stack.
1360  */
1361 static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1362 {
1363         struct sk_buff *skb;
1364         const struct cpl_rx_pkt *p;
1365         struct adapter *adapter = sge->adapter;
1366         struct sge_port_stats *st;
1367
1368         skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad);
1369         if (unlikely(!skb)) {
1370                 sge->stats.rx_drops++;
1371                 return;
1372         }
1373
1374         p = (const struct cpl_rx_pkt *) skb->data;
1375         if (p->iff >= adapter->params.nports) {
1376                 kfree_skb(skb);
1377                 return;
1378         }
1379         __skb_pull(skb, sizeof(*p));
1380
1381         st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id());
1382
1383         skb->protocol = eth_type_trans(skb, adapter->port[p->iff].dev);
1384         if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
1385             skb->protocol == htons(ETH_P_IP) &&
1386             (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
1387                 ++st->rx_cso_good;
1388                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1389         } else
1390                 skb->ip_summed = CHECKSUM_NONE;
1391
1392         if (unlikely(adapter->vlan_grp && p->vlan_valid)) {
1393                 st->vlan_xtract++;
1394                 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp,
1395                                          ntohs(p->vlan));
1396         } else
1397                 netif_receive_skb(skb);
1398 }
1399
1400 /*
1401  * Returns true if a command queue has enough available descriptors that
1402  * we can resume Tx operation after temporarily disabling its packet queue.
1403  */
1404 static inline int enough_free_Tx_descs(const struct cmdQ *q)
1405 {
1406         unsigned int r = q->processed - q->cleaned;
1407
1408         return q->in_use - r < (q->size >> 1);
1409 }
1410
1411 /*
1412  * Called when sufficient space has become available in the SGE command queues
1413  * after the Tx packet schedulers have been suspended to restart the Tx path.
1414  */
1415 static void restart_tx_queues(struct sge *sge)
1416 {
1417         struct adapter *adap = sge->adapter;
1418         int i;
1419
1420         if (!enough_free_Tx_descs(&sge->cmdQ[0]))
1421                 return;
1422
1423         for_each_port(adap, i) {
1424                 struct net_device *nd = adap->port[i].dev;
1425
1426                 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) &&
1427                     netif_running(nd)) {
1428                         sge->stats.cmdQ_restarted[2]++;
1429                         netif_wake_queue(nd);
1430                 }
1431         }
1432 }
1433
1434 /*
1435  * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1436  * information.
1437  */
1438 static unsigned int update_tx_info(struct adapter *adapter,
1439                                           unsigned int flags,
1440                                           unsigned int pr0)
1441 {
1442         struct sge *sge = adapter->sge;
1443         struct cmdQ *cmdq = &sge->cmdQ[0];
1444
1445         cmdq->processed += pr0;
1446         if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1447                 freelQs_empty(sge);
1448                 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1449         }
1450         if (flags & F_CMDQ0_ENABLE) {
1451                 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1452
1453                 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1454                     !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1455                         set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1456                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1457                 }
1458                 if (sge->tx_sched)
1459                         tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1460
1461                 flags &= ~F_CMDQ0_ENABLE;
1462         }
1463
1464         if (unlikely(sge->stopped_tx_queues != 0))
1465                 restart_tx_queues(sge);
1466
1467         return flags;
1468 }
1469
1470 /*
1471  * Process SGE responses, up to the supplied budget.  Returns the number of
1472  * responses processed.  A negative budget is effectively unlimited.
1473  */
1474 static int process_responses(struct adapter *adapter, int budget)
1475 {
1476         struct sge *sge = adapter->sge;
1477         struct respQ *q = &sge->respQ;
1478         struct respQ_e *e = &q->entries[q->cidx];
1479         int done = 0;
1480         unsigned int flags = 0;
1481         unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1482
1483         while (done < budget && e->GenerationBit == q->genbit) {
1484                 flags |= e->Qsleeping;
1485
1486                 cmdq_processed[0] += e->Cmdq0CreditReturn;
1487                 cmdq_processed[1] += e->Cmdq1CreditReturn;
1488
1489                 /* We batch updates to the TX side to avoid cacheline
1490                  * ping-pong of TX state information on MP where the sender
1491                  * might run on a different CPU than this function...
1492                  */
1493                 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) {
1494                         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1495                         cmdq_processed[0] = 0;
1496                 }
1497
1498                 if (unlikely(cmdq_processed[1] > 16)) {
1499                         sge->cmdQ[1].processed += cmdq_processed[1];
1500                         cmdq_processed[1] = 0;
1501                 }
1502
1503                 if (likely(e->DataValid)) {
1504                         struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1505
1506                         BUG_ON(!e->Sop || !e->Eop);
1507                         if (unlikely(e->Offload))
1508                                 unexpected_offload(adapter, fl);
1509                         else
1510                                 sge_rx(sge, fl, e->BufferLength);
1511
1512                         ++done;
1513
1514                         /*
1515                          * Note: this depends on each packet consuming a
1516                          * single free-list buffer; cf. the BUG above.
1517                          */
1518                         if (++fl->cidx == fl->size)
1519                                 fl->cidx = 0;
1520                         prefetch(fl->centries[fl->cidx].skb);
1521
1522                         if (unlikely(--fl->credits <
1523                                      fl->size - SGE_FREEL_REFILL_THRESH))
1524                                 refill_free_list(sge, fl);
1525                 } else
1526                         sge->stats.pure_rsps++;
1527
1528                 e++;
1529                 if (unlikely(++q->cidx == q->size)) {
1530                         q->cidx = 0;
1531                         q->genbit ^= 1;
1532                         e = q->entries;
1533                 }
1534                 prefetch(e);
1535
1536                 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1537                         writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1538                         q->credits = 0;
1539                 }
1540         }
1541
1542         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1543         sge->cmdQ[1].processed += cmdq_processed[1];
1544
1545         return done;
1546 }
1547
1548 static inline int responses_pending(const struct adapter *adapter)
1549 {
1550         const struct respQ *Q = &adapter->sge->respQ;
1551         const struct respQ_e *e = &Q->entries[Q->cidx];
1552
1553         return (e->GenerationBit == Q->genbit);
1554 }
1555
1556 /*
1557  * A simpler version of process_responses() that handles only pure (i.e.,
1558  * non data-carrying) responses.  Such respones are too light-weight to justify
1559  * calling a softirq when using NAPI, so we handle them specially in hard
1560  * interrupt context.  The function is called with a pointer to a response,
1561  * which the caller must ensure is a valid pure response.  Returns 1 if it
1562  * encounters a valid data-carrying response, 0 otherwise.
1563  */
1564 static int process_pure_responses(struct adapter *adapter)
1565 {
1566         struct sge *sge = adapter->sge;
1567         struct respQ *q = &sge->respQ;
1568         struct respQ_e *e = &q->entries[q->cidx];
1569         const struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1570         unsigned int flags = 0;
1571         unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1572
1573         prefetch(fl->centries[fl->cidx].skb);
1574         if (e->DataValid)
1575                 return 1;
1576
1577         do {
1578                 flags |= e->Qsleeping;
1579
1580                 cmdq_processed[0] += e->Cmdq0CreditReturn;
1581                 cmdq_processed[1] += e->Cmdq1CreditReturn;
1582
1583                 e++;
1584                 if (unlikely(++q->cidx == q->size)) {
1585                         q->cidx = 0;
1586                         q->genbit ^= 1;
1587                         e = q->entries;
1588                 }
1589                 prefetch(e);
1590
1591                 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1592                         writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1593                         q->credits = 0;
1594                 }
1595                 sge->stats.pure_rsps++;
1596         } while (e->GenerationBit == q->genbit && !e->DataValid);
1597
1598         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1599         sge->cmdQ[1].processed += cmdq_processed[1];
1600
1601         return e->GenerationBit == q->genbit;
1602 }
1603
1604 /*
1605  * Handler for new data events when using NAPI.  This does not need any locking
1606  * or protection from interrupts as data interrupts are off at this point and
1607  * other adapter interrupts do not interfere.
1608  */
1609 int t1_poll(struct napi_struct *napi, int budget)
1610 {
1611         struct adapter *adapter = container_of(napi, struct adapter, napi);
1612         int work_done = process_responses(adapter, budget);
1613
1614         if (likely(work_done < budget)) {
1615                 napi_complete(napi);
1616                 writel(adapter->sge->respQ.cidx,
1617                        adapter->regs + A_SG_SLEEPING);
1618         }
1619         return work_done;
1620 }
1621
1622 irqreturn_t t1_interrupt(int irq, void *data)
1623 {
1624         struct adapter *adapter = data;
1625         struct sge *sge = adapter->sge;
1626         int handled;
1627
1628         if (likely(responses_pending(adapter))) {
1629                 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1630
1631                 if (napi_schedule_prep(&adapter->napi)) {
1632                         if (process_pure_responses(adapter))
1633                                 __napi_schedule(&adapter->napi);
1634                         else {
1635                                 /* no data, no NAPI needed */
1636                                 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1637                                 /* undo schedule_prep */
1638                                 napi_enable(&adapter->napi);
1639                         }
1640                 }
1641                 return IRQ_HANDLED;
1642         }
1643
1644         spin_lock(&adapter->async_lock);
1645         handled = t1_slow_intr_handler(adapter);
1646         spin_unlock(&adapter->async_lock);
1647
1648         if (!handled)
1649                 sge->stats.unhandled_irqs++;
1650
1651         return IRQ_RETVAL(handled != 0);
1652 }
1653
1654 /*
1655  * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1656  *
1657  * The code figures out how many entries the sk_buff will require in the
1658  * cmdQ and updates the cmdQ data structure with the state once the enqueue
1659  * has complete. Then, it doesn't access the global structure anymore, but
1660  * uses the corresponding fields on the stack. In conjuction with a spinlock
1661  * around that code, we can make the function reentrant without holding the
1662  * lock when we actually enqueue (which might be expensive, especially on
1663  * architectures with IO MMUs).
1664  *
1665  * This runs with softirqs disabled.
1666  */
1667 static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1668                      unsigned int qid, struct net_device *dev)
1669 {
1670         struct sge *sge = adapter->sge;
1671         struct cmdQ *q = &sge->cmdQ[qid];
1672         unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1673
1674         if (!spin_trylock(&q->lock))
1675                 return NETDEV_TX_LOCKED;
1676
1677         reclaim_completed_tx(sge, q);
1678
1679         pidx = q->pidx;
1680         credits = q->size - q->in_use;
1681         count = 1 + skb_shinfo(skb)->nr_frags;
1682         count += compute_large_page_tx_descs(skb);
1683
1684         /* Ethernet packet */
1685         if (unlikely(credits < count)) {
1686                 if (!netif_queue_stopped(dev)) {
1687                         netif_stop_queue(dev);
1688                         set_bit(dev->if_port, &sge->stopped_tx_queues);
1689                         sge->stats.cmdQ_full[2]++;
1690                         CH_ERR("%s: Tx ring full while queue awake!\n",
1691                                adapter->name);
1692                 }
1693                 spin_unlock(&q->lock);
1694                 return NETDEV_TX_BUSY;
1695         }
1696
1697         if (unlikely(credits - count < q->stop_thres)) {
1698                 netif_stop_queue(dev);
1699                 set_bit(dev->if_port, &sge->stopped_tx_queues);
1700                 sge->stats.cmdQ_full[2]++;
1701         }
1702
1703         /* T204 cmdQ0 skbs that are destined for a certain port have to go
1704          * through the scheduler.
1705          */
1706         if (sge->tx_sched && !qid && skb->dev) {
1707 use_sched:
1708                 use_sched_skb = 1;
1709                 /* Note that the scheduler might return a different skb than
1710                  * the one passed in.
1711                  */
1712                 skb = sched_skb(sge, skb, credits);
1713                 if (!skb) {
1714                         spin_unlock(&q->lock);
1715                         return NETDEV_TX_OK;
1716                 }
1717                 pidx = q->pidx;
1718                 count = 1 + skb_shinfo(skb)->nr_frags;
1719                 count += compute_large_page_tx_descs(skb);
1720         }
1721
1722         q->in_use += count;
1723         genbit = q->genbit;
1724         pidx = q->pidx;
1725         q->pidx += count;
1726         if (q->pidx >= q->size) {
1727                 q->pidx -= q->size;
1728                 q->genbit ^= 1;
1729         }
1730         spin_unlock(&q->lock);
1731
1732         write_tx_descs(adapter, skb, pidx, genbit, q);
1733
1734         /*
1735          * We always ring the doorbell for cmdQ1.  For cmdQ0, we only ring
1736          * the doorbell if the Q is asleep. There is a natural race, where
1737          * the hardware is going to sleep just after we checked, however,
1738          * then the interrupt handler will detect the outstanding TX packet
1739          * and ring the doorbell for us.
1740          */
1741         if (qid)
1742                 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1743         else {
1744                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1745                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1746                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1747                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1748                 }
1749         }
1750
1751         if (use_sched_skb) {
1752                 if (spin_trylock(&q->lock)) {
1753                         credits = q->size - q->in_use;
1754                         skb = NULL;
1755                         goto use_sched;
1756                 }
1757         }
1758         return NETDEV_TX_OK;
1759 }
1760
1761 #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1762
1763 /*
1764  *      eth_hdr_len - return the length of an Ethernet header
1765  *      @data: pointer to the start of the Ethernet header
1766  *
1767  *      Returns the length of an Ethernet header, including optional VLAN tag.
1768  */
1769 static inline int eth_hdr_len(const void *data)
1770 {
1771         const struct ethhdr *e = data;
1772
1773         return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1774 }
1775
1776 /*
1777  * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1778  */
1779 int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1780 {
1781         struct adapter *adapter = dev->ml_priv;
1782         struct sge *sge = adapter->sge;
1783         struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port],
1784                                                 smp_processor_id());
1785         struct cpl_tx_pkt *cpl;
1786         struct sk_buff *orig_skb = skb;
1787         int ret;
1788
1789         if (skb->protocol == htons(ETH_P_CPL5))
1790                 goto send;
1791
1792         /*
1793          * We are using a non-standard hard_header_len.
1794          * Allocate more header room in the rare cases it is not big enough.
1795          */
1796         if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1797                 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1798                 ++st->tx_need_hdrroom;
1799                 dev_kfree_skb_any(orig_skb);
1800                 if (!skb)
1801                         return NETDEV_TX_OK;
1802         }
1803
1804         if (skb_shinfo(skb)->gso_size) {
1805                 int eth_type;
1806                 struct cpl_tx_pkt_lso *hdr;
1807
1808                 ++st->tx_tso;
1809
1810                 eth_type = skb_network_offset(skb) == ETH_HLEN ?
1811                         CPL_ETH_II : CPL_ETH_II_VLAN;
1812
1813                 hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr));
1814                 hdr->opcode = CPL_TX_PKT_LSO;
1815                 hdr->ip_csum_dis = hdr->l4_csum_dis = 0;
1816                 hdr->ip_hdr_words = ip_hdr(skb)->ihl;
1817                 hdr->tcp_hdr_words = tcp_hdr(skb)->doff;
1818                 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1819                                                           skb_shinfo(skb)->gso_size));
1820                 hdr->len = htonl(skb->len - sizeof(*hdr));
1821                 cpl = (struct cpl_tx_pkt *)hdr;
1822         } else {
1823                 /*
1824                  * Packets shorter than ETH_HLEN can break the MAC, drop them
1825                  * early.  Also, we may get oversized packets because some
1826                  * parts of the kernel don't handle our unusual hard_header_len
1827                  * right, drop those too.
1828                  */
1829                 if (unlikely(skb->len < ETH_HLEN ||
1830                              skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1831                         pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1832                                  skb->len, eth_hdr_len(skb->data), dev->mtu);
1833                         dev_kfree_skb_any(skb);
1834                         return NETDEV_TX_OK;
1835                 }
1836
1837                 if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
1838                     skb->ip_summed == CHECKSUM_PARTIAL &&
1839                     ip_hdr(skb)->protocol == IPPROTO_UDP) {
1840                         if (unlikely(skb_checksum_help(skb))) {
1841                                 pr_debug("%s: unable to do udp checksum\n", dev->name);
1842                                 dev_kfree_skb_any(skb);
1843                                 return NETDEV_TX_OK;
1844                         }
1845                 }
1846
1847                 /* Hmmm, assuming to catch the gratious arp... and we'll use
1848                  * it to flush out stuck espi packets...
1849                  */
1850                 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1851                         if (skb->protocol == htons(ETH_P_ARP) &&
1852                             arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) {
1853                                 adapter->sge->espibug_skb[dev->if_port] = skb;
1854                                 /* We want to re-use this skb later. We
1855                                  * simply bump the reference count and it
1856                                  * will not be freed...
1857                                  */
1858                                 skb = skb_get(skb);
1859                         }
1860                 }
1861
1862                 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1863                 cpl->opcode = CPL_TX_PKT;
1864                 cpl->ip_csum_dis = 1;    /* SW calculates IP csum */
1865                 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1;
1866                 /* the length field isn't used so don't bother setting it */
1867
1868                 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1869         }
1870         cpl->iff = dev->if_port;
1871
1872 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1873         if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
1874                 cpl->vlan_valid = 1;
1875                 cpl->vlan = htons(vlan_tx_tag_get(skb));
1876                 st->vlan_insert++;
1877         } else
1878 #endif
1879                 cpl->vlan_valid = 0;
1880
1881 send:
1882         dev->trans_start = jiffies;
1883         ret = t1_sge_tx(skb, adapter, 0, dev);
1884
1885         /* If transmit busy, and we reallocated skb's due to headroom limit,
1886          * then silently discard to avoid leak.
1887          */
1888         if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
1889                 dev_kfree_skb_any(skb);
1890                 ret = NETDEV_TX_OK;
1891         }
1892         return ret;
1893 }
1894
1895 /*
1896  * Callback for the Tx buffer reclaim timer.  Runs with softirqs disabled.
1897  */
1898 static void sge_tx_reclaim_cb(unsigned long data)
1899 {
1900         int i;
1901         struct sge *sge = (struct sge *)data;
1902
1903         for (i = 0; i < SGE_CMDQ_N; ++i) {
1904                 struct cmdQ *q = &sge->cmdQ[i];
1905
1906                 if (!spin_trylock(&q->lock))
1907                         continue;
1908
1909                 reclaim_completed_tx(sge, q);
1910                 if (i == 0 && q->in_use) {    /* flush pending credits */
1911                         writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1912                 }
1913                 spin_unlock(&q->lock);
1914         }
1915         mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1916 }
1917
1918 /*
1919  * Propagate changes of the SGE coalescing parameters to the HW.
1920  */
1921 int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1922 {
1923         sge->fixed_intrtimer = p->rx_coalesce_usecs *
1924                 core_ticks_per_usec(sge->adapter);
1925         writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1926         return 0;
1927 }
1928
1929 /*
1930  * Allocates both RX and TX resources and configures the SGE. However,
1931  * the hardware is not enabled yet.
1932  */
1933 int t1_sge_configure(struct sge *sge, struct sge_params *p)
1934 {
1935         if (alloc_rx_resources(sge, p))
1936                 return -ENOMEM;
1937         if (alloc_tx_resources(sge, p)) {
1938                 free_rx_resources(sge);
1939                 return -ENOMEM;
1940         }
1941         configure_sge(sge, p);
1942
1943         /*
1944          * Now that we have sized the free lists calculate the payload
1945          * capacity of the large buffers.  Other parts of the driver use
1946          * this to set the max offload coalescing size so that RX packets
1947          * do not overflow our large buffers.
1948          */
1949         p->large_buf_capacity = jumbo_payload_capacity(sge);
1950         return 0;
1951 }
1952
1953 /*
1954  * Disables the DMA engine.
1955  */
1956 void t1_sge_stop(struct sge *sge)
1957 {
1958         int i;
1959         writel(0, sge->adapter->regs + A_SG_CONTROL);
1960         readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1961
1962         if (is_T2(sge->adapter))
1963                 del_timer_sync(&sge->espibug_timer);
1964
1965         del_timer_sync(&sge->tx_reclaim_timer);
1966         if (sge->tx_sched)
1967                 tx_sched_stop(sge);
1968
1969         for (i = 0; i < MAX_NPORTS; i++)
1970                 kfree_skb(sge->espibug_skb[i]);
1971 }
1972
1973 /*
1974  * Enables the DMA engine.
1975  */
1976 void t1_sge_start(struct sge *sge)
1977 {
1978         refill_free_list(sge, &sge->freelQ[0]);
1979         refill_free_list(sge, &sge->freelQ[1]);
1980
1981         writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1982         doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1983         readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1984
1985         mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1986
1987         if (is_T2(sge->adapter))
1988                 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1989 }
1990
1991 /*
1992  * Callback for the T2 ESPI 'stuck packet feature' workaorund
1993  */
1994 static void espibug_workaround_t204(unsigned long data)
1995 {
1996         struct adapter *adapter = (struct adapter *)data;
1997         struct sge *sge = adapter->sge;
1998         unsigned int nports = adapter->params.nports;
1999         u32 seop[MAX_NPORTS];
2000
2001         if (adapter->open_device_map & PORT_MASK) {
2002                 int i;
2003
2004                 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0)
2005                         return;
2006
2007                 for (i = 0; i < nports; i++) {
2008                         struct sk_buff *skb = sge->espibug_skb[i];
2009
2010                         if (!netif_running(adapter->port[i].dev) ||
2011                             netif_queue_stopped(adapter->port[i].dev) ||
2012                             !seop[i] || ((seop[i] & 0xfff) != 0) || !skb)
2013                                 continue;
2014
2015                         if (!skb->cb[0]) {
2016                                 u8 ch_mac_addr[ETH_ALEN] = {
2017                                         0x0, 0x7, 0x43, 0x0, 0x0, 0x0
2018                                 };
2019
2020                                 skb_copy_to_linear_data_offset(skb,
2021                                                     sizeof(struct cpl_tx_pkt),
2022                                                                ch_mac_addr,
2023                                                                ETH_ALEN);
2024                                 skb_copy_to_linear_data_offset(skb,
2025                                                                skb->len - 10,
2026                                                                ch_mac_addr,
2027                                                                ETH_ALEN);
2028                                 skb->cb[0] = 0xff;
2029                         }
2030
2031                         /* bump the reference count to avoid freeing of
2032                          * the skb once the DMA has completed.
2033                          */
2034                         skb = skb_get(skb);
2035                         t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
2036                 }
2037         }
2038         mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2039 }
2040
2041 static void espibug_workaround(unsigned long data)
2042 {
2043         struct adapter *adapter = (struct adapter *)data;
2044         struct sge *sge = adapter->sge;
2045
2046         if (netif_running(adapter->port[0].dev)) {
2047                 struct sk_buff *skb = sge->espibug_skb[0];
2048                 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2049
2050                 if ((seop & 0xfff0fff) == 0xfff && skb) {
2051                         if (!skb->cb[0]) {
2052                                 u8 ch_mac_addr[ETH_ALEN] =
2053                                     {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
2054                                 skb_copy_to_linear_data_offset(skb,
2055                                                      sizeof(struct cpl_tx_pkt),
2056                                                                ch_mac_addr,
2057                                                                ETH_ALEN);
2058                                 skb_copy_to_linear_data_offset(skb,
2059                                                                skb->len - 10,
2060                                                                ch_mac_addr,
2061                                                                ETH_ALEN);
2062                                 skb->cb[0] = 0xff;
2063                         }
2064
2065                         /* bump the reference count to avoid freeing of the
2066                          * skb once the DMA has completed.
2067                          */
2068                         skb = skb_get(skb);
2069                         t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2070                 }
2071         }
2072         mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2073 }
2074
2075 /*
2076  * Creates a t1_sge structure and returns suggested resource parameters.
2077  */
2078 struct sge * __devinit t1_sge_create(struct adapter *adapter,
2079                                      struct sge_params *p)
2080 {
2081         struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2082         int i;
2083
2084         if (!sge)
2085                 return NULL;
2086
2087         sge->adapter = adapter;
2088         sge->netdev = adapter->port[0].dev;
2089         sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
2090         sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
2091
2092         for_each_port(adapter, i) {
2093                 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2094                 if (!sge->port_stats[i])
2095                         goto nomem_port;
2096         }
2097
2098         init_timer(&sge->tx_reclaim_timer);
2099         sge->tx_reclaim_timer.data = (unsigned long)sge;
2100         sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
2101
2102         if (is_T2(sge->adapter)) {
2103                 init_timer(&sge->espibug_timer);
2104
2105                 if (adapter->params.nports > 1) {
2106                         tx_sched_init(sge);
2107                         sge->espibug_timer.function = espibug_workaround_t204;
2108                 } else
2109                         sge->espibug_timer.function = espibug_workaround;
2110                 sge->espibug_timer.data = (unsigned long)sge->adapter;
2111
2112                 sge->espibug_timeout = 1;
2113                 /* for T204, every 10ms */
2114                 if (adapter->params.nports > 1)
2115                         sge->espibug_timeout = HZ/100;
2116         }
2117
2118
2119         p->cmdQ_size[0] = SGE_CMDQ0_E_N;
2120         p->cmdQ_size[1] = SGE_CMDQ1_E_N;
2121         p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
2122         p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
2123         if (sge->tx_sched) {
2124                 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2125                         p->rx_coalesce_usecs = 15;
2126                 else
2127                         p->rx_coalesce_usecs = 50;
2128         } else
2129                 p->rx_coalesce_usecs = 50;
2130
2131         p->coalesce_enable = 0;
2132         p->sample_interval_usecs = 0;
2133
2134         return sge;
2135 nomem_port:
2136         while (i >= 0) {
2137                 free_percpu(sge->port_stats[i]);
2138                 --i;
2139         }
2140         kfree(sge);
2141         return NULL;
2142
2143 }