[PATCH] chelsio: cleanup pm3393 code
[linux-2.6.git] / drivers / net / chelsio / pm3393.c
1 /*****************************************************************************
2  *                                                                           *
3  * File: pm3393.c                                                            *
4  * $Revision: 1.16 $                                                         *
5  * $Date: 2005/05/14 00:59:32 $                                              *
6  * Description:                                                              *
7  *  PMC/SIERRA (pm3393) MAC-PHY functionality.                               *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  * This program is free software; you can redistribute it and/or modify      *
11  * it under the terms of the GNU General Public License, version 2, as       *
12  * published by the Free Software Foundation.                                *
13  *                                                                           *
14  * You should have received a copy of the GNU General Public License along   *
15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
17  *                                                                           *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
21  *                                                                           *
22  * http://www.chelsio.com                                                    *
23  *                                                                           *
24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
25  * All rights reserved.                                                      *
26  *                                                                           *
27  * Maintainers: maintainers@chelsio.com                                      *
28  *                                                                           *
29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
30  *          Tina Yang               <tainay@chelsio.com>                     *
31  *          Felix Marti             <felix@chelsio.com>                      *
32  *          Scott Bardone           <sbardone@chelsio.com>                   *
33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
34  *          Frank DiMambro          <frank@chelsio.com>                      *
35  *                                                                           *
36  * History:                                                                  *
37  *                                                                           *
38  ****************************************************************************/
39
40 #include "common.h"
41 #include "regs.h"
42 #include "gmac.h"
43 #include "elmer0.h"
44 #include "suni1x10gexp_regs.h"
45
46 #define OFFSET(REG_ADDR)    (REG_ADDR << 2)
47
48 /* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
49 #define MAX_FRAME_SIZE  9600
50
51 #define IPG 12
52 #define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \
53         SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \
54         SUNI1x10GEXP_BITMSK_TXXG_PADEN)
55 #define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
56         SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP)
57
58 /* Update statistics every 15 minutes */
59 #define STATS_TICK_SECS (15 * 60)
60
61 enum {                     /* RMON registers */
62         RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW,
63         RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW,
64         RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW,
65         RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW,
66         RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW,
67         RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW,
68         RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW,
69         RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW,
70         RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW,
71         RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW,
72         RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
73         RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
74         RxUndersizedFrames =  SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
75         RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
76         RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
77
78         TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
79         TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
80         TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW,
81         TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
82         TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
83         TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
84         TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
85         TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
86         TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
87 };
88
89 struct _cmac_instance {
90         u8 enabled;
91         u8 fc;
92         u8 mac_addr[6];
93 };
94
95 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
96 {
97         t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
98         return 0;
99 }
100
101 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
102 {
103         t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
104         return 0;
105 }
106
107 /* Port reset. */
108 static int pm3393_reset(struct cmac *cmac)
109 {
110         return 0;
111 }
112
113 /*
114  * Enable interrupts for the PM3393
115  *
116  *      1. Enable PM3393 BLOCK interrupts.
117  *      2. Enable PM3393 Master Interrupt bit(INTE)
118  *      3. Enable ELMER's PM3393 bit.
119  *      4. Enable Terminator external interrupt.
120  */
121 static int pm3393_interrupt_enable(struct cmac *cmac)
122 {
123         u32 pl_intr;
124
125         /* PM3393 - Enabling all hardware block interrupts.
126          */
127         pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
128         pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
129         pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
130         pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
131
132         /* Don't interrupt on statistics overflow, we are polling */
133         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
134         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
135         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
136         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
137
138         pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
139         pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
140         pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
141         pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
142         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
143         pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
144         pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
145         pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
146         pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
147
148         /* PM3393 - Global interrupt enable
149          */
150         /* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */
151         pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
152                 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ );
153
154         /* TERMINATOR - PL_INTERUPTS_EXT */
155         pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
156         pl_intr |= F_PL_INTR_EXT;
157         writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
158         return 0;
159 }
160
161 static int pm3393_interrupt_disable(struct cmac *cmac)
162 {
163         u32 elmer;
164
165         /* PM3393 - Enabling HW interrupt blocks. */
166         pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
167         pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
168         pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
169         pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
170         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
171         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
172         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
173         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
174         pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
175         pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
176         pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
177         pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
178         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
179         pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
180         pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
181         pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
182         pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
183
184         /* PM3393 - Global interrupt enable */
185         pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
186
187         /* ELMER - External chip interrupts. */
188         t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
189         elmer &= ~ELMER0_GP_BIT1;
190         t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
191
192         /* TERMINATOR - PL_INTERUPTS_EXT */
193         /* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP
194          * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.
195          */
196
197         return 0;
198 }
199
200 static int pm3393_interrupt_clear(struct cmac *cmac)
201 {
202         u32 elmer;
203         u32 pl_intr;
204         u32 val32;
205
206         /* PM3393 - Clearing HW interrupt blocks. Note, this assumes
207          *          bit WCIMODE=0 for a clear-on-read.
208          */
209         pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
210         pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
211         pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
212         pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
213         pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
214         pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
215         pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
216         pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
217         pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
218         pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
219         pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
220         pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
221                &val32);
222         pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
223         pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
224
225         /* PM3393 - Global interrupt status
226          */
227         pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
228
229         /* ELMER - External chip interrupts.
230          */
231         t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
232         elmer |= ELMER0_GP_BIT1;
233         t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
234
235         /* TERMINATOR - PL_INTERUPTS_EXT
236          */
237         pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
238         pl_intr |= F_PL_INTR_EXT;
239         writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
240
241         return 0;
242 }
243
244 /* Interrupt handler */
245 static int pm3393_interrupt_handler(struct cmac *cmac)
246 {
247         u32 master_intr_status;
248
249         /* Read the master interrupt status register. */
250         pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
251                &master_intr_status);
252         CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n",
253                master_intr_status);
254
255         /* TBD XXX Lets just clear everything for now */
256         pm3393_interrupt_clear(cmac);
257
258         return 0;
259 }
260
261 static int pm3393_enable(struct cmac *cmac, int which)
262 {
263         if (which & MAC_DIRECTION_RX)
264                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
265                         (RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN));
266
267         if (which & MAC_DIRECTION_TX) {
268                 u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0;
269
270                 if (cmac->instance->fc & PAUSE_RX)
271                         val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX;
272                 if (cmac->instance->fc & PAUSE_TX)
273                         val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX;
274                 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
275         }
276
277         cmac->instance->enabled |= which;
278         return 0;
279 }
280
281 static int pm3393_enable_port(struct cmac *cmac, int which)
282 {
283         /* Clear port statistics */
284         pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
285                 SUNI1x10GEXP_BITMSK_MSTAT_CLEAR);
286         udelay(2);
287         memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
288
289         pm3393_enable(cmac, which);
290
291         /*
292          * XXX This should be done by the PHY and preferrably not at all.
293          * The PHY doesn't give us link status indication on its own so have
294          * the link management code query it instead.
295          */
296         t1_link_changed(cmac->adapter, 0);
297         return 0;
298 }
299
300 static int pm3393_disable(struct cmac *cmac, int which)
301 {
302         if (which & MAC_DIRECTION_RX)
303                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
304         if (which & MAC_DIRECTION_TX)
305                 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
306
307         /*
308          * The disable is graceful. Give the PM3393 time.  Can't wait very
309          * long here, we may be holding locks.
310          */
311         udelay(20);
312
313         cmac->instance->enabled &= ~which;
314         return 0;
315 }
316
317 static int pm3393_loopback_enable(struct cmac *cmac)
318 {
319         return 0;
320 }
321
322 static int pm3393_loopback_disable(struct cmac *cmac)
323 {
324         return 0;
325 }
326
327 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
328 {
329         int enabled = cmac->instance->enabled;
330
331         /* MAX_FRAME_SIZE includes header + FCS, mtu doesn't */
332         mtu += 14 + 4;
333         if (mtu > MAX_FRAME_SIZE)
334                 return -EINVAL;
335
336         /* Disable Rx/Tx MAC before configuring it. */
337         if (enabled)
338                 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
339
340         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
341         pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
342
343         if (enabled)
344                 pm3393_enable(cmac, enabled);
345         return 0;
346 }
347
348 static u32 calc_crc(u8 *b, int len)
349 {
350         int i;
351         u32 crc = (u32)~0;
352
353         /* calculate crc one bit at a time */
354         while (len--) {
355                 crc ^= *b++;
356                 for (i = 0; i < 8; i++) {
357                         if (crc & 0x1)
358                                 crc = (crc >> 1) ^ 0xedb88320;
359                         else
360                                 crc = (crc >> 1);
361                 }
362         }
363
364         /* reverse bits */
365         crc = ((crc >> 4) & 0x0f0f0f0f) | ((crc << 4) & 0xf0f0f0f0);
366         crc = ((crc >> 2) & 0x33333333) | ((crc << 2) & 0xcccccccc);
367         crc = ((crc >> 1) & 0x55555555) | ((crc << 1) & 0xaaaaaaaa);
368         /* swap bytes */
369         crc = (crc >> 16) | (crc << 16);
370         crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
371
372         return crc;
373 }
374
375 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
376 {
377         int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
378         u32 rx_mode;
379
380         /* Disable MAC RX before reconfiguring it */
381         if (enabled)
382                 pm3393_disable(cmac, MAC_DIRECTION_RX);
383
384         pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
385         rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE |
386                      SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN);
387         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
388                 (u16)rx_mode);
389
390         if (t1_rx_mode_promisc(rm)) {
391                 /* Promiscuous mode. */
392                 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE;
393         }
394         if (t1_rx_mode_allmulti(rm)) {
395                 /* Accept all multicast. */
396                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
397                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
398                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
399                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
400                 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
401         } else if (t1_rx_mode_mc_cnt(rm)) {
402                 /* Accept one or more multicast(s). */
403                 u8 *addr;
404                 int bit;
405                 u16 mc_filter[4] = { 0, };
406
407                 while ((addr = t1_get_next_mcaddr(rm))) {
408                         bit = (calc_crc(addr, ETH_ALEN) >> 23) & 0x3f;  /* bit[23:28] */
409                         mc_filter[bit >> 4] |= 1 << (bit & 0xf);
410                 }
411                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
412                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
413                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
414                 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
415                 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
416         }
417
418         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
419
420         if (enabled)
421                 pm3393_enable(cmac, MAC_DIRECTION_RX);
422
423         return 0;
424 }
425
426 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
427                                       int *duplex, int *fc)
428 {
429         if (speed)
430                 *speed = SPEED_10000;
431         if (duplex)
432                 *duplex = DUPLEX_FULL;
433         if (fc)
434                 *fc = cmac->instance->fc;
435         return 0;
436 }
437
438 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
439                                       int fc)
440 {
441         if (speed >= 0 && speed != SPEED_10000)
442                 return -1;
443         if (duplex >= 0 && duplex != DUPLEX_FULL)
444                 return -1;
445         if (fc & ~(PAUSE_TX | PAUSE_RX))
446                 return -1;
447
448         if (fc != cmac->instance->fc) {
449                 cmac->instance->fc = (u8) fc;
450                 if (cmac->instance->enabled & MAC_DIRECTION_TX)
451                         pm3393_enable(cmac, MAC_DIRECTION_TX);
452         }
453         return 0;
454 }
455
456 static void pm3393_rmon_update(struct adapter *adapter, u32 offs, u64 *val,
457                                int over)
458 {
459         u32 val0, val1, val2;
460
461         t1_tpi_read(adapter, offs, &val0);
462         t1_tpi_read(adapter, offs + 4, &val1);
463         t1_tpi_read(adapter, offs + 8, &val2);
464
465         *val &= ~0ull << 40;
466         *val |= val0 & 0xffff;
467         *val |= (val1 & 0xffff) << 16;
468         *val |= (u64)(val2 & 0xff) << 32;
469
470         if (over)
471                 *val += 1ull << 40;
472 }
473
474 #define RMON_UPDATE(mac, name, stat_name) \
475         pm3393_rmon_update((mac)->adapter, OFFSET(name),                \
476                            &(mac)->stats.stat_name,                     \
477                    (ro &((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2)))
478
479
480 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
481                                                               int flag)
482 {
483         u64     ro;
484         u32     val0, val1, val2, val3;
485
486         /* Snap the counters */
487         pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
488                 SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
489
490         /* Counter rollover, clear on read */
491         pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
492         pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1);
493         pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2);
494         pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3);
495         ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
496                 (((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
497
498         /* Rx stats */
499         RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK);
500         RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK);
501         RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK);
502         RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK);
503         RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames);
504         RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors);
505         RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors,
506                                 RxInternalMACRcvError);
507         RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
508         RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors);
509         RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors);
510         RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
511         RMON_UPDATE(mac, RxFragments, RxRuntErrors);
512         RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
513         RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
514         RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
515
516         /* Tx stats */
517         RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
518         RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError,
519                                 TxInternalMACXmitError);
520         RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors);
521         RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK);
522         RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
523         RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
524         RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
525         RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
526         RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
527
528         return &mac->stats;
529 }
530
531 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
532 {
533         memcpy(mac_addr, cmac->instance->mac_addr, 6);
534         return 0;
535 }
536
537 static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
538 {
539         u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
540
541         /*
542          * MAC addr: 00:07:43:00:13:09
543          *
544          * ma[5] = 0x09
545          * ma[4] = 0x13
546          * ma[3] = 0x00
547          * ma[2] = 0x43
548          * ma[1] = 0x07
549          * ma[0] = 0x00
550          *
551          * The PM3393 requires byte swapping and reverse order entry
552          * when programming MAC addresses:
553          *
554          * low_bits[15:0]    = ma[1]:ma[0]
555          * mid_bits[31:16]   = ma[3]:ma[2]
556          * high_bits[47:32]  = ma[5]:ma[4]
557          */
558
559         /* Store local copy */
560         memcpy(cmac->instance->mac_addr, ma, 6);
561
562         lo = ((u32) ma[1] << 8) | (u32) ma[0];
563         mid = ((u32) ma[3] << 8) | (u32) ma[2];
564         hi = ((u32) ma[5] << 8) | (u32) ma[4];
565
566         /* Disable Rx/Tx MAC before configuring it. */
567         if (enabled)
568                 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
569
570         /* Set RXXG Station Address */
571         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
572         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
573         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
574
575         /* Set TXXG Station Address */
576         pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
577         pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
578         pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
579
580         /* Setup Exact Match Filter 1 with our MAC address
581          *
582          * Must disable exact match filter before configuring it.
583          */
584         pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
585         val &= 0xff0f;
586         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
587
588         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
589         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
590         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
591
592         val |= 0x0090;
593         pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
594
595         if (enabled)
596                 pm3393_enable(cmac, enabled);
597         return 0;
598 }
599
600 static void pm3393_destroy(struct cmac *cmac)
601 {
602         kfree(cmac);
603 }
604
605 static struct cmac_ops pm3393_ops = {
606         .destroy                 = pm3393_destroy,
607         .reset                   = pm3393_reset,
608         .interrupt_enable        = pm3393_interrupt_enable,
609         .interrupt_disable       = pm3393_interrupt_disable,
610         .interrupt_clear         = pm3393_interrupt_clear,
611         .interrupt_handler       = pm3393_interrupt_handler,
612         .enable                  = pm3393_enable_port,
613         .disable                 = pm3393_disable,
614         .loopback_enable         = pm3393_loopback_enable,
615         .loopback_disable        = pm3393_loopback_disable,
616         .set_mtu                 = pm3393_set_mtu,
617         .set_rx_mode             = pm3393_set_rx_mode,
618         .get_speed_duplex_fc     = pm3393_get_speed_duplex_fc,
619         .set_speed_duplex_fc     = pm3393_set_speed_duplex_fc,
620         .statistics_update       = pm3393_update_statistics,
621         .macaddress_get          = pm3393_macaddress_get,
622         .macaddress_set          = pm3393_macaddress_set
623 };
624
625 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
626 {
627         struct cmac *cmac;
628
629         cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
630         if (!cmac)
631                 return NULL;
632
633         cmac->ops = &pm3393_ops;
634         cmac->instance = (cmac_instance *) (cmac + 1);
635         cmac->adapter = adapter;
636         cmac->instance->fc = PAUSE_TX | PAUSE_RX;
637
638         t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
639         t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
640         t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
641         t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001);   /* PL4IO Enable */
642         t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
643         t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
644         t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
645         t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
646         t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
647         t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
648         t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
649         t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
650         t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
651         t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
652         t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
653         t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
654         t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
655         t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
656         t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
657         t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
658         t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
659         t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202);      /* PL4IO Calendar Repetitions */
660
661         t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080);      /* EFLX Enable */
662         t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000);      /* EFLX Channel Deprovision */
663         t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000);      /* EFLX Low Limit */
664         t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040);      /* EFLX High Limit */
665         t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc);      /* EFLX Almost Full */
666         t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199);      /* EFLX Almost Empty */
667         t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240);      /* EFLX Cut Through Threshold */
668         t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000);      /* EFLX Indirect Register Update */
669         t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001);      /* EFLX Channel Provision */
670         t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff);      /* EFLX Undocumented */
671         t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff);      /* EFLX Undocumented */
672         t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff);      /* EFLX enable overflow interrupt The other bit are undocumented */
673         t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff);      /* EFLX Undocumented */
674
675         t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000);      /* IFLX Configuration - enable */
676         t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000);      /* IFLX Channel Deprovision */
677         t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000);      /* IFLX Low Limit */
678         t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100);      /* IFLX High Limit */
679         t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00);      /* IFLX Almost Full Limit */
680         t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599);      /* IFLX Almost Empty Limit */
681         t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000);      /* IFLX Indirect Register Update */
682         t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001);      /* IFLX Channel Provision */
683         t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff);      /* IFLX Undocumented */
684         t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff);      /* IFLX Undocumented */
685         t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff);      /* IFLX Enable overflow interrupt.  The other bit are undocumented */
686
687         t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe);      /* PL4MOS Undocumented */
688         t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff);      /* PL4MOS Undocumented */
689         t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008);      /* PL4MOS Starving Burst Size */
690         t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008);      /* PL4MOS Hungry Burst Size */
691         t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008);      /* PL4MOS Transfer Size */
692         t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005);      /* PL4MOS Disable */
693
694         t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103);      /* PL4ODP Training Repeat and SOP rule */
695         t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000);      /* PL4ODP MAX_T setting */
696
697         t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087);      /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
698         t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f);      /* PL4IDU Enable Dip4 check error interrupts */
699
700         t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32);  /* # TXXG Config */
701         /* For T1 use timer based Mac flow control. */
702         t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
703         t1_tpi_write(adapter, OFFSET(0x2040), 0x059c);  /* # RXXG Config */
704         t1_tpi_write(adapter, OFFSET(0x2049), 0x0001);  /* # RXXG Cut Through */
705         t1_tpi_write(adapter, OFFSET(0x2070), 0x0000);  /* # Disable promiscuous mode */
706
707         /* Setup Exact Match Filter 0 to allow broadcast packets.
708          */
709         t1_tpi_write(adapter, OFFSET(0x206e), 0x0000);  /* # Disable Match Enable bit */
710         t1_tpi_write(adapter, OFFSET(0x204a), 0xffff);  /* # low addr */
711         t1_tpi_write(adapter, OFFSET(0x204b), 0xffff);  /* # mid addr */
712         t1_tpi_write(adapter, OFFSET(0x204c), 0xffff);  /* # high addr */
713         t1_tpi_write(adapter, OFFSET(0x206e), 0x0009);  /* # Enable Match Enable bit */
714
715         t1_tpi_write(adapter, OFFSET(0x0003), 0x0000);  /* # NO SOP/ PAD_EN setup */
716         t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0);  /* # RXEQB disabled */
717         t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f);  /* # No Preemphasis */
718
719         return cmac;
720 }
721
722 static int pm3393_mac_reset(adapter_t * adapter)
723 {
724         u32 val;
725         u32 x;
726         u32 is_pl4_reset_finished;
727         u32 is_pl4_outof_lock;
728         u32 is_xaui_mabc_pll_locked;
729         u32 successful_reset;
730         int i;
731
732         /* The following steps are required to properly reset
733          * the PM3393. This information is provided in the
734          * PM3393 datasheet (Issue 2: November 2002)
735          * section 13.1 -- Device Reset.
736          *
737          * The PM3393 has three types of components that are
738          * individually reset:
739          *
740          * DRESETB      - Digital circuitry
741          * PL4_ARESETB  - PL4 analog circuitry
742          * XAUI_ARESETB - XAUI bus analog circuitry
743          *
744          * Steps to reset PM3393 using RSTB pin:
745          *
746          * 1. Assert RSTB pin low ( write 0 )
747          * 2. Wait at least 1ms to initiate a complete initialization of device.
748          * 3. Wait until all external clocks and REFSEL are stable.
749          * 4. Wait minimum of 1ms. (after external clocks and REFEL are stable)
750          * 5. De-assert RSTB ( write 1 )
751          * 6. Wait until internal timers to expires after ~14ms.
752          *    - Allows analog clock synthesizer(PL4CSU) to stabilize to
753          *      selected reference frequency before allowing the digital
754          *      portion of the device to operate.
755          * 7. Wait at least 200us for XAUI interface to stabilize.
756          * 8. Verify the PM3393 came out of reset successfully.
757          *    Set successful reset flag if everything worked else try again
758          *    a few more times.
759          */
760
761         successful_reset = 0;
762         for (i = 0; i < 3 && !successful_reset; i++) {
763                 /* 1 */
764                 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
765                 val &= ~1;
766                 t1_tpi_write(adapter, A_ELMER0_GPO, val);
767
768                 /* 2 */
769                 msleep(1);
770
771                 /* 3 */
772                 msleep(1);
773
774                 /* 4 */
775                 msleep(2 /*1 extra ms for safety */ );
776
777                 /* 5 */
778                 val |= 1;
779                 t1_tpi_write(adapter, A_ELMER0_GPO, val);
780
781                 /* 6 */
782                 msleep(15 /*1 extra ms for safety */ );
783
784                 /* 7 */
785                 msleep(1);
786
787                 /* 8 */
788
789                 /* Has PL4 analog block come out of reset correctly? */
790                 t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);
791                 is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED);
792
793                 /* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence
794                  *         figure out why? */
795
796                 /* Have all PL4 block clocks locked? */
797                 x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL
798                      /*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */  |
799                      SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL |
800                      SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL |
801                      SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL);
802                 is_pl4_outof_lock = (val & x);
803
804                 /* ??? If this fails, might be able to software reset the XAUI part
805                  *     and try to recover... thus saving us from doing another HW reset */
806                 /* Has the XAUI MABC PLL circuitry stablized? */
807                 is_xaui_mabc_pll_locked =
808                     (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED);
809
810                 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
811                                     && is_xaui_mabc_pll_locked);
812
813                 CH_DBG(adapter, HW,
814                        "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
815                        "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
816                        i, is_pl4_reset_finished, val, is_pl4_outof_lock,
817                        is_xaui_mabc_pll_locked);
818         }
819         return successful_reset ? 0 : 1;
820 }
821
822 struct gmac t1_pm3393_ops = {
823         STATS_TICK_SECS,
824         pm3393_mac_create,
825         pm3393_mac_reset
826 };