[CASSINI]: Use shorter list_splice_init() macro for brevity.
[linux-2.6.git] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page.
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targetted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.
67  */
68
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/types.h>
73 #include <linux/compiler.h>
74 #include <linux/slab.h>
75 #include <linux/delay.h>
76 #include <linux/init.h>
77 #include <linux/ioport.h>
78 #include <linux/pci.h>
79 #include <linux/mm.h>
80 #include <linux/highmem.h>
81 #include <linux/list.h>
82 #include <linux/dma-mapping.h>
83
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/crc32.h>
89 #include <linux/random.h>
90 #include <linux/mii.h>
91 #include <linux/ip.h>
92 #include <linux/tcp.h>
93 #include <linux/mutex.h>
94
95 #include <net/checksum.h>
96
97 #include <asm/atomic.h>
98 #include <asm/system.h>
99 #include <asm/io.h>
100 #include <asm/byteorder.h>
101 #include <asm/uaccess.h>
102
103 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
104 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define CAS_NCPUS            num_online_cpus()
106
107 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
108 #define USE_NAPI
109 #define cas_skb_release(x)  netif_receive_skb(x)
110 #else
111 #define cas_skb_release(x)  netif_rx(x)
112 #endif
113
114 /* select which firmware to use */
115 #define USE_HP_WORKAROUND
116 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
117 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
118
119 #include "cassini.h"
120
121 #define USE_TX_COMPWB      /* use completion writeback registers */
122 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
123 #define USE_RX_BLANK       /* hw interrupt mitigation */
124 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
125
126 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
127  * also, we need to make cp->lock finer-grained.
128  */
129 #undef  USE_PCI_INTB
130 #undef  USE_PCI_INTC
131 #undef  USE_PCI_INTD
132 #undef  USE_QOS
133
134 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
135
136 /* rx processing options */
137 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
138 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
139 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
140 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
141 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
142
143 #define DRV_MODULE_NAME         "cassini"
144 #define PFX DRV_MODULE_NAME     ": "
145 #define DRV_MODULE_VERSION      "1.5"
146 #define DRV_MODULE_RELDATE      "4 Jan 2008"
147
148 #define CAS_DEF_MSG_ENABLE        \
149         (NETIF_MSG_DRV          | \
150          NETIF_MSG_PROBE        | \
151          NETIF_MSG_LINK         | \
152          NETIF_MSG_TIMER        | \
153          NETIF_MSG_IFDOWN       | \
154          NETIF_MSG_IFUP         | \
155          NETIF_MSG_RX_ERR       | \
156          NETIF_MSG_TX_ERR)
157
158 /* length of time before we decide the hardware is borked,
159  * and dev->tx_timeout() should be called to fix the problem
160  */
161 #define CAS_TX_TIMEOUT                  (HZ)
162 #define CAS_LINK_TIMEOUT                (22*HZ/10)
163 #define CAS_LINK_FAST_TIMEOUT           (1)
164
165 /* timeout values for state changing. these specify the number
166  * of 10us delays to be used before giving up.
167  */
168 #define STOP_TRIES_PHY 1000
169 #define STOP_TRIES     5000
170
171 /* specify a minimum frame size to deal with some fifo issues
172  * max mtu == 2 * page size - ethernet header - 64 - swivel =
173  *            2 * page_size - 0x50
174  */
175 #define CAS_MIN_FRAME                   97
176 #define CAS_1000MB_MIN_FRAME            255
177 #define CAS_MIN_MTU                     60
178 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
179
180 #if 1
181 /*
182  * Eliminate these and use separate atomic counters for each, to
183  * avoid a race condition.
184  */
185 #else
186 #define CAS_RESET_MTU                   1
187 #define CAS_RESET_ALL                   2
188 #define CAS_RESET_SPARE                 3
189 #endif
190
191 static char version[] __devinitdata =
192         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
193
194 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
195 static int link_mode;
196
197 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
198 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
199 MODULE_LICENSE("GPL");
200 module_param(cassini_debug, int, 0);
201 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
202 module_param(link_mode, int, 0);
203 MODULE_PARM_DESC(link_mode, "default link mode");
204
205 /*
206  * Work around for a PCS bug in which the link goes down due to the chip
207  * being confused and never showing a link status of "up."
208  */
209 #define DEFAULT_LINKDOWN_TIMEOUT 5
210 /*
211  * Value in seconds, for user input.
212  */
213 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
214 module_param(linkdown_timeout, int, 0);
215 MODULE_PARM_DESC(linkdown_timeout,
216 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
217
218 /*
219  * value in 'ticks' (units used by jiffies). Set when we init the
220  * module because 'HZ' in actually a function call on some flavors of
221  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
222  */
223 static int link_transition_timeout;
224
225
226
227 static u16 link_modes[] __devinitdata = {
228         BMCR_ANENABLE,                   /* 0 : autoneg */
229         0,                               /* 1 : 10bt half duplex */
230         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
231         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
232         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
233         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
234 };
235
236 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
237         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241         { 0, }
242 };
243
244 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
245
246 static void cas_set_link_modes(struct cas *cp);
247
248 static inline void cas_lock_tx(struct cas *cp)
249 {
250         int i;
251
252         for (i = 0; i < N_TX_RINGS; i++)
253                 spin_lock(&cp->tx_lock[i]);
254 }
255
256 static inline void cas_lock_all(struct cas *cp)
257 {
258         spin_lock_irq(&cp->lock);
259         cas_lock_tx(cp);
260 }
261
262 /* WTZ: QA was finding deadlock problems with the previous
263  * versions after long test runs with multiple cards per machine.
264  * See if replacing cas_lock_all with safer versions helps. The
265  * symptoms QA is reporting match those we'd expect if interrupts
266  * aren't being properly restored, and we fixed a previous deadlock
267  * with similar symptoms by using save/restore versions in other
268  * places.
269  */
270 #define cas_lock_all_save(cp, flags) \
271 do { \
272         struct cas *xxxcp = (cp); \
273         spin_lock_irqsave(&xxxcp->lock, flags); \
274         cas_lock_tx(xxxcp); \
275 } while (0)
276
277 static inline void cas_unlock_tx(struct cas *cp)
278 {
279         int i;
280
281         for (i = N_TX_RINGS; i > 0; i--)
282                 spin_unlock(&cp->tx_lock[i - 1]);
283 }
284
285 static inline void cas_unlock_all(struct cas *cp)
286 {
287         cas_unlock_tx(cp);
288         spin_unlock_irq(&cp->lock);
289 }
290
291 #define cas_unlock_all_restore(cp, flags) \
292 do { \
293         struct cas *xxxcp = (cp); \
294         cas_unlock_tx(xxxcp); \
295         spin_unlock_irqrestore(&xxxcp->lock, flags); \
296 } while (0)
297
298 static void cas_disable_irq(struct cas *cp, const int ring)
299 {
300         /* Make sure we won't get any more interrupts */
301         if (ring == 0) {
302                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
303                 return;
304         }
305
306         /* disable completion interrupts and selectively mask */
307         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
308                 switch (ring) {
309 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
310 #ifdef USE_PCI_INTB
311                 case 1:
312 #endif
313 #ifdef USE_PCI_INTC
314                 case 2:
315 #endif
316 #ifdef USE_PCI_INTD
317                 case 3:
318 #endif
319                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
320                                cp->regs + REG_PLUS_INTRN_MASK(ring));
321                         break;
322 #endif
323                 default:
324                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
325                                REG_PLUS_INTRN_MASK(ring));
326                         break;
327                 }
328         }
329 }
330
331 static inline void cas_mask_intr(struct cas *cp)
332 {
333         int i;
334
335         for (i = 0; i < N_RX_COMP_RINGS; i++)
336                 cas_disable_irq(cp, i);
337 }
338
339 static void cas_enable_irq(struct cas *cp, const int ring)
340 {
341         if (ring == 0) { /* all but TX_DONE */
342                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
343                 return;
344         }
345
346         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
347                 switch (ring) {
348 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
349 #ifdef USE_PCI_INTB
350                 case 1:
351 #endif
352 #ifdef USE_PCI_INTC
353                 case 2:
354 #endif
355 #ifdef USE_PCI_INTD
356                 case 3:
357 #endif
358                         writel(INTRN_MASK_RX_EN, cp->regs +
359                                REG_PLUS_INTRN_MASK(ring));
360                         break;
361 #endif
362                 default:
363                         break;
364                 }
365         }
366 }
367
368 static inline void cas_unmask_intr(struct cas *cp)
369 {
370         int i;
371
372         for (i = 0; i < N_RX_COMP_RINGS; i++)
373                 cas_enable_irq(cp, i);
374 }
375
376 static inline void cas_entropy_gather(struct cas *cp)
377 {
378 #ifdef USE_ENTROPY_DEV
379         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
380                 return;
381
382         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
383                             readl(cp->regs + REG_ENTROPY_IV),
384                             sizeof(uint64_t)*8);
385 #endif
386 }
387
388 static inline void cas_entropy_reset(struct cas *cp)
389 {
390 #ifdef USE_ENTROPY_DEV
391         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
392                 return;
393
394         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
395                cp->regs + REG_BIM_LOCAL_DEV_EN);
396         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
397         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
398
399         /* if we read back 0x0, we don't have an entropy device */
400         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
401                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
402 #endif
403 }
404
405 /* access to the phy. the following assumes that we've initialized the MIF to
406  * be in frame rather than bit-bang mode
407  */
408 static u16 cas_phy_read(struct cas *cp, int reg)
409 {
410         u32 cmd;
411         int limit = STOP_TRIES_PHY;
412
413         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
414         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
415         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
416         cmd |= MIF_FRAME_TURN_AROUND_MSB;
417         writel(cmd, cp->regs + REG_MIF_FRAME);
418
419         /* poll for completion */
420         while (limit-- > 0) {
421                 udelay(10);
422                 cmd = readl(cp->regs + REG_MIF_FRAME);
423                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
424                         return (cmd & MIF_FRAME_DATA_MASK);
425         }
426         return 0xFFFF; /* -1 */
427 }
428
429 static int cas_phy_write(struct cas *cp, int reg, u16 val)
430 {
431         int limit = STOP_TRIES_PHY;
432         u32 cmd;
433
434         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
435         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
436         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
437         cmd |= MIF_FRAME_TURN_AROUND_MSB;
438         cmd |= val & MIF_FRAME_DATA_MASK;
439         writel(cmd, cp->regs + REG_MIF_FRAME);
440
441         /* poll for completion */
442         while (limit-- > 0) {
443                 udelay(10);
444                 cmd = readl(cp->regs + REG_MIF_FRAME);
445                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
446                         return 0;
447         }
448         return -1;
449 }
450
451 static void cas_phy_powerup(struct cas *cp)
452 {
453         u16 ctl = cas_phy_read(cp, MII_BMCR);
454
455         if ((ctl & BMCR_PDOWN) == 0)
456                 return;
457         ctl &= ~BMCR_PDOWN;
458         cas_phy_write(cp, MII_BMCR, ctl);
459 }
460
461 static void cas_phy_powerdown(struct cas *cp)
462 {
463         u16 ctl = cas_phy_read(cp, MII_BMCR);
464
465         if (ctl & BMCR_PDOWN)
466                 return;
467         ctl |= BMCR_PDOWN;
468         cas_phy_write(cp, MII_BMCR, ctl);
469 }
470
471 /* cp->lock held. note: the last put_page will free the buffer */
472 static int cas_page_free(struct cas *cp, cas_page_t *page)
473 {
474         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
475                        PCI_DMA_FROMDEVICE);
476         __free_pages(page->buffer, cp->page_order);
477         kfree(page);
478         return 0;
479 }
480
481 #ifdef RX_COUNT_BUFFERS
482 #define RX_USED_ADD(x, y)       ((x)->used += (y))
483 #define RX_USED_SET(x, y)       ((x)->used  = (y))
484 #else
485 #define RX_USED_ADD(x, y)
486 #define RX_USED_SET(x, y)
487 #endif
488
489 /* local page allocation routines for the receive buffers. jumbo pages
490  * require at least 8K contiguous and 8K aligned buffers.
491  */
492 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
493 {
494         cas_page_t *page;
495
496         page = kmalloc(sizeof(cas_page_t), flags);
497         if (!page)
498                 return NULL;
499
500         INIT_LIST_HEAD(&page->list);
501         RX_USED_SET(page, 0);
502         page->buffer = alloc_pages(flags, cp->page_order);
503         if (!page->buffer)
504                 goto page_err;
505         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
506                                       cp->page_size, PCI_DMA_FROMDEVICE);
507         return page;
508
509 page_err:
510         kfree(page);
511         return NULL;
512 }
513
514 /* initialize spare pool of rx buffers, but allocate during the open */
515 static void cas_spare_init(struct cas *cp)
516 {
517         spin_lock(&cp->rx_inuse_lock);
518         INIT_LIST_HEAD(&cp->rx_inuse_list);
519         spin_unlock(&cp->rx_inuse_lock);
520
521         spin_lock(&cp->rx_spare_lock);
522         INIT_LIST_HEAD(&cp->rx_spare_list);
523         cp->rx_spares_needed = RX_SPARE_COUNT;
524         spin_unlock(&cp->rx_spare_lock);
525 }
526
527 /* used on close. free all the spare buffers. */
528 static void cas_spare_free(struct cas *cp)
529 {
530         struct list_head list, *elem, *tmp;
531
532         /* free spare buffers */
533         INIT_LIST_HEAD(&list);
534         spin_lock(&cp->rx_spare_lock);
535         list_splice_init(&cp->rx_spare_list, &list);
536         spin_unlock(&cp->rx_spare_lock);
537         list_for_each_safe(elem, tmp, &list) {
538                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
539         }
540
541         INIT_LIST_HEAD(&list);
542 #if 1
543         /*
544          * Looks like Adrian had protected this with a different
545          * lock than used everywhere else to manipulate this list.
546          */
547         spin_lock(&cp->rx_inuse_lock);
548         list_splice_init(&cp->rx_inuse_list, &list);
549         spin_unlock(&cp->rx_inuse_lock);
550 #else
551         spin_lock(&cp->rx_spare_lock);
552         list_splice_init(&cp->rx_inuse_list, &list);
553         spin_unlock(&cp->rx_spare_lock);
554 #endif
555         list_for_each_safe(elem, tmp, &list) {
556                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
557         }
558 }
559
560 /* replenish spares if needed */
561 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
562 {
563         struct list_head list, *elem, *tmp;
564         int needed, i;
565
566         /* check inuse list. if we don't need any more free buffers,
567          * just free it
568          */
569
570         /* make a local copy of the list */
571         INIT_LIST_HEAD(&list);
572         spin_lock(&cp->rx_inuse_lock);
573         list_splice_init(&cp->rx_inuse_list, &list);
574         spin_unlock(&cp->rx_inuse_lock);
575
576         list_for_each_safe(elem, tmp, &list) {
577                 cas_page_t *page = list_entry(elem, cas_page_t, list);
578
579                 if (page_count(page->buffer) > 1)
580                         continue;
581
582                 list_del(elem);
583                 spin_lock(&cp->rx_spare_lock);
584                 if (cp->rx_spares_needed > 0) {
585                         list_add(elem, &cp->rx_spare_list);
586                         cp->rx_spares_needed--;
587                         spin_unlock(&cp->rx_spare_lock);
588                 } else {
589                         spin_unlock(&cp->rx_spare_lock);
590                         cas_page_free(cp, page);
591                 }
592         }
593
594         /* put any inuse buffers back on the list */
595         if (!list_empty(&list)) {
596                 spin_lock(&cp->rx_inuse_lock);
597                 list_splice(&list, &cp->rx_inuse_list);
598                 spin_unlock(&cp->rx_inuse_lock);
599         }
600
601         spin_lock(&cp->rx_spare_lock);
602         needed = cp->rx_spares_needed;
603         spin_unlock(&cp->rx_spare_lock);
604         if (!needed)
605                 return;
606
607         /* we still need spares, so try to allocate some */
608         INIT_LIST_HEAD(&list);
609         i = 0;
610         while (i < needed) {
611                 cas_page_t *spare = cas_page_alloc(cp, flags);
612                 if (!spare)
613                         break;
614                 list_add(&spare->list, &list);
615                 i++;
616         }
617
618         spin_lock(&cp->rx_spare_lock);
619         list_splice(&list, &cp->rx_spare_list);
620         cp->rx_spares_needed -= i;
621         spin_unlock(&cp->rx_spare_lock);
622 }
623
624 /* pull a page from the list. */
625 static cas_page_t *cas_page_dequeue(struct cas *cp)
626 {
627         struct list_head *entry;
628         int recover;
629
630         spin_lock(&cp->rx_spare_lock);
631         if (list_empty(&cp->rx_spare_list)) {
632                 /* try to do a quick recovery */
633                 spin_unlock(&cp->rx_spare_lock);
634                 cas_spare_recover(cp, GFP_ATOMIC);
635                 spin_lock(&cp->rx_spare_lock);
636                 if (list_empty(&cp->rx_spare_list)) {
637                         if (netif_msg_rx_err(cp))
638                                 printk(KERN_ERR "%s: no spare buffers "
639                                        "available.\n", cp->dev->name);
640                         spin_unlock(&cp->rx_spare_lock);
641                         return NULL;
642                 }
643         }
644
645         entry = cp->rx_spare_list.next;
646         list_del(entry);
647         recover = ++cp->rx_spares_needed;
648         spin_unlock(&cp->rx_spare_lock);
649
650         /* trigger the timer to do the recovery */
651         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
652 #if 1
653                 atomic_inc(&cp->reset_task_pending);
654                 atomic_inc(&cp->reset_task_pending_spare);
655                 schedule_work(&cp->reset_task);
656 #else
657                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
658                 schedule_work(&cp->reset_task);
659 #endif
660         }
661         return list_entry(entry, cas_page_t, list);
662 }
663
664
665 static void cas_mif_poll(struct cas *cp, const int enable)
666 {
667         u32 cfg;
668
669         cfg  = readl(cp->regs + REG_MIF_CFG);
670         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
671
672         if (cp->phy_type & CAS_PHY_MII_MDIO1)
673                 cfg |= MIF_CFG_PHY_SELECT;
674
675         /* poll and interrupt on link status change. */
676         if (enable) {
677                 cfg |= MIF_CFG_POLL_EN;
678                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
679                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
680         }
681         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
682                cp->regs + REG_MIF_MASK);
683         writel(cfg, cp->regs + REG_MIF_CFG);
684 }
685
686 /* Must be invoked under cp->lock */
687 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
688 {
689         u16 ctl;
690 #if 1
691         int lcntl;
692         int changed = 0;
693         int oldstate = cp->lstate;
694         int link_was_not_down = !(oldstate == link_down);
695 #endif
696         /* Setup link parameters */
697         if (!ep)
698                 goto start_aneg;
699         lcntl = cp->link_cntl;
700         if (ep->autoneg == AUTONEG_ENABLE)
701                 cp->link_cntl = BMCR_ANENABLE;
702         else {
703                 cp->link_cntl = 0;
704                 if (ep->speed == SPEED_100)
705                         cp->link_cntl |= BMCR_SPEED100;
706                 else if (ep->speed == SPEED_1000)
707                         cp->link_cntl |= CAS_BMCR_SPEED1000;
708                 if (ep->duplex == DUPLEX_FULL)
709                         cp->link_cntl |= BMCR_FULLDPLX;
710         }
711 #if 1
712         changed = (lcntl != cp->link_cntl);
713 #endif
714 start_aneg:
715         if (cp->lstate == link_up) {
716                 printk(KERN_INFO "%s: PCS link down.\n",
717                        cp->dev->name);
718         } else {
719                 if (changed) {
720                         printk(KERN_INFO "%s: link configuration changed\n",
721                                cp->dev->name);
722                 }
723         }
724         cp->lstate = link_down;
725         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
726         if (!cp->hw_running)
727                 return;
728 #if 1
729         /*
730          * WTZ: If the old state was link_up, we turn off the carrier
731          * to replicate everything we do elsewhere on a link-down
732          * event when we were already in a link-up state..
733          */
734         if (oldstate == link_up)
735                 netif_carrier_off(cp->dev);
736         if (changed  && link_was_not_down) {
737                 /*
738                  * WTZ: This branch will simply schedule a full reset after
739                  * we explicitly changed link modes in an ioctl. See if this
740                  * fixes the link-problems we were having for forced mode.
741                  */
742                 atomic_inc(&cp->reset_task_pending);
743                 atomic_inc(&cp->reset_task_pending_all);
744                 schedule_work(&cp->reset_task);
745                 cp->timer_ticks = 0;
746                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
747                 return;
748         }
749 #endif
750         if (cp->phy_type & CAS_PHY_SERDES) {
751                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
752
753                 if (cp->link_cntl & BMCR_ANENABLE) {
754                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
755                         cp->lstate = link_aneg;
756                 } else {
757                         if (cp->link_cntl & BMCR_FULLDPLX)
758                                 val |= PCS_MII_CTRL_DUPLEX;
759                         val &= ~PCS_MII_AUTONEG_EN;
760                         cp->lstate = link_force_ok;
761                 }
762                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
763                 writel(val, cp->regs + REG_PCS_MII_CTRL);
764
765         } else {
766                 cas_mif_poll(cp, 0);
767                 ctl = cas_phy_read(cp, MII_BMCR);
768                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
769                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
770                 ctl |= cp->link_cntl;
771                 if (ctl & BMCR_ANENABLE) {
772                         ctl |= BMCR_ANRESTART;
773                         cp->lstate = link_aneg;
774                 } else {
775                         cp->lstate = link_force_ok;
776                 }
777                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
778                 cas_phy_write(cp, MII_BMCR, ctl);
779                 cas_mif_poll(cp, 1);
780         }
781
782         cp->timer_ticks = 0;
783         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
784 }
785
786 /* Must be invoked under cp->lock. */
787 static int cas_reset_mii_phy(struct cas *cp)
788 {
789         int limit = STOP_TRIES_PHY;
790         u16 val;
791
792         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
793         udelay(100);
794         while (limit--) {
795                 val = cas_phy_read(cp, MII_BMCR);
796                 if ((val & BMCR_RESET) == 0)
797                         break;
798                 udelay(10);
799         }
800         return (limit <= 0);
801 }
802
803 static void cas_saturn_firmware_load(struct cas *cp)
804 {
805         cas_saturn_patch_t *patch = cas_saturn_patch;
806
807         cas_phy_powerdown(cp);
808
809         /* expanded memory access mode */
810         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
811
812         /* pointer configuration for new firmware */
813         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
814         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
815         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
816         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
817         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
818         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
819         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
820         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
821
822         /* download new firmware */
823         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
824         cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
825         while (patch->addr) {
826                 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
827                 patch++;
828         }
829
830         /* enable firmware */
831         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
832         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
833 }
834
835
836 /* phy initialization */
837 static void cas_phy_init(struct cas *cp)
838 {
839         u16 val;
840
841         /* if we're in MII/GMII mode, set up phy */
842         if (CAS_PHY_MII(cp->phy_type)) {
843                 writel(PCS_DATAPATH_MODE_MII,
844                        cp->regs + REG_PCS_DATAPATH_MODE);
845
846                 cas_mif_poll(cp, 0);
847                 cas_reset_mii_phy(cp); /* take out of isolate mode */
848
849                 if (PHY_LUCENT_B0 == cp->phy_id) {
850                         /* workaround link up/down issue with lucent */
851                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
852                         cas_phy_write(cp, MII_BMCR, 0x00f1);
853                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
854
855                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
856                         /* workarounds for broadcom phy */
857                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
858                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
859                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
860                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
861                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
862                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
863                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
864                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
865                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
866                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
867                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
868
869                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
870                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
871                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
872                         if (val & 0x0080) {
873                                 /* link workaround */
874                                 cas_phy_write(cp, BROADCOM_MII_REG4,
875                                               val & ~0x0080);
876                         }
877
878                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
879                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
880                                SATURN_PCFG_FSI : 0x0,
881                                cp->regs + REG_SATURN_PCFG);
882
883                         /* load firmware to address 10Mbps auto-negotiation
884                          * issue. NOTE: this will need to be changed if the
885                          * default firmware gets fixed.
886                          */
887                         if (PHY_NS_DP83065 == cp->phy_id) {
888                                 cas_saturn_firmware_load(cp);
889                         }
890                         cas_phy_powerup(cp);
891                 }
892
893                 /* advertise capabilities */
894                 val = cas_phy_read(cp, MII_BMCR);
895                 val &= ~BMCR_ANENABLE;
896                 cas_phy_write(cp, MII_BMCR, val);
897                 udelay(10);
898
899                 cas_phy_write(cp, MII_ADVERTISE,
900                               cas_phy_read(cp, MII_ADVERTISE) |
901                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
902                                ADVERTISE_100HALF | ADVERTISE_100FULL |
903                                CAS_ADVERTISE_PAUSE |
904                                CAS_ADVERTISE_ASYM_PAUSE));
905
906                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
907                         /* make sure that we don't advertise half
908                          * duplex to avoid a chip issue
909                          */
910                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
911                         val &= ~CAS_ADVERTISE_1000HALF;
912                         val |= CAS_ADVERTISE_1000FULL;
913                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
914                 }
915
916         } else {
917                 /* reset pcs for serdes */
918                 u32 val;
919                 int limit;
920
921                 writel(PCS_DATAPATH_MODE_SERDES,
922                        cp->regs + REG_PCS_DATAPATH_MODE);
923
924                 /* enable serdes pins on saturn */
925                 if (cp->cas_flags & CAS_FLAG_SATURN)
926                         writel(0, cp->regs + REG_SATURN_PCFG);
927
928                 /* Reset PCS unit. */
929                 val = readl(cp->regs + REG_PCS_MII_CTRL);
930                 val |= PCS_MII_RESET;
931                 writel(val, cp->regs + REG_PCS_MII_CTRL);
932
933                 limit = STOP_TRIES;
934                 while (limit-- > 0) {
935                         udelay(10);
936                         if ((readl(cp->regs + REG_PCS_MII_CTRL) &
937                              PCS_MII_RESET) == 0)
938                                 break;
939                 }
940                 if (limit <= 0)
941                         printk(KERN_WARNING "%s: PCS reset bit would not "
942                                "clear [%08x].\n", cp->dev->name,
943                                readl(cp->regs + REG_PCS_STATE_MACHINE));
944
945                 /* Make sure PCS is disabled while changing advertisement
946                  * configuration.
947                  */
948                 writel(0x0, cp->regs + REG_PCS_CFG);
949
950                 /* Advertise all capabilities except half-duplex. */
951                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
952                 val &= ~PCS_MII_ADVERT_HD;
953                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
954                         PCS_MII_ADVERT_ASYM_PAUSE);
955                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
956
957                 /* enable PCS */
958                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
959
960                 /* pcs workaround: enable sync detect */
961                 writel(PCS_SERDES_CTRL_SYNCD_EN,
962                        cp->regs + REG_PCS_SERDES_CTRL);
963         }
964 }
965
966
967 static int cas_pcs_link_check(struct cas *cp)
968 {
969         u32 stat, state_machine;
970         int retval = 0;
971
972         /* The link status bit latches on zero, so you must
973          * read it twice in such a case to see a transition
974          * to the link being up.
975          */
976         stat = readl(cp->regs + REG_PCS_MII_STATUS);
977         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
978                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
979
980         /* The remote-fault indication is only valid
981          * when autoneg has completed.
982          */
983         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
984                      PCS_MII_STATUS_REMOTE_FAULT)) ==
985             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
986                 if (netif_msg_link(cp))
987                         printk(KERN_INFO "%s: PCS RemoteFault\n",
988                                cp->dev->name);
989         }
990
991         /* work around link detection issue by querying the PCS state
992          * machine directly.
993          */
994         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
995         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
996                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
997         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
998                 stat |= PCS_MII_STATUS_LINK_STATUS;
999         }
1000
1001         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1002                 if (cp->lstate != link_up) {
1003                         if (cp->opened) {
1004                                 cp->lstate = link_up;
1005                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1006
1007                                 cas_set_link_modes(cp);
1008                                 netif_carrier_on(cp->dev);
1009                         }
1010                 }
1011         } else if (cp->lstate == link_up) {
1012                 cp->lstate = link_down;
1013                 if (link_transition_timeout != 0 &&
1014                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1015                     !cp->link_transition_jiffies_valid) {
1016                         /*
1017                          * force a reset, as a workaround for the
1018                          * link-failure problem. May want to move this to a
1019                          * point a bit earlier in the sequence. If we had
1020                          * generated a reset a short time ago, we'll wait for
1021                          * the link timer to check the status until a
1022                          * timer expires (link_transistion_jiffies_valid is
1023                          * true when the timer is running.)  Instead of using
1024                          * a system timer, we just do a check whenever the
1025                          * link timer is running - this clears the flag after
1026                          * a suitable delay.
1027                          */
1028                         retval = 1;
1029                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1030                         cp->link_transition_jiffies = jiffies;
1031                         cp->link_transition_jiffies_valid = 1;
1032                 } else {
1033                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1034                 }
1035                 netif_carrier_off(cp->dev);
1036                 if (cp->opened && netif_msg_link(cp)) {
1037                         printk(KERN_INFO "%s: PCS link down.\n",
1038                                cp->dev->name);
1039                 }
1040
1041                 /* Cassini only: if you force a mode, there can be
1042                  * sync problems on link down. to fix that, the following
1043                  * things need to be checked:
1044                  * 1) read serialink state register
1045                  * 2) read pcs status register to verify link down.
1046                  * 3) if link down and serial link == 0x03, then you need
1047                  *    to global reset the chip.
1048                  */
1049                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1050                         /* should check to see if we're in a forced mode */
1051                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1052                         if (stat == 0x03)
1053                                 return 1;
1054                 }
1055         } else if (cp->lstate == link_down) {
1056                 if (link_transition_timeout != 0 &&
1057                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1058                     !cp->link_transition_jiffies_valid) {
1059                         /* force a reset, as a workaround for the
1060                          * link-failure problem.  May want to move
1061                          * this to a point a bit earlier in the
1062                          * sequence.
1063                          */
1064                         retval = 1;
1065                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1066                         cp->link_transition_jiffies = jiffies;
1067                         cp->link_transition_jiffies_valid = 1;
1068                 } else {
1069                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1070                 }
1071         }
1072
1073         return retval;
1074 }
1075
1076 static int cas_pcs_interrupt(struct net_device *dev,
1077                              struct cas *cp, u32 status)
1078 {
1079         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1080
1081         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1082                 return 0;
1083         return cas_pcs_link_check(cp);
1084 }
1085
1086 static int cas_txmac_interrupt(struct net_device *dev,
1087                                struct cas *cp, u32 status)
1088 {
1089         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1090
1091         if (!txmac_stat)
1092                 return 0;
1093
1094         if (netif_msg_intr(cp))
1095                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1096                         cp->dev->name, txmac_stat);
1097
1098         /* Defer timer expiration is quite normal,
1099          * don't even log the event.
1100          */
1101         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1102             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1103                 return 0;
1104
1105         spin_lock(&cp->stat_lock[0]);
1106         if (txmac_stat & MAC_TX_UNDERRUN) {
1107                 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1108                        dev->name);
1109                 cp->net_stats[0].tx_fifo_errors++;
1110         }
1111
1112         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1113                 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1114                        dev->name);
1115                 cp->net_stats[0].tx_errors++;
1116         }
1117
1118         /* The rest are all cases of one of the 16-bit TX
1119          * counters expiring.
1120          */
1121         if (txmac_stat & MAC_TX_COLL_NORMAL)
1122                 cp->net_stats[0].collisions += 0x10000;
1123
1124         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1125                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1126                 cp->net_stats[0].collisions += 0x10000;
1127         }
1128
1129         if (txmac_stat & MAC_TX_COLL_LATE) {
1130                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1131                 cp->net_stats[0].collisions += 0x10000;
1132         }
1133         spin_unlock(&cp->stat_lock[0]);
1134
1135         /* We do not keep track of MAC_TX_COLL_FIRST and
1136          * MAC_TX_PEAK_ATTEMPTS events.
1137          */
1138         return 0;
1139 }
1140
1141 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1142 {
1143         cas_hp_inst_t *inst;
1144         u32 val;
1145         int i;
1146
1147         i = 0;
1148         while ((inst = firmware) && inst->note) {
1149                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1150
1151                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1152                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1153                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1154
1155                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1156                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1157                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1158                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1159                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1160                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1161                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1162                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1163
1164                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1165                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1166                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1167                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1168                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1169                 ++firmware;
1170                 ++i;
1171         }
1172 }
1173
1174 static void cas_init_rx_dma(struct cas *cp)
1175 {
1176         u64 desc_dma = cp->block_dvma;
1177         u32 val;
1178         int i, size;
1179
1180         /* rx free descriptors */
1181         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1182         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1183         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1184         if ((N_RX_DESC_RINGS > 1) &&
1185             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1186                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1187         writel(val, cp->regs + REG_RX_CFG);
1188
1189         val = (unsigned long) cp->init_rxds[0] -
1190                 (unsigned long) cp->init_block;
1191         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1192         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1193         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1194
1195         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1196                 /* rx desc 2 is for IPSEC packets. however,
1197                  * we don't it that for that purpose.
1198                  */
1199                 val = (unsigned long) cp->init_rxds[1] -
1200                         (unsigned long) cp->init_block;
1201                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1202                 writel((desc_dma + val) & 0xffffffff, cp->regs +
1203                        REG_PLUS_RX_DB1_LOW);
1204                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1205                        REG_PLUS_RX_KICK1);
1206         }
1207
1208         /* rx completion registers */
1209         val = (unsigned long) cp->init_rxcs[0] -
1210                 (unsigned long) cp->init_block;
1211         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1212         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1213
1214         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1215                 /* rx comp 2-4 */
1216                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1217                         val = (unsigned long) cp->init_rxcs[i] -
1218                                 (unsigned long) cp->init_block;
1219                         writel((desc_dma + val) >> 32, cp->regs +
1220                                REG_PLUS_RX_CBN_HI(i));
1221                         writel((desc_dma + val) & 0xffffffff, cp->regs +
1222                                REG_PLUS_RX_CBN_LOW(i));
1223                 }
1224         }
1225
1226         /* read selective clear regs to prevent spurious interrupts
1227          * on reset because complete == kick.
1228          * selective clear set up to prevent interrupts on resets
1229          */
1230         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1231         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1232         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1233                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1234                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1235
1236                 /* 2 is different from 3 and 4 */
1237                 if (N_RX_COMP_RINGS > 1)
1238                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1239                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1240
1241                 for (i = 2; i < N_RX_COMP_RINGS; i++)
1242                         writel(INTR_RX_DONE_ALT,
1243                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1244         }
1245
1246         /* set up pause thresholds */
1247         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1248                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1249         val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1250                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1251         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1252
1253         /* zero out dma reassembly buffers */
1254         for (i = 0; i < 64; i++) {
1255                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1256                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1257                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1258                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1259         }
1260
1261         /* make sure address register is 0 for normal operation */
1262         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1263         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1264
1265         /* interrupt mitigation */
1266 #ifdef USE_RX_BLANK
1267         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1268         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1269         writel(val, cp->regs + REG_RX_BLANK);
1270 #else
1271         writel(0x0, cp->regs + REG_RX_BLANK);
1272 #endif
1273
1274         /* interrupt generation as a function of low water marks for
1275          * free desc and completion entries. these are used to trigger
1276          * housekeeping for rx descs. we don't use the free interrupt
1277          * as it's not very useful
1278          */
1279         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1280         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1281         writel(val, cp->regs + REG_RX_AE_THRESH);
1282         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1283                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1284                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1285         }
1286
1287         /* Random early detect registers. useful for congestion avoidance.
1288          * this should be tunable.
1289          */
1290         writel(0x0, cp->regs + REG_RX_RED);
1291
1292         /* receive page sizes. default == 2K (0x800) */
1293         val = 0;
1294         if (cp->page_size == 0x1000)
1295                 val = 0x1;
1296         else if (cp->page_size == 0x2000)
1297                 val = 0x2;
1298         else if (cp->page_size == 0x4000)
1299                 val = 0x3;
1300
1301         /* round mtu + offset. constrain to page size. */
1302         size = cp->dev->mtu + 64;
1303         if (size > cp->page_size)
1304                 size = cp->page_size;
1305
1306         if (size <= 0x400)
1307                 i = 0x0;
1308         else if (size <= 0x800)
1309                 i = 0x1;
1310         else if (size <= 0x1000)
1311                 i = 0x2;
1312         else
1313                 i = 0x3;
1314
1315         cp->mtu_stride = 1 << (i + 10);
1316         val  = CAS_BASE(RX_PAGE_SIZE, val);
1317         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1318         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1319         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1320         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1321
1322         /* enable the header parser if desired */
1323         if (CAS_HP_FIRMWARE == cas_prog_null)
1324                 return;
1325
1326         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1327         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1328         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1329         writel(val, cp->regs + REG_HP_CFG);
1330 }
1331
1332 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1333 {
1334         memset(rxc, 0, sizeof(*rxc));
1335         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1336 }
1337
1338 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1339  * flipping is protected by the fact that the chip will not
1340  * hand back the same page index while it's being processed.
1341  */
1342 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1343 {
1344         cas_page_t *page = cp->rx_pages[1][index];
1345         cas_page_t *new;
1346
1347         if (page_count(page->buffer) == 1)
1348                 return page;
1349
1350         new = cas_page_dequeue(cp);
1351         if (new) {
1352                 spin_lock(&cp->rx_inuse_lock);
1353                 list_add(&page->list, &cp->rx_inuse_list);
1354                 spin_unlock(&cp->rx_inuse_lock);
1355         }
1356         return new;
1357 }
1358
1359 /* this needs to be changed if we actually use the ENC RX DESC ring */
1360 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1361                                  const int index)
1362 {
1363         cas_page_t **page0 = cp->rx_pages[0];
1364         cas_page_t **page1 = cp->rx_pages[1];
1365
1366         /* swap if buffer is in use */
1367         if (page_count(page0[index]->buffer) > 1) {
1368                 cas_page_t *new = cas_page_spare(cp, index);
1369                 if (new) {
1370                         page1[index] = page0[index];
1371                         page0[index] = new;
1372                 }
1373         }
1374         RX_USED_SET(page0[index], 0);
1375         return page0[index];
1376 }
1377
1378 static void cas_clean_rxds(struct cas *cp)
1379 {
1380         /* only clean ring 0 as ring 1 is used for spare buffers */
1381         struct cas_rx_desc *rxd = cp->init_rxds[0];
1382         int i, size;
1383
1384         /* release all rx flows */
1385         for (i = 0; i < N_RX_FLOWS; i++) {
1386                 struct sk_buff *skb;
1387                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1388                         cas_skb_release(skb);
1389                 }
1390         }
1391
1392         /* initialize descriptors */
1393         size = RX_DESC_RINGN_SIZE(0);
1394         for (i = 0; i < size; i++) {
1395                 cas_page_t *page = cas_page_swap(cp, 0, i);
1396                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1397                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1398                                             CAS_BASE(RX_INDEX_RING, 0));
1399         }
1400
1401         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1402         cp->rx_last[0] = 0;
1403         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1404 }
1405
1406 static void cas_clean_rxcs(struct cas *cp)
1407 {
1408         int i, j;
1409
1410         /* take ownership of rx comp descriptors */
1411         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1412         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1413         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1414                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1415                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1416                         cas_rxc_init(rxc + j);
1417                 }
1418         }
1419 }
1420
1421 #if 0
1422 /* When we get a RX fifo overflow, the RX unit is probably hung
1423  * so we do the following.
1424  *
1425  * If any part of the reset goes wrong, we return 1 and that causes the
1426  * whole chip to be reset.
1427  */
1428 static int cas_rxmac_reset(struct cas *cp)
1429 {
1430         struct net_device *dev = cp->dev;
1431         int limit;
1432         u32 val;
1433
1434         /* First, reset MAC RX. */
1435         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1436         for (limit = 0; limit < STOP_TRIES; limit++) {
1437                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1438                         break;
1439                 udelay(10);
1440         }
1441         if (limit == STOP_TRIES) {
1442                 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1443                        "chip.\n", dev->name);
1444                 return 1;
1445         }
1446
1447         /* Second, disable RX DMA. */
1448         writel(0, cp->regs + REG_RX_CFG);
1449         for (limit = 0; limit < STOP_TRIES; limit++) {
1450                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1451                         break;
1452                 udelay(10);
1453         }
1454         if (limit == STOP_TRIES) {
1455                 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1456                        "chip.\n", dev->name);
1457                 return 1;
1458         }
1459
1460         mdelay(5);
1461
1462         /* Execute RX reset command. */
1463         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1464         for (limit = 0; limit < STOP_TRIES; limit++) {
1465                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1466                         break;
1467                 udelay(10);
1468         }
1469         if (limit == STOP_TRIES) {
1470                 printk(KERN_ERR "%s: RX reset command will not execute, "
1471                        "resetting whole chip.\n", dev->name);
1472                 return 1;
1473         }
1474
1475         /* reset driver rx state */
1476         cas_clean_rxds(cp);
1477         cas_clean_rxcs(cp);
1478
1479         /* Now, reprogram the rest of RX unit. */
1480         cas_init_rx_dma(cp);
1481
1482         /* re-enable */
1483         val = readl(cp->regs + REG_RX_CFG);
1484         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1485         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1486         val = readl(cp->regs + REG_MAC_RX_CFG);
1487         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1488         return 0;
1489 }
1490 #endif
1491
1492 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1493                                u32 status)
1494 {
1495         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1496
1497         if (!stat)
1498                 return 0;
1499
1500         if (netif_msg_intr(cp))
1501                 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1502                         cp->dev->name, stat);
1503
1504         /* these are all rollovers */
1505         spin_lock(&cp->stat_lock[0]);
1506         if (stat & MAC_RX_ALIGN_ERR)
1507                 cp->net_stats[0].rx_frame_errors += 0x10000;
1508
1509         if (stat & MAC_RX_CRC_ERR)
1510                 cp->net_stats[0].rx_crc_errors += 0x10000;
1511
1512         if (stat & MAC_RX_LEN_ERR)
1513                 cp->net_stats[0].rx_length_errors += 0x10000;
1514
1515         if (stat & MAC_RX_OVERFLOW) {
1516                 cp->net_stats[0].rx_over_errors++;
1517                 cp->net_stats[0].rx_fifo_errors++;
1518         }
1519
1520         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1521          * events.
1522          */
1523         spin_unlock(&cp->stat_lock[0]);
1524         return 0;
1525 }
1526
1527 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1528                              u32 status)
1529 {
1530         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1531
1532         if (!stat)
1533                 return 0;
1534
1535         if (netif_msg_intr(cp))
1536                 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1537                         cp->dev->name, stat);
1538
1539         /* This interrupt is just for pause frame and pause
1540          * tracking.  It is useful for diagnostics and debug
1541          * but probably by default we will mask these events.
1542          */
1543         if (stat & MAC_CTRL_PAUSE_STATE)
1544                 cp->pause_entered++;
1545
1546         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1547                 cp->pause_last_time_recvd = (stat >> 16);
1548
1549         return 0;
1550 }
1551
1552
1553 /* Must be invoked under cp->lock. */
1554 static inline int cas_mdio_link_not_up(struct cas *cp)
1555 {
1556         u16 val;
1557
1558         switch (cp->lstate) {
1559         case link_force_ret:
1560                 if (netif_msg_link(cp))
1561                         printk(KERN_INFO "%s: Autoneg failed again, keeping"
1562                                 " forced mode\n", cp->dev->name);
1563                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1564                 cp->timer_ticks = 5;
1565                 cp->lstate = link_force_ok;
1566                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1567                 break;
1568
1569         case link_aneg:
1570                 val = cas_phy_read(cp, MII_BMCR);
1571
1572                 /* Try forced modes. we try things in the following order:
1573                  * 1000 full -> 100 full/half -> 10 half
1574                  */
1575                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1576                 val |= BMCR_FULLDPLX;
1577                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1578                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1579                 cas_phy_write(cp, MII_BMCR, val);
1580                 cp->timer_ticks = 5;
1581                 cp->lstate = link_force_try;
1582                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1583                 break;
1584
1585         case link_force_try:
1586                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1587                 val = cas_phy_read(cp, MII_BMCR);
1588                 cp->timer_ticks = 5;
1589                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1590                         val &= ~CAS_BMCR_SPEED1000;
1591                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1592                         cas_phy_write(cp, MII_BMCR, val);
1593                         break;
1594                 }
1595
1596                 if (val & BMCR_SPEED100) {
1597                         if (val & BMCR_FULLDPLX) /* fd failed */
1598                                 val &= ~BMCR_FULLDPLX;
1599                         else { /* 100Mbps failed */
1600                                 val &= ~BMCR_SPEED100;
1601                         }
1602                         cas_phy_write(cp, MII_BMCR, val);
1603                         break;
1604                 }
1605         default:
1606                 break;
1607         }
1608         return 0;
1609 }
1610
1611
1612 /* must be invoked with cp->lock held */
1613 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1614 {
1615         int restart;
1616
1617         if (bmsr & BMSR_LSTATUS) {
1618                 /* Ok, here we got a link. If we had it due to a forced
1619                  * fallback, and we were configured for autoneg, we
1620                  * retry a short autoneg pass. If you know your hub is
1621                  * broken, use ethtool ;)
1622                  */
1623                 if ((cp->lstate == link_force_try) &&
1624                     (cp->link_cntl & BMCR_ANENABLE)) {
1625                         cp->lstate = link_force_ret;
1626                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1627                         cas_mif_poll(cp, 0);
1628                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1629                         cp->timer_ticks = 5;
1630                         if (cp->opened && netif_msg_link(cp))
1631                                 printk(KERN_INFO "%s: Got link after fallback, retrying"
1632                                        " autoneg once...\n", cp->dev->name);
1633                         cas_phy_write(cp, MII_BMCR,
1634                                       cp->link_fcntl | BMCR_ANENABLE |
1635                                       BMCR_ANRESTART);
1636                         cas_mif_poll(cp, 1);
1637
1638                 } else if (cp->lstate != link_up) {
1639                         cp->lstate = link_up;
1640                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1641
1642                         if (cp->opened) {
1643                                 cas_set_link_modes(cp);
1644                                 netif_carrier_on(cp->dev);
1645                         }
1646                 }
1647                 return 0;
1648         }
1649
1650         /* link not up. if the link was previously up, we restart the
1651          * whole process
1652          */
1653         restart = 0;
1654         if (cp->lstate == link_up) {
1655                 cp->lstate = link_down;
1656                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1657
1658                 netif_carrier_off(cp->dev);
1659                 if (cp->opened && netif_msg_link(cp))
1660                         printk(KERN_INFO "%s: Link down\n",
1661                                cp->dev->name);
1662                 restart = 1;
1663
1664         } else if (++cp->timer_ticks > 10)
1665                 cas_mdio_link_not_up(cp);
1666
1667         return restart;
1668 }
1669
1670 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1671                              u32 status)
1672 {
1673         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1674         u16 bmsr;
1675
1676         /* check for a link change */
1677         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1678                 return 0;
1679
1680         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1681         return cas_mii_link_check(cp, bmsr);
1682 }
1683
1684 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1685                              u32 status)
1686 {
1687         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1688
1689         if (!stat)
1690                 return 0;
1691
1692         printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1693                readl(cp->regs + REG_BIM_DIAG));
1694
1695         /* cassini+ has this reserved */
1696         if ((stat & PCI_ERR_BADACK) &&
1697             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1698                 printk("<No ACK64# during ABS64 cycle> ");
1699
1700         if (stat & PCI_ERR_DTRTO)
1701                 printk("<Delayed transaction timeout> ");
1702         if (stat & PCI_ERR_OTHER)
1703                 printk("<other> ");
1704         if (stat & PCI_ERR_BIM_DMA_WRITE)
1705                 printk("<BIM DMA 0 write req> ");
1706         if (stat & PCI_ERR_BIM_DMA_READ)
1707                 printk("<BIM DMA 0 read req> ");
1708         printk("\n");
1709
1710         if (stat & PCI_ERR_OTHER) {
1711                 u16 cfg;
1712
1713                 /* Interrogate PCI config space for the
1714                  * true cause.
1715                  */
1716                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1717                 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1718                        dev->name, cfg);
1719                 if (cfg & PCI_STATUS_PARITY)
1720                         printk(KERN_ERR "%s: PCI parity error detected.\n",
1721                                dev->name);
1722                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1723                         printk(KERN_ERR "%s: PCI target abort.\n",
1724                                dev->name);
1725                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1726                         printk(KERN_ERR "%s: PCI master acks target abort.\n",
1727                                dev->name);
1728                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1729                         printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1730                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1731                         printk(KERN_ERR "%s: PCI system error SERR#.\n",
1732                                dev->name);
1733                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1734                         printk(KERN_ERR "%s: PCI parity error.\n",
1735                                dev->name);
1736
1737                 /* Write the error bits back to clear them. */
1738                 cfg &= (PCI_STATUS_PARITY |
1739                         PCI_STATUS_SIG_TARGET_ABORT |
1740                         PCI_STATUS_REC_TARGET_ABORT |
1741                         PCI_STATUS_REC_MASTER_ABORT |
1742                         PCI_STATUS_SIG_SYSTEM_ERROR |
1743                         PCI_STATUS_DETECTED_PARITY);
1744                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1745         }
1746
1747         /* For all PCI errors, we should reset the chip. */
1748         return 1;
1749 }
1750
1751 /* All non-normal interrupt conditions get serviced here.
1752  * Returns non-zero if we should just exit the interrupt
1753  * handler right now (ie. if we reset the card which invalidates
1754  * all of the other original irq status bits).
1755  */
1756 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1757                             u32 status)
1758 {
1759         if (status & INTR_RX_TAG_ERROR) {
1760                 /* corrupt RX tag framing */
1761                 if (netif_msg_rx_err(cp))
1762                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1763                                 cp->dev->name);
1764                 spin_lock(&cp->stat_lock[0]);
1765                 cp->net_stats[0].rx_errors++;
1766                 spin_unlock(&cp->stat_lock[0]);
1767                 goto do_reset;
1768         }
1769
1770         if (status & INTR_RX_LEN_MISMATCH) {
1771                 /* length mismatch. */
1772                 if (netif_msg_rx_err(cp))
1773                         printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1774                                 cp->dev->name);
1775                 spin_lock(&cp->stat_lock[0]);
1776                 cp->net_stats[0].rx_errors++;
1777                 spin_unlock(&cp->stat_lock[0]);
1778                 goto do_reset;
1779         }
1780
1781         if (status & INTR_PCS_STATUS) {
1782                 if (cas_pcs_interrupt(dev, cp, status))
1783                         goto do_reset;
1784         }
1785
1786         if (status & INTR_TX_MAC_STATUS) {
1787                 if (cas_txmac_interrupt(dev, cp, status))
1788                         goto do_reset;
1789         }
1790
1791         if (status & INTR_RX_MAC_STATUS) {
1792                 if (cas_rxmac_interrupt(dev, cp, status))
1793                         goto do_reset;
1794         }
1795
1796         if (status & INTR_MAC_CTRL_STATUS) {
1797                 if (cas_mac_interrupt(dev, cp, status))
1798                         goto do_reset;
1799         }
1800
1801         if (status & INTR_MIF_STATUS) {
1802                 if (cas_mif_interrupt(dev, cp, status))
1803                         goto do_reset;
1804         }
1805
1806         if (status & INTR_PCI_ERROR_STATUS) {
1807                 if (cas_pci_interrupt(dev, cp, status))
1808                         goto do_reset;
1809         }
1810         return 0;
1811
1812 do_reset:
1813 #if 1
1814         atomic_inc(&cp->reset_task_pending);
1815         atomic_inc(&cp->reset_task_pending_all);
1816         printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1817                dev->name, status);
1818         schedule_work(&cp->reset_task);
1819 #else
1820         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1821         printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1822         schedule_work(&cp->reset_task);
1823 #endif
1824         return 1;
1825 }
1826
1827 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1828  *       determining whether to do a netif_stop/wakeup
1829  */
1830 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1831 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1832 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1833                                   const int len)
1834 {
1835         unsigned long off = addr + len;
1836
1837         if (CAS_TABORT(cp) == 1)
1838                 return 0;
1839         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1840                 return 0;
1841         return TX_TARGET_ABORT_LEN;
1842 }
1843
1844 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1845 {
1846         struct cas_tx_desc *txds;
1847         struct sk_buff **skbs;
1848         struct net_device *dev = cp->dev;
1849         int entry, count;
1850
1851         spin_lock(&cp->tx_lock[ring]);
1852         txds = cp->init_txds[ring];
1853         skbs = cp->tx_skbs[ring];
1854         entry = cp->tx_old[ring];
1855
1856         count = TX_BUFF_COUNT(ring, entry, limit);
1857         while (entry != limit) {
1858                 struct sk_buff *skb = skbs[entry];
1859                 dma_addr_t daddr;
1860                 u32 dlen;
1861                 int frag;
1862
1863                 if (!skb) {
1864                         /* this should never occur */
1865                         entry = TX_DESC_NEXT(ring, entry);
1866                         continue;
1867                 }
1868
1869                 /* however, we might get only a partial skb release. */
1870                 count -= skb_shinfo(skb)->nr_frags +
1871                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1872                 if (count < 0)
1873                         break;
1874
1875                 if (netif_msg_tx_done(cp))
1876                         printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1877                                cp->dev->name, ring, entry);
1878
1879                 skbs[entry] = NULL;
1880                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1881
1882                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1883                         struct cas_tx_desc *txd = txds + entry;
1884
1885                         daddr = le64_to_cpu(txd->buffer);
1886                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1887                                        le64_to_cpu(txd->control));
1888                         pci_unmap_page(cp->pdev, daddr, dlen,
1889                                        PCI_DMA_TODEVICE);
1890                         entry = TX_DESC_NEXT(ring, entry);
1891
1892                         /* tiny buffer may follow */
1893                         if (cp->tx_tiny_use[ring][entry].used) {
1894                                 cp->tx_tiny_use[ring][entry].used = 0;
1895                                 entry = TX_DESC_NEXT(ring, entry);
1896                         }
1897                 }
1898
1899                 spin_lock(&cp->stat_lock[ring]);
1900                 cp->net_stats[ring].tx_packets++;
1901                 cp->net_stats[ring].tx_bytes += skb->len;
1902                 spin_unlock(&cp->stat_lock[ring]);
1903                 dev_kfree_skb_irq(skb);
1904         }
1905         cp->tx_old[ring] = entry;
1906
1907         /* this is wrong for multiple tx rings. the net device needs
1908          * multiple queues for this to do the right thing.  we wait
1909          * for 2*packets to be available when using tiny buffers
1910          */
1911         if (netif_queue_stopped(dev) &&
1912             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1913                 netif_wake_queue(dev);
1914         spin_unlock(&cp->tx_lock[ring]);
1915 }
1916
1917 static void cas_tx(struct net_device *dev, struct cas *cp,
1918                    u32 status)
1919 {
1920         int limit, ring;
1921 #ifdef USE_TX_COMPWB
1922         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1923 #endif
1924         if (netif_msg_intr(cp))
1925                 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1926                         cp->dev->name, status, (unsigned long long)compwb);
1927         /* process all the rings */
1928         for (ring = 0; ring < N_TX_RINGS; ring++) {
1929 #ifdef USE_TX_COMPWB
1930                 /* use the completion writeback registers */
1931                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1932                         CAS_VAL(TX_COMPWB_LSB, compwb);
1933                 compwb = TX_COMPWB_NEXT(compwb);
1934 #else
1935                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1936 #endif
1937                 if (cp->tx_old[ring] != limit)
1938                         cas_tx_ringN(cp, ring, limit);
1939         }
1940 }
1941
1942
1943 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1944                               int entry, const u64 *words,
1945                               struct sk_buff **skbref)
1946 {
1947         int dlen, hlen, len, i, alloclen;
1948         int off, swivel = RX_SWIVEL_OFF_VAL;
1949         struct cas_page *page;
1950         struct sk_buff *skb;
1951         void *addr, *crcaddr;
1952         __sum16 csum;
1953         char *p;
1954
1955         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1956         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1957         len  = hlen + dlen;
1958
1959         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1960                 alloclen = len;
1961         else
1962                 alloclen = max(hlen, RX_COPY_MIN);
1963
1964         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1965         if (skb == NULL)
1966                 return -1;
1967
1968         *skbref = skb;
1969         skb_reserve(skb, swivel);
1970
1971         p = skb->data;
1972         addr = crcaddr = NULL;
1973         if (hlen) { /* always copy header pages */
1974                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1975                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1976                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1977                         swivel;
1978
1979                 i = hlen;
1980                 if (!dlen) /* attach FCS */
1981                         i += cp->crc_size;
1982                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1983                                     PCI_DMA_FROMDEVICE);
1984                 addr = cas_page_map(page->buffer);
1985                 memcpy(p, addr + off, i);
1986                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1987                                     PCI_DMA_FROMDEVICE);
1988                 cas_page_unmap(addr);
1989                 RX_USED_ADD(page, 0x100);
1990                 p += hlen;
1991                 swivel = 0;
1992         }
1993
1994
1995         if (alloclen < (hlen + dlen)) {
1996                 skb_frag_t *frag = skb_shinfo(skb)->frags;
1997
1998                 /* normal or jumbo packets. we use frags */
1999                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2000                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2001                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2002
2003                 hlen = min(cp->page_size - off, dlen);
2004                 if (hlen < 0) {
2005                         if (netif_msg_rx_err(cp)) {
2006                                 printk(KERN_DEBUG "%s: rx page overflow: "
2007                                        "%d\n", cp->dev->name, hlen);
2008                         }
2009                         dev_kfree_skb_irq(skb);
2010                         return -1;
2011                 }
2012                 i = hlen;
2013                 if (i == dlen)  /* attach FCS */
2014                         i += cp->crc_size;
2015                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2016                                     PCI_DMA_FROMDEVICE);
2017
2018                 /* make sure we always copy a header */
2019                 swivel = 0;
2020                 if (p == (char *) skb->data) { /* not split */
2021                         addr = cas_page_map(page->buffer);
2022                         memcpy(p, addr + off, RX_COPY_MIN);
2023                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2024                                         PCI_DMA_FROMDEVICE);
2025                         cas_page_unmap(addr);
2026                         off += RX_COPY_MIN;
2027                         swivel = RX_COPY_MIN;
2028                         RX_USED_ADD(page, cp->mtu_stride);
2029                 } else {
2030                         RX_USED_ADD(page, hlen);
2031                 }
2032                 skb_put(skb, alloclen);
2033
2034                 skb_shinfo(skb)->nr_frags++;
2035                 skb->data_len += hlen - swivel;
2036                 skb->truesize += hlen - swivel;
2037                 skb->len      += hlen - swivel;
2038
2039                 get_page(page->buffer);
2040                 frag->page = page->buffer;
2041                 frag->page_offset = off;
2042                 frag->size = hlen - swivel;
2043
2044                 /* any more data? */
2045                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2046                         hlen = dlen;
2047                         off = 0;
2048
2049                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2050                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2051                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2052                                             hlen + cp->crc_size,
2053                                             PCI_DMA_FROMDEVICE);
2054                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2055                                             hlen + cp->crc_size,
2056                                             PCI_DMA_FROMDEVICE);
2057
2058                         skb_shinfo(skb)->nr_frags++;
2059                         skb->data_len += hlen;
2060                         skb->len      += hlen;
2061                         frag++;
2062
2063                         get_page(page->buffer);
2064                         frag->page = page->buffer;
2065                         frag->page_offset = 0;
2066                         frag->size = hlen;
2067                         RX_USED_ADD(page, hlen + cp->crc_size);
2068                 }
2069
2070                 if (cp->crc_size) {
2071                         addr = cas_page_map(page->buffer);
2072                         crcaddr  = addr + off + hlen;
2073                 }
2074
2075         } else {
2076                 /* copying packet */
2077                 if (!dlen)
2078                         goto end_copy_pkt;
2079
2080                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2081                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2082                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2083                 hlen = min(cp->page_size - off, dlen);
2084                 if (hlen < 0) {
2085                         if (netif_msg_rx_err(cp)) {
2086                                 printk(KERN_DEBUG "%s: rx page overflow: "
2087                                        "%d\n", cp->dev->name, hlen);
2088                         }
2089                         dev_kfree_skb_irq(skb);
2090                         return -1;
2091                 }
2092                 i = hlen;
2093                 if (i == dlen) /* attach FCS */
2094                         i += cp->crc_size;
2095                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2096                                     PCI_DMA_FROMDEVICE);
2097                 addr = cas_page_map(page->buffer);
2098                 memcpy(p, addr + off, i);
2099                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2100                                     PCI_DMA_FROMDEVICE);
2101                 cas_page_unmap(addr);
2102                 if (p == (char *) skb->data) /* not split */
2103                         RX_USED_ADD(page, cp->mtu_stride);
2104                 else
2105                         RX_USED_ADD(page, i);
2106
2107                 /* any more data? */
2108                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2109                         p += hlen;
2110                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2111                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2112                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2113                                             dlen + cp->crc_size,
2114                                             PCI_DMA_FROMDEVICE);
2115                         addr = cas_page_map(page->buffer);
2116                         memcpy(p, addr, dlen + cp->crc_size);
2117                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2118                                             dlen + cp->crc_size,
2119                                             PCI_DMA_FROMDEVICE);
2120                         cas_page_unmap(addr);
2121                         RX_USED_ADD(page, dlen + cp->crc_size);
2122                 }
2123 end_copy_pkt:
2124                 if (cp->crc_size) {
2125                         addr    = NULL;
2126                         crcaddr = skb->data + alloclen;
2127                 }
2128                 skb_put(skb, alloclen);
2129         }
2130
2131         csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2132         if (cp->crc_size) {
2133                 /* checksum includes FCS. strip it out. */
2134                 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2135                                               csum_unfold(csum)));
2136                 if (addr)
2137                         cas_page_unmap(addr);
2138         }
2139         skb->csum = csum_unfold(~csum);
2140         skb->ip_summed = CHECKSUM_COMPLETE;
2141         skb->protocol = eth_type_trans(skb, cp->dev);
2142         return len;
2143 }
2144
2145
2146 /* we can handle up to 64 rx flows at a time. we do the same thing
2147  * as nonreassm except that we batch up the buffers.
2148  * NOTE: we currently just treat each flow as a bunch of packets that
2149  *       we pass up. a better way would be to coalesce the packets
2150  *       into a jumbo packet. to do that, we need to do the following:
2151  *       1) the first packet will have a clean split between header and
2152  *          data. save both.
2153  *       2) each time the next flow packet comes in, extend the
2154  *          data length and merge the checksums.
2155  *       3) on flow release, fix up the header.
2156  *       4) make sure the higher layer doesn't care.
2157  * because packets get coalesced, we shouldn't run into fragment count
2158  * issues.
2159  */
2160 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2161                                    struct sk_buff *skb)
2162 {
2163         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2164         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2165
2166         /* this is protected at a higher layer, so no need to
2167          * do any additional locking here. stick the buffer
2168          * at the end.
2169          */
2170         __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2171         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2172                 while ((skb = __skb_dequeue(flow))) {
2173                         cas_skb_release(skb);
2174                 }
2175         }
2176 }
2177
2178 /* put rx descriptor back on ring. if a buffer is in use by a higher
2179  * layer, this will need to put in a replacement.
2180  */
2181 static void cas_post_page(struct cas *cp, const int ring, const int index)
2182 {
2183         cas_page_t *new;
2184         int entry;
2185
2186         entry = cp->rx_old[ring];
2187
2188         new = cas_page_swap(cp, ring, index);
2189         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2190         cp->init_rxds[ring][entry].index  =
2191                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2192                             CAS_BASE(RX_INDEX_RING, ring));
2193
2194         entry = RX_DESC_ENTRY(ring, entry + 1);
2195         cp->rx_old[ring] = entry;
2196
2197         if (entry % 4)
2198                 return;
2199
2200         if (ring == 0)
2201                 writel(entry, cp->regs + REG_RX_KICK);
2202         else if ((N_RX_DESC_RINGS > 1) &&
2203                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2204                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2205 }
2206
2207
2208 /* only when things are bad */
2209 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2210 {
2211         unsigned int entry, last, count, released;
2212         int cluster;
2213         cas_page_t **page = cp->rx_pages[ring];
2214
2215         entry = cp->rx_old[ring];
2216
2217         if (netif_msg_intr(cp))
2218                 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2219                        cp->dev->name, ring, entry);
2220
2221         cluster = -1;
2222         count = entry & 0x3;
2223         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2224         released = 0;
2225         while (entry != last) {
2226                 /* make a new buffer if it's still in use */
2227                 if (page_count(page[entry]->buffer) > 1) {
2228                         cas_page_t *new = cas_page_dequeue(cp);
2229                         if (!new) {
2230                                 /* let the timer know that we need to
2231                                  * do this again
2232                                  */
2233                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2234                                 if (!timer_pending(&cp->link_timer))
2235                                         mod_timer(&cp->link_timer, jiffies +
2236                                                   CAS_LINK_FAST_TIMEOUT);
2237                                 cp->rx_old[ring]  = entry;
2238                                 cp->rx_last[ring] = num ? num - released : 0;
2239                                 return -ENOMEM;
2240                         }
2241                         spin_lock(&cp->rx_inuse_lock);
2242                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2243                         spin_unlock(&cp->rx_inuse_lock);
2244                         cp->init_rxds[ring][entry].buffer =
2245                                 cpu_to_le64(new->dma_addr);
2246                         page[entry] = new;
2247
2248                 }
2249
2250                 if (++count == 4) {
2251                         cluster = entry;
2252                         count = 0;
2253                 }
2254                 released++;
2255                 entry = RX_DESC_ENTRY(ring, entry + 1);
2256         }
2257         cp->rx_old[ring] = entry;
2258
2259         if (cluster < 0)
2260                 return 0;
2261
2262         if (ring == 0)
2263                 writel(cluster, cp->regs + REG_RX_KICK);
2264         else if ((N_RX_DESC_RINGS > 1) &&
2265                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2266                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2267         return 0;
2268 }
2269
2270
2271 /* process a completion ring. packets are set up in three basic ways:
2272  * small packets: should be copied header + data in single buffer.
2273  * large packets: header and data in a single buffer.
2274  * split packets: header in a separate buffer from data.
2275  *                data may be in multiple pages. data may be > 256
2276  *                bytes but in a single page.
2277  *
2278  * NOTE: RX page posting is done in this routine as well. while there's
2279  *       the capability of using multiple RX completion rings, it isn't
2280  *       really worthwhile due to the fact that the page posting will
2281  *       force serialization on the single descriptor ring.
2282  */
2283 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2284 {
2285         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2286         int entry, drops;
2287         int npackets = 0;
2288
2289         if (netif_msg_intr(cp))
2290                 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2291                        cp->dev->name, ring,
2292                        readl(cp->regs + REG_RX_COMP_HEAD),
2293                        cp->rx_new[ring]);
2294
2295         entry = cp->rx_new[ring];
2296         drops = 0;
2297         while (1) {
2298                 struct cas_rx_comp *rxc = rxcs + entry;
2299                 struct sk_buff *skb;
2300                 int type, len;
2301                 u64 words[4];
2302                 int i, dring;
2303
2304                 words[0] = le64_to_cpu(rxc->word1);
2305                 words[1] = le64_to_cpu(rxc->word2);
2306                 words[2] = le64_to_cpu(rxc->word3);
2307                 words[3] = le64_to_cpu(rxc->word4);
2308
2309                 /* don't touch if still owned by hw */
2310                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2311                 if (type == 0)
2312                         break;
2313
2314                 /* hw hasn't cleared the zero bit yet */
2315                 if (words[3] & RX_COMP4_ZERO) {
2316                         break;
2317                 }
2318
2319                 /* get info on the packet */
2320                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2321                         spin_lock(&cp->stat_lock[ring]);
2322                         cp->net_stats[ring].rx_errors++;
2323                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2324                                 cp->net_stats[ring].rx_length_errors++;
2325                         if (words[3] & RX_COMP4_BAD)
2326                                 cp->net_stats[ring].rx_crc_errors++;
2327                         spin_unlock(&cp->stat_lock[ring]);
2328
2329                         /* We'll just return it to Cassini. */
2330                 drop_it:
2331                         spin_lock(&cp->stat_lock[ring]);
2332                         ++cp->net_stats[ring].rx_dropped;
2333                         spin_unlock(&cp->stat_lock[ring]);
2334                         goto next;
2335                 }
2336
2337                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2338                 if (len < 0) {
2339                         ++drops;
2340                         goto drop_it;
2341                 }
2342
2343                 /* see if it's a flow re-assembly or not. the driver
2344                  * itself handles release back up.
2345                  */
2346                 if (RX_DONT_BATCH || (type == 0x2)) {
2347                         /* non-reassm: these always get released */
2348                         cas_skb_release(skb);
2349                 } else {
2350                         cas_rx_flow_pkt(cp, words, skb);
2351                 }
2352
2353                 spin_lock(&cp->stat_lock[ring]);
2354                 cp->net_stats[ring].rx_packets++;
2355                 cp->net_stats[ring].rx_bytes += len;
2356                 spin_unlock(&cp->stat_lock[ring]);
2357                 cp->dev->last_rx = jiffies;
2358
2359         next:
2360                 npackets++;
2361
2362                 /* should it be released? */
2363                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2364                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2365                         dring = CAS_VAL(RX_INDEX_RING, i);
2366                         i = CAS_VAL(RX_INDEX_NUM, i);
2367                         cas_post_page(cp, dring, i);
2368                 }
2369
2370                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2371                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2372                         dring = CAS_VAL(RX_INDEX_RING, i);
2373                         i = CAS_VAL(RX_INDEX_NUM, i);
2374                         cas_post_page(cp, dring, i);
2375                 }
2376
2377                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2378                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2379                         dring = CAS_VAL(RX_INDEX_RING, i);
2380                         i = CAS_VAL(RX_INDEX_NUM, i);
2381                         cas_post_page(cp, dring, i);
2382                 }
2383
2384                 /* skip to the next entry */
2385                 entry = RX_COMP_ENTRY(ring, entry + 1 +
2386                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2387 #ifdef USE_NAPI
2388                 if (budget && (npackets >= budget))
2389                         break;
2390 #endif
2391         }
2392         cp->rx_new[ring] = entry;
2393
2394         if (drops)
2395                 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2396                        cp->dev->name);
2397         return npackets;
2398 }
2399
2400
2401 /* put completion entries back on the ring */
2402 static void cas_post_rxcs_ringN(struct net_device *dev,
2403                                 struct cas *cp, int ring)
2404 {
2405         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2406         int last, entry;
2407
2408         last = cp->rx_cur[ring];
2409         entry = cp->rx_new[ring];
2410         if (netif_msg_intr(cp))
2411                 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2412                        dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2413                        entry);
2414
2415         /* zero and re-mark descriptors */
2416         while (last != entry) {
2417                 cas_rxc_init(rxc + last);
2418                 last = RX_COMP_ENTRY(ring, last + 1);
2419         }
2420         cp->rx_cur[ring] = last;
2421
2422         if (ring == 0)
2423                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2424         else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2425                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2426 }
2427
2428
2429
2430 /* cassini can use all four PCI interrupts for the completion ring.
2431  * rings 3 and 4 are identical
2432  */
2433 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2434 static inline void cas_handle_irqN(struct net_device *dev,
2435                                    struct cas *cp, const u32 status,
2436                                    const int ring)
2437 {
2438         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2439                 cas_post_rxcs_ringN(dev, cp, ring);
2440 }
2441
2442 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2443 {
2444         struct net_device *dev = dev_id;
2445         struct cas *cp = netdev_priv(dev);
2446         unsigned long flags;
2447         int ring;
2448         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2449
2450         /* check for shared irq */
2451         if (status == 0)
2452                 return IRQ_NONE;
2453
2454         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2455         spin_lock_irqsave(&cp->lock, flags);
2456         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2457 #ifdef USE_NAPI
2458                 cas_mask_intr(cp);
2459                 netif_rx_schedule(dev, &cp->napi);
2460 #else
2461                 cas_rx_ringN(cp, ring, 0);
2462 #endif
2463                 status &= ~INTR_RX_DONE_ALT;
2464         }
2465
2466         if (status)
2467                 cas_handle_irqN(dev, cp, status, ring);
2468         spin_unlock_irqrestore(&cp->lock, flags);
2469         return IRQ_HANDLED;
2470 }
2471 #endif
2472
2473 #ifdef USE_PCI_INTB
2474 /* everything but rx packets */
2475 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2476 {
2477         if (status & INTR_RX_BUF_UNAVAIL_1) {
2478                 /* Frame arrived, no free RX buffers available.
2479                  * NOTE: we can get this on a link transition. */
2480                 cas_post_rxds_ringN(cp, 1, 0);
2481                 spin_lock(&cp->stat_lock[1]);
2482                 cp->net_stats[1].rx_dropped++;
2483                 spin_unlock(&cp->stat_lock[1]);
2484         }
2485
2486         if (status & INTR_RX_BUF_AE_1)
2487                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2488                                     RX_AE_FREEN_VAL(1));
2489
2490         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2491                 cas_post_rxcs_ringN(cp, 1);
2492 }
2493
2494 /* ring 2 handles a few more events than 3 and 4 */
2495 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2496 {
2497         struct net_device *dev = dev_id;
2498         struct cas *cp = netdev_priv(dev);
2499         unsigned long flags;
2500         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2501
2502         /* check for shared interrupt */
2503         if (status == 0)
2504                 return IRQ_NONE;
2505
2506         spin_lock_irqsave(&cp->lock, flags);
2507         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2508 #ifdef USE_NAPI
2509                 cas_mask_intr(cp);
2510                 netif_rx_schedule(dev, &cp->napi);
2511 #else
2512                 cas_rx_ringN(cp, 1, 0);
2513 #endif
2514                 status &= ~INTR_RX_DONE_ALT;
2515         }
2516         if (status)
2517                 cas_handle_irq1(cp, status);
2518         spin_unlock_irqrestore(&cp->lock, flags);
2519         return IRQ_HANDLED;
2520 }
2521 #endif
2522
2523 static inline void cas_handle_irq(struct net_device *dev,
2524                                   struct cas *cp, const u32 status)
2525 {
2526         /* housekeeping interrupts */
2527         if (status & INTR_ERROR_MASK)
2528                 cas_abnormal_irq(dev, cp, status);
2529
2530         if (status & INTR_RX_BUF_UNAVAIL) {
2531                 /* Frame arrived, no free RX buffers available.
2532                  * NOTE: we can get this on a link transition.
2533                  */
2534                 cas_post_rxds_ringN(cp, 0, 0);
2535                 spin_lock(&cp->stat_lock[0]);
2536                 cp->net_stats[0].rx_dropped++;
2537                 spin_unlock(&cp->stat_lock[0]);
2538         } else if (status & INTR_RX_BUF_AE) {
2539                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2540                                     RX_AE_FREEN_VAL(0));
2541         }
2542
2543         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2544                 cas_post_rxcs_ringN(dev, cp, 0);
2545 }
2546
2547 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2548 {
2549         struct net_device *dev = dev_id;
2550         struct cas *cp = netdev_priv(dev);
2551         unsigned long flags;
2552         u32 status = readl(cp->regs + REG_INTR_STATUS);
2553
2554         if (status == 0)
2555                 return IRQ_NONE;
2556
2557         spin_lock_irqsave(&cp->lock, flags);
2558         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2559                 cas_tx(dev, cp, status);
2560                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2561         }
2562
2563         if (status & INTR_RX_DONE) {
2564 #ifdef USE_NAPI
2565                 cas_mask_intr(cp);
2566                 netif_rx_schedule(dev, &cp->napi);
2567 #else
2568                 cas_rx_ringN(cp, 0, 0);
2569 #endif
2570                 status &= ~INTR_RX_DONE;
2571         }
2572
2573         if (status)
2574                 cas_handle_irq(dev, cp, status);
2575         spin_unlock_irqrestore(&cp->lock, flags);
2576         return IRQ_HANDLED;
2577 }
2578
2579
2580 #ifdef USE_NAPI
2581 static int cas_poll(struct napi_struct *napi, int budget)
2582 {
2583         struct cas *cp = container_of(napi, struct cas, napi);
2584         struct net_device *dev = cp->dev;
2585         int i, enable_intr, credits;
2586         u32 status = readl(cp->regs + REG_INTR_STATUS);
2587         unsigned long flags;
2588
2589         spin_lock_irqsave(&cp->lock, flags);
2590         cas_tx(dev, cp, status);
2591         spin_unlock_irqrestore(&cp->lock, flags);
2592
2593         /* NAPI rx packets. we spread the credits across all of the
2594          * rxc rings
2595          *
2596          * to make sure we're fair with the work we loop through each
2597          * ring N_RX_COMP_RING times with a request of
2598          * budget / N_RX_COMP_RINGS
2599          */
2600         enable_intr = 1;
2601         credits = 0;
2602         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2603                 int j;
2604                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2605                         credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2606                         if (credits >= budget) {
2607                                 enable_intr = 0;
2608                                 goto rx_comp;
2609                         }
2610                 }
2611         }
2612
2613 rx_comp:
2614         /* final rx completion */
2615         spin_lock_irqsave(&cp->lock, flags);
2616         if (status)
2617                 cas_handle_irq(dev, cp, status);
2618
2619 #ifdef USE_PCI_INTB
2620         if (N_RX_COMP_RINGS > 1) {
2621                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2622                 if (status)
2623                         cas_handle_irq1(dev, cp, status);
2624         }
2625 #endif
2626
2627 #ifdef USE_PCI_INTC
2628         if (N_RX_COMP_RINGS > 2) {
2629                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2630                 if (status)
2631                         cas_handle_irqN(dev, cp, status, 2);
2632         }
2633 #endif
2634
2635 #ifdef USE_PCI_INTD
2636         if (N_RX_COMP_RINGS > 3) {
2637                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2638                 if (status)
2639                         cas_handle_irqN(dev, cp, status, 3);
2640         }
2641 #endif
2642         spin_unlock_irqrestore(&cp->lock, flags);
2643         if (enable_intr) {
2644                 netif_rx_complete(dev, napi);
2645                 cas_unmask_intr(cp);
2646         }
2647         return credits;
2648 }
2649 #endif
2650
2651 #ifdef CONFIG_NET_POLL_CONTROLLER
2652 static void cas_netpoll(struct net_device *dev)
2653 {
2654         struct cas *cp = netdev_priv(dev);
2655
2656         cas_disable_irq(cp, 0);
2657         cas_interrupt(cp->pdev->irq, dev);
2658         cas_enable_irq(cp, 0);
2659
2660 #ifdef USE_PCI_INTB
2661         if (N_RX_COMP_RINGS > 1) {
2662                 /* cas_interrupt1(); */
2663         }
2664 #endif
2665 #ifdef USE_PCI_INTC
2666         if (N_RX_COMP_RINGS > 2) {
2667                 /* cas_interruptN(); */
2668         }
2669 #endif
2670 #ifdef USE_PCI_INTD
2671         if (N_RX_COMP_RINGS > 3) {
2672                 /* cas_interruptN(); */
2673         }
2674 #endif
2675 }
2676 #endif
2677
2678 static void cas_tx_timeout(struct net_device *dev)
2679 {
2680         struct cas *cp = netdev_priv(dev);
2681
2682         printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2683         if (!cp->hw_running) {
2684                 printk("%s: hrm.. hw not running!\n", dev->name);
2685                 return;
2686         }
2687
2688         printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2689                dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2690
2691         printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2692                dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2693
2694         printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2695                "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2696                dev->name,
2697                readl(cp->regs + REG_TX_CFG),
2698                readl(cp->regs + REG_MAC_TX_STATUS),
2699                readl(cp->regs + REG_MAC_TX_CFG),
2700                readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2701                readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2702                readl(cp->regs + REG_TX_FIFO_READ_PTR),
2703                readl(cp->regs + REG_TX_SM_1),
2704                readl(cp->regs + REG_TX_SM_2));
2705
2706         printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2707                dev->name,
2708                readl(cp->regs + REG_RX_CFG),
2709                readl(cp->regs + REG_MAC_RX_STATUS),
2710                readl(cp->regs + REG_MAC_RX_CFG));
2711
2712         printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2713                dev->name,
2714                readl(cp->regs + REG_HP_STATE_MACHINE),
2715                readl(cp->regs + REG_HP_STATUS0),
2716                readl(cp->regs + REG_HP_STATUS1),
2717                readl(cp->regs + REG_HP_STATUS2));
2718
2719 #if 1
2720         atomic_inc(&cp->reset_task_pending);
2721         atomic_inc(&cp->reset_task_pending_all);
2722         schedule_work(&cp->reset_task);
2723 #else
2724         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2725         schedule_work(&cp->reset_task);
2726 #endif
2727 }
2728
2729 static inline int cas_intme(int ring, int entry)
2730 {
2731         /* Algorithm: IRQ every 1/2 of descriptors. */
2732         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2733                 return 1;
2734         return 0;
2735 }
2736
2737
2738 static void cas_write_txd(struct cas *cp, int ring, int entry,
2739                           dma_addr_t mapping, int len, u64 ctrl, int last)
2740 {
2741         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2742
2743         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2744         if (cas_intme(ring, entry))
2745                 ctrl |= TX_DESC_INTME;
2746         if (last)
2747                 ctrl |= TX_DESC_EOF;
2748         txd->control = cpu_to_le64(ctrl);
2749         txd->buffer = cpu_to_le64(mapping);
2750 }
2751
2752 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2753                                 const int entry)
2754 {
2755         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2756 }
2757
2758 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2759                                      const int entry, const int tentry)
2760 {
2761         cp->tx_tiny_use[ring][tentry].nbufs++;
2762         cp->tx_tiny_use[ring][entry].used = 1;
2763         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2764 }
2765
2766 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2767                                     struct sk_buff *skb)
2768 {
2769         struct net_device *dev = cp->dev;
2770         int entry, nr_frags, frag, tabort, tentry;
2771         dma_addr_t mapping;
2772         unsigned long flags;
2773         u64 ctrl;
2774         u32 len;
2775
2776         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2777
2778         /* This is a hard error, log it. */
2779         if (TX_BUFFS_AVAIL(cp, ring) <=
2780             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2781                 netif_stop_queue(dev);
2782                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2783                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2784                        "queue awake!\n", dev->name);
2785                 return 1;
2786         }
2787
2788         ctrl = 0;
2789         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2790                 const u64 csum_start_off = skb_transport_offset(skb);
2791                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2792
2793                 ctrl =  TX_DESC_CSUM_EN |
2794                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2795                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2796         }
2797
2798         entry = cp->tx_new[ring];
2799         cp->tx_skbs[ring][entry] = skb;
2800
2801         nr_frags = skb_shinfo(skb)->nr_frags;
2802         len = skb_headlen(skb);
2803         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2804                                offset_in_page(skb->data), len,
2805                                PCI_DMA_TODEVICE);
2806
2807         tentry = entry;
2808         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2809         if (unlikely(tabort)) {
2810                 /* NOTE: len is always >  tabort */
2811                 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2812                               ctrl | TX_DESC_SOF, 0);
2813                 entry = TX_DESC_NEXT(ring, entry);
2814
2815                 skb_copy_from_linear_data_offset(skb, len - tabort,
2816                               tx_tiny_buf(cp, ring, entry), tabort);
2817                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2818                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2819                               (nr_frags == 0));
2820         } else {
2821                 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2822                               TX_DESC_SOF, (nr_frags == 0));
2823         }
2824         entry = TX_DESC_NEXT(ring, entry);
2825
2826         for (frag = 0; frag < nr_frags; frag++) {
2827                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2828
2829                 len = fragp->size;
2830                 mapping = pci_map_page(cp->pdev, fragp->page,
2831                                        fragp->page_offset, len,
2832                                        PCI_DMA_TODEVICE);
2833
2834                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2835                 if (unlikely(tabort)) {
2836                         void *addr;
2837
2838                         /* NOTE: len is always > tabort */
2839                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2840                                       ctrl, 0);
2841                         entry = TX_DESC_NEXT(ring, entry);
2842
2843                         addr = cas_page_map(fragp->page);
2844                         memcpy(tx_tiny_buf(cp, ring, entry),
2845                                addr + fragp->page_offset + len - tabort,
2846                                tabort);
2847                         cas_page_unmap(addr);
2848                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2849                         len     = tabort;
2850                 }
2851
2852                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2853                               (frag + 1 == nr_frags));
2854                 entry = TX_DESC_NEXT(ring, entry);
2855         }
2856
2857         cp->tx_new[ring] = entry;
2858         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2859                 netif_stop_queue(dev);
2860
2861         if (netif_msg_tx_queued(cp))
2862                 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2863                        "avail %d\n",
2864                        dev->name, ring, entry, skb->len,
2865                        TX_BUFFS_AVAIL(cp, ring));
2866         writel(entry, cp->regs + REG_TX_KICKN(ring));
2867         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2868         return 0;
2869 }
2870
2871 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2872 {
2873         struct cas *cp = netdev_priv(dev);
2874
2875         /* this is only used as a load-balancing hint, so it doesn't
2876          * need to be SMP safe
2877          */
2878         static int ring;
2879
2880         if (skb_padto(skb, cp->min_frame_size))
2881                 return 0;
2882
2883         /* XXX: we need some higher-level QoS hooks to steer packets to
2884          *      individual queues.
2885          */
2886         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2887                 return 1;
2888         dev->trans_start = jiffies;
2889         return 0;
2890 }
2891
2892 static void cas_init_tx_dma(struct cas *cp)
2893 {
2894         u64 desc_dma = cp->block_dvma;
2895         unsigned long off;
2896         u32 val;
2897         int i;
2898
2899         /* set up tx completion writeback registers. must be 8-byte aligned */
2900 #ifdef USE_TX_COMPWB
2901         off = offsetof(struct cas_init_block, tx_compwb);
2902         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2903         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2904 #endif
2905
2906         /* enable completion writebacks, enable paced mode,
2907          * disable read pipe, and disable pre-interrupt compwbs
2908          */
2909         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2910                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2911                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2912                 TX_CFG_INTR_COMPWB_DIS;
2913
2914         /* write out tx ring info and tx desc bases */
2915         for (i = 0; i < MAX_TX_RINGS; i++) {
2916                 off = (unsigned long) cp->init_txds[i] -
2917                         (unsigned long) cp->init_block;
2918
2919                 val |= CAS_TX_RINGN_BASE(i);
2920                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2921                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2922                        REG_TX_DBN_LOW(i));
2923                 /* don't zero out the kick register here as the system
2924                  * will wedge
2925                  */
2926         }
2927         writel(val, cp->regs + REG_TX_CFG);
2928
2929         /* program max burst sizes. these numbers should be different
2930          * if doing QoS.
2931          */
2932 #ifdef USE_QOS
2933         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2934         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2935         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2936         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2937 #else
2938         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2939         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2940         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2941         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2942 #endif
2943 }
2944
2945 /* Must be invoked under cp->lock. */
2946 static inline void cas_init_dma(struct cas *cp)
2947 {
2948         cas_init_tx_dma(cp);
2949         cas_init_rx_dma(cp);
2950 }
2951
2952 /* Must be invoked under cp->lock. */
2953 static u32 cas_setup_multicast(struct cas *cp)
2954 {
2955         u32 rxcfg = 0;
2956         int i;
2957
2958         if (cp->dev->flags & IFF_PROMISC) {
2959                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2960
2961         } else if (cp->dev->flags & IFF_ALLMULTI) {
2962                 for (i=0; i < 16; i++)
2963                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2964                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2965
2966         } else {
2967                 u16 hash_table[16];
2968                 u32 crc;
2969                 struct dev_mc_list *dmi = cp->dev->mc_list;
2970                 int i;
2971
2972                 /* use the alternate mac address registers for the
2973                  * first 15 multicast addresses
2974                  */
2975                 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
2976                         if (!dmi) {
2977                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
2978                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
2979                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
2980                                 continue;
2981                         }
2982                         writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
2983                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
2984                         writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
2985                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
2986                         writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
2987                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
2988                         dmi = dmi->next;
2989                 }
2990
2991                 /* use hw hash table for the next series of
2992                  * multicast addresses
2993                  */
2994                 memset(hash_table, 0, sizeof(hash_table));
2995                 while (dmi) {
2996                         crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
2997                         crc >>= 24;
2998                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2999                         dmi = dmi->next;
3000                 }
3001                 for (i=0; i < 16; i++)
3002                         writel(hash_table[i], cp->regs +
3003                                REG_MAC_HASH_TABLEN(i));
3004                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3005         }
3006
3007         return rxcfg;
3008 }
3009
3010 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3011 static void cas_clear_mac_err(struct cas *cp)
3012 {
3013         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3014         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3015         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3016         writel(0, cp->regs + REG_MAC_COLL_LATE);
3017         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3018         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3019         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3020         writel(0, cp->regs + REG_MAC_LEN_ERR);
3021         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3022         writel(0, cp->regs + REG_MAC_FCS_ERR);
3023         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3024 }
3025
3026
3027 static void cas_mac_reset(struct cas *cp)
3028 {
3029         int i;
3030
3031         /* do both TX and RX reset */
3032         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3033         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3034
3035         /* wait for TX */
3036         i = STOP_TRIES;
3037         while (i-- > 0) {
3038                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3039                         break;
3040                 udelay(10);
3041         }
3042
3043         /* wait for RX */
3044         i = STOP_TRIES;
3045         while (i-- > 0) {
3046                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3047                         break;
3048                 udelay(10);
3049         }
3050
3051         if (readl(cp->regs + REG_MAC_TX_RESET) |
3052             readl(cp->regs + REG_MAC_RX_RESET))
3053                 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3054                        cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3055                        readl(cp->regs + REG_MAC_RX_RESET),
3056                        readl(cp->regs + REG_MAC_STATE_MACHINE));
3057 }
3058
3059
3060 /* Must be invoked under cp->lock. */
3061 static void cas_init_mac(struct cas *cp)
3062 {
3063         unsigned char *e = &cp->dev->dev_addr[0];
3064         int i;
3065 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3066         u32 rxcfg;
3067 #endif
3068         cas_mac_reset(cp);
3069
3070         /* setup core arbitration weight register */
3071         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3072
3073         /* XXX Use pci_dma_burst_advice() */
3074 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3075         /* set the infinite burst register for chips that don't have
3076          * pci issues.
3077          */
3078         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3079                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3080 #endif
3081
3082         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3083
3084         writel(0x00, cp->regs + REG_MAC_IPG0);
3085         writel(0x08, cp->regs + REG_MAC_IPG1);
3086         writel(0x04, cp->regs + REG_MAC_IPG2);
3087
3088         /* change later for 802.3z */
3089         writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3090
3091         /* min frame + FCS */
3092         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3093
3094         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3095          * specify the maximum frame size to prevent RX tag errors on
3096          * oversized frames.
3097          */
3098         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3099                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3100                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3101                cp->regs + REG_MAC_FRAMESIZE_MAX);
3102
3103         /* NOTE: crc_size is used as a surrogate for half-duplex.
3104          * workaround saturn half-duplex issue by increasing preamble
3105          * size to 65 bytes.
3106          */
3107         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3108                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3109         else
3110                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3111         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3112         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3113         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3114
3115         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3116
3117         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3118         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3119         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3120         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3121         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3122
3123         /* setup mac address in perfect filter array */
3124         for (i = 0; i < 45; i++)
3125                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3126
3127         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3128         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3129         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3130
3131         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3132         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3133         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3134
3135 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3136         cp->mac_rx_cfg = cas_setup_multicast(cp);
3137 #else
3138         /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3139          * a writel does not seem to be necessary because Cassini
3140          * seems to preserve the configuration when we do the reset.
3141          * If the chip is in trouble, though, it is not clear if we
3142          * can really count on this behavior. cas_set_multicast uses
3143          * spin_lock_irqsave, but we are called only in cas_init_hw and
3144          * cas_init_hw is protected by cas_lock_all, which calls
3145          * spin_lock_irq (so it doesn't need to save the flags, and
3146          * we should be OK for the writel, as that is the only
3147          * difference).
3148          */
3149         cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3150         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3151 #endif
3152         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3153         cas_clear_mac_err(cp);
3154         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3155
3156         /* Setup MAC interrupts.  We want to get all of the interesting
3157          * counter expiration events, but we do not want to hear about
3158          * normal rx/tx as the DMA engine tells us that.
3159          */
3160         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3161         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3162
3163         /* Don't enable even the PAUSE interrupts for now, we
3164          * make no use of those events other than to record them.
3165          */
3166         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3167 }
3168
3169 /* Must be invoked under cp->lock. */
3170 static void cas_init_pause_thresholds(struct cas *cp)
3171 {
3172         /* Calculate pause thresholds.  Setting the OFF threshold to the
3173          * full RX fifo size effectively disables PAUSE generation
3174          */
3175         if (cp->rx_fifo_size <= (2 * 1024)) {
3176                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3177         } else {
3178                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3179                 if (max_frame * 3 > cp->rx_fifo_size) {
3180                         cp->rx_pause_off = 7104;
3181                         cp->rx_pause_on  = 960;
3182                 } else {
3183                         int off = (cp->rx_fifo_size - (max_frame * 2));
3184                         int on = off - max_frame;
3185                         cp->rx_pause_off = off;
3186                         cp->rx_pause_on = on;
3187                 }
3188         }
3189 }
3190
3191 static int cas_vpd_match(const void __iomem *p, const char *str)
3192 {
3193         int len = strlen(str) + 1;
3194         int i;
3195
3196         for (i = 0; i < len; i++) {
3197                 if (readb(p + i) != str[i])
3198                         return 0;
3199         }
3200         return 1;
3201 }
3202
3203
3204 /* get the mac address by reading the vpd information in the rom.
3205  * also get the phy type and determine if there's an entropy generator.
3206  * NOTE: this is a bit convoluted for the following reasons:
3207  *  1) vpd info has order-dependent mac addresses for multinic cards
3208  *  2) the only way to determine the nic order is to use the slot
3209  *     number.
3210  *  3) fiber cards don't have bridges, so their slot numbers don't
3211  *     mean anything.
3212  *  4) we don't actually know we have a fiber card until after
3213  *     the mac addresses are parsed.
3214  */
3215 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3216                             const int offset)
3217 {
3218         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3219         void __iomem *base, *kstart;
3220         int i, len;
3221         int found = 0;
3222 #define VPD_FOUND_MAC        0x01
3223 #define VPD_FOUND_PHY        0x02
3224
3225         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3226         int mac_off  = 0;
3227
3228         /* give us access to the PROM */
3229         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3230                cp->regs + REG_BIM_LOCAL_DEV_EN);
3231
3232         /* check for an expansion rom */
3233         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3234                 goto use_random_mac_addr;
3235
3236         /* search for beginning of vpd */
3237         base = NULL;
3238         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3239                 /* check for PCIR */
3240                 if ((readb(p + i + 0) == 0x50) &&
3241                     (readb(p + i + 1) == 0x43) &&
3242                     (readb(p + i + 2) == 0x49) &&
3243                     (readb(p + i + 3) == 0x52)) {
3244                         base = p + (readb(p + i + 8) |
3245                                     (readb(p + i + 9) << 8));
3246                         break;
3247                 }
3248         }
3249
3250         if (!base || (readb(base) != 0x82))
3251                 goto use_random_mac_addr;
3252
3253         i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3254         while (i < EXPANSION_ROM_SIZE) {
3255                 if (readb(base + i) != 0x90) /* no vpd found */
3256                         goto use_random_mac_addr;
3257
3258                 /* found a vpd field */
3259                 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3260
3261                 /* extract keywords */
3262                 kstart = base + i + 3;
3263                 p = kstart;
3264                 while ((p - kstart) < len) {
3265                         int klen = readb(p + 2);
3266                         int j;
3267                         char type;
3268
3269                         p += 3;
3270
3271                         /* look for the following things:
3272                          * -- correct length == 29
3273                          * 3 (type) + 2 (size) +
3274                          * 18 (strlen("local-mac-address") + 1) +
3275                          * 6 (mac addr)
3276                          * -- VPD Instance 'I'
3277                          * -- VPD Type Bytes 'B'
3278                          * -- VPD data length == 6
3279                          * -- property string == local-mac-address
3280                          *
3281                          * -- correct length == 24
3282                          * 3 (type) + 2 (size) +
3283                          * 12 (strlen("entropy-dev") + 1) +
3284                          * 7 (strlen("vms110") + 1)
3285                          * -- VPD Instance 'I'
3286                          * -- VPD Type String 'B'
3287                          * -- VPD data length == 7
3288                          * -- property string == entropy-dev
3289                          *
3290                          * -- correct length == 18
3291                          * 3 (type) + 2 (size) +
3292                          * 9 (strlen("phy-type") + 1) +
3293                          * 4 (strlen("pcs") + 1)
3294                          * -- VPD Instance 'I'
3295                          * -- VPD Type String 'S'
3296                          * -- VPD data length == 4
3297                          * -- property string == phy-type
3298                          *
3299                          * -- correct length == 23
3300                          * 3 (type) + 2 (size) +
3301                          * 14 (strlen("phy-interface") + 1) +
3302                          * 4 (strlen("pcs") + 1)
3303                          * -- VPD Instance 'I'
3304                          * -- VPD Type String 'S'
3305                          * -- VPD data length == 4
3306                          * -- property string == phy-interface
3307                          */
3308                         if (readb(p) != 'I')
3309                                 goto next;
3310
3311                         /* finally, check string and length */
3312                         type = readb(p + 3);
3313                         if (type == 'B') {
3314                                 if ((klen == 29) && readb(p + 4) == 6 &&
3315                                     cas_vpd_match(p + 5,
3316                                                   "local-mac-address")) {
3317                                         if (mac_off++ > offset)
3318                                                 goto next;
3319
3320                                         /* set mac address */
3321                                         for (j = 0; j < 6; j++)
3322                                                 dev_addr[j] =
3323                                                         readb(p + 23 + j);
3324                                         goto found_mac;
3325                                 }
3326                         }
3327
3328                         if (type != 'S')
3329                                 goto next;
3330
3331 #ifdef USE_ENTROPY_DEV
3332                         if ((klen == 24) &&
3333                             cas_vpd_match(p + 5, "entropy-dev") &&
3334                             cas_vpd_match(p + 17, "vms110")) {
3335                                 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3336                                 goto next;
3337                         }
3338 #endif
3339
3340                         if (found & VPD_FOUND_PHY)
3341                                 goto next;
3342
3343                         if ((klen == 18) && readb(p + 4) == 4 &&
3344                             cas_vpd_match(p + 5, "phy-type")) {
3345                                 if (cas_vpd_match(p + 14, "pcs")) {
3346                                         phy_type = CAS_PHY_SERDES;
3347                                         goto found_phy;
3348                                 }
3349                         }
3350
3351                         if ((klen == 23) && readb(p + 4) == 4 &&
3352                             cas_vpd_match(p + 5, "phy-interface")) {
3353                                 if (cas_vpd_match(p + 19, "pcs")) {
3354                                         phy_type = CAS_PHY_SERDES;
3355                                         goto found_phy;
3356                                 }
3357                         }
3358 found_mac:
3359                         found |= VPD_FOUND_MAC;
3360                         goto next;
3361
3362 found_phy:
3363                         found |= VPD_FOUND_PHY;
3364
3365 next:
3366                         p += klen;
3367                 }
3368                 i += len + 3;
3369         }
3370
3371 use_random_mac_addr:
3372         if (found & VPD_FOUND_MAC)
3373                 goto done;
3374
3375         /* Sun MAC prefix then 3 random bytes. */
3376         printk(PFX "MAC address not found in ROM VPD\n");
3377         dev_addr[0] = 0x08;
3378         dev_addr[1] = 0x00;
3379         dev_addr[2] = 0x20;
3380         get_random_bytes(dev_addr + 3, 3);
3381
3382 done:
3383         writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3384         return phy_type;
3385 }
3386
3387 /* check pci invariants */
3388 static void cas_check_pci_invariants(struct cas *cp)
3389 {
3390         struct pci_dev *pdev = cp->pdev;
3391
3392         cp->cas_flags = 0;
3393         if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3394             (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3395                 if (pdev->revision >= CAS_ID_REVPLUS)
3396                         cp->cas_flags |= CAS_FLAG_REG_PLUS;
3397                 if (pdev->revision < CAS_ID_REVPLUS02u)
3398                         cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3399
3400                 /* Original Cassini supports HW CSUM, but it's not
3401                  * enabled by default as it can trigger TX hangs.
3402                  */
3403                 if (pdev->revision < CAS_ID_REV2)
3404                         cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3405         } else {
3406                 /* Only sun has original cassini chips.  */
3407                 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3408
3409                 /* We use a flag because the same phy might be externally
3410                  * connected.
3411                  */
3412                 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3413                     (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3414                         cp->cas_flags |= CAS_FLAG_SATURN;
3415         }
3416 }
3417
3418
3419 static int cas_check_invariants(struct cas *cp)
3420 {
3421         struct pci_dev *pdev = cp->pdev;
3422         u32 cfg;
3423         int i;
3424
3425         /* get page size for rx buffers. */
3426         cp->page_order = 0;
3427 #ifdef USE_PAGE_ORDER
3428         if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3429                 /* see if we can allocate larger pages */
3430                 struct page *page = alloc_pages(GFP_ATOMIC,
3431                                                 CAS_JUMBO_PAGE_SHIFT -
3432                                                 PAGE_SHIFT);
3433                 if (page) {
3434                         __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3435                         cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3436                 } else {
3437                         printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3438                 }
3439         }
3440 #endif
3441         cp->page_size = (PAGE_SIZE << cp->page_order);
3442
3443         /* Fetch the FIFO configurations. */
3444         cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3445         cp->rx_fifo_size = RX_FIFO_SIZE;
3446
3447         /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3448          * they're both connected.
3449          */
3450         cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3451                                         PCI_SLOT(pdev->devfn));
3452         if (cp->phy_type & CAS_PHY_SERDES) {
3453                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3454                 return 0; /* no more checking needed */
3455         }
3456
3457         /* MII */
3458         cfg = readl(cp->regs + REG_MIF_CFG);
3459         if (cfg & MIF_CFG_MDIO_1) {
3460                 cp->phy_type = CAS_PHY_MII_MDIO1;
3461         } else if (cfg & MIF_CFG_MDIO_0) {
3462                 cp->phy_type = CAS_PHY_MII_MDIO0;
3463         }
3464
3465         cas_mif_poll(cp, 0);
3466         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3467
3468         for (i = 0; i < 32; i++) {
3469                 u32 phy_id;
3470                 int j;
3471
3472                 for (j = 0; j < 3; j++) {
3473                         cp->phy_addr = i;
3474                         phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3475                         phy_id |= cas_phy_read(cp, MII_PHYSID2);
3476                         if (phy_id && (phy_id != 0xFFFFFFFF)) {
3477                                 cp->phy_id = phy_id;
3478                                 goto done;
3479                         }
3480                 }
3481         }
3482         printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3483                readl(cp->regs + REG_MIF_STATE_MACHINE));
3484         return -1;
3485
3486 done:
3487         /* see if we can do gigabit */
3488         cfg = cas_phy_read(cp, MII_BMSR);
3489         if ((cfg & CAS_BMSR_1000_EXTEND) &&
3490             cas_phy_read(cp, CAS_MII_1000_EXTEND))
3491                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3492         return 0;
3493 }
3494
3495 /* Must be invoked under cp->lock. */
3496 static inline void cas_start_dma(struct cas *cp)
3497 {
3498         int i;
3499         u32 val;
3500         int txfailed = 0;
3501
3502         /* enable dma */
3503         val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3504         writel(val, cp->regs + REG_TX_CFG);
3505         val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3506         writel(val, cp->regs + REG_RX_CFG);
3507
3508         /* enable the mac */
3509         val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3510         writel(val, cp->regs + REG_MAC_TX_CFG);
3511         val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3512         writel(val, cp->regs + REG_MAC_RX_CFG);
3513
3514         i = STOP_TRIES;
3515         while (i-- > 0) {
3516                 val = readl(cp->regs + REG_MAC_TX_CFG);
3517                 if ((val & MAC_TX_CFG_EN))
3518                         break;
3519                 udelay(10);
3520         }
3521         if (i < 0) txfailed = 1;
3522         i = STOP_TRIES;
3523         while (i-- > 0) {
3524                 val = readl(cp->regs + REG_MAC_RX_CFG);
3525                 if ((val & MAC_RX_CFG_EN)) {
3526                         if (txfailed) {
3527                           printk(KERN_ERR
3528                                  "%s: enabling mac failed [tx:%08x:%08x].\n",
3529                                  cp->dev->name,
3530                                  readl(cp->regs + REG_MIF_STATE_MACHINE),
3531                                  readl(cp->regs + REG_MAC_STATE_MACHINE));
3532                         }
3533                         goto enable_rx_done;
3534                 }
3535                 udelay(10);
3536         }
3537         printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3538                cp->dev->name,
3539                (txfailed? "tx,rx":"rx"),
3540                readl(cp->regs + REG_MIF_STATE_MACHINE),
3541                readl(cp->regs + REG_MAC_STATE_MACHINE));
3542
3543 enable_rx_done:
3544         cas_unmask_intr(cp); /* enable interrupts */
3545         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3546         writel(0, cp->regs + REG_RX_COMP_TAIL);
3547
3548         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3549                 if (N_RX_DESC_RINGS > 1)
3550                         writel(RX_DESC_RINGN_SIZE(1) - 4,
3551                                cp->regs + REG_PLUS_RX_KICK1);
3552
3553                 for (i = 1; i < N_RX_COMP_RINGS; i++)
3554                         writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3555         }
3556 }
3557
3558 /* Must be invoked under cp->lock. */
3559 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3560                                    int *pause)
3561 {
3562         u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3563         *fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3564         *pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3565         if (val & PCS_MII_LPA_ASYM_PAUSE)
3566                 *pause |= 0x10;
3567         *spd = 1000;
3568 }
3569
3570 /* Must be invoked under cp->lock. */
3571 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3572                                    int *pause)
3573 {
3574         u32 val;
3575
3576         *fd = 0;
3577         *spd = 10;
3578         *pause = 0;
3579
3580         /* use GMII registers */
3581         val = cas_phy_read(cp, MII_LPA);
3582         if (val & CAS_LPA_PAUSE)
3583                 *pause = 0x01;
3584
3585         if (val & CAS_LPA_ASYM_PAUSE)
3586                 *pause |= 0x10;
3587
3588         if (val & LPA_DUPLEX)
3589                 *fd = 1;
3590         if (val & LPA_100)
3591                 *spd = 100;
3592
3593         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3594                 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3595                 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3596                         *spd = 1000;
3597                 if (val & CAS_LPA_1000FULL)
3598                         *fd = 1;
3599         }
3600 }
3601
3602 /* A link-up condition has occurred, initialize and enable the
3603  * rest of the chip.
3604  *
3605  * Must be invoked under cp->lock.
3606  */
3607 static void cas_set_link_modes(struct cas *cp)
3608 {
3609         u32 val;
3610         int full_duplex, speed, pause;
3611
3612         full_duplex = 0;
3613         speed = 10;
3614         pause = 0;
3615
3616         if (CAS_PHY_MII(cp->phy_type)) {
3617                 cas_mif_poll(cp, 0);
3618                 val = cas_phy_read(cp, MII_BMCR);
3619                 if (val & BMCR_ANENABLE) {
3620                         cas_read_mii_link_mode(cp, &full_duplex, &speed,
3621                                                &pause);
3622                 } else {
3623                         if (val & BMCR_FULLDPLX)
3624                                 full_duplex = 1;
3625
3626                         if (val & BMCR_SPEED100)
3627                                 speed = 100;
3628                         else if (val & CAS_BMCR_SPEED1000)
3629                                 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3630                                         1000 : 100;
3631                 }
3632                 cas_mif_poll(cp, 1);
3633
3634         } else {
3635                 val = readl(cp->regs + REG_PCS_MII_CTRL);
3636                 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3637                 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3638                         if (val & PCS_MII_CTRL_DUPLEX)
3639                                 full_duplex = 1;
3640                 }
3641         }
3642
3643         if (netif_msg_link(cp))
3644                 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3645                        cp->dev->name, speed, (full_duplex ? "full" : "half"));
3646
3647         val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3648         if (CAS_PHY_MII(cp->phy_type)) {
3649                 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3650                 if (!full_duplex)
3651                         val |= MAC_XIF_DISABLE_ECHO;
3652         }
3653         if (full_duplex)
3654                 val |= MAC_XIF_FDPLX_LED;
3655         if (speed == 1000)
3656                 val |= MAC_XIF_GMII_MODE;
3657         writel(val, cp->regs + REG_MAC_XIF_CFG);
3658
3659         /* deal with carrier and collision detect. */
3660         val = MAC_TX_CFG_IPG_EN;
3661         if (full_duplex) {
3662                 val |= MAC_TX_CFG_IGNORE_CARRIER;
3663                 val |= MAC_TX_CFG_IGNORE_COLL;
3664         } else {
3665 #ifndef USE_CSMA_CD_PROTO
3666                 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3667                 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3668 #endif
3669         }
3670         /* val now set up for REG_MAC_TX_CFG */
3671
3672         /* If gigabit and half-duplex, enable carrier extension
3673          * mode.  increase slot time to 512 bytes as well.
3674          * else, disable it and make sure slot time is 64 bytes.
3675          * also activate checksum bug workaround
3676          */
3677         if ((speed == 1000) && !full_duplex) {
3678                 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3679                        cp->regs + REG_MAC_TX_CFG);
3680
3681                 val = readl(cp->regs + REG_MAC_RX_CFG);
3682                 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3683                 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3684                        cp->regs + REG_MAC_RX_CFG);
3685
3686                 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3687
3688                 cp->crc_size = 4;
3689                 /* minimum size gigabit frame at half duplex */
3690                 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3691
3692         } else {
3693                 writel(val, cp->regs + REG_MAC_TX_CFG);
3694
3695                 /* checksum bug workaround. don't strip FCS when in
3696                  * half-duplex mode
3697                  */
3698                 val = readl(cp->regs + REG_MAC_RX_CFG);
3699                 if (full_duplex) {
3700                         val |= MAC_RX_CFG_STRIP_FCS;
3701                         cp->crc_size = 0;
3702                         cp->min_frame_size = CAS_MIN_MTU;
3703                 } else {
3704                         val &= ~MAC_RX_CFG_STRIP_FCS;
3705                         cp->crc_size = 4;
3706                         cp->min_frame_size = CAS_MIN_FRAME;
3707                 }
3708                 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3709                        cp->regs + REG_MAC_RX_CFG);
3710                 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3711         }
3712
3713         if (netif_msg_link(cp)) {
3714                 if (pause & 0x01) {
3715                         printk(KERN_INFO "%s: Pause is enabled "
3716                                "(rxfifo: %d off: %d on: %d)\n",
3717                                cp->dev->name,
3718                                cp->rx_fifo_size,
3719                                cp->rx_pause_off,
3720                                cp->rx_pause_on);
3721                 } else if (pause & 0x10) {
3722                         printk(KERN_INFO "%s: TX pause enabled\n",
3723                                cp->dev->name);
3724                 } else {
3725                         printk(KERN_INFO "%s: Pause is disabled\n",
3726                                cp->dev->name);
3727                 }
3728         }
3729
3730         val = readl(cp->regs + REG_MAC_CTRL_CFG);
3731         val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3732         if (pause) { /* symmetric or asymmetric pause */
3733                 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3734                 if (pause & 0x01) { /* symmetric pause */
3735                         val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3736                 }
3737         }
3738         writel(val, cp->regs + REG_MAC_CTRL_CFG);
3739         cas_start_dma(cp);
3740 }
3741
3742 /* Must be invoked under cp->lock. */
3743 static void cas_init_hw(struct cas *cp, int restart_link)
3744 {
3745         if (restart_link)
3746                 cas_phy_init(cp);
3747
3748         cas_init_pause_thresholds(cp);
3749         cas_init_mac(cp);
3750         cas_init_dma(cp);
3751
3752         if (restart_link) {
3753                 /* Default aneg parameters */
3754                 cp->timer_ticks = 0;
3755                 cas_begin_auto_negotiation(cp, NULL);
3756         } else if (cp->lstate == link_up) {
3757                 cas_set_link_modes(cp);
3758                 netif_carrier_on(cp->dev);
3759         }
3760 }
3761
3762 /* Must be invoked under cp->lock. on earlier cassini boards,
3763  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3764  * let it settle out, and then restore pci state.
3765  */
3766 static void cas_hard_reset(struct cas *cp)
3767 {
3768         writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3769         udelay(20);
3770         pci_restore_state(cp->pdev);
3771 }
3772
3773
3774 static void cas_global_reset(struct cas *cp, int blkflag)
3775 {
3776         int limit;
3777
3778         /* issue a global reset. don't use RSTOUT. */
3779         if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3780                 /* For PCS, when the blkflag is set, we should set the
3781                  * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3782                  * the last autonegotiation from being cleared.  We'll
3783                  * need some special handling if the chip is set into a
3784                  * loopback mode.
3785                  */
3786                 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3787                        cp->regs + REG_SW_RESET);
3788         } else {
3789                 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3790         }
3791
3792         /* need to wait at least 3ms before polling register */
3793         mdelay(3);
3794
3795         limit = STOP_TRIES;
3796         while (limit-- > 0) {
3797                 u32 val = readl(cp->regs + REG_SW_RESET);
3798                 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3799                         goto done;
3800                 udelay(10);
3801         }
3802         printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3803
3804 done:
3805         /* enable various BIM interrupts */
3806         writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3807                BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3808
3809         /* clear out pci error status mask for handled errors.
3810          * we don't deal with DMA counter overflows as they happen
3811          * all the time.
3812          */
3813         writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3814                                PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3815                                PCI_ERR_BIM_DMA_READ), cp->regs +
3816                REG_PCI_ERR_STATUS_MASK);
3817
3818         /* set up for MII by default to address mac rx reset timeout
3819          * issue
3820          */
3821         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3822 }
3823
3824 static void cas_reset(struct cas *cp, int blkflag)
3825 {
3826         u32 val;
3827
3828         cas_mask_intr(cp);
3829         cas_global_reset(cp, blkflag);
3830         cas_mac_reset(cp);
3831         cas_entropy_reset(cp);
3832
3833         /* disable dma engines. */
3834         val = readl(cp->regs + REG_TX_CFG);
3835         val &= ~TX_CFG_DMA_EN;
3836         writel(val, cp->regs + REG_TX_CFG);
3837
3838         val = readl(cp->regs + REG_RX_CFG);
3839         val &= ~RX_CFG_DMA_EN;
3840         writel(val, cp->regs + REG_RX_CFG);
3841
3842         /* program header parser */
3843         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3844             (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3845                 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3846         } else {
3847                 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3848         }
3849
3850         /* clear out error registers */
3851         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3852         cas_clear_mac_err(cp);
3853         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3854 }
3855
3856 /* Shut down the chip, must be called with pm_mutex held.  */
3857 static void cas_shutdown(struct cas *cp)
3858 {
3859         unsigned long flags;
3860
3861         /* Make us not-running to avoid timers respawning */
3862         cp->hw_running = 0;
3863
3864         del_timer_sync(&cp->link_timer);
3865
3866         /* Stop the reset task */
3867 #if 0
3868         while (atomic_read(&cp->reset_task_pending_mtu) ||
3869                atomic_read(&cp->reset_task_pending_spare) ||
3870                atomic_read(&cp->reset_task_pending_all))
3871                 schedule();
3872
3873 #else
3874         while (atomic_read(&cp->reset_task_pending))
3875                 schedule();
3876 #endif
3877         /* Actually stop the chip */
3878         cas_lock_all_save(cp, flags);
3879         cas_reset(cp, 0);
3880         if (cp->cas_flags & CAS_FLAG_SATURN)
3881                 cas_phy_powerdown(cp);
3882         cas_unlock_all_restore(cp, flags);
3883 }
3884
3885 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3886 {
3887         struct cas *cp = netdev_priv(dev);
3888
3889         if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3890                 return -EINVAL;
3891
3892         dev->mtu = new_mtu;
3893         if (!netif_running(dev) || !netif_device_present(dev))
3894                 return 0;
3895
3896         /* let the reset task handle it */
3897 #if 1
3898         atomic_inc(&cp->reset_task_pending);
3899         if ((cp->phy_type & CAS_PHY_SERDES)) {
3900                 atomic_inc(&cp->reset_task_pending_all);
3901         } else {
3902                 atomic_inc(&cp->reset_task_pending_mtu);
3903         }
3904         schedule_work(&cp->reset_task);
3905 #else
3906         atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3907                    CAS_RESET_ALL : CAS_RESET_MTU);
3908         printk(KERN_ERR "reset called in cas_change_mtu\n");
3909         schedule_work(&cp->reset_task);
3910 #endif
3911
3912         flush_scheduled_work();
3913         return 0;
3914 }
3915
3916 static void cas_clean_txd(struct cas *cp, int ring)
3917 {
3918         struct cas_tx_desc *txd = cp->init_txds[ring];
3919         struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3920         u64 daddr, dlen;
3921         int i, size;
3922
3923         size = TX_DESC_RINGN_SIZE(ring);
3924         for (i = 0; i < size; i++) {
3925                 int frag;
3926
3927                 if (skbs[i] == NULL)
3928                         continue;
3929
3930                 skb = skbs[i];
3931                 skbs[i] = NULL;
3932
3933                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3934                         int ent = i & (size - 1);
3935
3936                         /* first buffer is never a tiny buffer and so
3937                          * needs to be unmapped.
3938                          */
3939                         daddr = le64_to_cpu(txd[ent].buffer);
3940                         dlen  =  CAS_VAL(TX_DESC_BUFLEN,
3941                                          le64_to_cpu(txd[ent].control));
3942                         pci_unmap_page(cp->pdev, daddr, dlen,
3943                                        PCI_DMA_TODEVICE);
3944
3945                         if (frag != skb_shinfo(skb)->nr_frags) {
3946                                 i++;
3947
3948                                 /* next buffer might by a tiny buffer.
3949                                  * skip past it.
3950                                  */
3951                                 ent = i & (size - 1);
3952                                 if (cp->tx_tiny_use[ring][ent].used)
3953                                         i++;
3954                         }
3955                 }
3956                 dev_kfree_skb_any(skb);
3957         }
3958
3959         /* zero out tiny buf usage */
3960         memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3961 }
3962
3963 /* freed on close */
3964 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3965 {
3966         cas_page_t **page = cp->rx_pages[ring];
3967         int i, size;
3968
3969         size = RX_DESC_RINGN_SIZE(ring);
3970         for (i = 0; i < size; i++) {
3971                 if (page[i]) {
3972                         cas_page_free(cp, page[i]);
3973                         page[i] = NULL;
3974                 }
3975         }
3976 }
3977
3978 static void cas_free_rxds(struct cas *cp)
3979 {
3980         int i;
3981
3982         for (i = 0; i < N_RX_DESC_RINGS; i++)
3983                 cas_free_rx_desc(cp, i);
3984 }
3985
3986 /* Must be invoked under cp->lock. */
3987 static void cas_clean_rings(struct cas *cp)
3988 {
3989         int i;
3990
3991         /* need to clean all tx rings */
3992         memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3993         memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3994         for (i = 0; i < N_TX_RINGS; i++)
3995                 cas_clean_txd(cp, i);
3996
3997         /* zero out init block */
3998         memset(cp->init_block, 0, sizeof(struct cas_init_block));
3999         cas_clean_rxds(cp);
4000         cas_clean_rxcs(cp);
4001 }
4002
4003 /* allocated on open */
4004 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4005 {
4006         cas_page_t **page = cp->rx_pages[ring];
4007         int size, i = 0;
4008
4009         size = RX_DESC_RINGN_SIZE(ring);
4010         for (i = 0; i < size; i++) {
4011                 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4012                         return -1;
4013         }
4014         return 0;
4015 }
4016
4017 static int cas_alloc_rxds(struct cas *cp)
4018 {
4019         int i;
4020
4021         for (i = 0; i < N_RX_DESC_RINGS; i++) {
4022                 if (cas_alloc_rx_desc(cp, i) < 0) {
4023                         cas_free_rxds(cp);
4024                         return -1;
4025                 }
4026         }
4027         return 0;
4028 }
4029
4030 static void cas_reset_task(struct work_struct *work)
4031 {
4032         struct cas *cp = container_of(work, struct cas, reset_task);
4033 #if 0
4034         int pending = atomic_read(&cp->reset_task_pending);
4035 #else
4036         int pending_all = atomic_read(&cp->reset_task_pending_all);
4037         int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4038         int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4039
4040         if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4041                 /* We can have more tasks scheduled than actually
4042                  * needed.
4043                  */
4044                 atomic_dec(&cp->reset_task_pending);
4045                 return;
4046         }
4047 #endif
4048         /* The link went down, we reset the ring, but keep
4049          * DMA stopped. Use this function for reset
4050          * on error as well.
4051          */
4052         if (cp->hw_running) {
4053                 unsigned long flags;
4054
4055                 /* Make sure we don't get interrupts or tx packets */
4056                 netif_device_detach(cp->dev);
4057                 cas_lock_all_save(cp, flags);
4058
4059                 if (cp->opened) {
4060                         /* We call cas_spare_recover when we call cas_open.
4061                          * but we do not initialize the lists cas_spare_recover
4062                          * uses until cas_open is called.
4063                          */
4064                         cas_spare_recover(cp, GFP_ATOMIC);
4065                 }
4066 #if 1
4067                 /* test => only pending_spare set */
4068                 if (!pending_all && !pending_mtu)
4069                         goto done;
4070 #else
4071                 if (pending == CAS_RESET_SPARE)
4072                         goto done;
4073 #endif
4074                 /* when pending == CAS_RESET_ALL, the following
4075                  * call to cas_init_hw will restart auto negotiation.
4076                  * Setting the second argument of cas_reset to
4077                  * !(pending == CAS_RESET_ALL) will set this argument
4078                  * to 1 (avoiding reinitializing the PHY for the normal
4079                  * PCS case) when auto negotiation is not restarted.
4080                  */
4081 #if 1
4082                 cas_reset(cp, !(pending_all > 0));
4083                 if (cp->opened)
4084                         cas_clean_rings(cp);
4085                 cas_init_hw(cp, (pending_all > 0));
4086 #else
4087                 cas_reset(cp, !(pending == CAS_RESET_ALL));
4088                 if (cp->opened)
4089                         cas_clean_rings(cp);
4090                 cas_init_hw(cp, pending == CAS_RESET_ALL);
4091 #endif
4092
4093 done:
4094                 cas_unlock_all_restore(cp, flags);
4095                 netif_device_attach(cp->dev);
4096         }
4097 #if 1
4098         atomic_sub(pending_all, &cp->reset_task_pending_all);
4099         atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4100         atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4101         atomic_dec(&cp->reset_task_pending);
4102 #else
4103         atomic_set(&cp->reset_task_pending, 0);
4104 #endif
4105 }
4106
4107 static void cas_link_timer(unsigned long data)
4108 {
4109         struct cas *cp = (struct cas *) data;
4110         int mask, pending = 0, reset = 0;
4111         unsigned long flags;
4112
4113         if (link_transition_timeout != 0 &&
4114             cp->link_transition_jiffies_valid &&
4115             ((jiffies - cp->link_transition_jiffies) >
4116               (link_transition_timeout))) {
4117                 /* One-second counter so link-down workaround doesn't
4118                  * cause resets to occur so fast as to fool the switch
4119                  * into thinking the link is down.
4120                  */
4121                 cp->link_transition_jiffies_valid = 0;
4122         }
4123
4124         if (!cp->hw_running)
4125                 return;
4126
4127         spin_lock_irqsave(&cp->lock, flags);
4128         cas_lock_tx(cp);
4129         cas_entropy_gather(cp);
4130
4131         /* If the link task is still pending, we just
4132          * reschedule the link timer
4133          */
4134 #if 1
4135         if (atomic_read(&cp->reset_task_pending_all) ||
4136             atomic_read(&cp->reset_task_pending_spare) ||
4137             atomic_read(&cp->reset_task_pending_mtu))
4138                 goto done;
4139 #else
4140         if (atomic_read(&cp->reset_task_pending))
4141                 goto done;
4142 #endif
4143
4144         /* check for rx cleaning */
4145         if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4146                 int i, rmask;
4147
4148                 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4149                         rmask = CAS_FLAG_RXD_POST(i);
4150                         if ((mask & rmask) == 0)
4151                                 continue;
4152
4153                         /* post_rxds will do a mod_timer */
4154                         if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4155                                 pending = 1;
4156                                 continue;
4157                         }
4158                         cp->cas_flags &= ~rmask;
4159                 }
4160         }
4161
4162         if (CAS_PHY_MII(cp->phy_type)) {
4163                 u16 bmsr;
4164                 cas_mif_poll(cp, 0);
4165                 bmsr = cas_phy_read(cp, MII_BMSR);
4166                 /* WTZ: Solaris driver reads this twice, but that
4167                  * may be due to the PCS case and the use of a
4168                  * common implementation. Read it twice here to be
4169                  * safe.
4170                  */
4171                 bmsr = cas_phy_read(cp, MII_BMSR);
4172                 cas_mif_poll(cp, 1);
4173                 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4174                 reset = cas_mii_link_check(cp, bmsr);
4175         } else {
4176                 reset = cas_pcs_link_check(cp);
4177         }
4178
4179         if (reset)
4180                 goto done;
4181
4182         /* check for tx state machine confusion */
4183         if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4184                 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4185                 u32 wptr, rptr;
4186                 int tlm  = CAS_VAL(MAC_SM_TLM, val);
4187
4188                 if (((tlm == 0x5) || (tlm == 0x3)) &&
4189                     (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4190                         if (netif_msg_tx_err(cp))
4191                                 printk(KERN_DEBUG "%s: tx err: "
4192                                        "MAC_STATE[%08x]\n",
4193                                        cp->dev->name, val);
4194                         reset = 1;
4195                         goto done;
4196                 }
4197
4198                 val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4199                 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4200                 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4201                 if ((val == 0) && (wptr != rptr)) {
4202                         if (netif_msg_tx_err(cp))
4203                                 printk(KERN_DEBUG "%s: tx err: "
4204                                        "TX_FIFO[%08x:%08x:%08x]\n",
4205                                        cp->dev->name, val, wptr, rptr);
4206                         reset = 1;
4207                 }
4208
4209                 if (reset)
4210                         cas_hard_reset(cp);
4211         }
4212
4213 done:
4214         if (reset) {
4215 #if 1
4216                 atomic_inc(&cp->reset_task_pending);
4217                 atomic_inc(&cp->reset_task_pending_all);
4218                 schedule_work(&cp->reset_task);
4219 #else
4220                 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4221                 printk(KERN_ERR "reset called in cas_link_timer\n");
4222                 schedule_work(&cp->reset_task);
4223 #endif
4224         }
4225
4226         if (!pending)
4227                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4228         cas_unlock_tx(cp);
4229         spin_unlock_irqrestore(&cp->lock, flags);
4230 }
4231
4232 /* tiny buffers are used to avoid target abort issues with
4233  * older cassini's
4234  */
4235 static void cas_tx_tiny_free(struct cas *cp)
4236 {
4237         struct pci_dev *pdev = cp->pdev;
4238         int i;
4239
4240         for (i = 0; i < N_TX_RINGS; i++) {
4241                 if (!cp->tx_tiny_bufs[i])
4242                         continue;
4243
4244                 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4245                                     cp->tx_tiny_bufs[i],
4246                                     cp->tx_tiny_dvma[i]);
4247                 cp->tx_tiny_bufs[i] = NULL;
4248         }
4249 }
4250
4251 static int cas_tx_tiny_alloc(struct cas *cp)
4252 {
4253         struct pci_dev *pdev = cp->pdev;
4254         int i;
4255
4256         for (i = 0; i < N_TX_RINGS; i++) {
4257                 cp->tx_tiny_bufs[i] =
4258                         pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4259                                              &cp->tx_tiny_dvma[i]);
4260                 if (!cp->tx_tiny_bufs[i]) {
4261                         cas_tx_tiny_free(cp);
4262                         return -1;
4263                 }
4264         }
4265         return 0;
4266 }
4267
4268
4269 static int cas_open(struct net_device *dev)
4270 {
4271         struct cas *cp = netdev_priv(dev);
4272         int hw_was_up, err;
4273         unsigned long flags;
4274
4275         mutex_lock(&cp->pm_mutex);
4276
4277         hw_was_up = cp->hw_running;
4278
4279         /* The power-management mutex protects the hw_running
4280          * etc. state so it is safe to do this bit without cp->lock
4281          */
4282         if (!cp->hw_running) {
4283                 /* Reset the chip */
4284                 cas_lock_all_save(cp, flags);
4285                 /* We set the second arg to cas_reset to zero
4286                  * because cas_init_hw below will have its second
4287                  * argument set to non-zero, which will force
4288                  * autonegotiation to start.
4289                  */
4290                 cas_reset(cp, 0);
4291                 cp->hw_running = 1;
4292                 cas_unlock_all_restore(cp, flags);
4293         }
4294
4295         if (cas_tx_tiny_alloc(cp) < 0)
4296                 return -ENOMEM;
4297
4298         /* alloc rx descriptors */
4299         err = -ENOMEM;
4300         if (cas_alloc_rxds(cp) < 0)
4301                 goto err_tx_tiny;
4302
4303         /* allocate spares */
4304         cas_spare_init(cp);
4305         cas_spare_recover(cp, GFP_KERNEL);
4306
4307         /* We can now request the interrupt as we know it's masked
4308          * on the controller. cassini+ has up to 4 interrupts
4309          * that can be used, but you need to do explicit pci interrupt
4310          * mapping to expose them
4311          */
4312         if (request_irq(cp->pdev->irq, cas_interrupt,
4313                         IRQF_SHARED, dev->name, (void *) dev)) {
4314                 printk(KERN_ERR "%s: failed to request irq !\n",
4315                        cp->dev->name);
4316                 err = -EAGAIN;
4317                 goto err_spare;
4318         }
4319
4320 #ifdef USE_NAPI
4321         napi_enable(&cp->napi);
4322 #endif
4323         /* init hw */
4324         cas_lock_all_save(cp, flags);
4325         cas_clean_rings(cp);
4326         cas_init_hw(cp, !hw_was_up);
4327         cp->opened = 1;
4328         cas_unlock_all_restore(cp, flags);
4329
4330         netif_start_queue(dev);
4331         mutex_unlock(&cp->pm_mutex);
4332         return 0;
4333
4334 err_spare:
4335         cas_spare_free(cp);
4336         cas_free_rxds(cp);
4337 err_tx_tiny:
4338         cas_tx_tiny_free(cp);
4339         mutex_unlock(&cp->pm_mutex);
4340         return err;
4341 }
4342
4343 static int cas_close(struct net_device *dev)
4344 {
4345         unsigned long flags;
4346         struct cas *cp = netdev_priv(dev);
4347
4348 #ifdef USE_NAPI
4349         napi_disable(&cp->napi);
4350 #endif
4351         /* Make sure we don't get distracted by suspend/resume */
4352         mutex_lock(&cp->pm_mutex);
4353
4354         netif_stop_queue(dev);
4355
4356         /* Stop traffic, mark us closed */
4357         cas_lock_all_save(cp, flags);
4358         cp->opened = 0;
4359         cas_reset(cp, 0);
4360         cas_phy_init(cp);
4361         cas_begin_auto_negotiation(cp, NULL);
4362         cas_clean_rings(cp);
4363         cas_unlock_all_restore(cp, flags);
4364
4365         free_irq(cp->pdev->irq, (void *) dev);
4366         cas_spare_free(cp);
4367         cas_free_rxds(cp);
4368         cas_tx_tiny_free(cp);
4369         mutex_unlock(&cp->pm_mutex);
4370         return 0;
4371 }
4372
4373 static struct {
4374         const char name[ETH_GSTRING_LEN];
4375 } ethtool_cassini_statnames[] = {
4376         {"collisions"},
4377         {"rx_bytes"},
4378         {"rx_crc_errors"},
4379         {"rx_dropped"},
4380         {"rx_errors"},
4381         {"rx_fifo_errors"},
4382         {"rx_frame_errors"},
4383         {"rx_length_errors"},
4384         {"rx_over_errors"},
4385         {"rx_packets"},
4386         {"tx_aborted_errors"},
4387         {"tx_bytes"},
4388         {"tx_dropped"},
4389         {"tx_errors"},
4390         {"tx_fifo_errors"},
4391         {"tx_packets"}
4392 };
4393 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4394
4395 static struct {
4396         const int offsets;      /* neg. values for 2nd arg to cas_read_phy */
4397 } ethtool_register_table[] = {
4398         {-MII_BMSR},
4399         {-MII_BMCR},
4400         {REG_CAWR},
4401         {REG_INF_BURST},
4402         {REG_BIM_CFG},
4403         {REG_RX_CFG},
4404         {REG_HP_CFG},
4405         {REG_MAC_TX_CFG},
4406         {REG_MAC_RX_CFG},
4407         {REG_MAC_CTRL_CFG},
4408         {REG_MAC_XIF_CFG},
4409         {REG_MIF_CFG},
4410         {REG_PCS_CFG},
4411         {REG_SATURN_PCFG},
4412         {REG_PCS_MII_STATUS},
4413         {REG_PCS_STATE_MACHINE},
4414         {REG_MAC_COLL_EXCESS},
4415         {REG_MAC_COLL_LATE}
4416 };
4417 #define CAS_REG_LEN     ARRAY_SIZE(ethtool_register_table)
4418 #define CAS_MAX_REGS    (sizeof (u32)*CAS_REG_LEN)
4419
4420 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4421 {
4422         u8 *p;
4423         int i;
4424         unsigned long flags;
4425
4426         spin_lock_irqsave(&cp->lock, flags);
4427         for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4428                 u16 hval;
4429                 u32 val;
4430                 if (ethtool_register_table[i].offsets < 0) {
4431                         hval = cas_phy_read(cp,
4432                                     -ethtool_register_table[i].offsets);
4433                         val = hval;
4434                 } else {
4435                         val= readl(cp->regs+ethtool_register_table[i].offsets);
4436                 }
4437                 memcpy(p, (u8 *)&val, sizeof(u32));
4438         }
4439         spin_unlock_irqrestore(&cp->lock, flags);
4440 }
4441
4442 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4443 {
4444         struct cas *cp = netdev_priv(dev);
4445         struct net_device_stats *stats = cp->net_stats;
4446         unsigned long flags;
4447         int i;
4448         unsigned long tmp;
4449
4450         /* we collate all of the stats into net_stats[N_TX_RING] */
4451         if (!cp->hw_running)
4452                 return stats + N_TX_RINGS;
4453
4454         /* collect outstanding stats */
4455         /* WTZ: the Cassini spec gives these as 16 bit counters but
4456          * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4457          * in case the chip somehow puts any garbage in the other bits.
4458          * Also, counter usage didn't seem to mach what Adrian did
4459          * in the parts of the code that set these quantities. Made
4460          * that consistent.
4461          */
4462         spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4463         stats[N_TX_RINGS].rx_crc_errors +=
4464           readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4465         stats[N_TX_RINGS].rx_frame_errors +=
4466                 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4467         stats[N_TX_RINGS].rx_length_errors +=
4468                 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4469 #if 1
4470         tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4471                 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4472         stats[N_TX_RINGS].tx_aborted_errors += tmp;
4473         stats[N_TX_RINGS].collisions +=
4474           tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4475 #else
4476         stats[N_TX_RINGS].tx_aborted_errors +=
4477                 readl(cp->regs + REG_MAC_COLL_EXCESS);
4478         stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4479                 readl(cp->regs + REG_MAC_COLL_LATE);
4480 #endif
4481         cas_clear_mac_err(cp);
4482
4483         /* saved bits that are unique to ring 0 */
4484         spin_lock(&cp->stat_lock[0]);
4485         stats[N_TX_RINGS].collisions        += stats[0].collisions;
4486         stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4487         stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4488         stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4489         stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4490         stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4491         spin_unlock(&cp->stat_lock[0]);
4492
4493         for (i = 0; i < N_TX_RINGS; i++) {
4494                 spin_lock(&cp->stat_lock[i]);
4495                 stats[N_TX_RINGS].rx_length_errors +=
4496                         stats[i].rx_length_errors;
4497                 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4498                 stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4499                 stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4500                 stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4501                 stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4502                 stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4503                 stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4504                 stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4505                 stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4506                 memset(stats + i, 0, sizeof(struct net_device_stats));
4507                 spin_unlock(&cp->stat_lock[i]);
4508         }
4509         spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4510         return stats + N_TX_RINGS;
4511 }
4512
4513
4514 static void cas_set_multicast(struct net_device *dev)
4515 {
4516         struct cas *cp = netdev_priv(dev);
4517         u32 rxcfg, rxcfg_new;
4518         unsigned long flags;
4519         int limit = STOP_TRIES;
4520
4521         if (!cp->hw_running)
4522                 return;
4523
4524         spin_lock_irqsave(&cp->lock, flags);
4525         rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4526
4527         /* disable RX MAC and wait for completion */
4528         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4529         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4530                 if (!limit--)
4531                         break;
4532                 udelay(10);
4533         }
4534
4535         /* disable hash filter and wait for completion */
4536         limit = STOP_TRIES;
4537         rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4538         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4539         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4540                 if (!limit--)
4541                         break;
4542                 udelay(10);
4543         }
4544
4545         /* program hash filters */
4546         cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4547         rxcfg |= rxcfg_new;
4548         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4549         spin_unlock_irqrestore(&cp->lock, flags);
4550 }
4551
4552 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4553 {
4554         struct cas *cp = netdev_priv(dev);
4555         strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4556         strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4557         info->fw_version[0] = '\0';
4558         strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4559         info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4560                 cp->casreg_len : CAS_MAX_REGS;
4561         info->n_stats = CAS_NUM_STAT_KEYS;
4562 }
4563
4564 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4565 {
4566         struct cas *cp = netdev_priv(dev);
4567         u16 bmcr;
4568         int full_duplex, speed, pause;
4569         unsigned long flags;
4570         enum link_state linkstate = link_up;
4571
4572         cmd->advertising = 0;
4573         cmd->supported = SUPPORTED_Autoneg;
4574         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4575                 cmd->supported |= SUPPORTED_1000baseT_Full;
4576                 cmd->advertising |= ADVERTISED_1000baseT_Full;
4577         }
4578
4579         /* Record PHY settings if HW is on. */
4580         spin_lock_irqsave(&cp->lock, flags);
4581         bmcr = 0;
4582         linkstate = cp->lstate;
4583         if (CAS_PHY_MII(cp->phy_type)) {
4584                 cmd->port = PORT_MII;
4585                 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4586                         XCVR_INTERNAL : XCVR_EXTERNAL;
4587                 cmd->phy_address = cp->phy_addr;
4588                 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4589                         ADVERTISED_10baseT_Half |
4590                         ADVERTISED_10baseT_Full |
4591                         ADVERTISED_100baseT_Half |
4592                         ADVERTISED_100baseT_Full;
4593
4594                 cmd->supported |=
4595                         (SUPPORTED_10baseT_Half |
4596                          SUPPORTED_10baseT_Full |
4597                          SUPPORTED_100baseT_Half |
4598                          SUPPORTED_100baseT_Full |
4599                          SUPPORTED_TP | SUPPORTED_MII);
4600
4601                 if (cp->hw_running) {
4602                         cas_mif_poll(cp, 0);
4603                         bmcr = cas_phy_read(cp, MII_BMCR);
4604                         cas_read_mii_link_mode(cp, &full_duplex,
4605                                                &speed, &pause);
4606                         cas_mif_poll(cp, 1);
4607                 }
4608
4609         } else {
4610                 cmd->port = PORT_FIBRE;
4611                 cmd->transceiver = XCVR_INTERNAL;
4612                 cmd->phy_address = 0;
4613                 cmd->supported   |= SUPPORTED_FIBRE;
4614                 cmd->advertising |= ADVERTISED_FIBRE;
4615
4616                 if (cp->hw_running) {
4617                         /* pcs uses the same bits as mii */
4618                         bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4619                         cas_read_pcs_link_mode(cp, &full_duplex,
4620                                                &speed, &pause);
4621                 }
4622         }
4623         spin_unlock_irqrestore(&cp->lock, flags);
4624
4625         if (bmcr & BMCR_ANENABLE) {
4626                 cmd->advertising |= ADVERTISED_Autoneg;
4627                 cmd->autoneg = AUTONEG_ENABLE;
4628                 cmd->speed = ((speed == 10) ?
4629                               SPEED_10 :
4630                               ((speed == 1000) ?
4631                                SPEED_1000 : SPEED_100));
4632                 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4633         } else {
4634                 cmd->autoneg = AUTONEG_DISABLE;
4635                 cmd->speed =
4636                         (bmcr & CAS_BMCR_SPEED1000) ?
4637                         SPEED_1000 :
4638                         ((bmcr & BMCR_SPEED100) ? SPEED_100:
4639                          SPEED_10);
4640                 cmd->duplex =
4641                         (bmcr & BMCR_FULLDPLX) ?
4642                         DUPLEX_FULL : DUPLEX_HALF;
4643         }
4644         if (linkstate != link_up) {
4645                 /* Force these to "unknown" if the link is not up and
4646                  * autonogotiation in enabled. We can set the link
4647                  * speed to 0, but not cmd->duplex,
4648                  * because its legal values are 0 and 1.  Ethtool will
4649                  * print the value reported in parentheses after the
4650                  * word "Unknown" for unrecognized values.
4651                  *
4652                  * If in forced mode, we report the speed and duplex
4653                  * settings that we configured.
4654                  */
4655                 if (cp->link_cntl & BMCR_ANENABLE) {
4656                         cmd->speed = 0;
4657                         cmd->duplex = 0xff;
4658                 } else {
4659                         cmd->speed = SPEED_10;
4660                         if (cp->link_cntl & BMCR_SPEED100) {
4661                                 cmd->speed = SPEED_100;
4662                         } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4663                                 cmd->speed = SPEED_1000;
4664                         }
4665                         cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4666                                 DUPLEX_FULL : DUPLEX_HALF;
4667                 }
4668         }
4669         return 0;
4670 }
4671
4672 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4673 {
4674         struct cas *cp = netdev_priv(dev);
4675         unsigned long flags;
4676
4677         /* Verify the settings we care about. */
4678         if (cmd->autoneg != AUTONEG_ENABLE &&
4679             cmd->autoneg != AUTONEG_DISABLE)
4680                 return -EINVAL;
4681
4682         if (cmd->autoneg == AUTONEG_DISABLE &&
4683             ((cmd->speed != SPEED_1000 &&
4684               cmd->speed != SPEED_100 &&
4685               cmd->speed != SPEED_10) ||
4686              (cmd->duplex != DUPLEX_HALF &&
4687               cmd->duplex != DUPLEX_FULL)))
4688                 return -EINVAL;
4689
4690         /* Apply settings and restart link process. */
4691         spin_lock_irqsave(&cp->lock, flags);
4692         cas_begin_auto_negotiation(cp, cmd);
4693         spin_unlock_irqrestore(&cp->lock, flags);
4694         return 0;
4695 }
4696
4697 static int cas_nway_reset(struct net_device *dev)
4698 {
4699         struct cas *cp = netdev_priv(dev);
4700         unsigned long flags;
4701
4702         if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4703                 return -EINVAL;
4704
4705         /* Restart link process. */
4706         spin_lock_irqsave(&cp->lock, flags);
4707         cas_begin_auto_negotiation(cp, NULL);
4708         spin_unlock_irqrestore(&cp->lock, flags);
4709
4710         return 0;
4711 }
4712
4713 static u32 cas_get_link(struct net_device *dev)
4714 {
4715         struct cas *cp = netdev_priv(dev);
4716         return cp->lstate == link_up;
4717 }
4718
4719 static u32 cas_get_msglevel(struct net_device *dev)
4720 {
4721         struct cas *cp = netdev_priv(dev);
4722         return cp->msg_enable;
4723 }
4724
4725 static void cas_set_msglevel(struct net_device *dev, u32 value)
4726 {
4727         struct cas *cp = netdev_priv(dev);
4728         cp->msg_enable = value;
4729 }
4730
4731 static int cas_get_regs_len(struct net_device *dev)
4732 {
4733         struct cas *cp = netdev_priv(dev);
4734         return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4735 }
4736
4737 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4738                              void *p)
4739 {
4740         struct cas *cp = netdev_priv(dev);
4741         regs->version = 0;
4742         /* cas_read_regs handles locks (cp->lock).  */
4743         cas_read_regs(cp, p, regs->len / sizeof(u32));
4744 }
4745
4746 static int cas_get_sset_count(struct net_device *dev, int sset)
4747 {
4748         switch (sset) {
4749         case ETH_SS_STATS:
4750                 return CAS_NUM_STAT_KEYS;
4751         default:
4752                 return -EOPNOTSUPP;
4753         }
4754 }
4755
4756 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4757 {
4758          memcpy(data, &ethtool_cassini_statnames,
4759                                          CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4760 }
4761
4762 static void cas_get_ethtool_stats(struct net_device *dev,
4763                                       struct ethtool_stats *estats, u64 *data)
4764 {
4765         struct cas *cp = netdev_priv(dev);
4766         struct net_device_stats *stats = cas_get_stats(cp->dev);
4767         int i = 0;
4768         data[i++] = stats->collisions;
4769         data[i++] = stats->rx_bytes;
4770         data[i++] = stats->rx_crc_errors;
4771         data[i++] = stats->rx_dropped;
4772         data[i++] = stats->rx_errors;
4773         data[i++] = stats->rx_fifo_errors;
4774         data[i++] = stats->rx_frame_errors;
4775         data[i++] = stats->rx_length_errors;
4776         data[i++] = stats->rx_over_errors;
4777         data[i++] = stats->rx_packets;
4778         data[i++] = stats->tx_aborted_errors;
4779         data[i++] = stats->tx_bytes;
4780         data[i++] = stats->tx_dropped;
4781         data[i++] = stats->tx_errors;
4782         data[i++] = stats->tx_fifo_errors;
4783         data[i++] = stats->tx_packets;
4784         BUG_ON(i != CAS_NUM_STAT_KEYS);
4785 }
4786
4787 static const struct ethtool_ops cas_ethtool_ops = {
4788         .get_drvinfo            = cas_get_drvinfo,
4789         .get_settings           = cas_get_settings,
4790         .set_settings           = cas_set_settings,
4791         .nway_reset             = cas_nway_reset,
4792         .get_link               = cas_get_link,
4793         .get_msglevel           = cas_get_msglevel,
4794         .set_msglevel           = cas_set_msglevel,
4795         .get_regs_len           = cas_get_regs_len,
4796         .get_regs               = cas_get_regs,
4797         .get_sset_count         = cas_get_sset_count,
4798         .get_strings            = cas_get_strings,
4799         .get_ethtool_stats      = cas_get_ethtool_stats,
4800 };
4801
4802 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4803 {
4804         struct cas *cp = netdev_priv(dev);
4805         struct mii_ioctl_data *data = if_mii(ifr);
4806         unsigned long flags;
4807         int rc = -EOPNOTSUPP;
4808
4809         /* Hold the PM mutex while doing ioctl's or we may collide
4810          * with open/close and power management and oops.
4811          */
4812         mutex_lock(&cp->pm_mutex);
4813         switch (cmd) {
4814         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
4815                 data->phy_id = cp->phy_addr;
4816                 /* Fallthrough... */
4817
4818         case SIOCGMIIREG:               /* Read MII PHY register. */
4819                 spin_lock_irqsave(&cp->lock, flags);
4820                 cas_mif_poll(cp, 0);
4821                 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4822                 cas_mif_poll(cp, 1);
4823                 spin_unlock_irqrestore(&cp->lock, flags);
4824                 rc = 0;
4825                 break;
4826
4827         case SIOCSMIIREG:               /* Write MII PHY register. */
4828                 if (!capable(CAP_NET_ADMIN)) {
4829                         rc = -EPERM;
4830                         break;
4831                 }
4832                 spin_lock_irqsave(&cp->lock, flags);
4833                 cas_mif_poll(cp, 0);
4834                 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4835                 cas_mif_poll(cp, 1);
4836                 spin_unlock_irqrestore(&cp->lock, flags);
4837                 break;
4838         default:
4839                 break;
4840         };
4841
4842         mutex_unlock(&cp->pm_mutex);
4843         return rc;
4844 }
4845
4846 /* When this chip sits underneath an Intel 31154 bridge, it is the
4847  * only subordinate device and we can tweak the bridge settings to
4848  * reflect that fact.
4849  */
4850 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4851 {
4852         struct pci_dev *pdev = cas_pdev->bus->self;
4853         u32 val;
4854
4855         if (!pdev)
4856                 return;
4857
4858         if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4859                 return;
4860
4861         /* Clear bit 10 (Bus Parking Control) in the Secondary
4862          * Arbiter Control/Status Register which lives at offset
4863          * 0x41.  Using a 32-bit word read/modify/write at 0x40
4864          * is much simpler so that's how we do this.
4865          */
4866         pci_read_config_dword(pdev, 0x40, &val);
4867         val &= ~0x00040000;
4868         pci_write_config_dword(pdev, 0x40, val);
4869
4870         /* Max out the Multi-Transaction Timer settings since
4871          * Cassini is the only device present.
4872          *
4873          * The register is 16-bit and lives at 0x50.  When the
4874          * settings are enabled, it extends the GRANT# signal
4875          * for a requestor after a transaction is complete.  This
4876          * allows the next request to run without first needing
4877          * to negotiate the GRANT# signal back.
4878          *
4879          * Bits 12:10 define the grant duration:
4880          *
4881          *      1       --      16 clocks
4882          *      2       --      32 clocks
4883          *      3       --      64 clocks
4884          *      4       --      128 clocks
4885          *      5       --      256 clocks
4886          *
4887          * All other values are illegal.
4888          *
4889          * Bits 09:00 define which REQ/GNT signal pairs get the
4890          * GRANT# signal treatment.  We set them all.
4891          */
4892         pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4893
4894         /* The Read Prefecth Policy register is 16-bit and sits at
4895          * offset 0x52.  It enables a "smart" pre-fetch policy.  We
4896          * enable it and max out all of the settings since only one
4897          * device is sitting underneath and thus bandwidth sharing is
4898          * not an issue.
4899          *
4900          * The register has several 3 bit fields, which indicates a
4901          * multiplier applied to the base amount of prefetching the
4902          * chip would do.  These fields are at:
4903          *
4904          *      15:13   ---     ReRead Primary Bus
4905          *      12:10   ---     FirstRead Primary Bus
4906          *      09:07   ---     ReRead Secondary Bus
4907          *      06:04   ---     FirstRead Secondary Bus
4908          *
4909          * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4910          * get enabled on.  Bit 3 is a grouped enabler which controls
4911          * all of the REQ/GNT pairs from [8:3].  Bits 2 to 0 control
4912          * the individual REQ/GNT pairs [2:0].
4913          */
4914         pci_write_config_word(pdev, 0x52,
4915                               (0x7 << 13) |
4916                               (0x7 << 10) |
4917                               (0x7 <<  7) |
4918                               (0x7 <<  4) |
4919                               (0xf <<  0));
4920
4921         /* Force cacheline size to 0x8 */
4922         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4923
4924         /* Force latency timer to maximum setting so Cassini can
4925          * sit on the bus as long as it likes.
4926          */
4927         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4928 }
4929
4930 static int __devinit cas_init_one(struct pci_dev *pdev,
4931                                   const struct pci_device_id *ent)
4932 {
4933         static int cas_version_printed = 0;
4934         unsigned long casreg_len;
4935         struct net_device *dev;
4936         struct cas *cp;
4937         int i, err, pci_using_dac;
4938         u16 pci_cmd;
4939         u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4940         DECLARE_MAC_BUF(mac);
4941
4942         if (cas_version_printed++ == 0)
4943                 printk(KERN_INFO "%s", version);
4944
4945         err = pci_enable_device(pdev);
4946         if (err) {
4947                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
4948                 return err;
4949         }
4950
4951         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4952                 dev_err(&pdev->dev, "Cannot find proper PCI device "
4953                        "base address, aborting.\n");
4954                 err = -ENODEV;
4955                 goto err_out_disable_pdev;
4956         }
4957
4958         dev = alloc_etherdev(sizeof(*cp));
4959         if (!dev) {
4960                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
4961                 err = -ENOMEM;
4962                 goto err_out_disable_pdev;
4963         }
4964         SET_NETDEV_DEV(dev, &pdev->dev);
4965
4966         err = pci_request_regions(pdev, dev->name);
4967         if (err) {
4968                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
4969                 goto err_out_free_netdev;
4970         }
4971         pci_set_master(pdev);
4972
4973         /* we must always turn on parity response or else parity
4974          * doesn't get generated properly. disable SERR/PERR as well.
4975          * in addition, we want to turn MWI on.
4976          */
4977         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4978         pci_cmd &= ~PCI_COMMAND_SERR;
4979         pci_cmd |= PCI_COMMAND_PARITY;
4980         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4981         if (pci_try_set_mwi(pdev))
4982                 printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
4983                        pci_name(pdev));
4984
4985         cas_program_bridge(pdev);
4986
4987         /*
4988          * On some architectures, the default cache line size set
4989          * by pci_try_set_mwi reduces perforamnce.  We have to increase
4990          * it for this case.  To start, we'll print some configuration
4991          * data.
4992          */
4993 #if 1
4994         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4995                              &orig_cacheline_size);
4996         if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4997                 cas_cacheline_size =
4998                         (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4999                         CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
5000                 if (pci_write_config_byte(pdev,
5001                                           PCI_CACHE_LINE_SIZE,
5002                                           cas_cacheline_size)) {
5003                         dev_err(&pdev->dev, "Could not set PCI cache "
5004                                "line size\n");
5005                         goto err_write_cacheline;
5006                 }
5007         }
5008 #endif
5009
5010
5011         /* Configure DMA attributes. */
5012         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
5013                 pci_using_dac = 1;
5014                 err = pci_set_consistent_dma_mask(pdev,
5015                                                   DMA_64BIT_MASK);
5016                 if (err < 0) {
5017                         dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5018                                "for consistent allocations\n");
5019                         goto err_out_free_res;
5020                 }
5021
5022         } else {
5023                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
5024                 if (err) {
5025                         dev_err(&pdev->dev, "No usable DMA configuration, "
5026                                "aborting.\n");
5027                         goto err_out_free_res;
5028                 }
5029                 pci_using_dac = 0;
5030         }
5031
5032         casreg_len = pci_resource_len(pdev, 0);
5033
5034         cp = netdev_priv(dev);
5035         cp->pdev = pdev;
5036 #if 1
5037         /* A value of 0 indicates we never explicitly set it */
5038         cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5039 #endif
5040         cp->dev = dev;
5041         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5042           cassini_debug;
5043
5044         cp->link_transition = LINK_TRANSITION_UNKNOWN;
5045         cp->link_transition_jiffies_valid = 0;
5046
5047         spin_lock_init(&cp->lock);
5048         spin_lock_init(&cp->rx_inuse_lock);
5049         spin_lock_init(&cp->rx_spare_lock);
5050         for (i = 0; i < N_TX_RINGS; i++) {
5051                 spin_lock_init(&cp->stat_lock[i]);
5052                 spin_lock_init(&cp->tx_lock[i]);
5053         }
5054         spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5055         mutex_init(&cp->pm_mutex);
5056
5057         init_timer(&cp->link_timer);
5058         cp->link_timer.function = cas_link_timer;
5059         cp->link_timer.data = (unsigned long) cp;
5060
5061 #if 1
5062         /* Just in case the implementation of atomic operations
5063          * change so that an explicit initialization is necessary.
5064          */
5065         atomic_set(&cp->reset_task_pending, 0);
5066         atomic_set(&cp->reset_task_pending_all, 0);
5067         atomic_set(&cp->reset_task_pending_spare, 0);
5068         atomic_set(&cp->reset_task_pending_mtu, 0);
5069 #endif
5070         INIT_WORK(&cp->reset_task, cas_reset_task);
5071
5072         /* Default link parameters */
5073         if (link_mode >= 0 && link_mode <= 6)
5074                 cp->link_cntl = link_modes[link_mode];
5075         else
5076                 cp->link_cntl = BMCR_ANENABLE;
5077         cp->lstate = link_down;
5078         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5079         netif_carrier_off(cp->dev);
5080         cp->timer_ticks = 0;
5081
5082         /* give us access to cassini registers */
5083         cp->regs = pci_iomap(pdev, 0, casreg_len);
5084         if (!cp->regs) {
5085                 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
5086                 goto err_out_free_res;
5087         }
5088         cp->casreg_len = casreg_len;
5089
5090         pci_save_state(pdev);
5091         cas_check_pci_invariants(cp);
5092         cas_hard_reset(cp);
5093         cas_reset(cp, 0);
5094         if (cas_check_invariants(cp))
5095                 goto err_out_iounmap;
5096
5097         cp->init_block = (struct cas_init_block *)
5098                 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5099                                      &cp->block_dvma);
5100         if (!cp->init_block) {
5101                 dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n");
5102                 goto err_out_iounmap;
5103         }
5104
5105         for (i = 0; i < N_TX_RINGS; i++)
5106                 cp->init_txds[i] = cp->init_block->txds[i];
5107
5108         for (i = 0; i < N_RX_DESC_RINGS; i++)
5109                 cp->init_rxds[i] = cp->init_block->rxds[i];
5110
5111         for (i = 0; i < N_RX_COMP_RINGS; i++)
5112                 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5113
5114         for (i = 0; i < N_RX_FLOWS; i++)
5115                 skb_queue_head_init(&cp->rx_flows[i]);
5116
5117         dev->open = cas_open;
5118         dev->stop = cas_close;
5119         dev->hard_start_xmit = cas_start_xmit;
5120         dev->get_stats = cas_get_stats;
5121         dev->set_multicast_list = cas_set_multicast;
5122         dev->do_ioctl = cas_ioctl;
5123         dev->ethtool_ops = &cas_ethtool_ops;
5124         dev->tx_timeout = cas_tx_timeout;
5125         dev->watchdog_timeo = CAS_TX_TIMEOUT;
5126         dev->change_mtu = cas_change_mtu;
5127 #ifdef USE_NAPI
5128         netif_napi_add(dev, &cp->napi, cas_poll, 64);
5129 #endif
5130 #ifdef CONFIG_NET_POLL_CONTROLLER
5131         dev->poll_controller = cas_netpoll;
5132 #endif
5133         dev->irq = pdev->irq;
5134         dev->dma = 0;
5135
5136         /* Cassini features. */
5137         if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5138                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5139
5140         if (pci_using_dac)
5141                 dev->features |= NETIF_F_HIGHDMA;
5142
5143         if (register_netdev(dev)) {
5144                 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5145                 goto err_out_free_consistent;
5146         }
5147
5148         i = readl(cp->regs + REG_BIM_CFG);
5149         printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5150                "Ethernet[%d] %s\n",  dev->name,
5151                (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5152                (i & BIM_CFG_32BIT) ? "32" : "64",
5153                (i & BIM_CFG_66MHZ) ? "66" : "33",
5154                (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5155                print_mac(mac, dev->dev_addr));
5156
5157         pci_set_drvdata(pdev, dev);
5158         cp->hw_running = 1;
5159         cas_entropy_reset(cp);
5160         cas_phy_init(cp);
5161         cas_begin_auto_negotiation(cp, NULL);
5162         return 0;
5163
5164 err_out_free_consistent:
5165         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5166                             cp->init_block, cp->block_dvma);
5167
5168 err_out_iounmap:
5169         mutex_lock(&cp->pm_mutex);
5170         if (cp->hw_running)
5171                 cas_shutdown(cp);
5172         mutex_unlock(&cp->pm_mutex);
5173
5174         pci_iounmap(pdev, cp->regs);
5175
5176
5177 err_out_free_res:
5178         pci_release_regions(pdev);
5179
5180 err_write_cacheline:
5181         /* Try to restore it in case the error occured after we
5182          * set it.
5183          */
5184         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5185
5186 err_out_free_netdev:
5187         free_netdev(dev);
5188
5189 err_out_disable_pdev:
5190         pci_disable_device(pdev);
5191         pci_set_drvdata(pdev, NULL);
5192         return -ENODEV;
5193 }
5194
5195 static void __devexit cas_remove_one(struct pci_dev *pdev)
5196 {
5197         struct net_device *dev = pci_get_drvdata(pdev);
5198         struct cas *cp;
5199         if (!dev)
5200                 return;
5201
5202         cp = netdev_priv(dev);
5203         unregister_netdev(dev);
5204
5205         mutex_lock(&cp->pm_mutex);
5206         flush_scheduled_work();
5207         if (cp->hw_running)
5208                 cas_shutdown(cp);
5209         mutex_unlock(&cp->pm_mutex);
5210
5211 #if 1
5212         if (cp->orig_cacheline_size) {
5213                 /* Restore the cache line size if we had modified
5214                  * it.
5215                  */
5216                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5217                                       cp->orig_cacheline_size);
5218         }
5219 #endif
5220         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5221                             cp->init_block, cp->block_dvma);
5222         pci_iounmap(pdev, cp->regs);
5223         free_netdev(dev);
5224         pci_release_regions(pdev);
5225         pci_disable_device(pdev);
5226         pci_set_drvdata(pdev, NULL);
5227 }
5228
5229 #ifdef CONFIG_PM
5230 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5231 {
5232         struct net_device *dev = pci_get_drvdata(pdev);
5233         struct cas *cp = netdev_priv(dev);
5234         unsigned long flags;
5235
5236         mutex_lock(&cp->pm_mutex);
5237
5238         /* If the driver is opened, we stop the DMA */
5239         if (cp->opened) {
5240                 netif_device_detach(dev);
5241
5242                 cas_lock_all_save(cp, flags);
5243
5244                 /* We can set the second arg of cas_reset to 0
5245                  * because on resume, we'll call cas_init_hw with
5246                  * its second arg set so that autonegotiation is
5247                  * restarted.
5248                  */
5249                 cas_reset(cp, 0);
5250                 cas_clean_rings(cp);
5251                 cas_unlock_all_restore(cp, flags);
5252         }
5253
5254         if (cp->hw_running)
5255                 cas_shutdown(cp);
5256         mutex_unlock(&cp->pm_mutex);
5257
5258         return 0;
5259 }
5260
5261 static int cas_resume(struct pci_dev *pdev)
5262 {
5263         struct net_device *dev = pci_get_drvdata(pdev);
5264         struct cas *cp = netdev_priv(dev);
5265
5266         printk(KERN_INFO "%s: resuming\n", dev->name);
5267
5268         mutex_lock(&cp->pm_mutex);
5269         cas_hard_reset(cp);
5270         if (cp->opened) {
5271                 unsigned long flags;
5272                 cas_lock_all_save(cp, flags);
5273                 cas_reset(cp, 0);
5274                 cp->hw_running = 1;
5275                 cas_clean_rings(cp);
5276                 cas_init_hw(cp, 1);
5277                 cas_unlock_all_restore(cp, flags);
5278
5279                 netif_device_attach(dev);
5280         }
5281         mutex_unlock(&cp->pm_mutex);
5282         return 0;
5283 }
5284 #endif /* CONFIG_PM */
5285
5286 static struct pci_driver cas_driver = {
5287         .name           = DRV_MODULE_NAME,
5288         .id_table       = cas_pci_tbl,
5289         .probe          = cas_init_one,
5290         .remove         = __devexit_p(cas_remove_one),
5291 #ifdef CONFIG_PM
5292         .suspend        = cas_suspend,
5293         .resume         = cas_resume
5294 #endif
5295 };
5296
5297 static int __init cas_init(void)
5298 {
5299         if (linkdown_timeout > 0)
5300                 link_transition_timeout = linkdown_timeout * HZ;
5301         else
5302                 link_transition_timeout = 0;
5303
5304         return pci_register_driver(&cas_driver);
5305 }
5306
5307 static void __exit cas_cleanup(void)
5308 {
5309         pci_unregister_driver(&cas_driver);
5310 }
5311
5312 module_init(cas_init);
5313 module_exit(cas_cleanup);