ACPI: Add the reference count to avoid unloading ACPI video bus twice
[linux-2.6.git] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page.
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targetted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.
67  */
68
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/types.h>
73 #include <linux/compiler.h>
74 #include <linux/slab.h>
75 #include <linux/delay.h>
76 #include <linux/init.h>
77 #include <linux/vmalloc.h>
78 #include <linux/ioport.h>
79 #include <linux/pci.h>
80 #include <linux/mm.h>
81 #include <linux/highmem.h>
82 #include <linux/list.h>
83 #include <linux/dma-mapping.h>
84
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/crc32.h>
90 #include <linux/random.h>
91 #include <linux/mii.h>
92 #include <linux/ip.h>
93 #include <linux/tcp.h>
94 #include <linux/mutex.h>
95 #include <linux/firmware.h>
96
97 #include <net/checksum.h>
98
99 #include <asm/atomic.h>
100 #include <asm/system.h>
101 #include <asm/io.h>
102 #include <asm/byteorder.h>
103 #include <asm/uaccess.h>
104
105 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
106 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
107 #define CAS_NCPUS            num_online_cpus()
108
109 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
110 #define USE_NAPI
111 #define cas_skb_release(x)  netif_receive_skb(x)
112 #else
113 #define cas_skb_release(x)  netif_rx(x)
114 #endif
115
116 /* select which firmware to use */
117 #define USE_HP_WORKAROUND
118 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
119 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
120
121 #include "cassini.h"
122
123 #define USE_TX_COMPWB      /* use completion writeback registers */
124 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
125 #define USE_RX_BLANK       /* hw interrupt mitigation */
126 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
127
128 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
129  * also, we need to make cp->lock finer-grained.
130  */
131 #undef  USE_PCI_INTB
132 #undef  USE_PCI_INTC
133 #undef  USE_PCI_INTD
134 #undef  USE_QOS
135
136 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
137
138 /* rx processing options */
139 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
140 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
141 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
142 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
143 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
144
145 #define DRV_MODULE_NAME         "cassini"
146 #define PFX DRV_MODULE_NAME     ": "
147 #define DRV_MODULE_VERSION      "1.6"
148 #define DRV_MODULE_RELDATE      "21 May 2008"
149
150 #define CAS_DEF_MSG_ENABLE        \
151         (NETIF_MSG_DRV          | \
152          NETIF_MSG_PROBE        | \
153          NETIF_MSG_LINK         | \
154          NETIF_MSG_TIMER        | \
155          NETIF_MSG_IFDOWN       | \
156          NETIF_MSG_IFUP         | \
157          NETIF_MSG_RX_ERR       | \
158          NETIF_MSG_TX_ERR)
159
160 /* length of time before we decide the hardware is borked,
161  * and dev->tx_timeout() should be called to fix the problem
162  */
163 #define CAS_TX_TIMEOUT                  (HZ)
164 #define CAS_LINK_TIMEOUT                (22*HZ/10)
165 #define CAS_LINK_FAST_TIMEOUT           (1)
166
167 /* timeout values for state changing. these specify the number
168  * of 10us delays to be used before giving up.
169  */
170 #define STOP_TRIES_PHY 1000
171 #define STOP_TRIES     5000
172
173 /* specify a minimum frame size to deal with some fifo issues
174  * max mtu == 2 * page size - ethernet header - 64 - swivel =
175  *            2 * page_size - 0x50
176  */
177 #define CAS_MIN_FRAME                   97
178 #define CAS_1000MB_MIN_FRAME            255
179 #define CAS_MIN_MTU                     60
180 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
181
182 #if 1
183 /*
184  * Eliminate these and use separate atomic counters for each, to
185  * avoid a race condition.
186  */
187 #else
188 #define CAS_RESET_MTU                   1
189 #define CAS_RESET_ALL                   2
190 #define CAS_RESET_SPARE                 3
191 #endif
192
193 static char version[] __devinitdata =
194         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
195
196 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
197 static int link_mode;
198
199 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
200 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
201 MODULE_LICENSE("GPL");
202 MODULE_FIRMWARE("sun/cassini.bin");
203 module_param(cassini_debug, int, 0);
204 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
205 module_param(link_mode, int, 0);
206 MODULE_PARM_DESC(link_mode, "default link mode");
207
208 /*
209  * Work around for a PCS bug in which the link goes down due to the chip
210  * being confused and never showing a link status of "up."
211  */
212 #define DEFAULT_LINKDOWN_TIMEOUT 5
213 /*
214  * Value in seconds, for user input.
215  */
216 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
217 module_param(linkdown_timeout, int, 0);
218 MODULE_PARM_DESC(linkdown_timeout,
219 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
220
221 /*
222  * value in 'ticks' (units used by jiffies). Set when we init the
223  * module because 'HZ' in actually a function call on some flavors of
224  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
225  */
226 static int link_transition_timeout;
227
228
229
230 static u16 link_modes[] __devinitdata = {
231         BMCR_ANENABLE,                   /* 0 : autoneg */
232         0,                               /* 1 : 10bt half duplex */
233         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
234         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
235         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
236         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
237 };
238
239 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
240         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
243           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244         { 0, }
245 };
246
247 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
248
249 static void cas_set_link_modes(struct cas *cp);
250
251 static inline void cas_lock_tx(struct cas *cp)
252 {
253         int i;
254
255         for (i = 0; i < N_TX_RINGS; i++)
256                 spin_lock(&cp->tx_lock[i]);
257 }
258
259 static inline void cas_lock_all(struct cas *cp)
260 {
261         spin_lock_irq(&cp->lock);
262         cas_lock_tx(cp);
263 }
264
265 /* WTZ: QA was finding deadlock problems with the previous
266  * versions after long test runs with multiple cards per machine.
267  * See if replacing cas_lock_all with safer versions helps. The
268  * symptoms QA is reporting match those we'd expect if interrupts
269  * aren't being properly restored, and we fixed a previous deadlock
270  * with similar symptoms by using save/restore versions in other
271  * places.
272  */
273 #define cas_lock_all_save(cp, flags) \
274 do { \
275         struct cas *xxxcp = (cp); \
276         spin_lock_irqsave(&xxxcp->lock, flags); \
277         cas_lock_tx(xxxcp); \
278 } while (0)
279
280 static inline void cas_unlock_tx(struct cas *cp)
281 {
282         int i;
283
284         for (i = N_TX_RINGS; i > 0; i--)
285                 spin_unlock(&cp->tx_lock[i - 1]);
286 }
287
288 static inline void cas_unlock_all(struct cas *cp)
289 {
290         cas_unlock_tx(cp);
291         spin_unlock_irq(&cp->lock);
292 }
293
294 #define cas_unlock_all_restore(cp, flags) \
295 do { \
296         struct cas *xxxcp = (cp); \
297         cas_unlock_tx(xxxcp); \
298         spin_unlock_irqrestore(&xxxcp->lock, flags); \
299 } while (0)
300
301 static void cas_disable_irq(struct cas *cp, const int ring)
302 {
303         /* Make sure we won't get any more interrupts */
304         if (ring == 0) {
305                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
306                 return;
307         }
308
309         /* disable completion interrupts and selectively mask */
310         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
311                 switch (ring) {
312 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
313 #ifdef USE_PCI_INTB
314                 case 1:
315 #endif
316 #ifdef USE_PCI_INTC
317                 case 2:
318 #endif
319 #ifdef USE_PCI_INTD
320                 case 3:
321 #endif
322                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
323                                cp->regs + REG_PLUS_INTRN_MASK(ring));
324                         break;
325 #endif
326                 default:
327                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
328                                REG_PLUS_INTRN_MASK(ring));
329                         break;
330                 }
331         }
332 }
333
334 static inline void cas_mask_intr(struct cas *cp)
335 {
336         int i;
337
338         for (i = 0; i < N_RX_COMP_RINGS; i++)
339                 cas_disable_irq(cp, i);
340 }
341
342 static void cas_enable_irq(struct cas *cp, const int ring)
343 {
344         if (ring == 0) { /* all but TX_DONE */
345                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
346                 return;
347         }
348
349         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
350                 switch (ring) {
351 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
352 #ifdef USE_PCI_INTB
353                 case 1:
354 #endif
355 #ifdef USE_PCI_INTC
356                 case 2:
357 #endif
358 #ifdef USE_PCI_INTD
359                 case 3:
360 #endif
361                         writel(INTRN_MASK_RX_EN, cp->regs +
362                                REG_PLUS_INTRN_MASK(ring));
363                         break;
364 #endif
365                 default:
366                         break;
367                 }
368         }
369 }
370
371 static inline void cas_unmask_intr(struct cas *cp)
372 {
373         int i;
374
375         for (i = 0; i < N_RX_COMP_RINGS; i++)
376                 cas_enable_irq(cp, i);
377 }
378
379 static inline void cas_entropy_gather(struct cas *cp)
380 {
381 #ifdef USE_ENTROPY_DEV
382         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
383                 return;
384
385         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
386                             readl(cp->regs + REG_ENTROPY_IV),
387                             sizeof(uint64_t)*8);
388 #endif
389 }
390
391 static inline void cas_entropy_reset(struct cas *cp)
392 {
393 #ifdef USE_ENTROPY_DEV
394         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
395                 return;
396
397         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
398                cp->regs + REG_BIM_LOCAL_DEV_EN);
399         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
400         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
401
402         /* if we read back 0x0, we don't have an entropy device */
403         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
404                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
405 #endif
406 }
407
408 /* access to the phy. the following assumes that we've initialized the MIF to
409  * be in frame rather than bit-bang mode
410  */
411 static u16 cas_phy_read(struct cas *cp, int reg)
412 {
413         u32 cmd;
414         int limit = STOP_TRIES_PHY;
415
416         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
417         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
418         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
419         cmd |= MIF_FRAME_TURN_AROUND_MSB;
420         writel(cmd, cp->regs + REG_MIF_FRAME);
421
422         /* poll for completion */
423         while (limit-- > 0) {
424                 udelay(10);
425                 cmd = readl(cp->regs + REG_MIF_FRAME);
426                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
427                         return (cmd & MIF_FRAME_DATA_MASK);
428         }
429         return 0xFFFF; /* -1 */
430 }
431
432 static int cas_phy_write(struct cas *cp, int reg, u16 val)
433 {
434         int limit = STOP_TRIES_PHY;
435         u32 cmd;
436
437         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
438         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
439         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
440         cmd |= MIF_FRAME_TURN_AROUND_MSB;
441         cmd |= val & MIF_FRAME_DATA_MASK;
442         writel(cmd, cp->regs + REG_MIF_FRAME);
443
444         /* poll for completion */
445         while (limit-- > 0) {
446                 udelay(10);
447                 cmd = readl(cp->regs + REG_MIF_FRAME);
448                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
449                         return 0;
450         }
451         return -1;
452 }
453
454 static void cas_phy_powerup(struct cas *cp)
455 {
456         u16 ctl = cas_phy_read(cp, MII_BMCR);
457
458         if ((ctl & BMCR_PDOWN) == 0)
459                 return;
460         ctl &= ~BMCR_PDOWN;
461         cas_phy_write(cp, MII_BMCR, ctl);
462 }
463
464 static void cas_phy_powerdown(struct cas *cp)
465 {
466         u16 ctl = cas_phy_read(cp, MII_BMCR);
467
468         if (ctl & BMCR_PDOWN)
469                 return;
470         ctl |= BMCR_PDOWN;
471         cas_phy_write(cp, MII_BMCR, ctl);
472 }
473
474 /* cp->lock held. note: the last put_page will free the buffer */
475 static int cas_page_free(struct cas *cp, cas_page_t *page)
476 {
477         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
478                        PCI_DMA_FROMDEVICE);
479         __free_pages(page->buffer, cp->page_order);
480         kfree(page);
481         return 0;
482 }
483
484 #ifdef RX_COUNT_BUFFERS
485 #define RX_USED_ADD(x, y)       ((x)->used += (y))
486 #define RX_USED_SET(x, y)       ((x)->used  = (y))
487 #else
488 #define RX_USED_ADD(x, y)
489 #define RX_USED_SET(x, y)
490 #endif
491
492 /* local page allocation routines for the receive buffers. jumbo pages
493  * require at least 8K contiguous and 8K aligned buffers.
494  */
495 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
496 {
497         cas_page_t *page;
498
499         page = kmalloc(sizeof(cas_page_t), flags);
500         if (!page)
501                 return NULL;
502
503         INIT_LIST_HEAD(&page->list);
504         RX_USED_SET(page, 0);
505         page->buffer = alloc_pages(flags, cp->page_order);
506         if (!page->buffer)
507                 goto page_err;
508         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
509                                       cp->page_size, PCI_DMA_FROMDEVICE);
510         return page;
511
512 page_err:
513         kfree(page);
514         return NULL;
515 }
516
517 /* initialize spare pool of rx buffers, but allocate during the open */
518 static void cas_spare_init(struct cas *cp)
519 {
520         spin_lock(&cp->rx_inuse_lock);
521         INIT_LIST_HEAD(&cp->rx_inuse_list);
522         spin_unlock(&cp->rx_inuse_lock);
523
524         spin_lock(&cp->rx_spare_lock);
525         INIT_LIST_HEAD(&cp->rx_spare_list);
526         cp->rx_spares_needed = RX_SPARE_COUNT;
527         spin_unlock(&cp->rx_spare_lock);
528 }
529
530 /* used on close. free all the spare buffers. */
531 static void cas_spare_free(struct cas *cp)
532 {
533         struct list_head list, *elem, *tmp;
534
535         /* free spare buffers */
536         INIT_LIST_HEAD(&list);
537         spin_lock(&cp->rx_spare_lock);
538         list_splice_init(&cp->rx_spare_list, &list);
539         spin_unlock(&cp->rx_spare_lock);
540         list_for_each_safe(elem, tmp, &list) {
541                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
542         }
543
544         INIT_LIST_HEAD(&list);
545 #if 1
546         /*
547          * Looks like Adrian had protected this with a different
548          * lock than used everywhere else to manipulate this list.
549          */
550         spin_lock(&cp->rx_inuse_lock);
551         list_splice_init(&cp->rx_inuse_list, &list);
552         spin_unlock(&cp->rx_inuse_lock);
553 #else
554         spin_lock(&cp->rx_spare_lock);
555         list_splice_init(&cp->rx_inuse_list, &list);
556         spin_unlock(&cp->rx_spare_lock);
557 #endif
558         list_for_each_safe(elem, tmp, &list) {
559                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
560         }
561 }
562
563 /* replenish spares if needed */
564 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
565 {
566         struct list_head list, *elem, *tmp;
567         int needed, i;
568
569         /* check inuse list. if we don't need any more free buffers,
570          * just free it
571          */
572
573         /* make a local copy of the list */
574         INIT_LIST_HEAD(&list);
575         spin_lock(&cp->rx_inuse_lock);
576         list_splice_init(&cp->rx_inuse_list, &list);
577         spin_unlock(&cp->rx_inuse_lock);
578
579         list_for_each_safe(elem, tmp, &list) {
580                 cas_page_t *page = list_entry(elem, cas_page_t, list);
581
582                 /*
583                  * With the lockless pagecache, cassini buffering scheme gets
584                  * slightly less accurate: we might find that a page has an
585                  * elevated reference count here, due to a speculative ref,
586                  * and skip it as in-use. Ideally we would be able to reclaim
587                  * it. However this would be such a rare case, it doesn't
588                  * matter too much as we should pick it up the next time round.
589                  *
590                  * Importantly, if we find that the page has a refcount of 1
591                  * here (our refcount), then we know it is definitely not inuse
592                  * so we can reuse it.
593                  */
594                 if (page_count(page->buffer) > 1)
595                         continue;
596
597                 list_del(elem);
598                 spin_lock(&cp->rx_spare_lock);
599                 if (cp->rx_spares_needed > 0) {
600                         list_add(elem, &cp->rx_spare_list);
601                         cp->rx_spares_needed--;
602                         spin_unlock(&cp->rx_spare_lock);
603                 } else {
604                         spin_unlock(&cp->rx_spare_lock);
605                         cas_page_free(cp, page);
606                 }
607         }
608
609         /* put any inuse buffers back on the list */
610         if (!list_empty(&list)) {
611                 spin_lock(&cp->rx_inuse_lock);
612                 list_splice(&list, &cp->rx_inuse_list);
613                 spin_unlock(&cp->rx_inuse_lock);
614         }
615
616         spin_lock(&cp->rx_spare_lock);
617         needed = cp->rx_spares_needed;
618         spin_unlock(&cp->rx_spare_lock);
619         if (!needed)
620                 return;
621
622         /* we still need spares, so try to allocate some */
623         INIT_LIST_HEAD(&list);
624         i = 0;
625         while (i < needed) {
626                 cas_page_t *spare = cas_page_alloc(cp, flags);
627                 if (!spare)
628                         break;
629                 list_add(&spare->list, &list);
630                 i++;
631         }
632
633         spin_lock(&cp->rx_spare_lock);
634         list_splice(&list, &cp->rx_spare_list);
635         cp->rx_spares_needed -= i;
636         spin_unlock(&cp->rx_spare_lock);
637 }
638
639 /* pull a page from the list. */
640 static cas_page_t *cas_page_dequeue(struct cas *cp)
641 {
642         struct list_head *entry;
643         int recover;
644
645         spin_lock(&cp->rx_spare_lock);
646         if (list_empty(&cp->rx_spare_list)) {
647                 /* try to do a quick recovery */
648                 spin_unlock(&cp->rx_spare_lock);
649                 cas_spare_recover(cp, GFP_ATOMIC);
650                 spin_lock(&cp->rx_spare_lock);
651                 if (list_empty(&cp->rx_spare_list)) {
652                         if (netif_msg_rx_err(cp))
653                                 printk(KERN_ERR "%s: no spare buffers "
654                                        "available.\n", cp->dev->name);
655                         spin_unlock(&cp->rx_spare_lock);
656                         return NULL;
657                 }
658         }
659
660         entry = cp->rx_spare_list.next;
661         list_del(entry);
662         recover = ++cp->rx_spares_needed;
663         spin_unlock(&cp->rx_spare_lock);
664
665         /* trigger the timer to do the recovery */
666         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
667 #if 1
668                 atomic_inc(&cp->reset_task_pending);
669                 atomic_inc(&cp->reset_task_pending_spare);
670                 schedule_work(&cp->reset_task);
671 #else
672                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
673                 schedule_work(&cp->reset_task);
674 #endif
675         }
676         return list_entry(entry, cas_page_t, list);
677 }
678
679
680 static void cas_mif_poll(struct cas *cp, const int enable)
681 {
682         u32 cfg;
683
684         cfg  = readl(cp->regs + REG_MIF_CFG);
685         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
686
687         if (cp->phy_type & CAS_PHY_MII_MDIO1)
688                 cfg |= MIF_CFG_PHY_SELECT;
689
690         /* poll and interrupt on link status change. */
691         if (enable) {
692                 cfg |= MIF_CFG_POLL_EN;
693                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
694                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
695         }
696         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
697                cp->regs + REG_MIF_MASK);
698         writel(cfg, cp->regs + REG_MIF_CFG);
699 }
700
701 /* Must be invoked under cp->lock */
702 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
703 {
704         u16 ctl;
705 #if 1
706         int lcntl;
707         int changed = 0;
708         int oldstate = cp->lstate;
709         int link_was_not_down = !(oldstate == link_down);
710 #endif
711         /* Setup link parameters */
712         if (!ep)
713                 goto start_aneg;
714         lcntl = cp->link_cntl;
715         if (ep->autoneg == AUTONEG_ENABLE)
716                 cp->link_cntl = BMCR_ANENABLE;
717         else {
718                 cp->link_cntl = 0;
719                 if (ep->speed == SPEED_100)
720                         cp->link_cntl |= BMCR_SPEED100;
721                 else if (ep->speed == SPEED_1000)
722                         cp->link_cntl |= CAS_BMCR_SPEED1000;
723                 if (ep->duplex == DUPLEX_FULL)
724                         cp->link_cntl |= BMCR_FULLDPLX;
725         }
726 #if 1
727         changed = (lcntl != cp->link_cntl);
728 #endif
729 start_aneg:
730         if (cp->lstate == link_up) {
731                 printk(KERN_INFO "%s: PCS link down.\n",
732                        cp->dev->name);
733         } else {
734                 if (changed) {
735                         printk(KERN_INFO "%s: link configuration changed\n",
736                                cp->dev->name);
737                 }
738         }
739         cp->lstate = link_down;
740         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
741         if (!cp->hw_running)
742                 return;
743 #if 1
744         /*
745          * WTZ: If the old state was link_up, we turn off the carrier
746          * to replicate everything we do elsewhere on a link-down
747          * event when we were already in a link-up state..
748          */
749         if (oldstate == link_up)
750                 netif_carrier_off(cp->dev);
751         if (changed  && link_was_not_down) {
752                 /*
753                  * WTZ: This branch will simply schedule a full reset after
754                  * we explicitly changed link modes in an ioctl. See if this
755                  * fixes the link-problems we were having for forced mode.
756                  */
757                 atomic_inc(&cp->reset_task_pending);
758                 atomic_inc(&cp->reset_task_pending_all);
759                 schedule_work(&cp->reset_task);
760                 cp->timer_ticks = 0;
761                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
762                 return;
763         }
764 #endif
765         if (cp->phy_type & CAS_PHY_SERDES) {
766                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
767
768                 if (cp->link_cntl & BMCR_ANENABLE) {
769                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
770                         cp->lstate = link_aneg;
771                 } else {
772                         if (cp->link_cntl & BMCR_FULLDPLX)
773                                 val |= PCS_MII_CTRL_DUPLEX;
774                         val &= ~PCS_MII_AUTONEG_EN;
775                         cp->lstate = link_force_ok;
776                 }
777                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
778                 writel(val, cp->regs + REG_PCS_MII_CTRL);
779
780         } else {
781                 cas_mif_poll(cp, 0);
782                 ctl = cas_phy_read(cp, MII_BMCR);
783                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
784                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
785                 ctl |= cp->link_cntl;
786                 if (ctl & BMCR_ANENABLE) {
787                         ctl |= BMCR_ANRESTART;
788                         cp->lstate = link_aneg;
789                 } else {
790                         cp->lstate = link_force_ok;
791                 }
792                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
793                 cas_phy_write(cp, MII_BMCR, ctl);
794                 cas_mif_poll(cp, 1);
795         }
796
797         cp->timer_ticks = 0;
798         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
799 }
800
801 /* Must be invoked under cp->lock. */
802 static int cas_reset_mii_phy(struct cas *cp)
803 {
804         int limit = STOP_TRIES_PHY;
805         u16 val;
806
807         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
808         udelay(100);
809         while (--limit) {
810                 val = cas_phy_read(cp, MII_BMCR);
811                 if ((val & BMCR_RESET) == 0)
812                         break;
813                 udelay(10);
814         }
815         return (limit <= 0);
816 }
817
818 static int cas_saturn_firmware_init(struct cas *cp)
819 {
820         const struct firmware *fw;
821         const char fw_name[] = "sun/cassini.bin";
822         int err;
823
824         if (PHY_NS_DP83065 != cp->phy_id)
825                 return 0;
826
827         err = request_firmware(&fw, fw_name, &cp->pdev->dev);
828         if (err) {
829                 printk(KERN_ERR "cassini: Failed to load firmware \"%s\"\n",
830                        fw_name);
831                 return err;
832         }
833         if (fw->size < 2) {
834                 printk(KERN_ERR "cassini: bogus length %zu in \"%s\"\n",
835                        fw->size, fw_name);
836                 err = -EINVAL;
837                 goto out;
838         }
839         cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
840         cp->fw_size = fw->size - 2;
841         cp->fw_data = vmalloc(cp->fw_size);
842         if (!cp->fw_data) {
843                 err = -ENOMEM;
844                 printk(KERN_ERR "cassini: \"%s\" Failed %d\n", fw_name, err);
845                 goto out;
846         }
847         memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
848 out:
849         release_firmware(fw);
850         return err;
851 }
852
853 static void cas_saturn_firmware_load(struct cas *cp)
854 {
855         int i;
856
857         cas_phy_powerdown(cp);
858
859         /* expanded memory access mode */
860         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
861
862         /* pointer configuration for new firmware */
863         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
864         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
865         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
866         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
867         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
868         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
869         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
870         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
871
872         /* download new firmware */
873         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
874         cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
875         for (i = 0; i < cp->fw_size; i++)
876                 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
877
878         /* enable firmware */
879         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
880         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
881 }
882
883
884 /* phy initialization */
885 static void cas_phy_init(struct cas *cp)
886 {
887         u16 val;
888
889         /* if we're in MII/GMII mode, set up phy */
890         if (CAS_PHY_MII(cp->phy_type)) {
891                 writel(PCS_DATAPATH_MODE_MII,
892                        cp->regs + REG_PCS_DATAPATH_MODE);
893
894                 cas_mif_poll(cp, 0);
895                 cas_reset_mii_phy(cp); /* take out of isolate mode */
896
897                 if (PHY_LUCENT_B0 == cp->phy_id) {
898                         /* workaround link up/down issue with lucent */
899                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
900                         cas_phy_write(cp, MII_BMCR, 0x00f1);
901                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
902
903                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
904                         /* workarounds for broadcom phy */
905                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
906                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
907                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
908                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
909                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
910                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
911                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
912                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
913                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
914                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
915                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
916
917                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
918                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
919                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
920                         if (val & 0x0080) {
921                                 /* link workaround */
922                                 cas_phy_write(cp, BROADCOM_MII_REG4,
923                                               val & ~0x0080);
924                         }
925
926                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
927                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
928                                SATURN_PCFG_FSI : 0x0,
929                                cp->regs + REG_SATURN_PCFG);
930
931                         /* load firmware to address 10Mbps auto-negotiation
932                          * issue. NOTE: this will need to be changed if the
933                          * default firmware gets fixed.
934                          */
935                         if (PHY_NS_DP83065 == cp->phy_id) {
936                                 cas_saturn_firmware_load(cp);
937                         }
938                         cas_phy_powerup(cp);
939                 }
940
941                 /* advertise capabilities */
942                 val = cas_phy_read(cp, MII_BMCR);
943                 val &= ~BMCR_ANENABLE;
944                 cas_phy_write(cp, MII_BMCR, val);
945                 udelay(10);
946
947                 cas_phy_write(cp, MII_ADVERTISE,
948                               cas_phy_read(cp, MII_ADVERTISE) |
949                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
950                                ADVERTISE_100HALF | ADVERTISE_100FULL |
951                                CAS_ADVERTISE_PAUSE |
952                                CAS_ADVERTISE_ASYM_PAUSE));
953
954                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
955                         /* make sure that we don't advertise half
956                          * duplex to avoid a chip issue
957                          */
958                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
959                         val &= ~CAS_ADVERTISE_1000HALF;
960                         val |= CAS_ADVERTISE_1000FULL;
961                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
962                 }
963
964         } else {
965                 /* reset pcs for serdes */
966                 u32 val;
967                 int limit;
968
969                 writel(PCS_DATAPATH_MODE_SERDES,
970                        cp->regs + REG_PCS_DATAPATH_MODE);
971
972                 /* enable serdes pins on saturn */
973                 if (cp->cas_flags & CAS_FLAG_SATURN)
974                         writel(0, cp->regs + REG_SATURN_PCFG);
975
976                 /* Reset PCS unit. */
977                 val = readl(cp->regs + REG_PCS_MII_CTRL);
978                 val |= PCS_MII_RESET;
979                 writel(val, cp->regs + REG_PCS_MII_CTRL);
980
981                 limit = STOP_TRIES;
982                 while (--limit > 0) {
983                         udelay(10);
984                         if ((readl(cp->regs + REG_PCS_MII_CTRL) &
985                              PCS_MII_RESET) == 0)
986                                 break;
987                 }
988                 if (limit <= 0)
989                         printk(KERN_WARNING "%s: PCS reset bit would not "
990                                "clear [%08x].\n", cp->dev->name,
991                                readl(cp->regs + REG_PCS_STATE_MACHINE));
992
993                 /* Make sure PCS is disabled while changing advertisement
994                  * configuration.
995                  */
996                 writel(0x0, cp->regs + REG_PCS_CFG);
997
998                 /* Advertise all capabilities except half-duplex. */
999                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
1000                 val &= ~PCS_MII_ADVERT_HD;
1001                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
1002                         PCS_MII_ADVERT_ASYM_PAUSE);
1003                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
1004
1005                 /* enable PCS */
1006                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
1007
1008                 /* pcs workaround: enable sync detect */
1009                 writel(PCS_SERDES_CTRL_SYNCD_EN,
1010                        cp->regs + REG_PCS_SERDES_CTRL);
1011         }
1012 }
1013
1014
1015 static int cas_pcs_link_check(struct cas *cp)
1016 {
1017         u32 stat, state_machine;
1018         int retval = 0;
1019
1020         /* The link status bit latches on zero, so you must
1021          * read it twice in such a case to see a transition
1022          * to the link being up.
1023          */
1024         stat = readl(cp->regs + REG_PCS_MII_STATUS);
1025         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1026                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1027
1028         /* The remote-fault indication is only valid
1029          * when autoneg has completed.
1030          */
1031         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1032                      PCS_MII_STATUS_REMOTE_FAULT)) ==
1033             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
1034                 if (netif_msg_link(cp))
1035                         printk(KERN_INFO "%s: PCS RemoteFault\n",
1036                                cp->dev->name);
1037         }
1038
1039         /* work around link detection issue by querying the PCS state
1040          * machine directly.
1041          */
1042         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1043         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1044                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1045         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1046                 stat |= PCS_MII_STATUS_LINK_STATUS;
1047         }
1048
1049         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1050                 if (cp->lstate != link_up) {
1051                         if (cp->opened) {
1052                                 cp->lstate = link_up;
1053                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1054
1055                                 cas_set_link_modes(cp);
1056                                 netif_carrier_on(cp->dev);
1057                         }
1058                 }
1059         } else if (cp->lstate == link_up) {
1060                 cp->lstate = link_down;
1061                 if (link_transition_timeout != 0 &&
1062                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1063                     !cp->link_transition_jiffies_valid) {
1064                         /*
1065                          * force a reset, as a workaround for the
1066                          * link-failure problem. May want to move this to a
1067                          * point a bit earlier in the sequence. If we had
1068                          * generated a reset a short time ago, we'll wait for
1069                          * the link timer to check the status until a
1070                          * timer expires (link_transistion_jiffies_valid is
1071                          * true when the timer is running.)  Instead of using
1072                          * a system timer, we just do a check whenever the
1073                          * link timer is running - this clears the flag after
1074                          * a suitable delay.
1075                          */
1076                         retval = 1;
1077                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1078                         cp->link_transition_jiffies = jiffies;
1079                         cp->link_transition_jiffies_valid = 1;
1080                 } else {
1081                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1082                 }
1083                 netif_carrier_off(cp->dev);
1084                 if (cp->opened && netif_msg_link(cp)) {
1085                         printk(KERN_INFO "%s: PCS link down.\n",
1086                                cp->dev->name);
1087                 }
1088
1089                 /* Cassini only: if you force a mode, there can be
1090                  * sync problems on link down. to fix that, the following
1091                  * things need to be checked:
1092                  * 1) read serialink state register
1093                  * 2) read pcs status register to verify link down.
1094                  * 3) if link down and serial link == 0x03, then you need
1095                  *    to global reset the chip.
1096                  */
1097                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1098                         /* should check to see if we're in a forced mode */
1099                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1100                         if (stat == 0x03)
1101                                 return 1;
1102                 }
1103         } else if (cp->lstate == link_down) {
1104                 if (link_transition_timeout != 0 &&
1105                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1106                     !cp->link_transition_jiffies_valid) {
1107                         /* force a reset, as a workaround for the
1108                          * link-failure problem.  May want to move
1109                          * this to a point a bit earlier in the
1110                          * sequence.
1111                          */
1112                         retval = 1;
1113                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1114                         cp->link_transition_jiffies = jiffies;
1115                         cp->link_transition_jiffies_valid = 1;
1116                 } else {
1117                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1118                 }
1119         }
1120
1121         return retval;
1122 }
1123
1124 static int cas_pcs_interrupt(struct net_device *dev,
1125                              struct cas *cp, u32 status)
1126 {
1127         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1128
1129         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1130                 return 0;
1131         return cas_pcs_link_check(cp);
1132 }
1133
1134 static int cas_txmac_interrupt(struct net_device *dev,
1135                                struct cas *cp, u32 status)
1136 {
1137         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1138
1139         if (!txmac_stat)
1140                 return 0;
1141
1142         if (netif_msg_intr(cp))
1143                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1144                         cp->dev->name, txmac_stat);
1145
1146         /* Defer timer expiration is quite normal,
1147          * don't even log the event.
1148          */
1149         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1150             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1151                 return 0;
1152
1153         spin_lock(&cp->stat_lock[0]);
1154         if (txmac_stat & MAC_TX_UNDERRUN) {
1155                 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1156                        dev->name);
1157                 cp->net_stats[0].tx_fifo_errors++;
1158         }
1159
1160         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1161                 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1162                        dev->name);
1163                 cp->net_stats[0].tx_errors++;
1164         }
1165
1166         /* The rest are all cases of one of the 16-bit TX
1167          * counters expiring.
1168          */
1169         if (txmac_stat & MAC_TX_COLL_NORMAL)
1170                 cp->net_stats[0].collisions += 0x10000;
1171
1172         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1173                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1174                 cp->net_stats[0].collisions += 0x10000;
1175         }
1176
1177         if (txmac_stat & MAC_TX_COLL_LATE) {
1178                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1179                 cp->net_stats[0].collisions += 0x10000;
1180         }
1181         spin_unlock(&cp->stat_lock[0]);
1182
1183         /* We do not keep track of MAC_TX_COLL_FIRST and
1184          * MAC_TX_PEAK_ATTEMPTS events.
1185          */
1186         return 0;
1187 }
1188
1189 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1190 {
1191         cas_hp_inst_t *inst;
1192         u32 val;
1193         int i;
1194
1195         i = 0;
1196         while ((inst = firmware) && inst->note) {
1197                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1198
1199                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1200                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1201                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1202
1203                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1204                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1205                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1206                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1207                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1208                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1209                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1210                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1211
1212                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1213                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1214                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1215                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1216                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1217                 ++firmware;
1218                 ++i;
1219         }
1220 }
1221
1222 static void cas_init_rx_dma(struct cas *cp)
1223 {
1224         u64 desc_dma = cp->block_dvma;
1225         u32 val;
1226         int i, size;
1227
1228         /* rx free descriptors */
1229         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1230         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1231         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1232         if ((N_RX_DESC_RINGS > 1) &&
1233             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1234                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1235         writel(val, cp->regs + REG_RX_CFG);
1236
1237         val = (unsigned long) cp->init_rxds[0] -
1238                 (unsigned long) cp->init_block;
1239         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1240         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1241         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1242
1243         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1244                 /* rx desc 2 is for IPSEC packets. however,
1245                  * we don't it that for that purpose.
1246                  */
1247                 val = (unsigned long) cp->init_rxds[1] -
1248                         (unsigned long) cp->init_block;
1249                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1250                 writel((desc_dma + val) & 0xffffffff, cp->regs +
1251                        REG_PLUS_RX_DB1_LOW);
1252                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1253                        REG_PLUS_RX_KICK1);
1254         }
1255
1256         /* rx completion registers */
1257         val = (unsigned long) cp->init_rxcs[0] -
1258                 (unsigned long) cp->init_block;
1259         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1260         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1261
1262         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1263                 /* rx comp 2-4 */
1264                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1265                         val = (unsigned long) cp->init_rxcs[i] -
1266                                 (unsigned long) cp->init_block;
1267                         writel((desc_dma + val) >> 32, cp->regs +
1268                                REG_PLUS_RX_CBN_HI(i));
1269                         writel((desc_dma + val) & 0xffffffff, cp->regs +
1270                                REG_PLUS_RX_CBN_LOW(i));
1271                 }
1272         }
1273
1274         /* read selective clear regs to prevent spurious interrupts
1275          * on reset because complete == kick.
1276          * selective clear set up to prevent interrupts on resets
1277          */
1278         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1279         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1280         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1281                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1282                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1283
1284                 /* 2 is different from 3 and 4 */
1285                 if (N_RX_COMP_RINGS > 1)
1286                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1287                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1288
1289                 for (i = 2; i < N_RX_COMP_RINGS; i++)
1290                         writel(INTR_RX_DONE_ALT,
1291                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1292         }
1293
1294         /* set up pause thresholds */
1295         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1296                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1297         val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1298                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1299         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1300
1301         /* zero out dma reassembly buffers */
1302         for (i = 0; i < 64; i++) {
1303                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1304                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1305                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1306                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1307         }
1308
1309         /* make sure address register is 0 for normal operation */
1310         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1311         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1312
1313         /* interrupt mitigation */
1314 #ifdef USE_RX_BLANK
1315         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1316         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1317         writel(val, cp->regs + REG_RX_BLANK);
1318 #else
1319         writel(0x0, cp->regs + REG_RX_BLANK);
1320 #endif
1321
1322         /* interrupt generation as a function of low water marks for
1323          * free desc and completion entries. these are used to trigger
1324          * housekeeping for rx descs. we don't use the free interrupt
1325          * as it's not very useful
1326          */
1327         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1328         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1329         writel(val, cp->regs + REG_RX_AE_THRESH);
1330         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1331                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1332                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1333         }
1334
1335         /* Random early detect registers. useful for congestion avoidance.
1336          * this should be tunable.
1337          */
1338         writel(0x0, cp->regs + REG_RX_RED);
1339
1340         /* receive page sizes. default == 2K (0x800) */
1341         val = 0;
1342         if (cp->page_size == 0x1000)
1343                 val = 0x1;
1344         else if (cp->page_size == 0x2000)
1345                 val = 0x2;
1346         else if (cp->page_size == 0x4000)
1347                 val = 0x3;
1348
1349         /* round mtu + offset. constrain to page size. */
1350         size = cp->dev->mtu + 64;
1351         if (size > cp->page_size)
1352                 size = cp->page_size;
1353
1354         if (size <= 0x400)
1355                 i = 0x0;
1356         else if (size <= 0x800)
1357                 i = 0x1;
1358         else if (size <= 0x1000)
1359                 i = 0x2;
1360         else
1361                 i = 0x3;
1362
1363         cp->mtu_stride = 1 << (i + 10);
1364         val  = CAS_BASE(RX_PAGE_SIZE, val);
1365         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1366         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1367         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1368         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1369
1370         /* enable the header parser if desired */
1371         if (CAS_HP_FIRMWARE == cas_prog_null)
1372                 return;
1373
1374         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1375         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1376         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1377         writel(val, cp->regs + REG_HP_CFG);
1378 }
1379
1380 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1381 {
1382         memset(rxc, 0, sizeof(*rxc));
1383         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1384 }
1385
1386 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1387  * flipping is protected by the fact that the chip will not
1388  * hand back the same page index while it's being processed.
1389  */
1390 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1391 {
1392         cas_page_t *page = cp->rx_pages[1][index];
1393         cas_page_t *new;
1394
1395         if (page_count(page->buffer) == 1)
1396                 return page;
1397
1398         new = cas_page_dequeue(cp);
1399         if (new) {
1400                 spin_lock(&cp->rx_inuse_lock);
1401                 list_add(&page->list, &cp->rx_inuse_list);
1402                 spin_unlock(&cp->rx_inuse_lock);
1403         }
1404         return new;
1405 }
1406
1407 /* this needs to be changed if we actually use the ENC RX DESC ring */
1408 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1409                                  const int index)
1410 {
1411         cas_page_t **page0 = cp->rx_pages[0];
1412         cas_page_t **page1 = cp->rx_pages[1];
1413
1414         /* swap if buffer is in use */
1415         if (page_count(page0[index]->buffer) > 1) {
1416                 cas_page_t *new = cas_page_spare(cp, index);
1417                 if (new) {
1418                         page1[index] = page0[index];
1419                         page0[index] = new;
1420                 }
1421         }
1422         RX_USED_SET(page0[index], 0);
1423         return page0[index];
1424 }
1425
1426 static void cas_clean_rxds(struct cas *cp)
1427 {
1428         /* only clean ring 0 as ring 1 is used for spare buffers */
1429         struct cas_rx_desc *rxd = cp->init_rxds[0];
1430         int i, size;
1431
1432         /* release all rx flows */
1433         for (i = 0; i < N_RX_FLOWS; i++) {
1434                 struct sk_buff *skb;
1435                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1436                         cas_skb_release(skb);
1437                 }
1438         }
1439
1440         /* initialize descriptors */
1441         size = RX_DESC_RINGN_SIZE(0);
1442         for (i = 0; i < size; i++) {
1443                 cas_page_t *page = cas_page_swap(cp, 0, i);
1444                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1445                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1446                                             CAS_BASE(RX_INDEX_RING, 0));
1447         }
1448
1449         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1450         cp->rx_last[0] = 0;
1451         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1452 }
1453
1454 static void cas_clean_rxcs(struct cas *cp)
1455 {
1456         int i, j;
1457
1458         /* take ownership of rx comp descriptors */
1459         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1460         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1461         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1462                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1463                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1464                         cas_rxc_init(rxc + j);
1465                 }
1466         }
1467 }
1468
1469 #if 0
1470 /* When we get a RX fifo overflow, the RX unit is probably hung
1471  * so we do the following.
1472  *
1473  * If any part of the reset goes wrong, we return 1 and that causes the
1474  * whole chip to be reset.
1475  */
1476 static int cas_rxmac_reset(struct cas *cp)
1477 {
1478         struct net_device *dev = cp->dev;
1479         int limit;
1480         u32 val;
1481
1482         /* First, reset MAC RX. */
1483         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1484         for (limit = 0; limit < STOP_TRIES; limit++) {
1485                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1486                         break;
1487                 udelay(10);
1488         }
1489         if (limit == STOP_TRIES) {
1490                 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1491                        "chip.\n", dev->name);
1492                 return 1;
1493         }
1494
1495         /* Second, disable RX DMA. */
1496         writel(0, cp->regs + REG_RX_CFG);
1497         for (limit = 0; limit < STOP_TRIES; limit++) {
1498                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1499                         break;
1500                 udelay(10);
1501         }
1502         if (limit == STOP_TRIES) {
1503                 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1504                        "chip.\n", dev->name);
1505                 return 1;
1506         }
1507
1508         mdelay(5);
1509
1510         /* Execute RX reset command. */
1511         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1512         for (limit = 0; limit < STOP_TRIES; limit++) {
1513                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1514                         break;
1515                 udelay(10);
1516         }
1517         if (limit == STOP_TRIES) {
1518                 printk(KERN_ERR "%s: RX reset command will not execute, "
1519                        "resetting whole chip.\n", dev->name);
1520                 return 1;
1521         }
1522
1523         /* reset driver rx state */
1524         cas_clean_rxds(cp);
1525         cas_clean_rxcs(cp);
1526
1527         /* Now, reprogram the rest of RX unit. */
1528         cas_init_rx_dma(cp);
1529
1530         /* re-enable */
1531         val = readl(cp->regs + REG_RX_CFG);
1532         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1533         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1534         val = readl(cp->regs + REG_MAC_RX_CFG);
1535         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1536         return 0;
1537 }
1538 #endif
1539
1540 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1541                                u32 status)
1542 {
1543         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1544
1545         if (!stat)
1546                 return 0;
1547
1548         if (netif_msg_intr(cp))
1549                 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1550                         cp->dev->name, stat);
1551
1552         /* these are all rollovers */
1553         spin_lock(&cp->stat_lock[0]);
1554         if (stat & MAC_RX_ALIGN_ERR)
1555                 cp->net_stats[0].rx_frame_errors += 0x10000;
1556
1557         if (stat & MAC_RX_CRC_ERR)
1558                 cp->net_stats[0].rx_crc_errors += 0x10000;
1559
1560         if (stat & MAC_RX_LEN_ERR)
1561                 cp->net_stats[0].rx_length_errors += 0x10000;
1562
1563         if (stat & MAC_RX_OVERFLOW) {
1564                 cp->net_stats[0].rx_over_errors++;
1565                 cp->net_stats[0].rx_fifo_errors++;
1566         }
1567
1568         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1569          * events.
1570          */
1571         spin_unlock(&cp->stat_lock[0]);
1572         return 0;
1573 }
1574
1575 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1576                              u32 status)
1577 {
1578         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1579
1580         if (!stat)
1581                 return 0;
1582
1583         if (netif_msg_intr(cp))
1584                 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1585                         cp->dev->name, stat);
1586
1587         /* This interrupt is just for pause frame and pause
1588          * tracking.  It is useful for diagnostics and debug
1589          * but probably by default we will mask these events.
1590          */
1591         if (stat & MAC_CTRL_PAUSE_STATE)
1592                 cp->pause_entered++;
1593
1594         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1595                 cp->pause_last_time_recvd = (stat >> 16);
1596
1597         return 0;
1598 }
1599
1600
1601 /* Must be invoked under cp->lock. */
1602 static inline int cas_mdio_link_not_up(struct cas *cp)
1603 {
1604         u16 val;
1605
1606         switch (cp->lstate) {
1607         case link_force_ret:
1608                 if (netif_msg_link(cp))
1609                         printk(KERN_INFO "%s: Autoneg failed again, keeping"
1610                                 " forced mode\n", cp->dev->name);
1611                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1612                 cp->timer_ticks = 5;
1613                 cp->lstate = link_force_ok;
1614                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1615                 break;
1616
1617         case link_aneg:
1618                 val = cas_phy_read(cp, MII_BMCR);
1619
1620                 /* Try forced modes. we try things in the following order:
1621                  * 1000 full -> 100 full/half -> 10 half
1622                  */
1623                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1624                 val |= BMCR_FULLDPLX;
1625                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1626                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1627                 cas_phy_write(cp, MII_BMCR, val);
1628                 cp->timer_ticks = 5;
1629                 cp->lstate = link_force_try;
1630                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1631                 break;
1632
1633         case link_force_try:
1634                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1635                 val = cas_phy_read(cp, MII_BMCR);
1636                 cp->timer_ticks = 5;
1637                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1638                         val &= ~CAS_BMCR_SPEED1000;
1639                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1640                         cas_phy_write(cp, MII_BMCR, val);
1641                         break;
1642                 }
1643
1644                 if (val & BMCR_SPEED100) {
1645                         if (val & BMCR_FULLDPLX) /* fd failed */
1646                                 val &= ~BMCR_FULLDPLX;
1647                         else { /* 100Mbps failed */
1648                                 val &= ~BMCR_SPEED100;
1649                         }
1650                         cas_phy_write(cp, MII_BMCR, val);
1651                         break;
1652                 }
1653         default:
1654                 break;
1655         }
1656         return 0;
1657 }
1658
1659
1660 /* must be invoked with cp->lock held */
1661 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1662 {
1663         int restart;
1664
1665         if (bmsr & BMSR_LSTATUS) {
1666                 /* Ok, here we got a link. If we had it due to a forced
1667                  * fallback, and we were configured for autoneg, we
1668                  * retry a short autoneg pass. If you know your hub is
1669                  * broken, use ethtool ;)
1670                  */
1671                 if ((cp->lstate == link_force_try) &&
1672                     (cp->link_cntl & BMCR_ANENABLE)) {
1673                         cp->lstate = link_force_ret;
1674                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1675                         cas_mif_poll(cp, 0);
1676                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1677                         cp->timer_ticks = 5;
1678                         if (cp->opened && netif_msg_link(cp))
1679                                 printk(KERN_INFO "%s: Got link after fallback, retrying"
1680                                        " autoneg once...\n", cp->dev->name);
1681                         cas_phy_write(cp, MII_BMCR,
1682                                       cp->link_fcntl | BMCR_ANENABLE |
1683                                       BMCR_ANRESTART);
1684                         cas_mif_poll(cp, 1);
1685
1686                 } else if (cp->lstate != link_up) {
1687                         cp->lstate = link_up;
1688                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1689
1690                         if (cp->opened) {
1691                                 cas_set_link_modes(cp);
1692                                 netif_carrier_on(cp->dev);
1693                         }
1694                 }
1695                 return 0;
1696         }
1697
1698         /* link not up. if the link was previously up, we restart the
1699          * whole process
1700          */
1701         restart = 0;
1702         if (cp->lstate == link_up) {
1703                 cp->lstate = link_down;
1704                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1705
1706                 netif_carrier_off(cp->dev);
1707                 if (cp->opened && netif_msg_link(cp))
1708                         printk(KERN_INFO "%s: Link down\n",
1709                                cp->dev->name);
1710                 restart = 1;
1711
1712         } else if (++cp->timer_ticks > 10)
1713                 cas_mdio_link_not_up(cp);
1714
1715         return restart;
1716 }
1717
1718 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1719                              u32 status)
1720 {
1721         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1722         u16 bmsr;
1723
1724         /* check for a link change */
1725         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1726                 return 0;
1727
1728         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1729         return cas_mii_link_check(cp, bmsr);
1730 }
1731
1732 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1733                              u32 status)
1734 {
1735         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1736
1737         if (!stat)
1738                 return 0;
1739
1740         printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1741                readl(cp->regs + REG_BIM_DIAG));
1742
1743         /* cassini+ has this reserved */
1744         if ((stat & PCI_ERR_BADACK) &&
1745             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1746                 printk("<No ACK64# during ABS64 cycle> ");
1747
1748         if (stat & PCI_ERR_DTRTO)
1749                 printk("<Delayed transaction timeout> ");
1750         if (stat & PCI_ERR_OTHER)
1751                 printk("<other> ");
1752         if (stat & PCI_ERR_BIM_DMA_WRITE)
1753                 printk("<BIM DMA 0 write req> ");
1754         if (stat & PCI_ERR_BIM_DMA_READ)
1755                 printk("<BIM DMA 0 read req> ");
1756         printk("\n");
1757
1758         if (stat & PCI_ERR_OTHER) {
1759                 u16 cfg;
1760
1761                 /* Interrogate PCI config space for the
1762                  * true cause.
1763                  */
1764                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1765                 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1766                        dev->name, cfg);
1767                 if (cfg & PCI_STATUS_PARITY)
1768                         printk(KERN_ERR "%s: PCI parity error detected.\n",
1769                                dev->name);
1770                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1771                         printk(KERN_ERR "%s: PCI target abort.\n",
1772                                dev->name);
1773                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1774                         printk(KERN_ERR "%s: PCI master acks target abort.\n",
1775                                dev->name);
1776                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1777                         printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1778                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1779                         printk(KERN_ERR "%s: PCI system error SERR#.\n",
1780                                dev->name);
1781                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1782                         printk(KERN_ERR "%s: PCI parity error.\n",
1783                                dev->name);
1784
1785                 /* Write the error bits back to clear them. */
1786                 cfg &= (PCI_STATUS_PARITY |
1787                         PCI_STATUS_SIG_TARGET_ABORT |
1788                         PCI_STATUS_REC_TARGET_ABORT |
1789                         PCI_STATUS_REC_MASTER_ABORT |
1790                         PCI_STATUS_SIG_SYSTEM_ERROR |
1791                         PCI_STATUS_DETECTED_PARITY);
1792                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1793         }
1794
1795         /* For all PCI errors, we should reset the chip. */
1796         return 1;
1797 }
1798
1799 /* All non-normal interrupt conditions get serviced here.
1800  * Returns non-zero if we should just exit the interrupt
1801  * handler right now (ie. if we reset the card which invalidates
1802  * all of the other original irq status bits).
1803  */
1804 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1805                             u32 status)
1806 {
1807         if (status & INTR_RX_TAG_ERROR) {
1808                 /* corrupt RX tag framing */
1809                 if (netif_msg_rx_err(cp))
1810                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1811                                 cp->dev->name);
1812                 spin_lock(&cp->stat_lock[0]);
1813                 cp->net_stats[0].rx_errors++;
1814                 spin_unlock(&cp->stat_lock[0]);
1815                 goto do_reset;
1816         }
1817
1818         if (status & INTR_RX_LEN_MISMATCH) {
1819                 /* length mismatch. */
1820                 if (netif_msg_rx_err(cp))
1821                         printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1822                                 cp->dev->name);
1823                 spin_lock(&cp->stat_lock[0]);
1824                 cp->net_stats[0].rx_errors++;
1825                 spin_unlock(&cp->stat_lock[0]);
1826                 goto do_reset;
1827         }
1828
1829         if (status & INTR_PCS_STATUS) {
1830                 if (cas_pcs_interrupt(dev, cp, status))
1831                         goto do_reset;
1832         }
1833
1834         if (status & INTR_TX_MAC_STATUS) {
1835                 if (cas_txmac_interrupt(dev, cp, status))
1836                         goto do_reset;
1837         }
1838
1839         if (status & INTR_RX_MAC_STATUS) {
1840                 if (cas_rxmac_interrupt(dev, cp, status))
1841                         goto do_reset;
1842         }
1843
1844         if (status & INTR_MAC_CTRL_STATUS) {
1845                 if (cas_mac_interrupt(dev, cp, status))
1846                         goto do_reset;
1847         }
1848
1849         if (status & INTR_MIF_STATUS) {
1850                 if (cas_mif_interrupt(dev, cp, status))
1851                         goto do_reset;
1852         }
1853
1854         if (status & INTR_PCI_ERROR_STATUS) {
1855                 if (cas_pci_interrupt(dev, cp, status))
1856                         goto do_reset;
1857         }
1858         return 0;
1859
1860 do_reset:
1861 #if 1
1862         atomic_inc(&cp->reset_task_pending);
1863         atomic_inc(&cp->reset_task_pending_all);
1864         printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1865                dev->name, status);
1866         schedule_work(&cp->reset_task);
1867 #else
1868         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1869         printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1870         schedule_work(&cp->reset_task);
1871 #endif
1872         return 1;
1873 }
1874
1875 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1876  *       determining whether to do a netif_stop/wakeup
1877  */
1878 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1879 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1880 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1881                                   const int len)
1882 {
1883         unsigned long off = addr + len;
1884
1885         if (CAS_TABORT(cp) == 1)
1886                 return 0;
1887         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1888                 return 0;
1889         return TX_TARGET_ABORT_LEN;
1890 }
1891
1892 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1893 {
1894         struct cas_tx_desc *txds;
1895         struct sk_buff **skbs;
1896         struct net_device *dev = cp->dev;
1897         int entry, count;
1898
1899         spin_lock(&cp->tx_lock[ring]);
1900         txds = cp->init_txds[ring];
1901         skbs = cp->tx_skbs[ring];
1902         entry = cp->tx_old[ring];
1903
1904         count = TX_BUFF_COUNT(ring, entry, limit);
1905         while (entry != limit) {
1906                 struct sk_buff *skb = skbs[entry];
1907                 dma_addr_t daddr;
1908                 u32 dlen;
1909                 int frag;
1910
1911                 if (!skb) {
1912                         /* this should never occur */
1913                         entry = TX_DESC_NEXT(ring, entry);
1914                         continue;
1915                 }
1916
1917                 /* however, we might get only a partial skb release. */
1918                 count -= skb_shinfo(skb)->nr_frags +
1919                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1920                 if (count < 0)
1921                         break;
1922
1923                 if (netif_msg_tx_done(cp))
1924                         printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1925                                cp->dev->name, ring, entry);
1926
1927                 skbs[entry] = NULL;
1928                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1929
1930                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1931                         struct cas_tx_desc *txd = txds + entry;
1932
1933                         daddr = le64_to_cpu(txd->buffer);
1934                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1935                                        le64_to_cpu(txd->control));
1936                         pci_unmap_page(cp->pdev, daddr, dlen,
1937                                        PCI_DMA_TODEVICE);
1938                         entry = TX_DESC_NEXT(ring, entry);
1939
1940                         /* tiny buffer may follow */
1941                         if (cp->tx_tiny_use[ring][entry].used) {
1942                                 cp->tx_tiny_use[ring][entry].used = 0;
1943                                 entry = TX_DESC_NEXT(ring, entry);
1944                         }
1945                 }
1946
1947                 spin_lock(&cp->stat_lock[ring]);
1948                 cp->net_stats[ring].tx_packets++;
1949                 cp->net_stats[ring].tx_bytes += skb->len;
1950                 spin_unlock(&cp->stat_lock[ring]);
1951                 dev_kfree_skb_irq(skb);
1952         }
1953         cp->tx_old[ring] = entry;
1954
1955         /* this is wrong for multiple tx rings. the net device needs
1956          * multiple queues for this to do the right thing.  we wait
1957          * for 2*packets to be available when using tiny buffers
1958          */
1959         if (netif_queue_stopped(dev) &&
1960             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1961                 netif_wake_queue(dev);
1962         spin_unlock(&cp->tx_lock[ring]);
1963 }
1964
1965 static void cas_tx(struct net_device *dev, struct cas *cp,
1966                    u32 status)
1967 {
1968         int limit, ring;
1969 #ifdef USE_TX_COMPWB
1970         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1971 #endif
1972         if (netif_msg_intr(cp))
1973                 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1974                         cp->dev->name, status, (unsigned long long)compwb);
1975         /* process all the rings */
1976         for (ring = 0; ring < N_TX_RINGS; ring++) {
1977 #ifdef USE_TX_COMPWB
1978                 /* use the completion writeback registers */
1979                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1980                         CAS_VAL(TX_COMPWB_LSB, compwb);
1981                 compwb = TX_COMPWB_NEXT(compwb);
1982 #else
1983                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1984 #endif
1985                 if (cp->tx_old[ring] != limit)
1986                         cas_tx_ringN(cp, ring, limit);
1987         }
1988 }
1989
1990
1991 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1992                               int entry, const u64 *words,
1993                               struct sk_buff **skbref)
1994 {
1995         int dlen, hlen, len, i, alloclen;
1996         int off, swivel = RX_SWIVEL_OFF_VAL;
1997         struct cas_page *page;
1998         struct sk_buff *skb;
1999         void *addr, *crcaddr;
2000         __sum16 csum;
2001         char *p;
2002
2003         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
2004         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
2005         len  = hlen + dlen;
2006
2007         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
2008                 alloclen = len;
2009         else
2010                 alloclen = max(hlen, RX_COPY_MIN);
2011
2012         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
2013         if (skb == NULL)
2014                 return -1;
2015
2016         *skbref = skb;
2017         skb_reserve(skb, swivel);
2018
2019         p = skb->data;
2020         addr = crcaddr = NULL;
2021         if (hlen) { /* always copy header pages */
2022                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2023                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2024                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
2025                         swivel;
2026
2027                 i = hlen;
2028                 if (!dlen) /* attach FCS */
2029                         i += cp->crc_size;
2030                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2031                                     PCI_DMA_FROMDEVICE);
2032                 addr = cas_page_map(page->buffer);
2033                 memcpy(p, addr + off, i);
2034                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2035                                     PCI_DMA_FROMDEVICE);
2036                 cas_page_unmap(addr);
2037                 RX_USED_ADD(page, 0x100);
2038                 p += hlen;
2039                 swivel = 0;
2040         }
2041
2042
2043         if (alloclen < (hlen + dlen)) {
2044                 skb_frag_t *frag = skb_shinfo(skb)->frags;
2045
2046                 /* normal or jumbo packets. we use frags */
2047                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2048                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2049                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2050
2051                 hlen = min(cp->page_size - off, dlen);
2052                 if (hlen < 0) {
2053                         if (netif_msg_rx_err(cp)) {
2054                                 printk(KERN_DEBUG "%s: rx page overflow: "
2055                                        "%d\n", cp->dev->name, hlen);
2056                         }
2057                         dev_kfree_skb_irq(skb);
2058                         return -1;
2059                 }
2060                 i = hlen;
2061                 if (i == dlen)  /* attach FCS */
2062                         i += cp->crc_size;
2063                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2064                                     PCI_DMA_FROMDEVICE);
2065
2066                 /* make sure we always copy a header */
2067                 swivel = 0;
2068                 if (p == (char *) skb->data) { /* not split */
2069                         addr = cas_page_map(page->buffer);
2070                         memcpy(p, addr + off, RX_COPY_MIN);
2071                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2072                                         PCI_DMA_FROMDEVICE);
2073                         cas_page_unmap(addr);
2074                         off += RX_COPY_MIN;
2075                         swivel = RX_COPY_MIN;
2076                         RX_USED_ADD(page, cp->mtu_stride);
2077                 } else {
2078                         RX_USED_ADD(page, hlen);
2079                 }
2080                 skb_put(skb, alloclen);
2081
2082                 skb_shinfo(skb)->nr_frags++;
2083                 skb->data_len += hlen - swivel;
2084                 skb->truesize += hlen - swivel;
2085                 skb->len      += hlen - swivel;
2086
2087                 get_page(page->buffer);
2088                 frag->page = page->buffer;
2089                 frag->page_offset = off;
2090                 frag->size = hlen - swivel;
2091
2092                 /* any more data? */
2093                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2094                         hlen = dlen;
2095                         off = 0;
2096
2097                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2098                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2099                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2100                                             hlen + cp->crc_size,
2101                                             PCI_DMA_FROMDEVICE);
2102                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2103                                             hlen + cp->crc_size,
2104                                             PCI_DMA_FROMDEVICE);
2105
2106                         skb_shinfo(skb)->nr_frags++;
2107                         skb->data_len += hlen;
2108                         skb->len      += hlen;
2109                         frag++;
2110
2111                         get_page(page->buffer);
2112                         frag->page = page->buffer;
2113                         frag->page_offset = 0;
2114                         frag->size = hlen;
2115                         RX_USED_ADD(page, hlen + cp->crc_size);
2116                 }
2117
2118                 if (cp->crc_size) {
2119                         addr = cas_page_map(page->buffer);
2120                         crcaddr  = addr + off + hlen;
2121                 }
2122
2123         } else {
2124                 /* copying packet */
2125                 if (!dlen)
2126                         goto end_copy_pkt;
2127
2128                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2129                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2130                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2131                 hlen = min(cp->page_size - off, dlen);
2132                 if (hlen < 0) {
2133                         if (netif_msg_rx_err(cp)) {
2134                                 printk(KERN_DEBUG "%s: rx page overflow: "
2135                                        "%d\n", cp->dev->name, hlen);
2136                         }
2137                         dev_kfree_skb_irq(skb);
2138                         return -1;
2139                 }
2140                 i = hlen;
2141                 if (i == dlen) /* attach FCS */
2142                         i += cp->crc_size;
2143                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2144                                     PCI_DMA_FROMDEVICE);
2145                 addr = cas_page_map(page->buffer);
2146                 memcpy(p, addr + off, i);
2147                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2148                                     PCI_DMA_FROMDEVICE);
2149                 cas_page_unmap(addr);
2150                 if (p == (char *) skb->data) /* not split */
2151                         RX_USED_ADD(page, cp->mtu_stride);
2152                 else
2153                         RX_USED_ADD(page, i);
2154
2155                 /* any more data? */
2156                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2157                         p += hlen;
2158                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2159                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2160                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2161                                             dlen + cp->crc_size,
2162                                             PCI_DMA_FROMDEVICE);
2163                         addr = cas_page_map(page->buffer);
2164                         memcpy(p, addr, dlen + cp->crc_size);
2165                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2166                                             dlen + cp->crc_size,
2167                                             PCI_DMA_FROMDEVICE);
2168                         cas_page_unmap(addr);
2169                         RX_USED_ADD(page, dlen + cp->crc_size);
2170                 }
2171 end_copy_pkt:
2172                 if (cp->crc_size) {
2173                         addr    = NULL;
2174                         crcaddr = skb->data + alloclen;
2175                 }
2176                 skb_put(skb, alloclen);
2177         }
2178
2179         csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2180         if (cp->crc_size) {
2181                 /* checksum includes FCS. strip it out. */
2182                 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2183                                               csum_unfold(csum)));
2184                 if (addr)
2185                         cas_page_unmap(addr);
2186         }
2187         skb->protocol = eth_type_trans(skb, cp->dev);
2188         if (skb->protocol == htons(ETH_P_IP)) {
2189                 skb->csum = csum_unfold(~csum);
2190                 skb->ip_summed = CHECKSUM_COMPLETE;
2191         } else
2192                 skb->ip_summed = CHECKSUM_NONE;
2193         return len;
2194 }
2195
2196
2197 /* we can handle up to 64 rx flows at a time. we do the same thing
2198  * as nonreassm except that we batch up the buffers.
2199  * NOTE: we currently just treat each flow as a bunch of packets that
2200  *       we pass up. a better way would be to coalesce the packets
2201  *       into a jumbo packet. to do that, we need to do the following:
2202  *       1) the first packet will have a clean split between header and
2203  *          data. save both.
2204  *       2) each time the next flow packet comes in, extend the
2205  *          data length and merge the checksums.
2206  *       3) on flow release, fix up the header.
2207  *       4) make sure the higher layer doesn't care.
2208  * because packets get coalesced, we shouldn't run into fragment count
2209  * issues.
2210  */
2211 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2212                                    struct sk_buff *skb)
2213 {
2214         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2215         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2216
2217         /* this is protected at a higher layer, so no need to
2218          * do any additional locking here. stick the buffer
2219          * at the end.
2220          */
2221         __skb_queue_tail(flow, skb);
2222         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2223                 while ((skb = __skb_dequeue(flow))) {
2224                         cas_skb_release(skb);
2225                 }
2226         }
2227 }
2228
2229 /* put rx descriptor back on ring. if a buffer is in use by a higher
2230  * layer, this will need to put in a replacement.
2231  */
2232 static void cas_post_page(struct cas *cp, const int ring, const int index)
2233 {
2234         cas_page_t *new;
2235         int entry;
2236
2237         entry = cp->rx_old[ring];
2238
2239         new = cas_page_swap(cp, ring, index);
2240         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2241         cp->init_rxds[ring][entry].index  =
2242                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2243                             CAS_BASE(RX_INDEX_RING, ring));
2244
2245         entry = RX_DESC_ENTRY(ring, entry + 1);
2246         cp->rx_old[ring] = entry;
2247
2248         if (entry % 4)
2249                 return;
2250
2251         if (ring == 0)
2252                 writel(entry, cp->regs + REG_RX_KICK);
2253         else if ((N_RX_DESC_RINGS > 1) &&
2254                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2255                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2256 }
2257
2258
2259 /* only when things are bad */
2260 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2261 {
2262         unsigned int entry, last, count, released;
2263         int cluster;
2264         cas_page_t **page = cp->rx_pages[ring];
2265
2266         entry = cp->rx_old[ring];
2267
2268         if (netif_msg_intr(cp))
2269                 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2270                        cp->dev->name, ring, entry);
2271
2272         cluster = -1;
2273         count = entry & 0x3;
2274         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2275         released = 0;
2276         while (entry != last) {
2277                 /* make a new buffer if it's still in use */
2278                 if (page_count(page[entry]->buffer) > 1) {
2279                         cas_page_t *new = cas_page_dequeue(cp);
2280                         if (!new) {
2281                                 /* let the timer know that we need to
2282                                  * do this again
2283                                  */
2284                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2285                                 if (!timer_pending(&cp->link_timer))
2286                                         mod_timer(&cp->link_timer, jiffies +
2287                                                   CAS_LINK_FAST_TIMEOUT);
2288                                 cp->rx_old[ring]  = entry;
2289                                 cp->rx_last[ring] = num ? num - released : 0;
2290                                 return -ENOMEM;
2291                         }
2292                         spin_lock(&cp->rx_inuse_lock);
2293                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2294                         spin_unlock(&cp->rx_inuse_lock);
2295                         cp->init_rxds[ring][entry].buffer =
2296                                 cpu_to_le64(new->dma_addr);
2297                         page[entry] = new;
2298
2299                 }
2300
2301                 if (++count == 4) {
2302                         cluster = entry;
2303                         count = 0;
2304                 }
2305                 released++;
2306                 entry = RX_DESC_ENTRY(ring, entry + 1);
2307         }
2308         cp->rx_old[ring] = entry;
2309
2310         if (cluster < 0)
2311                 return 0;
2312
2313         if (ring == 0)
2314                 writel(cluster, cp->regs + REG_RX_KICK);
2315         else if ((N_RX_DESC_RINGS > 1) &&
2316                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2317                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2318         return 0;
2319 }
2320
2321
2322 /* process a completion ring. packets are set up in three basic ways:
2323  * small packets: should be copied header + data in single buffer.
2324  * large packets: header and data in a single buffer.
2325  * split packets: header in a separate buffer from data.
2326  *                data may be in multiple pages. data may be > 256
2327  *                bytes but in a single page.
2328  *
2329  * NOTE: RX page posting is done in this routine as well. while there's
2330  *       the capability of using multiple RX completion rings, it isn't
2331  *       really worthwhile due to the fact that the page posting will
2332  *       force serialization on the single descriptor ring.
2333  */
2334 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2335 {
2336         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2337         int entry, drops;
2338         int npackets = 0;
2339
2340         if (netif_msg_intr(cp))
2341                 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2342                        cp->dev->name, ring,
2343                        readl(cp->regs + REG_RX_COMP_HEAD),
2344                        cp->rx_new[ring]);
2345
2346         entry = cp->rx_new[ring];
2347         drops = 0;
2348         while (1) {
2349                 struct cas_rx_comp *rxc = rxcs + entry;
2350                 struct sk_buff *uninitialized_var(skb);
2351                 int type, len;
2352                 u64 words[4];
2353                 int i, dring;
2354
2355                 words[0] = le64_to_cpu(rxc->word1);
2356                 words[1] = le64_to_cpu(rxc->word2);
2357                 words[2] = le64_to_cpu(rxc->word3);
2358                 words[3] = le64_to_cpu(rxc->word4);
2359
2360                 /* don't touch if still owned by hw */
2361                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2362                 if (type == 0)
2363                         break;
2364
2365                 /* hw hasn't cleared the zero bit yet */
2366                 if (words[3] & RX_COMP4_ZERO) {
2367                         break;
2368                 }
2369
2370                 /* get info on the packet */
2371                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2372                         spin_lock(&cp->stat_lock[ring]);
2373                         cp->net_stats[ring].rx_errors++;
2374                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2375                                 cp->net_stats[ring].rx_length_errors++;
2376                         if (words[3] & RX_COMP4_BAD)
2377                                 cp->net_stats[ring].rx_crc_errors++;
2378                         spin_unlock(&cp->stat_lock[ring]);
2379
2380                         /* We'll just return it to Cassini. */
2381                 drop_it:
2382                         spin_lock(&cp->stat_lock[ring]);
2383                         ++cp->net_stats[ring].rx_dropped;
2384                         spin_unlock(&cp->stat_lock[ring]);
2385                         goto next;
2386                 }
2387
2388                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2389                 if (len < 0) {
2390                         ++drops;
2391                         goto drop_it;
2392                 }
2393
2394                 /* see if it's a flow re-assembly or not. the driver
2395                  * itself handles release back up.
2396                  */
2397                 if (RX_DONT_BATCH || (type == 0x2)) {
2398                         /* non-reassm: these always get released */
2399                         cas_skb_release(skb);
2400                 } else {
2401                         cas_rx_flow_pkt(cp, words, skb);
2402                 }
2403
2404                 spin_lock(&cp->stat_lock[ring]);
2405                 cp->net_stats[ring].rx_packets++;
2406                 cp->net_stats[ring].rx_bytes += len;
2407                 spin_unlock(&cp->stat_lock[ring]);
2408
2409         next:
2410                 npackets++;
2411
2412                 /* should it be released? */
2413                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2414                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2415                         dring = CAS_VAL(RX_INDEX_RING, i);
2416                         i = CAS_VAL(RX_INDEX_NUM, i);
2417                         cas_post_page(cp, dring, i);
2418                 }
2419
2420                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2421                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2422                         dring = CAS_VAL(RX_INDEX_RING, i);
2423                         i = CAS_VAL(RX_INDEX_NUM, i);
2424                         cas_post_page(cp, dring, i);
2425                 }
2426
2427                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2428                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2429                         dring = CAS_VAL(RX_INDEX_RING, i);
2430                         i = CAS_VAL(RX_INDEX_NUM, i);
2431                         cas_post_page(cp, dring, i);
2432                 }
2433
2434                 /* skip to the next entry */
2435                 entry = RX_COMP_ENTRY(ring, entry + 1 +
2436                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2437 #ifdef USE_NAPI
2438                 if (budget && (npackets >= budget))
2439                         break;
2440 #endif
2441         }
2442         cp->rx_new[ring] = entry;
2443
2444         if (drops)
2445                 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2446                        cp->dev->name);
2447         return npackets;
2448 }
2449
2450
2451 /* put completion entries back on the ring */
2452 static void cas_post_rxcs_ringN(struct net_device *dev,
2453                                 struct cas *cp, int ring)
2454 {
2455         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2456         int last, entry;
2457
2458         last = cp->rx_cur[ring];
2459         entry = cp->rx_new[ring];
2460         if (netif_msg_intr(cp))
2461                 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2462                        dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2463                        entry);
2464
2465         /* zero and re-mark descriptors */
2466         while (last != entry) {
2467                 cas_rxc_init(rxc + last);
2468                 last = RX_COMP_ENTRY(ring, last + 1);
2469         }
2470         cp->rx_cur[ring] = last;
2471
2472         if (ring == 0)
2473                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2474         else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2475                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2476 }
2477
2478
2479
2480 /* cassini can use all four PCI interrupts for the completion ring.
2481  * rings 3 and 4 are identical
2482  */
2483 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2484 static inline void cas_handle_irqN(struct net_device *dev,
2485                                    struct cas *cp, const u32 status,
2486                                    const int ring)
2487 {
2488         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2489                 cas_post_rxcs_ringN(dev, cp, ring);
2490 }
2491
2492 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2493 {
2494         struct net_device *dev = dev_id;
2495         struct cas *cp = netdev_priv(dev);
2496         unsigned long flags;
2497         int ring;
2498         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2499
2500         /* check for shared irq */
2501         if (status == 0)
2502                 return IRQ_NONE;
2503
2504         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2505         spin_lock_irqsave(&cp->lock, flags);
2506         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2507 #ifdef USE_NAPI
2508                 cas_mask_intr(cp);
2509                 napi_schedule(&cp->napi);
2510 #else
2511                 cas_rx_ringN(cp, ring, 0);
2512 #endif
2513                 status &= ~INTR_RX_DONE_ALT;
2514         }
2515
2516         if (status)
2517                 cas_handle_irqN(dev, cp, status, ring);
2518         spin_unlock_irqrestore(&cp->lock, flags);
2519         return IRQ_HANDLED;
2520 }
2521 #endif
2522
2523 #ifdef USE_PCI_INTB
2524 /* everything but rx packets */
2525 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2526 {
2527         if (status & INTR_RX_BUF_UNAVAIL_1) {
2528                 /* Frame arrived, no free RX buffers available.
2529                  * NOTE: we can get this on a link transition. */
2530                 cas_post_rxds_ringN(cp, 1, 0);
2531                 spin_lock(&cp->stat_lock[1]);
2532                 cp->net_stats[1].rx_dropped++;
2533                 spin_unlock(&cp->stat_lock[1]);
2534         }
2535
2536         if (status & INTR_RX_BUF_AE_1)
2537                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2538                                     RX_AE_FREEN_VAL(1));
2539
2540         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2541                 cas_post_rxcs_ringN(cp, 1);
2542 }
2543
2544 /* ring 2 handles a few more events than 3 and 4 */
2545 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2546 {
2547         struct net_device *dev = dev_id;
2548         struct cas *cp = netdev_priv(dev);
2549         unsigned long flags;
2550         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2551
2552         /* check for shared interrupt */
2553         if (status == 0)
2554                 return IRQ_NONE;
2555
2556         spin_lock_irqsave(&cp->lock, flags);
2557         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2558 #ifdef USE_NAPI
2559                 cas_mask_intr(cp);
2560                 napi_schedule(&cp->napi);
2561 #else
2562                 cas_rx_ringN(cp, 1, 0);
2563 #endif
2564                 status &= ~INTR_RX_DONE_ALT;
2565         }
2566         if (status)
2567                 cas_handle_irq1(cp, status);
2568         spin_unlock_irqrestore(&cp->lock, flags);
2569         return IRQ_HANDLED;
2570 }
2571 #endif
2572
2573 static inline void cas_handle_irq(struct net_device *dev,
2574                                   struct cas *cp, const u32 status)
2575 {
2576         /* housekeeping interrupts */
2577         if (status & INTR_ERROR_MASK)
2578                 cas_abnormal_irq(dev, cp, status);
2579
2580         if (status & INTR_RX_BUF_UNAVAIL) {
2581                 /* Frame arrived, no free RX buffers available.
2582                  * NOTE: we can get this on a link transition.
2583                  */
2584                 cas_post_rxds_ringN(cp, 0, 0);
2585                 spin_lock(&cp->stat_lock[0]);
2586                 cp->net_stats[0].rx_dropped++;
2587                 spin_unlock(&cp->stat_lock[0]);
2588         } else if (status & INTR_RX_BUF_AE) {
2589                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2590                                     RX_AE_FREEN_VAL(0));
2591         }
2592
2593         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2594                 cas_post_rxcs_ringN(dev, cp, 0);
2595 }
2596
2597 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2598 {
2599         struct net_device *dev = dev_id;
2600         struct cas *cp = netdev_priv(dev);
2601         unsigned long flags;
2602         u32 status = readl(cp->regs + REG_INTR_STATUS);
2603
2604         if (status == 0)
2605                 return IRQ_NONE;
2606
2607         spin_lock_irqsave(&cp->lock, flags);
2608         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2609                 cas_tx(dev, cp, status);
2610                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2611         }
2612
2613         if (status & INTR_RX_DONE) {
2614 #ifdef USE_NAPI
2615                 cas_mask_intr(cp);
2616                 napi_schedule(&cp->napi);
2617 #else
2618                 cas_rx_ringN(cp, 0, 0);
2619 #endif
2620                 status &= ~INTR_RX_DONE;
2621         }
2622
2623         if (status)
2624                 cas_handle_irq(dev, cp, status);
2625         spin_unlock_irqrestore(&cp->lock, flags);
2626         return IRQ_HANDLED;
2627 }
2628
2629
2630 #ifdef USE_NAPI
2631 static int cas_poll(struct napi_struct *napi, int budget)
2632 {
2633         struct cas *cp = container_of(napi, struct cas, napi);
2634         struct net_device *dev = cp->dev;
2635         int i, enable_intr, credits;
2636         u32 status = readl(cp->regs + REG_INTR_STATUS);
2637         unsigned long flags;
2638
2639         spin_lock_irqsave(&cp->lock, flags);
2640         cas_tx(dev, cp, status);
2641         spin_unlock_irqrestore(&cp->lock, flags);
2642
2643         /* NAPI rx packets. we spread the credits across all of the
2644          * rxc rings
2645          *
2646          * to make sure we're fair with the work we loop through each
2647          * ring N_RX_COMP_RING times with a request of
2648          * budget / N_RX_COMP_RINGS
2649          */
2650         enable_intr = 1;
2651         credits = 0;
2652         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2653                 int j;
2654                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2655                         credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2656                         if (credits >= budget) {
2657                                 enable_intr = 0;
2658                                 goto rx_comp;
2659                         }
2660                 }
2661         }
2662
2663 rx_comp:
2664         /* final rx completion */
2665         spin_lock_irqsave(&cp->lock, flags);
2666         if (status)
2667                 cas_handle_irq(dev, cp, status);
2668
2669 #ifdef USE_PCI_INTB
2670         if (N_RX_COMP_RINGS > 1) {
2671                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2672                 if (status)
2673                         cas_handle_irq1(dev, cp, status);
2674         }
2675 #endif
2676
2677 #ifdef USE_PCI_INTC
2678         if (N_RX_COMP_RINGS > 2) {
2679                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2680                 if (status)
2681                         cas_handle_irqN(dev, cp, status, 2);
2682         }
2683 #endif
2684
2685 #ifdef USE_PCI_INTD
2686         if (N_RX_COMP_RINGS > 3) {
2687                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2688                 if (status)
2689                         cas_handle_irqN(dev, cp, status, 3);
2690         }
2691 #endif
2692         spin_unlock_irqrestore(&cp->lock, flags);
2693         if (enable_intr) {
2694                 napi_complete(napi);
2695                 cas_unmask_intr(cp);
2696         }
2697         return credits;
2698 }
2699 #endif
2700
2701 #ifdef CONFIG_NET_POLL_CONTROLLER
2702 static void cas_netpoll(struct net_device *dev)
2703 {
2704         struct cas *cp = netdev_priv(dev);
2705
2706         cas_disable_irq(cp, 0);
2707         cas_interrupt(cp->pdev->irq, dev);
2708         cas_enable_irq(cp, 0);
2709
2710 #ifdef USE_PCI_INTB
2711         if (N_RX_COMP_RINGS > 1) {
2712                 /* cas_interrupt1(); */
2713         }
2714 #endif
2715 #ifdef USE_PCI_INTC
2716         if (N_RX_COMP_RINGS > 2) {
2717                 /* cas_interruptN(); */
2718         }
2719 #endif
2720 #ifdef USE_PCI_INTD
2721         if (N_RX_COMP_RINGS > 3) {
2722                 /* cas_interruptN(); */
2723         }
2724 #endif
2725 }
2726 #endif
2727
2728 static void cas_tx_timeout(struct net_device *dev)
2729 {
2730         struct cas *cp = netdev_priv(dev);
2731
2732         printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2733         if (!cp->hw_running) {
2734                 printk("%s: hrm.. hw not running!\n", dev->name);
2735                 return;
2736         }
2737
2738         printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2739                dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2740
2741         printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2742                dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2743
2744         printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2745                "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2746                dev->name,
2747                readl(cp->regs + REG_TX_CFG),
2748                readl(cp->regs + REG_MAC_TX_STATUS),
2749                readl(cp->regs + REG_MAC_TX_CFG),
2750                readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2751                readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2752                readl(cp->regs + REG_TX_FIFO_READ_PTR),
2753                readl(cp->regs + REG_TX_SM_1),
2754                readl(cp->regs + REG_TX_SM_2));
2755
2756         printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2757                dev->name,
2758                readl(cp->regs + REG_RX_CFG),
2759                readl(cp->regs + REG_MAC_RX_STATUS),
2760                readl(cp->regs + REG_MAC_RX_CFG));
2761
2762         printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2763                dev->name,
2764                readl(cp->regs + REG_HP_STATE_MACHINE),
2765                readl(cp->regs + REG_HP_STATUS0),
2766                readl(cp->regs + REG_HP_STATUS1),
2767                readl(cp->regs + REG_HP_STATUS2));
2768
2769 #if 1
2770         atomic_inc(&cp->reset_task_pending);
2771         atomic_inc(&cp->reset_task_pending_all);
2772         schedule_work(&cp->reset_task);
2773 #else
2774         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2775         schedule_work(&cp->reset_task);
2776 #endif
2777 }
2778
2779 static inline int cas_intme(int ring, int entry)
2780 {
2781         /* Algorithm: IRQ every 1/2 of descriptors. */
2782         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2783                 return 1;
2784         return 0;
2785 }
2786
2787
2788 static void cas_write_txd(struct cas *cp, int ring, int entry,
2789                           dma_addr_t mapping, int len, u64 ctrl, int last)
2790 {
2791         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2792
2793         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2794         if (cas_intme(ring, entry))
2795                 ctrl |= TX_DESC_INTME;
2796         if (last)
2797                 ctrl |= TX_DESC_EOF;
2798         txd->control = cpu_to_le64(ctrl);
2799         txd->buffer = cpu_to_le64(mapping);
2800 }
2801
2802 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2803                                 const int entry)
2804 {
2805         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2806 }
2807
2808 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2809                                      const int entry, const int tentry)
2810 {
2811         cp->tx_tiny_use[ring][tentry].nbufs++;
2812         cp->tx_tiny_use[ring][entry].used = 1;
2813         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2814 }
2815
2816 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2817                                     struct sk_buff *skb)
2818 {
2819         struct net_device *dev = cp->dev;
2820         int entry, nr_frags, frag, tabort, tentry;
2821         dma_addr_t mapping;
2822         unsigned long flags;
2823         u64 ctrl;
2824         u32 len;
2825
2826         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2827
2828         /* This is a hard error, log it. */
2829         if (TX_BUFFS_AVAIL(cp, ring) <=
2830             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2831                 netif_stop_queue(dev);
2832                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2833                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2834                        "queue awake!\n", dev->name);
2835                 return 1;
2836         }
2837
2838         ctrl = 0;
2839         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2840                 const u64 csum_start_off = skb_transport_offset(skb);
2841                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2842
2843                 ctrl =  TX_DESC_CSUM_EN |
2844                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2845                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2846         }
2847
2848         entry = cp->tx_new[ring];
2849         cp->tx_skbs[ring][entry] = skb;
2850
2851         nr_frags = skb_shinfo(skb)->nr_frags;
2852         len = skb_headlen(skb);
2853         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2854                                offset_in_page(skb->data), len,
2855                                PCI_DMA_TODEVICE);
2856
2857         tentry = entry;
2858         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2859         if (unlikely(tabort)) {
2860                 /* NOTE: len is always >  tabort */
2861                 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2862                               ctrl | TX_DESC_SOF, 0);
2863                 entry = TX_DESC_NEXT(ring, entry);
2864
2865                 skb_copy_from_linear_data_offset(skb, len - tabort,
2866                               tx_tiny_buf(cp, ring, entry), tabort);
2867                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2868                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2869                               (nr_frags == 0));
2870         } else {
2871                 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2872                               TX_DESC_SOF, (nr_frags == 0));
2873         }
2874         entry = TX_DESC_NEXT(ring, entry);
2875
2876         for (frag = 0; frag < nr_frags; frag++) {
2877                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2878
2879                 len = fragp->size;
2880                 mapping = pci_map_page(cp->pdev, fragp->page,
2881                                        fragp->page_offset, len,
2882                                        PCI_DMA_TODEVICE);
2883
2884                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2885                 if (unlikely(tabort)) {
2886                         void *addr;
2887
2888                         /* NOTE: len is always > tabort */
2889                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2890                                       ctrl, 0);
2891                         entry = TX_DESC_NEXT(ring, entry);
2892
2893                         addr = cas_page_map(fragp->page);
2894                         memcpy(tx_tiny_buf(cp, ring, entry),
2895                                addr + fragp->page_offset + len - tabort,
2896                                tabort);
2897                         cas_page_unmap(addr);
2898                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2899                         len     = tabort;
2900                 }
2901
2902                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2903                               (frag + 1 == nr_frags));
2904                 entry = TX_DESC_NEXT(ring, entry);
2905         }
2906
2907         cp->tx_new[ring] = entry;
2908         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2909                 netif_stop_queue(dev);
2910
2911         if (netif_msg_tx_queued(cp))
2912                 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2913                        "avail %d\n",
2914                        dev->name, ring, entry, skb->len,
2915                        TX_BUFFS_AVAIL(cp, ring));
2916         writel(entry, cp->regs + REG_TX_KICKN(ring));
2917         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2918         return 0;
2919 }
2920
2921 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2922 {
2923         struct cas *cp = netdev_priv(dev);
2924
2925         /* this is only used as a load-balancing hint, so it doesn't
2926          * need to be SMP safe
2927          */
2928         static int ring;
2929
2930         if (skb_padto(skb, cp->min_frame_size))
2931                 return 0;
2932
2933         /* XXX: we need some higher-level QoS hooks to steer packets to
2934          *      individual queues.
2935          */
2936         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2937                 return 1;
2938         dev->trans_start = jiffies;
2939         return 0;
2940 }
2941
2942 static void cas_init_tx_dma(struct cas *cp)
2943 {
2944         u64 desc_dma = cp->block_dvma;
2945         unsigned long off;
2946         u32 val;
2947         int i;
2948
2949         /* set up tx completion writeback registers. must be 8-byte aligned */
2950 #ifdef USE_TX_COMPWB
2951         off = offsetof(struct cas_init_block, tx_compwb);
2952         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2953         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2954 #endif
2955
2956         /* enable completion writebacks, enable paced mode,
2957          * disable read pipe, and disable pre-interrupt compwbs
2958          */
2959         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2960                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2961                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2962                 TX_CFG_INTR_COMPWB_DIS;
2963
2964         /* write out tx ring info and tx desc bases */
2965         for (i = 0; i < MAX_TX_RINGS; i++) {
2966                 off = (unsigned long) cp->init_txds[i] -
2967                         (unsigned long) cp->init_block;
2968
2969                 val |= CAS_TX_RINGN_BASE(i);
2970                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2971                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2972                        REG_TX_DBN_LOW(i));
2973                 /* don't zero out the kick register here as the system
2974                  * will wedge
2975                  */
2976         }
2977         writel(val, cp->regs + REG_TX_CFG);
2978
2979         /* program max burst sizes. these numbers should be different
2980          * if doing QoS.
2981          */
2982 #ifdef USE_QOS
2983         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2984         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2985         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2986         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2987 #else
2988         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2989         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2990         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2991         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2992 #endif
2993 }
2994
2995 /* Must be invoked under cp->lock. */
2996 static inline void cas_init_dma(struct cas *cp)
2997 {
2998         cas_init_tx_dma(cp);
2999         cas_init_rx_dma(cp);
3000 }
3001
3002 /* Must be invoked under cp->lock. */
3003 static u32 cas_setup_multicast(struct cas *cp)
3004 {
3005         u32 rxcfg = 0;
3006         int i;
3007
3008         if (cp->dev->flags & IFF_PROMISC) {
3009                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
3010
3011         } else if (cp->dev->flags & IFF_ALLMULTI) {
3012                 for (i=0; i < 16; i++)
3013                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
3014                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3015
3016         } else {
3017                 u16 hash_table[16];
3018                 u32 crc;
3019                 struct dev_mc_list *dmi = cp->dev->mc_list;
3020                 int i;
3021
3022                 /* use the alternate mac address registers for the
3023                  * first 15 multicast addresses
3024                  */
3025                 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
3026                         if (!dmi) {
3027                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
3028                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
3029                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
3030                                 continue;
3031                         }
3032                         writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
3033                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
3034                         writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
3035                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
3036                         writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
3037                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
3038                         dmi = dmi->next;
3039                 }
3040
3041                 /* use hw hash table for the next series of
3042                  * multicast addresses
3043                  */
3044                 memset(hash_table, 0, sizeof(hash_table));
3045                 while (dmi) {
3046                         crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3047                         crc >>= 24;
3048                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3049                         dmi = dmi->next;
3050                 }
3051                 for (i=0; i < 16; i++)
3052                         writel(hash_table[i], cp->regs +
3053                                REG_MAC_HASH_TABLEN(i));
3054                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3055         }
3056
3057         return rxcfg;
3058 }
3059
3060 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3061 static void cas_clear_mac_err(struct cas *cp)
3062 {
3063         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3064         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3065         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3066         writel(0, cp->regs + REG_MAC_COLL_LATE);
3067         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3068         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3069         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3070         writel(0, cp->regs + REG_MAC_LEN_ERR);
3071         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3072         writel(0, cp->regs + REG_MAC_FCS_ERR);
3073         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3074 }
3075
3076
3077 static void cas_mac_reset(struct cas *cp)
3078 {
3079         int i;
3080
3081         /* do both TX and RX reset */
3082         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3083         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3084
3085         /* wait for TX */
3086         i = STOP_TRIES;
3087         while (i-- > 0) {
3088                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3089                         break;
3090                 udelay(10);
3091         }
3092
3093         /* wait for RX */
3094         i = STOP_TRIES;
3095         while (i-- > 0) {
3096                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3097                         break;
3098                 udelay(10);
3099         }
3100
3101         if (readl(cp->regs + REG_MAC_TX_RESET) |
3102             readl(cp->regs + REG_MAC_RX_RESET))
3103                 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3104                        cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3105                        readl(cp->regs + REG_MAC_RX_RESET),
3106                        readl(cp->regs + REG_MAC_STATE_MACHINE));
3107 }
3108
3109
3110 /* Must be invoked under cp->lock. */
3111 static void cas_init_mac(struct cas *cp)
3112 {
3113         unsigned char *e = &cp->dev->dev_addr[0];
3114         int i;
3115 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3116         u32 rxcfg;
3117 #endif
3118         cas_mac_reset(cp);
3119
3120         /* setup core arbitration weight register */
3121         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3122
3123         /* XXX Use pci_dma_burst_advice() */
3124 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3125         /* set the infinite burst register for chips that don't have
3126          * pci issues.
3127          */
3128         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3129                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3130 #endif
3131
3132         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3133
3134         writel(0x00, cp->regs + REG_MAC_IPG0);
3135         writel(0x08, cp->regs + REG_MAC_IPG1);
3136         writel(0x04, cp->regs + REG_MAC_IPG2);
3137
3138         /* change later for 802.3z */
3139         writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3140
3141         /* min frame + FCS */
3142         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3143
3144         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3145          * specify the maximum frame size to prevent RX tag errors on
3146          * oversized frames.
3147          */
3148         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3149                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3150                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3151                cp->regs + REG_MAC_FRAMESIZE_MAX);
3152
3153         /* NOTE: crc_size is used as a surrogate for half-duplex.
3154          * workaround saturn half-duplex issue by increasing preamble
3155          * size to 65 bytes.
3156          */
3157         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3158                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3159         else
3160                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3161         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3162         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3163         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3164
3165         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3166
3167         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3168         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3169         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3170         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3171         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3172
3173         /* setup mac address in perfect filter array */
3174         for (i = 0; i < 45; i++)
3175                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3176
3177         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3178         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3179         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3180
3181         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3182         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3183         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3184
3185 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3186         cp->mac_rx_cfg = cas_setup_multicast(cp);
3187 #else
3188         /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3189          * a writel does not seem to be necessary because Cassini
3190          * seems to preserve the configuration when we do the reset.
3191          * If the chip is in trouble, though, it is not clear if we
3192          * can really count on this behavior. cas_set_multicast uses
3193          * spin_lock_irqsave, but we are called only in cas_init_hw and
3194          * cas_init_hw is protected by cas_lock_all, which calls
3195          * spin_lock_irq (so it doesn't need to save the flags, and
3196          * we should be OK for the writel, as that is the only
3197          * difference).
3198          */
3199         cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3200         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3201 #endif
3202         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3203         cas_clear_mac_err(cp);
3204         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3205
3206         /* Setup MAC interrupts.  We want to get all of the interesting
3207          * counter expiration events, but we do not want to hear about
3208          * normal rx/tx as the DMA engine tells us that.
3209          */
3210         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3211         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3212
3213         /* Don't enable even the PAUSE interrupts for now, we
3214          * make no use of those events other than to record them.
3215          */
3216         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3217 }
3218
3219 /* Must be invoked under cp->lock. */
3220 static void cas_init_pause_thresholds(struct cas *cp)
3221 {
3222         /* Calculate pause thresholds.  Setting the OFF threshold to the
3223          * full RX fifo size effectively disables PAUSE generation
3224          */
3225         if (cp->rx_fifo_size <= (2 * 1024)) {
3226                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3227         } else {
3228                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3229                 if (max_frame * 3 > cp->rx_fifo_size) {
3230                         cp->rx_pause_off = 7104;
3231                         cp->rx_pause_on  = 960;
3232                 } else {
3233                         int off = (cp->rx_fifo_size - (max_frame * 2));
3234                         int on = off - max_frame;
3235                         cp->rx_pause_off = off;
3236                         cp->rx_pause_on = on;
3237                 }
3238         }
3239 }
3240
3241 static int cas_vpd_match(const void __iomem *p, const char *str)
3242 {
3243         int len = strlen(str) + 1;
3244         int i;
3245
3246         for (i = 0; i < len; i++) {
3247                 if (readb(p + i) != str[i])
3248                         return 0;
3249         }
3250         return 1;
3251 }
3252
3253
3254 /* get the mac address by reading the vpd information in the rom.
3255  * also get the phy type and determine if there's an entropy generator.
3256  * NOTE: this is a bit convoluted for the following reasons:
3257  *  1) vpd info has order-dependent mac addresses for multinic cards
3258  *  2) the only way to determine the nic order is to use the slot
3259  *     number.
3260  *  3) fiber cards don't have bridges, so their slot numbers don't
3261  *     mean anything.
3262  *  4) we don't actually know we have a fiber card until after
3263  *     the mac addresses are parsed.
3264  */
3265 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3266                             const int offset)
3267 {
3268         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3269         void __iomem *base, *kstart;
3270         int i, len;
3271         int found = 0;
3272 #define VPD_FOUND_MAC        0x01
3273 #define VPD_FOUND_PHY        0x02
3274
3275         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3276         int mac_off  = 0;
3277
3278         /* give us access to the PROM */
3279         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3280                cp->regs + REG_BIM_LOCAL_DEV_EN);
3281
3282         /* check for an expansion rom */
3283         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3284                 goto use_random_mac_addr;
3285
3286         /* search for beginning of vpd */
3287         base = NULL;
3288         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3289                 /* check for PCIR */
3290                 if ((readb(p + i + 0) == 0x50) &&
3291                     (readb(p + i + 1) == 0x43) &&
3292                     (readb(p + i + 2) == 0x49) &&
3293                     (readb(p + i + 3) == 0x52)) {
3294                         base = p + (readb(p + i + 8) |
3295                                     (readb(p + i + 9) << 8));
3296                         break;
3297                 }
3298         }
3299
3300         if (!base || (readb(base) != 0x82))
3301                 goto use_random_mac_addr;
3302
3303         i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3304         while (i < EXPANSION_ROM_SIZE) {
3305                 if (readb(base + i) != 0x90) /* no vpd found */
3306                         goto use_random_mac_addr;
3307
3308                 /* found a vpd field */
3309                 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3310
3311                 /* extract keywords */
3312                 kstart = base + i + 3;
3313                 p = kstart;
3314                 while ((p - kstart) < len) {
3315                         int klen = readb(p + 2);
3316                         int j;
3317                         char type;
3318
3319                         p += 3;
3320
3321                         /* look for the following things:
3322                          * -- correct length == 29
3323                          * 3 (type) + 2 (size) +
3324                          * 18 (strlen("local-mac-address") + 1) +
3325                          * 6 (mac addr)
3326                          * -- VPD Instance 'I'
3327                          * -- VPD Type Bytes 'B'
3328                          * -- VPD data length == 6
3329                          * -- property string == local-mac-address
3330                          *
3331                          * -- correct length == 24
3332                          * 3 (type) + 2 (size) +
3333                          * 12 (strlen("entropy-dev") + 1) +
3334                          * 7 (strlen("vms110") + 1)
3335                          * -- VPD Instance 'I'
3336                          * -- VPD Type String 'B'
3337                          * -- VPD data length == 7
3338                          * -- property string == entropy-dev
3339                          *
3340                          * -- correct length == 18
3341                          * 3 (type) + 2 (size) +
3342                          * 9 (strlen("phy-type") + 1) +
3343                          * 4 (strlen("pcs") + 1)
3344                          * -- VPD Instance 'I'
3345                          * -- VPD Type String 'S'
3346                          * -- VPD data length == 4
3347                          * -- property string == phy-type
3348                          *
3349                          * -- correct length == 23
3350                          * 3 (type) + 2 (size) +
3351                          * 14 (strlen("phy-interface") + 1) +
3352                          * 4 (strlen("pcs") + 1)
3353                          * -- VPD Instance 'I'
3354                          * -- VPD Type String 'S'
3355                          * -- VPD data length == 4
3356                          * -- property string == phy-interface
3357                          */
3358                         if (readb(p) != 'I')
3359                                 goto next;
3360
3361                         /* finally, check string and length */
3362                         type = readb(p + 3);
3363                         if (type == 'B') {
3364                                 if ((klen == 29) && readb(p + 4) == 6 &&
3365                                     cas_vpd_match(p + 5,
3366                                                   "local-mac-address")) {
3367                                         if (mac_off++ > offset)
3368                                                 goto next;
3369
3370                                         /* set mac address */
3371                                         for (j = 0; j < 6; j++)
3372                                                 dev_addr[j] =
3373                                                         readb(p + 23 + j);
3374                                         goto found_mac;
3375                                 }
3376                         }
3377
3378                         if (type != 'S')
3379                                 goto next;
3380
3381 #ifdef USE_ENTROPY_DEV
3382                         if ((klen == 24) &&
3383                             cas_vpd_match(p + 5, "entropy-dev") &&
3384                             cas_vpd_match(p + 17, "vms110")) {
3385                                 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3386                                 goto next;
3387                         }
3388 #endif
3389
3390                         if (found & VPD_FOUND_PHY)
3391                                 goto next;
3392
3393                         if ((klen == 18) && readb(p + 4) == 4 &&
3394                             cas_vpd_match(p + 5, "phy-type")) {
3395                                 if (cas_vpd_match(p + 14, "pcs")) {
3396                                         phy_type = CAS_PHY_SERDES;
3397                                         goto found_phy;
3398                                 }
3399                         }
3400
3401                         if ((klen == 23) && readb(p + 4) == 4 &&
3402                             cas_vpd_match(p + 5, "phy-interface")) {
3403                                 if (cas_vpd_match(p + 19, "pcs")) {
3404                                         phy_type = CAS_PHY_SERDES;
3405                                         goto found_phy;
3406                                 }
3407                         }
3408 found_mac:
3409                         found |= VPD_FOUND_MAC;
3410                         goto next;
3411
3412 found_phy:
3413                         found |= VPD_FOUND_PHY;
3414
3415 next:
3416                         p += klen;
3417                 }
3418                 i += len + 3;
3419         }
3420
3421 use_random_mac_addr:
3422         if (found & VPD_FOUND_MAC)
3423                 goto done;
3424
3425         /* Sun MAC prefix then 3 random bytes. */
3426         printk(PFX "MAC address not found in ROM VPD\n");
3427         dev_addr[0] = 0x08;
3428         dev_addr[1] = 0x00;
3429         dev_addr[2] = 0x20;
3430         get_random_bytes(dev_addr + 3, 3);
3431
3432 done:
3433         writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3434         return phy_type;
3435 }
3436
3437 /* check pci invariants */
3438 static void cas_check_pci_invariants(struct cas *cp)
3439 {
3440         struct pci_dev *pdev = cp->pdev;
3441
3442         cp->cas_flags = 0;
3443         if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3444             (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3445                 if (pdev->revision >= CAS_ID_REVPLUS)
3446                         cp->cas_flags |= CAS_FLAG_REG_PLUS;
3447                 if (pdev->revision < CAS_ID_REVPLUS02u)
3448                         cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3449
3450                 /* Original Cassini supports HW CSUM, but it's not
3451                  * enabled by default as it can trigger TX hangs.
3452                  */
3453                 if (pdev->revision < CAS_ID_REV2)
3454                         cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3455         } else {
3456                 /* Only sun has original cassini chips.  */
3457                 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3458
3459                 /* We use a flag because the same phy might be externally
3460                  * connected.
3461                  */
3462                 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3463                     (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3464                         cp->cas_flags |= CAS_FLAG_SATURN;
3465         }
3466 }
3467
3468
3469 static int cas_check_invariants(struct cas *cp)
3470 {
3471         struct pci_dev *pdev = cp->pdev;
3472         u32 cfg;
3473         int i;
3474
3475         /* get page size for rx buffers. */
3476         cp->page_order = 0;
3477 #ifdef USE_PAGE_ORDER
3478         if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3479                 /* see if we can allocate larger pages */
3480                 struct page *page = alloc_pages(GFP_ATOMIC,
3481                                                 CAS_JUMBO_PAGE_SHIFT -
3482                                                 PAGE_SHIFT);
3483                 if (page) {
3484                         __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3485                         cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3486                 } else {
3487                         printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3488                 }
3489         }
3490 #endif
3491         cp->page_size = (PAGE_SIZE << cp->page_order);
3492
3493         /* Fetch the FIFO configurations. */
3494         cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3495         cp->rx_fifo_size = RX_FIFO_SIZE;
3496
3497         /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3498          * they're both connected.
3499          */
3500         cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3501                                         PCI_SLOT(pdev->devfn));
3502         if (cp->phy_type & CAS_PHY_SERDES) {
3503                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3504                 return 0; /* no more checking needed */
3505         }
3506
3507         /* MII */
3508         cfg = readl(cp->regs + REG_MIF_CFG);
3509         if (cfg & MIF_CFG_MDIO_1) {
3510                 cp->phy_type = CAS_PHY_MII_MDIO1;
3511         } else if (cfg & MIF_CFG_MDIO_0) {
3512                 cp->phy_type = CAS_PHY_MII_MDIO0;
3513         }
3514
3515         cas_mif_poll(cp, 0);
3516         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3517
3518         for (i = 0; i < 32; i++) {
3519                 u32 phy_id;
3520                 int j;
3521
3522                 for (j = 0; j < 3; j++) {
3523                         cp->phy_addr = i;
3524                         phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3525                         phy_id |= cas_phy_read(cp, MII_PHYSID2);
3526                         if (phy_id && (phy_id != 0xFFFFFFFF)) {
3527                                 cp->phy_id = phy_id;
3528                                 goto done;
3529                         }
3530                 }
3531         }
3532         printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3533                readl(cp->regs + REG_MIF_STATE_MACHINE));
3534         return -1;
3535
3536 done:
3537         /* see if we can do gigabit */
3538         cfg = cas_phy_read(cp, MII_BMSR);
3539         if ((cfg & CAS_BMSR_1000_EXTEND) &&
3540             cas_phy_read(cp, CAS_MII_1000_EXTEND))
3541                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3542         return 0;
3543 }
3544
3545 /* Must be invoked under cp->lock. */
3546 static inline void cas_start_dma(struct cas *cp)
3547 {
3548         int i;
3549         u32 val;
3550         int txfailed = 0;
3551
3552         /* enable dma */
3553         val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3554         writel(val, cp->regs + REG_TX_CFG);
3555         val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3556         writel(val, cp->regs + REG_RX_CFG);
3557
3558         /* enable the mac */
3559         val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3560         writel(val, cp->regs + REG_MAC_TX_CFG);
3561         val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3562         writel(val, cp->regs + REG_MAC_RX_CFG);
3563
3564         i = STOP_TRIES;
3565         while (i-- > 0) {
3566                 val = readl(cp->regs + REG_MAC_TX_CFG);
3567                 if ((val & MAC_TX_CFG_EN))
3568                         break;
3569                 udelay(10);
3570         }
3571         if (i < 0) txfailed = 1;
3572         i = STOP_TRIES;
3573         while (i-- > 0) {
3574                 val = readl(cp->regs + REG_MAC_RX_CFG);
3575                 if ((val & MAC_RX_CFG_EN)) {
3576                         if (txfailed) {
3577                           printk(KERN_ERR
3578                                  "%s: enabling mac failed [tx:%08x:%08x].\n",
3579                                  cp->dev->name,
3580                                  readl(cp->regs + REG_MIF_STATE_MACHINE),
3581                                  readl(cp->regs + REG_MAC_STATE_MACHINE));
3582                         }
3583                         goto enable_rx_done;
3584                 }
3585                 udelay(10);
3586         }
3587         printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3588                cp->dev->name,
3589                (txfailed? "tx,rx":"rx"),
3590                readl(cp->regs + REG_MIF_STATE_MACHINE),
3591                readl(cp->regs + REG_MAC_STATE_MACHINE));
3592
3593 enable_rx_done:
3594         cas_unmask_intr(cp); /* enable interrupts */
3595         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3596         writel(0, cp->regs + REG_RX_COMP_TAIL);
3597
3598         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3599                 if (N_RX_DESC_RINGS > 1)
3600                         writel(RX_DESC_RINGN_SIZE(1) - 4,
3601                                cp->regs + REG_PLUS_RX_KICK1);
3602
3603                 for (i = 1; i < N_RX_COMP_RINGS; i++)
3604                         writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3605         }
3606 }
3607
3608 /* Must be invoked under cp->lock. */
3609 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3610                                    int *pause)
3611 {
3612         u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3613         *fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3614         *pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3615         if (val & PCS_MII_LPA_ASYM_PAUSE)
3616                 *pause |= 0x10;
3617         *spd = 1000;
3618 }
3619
3620 /* Must be invoked under cp->lock. */
3621 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3622                                    int *pause)
3623 {
3624         u32 val;
3625
3626         *fd = 0;
3627         *spd = 10;
3628         *pause = 0;
3629
3630         /* use GMII registers */
3631         val = cas_phy_read(cp, MII_LPA);
3632         if (val & CAS_LPA_PAUSE)
3633                 *pause = 0x01;
3634
3635         if (val & CAS_LPA_ASYM_PAUSE)
3636                 *pause |= 0x10;
3637
3638         if (val & LPA_DUPLEX)
3639                 *fd = 1;
3640         if (val & LPA_100)
3641                 *spd = 100;
3642
3643         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3644                 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3645                 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3646                         *spd = 1000;
3647                 if (val & CAS_LPA_1000FULL)
3648                         *fd = 1;
3649         }
3650 }
3651
3652 /* A link-up condition has occurred, initialize and enable the
3653  * rest of the chip.
3654  *
3655  * Must be invoked under cp->lock.
3656  */
3657 static void cas_set_link_modes(struct cas *cp)
3658 {
3659         u32 val;
3660         int full_duplex, speed, pause;
3661
3662         full_duplex = 0;
3663         speed = 10;
3664         pause = 0;
3665
3666         if (CAS_PHY_MII(cp->phy_type)) {
3667                 cas_mif_poll(cp, 0);
3668                 val = cas_phy_read(cp, MII_BMCR);
3669                 if (val & BMCR_ANENABLE) {
3670                         cas_read_mii_link_mode(cp, &full_duplex, &speed,
3671                                                &pause);
3672                 } else {
3673                         if (val & BMCR_FULLDPLX)
3674                                 full_duplex = 1;
3675
3676                         if (val & BMCR_SPEED100)
3677                                 speed = 100;
3678                         else if (val & CAS_BMCR_SPEED1000)
3679                                 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3680                                         1000 : 100;
3681                 }
3682                 cas_mif_poll(cp, 1);
3683
3684         } else {
3685                 val = readl(cp->regs + REG_PCS_MII_CTRL);
3686                 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3687                 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3688                         if (val & PCS_MII_CTRL_DUPLEX)
3689                                 full_duplex = 1;
3690                 }
3691         }
3692
3693         if (netif_msg_link(cp))
3694                 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3695                        cp->dev->name, speed, (full_duplex ? "full" : "half"));
3696
3697         val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3698         if (CAS_PHY_MII(cp->phy_type)) {
3699                 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3700                 if (!full_duplex)
3701                         val |= MAC_XIF_DISABLE_ECHO;
3702         }
3703         if (full_duplex)
3704                 val |= MAC_XIF_FDPLX_LED;
3705         if (speed == 1000)
3706                 val |= MAC_XIF_GMII_MODE;
3707         writel(val, cp->regs + REG_MAC_XIF_CFG);
3708
3709         /* deal with carrier and collision detect. */
3710         val = MAC_TX_CFG_IPG_EN;
3711         if (full_duplex) {
3712                 val |= MAC_TX_CFG_IGNORE_CARRIER;
3713                 val |= MAC_TX_CFG_IGNORE_COLL;
3714         } else {
3715 #ifndef USE_CSMA_CD_PROTO
3716                 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3717                 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3718 #endif
3719         }
3720         /* val now set up for REG_MAC_TX_CFG */
3721
3722         /* If gigabit and half-duplex, enable carrier extension
3723          * mode.  increase slot time to 512 bytes as well.
3724          * else, disable it and make sure slot time is 64 bytes.
3725          * also activate checksum bug workaround
3726          */
3727         if ((speed == 1000) && !full_duplex) {
3728                 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3729                        cp->regs + REG_MAC_TX_CFG);
3730
3731                 val = readl(cp->regs + REG_MAC_RX_CFG);
3732                 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3733                 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3734                        cp->regs + REG_MAC_RX_CFG);
3735
3736                 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3737
3738                 cp->crc_size = 4;
3739                 /* minimum size gigabit frame at half duplex */
3740                 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3741
3742         } else {
3743                 writel(val, cp->regs + REG_MAC_TX_CFG);
3744
3745                 /* checksum bug workaround. don't strip FCS when in
3746                  * half-duplex mode
3747                  */
3748                 val = readl(cp->regs + REG_MAC_RX_CFG);
3749                 if (full_duplex) {
3750                         val |= MAC_RX_CFG_STRIP_FCS;
3751                         cp->crc_size = 0;
3752                         cp->min_frame_size = CAS_MIN_MTU;
3753                 } else {
3754                         val &= ~MAC_RX_CFG_STRIP_FCS;
3755                         cp->crc_size = 4;
3756                         cp->min_frame_size = CAS_MIN_FRAME;
3757                 }
3758                 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3759                        cp->regs + REG_MAC_RX_CFG);
3760                 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3761         }
3762
3763         if (netif_msg_link(cp)) {
3764                 if (pause & 0x01) {
3765                         printk(KERN_INFO "%s: Pause is enabled "
3766                                "(rxfifo: %d off: %d on: %d)\n",
3767                                cp->dev->name,
3768                                cp->rx_fifo_size,
3769                                cp->rx_pause_off,
3770                                cp->rx_pause_on);
3771                 } else if (pause & 0x10) {
3772                         printk(KERN_INFO "%s: TX pause enabled\n",
3773                                cp->dev->name);
3774                 } else {
3775                         printk(KERN_INFO "%s: Pause is disabled\n",
3776                                cp->dev->name);
3777                 }
3778         }
3779
3780         val = readl(cp->regs + REG_MAC_CTRL_CFG);
3781         val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3782         if (pause) { /* symmetric or asymmetric pause */
3783                 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3784                 if (pause & 0x01) { /* symmetric pause */
3785                         val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3786                 }
3787         }
3788         writel(val, cp->regs + REG_MAC_CTRL_CFG);
3789         cas_start_dma(cp);
3790 }
3791
3792 /* Must be invoked under cp->lock. */
3793 static void cas_init_hw(struct cas *cp, int restart_link)
3794 {
3795         if (restart_link)
3796                 cas_phy_init(cp);
3797
3798         cas_init_pause_thresholds(cp);
3799         cas_init_mac(cp);
3800         cas_init_dma(cp);
3801
3802         if (restart_link) {
3803                 /* Default aneg parameters */
3804                 cp->timer_ticks = 0;
3805                 cas_begin_auto_negotiation(cp, NULL);
3806         } else if (cp->lstate == link_up) {
3807                 cas_set_link_modes(cp);
3808                 netif_carrier_on(cp->dev);
3809         }
3810 }
3811
3812 /* Must be invoked under cp->lock. on earlier cassini boards,
3813  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3814  * let it settle out, and then restore pci state.
3815  */
3816 static void cas_hard_reset(struct cas *cp)
3817 {
3818         writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3819         udelay(20);
3820         pci_restore_state(cp->pdev);
3821 }
3822
3823
3824 static void cas_global_reset(struct cas *cp, int blkflag)
3825 {
3826         int limit;
3827
3828         /* issue a global reset. don't use RSTOUT. */
3829         if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3830                 /* For PCS, when the blkflag is set, we should set the
3831                  * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3832                  * the last autonegotiation from being cleared.  We'll
3833                  * need some special handling if the chip is set into a
3834                  * loopback mode.
3835                  */
3836                 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3837                        cp->regs + REG_SW_RESET);
3838         } else {
3839                 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3840         }
3841
3842         /* need to wait at least 3ms before polling register */
3843         mdelay(3);
3844
3845         limit = STOP_TRIES;
3846         while (limit-- > 0) {
3847                 u32 val = readl(cp->regs + REG_SW_RESET);
3848                 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3849                         goto done;
3850                 udelay(10);
3851         }
3852         printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3853
3854 done:
3855         /* enable various BIM interrupts */
3856         writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3857                BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3858
3859         /* clear out pci error status mask for handled errors.
3860          * we don't deal with DMA counter overflows as they happen
3861          * all the time.
3862          */
3863         writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3864                                PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3865                                PCI_ERR_BIM_DMA_READ), cp->regs +
3866                REG_PCI_ERR_STATUS_MASK);
3867
3868         /* set up for MII by default to address mac rx reset timeout
3869          * issue
3870          */
3871         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3872 }
3873
3874 static void cas_reset(struct cas *cp, int blkflag)
3875 {
3876         u32 val;
3877
3878         cas_mask_intr(cp);
3879         cas_global_reset(cp, blkflag);
3880         cas_mac_reset(cp);
3881         cas_entropy_reset(cp);
3882
3883         /* disable dma engines. */
3884         val = readl(cp->regs + REG_TX_CFG);
3885         val &= ~TX_CFG_DMA_EN;
3886         writel(val, cp->regs + REG_TX_CFG);
3887
3888         val = readl(cp->regs + REG_RX_CFG);
3889         val &= ~RX_CFG_DMA_EN;
3890         writel(val, cp->regs + REG_RX_CFG);
3891
3892         /* program header parser */
3893         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3894             (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3895                 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3896         } else {
3897                 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3898         }
3899
3900         /* clear out error registers */
3901         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3902         cas_clear_mac_err(cp);
3903         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3904 }
3905
3906 /* Shut down the chip, must be called with pm_mutex held.  */
3907 static void cas_shutdown(struct cas *cp)
3908 {
3909         unsigned long flags;
3910
3911         /* Make us not-running to avoid timers respawning */
3912         cp->hw_running = 0;
3913
3914         del_timer_sync(&cp->link_timer);
3915
3916         /* Stop the reset task */
3917 #if 0
3918         while (atomic_read(&cp->reset_task_pending_mtu) ||
3919                atomic_read(&cp->reset_task_pending_spare) ||
3920                atomic_read(&cp->reset_task_pending_all))
3921                 schedule();
3922
3923 #else
3924         while (atomic_read(&cp->reset_task_pending))
3925                 schedule();
3926 #endif
3927         /* Actually stop the chip */
3928         cas_lock_all_save(cp, flags);
3929         cas_reset(cp, 0);
3930         if (cp->cas_flags & CAS_FLAG_SATURN)
3931                 cas_phy_powerdown(cp);
3932         cas_unlock_all_restore(cp, flags);
3933 }
3934
3935 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3936 {
3937         struct cas *cp = netdev_priv(dev);
3938
3939         if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3940                 return -EINVAL;
3941
3942         dev->mtu = new_mtu;
3943         if (!netif_running(dev) || !netif_device_present(dev))
3944                 return 0;
3945
3946         /* let the reset task handle it */
3947 #if 1
3948         atomic_inc(&cp->reset_task_pending);
3949         if ((cp->phy_type & CAS_PHY_SERDES)) {
3950                 atomic_inc(&cp->reset_task_pending_all);
3951         } else {
3952                 atomic_inc(&cp->reset_task_pending_mtu);
3953         }
3954         schedule_work(&cp->reset_task);
3955 #else
3956         atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3957                    CAS_RESET_ALL : CAS_RESET_MTU);
3958         printk(KERN_ERR "reset called in cas_change_mtu\n");
3959         schedule_work(&cp->reset_task);
3960 #endif
3961
3962         flush_scheduled_work();
3963         return 0;
3964 }
3965
3966 static void cas_clean_txd(struct cas *cp, int ring)
3967 {
3968         struct cas_tx_desc *txd = cp->init_txds[ring];
3969         struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3970         u64 daddr, dlen;
3971         int i, size;
3972
3973         size = TX_DESC_RINGN_SIZE(ring);
3974         for (i = 0; i < size; i++) {
3975                 int frag;
3976
3977                 if (skbs[i] == NULL)
3978                         continue;
3979
3980                 skb = skbs[i];
3981                 skbs[i] = NULL;
3982
3983                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3984                         int ent = i & (size - 1);
3985
3986                         /* first buffer is never a tiny buffer and so
3987                          * needs to be unmapped.
3988                          */
3989                         daddr = le64_to_cpu(txd[ent].buffer);
3990                         dlen  =  CAS_VAL(TX_DESC_BUFLEN,
3991                                          le64_to_cpu(txd[ent].control));
3992                         pci_unmap_page(cp->pdev, daddr, dlen,
3993                                        PCI_DMA_TODEVICE);
3994
3995                         if (frag != skb_shinfo(skb)->nr_frags) {
3996                                 i++;
3997
3998                                 /* next buffer might by a tiny buffer.
3999                                  * skip past it.
4000                                  */
4001                                 ent = i & (size - 1);
4002                                 if (cp->tx_tiny_use[ring][ent].used)
4003                                         i++;
4004                         }
4005                 }
4006                 dev_kfree_skb_any(skb);
4007         }
4008
4009         /* zero out tiny buf usage */
4010         memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
4011 }
4012
4013 /* freed on close */
4014 static inline void cas_free_rx_desc(struct cas *cp, int ring)
4015 {
4016         cas_page_t **page = cp->rx_pages[ring];
4017         int i, size;
4018
4019         size = RX_DESC_RINGN_SIZE(ring);
4020         for (i = 0; i < size; i++) {
4021                 if (page[i]) {
4022                         cas_page_free(cp, page[i]);
4023                         page[i] = NULL;
4024                 }
4025         }
4026 }
4027
4028 static void cas_free_rxds(struct cas *cp)
4029 {
4030         int i;
4031
4032         for (i = 0; i < N_RX_DESC_RINGS; i++)
4033                 cas_free_rx_desc(cp, i);
4034 }
4035
4036 /* Must be invoked under cp->lock. */
4037 static void cas_clean_rings(struct cas *cp)
4038 {
4039         int i;
4040
4041         /* need to clean all tx rings */
4042         memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
4043         memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
4044         for (i = 0; i < N_TX_RINGS; i++)
4045                 cas_clean_txd(cp, i);
4046
4047         /* zero out init block */
4048         memset(cp->init_block, 0, sizeof(struct cas_init_block));
4049         cas_clean_rxds(cp);
4050         cas_clean_rxcs(cp);
4051 }
4052
4053 /* allocated on open */
4054 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4055 {
4056         cas_page_t **page = cp->rx_pages[ring];
4057         int size, i = 0;
4058
4059         size = RX_DESC_RINGN_SIZE(ring);
4060         for (i = 0; i < size; i++) {
4061                 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4062                         return -1;
4063         }
4064         return 0;
4065 }
4066
4067 static int cas_alloc_rxds(struct cas *cp)
4068 {
4069         int i;
4070
4071         for (i = 0; i < N_RX_DESC_RINGS; i++) {
4072                 if (cas_alloc_rx_desc(cp, i) < 0) {
4073                         cas_free_rxds(cp);
4074                         return -1;
4075                 }
4076         }
4077         return 0;
4078 }
4079
4080 static void cas_reset_task(struct work_struct *work)
4081 {
4082         struct cas *cp = container_of(work, struct cas, reset_task);
4083 #if 0
4084         int pending = atomic_read(&cp->reset_task_pending);
4085 #else
4086         int pending_all = atomic_read(&cp->reset_task_pending_all);
4087         int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4088         int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4089
4090         if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4091                 /* We can have more tasks scheduled than actually
4092                  * needed.
4093                  */
4094                 atomic_dec(&cp->reset_task_pending);
4095                 return;
4096         }
4097 #endif
4098         /* The link went down, we reset the ring, but keep
4099          * DMA stopped. Use this function for reset
4100          * on error as well.
4101          */
4102         if (cp->hw_running) {
4103                 unsigned long flags;
4104
4105                 /* Make sure we don't get interrupts or tx packets */
4106                 netif_device_detach(cp->dev);
4107                 cas_lock_all_save(cp, flags);
4108
4109                 if (cp->opened) {
4110                         /* We call cas_spare_recover when we call cas_open.
4111                          * but we do not initialize the lists cas_spare_recover
4112                          * uses until cas_open is called.
4113                          */
4114                         cas_spare_recover(cp, GFP_ATOMIC);
4115                 }
4116 #if 1
4117                 /* test => only pending_spare set */
4118                 if (!pending_all && !pending_mtu)
4119                         goto done;
4120 #else
4121                 if (pending == CAS_RESET_SPARE)
4122                         goto done;
4123 #endif
4124                 /* when pending == CAS_RESET_ALL, the following
4125                  * call to cas_init_hw will restart auto negotiation.
4126                  * Setting the second argument of cas_reset to
4127                  * !(pending == CAS_RESET_ALL) will set this argument
4128                  * to 1 (avoiding reinitializing the PHY for the normal
4129                  * PCS case) when auto negotiation is not restarted.
4130                  */
4131 #if 1
4132                 cas_reset(cp, !(pending_all > 0));
4133                 if (cp->opened)
4134                         cas_clean_rings(cp);
4135                 cas_init_hw(cp, (pending_all > 0));
4136 #else
4137                 cas_reset(cp, !(pending == CAS_RESET_ALL));
4138                 if (cp->opened)
4139                         cas_clean_rings(cp);
4140                 cas_init_hw(cp, pending == CAS_RESET_ALL);
4141 #endif
4142
4143 done:
4144                 cas_unlock_all_restore(cp, flags);
4145                 netif_device_attach(cp->dev);
4146         }
4147 #if 1
4148         atomic_sub(pending_all, &cp->reset_task_pending_all);
4149         atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4150         atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4151         atomic_dec(&cp->reset_task_pending);
4152 #else
4153         atomic_set(&cp->reset_task_pending, 0);
4154 #endif
4155 }
4156
4157 static void cas_link_timer(unsigned long data)
4158 {
4159         struct cas *cp = (struct cas *) data;
4160         int mask, pending = 0, reset = 0;
4161         unsigned long flags;
4162
4163         if (link_transition_timeout != 0 &&
4164             cp->link_transition_jiffies_valid &&
4165             ((jiffies - cp->link_transition_jiffies) >
4166               (link_transition_timeout))) {
4167                 /* One-second counter so link-down workaround doesn't
4168                  * cause resets to occur so fast as to fool the switch
4169                  * into thinking the link is down.
4170                  */
4171                 cp->link_transition_jiffies_valid = 0;
4172         }
4173
4174         if (!cp->hw_running)
4175                 return;
4176
4177         spin_lock_irqsave(&cp->lock, flags);
4178         cas_lock_tx(cp);
4179         cas_entropy_gather(cp);
4180
4181         /* If the link task is still pending, we just
4182          * reschedule the link timer
4183          */
4184 #if 1
4185         if (atomic_read(&cp->reset_task_pending_all) ||
4186             atomic_read(&cp->reset_task_pending_spare) ||
4187             atomic_read(&cp->reset_task_pending_mtu))
4188                 goto done;
4189 #else
4190         if (atomic_read(&cp->reset_task_pending))
4191                 goto done;
4192 #endif
4193
4194         /* check for rx cleaning */
4195         if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4196                 int i, rmask;
4197
4198                 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4199                         rmask = CAS_FLAG_RXD_POST(i);
4200                         if ((mask & rmask) == 0)
4201                                 continue;
4202
4203                         /* post_rxds will do a mod_timer */
4204                         if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4205                                 pending = 1;
4206                                 continue;
4207                         }
4208                         cp->cas_flags &= ~rmask;
4209                 }
4210         }
4211
4212         if (CAS_PHY_MII(cp->phy_type)) {
4213                 u16 bmsr;
4214                 cas_mif_poll(cp, 0);
4215                 bmsr = cas_phy_read(cp, MII_BMSR);
4216                 /* WTZ: Solaris driver reads this twice, but that
4217                  * may be due to the PCS case and the use of a
4218                  * common implementation. Read it twice here to be
4219                  * safe.
4220                  */
4221                 bmsr = cas_phy_read(cp, MII_BMSR);
4222                 cas_mif_poll(cp, 1);
4223                 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4224                 reset = cas_mii_link_check(cp, bmsr);
4225         } else {
4226                 reset = cas_pcs_link_check(cp);
4227         }
4228
4229         if (reset)
4230                 goto done;
4231
4232         /* check for tx state machine confusion */
4233         if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4234                 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4235                 u32 wptr, rptr;
4236                 int tlm  = CAS_VAL(MAC_SM_TLM, val);
4237
4238                 if (((tlm == 0x5) || (tlm == 0x3)) &&
4239                     (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4240                         if (netif_msg_tx_err(cp))
4241                                 printk(KERN_DEBUG "%s: tx err: "
4242                                        "MAC_STATE[%08x]\n",
4243                                        cp->dev->name, val);
4244                         reset = 1;
4245                         goto done;
4246                 }
4247
4248                 val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4249                 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4250                 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4251                 if ((val == 0) && (wptr != rptr)) {
4252                         if (netif_msg_tx_err(cp))
4253                                 printk(KERN_DEBUG "%s: tx err: "
4254                                        "TX_FIFO[%08x:%08x:%08x]\n",
4255                                        cp->dev->name, val, wptr, rptr);
4256                         reset = 1;
4257                 }
4258
4259                 if (reset)
4260                         cas_hard_reset(cp);
4261         }
4262
4263 done:
4264         if (reset) {
4265 #if 1
4266                 atomic_inc(&cp->reset_task_pending);
4267                 atomic_inc(&cp->reset_task_pending_all);
4268                 schedule_work(&cp->reset_task);
4269 #else
4270                 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4271                 printk(KERN_ERR "reset called in cas_link_timer\n");
4272                 schedule_work(&cp->reset_task);
4273 #endif
4274         }
4275
4276         if (!pending)
4277                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4278         cas_unlock_tx(cp);
4279         spin_unlock_irqrestore(&cp->lock, flags);
4280 }
4281
4282 /* tiny buffers are used to avoid target abort issues with
4283  * older cassini's
4284  */
4285 static void cas_tx_tiny_free(struct cas *cp)
4286 {
4287         struct pci_dev *pdev = cp->pdev;
4288         int i;
4289
4290         for (i = 0; i < N_TX_RINGS; i++) {
4291                 if (!cp->tx_tiny_bufs[i])
4292                         continue;
4293
4294                 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4295                                     cp->tx_tiny_bufs[i],
4296                                     cp->tx_tiny_dvma[i]);
4297                 cp->tx_tiny_bufs[i] = NULL;
4298         }
4299 }
4300
4301 static int cas_tx_tiny_alloc(struct cas *cp)
4302 {
4303         struct pci_dev *pdev = cp->pdev;
4304         int i;
4305
4306         for (i = 0; i < N_TX_RINGS; i++) {
4307                 cp->tx_tiny_bufs[i] =
4308                         pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4309                                              &cp->tx_tiny_dvma[i]);
4310                 if (!cp->tx_tiny_bufs[i]) {
4311                         cas_tx_tiny_free(cp);
4312                         return -1;
4313                 }
4314         }
4315         return 0;
4316 }
4317
4318
4319 static int cas_open(struct net_device *dev)
4320 {
4321         struct cas *cp = netdev_priv(dev);
4322         int hw_was_up, err;
4323         unsigned long flags;
4324
4325         mutex_lock(&cp->pm_mutex);
4326
4327         hw_was_up = cp->hw_running;
4328
4329         /* The power-management mutex protects the hw_running
4330          * etc. state so it is safe to do this bit without cp->lock
4331          */
4332         if (!cp->hw_running) {
4333                 /* Reset the chip */
4334                 cas_lock_all_save(cp, flags);
4335                 /* We set the second arg to cas_reset to zero
4336                  * because cas_init_hw below will have its second
4337                  * argument set to non-zero, which will force
4338                  * autonegotiation to start.
4339                  */
4340                 cas_reset(cp, 0);
4341                 cp->hw_running = 1;
4342                 cas_unlock_all_restore(cp, flags);
4343         }
4344
4345         if (cas_tx_tiny_alloc(cp) < 0)
4346                 return -ENOMEM;
4347
4348         /* alloc rx descriptors */
4349         err = -ENOMEM;
4350         if (cas_alloc_rxds(cp) < 0)
4351                 goto err_tx_tiny;
4352
4353         /* allocate spares */
4354         cas_spare_init(cp);
4355         cas_spare_recover(cp, GFP_KERNEL);
4356
4357         /* We can now request the interrupt as we know it's masked
4358          * on the controller. cassini+ has up to 4 interrupts
4359          * that can be used, but you need to do explicit pci interrupt
4360          * mapping to expose them
4361          */
4362         if (request_irq(cp->pdev->irq, cas_interrupt,
4363                         IRQF_SHARED, dev->name, (void *) dev)) {
4364                 printk(KERN_ERR "%s: failed to request irq !\n",
4365                        cp->dev->name);
4366                 err = -EAGAIN;
4367                 goto err_spare;
4368         }
4369
4370 #ifdef USE_NAPI
4371         napi_enable(&cp->napi);
4372 #endif
4373         /* init hw */
4374         cas_lock_all_save(cp, flags);
4375         cas_clean_rings(cp);
4376         cas_init_hw(cp, !hw_was_up);
4377         cp->opened = 1;
4378         cas_unlock_all_restore(cp, flags);
4379
4380         netif_start_queue(dev);
4381         mutex_unlock(&cp->pm_mutex);
4382         return 0;
4383
4384 err_spare:
4385         cas_spare_free(cp);
4386         cas_free_rxds(cp);
4387 err_tx_tiny:
4388         cas_tx_tiny_free(cp);
4389         mutex_unlock(&cp->pm_mutex);
4390         return err;
4391 }
4392
4393 static int cas_close(struct net_device *dev)
4394 {
4395         unsigned long flags;
4396         struct cas *cp = netdev_priv(dev);
4397
4398 #ifdef USE_NAPI
4399         napi_disable(&cp->napi);
4400 #endif
4401         /* Make sure we don't get distracted by suspend/resume */
4402         mutex_lock(&cp->pm_mutex);
4403
4404         netif_stop_queue(dev);
4405
4406         /* Stop traffic, mark us closed */
4407         cas_lock_all_save(cp, flags);
4408         cp->opened = 0;
4409         cas_reset(cp, 0);
4410         cas_phy_init(cp);
4411         cas_begin_auto_negotiation(cp, NULL);
4412         cas_clean_rings(cp);
4413         cas_unlock_all_restore(cp, flags);
4414
4415         free_irq(cp->pdev->irq, (void *) dev);
4416         cas_spare_free(cp);
4417         cas_free_rxds(cp);
4418         cas_tx_tiny_free(cp);
4419         mutex_unlock(&cp->pm_mutex);
4420         return 0;
4421 }
4422
4423 static struct {
4424         const char name[ETH_GSTRING_LEN];
4425 } ethtool_cassini_statnames[] = {
4426         {"collisions"},
4427         {"rx_bytes"},
4428         {"rx_crc_errors"},
4429         {"rx_dropped"},
4430         {"rx_errors"},
4431         {"rx_fifo_errors"},
4432         {"rx_frame_errors"},
4433         {"rx_length_errors"},
4434         {"rx_over_errors"},
4435         {"rx_packets"},
4436         {"tx_aborted_errors"},
4437         {"tx_bytes"},
4438         {"tx_dropped"},
4439         {"tx_errors"},
4440         {"tx_fifo_errors"},
4441         {"tx_packets"}
4442 };
4443 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4444
4445 static struct {
4446         const int offsets;      /* neg. values for 2nd arg to cas_read_phy */
4447 } ethtool_register_table[] = {
4448         {-MII_BMSR},
4449         {-MII_BMCR},
4450         {REG_CAWR},
4451         {REG_INF_BURST},
4452         {REG_BIM_CFG},
4453         {REG_RX_CFG},
4454         {REG_HP_CFG},
4455         {REG_MAC_TX_CFG},
4456         {REG_MAC_RX_CFG},
4457         {REG_MAC_CTRL_CFG},
4458         {REG_MAC_XIF_CFG},
4459         {REG_MIF_CFG},
4460         {REG_PCS_CFG},
4461         {REG_SATURN_PCFG},
4462         {REG_PCS_MII_STATUS},
4463         {REG_PCS_STATE_MACHINE},
4464         {REG_MAC_COLL_EXCESS},
4465         {REG_MAC_COLL_LATE}
4466 };
4467 #define CAS_REG_LEN     ARRAY_SIZE(ethtool_register_table)
4468 #define CAS_MAX_REGS    (sizeof (u32)*CAS_REG_LEN)
4469
4470 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4471 {
4472         u8 *p;
4473         int i;
4474         unsigned long flags;
4475
4476         spin_lock_irqsave(&cp->lock, flags);
4477         for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4478                 u16 hval;
4479                 u32 val;
4480                 if (ethtool_register_table[i].offsets < 0) {
4481                         hval = cas_phy_read(cp,
4482                                     -ethtool_register_table[i].offsets);
4483                         val = hval;
4484                 } else {
4485                         val= readl(cp->regs+ethtool_register_table[i].offsets);
4486                 }
4487                 memcpy(p, (u8 *)&val, sizeof(u32));
4488         }
4489         spin_unlock_irqrestore(&cp->lock, flags);
4490 }
4491
4492 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4493 {
4494         struct cas *cp = netdev_priv(dev);
4495         struct net_device_stats *stats = cp->net_stats;
4496         unsigned long flags;
4497         int i;
4498         unsigned long tmp;
4499
4500         /* we collate all of the stats into net_stats[N_TX_RING] */
4501         if (!cp->hw_running)
4502                 return stats + N_TX_RINGS;
4503
4504         /* collect outstanding stats */
4505         /* WTZ: the Cassini spec gives these as 16 bit counters but
4506          * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4507          * in case the chip somehow puts any garbage in the other bits.
4508          * Also, counter usage didn't seem to mach what Adrian did
4509          * in the parts of the code that set these quantities. Made
4510          * that consistent.
4511          */
4512         spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4513         stats[N_TX_RINGS].rx_crc_errors +=
4514           readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4515         stats[N_TX_RINGS].rx_frame_errors +=
4516                 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4517         stats[N_TX_RINGS].rx_length_errors +=
4518                 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4519 #if 1
4520         tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4521                 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4522         stats[N_TX_RINGS].tx_aborted_errors += tmp;
4523         stats[N_TX_RINGS].collisions +=
4524           tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4525 #else
4526         stats[N_TX_RINGS].tx_aborted_errors +=
4527                 readl(cp->regs + REG_MAC_COLL_EXCESS);
4528         stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4529                 readl(cp->regs + REG_MAC_COLL_LATE);
4530 #endif
4531         cas_clear_mac_err(cp);
4532
4533         /* saved bits that are unique to ring 0 */
4534         spin_lock(&cp->stat_lock[0]);
4535         stats[N_TX_RINGS].collisions        += stats[0].collisions;
4536         stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4537         stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4538         stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4539         stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4540         stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4541         spin_unlock(&cp->stat_lock[0]);
4542
4543         for (i = 0; i < N_TX_RINGS; i++) {
4544                 spin_lock(&cp->stat_lock[i]);
4545                 stats[N_TX_RINGS].rx_length_errors +=
4546                         stats[i].rx_length_errors;
4547                 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4548                 stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4549                 stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4550                 stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4551                 stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4552                 stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4553                 stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4554                 stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4555                 stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4556                 memset(stats + i, 0, sizeof(struct net_device_stats));
4557                 spin_unlock(&cp->stat_lock[i]);
4558         }
4559         spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4560         return stats + N_TX_RINGS;
4561 }
4562
4563
4564 static void cas_set_multicast(struct net_device *dev)
4565 {
4566         struct cas *cp = netdev_priv(dev);
4567         u32 rxcfg, rxcfg_new;
4568         unsigned long flags;
4569         int limit = STOP_TRIES;
4570
4571         if (!cp->hw_running)
4572                 return;
4573
4574         spin_lock_irqsave(&cp->lock, flags);
4575         rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4576
4577         /* disable RX MAC and wait for completion */
4578         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4579         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4580                 if (!limit--)
4581                         break;
4582                 udelay(10);
4583         }
4584
4585         /* disable hash filter and wait for completion */
4586         limit = STOP_TRIES;
4587         rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4588         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4589         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4590                 if (!limit--)
4591                         break;
4592                 udelay(10);
4593         }
4594
4595         /* program hash filters */
4596         cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4597         rxcfg |= rxcfg_new;
4598         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4599         spin_unlock_irqrestore(&cp->lock, flags);
4600 }
4601
4602 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4603 {
4604         struct cas *cp = netdev_priv(dev);
4605         strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4606         strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4607         info->fw_version[0] = '\0';
4608         strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4609         info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4610                 cp->casreg_len : CAS_MAX_REGS;
4611         info->n_stats = CAS_NUM_STAT_KEYS;
4612 }
4613
4614 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4615 {
4616         struct cas *cp = netdev_priv(dev);
4617         u16 bmcr;
4618         int full_duplex, speed, pause;
4619         unsigned long flags;
4620         enum link_state linkstate = link_up;
4621
4622         cmd->advertising = 0;
4623         cmd->supported = SUPPORTED_Autoneg;
4624         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4625                 cmd->supported |= SUPPORTED_1000baseT_Full;
4626                 cmd->advertising |= ADVERTISED_1000baseT_Full;
4627         }
4628
4629         /* Record PHY settings if HW is on. */
4630         spin_lock_irqsave(&cp->lock, flags);
4631         bmcr = 0;
4632         linkstate = cp->lstate;
4633         if (CAS_PHY_MII(cp->phy_type)) {
4634                 cmd->port = PORT_MII;
4635                 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4636                         XCVR_INTERNAL : XCVR_EXTERNAL;
4637                 cmd->phy_address = cp->phy_addr;
4638                 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4639                         ADVERTISED_10baseT_Half |
4640                         ADVERTISED_10baseT_Full |
4641                         ADVERTISED_100baseT_Half |
4642                         ADVERTISED_100baseT_Full;
4643
4644                 cmd->supported |=
4645                         (SUPPORTED_10baseT_Half |
4646                          SUPPORTED_10baseT_Full |
4647                          SUPPORTED_100baseT_Half |
4648                          SUPPORTED_100baseT_Full |
4649                          SUPPORTED_TP | SUPPORTED_MII);
4650
4651                 if (cp->hw_running) {
4652                         cas_mif_poll(cp, 0);
4653                         bmcr = cas_phy_read(cp, MII_BMCR);
4654                         cas_read_mii_link_mode(cp, &full_duplex,
4655                                                &speed, &pause);
4656                         cas_mif_poll(cp, 1);
4657                 }
4658
4659         } else {
4660                 cmd->port = PORT_FIBRE;
4661                 cmd->transceiver = XCVR_INTERNAL;
4662                 cmd->phy_address = 0;
4663                 cmd->supported   |= SUPPORTED_FIBRE;
4664                 cmd->advertising |= ADVERTISED_FIBRE;
4665
4666                 if (cp->hw_running) {
4667                         /* pcs uses the same bits as mii */
4668                         bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4669                         cas_read_pcs_link_mode(cp, &full_duplex,
4670                                                &speed, &pause);
4671                 }
4672         }
4673         spin_unlock_irqrestore(&cp->lock, flags);
4674
4675         if (bmcr & BMCR_ANENABLE) {
4676                 cmd->advertising |= ADVERTISED_Autoneg;
4677                 cmd->autoneg = AUTONEG_ENABLE;
4678                 cmd->speed = ((speed == 10) ?
4679                               SPEED_10 :
4680                               ((speed == 1000) ?
4681                                SPEED_1000 : SPEED_100));
4682                 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4683         } else {
4684                 cmd->autoneg = AUTONEG_DISABLE;
4685                 cmd->speed =
4686                         (bmcr & CAS_BMCR_SPEED1000) ?
4687                         SPEED_1000 :
4688                         ((bmcr & BMCR_SPEED100) ? SPEED_100:
4689                          SPEED_10);
4690                 cmd->duplex =
4691                         (bmcr & BMCR_FULLDPLX) ?
4692                         DUPLEX_FULL : DUPLEX_HALF;
4693         }
4694         if (linkstate != link_up) {
4695                 /* Force these to "unknown" if the link is not up and
4696                  * autonogotiation in enabled. We can set the link
4697                  * speed to 0, but not cmd->duplex,
4698                  * because its legal values are 0 and 1.  Ethtool will
4699                  * print the value reported in parentheses after the
4700                  * word "Unknown" for unrecognized values.
4701                  *
4702                  * If in forced mode, we report the speed and duplex
4703                  * settings that we configured.
4704                  */
4705                 if (cp->link_cntl & BMCR_ANENABLE) {
4706                         cmd->speed = 0;
4707                         cmd->duplex = 0xff;
4708                 } else {
4709                         cmd->speed = SPEED_10;
4710                         if (cp->link_cntl & BMCR_SPEED100) {
4711                                 cmd->speed = SPEED_100;
4712                         } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4713                                 cmd->speed = SPEED_1000;
4714                         }
4715                         cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4716                                 DUPLEX_FULL : DUPLEX_HALF;
4717                 }
4718         }
4719         return 0;
4720 }
4721
4722 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4723 {
4724         struct cas *cp = netdev_priv(dev);
4725         unsigned long flags;
4726
4727         /* Verify the settings we care about. */
4728         if (cmd->autoneg != AUTONEG_ENABLE &&
4729             cmd->autoneg != AUTONEG_DISABLE)
4730                 return -EINVAL;
4731
4732         if (cmd->autoneg == AUTONEG_DISABLE &&
4733             ((cmd->speed != SPEED_1000 &&
4734               cmd->speed != SPEED_100 &&
4735               cmd->speed != SPEED_10) ||
4736              (cmd->duplex != DUPLEX_HALF &&
4737               cmd->duplex != DUPLEX_FULL)))
4738                 return -EINVAL;
4739
4740         /* Apply settings and restart link process. */
4741         spin_lock_irqsave(&cp->lock, flags);
4742         cas_begin_auto_negotiation(cp, cmd);
4743         spin_unlock_irqrestore(&cp->lock, flags);
4744         return 0;
4745 }
4746
4747 static int cas_nway_reset(struct net_device *dev)
4748 {
4749         struct cas *cp = netdev_priv(dev);
4750         unsigned long flags;
4751
4752         if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4753                 return -EINVAL;
4754
4755         /* Restart link process. */
4756         spin_lock_irqsave(&cp->lock, flags);
4757         cas_begin_auto_negotiation(cp, NULL);
4758         spin_unlock_irqrestore(&cp->lock, flags);
4759
4760         return 0;
4761 }
4762
4763 static u32 cas_get_link(struct net_device *dev)
4764 {
4765         struct cas *cp = netdev_priv(dev);
4766         return cp->lstate == link_up;
4767 }
4768
4769 static u32 cas_get_msglevel(struct net_device *dev)
4770 {
4771         struct cas *cp = netdev_priv(dev);
4772         return cp->msg_enable;
4773 }
4774
4775 static void cas_set_msglevel(struct net_device *dev, u32 value)
4776 {
4777         struct cas *cp = netdev_priv(dev);
4778         cp->msg_enable = value;
4779 }
4780
4781 static int cas_get_regs_len(struct net_device *dev)
4782 {
4783         struct cas *cp = netdev_priv(dev);
4784         return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4785 }
4786
4787 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4788                              void *p)
4789 {
4790         struct cas *cp = netdev_priv(dev);
4791         regs->version = 0;
4792         /* cas_read_regs handles locks (cp->lock).  */
4793         cas_read_regs(cp, p, regs->len / sizeof(u32));
4794 }
4795
4796 static int cas_get_sset_count(struct net_device *dev, int sset)
4797 {
4798         switch (sset) {
4799         case ETH_SS_STATS:
4800                 return CAS_NUM_STAT_KEYS;
4801         default:
4802                 return -EOPNOTSUPP;
4803         }
4804 }
4805
4806 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4807 {
4808          memcpy(data, &ethtool_cassini_statnames,
4809                                          CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4810 }
4811
4812 static void cas_get_ethtool_stats(struct net_device *dev,
4813                                       struct ethtool_stats *estats, u64 *data)
4814 {
4815         struct cas *cp = netdev_priv(dev);
4816         struct net_device_stats *stats = cas_get_stats(cp->dev);
4817         int i = 0;
4818         data[i++] = stats->collisions;
4819         data[i++] = stats->rx_bytes;
4820         data[i++] = stats->rx_crc_errors;
4821         data[i++] = stats->rx_dropped;
4822         data[i++] = stats->rx_errors;
4823         data[i++] = stats->rx_fifo_errors;
4824         data[i++] = stats->rx_frame_errors;
4825         data[i++] = stats->rx_length_errors;
4826         data[i++] = stats->rx_over_errors;
4827         data[i++] = stats->rx_packets;
4828         data[i++] = stats->tx_aborted_errors;
4829         data[i++] = stats->tx_bytes;
4830         data[i++] = stats->tx_dropped;
4831         data[i++] = stats->tx_errors;
4832         data[i++] = stats->tx_fifo_errors;
4833         data[i++] = stats->tx_packets;
4834         BUG_ON(i != CAS_NUM_STAT_KEYS);
4835 }
4836
4837 static const struct ethtool_ops cas_ethtool_ops = {
4838         .get_drvinfo            = cas_get_drvinfo,
4839         .get_settings           = cas_get_settings,
4840         .set_settings           = cas_set_settings,
4841         .nway_reset             = cas_nway_reset,
4842         .get_link               = cas_get_link,
4843         .get_msglevel           = cas_get_msglevel,
4844         .set_msglevel           = cas_set_msglevel,
4845         .get_regs_len           = cas_get_regs_len,
4846         .get_regs               = cas_get_regs,
4847         .get_sset_count         = cas_get_sset_count,
4848         .get_strings            = cas_get_strings,
4849         .get_ethtool_stats      = cas_get_ethtool_stats,
4850 };
4851
4852 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4853 {
4854         struct cas *cp = netdev_priv(dev);
4855         struct mii_ioctl_data *data = if_mii(ifr);
4856         unsigned long flags;
4857         int rc = -EOPNOTSUPP;
4858
4859         /* Hold the PM mutex while doing ioctl's or we may collide
4860          * with open/close and power management and oops.
4861          */
4862         mutex_lock(&cp->pm_mutex);
4863         switch (cmd) {
4864         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
4865                 data->phy_id = cp->phy_addr;
4866                 /* Fallthrough... */
4867
4868         case SIOCGMIIREG:               /* Read MII PHY register. */
4869                 spin_lock_irqsave(&cp->lock, flags);
4870                 cas_mif_poll(cp, 0);
4871                 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4872                 cas_mif_poll(cp, 1);
4873                 spin_unlock_irqrestore(&cp->lock, flags);
4874                 rc = 0;
4875                 break;
4876
4877         case SIOCSMIIREG:               /* Write MII PHY register. */
4878                 if (!capable(CAP_NET_ADMIN)) {
4879                         rc = -EPERM;
4880                         break;
4881                 }
4882                 spin_lock_irqsave(&cp->lock, flags);
4883                 cas_mif_poll(cp, 0);
4884                 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4885                 cas_mif_poll(cp, 1);
4886                 spin_unlock_irqrestore(&cp->lock, flags);
4887                 break;
4888         default:
4889                 break;
4890         };
4891
4892         mutex_unlock(&cp->pm_mutex);
4893         return rc;
4894 }
4895
4896 /* When this chip sits underneath an Intel 31154 bridge, it is the
4897  * only subordinate device and we can tweak the bridge settings to
4898  * reflect that fact.
4899  */
4900 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4901 {
4902         struct pci_dev *pdev = cas_pdev->bus->self;
4903         u32 val;
4904
4905         if (!pdev)
4906                 return;
4907
4908         if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4909                 return;
4910
4911         /* Clear bit 10 (Bus Parking Control) in the Secondary
4912          * Arbiter Control/Status Register which lives at offset
4913          * 0x41.  Using a 32-bit word read/modify/write at 0x40
4914          * is much simpler so that's how we do this.
4915          */
4916         pci_read_config_dword(pdev, 0x40, &val);
4917         val &= ~0x00040000;
4918         pci_write_config_dword(pdev, 0x40, val);
4919
4920         /* Max out the Multi-Transaction Timer settings since
4921          * Cassini is the only device present.
4922          *
4923          * The register is 16-bit and lives at 0x50.  When the
4924          * settings are enabled, it extends the GRANT# signal
4925          * for a requestor after a transaction is complete.  This
4926          * allows the next request to run without first needing
4927          * to negotiate the GRANT# signal back.
4928          *
4929          * Bits 12:10 define the grant duration:
4930          *
4931          *      1       --      16 clocks
4932          *      2       --      32 clocks
4933          *      3       --      64 clocks
4934          *      4       --      128 clocks
4935          *      5       --      256 clocks
4936          *
4937          * All other values are illegal.
4938          *
4939          * Bits 09:00 define which REQ/GNT signal pairs get the
4940          * GRANT# signal treatment.  We set them all.
4941          */
4942         pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4943
4944         /* The Read Prefecth Policy register is 16-bit and sits at
4945          * offset 0x52.  It enables a "smart" pre-fetch policy.  We
4946          * enable it and max out all of the settings since only one
4947          * device is sitting underneath and thus bandwidth sharing is
4948          * not an issue.
4949          *
4950          * The register has several 3 bit fields, which indicates a
4951          * multiplier applied to the base amount of prefetching the
4952          * chip would do.  These fields are at:
4953          *
4954          *      15:13   ---     ReRead Primary Bus
4955          *      12:10   ---     FirstRead Primary Bus
4956          *      09:07   ---     ReRead Secondary Bus
4957          *      06:04   ---     FirstRead Secondary Bus
4958          *
4959          * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4960          * get enabled on.  Bit 3 is a grouped enabler which controls
4961          * all of the REQ/GNT pairs from [8:3].  Bits 2 to 0 control
4962          * the individual REQ/GNT pairs [2:0].
4963          */
4964         pci_write_config_word(pdev, 0x52,
4965                               (0x7 << 13) |
4966                               (0x7 << 10) |
4967                               (0x7 <<  7) |
4968                               (0x7 <<  4) |
4969                               (0xf <<  0));
4970
4971         /* Force cacheline size to 0x8 */
4972         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4973
4974         /* Force latency timer to maximum setting so Cassini can
4975          * sit on the bus as long as it likes.
4976          */
4977         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4978 }
4979
4980 static const struct net_device_ops cas_netdev_ops = {
4981         .ndo_open               = cas_open,
4982         .ndo_stop               = cas_close,
4983         .ndo_start_xmit         = cas_start_xmit,
4984         .ndo_get_stats          = cas_get_stats,
4985         .ndo_set_multicast_list = cas_set_multicast,
4986         .ndo_do_ioctl           = cas_ioctl,
4987         .ndo_tx_timeout         = cas_tx_timeout,
4988         .ndo_change_mtu         = cas_change_mtu,
4989         .ndo_set_mac_address    = eth_mac_addr,
4990         .ndo_validate_addr      = eth_validate_addr,
4991 #ifdef CONFIG_NET_POLL_CONTROLLER
4992         .ndo_poll_controller    = cas_netpoll,
4993 #endif
4994 };
4995
4996 static int __devinit cas_init_one(struct pci_dev *pdev,
4997                                   const struct pci_device_id *ent)
4998 {
4999         static int cas_version_printed = 0;
5000         unsigned long casreg_len;
5001         struct net_device *dev;
5002         struct cas *cp;
5003         int i, err, pci_using_dac;
5004         u16 pci_cmd;
5005         u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
5006
5007         if (cas_version_printed++ == 0)
5008                 printk(KERN_INFO "%s", version);
5009
5010         err = pci_enable_device(pdev);
5011         if (err) {
5012                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
5013                 return err;
5014         }
5015
5016         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5017                 dev_err(&pdev->dev, "Cannot find proper PCI device "
5018                        "base address, aborting.\n");
5019                 err = -ENODEV;
5020                 goto err_out_disable_pdev;
5021         }
5022
5023         dev = alloc_etherdev(sizeof(*cp));
5024         if (!dev) {
5025                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
5026                 err = -ENOMEM;
5027                 goto err_out_disable_pdev;
5028         }
5029         SET_NETDEV_DEV(dev, &pdev->dev);
5030
5031         err = pci_request_regions(pdev, dev->name);
5032         if (err) {
5033                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
5034                 goto err_out_free_netdev;
5035         }
5036         pci_set_master(pdev);
5037
5038         /* we must always turn on parity response or else parity
5039          * doesn't get generated properly. disable SERR/PERR as well.
5040          * in addition, we want to turn MWI on.
5041          */
5042         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5043         pci_cmd &= ~PCI_COMMAND_SERR;
5044         pci_cmd |= PCI_COMMAND_PARITY;
5045         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5046         if (pci_try_set_mwi(pdev))
5047                 printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
5048                        pci_name(pdev));
5049
5050         cas_program_bridge(pdev);
5051
5052         /*
5053          * On some architectures, the default cache line size set
5054          * by pci_try_set_mwi reduces perforamnce.  We have to increase
5055          * it for this case.  To start, we'll print some configuration
5056          * data.
5057          */
5058 #if 1
5059         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5060                              &orig_cacheline_size);
5061         if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
5062                 cas_cacheline_size =
5063                         (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
5064                         CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
5065                 if (pci_write_config_byte(pdev,
5066                                           PCI_CACHE_LINE_SIZE,
5067                                           cas_cacheline_size)) {
5068                         dev_err(&pdev->dev, "Could not set PCI cache "
5069                                "line size\n");
5070                         goto err_write_cacheline;
5071                 }
5072         }
5073 #endif
5074
5075
5076         /* Configure DMA attributes. */
5077         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5078                 pci_using_dac = 1;
5079                 err = pci_set_consistent_dma_mask(pdev,
5080                                                   DMA_BIT_MASK(64));
5081                 if (err < 0) {
5082                         dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5083                                "for consistent allocations\n");
5084                         goto err_out_free_res;
5085                 }
5086
5087         } else {
5088                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5089                 if (err) {
5090                         dev_err(&pdev->dev, "No usable DMA configuration, "
5091                                "aborting.\n");
5092                         goto err_out_free_res;
5093                 }
5094                 pci_using_dac = 0;
5095         }
5096
5097         casreg_len = pci_resource_len(pdev, 0);
5098
5099         cp = netdev_priv(dev);
5100         cp->pdev = pdev;
5101 #if 1
5102         /* A value of 0 indicates we never explicitly set it */
5103         cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5104 #endif
5105         cp->dev = dev;
5106         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5107           cassini_debug;
5108
5109         cp->link_transition = LINK_TRANSITION_UNKNOWN;
5110         cp->link_transition_jiffies_valid = 0;
5111
5112         spin_lock_init(&cp->lock);
5113         spin_lock_init(&cp->rx_inuse_lock);
5114         spin_lock_init(&cp->rx_spare_lock);
5115         for (i = 0; i < N_TX_RINGS; i++) {
5116                 spin_lock_init(&cp->stat_lock[i]);
5117                 spin_lock_init(&cp->tx_lock[i]);
5118         }
5119         spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5120         mutex_init(&cp->pm_mutex);
5121
5122         init_timer(&cp->link_timer);
5123         cp->link_timer.function = cas_link_timer;
5124         cp->link_timer.data = (unsigned long) cp;
5125
5126 #if 1
5127         /* Just in case the implementation of atomic operations
5128          * change so that an explicit initialization is necessary.
5129          */
5130         atomic_set(&cp->reset_task_pending, 0);
5131         atomic_set(&cp->reset_task_pending_all, 0);
5132         atomic_set(&cp->reset_task_pending_spare, 0);
5133         atomic_set(&cp->reset_task_pending_mtu, 0);
5134 #endif
5135         INIT_WORK(&cp->reset_task, cas_reset_task);
5136
5137         /* Default link parameters */
5138         if (link_mode >= 0 && link_mode <= 6)
5139                 cp->link_cntl = link_modes[link_mode];
5140         else
5141                 cp->link_cntl = BMCR_ANENABLE;
5142         cp->lstate = link_down;
5143         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5144         netif_carrier_off(cp->dev);
5145         cp->timer_ticks = 0;
5146
5147         /* give us access to cassini registers */
5148         cp->regs = pci_iomap(pdev, 0, casreg_len);
5149         if (!cp->regs) {
5150                 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
5151                 goto err_out_free_res;
5152         }
5153         cp->casreg_len = casreg_len;
5154
5155         pci_save_state(pdev);
5156         cas_check_pci_invariants(cp);
5157         cas_hard_reset(cp);
5158         cas_reset(cp, 0);
5159         if (cas_check_invariants(cp))
5160                 goto err_out_iounmap;
5161         if (cp->cas_flags & CAS_FLAG_SATURN)
5162                 if (cas_saturn_firmware_init(cp))
5163                         goto err_out_iounmap;
5164
5165         cp->init_block = (struct cas_init_block *)
5166                 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5167                                      &cp->block_dvma);
5168         if (!cp->init_block) {
5169                 dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n");
5170                 goto err_out_iounmap;
5171         }
5172
5173         for (i = 0; i < N_TX_RINGS; i++)
5174                 cp->init_txds[i] = cp->init_block->txds[i];
5175
5176         for (i = 0; i < N_RX_DESC_RINGS; i++)
5177                 cp->init_rxds[i] = cp->init_block->rxds[i];
5178
5179         for (i = 0; i < N_RX_COMP_RINGS; i++)
5180                 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5181
5182         for (i = 0; i < N_RX_FLOWS; i++)
5183                 skb_queue_head_init(&cp->rx_flows[i]);
5184
5185         dev->netdev_ops = &cas_netdev_ops;
5186         dev->ethtool_ops = &cas_ethtool_ops;
5187         dev->watchdog_timeo = CAS_TX_TIMEOUT;
5188
5189 #ifdef USE_NAPI
5190         netif_napi_add(dev, &cp->napi, cas_poll, 64);
5191 #endif
5192         dev->irq = pdev->irq;
5193         dev->dma = 0;
5194
5195         /* Cassini features. */
5196         if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5197                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5198
5199         if (pci_using_dac)
5200                 dev->features |= NETIF_F_HIGHDMA;
5201
5202         if (register_netdev(dev)) {
5203                 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5204                 goto err_out_free_consistent;
5205         }
5206
5207         i = readl(cp->regs + REG_BIM_CFG);
5208         printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5209                "Ethernet[%d] %pM\n",  dev->name,
5210                (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5211                (i & BIM_CFG_32BIT) ? "32" : "64",
5212                (i & BIM_CFG_66MHZ) ? "66" : "33",
5213                (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5214                dev->dev_addr);
5215
5216         pci_set_drvdata(pdev, dev);
5217         cp->hw_running = 1;
5218         cas_entropy_reset(cp);
5219         cas_phy_init(cp);
5220         cas_begin_auto_negotiation(cp, NULL);
5221         return 0;
5222
5223 err_out_free_consistent:
5224         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5225                             cp->init_block, cp->block_dvma);
5226
5227 err_out_iounmap:
5228         mutex_lock(&cp->pm_mutex);
5229         if (cp->hw_running)
5230                 cas_shutdown(cp);
5231         mutex_unlock(&cp->pm_mutex);
5232
5233         pci_iounmap(pdev, cp->regs);
5234
5235
5236 err_out_free_res:
5237         pci_release_regions(pdev);
5238
5239 err_write_cacheline:
5240         /* Try to restore it in case the error occured after we
5241          * set it.
5242          */
5243         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5244
5245 err_out_free_netdev:
5246         free_netdev(dev);
5247
5248 err_out_disable_pdev:
5249         pci_disable_device(pdev);
5250         pci_set_drvdata(pdev, NULL);
5251         return -ENODEV;
5252 }
5253
5254 static void __devexit cas_remove_one(struct pci_dev *pdev)
5255 {
5256         struct net_device *dev = pci_get_drvdata(pdev);
5257         struct cas *cp;
5258         if (!dev)
5259                 return;
5260
5261         cp = netdev_priv(dev);
5262         unregister_netdev(dev);
5263
5264         if (cp->fw_data)
5265                 vfree(cp->fw_data);
5266
5267         mutex_lock(&cp->pm_mutex);
5268         flush_scheduled_work();
5269         if (cp->hw_running)
5270                 cas_shutdown(cp);
5271         mutex_unlock(&cp->pm_mutex);
5272
5273 #if 1
5274         if (cp->orig_cacheline_size) {
5275                 /* Restore the cache line size if we had modified
5276                  * it.
5277                  */
5278                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5279                                       cp->orig_cacheline_size);
5280         }
5281 #endif
5282         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5283                             cp->init_block, cp->block_dvma);
5284         pci_iounmap(pdev, cp->regs);
5285         free_netdev(dev);
5286         pci_release_regions(pdev);
5287         pci_disable_device(pdev);
5288         pci_set_drvdata(pdev, NULL);
5289 }
5290
5291 #ifdef CONFIG_PM
5292 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5293 {
5294         struct net_device *dev = pci_get_drvdata(pdev);
5295         struct cas *cp = netdev_priv(dev);
5296         unsigned long flags;
5297
5298         mutex_lock(&cp->pm_mutex);
5299
5300         /* If the driver is opened, we stop the DMA */
5301         if (cp->opened) {
5302                 netif_device_detach(dev);
5303
5304                 cas_lock_all_save(cp, flags);
5305
5306                 /* We can set the second arg of cas_reset to 0
5307                  * because on resume, we'll call cas_init_hw with
5308                  * its second arg set so that autonegotiation is
5309                  * restarted.
5310                  */
5311                 cas_reset(cp, 0);
5312                 cas_clean_rings(cp);
5313                 cas_unlock_all_restore(cp, flags);
5314         }
5315
5316         if (cp->hw_running)
5317                 cas_shutdown(cp);
5318         mutex_unlock(&cp->pm_mutex);
5319
5320         return 0;
5321 }
5322
5323 static int cas_resume(struct pci_dev *pdev)
5324 {
5325         struct net_device *dev = pci_get_drvdata(pdev);
5326         struct cas *cp = netdev_priv(dev);
5327
5328         printk(KERN_INFO "%s: resuming\n", dev->name);
5329
5330         mutex_lock(&cp->pm_mutex);
5331         cas_hard_reset(cp);
5332         if (cp->opened) {
5333                 unsigned long flags;
5334                 cas_lock_all_save(cp, flags);
5335                 cas_reset(cp, 0);
5336                 cp->hw_running = 1;
5337                 cas_clean_rings(cp);
5338                 cas_init_hw(cp, 1);
5339                 cas_unlock_all_restore(cp, flags);
5340
5341                 netif_device_attach(dev);
5342         }
5343         mutex_unlock(&cp->pm_mutex);
5344         return 0;
5345 }
5346 #endif /* CONFIG_PM */
5347
5348 static struct pci_driver cas_driver = {
5349         .name           = DRV_MODULE_NAME,
5350         .id_table       = cas_pci_tbl,
5351         .probe          = cas_init_one,
5352         .remove         = __devexit_p(cas_remove_one),
5353 #ifdef CONFIG_PM
5354         .suspend        = cas_suspend,
5355         .resume         = cas_resume
5356 #endif
5357 };
5358
5359 static int __init cas_init(void)
5360 {
5361         if (linkdown_timeout > 0)
5362                 link_transition_timeout = linkdown_timeout * HZ;
5363         else
5364                 link_transition_timeout = 0;
5365
5366         return pci_register_driver(&cas_driver);
5367 }
5368
5369 static void __exit cas_cleanup(void)
5370 {
5371         pci_unregister_driver(&cas_driver);
5372 }
5373
5374 module_init(cas_init);
5375 module_exit(cas_cleanup);