6e295fce5c6f08c3a1554ea87c9d9be18e86e4cc
[linux-2.6.git] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page. 
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targetted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering 
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.  
67  */
68
69 #include <linux/config.h>
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/ioport.h>
79 #include <linux/pci.h>
80 #include <linux/mm.h>
81 #include <linux/highmem.h>
82 #include <linux/list.h>
83 #include <linux/dma-mapping.h>
84
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/crc32.h>
90 #include <linux/random.h>
91 #include <linux/mii.h>
92 #include <linux/ip.h>
93 #include <linux/tcp.h>
94
95 #include <net/checksum.h>
96
97 #include <asm/atomic.h>
98 #include <asm/system.h>
99 #include <asm/io.h>
100 #include <asm/byteorder.h>
101 #include <asm/uaccess.h>
102
103 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
104 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define CAS_NCPUS            num_online_cpus()
106
107 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
108 #define USE_NAPI
109 #define cas_skb_release(x)  netif_receive_skb(x)
110 #else
111 #define cas_skb_release(x)  netif_rx(x)
112 #endif
113
114 /* select which firmware to use */
115 #define USE_HP_WORKAROUND     
116 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
117 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
118
119 #include "cassini.h"
120
121 #define USE_TX_COMPWB      /* use completion writeback registers */
122 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
123 #define USE_RX_BLANK       /* hw interrupt mitigation */
124 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
125
126 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
127  * also, we need to make cp->lock finer-grained.
128  */
129 #undef  USE_PCI_INTB
130 #undef  USE_PCI_INTC
131 #undef  USE_PCI_INTD
132 #undef  USE_QOS
133
134 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
135
136 /* rx processing options */
137 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
138 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
139 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
140 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
141 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
142
143 #define DRV_MODULE_NAME         "cassini"
144 #define PFX DRV_MODULE_NAME     ": "
145 #define DRV_MODULE_VERSION      "1.4"
146 #define DRV_MODULE_RELDATE      "1 July 2004"
147
148 #define CAS_DEF_MSG_ENABLE        \
149         (NETIF_MSG_DRV          | \
150          NETIF_MSG_PROBE        | \
151          NETIF_MSG_LINK         | \
152          NETIF_MSG_TIMER        | \
153          NETIF_MSG_IFDOWN       | \
154          NETIF_MSG_IFUP         | \
155          NETIF_MSG_RX_ERR       | \
156          NETIF_MSG_TX_ERR)
157
158 /* length of time before we decide the hardware is borked,
159  * and dev->tx_timeout() should be called to fix the problem
160  */
161 #define CAS_TX_TIMEOUT                  (HZ)
162 #define CAS_LINK_TIMEOUT                (22*HZ/10)
163 #define CAS_LINK_FAST_TIMEOUT           (1)
164
165 /* timeout values for state changing. these specify the number
166  * of 10us delays to be used before giving up.
167  */
168 #define STOP_TRIES_PHY 1000
169 #define STOP_TRIES     5000
170
171 /* specify a minimum frame size to deal with some fifo issues 
172  * max mtu == 2 * page size - ethernet header - 64 - swivel =
173  *            2 * page_size - 0x50
174  */
175 #define CAS_MIN_FRAME                   97
176 #define CAS_1000MB_MIN_FRAME            255
177 #define CAS_MIN_MTU                     60
178 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
179
180 #if 1
181 /*
182  * Eliminate these and use separate atomic counters for each, to
183  * avoid a race condition.
184  */
185 #else
186 #define CAS_RESET_MTU                   1
187 #define CAS_RESET_ALL                   2
188 #define CAS_RESET_SPARE                 3
189 #endif
190
191 static char version[] __devinitdata =
192         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
193
194 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
195 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
196 MODULE_LICENSE("GPL");
197 MODULE_PARM(cassini_debug, "i");
198 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
199 MODULE_PARM(link_mode, "i");
200 MODULE_PARM_DESC(link_mode, "default link mode");
201
202 /*
203  * Work around for a PCS bug in which the link goes down due to the chip
204  * being confused and never showing a link status of "up."
205  */
206 #define DEFAULT_LINKDOWN_TIMEOUT 5
207 /* 
208  * Value in seconds, for user input.
209  */
210 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
211 MODULE_PARM(linkdown_timeout, "i");
212 MODULE_PARM_DESC(linkdown_timeout,
213 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
214
215 /*
216  * value in 'ticks' (units used by jiffies). Set when we init the
217  * module because 'HZ' in actually a function call on some flavors of
218  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
219  */
220 static int link_transition_timeout;
221
222
223 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
224 static int link_mode;
225
226 static u16 link_modes[] __devinitdata = {
227         BMCR_ANENABLE,                   /* 0 : autoneg */
228         0,                               /* 1 : 10bt half duplex */
229         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
230         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
231         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
232         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
233 };
234
235 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
236         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240         { 0, }
241 };
242
243 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
244
245 static void cas_set_link_modes(struct cas *cp);
246
247 static inline void cas_lock_tx(struct cas *cp)
248 {
249         int i;
250
251         for (i = 0; i < N_TX_RINGS; i++)  
252                 spin_lock(&cp->tx_lock[i]);
253 }
254
255 static inline void cas_lock_all(struct cas *cp)
256 {
257         spin_lock_irq(&cp->lock);
258         cas_lock_tx(cp);
259 }
260
261 /* WTZ: QA was finding deadlock problems with the previous
262  * versions after long test runs with multiple cards per machine.
263  * See if replacing cas_lock_all with safer versions helps. The
264  * symptoms QA is reporting match those we'd expect if interrupts
265  * aren't being properly restored, and we fixed a previous deadlock
266  * with similar symptoms by using save/restore versions in other
267  * places.
268  */
269 #define cas_lock_all_save(cp, flags) \
270 do { \
271         struct cas *xxxcp = (cp); \
272         spin_lock_irqsave(&xxxcp->lock, flags); \
273         cas_lock_tx(xxxcp); \
274 } while (0)
275
276 static inline void cas_unlock_tx(struct cas *cp)
277 {
278         int i;
279
280         for (i = N_TX_RINGS; i > 0; i--)  
281                 spin_unlock(&cp->tx_lock[i - 1]);  
282 }
283
284 static inline void cas_unlock_all(struct cas *cp)
285 {
286         cas_unlock_tx(cp);
287         spin_unlock_irq(&cp->lock);
288 }
289
290 #define cas_unlock_all_restore(cp, flags) \
291 do { \
292         struct cas *xxxcp = (cp); \
293         cas_unlock_tx(xxxcp); \
294         spin_unlock_irqrestore(&xxxcp->lock, flags); \
295 } while (0)
296
297 static void cas_disable_irq(struct cas *cp, const int ring)
298 {
299         /* Make sure we won't get any more interrupts */
300         if (ring == 0) {
301                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
302                 return;
303         }
304
305         /* disable completion interrupts and selectively mask */
306         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
307                 switch (ring) {
308 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
309 #ifdef USE_PCI_INTB
310                 case 1:
311 #endif
312 #ifdef USE_PCI_INTC
313                 case 2:
314 #endif
315 #ifdef USE_PCI_INTD
316                 case 3:
317 #endif
318                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, 
319                                cp->regs + REG_PLUS_INTRN_MASK(ring));
320                         break;
321 #endif
322                 default:
323                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
324                                REG_PLUS_INTRN_MASK(ring));
325                         break;
326                 }
327         }
328 }
329
330 static inline void cas_mask_intr(struct cas *cp)
331 {
332         int i;
333
334         for (i = 0; i < N_RX_COMP_RINGS; i++)
335                 cas_disable_irq(cp, i);
336 }
337
338 static inline void cas_buffer_init(cas_page_t *cp)
339 {
340         struct page *page = cp->buffer;
341         atomic_set((atomic_t *)&page->lru.next, 1);
342 }
343
344 static inline int cas_buffer_count(cas_page_t *cp)
345 {
346         struct page *page = cp->buffer;
347         return atomic_read((atomic_t *)&page->lru.next);
348 }
349
350 static inline void cas_buffer_inc(cas_page_t *cp)
351 {
352         struct page *page = cp->buffer;
353         atomic_inc((atomic_t *)&page->lru.next);
354 }
355
356 static inline void cas_buffer_dec(cas_page_t *cp)
357 {
358         struct page *page = cp->buffer;
359         atomic_dec((atomic_t *)&page->lru.next);
360 }
361
362 static void cas_enable_irq(struct cas *cp, const int ring)
363 {
364         if (ring == 0) { /* all but TX_DONE */
365                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
366                 return;
367         }
368
369         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
370                 switch (ring) {
371 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
372 #ifdef USE_PCI_INTB
373                 case 1:
374 #endif
375 #ifdef USE_PCI_INTC
376                 case 2:
377 #endif
378 #ifdef USE_PCI_INTD
379                 case 3:
380 #endif
381                         writel(INTRN_MASK_RX_EN, cp->regs +
382                                REG_PLUS_INTRN_MASK(ring));
383                         break;
384 #endif
385                 default:
386                         break;
387                 }
388         }
389 }
390
391 static inline void cas_unmask_intr(struct cas *cp)
392 {
393         int i;
394
395         for (i = 0; i < N_RX_COMP_RINGS; i++)
396                 cas_enable_irq(cp, i);
397 }
398
399 static inline void cas_entropy_gather(struct cas *cp)
400 {
401 #ifdef USE_ENTROPY_DEV
402         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
403                 return;
404
405         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
406                             readl(cp->regs + REG_ENTROPY_IV),
407                             sizeof(uint64_t)*8);
408 #endif
409 }
410
411 static inline void cas_entropy_reset(struct cas *cp)
412 {
413 #ifdef USE_ENTROPY_DEV
414         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
415                 return;
416
417         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, 
418                cp->regs + REG_BIM_LOCAL_DEV_EN);
419         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
420         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
421
422         /* if we read back 0x0, we don't have an entropy device */
423         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
424                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
425 #endif
426 }
427
428 /* access to the phy. the following assumes that we've initialized the MIF to 
429  * be in frame rather than bit-bang mode
430  */
431 static u16 cas_phy_read(struct cas *cp, int reg)
432 {
433         u32 cmd;
434         int limit = STOP_TRIES_PHY;
435
436         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
437         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
438         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
439         cmd |= MIF_FRAME_TURN_AROUND_MSB;
440         writel(cmd, cp->regs + REG_MIF_FRAME);
441         
442         /* poll for completion */
443         while (limit-- > 0) {
444                 udelay(10);
445                 cmd = readl(cp->regs + REG_MIF_FRAME);
446                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
447                         return (cmd & MIF_FRAME_DATA_MASK);
448         }
449         return 0xFFFF; /* -1 */
450 }
451
452 static int cas_phy_write(struct cas *cp, int reg, u16 val)
453 {
454         int limit = STOP_TRIES_PHY;
455         u32 cmd;
456
457         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
458         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
459         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
460         cmd |= MIF_FRAME_TURN_AROUND_MSB;
461         cmd |= val & MIF_FRAME_DATA_MASK;
462         writel(cmd, cp->regs + REG_MIF_FRAME);
463         
464         /* poll for completion */
465         while (limit-- > 0) {
466                 udelay(10);
467                 cmd = readl(cp->regs + REG_MIF_FRAME);
468                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
469                         return 0;
470         }
471         return -1;
472 }
473
474 static void cas_phy_powerup(struct cas *cp)
475 {
476         u16 ctl = cas_phy_read(cp, MII_BMCR);   
477
478         if ((ctl & BMCR_PDOWN) == 0)
479                 return;
480         ctl &= ~BMCR_PDOWN;
481         cas_phy_write(cp, MII_BMCR, ctl);
482 }
483
484 static void cas_phy_powerdown(struct cas *cp)
485 {
486         u16 ctl = cas_phy_read(cp, MII_BMCR);   
487
488         if (ctl & BMCR_PDOWN)
489                 return;
490         ctl |= BMCR_PDOWN;
491         cas_phy_write(cp, MII_BMCR, ctl);
492 }
493
494 /* cp->lock held. note: the last put_page will free the buffer */
495 static int cas_page_free(struct cas *cp, cas_page_t *page)
496 {
497         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size, 
498                        PCI_DMA_FROMDEVICE);
499         cas_buffer_dec(page);
500         __free_pages(page->buffer, cp->page_order);
501         kfree(page);
502         return 0;
503 }
504
505 #ifdef RX_COUNT_BUFFERS
506 #define RX_USED_ADD(x, y)       ((x)->used += (y))
507 #define RX_USED_SET(x, y)       ((x)->used  = (y))
508 #else
509 #define RX_USED_ADD(x, y) 
510 #define RX_USED_SET(x, y)
511 #endif
512
513 /* local page allocation routines for the receive buffers. jumbo pages
514  * require at least 8K contiguous and 8K aligned buffers.
515  */
516 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
517 {
518         cas_page_t *page;
519
520         page = kmalloc(sizeof(cas_page_t), flags);
521         if (!page)
522                 return NULL;
523
524         INIT_LIST_HEAD(&page->list);
525         RX_USED_SET(page, 0);
526         page->buffer = alloc_pages(flags, cp->page_order);
527         if (!page->buffer)
528                 goto page_err;
529         cas_buffer_init(page);
530         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
531                                       cp->page_size, PCI_DMA_FROMDEVICE);
532         return page;
533
534 page_err:
535         kfree(page);
536         return NULL;
537 }
538
539 /* initialize spare pool of rx buffers, but allocate during the open */
540 static void cas_spare_init(struct cas *cp)
541 {
542         spin_lock(&cp->rx_inuse_lock);
543         INIT_LIST_HEAD(&cp->rx_inuse_list);
544         spin_unlock(&cp->rx_inuse_lock);
545
546         spin_lock(&cp->rx_spare_lock);
547         INIT_LIST_HEAD(&cp->rx_spare_list);
548         cp->rx_spares_needed = RX_SPARE_COUNT;
549         spin_unlock(&cp->rx_spare_lock);
550 }
551
552 /* used on close. free all the spare buffers. */
553 static void cas_spare_free(struct cas *cp)
554 {
555         struct list_head list, *elem, *tmp;
556
557         /* free spare buffers */
558         INIT_LIST_HEAD(&list);
559         spin_lock(&cp->rx_spare_lock);
560         list_splice(&cp->rx_spare_list, &list);
561         INIT_LIST_HEAD(&cp->rx_spare_list);
562         spin_unlock(&cp->rx_spare_lock);
563         list_for_each_safe(elem, tmp, &list) {
564                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
565         }
566
567         INIT_LIST_HEAD(&list);
568 #if 1
569         /*
570          * Looks like Adrian had protected this with a different
571          * lock than used everywhere else to manipulate this list.
572          */
573         spin_lock(&cp->rx_inuse_lock);
574         list_splice(&cp->rx_inuse_list, &list);
575         INIT_LIST_HEAD(&cp->rx_inuse_list);
576         spin_unlock(&cp->rx_inuse_lock);
577 #else
578         spin_lock(&cp->rx_spare_lock);
579         list_splice(&cp->rx_inuse_list, &list);
580         INIT_LIST_HEAD(&cp->rx_inuse_list);
581         spin_unlock(&cp->rx_spare_lock);
582 #endif
583         list_for_each_safe(elem, tmp, &list) {
584                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
585         }
586 }
587
588 /* replenish spares if needed */
589 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
590 {
591         struct list_head list, *elem, *tmp;
592         int needed, i;
593
594         /* check inuse list. if we don't need any more free buffers,
595          * just free it
596          */
597
598         /* make a local copy of the list */
599         INIT_LIST_HEAD(&list);
600         spin_lock(&cp->rx_inuse_lock);
601         list_splice(&cp->rx_inuse_list, &list);
602         INIT_LIST_HEAD(&cp->rx_inuse_list);
603         spin_unlock(&cp->rx_inuse_lock);
604         
605         list_for_each_safe(elem, tmp, &list) {
606                 cas_page_t *page = list_entry(elem, cas_page_t, list);
607
608                 if (cas_buffer_count(page) > 1)
609                         continue;
610
611                 list_del(elem);
612                 spin_lock(&cp->rx_spare_lock);
613                 if (cp->rx_spares_needed > 0) {
614                         list_add(elem, &cp->rx_spare_list);
615                         cp->rx_spares_needed--;
616                         spin_unlock(&cp->rx_spare_lock);
617                 } else {
618                         spin_unlock(&cp->rx_spare_lock);
619                         cas_page_free(cp, page);
620                 }
621         }
622
623         /* put any inuse buffers back on the list */
624         if (!list_empty(&list)) {
625                 spin_lock(&cp->rx_inuse_lock);
626                 list_splice(&list, &cp->rx_inuse_list);
627                 spin_unlock(&cp->rx_inuse_lock);
628         }
629         
630         spin_lock(&cp->rx_spare_lock);
631         needed = cp->rx_spares_needed;
632         spin_unlock(&cp->rx_spare_lock);
633         if (!needed)
634                 return;
635
636         /* we still need spares, so try to allocate some */
637         INIT_LIST_HEAD(&list);
638         i = 0;
639         while (i < needed) {
640                 cas_page_t *spare = cas_page_alloc(cp, flags);
641                 if (!spare) 
642                         break;
643                 list_add(&spare->list, &list);
644                 i++;
645         }
646
647         spin_lock(&cp->rx_spare_lock);
648         list_splice(&list, &cp->rx_spare_list);
649         cp->rx_spares_needed -= i;
650         spin_unlock(&cp->rx_spare_lock);
651 }
652
653 /* pull a page from the list. */
654 static cas_page_t *cas_page_dequeue(struct cas *cp)
655 {
656         struct list_head *entry;
657         int recover;
658
659         spin_lock(&cp->rx_spare_lock);
660         if (list_empty(&cp->rx_spare_list)) {
661                 /* try to do a quick recovery */
662                 spin_unlock(&cp->rx_spare_lock);
663                 cas_spare_recover(cp, GFP_ATOMIC);
664                 spin_lock(&cp->rx_spare_lock);
665                 if (list_empty(&cp->rx_spare_list)) {
666                         if (netif_msg_rx_err(cp))
667                                 printk(KERN_ERR "%s: no spare buffers "
668                                        "available.\n", cp->dev->name);
669                         spin_unlock(&cp->rx_spare_lock);
670                         return NULL;
671                 }
672         }
673
674         entry = cp->rx_spare_list.next;
675         list_del(entry);
676         recover = ++cp->rx_spares_needed;
677         spin_unlock(&cp->rx_spare_lock);
678
679         /* trigger the timer to do the recovery */
680         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
681 #if 1
682                 atomic_inc(&cp->reset_task_pending);
683                 atomic_inc(&cp->reset_task_pending_spare);
684                 schedule_work(&cp->reset_task);
685 #else
686                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
687                 schedule_work(&cp->reset_task);
688 #endif
689         }
690         return list_entry(entry, cas_page_t, list);
691 }
692
693
694 static void cas_mif_poll(struct cas *cp, const int enable)
695 {
696         u32 cfg;
697         
698         cfg  = readl(cp->regs + REG_MIF_CFG); 
699         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
700
701         if (cp->phy_type & CAS_PHY_MII_MDIO1)
702                 cfg |= MIF_CFG_PHY_SELECT; 
703
704         /* poll and interrupt on link status change. */
705         if (enable) {
706                 cfg |= MIF_CFG_POLL_EN;
707                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
708                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
709         }
710         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, 
711                cp->regs + REG_MIF_MASK); 
712         writel(cfg, cp->regs + REG_MIF_CFG);
713 }
714
715 /* Must be invoked under cp->lock */
716 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
717 {
718         u16 ctl;
719 #if 1
720         int lcntl;
721         int changed = 0;
722         int oldstate = cp->lstate;
723         int link_was_not_down = !(oldstate == link_down);
724 #endif
725         /* Setup link parameters */
726         if (!ep)
727                 goto start_aneg;
728         lcntl = cp->link_cntl;
729         if (ep->autoneg == AUTONEG_ENABLE)
730                 cp->link_cntl = BMCR_ANENABLE;
731         else {
732                 cp->link_cntl = 0;
733                 if (ep->speed == SPEED_100)
734                         cp->link_cntl |= BMCR_SPEED100;
735                 else if (ep->speed == SPEED_1000)
736                         cp->link_cntl |= CAS_BMCR_SPEED1000;
737                 if (ep->duplex == DUPLEX_FULL)
738                         cp->link_cntl |= BMCR_FULLDPLX;
739         }
740 #if 1
741         changed = (lcntl != cp->link_cntl);
742 #endif
743 start_aneg:
744         if (cp->lstate == link_up) {
745                 printk(KERN_INFO "%s: PCS link down.\n",
746                        cp->dev->name);
747         } else {
748                 if (changed) {
749                         printk(KERN_INFO "%s: link configuration changed\n",
750                                cp->dev->name);
751                 }
752         }
753         cp->lstate = link_down;
754         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
755         if (!cp->hw_running)
756                 return;
757 #if 1
758         /*
759          * WTZ: If the old state was link_up, we turn off the carrier
760          * to replicate everything we do elsewhere on a link-down
761          * event when we were already in a link-up state..  
762          */
763         if (oldstate == link_up)
764                 netif_carrier_off(cp->dev);
765         if (changed  && link_was_not_down) {
766                 /*
767                  * WTZ: This branch will simply schedule a full reset after
768                  * we explicitly changed link modes in an ioctl. See if this
769                  * fixes the link-problems we were having for forced mode. 
770                  */
771                 atomic_inc(&cp->reset_task_pending);
772                 atomic_inc(&cp->reset_task_pending_all);
773                 schedule_work(&cp->reset_task);
774                 cp->timer_ticks = 0;
775                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
776                 return;
777         }
778 #endif
779         if (cp->phy_type & CAS_PHY_SERDES) {
780                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
781
782                 if (cp->link_cntl & BMCR_ANENABLE) {
783                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
784                         cp->lstate = link_aneg;
785                 } else {
786                         if (cp->link_cntl & BMCR_FULLDPLX)
787                                 val |= PCS_MII_CTRL_DUPLEX;
788                         val &= ~PCS_MII_AUTONEG_EN;
789                         cp->lstate = link_force_ok;
790                 }
791                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
792                 writel(val, cp->regs + REG_PCS_MII_CTRL);
793
794         } else {
795                 cas_mif_poll(cp, 0);
796                 ctl = cas_phy_read(cp, MII_BMCR);
797                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | 
798                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
799                 ctl |= cp->link_cntl;
800                 if (ctl & BMCR_ANENABLE) {
801                         ctl |= BMCR_ANRESTART;
802                         cp->lstate = link_aneg;
803                 } else {
804                         cp->lstate = link_force_ok;
805                 }
806                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
807                 cas_phy_write(cp, MII_BMCR, ctl);
808                 cas_mif_poll(cp, 1);
809         }
810
811         cp->timer_ticks = 0;
812         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
813 }
814
815 /* Must be invoked under cp->lock. */
816 static int cas_reset_mii_phy(struct cas *cp)
817 {
818         int limit = STOP_TRIES_PHY;
819         u16 val;
820         
821         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
822         udelay(100);
823         while (limit--) {
824                 val = cas_phy_read(cp, MII_BMCR);
825                 if ((val & BMCR_RESET) == 0)
826                         break;
827                 udelay(10);
828         }
829         return (limit <= 0);
830 }
831
832 static void cas_saturn_firmware_load(struct cas *cp)
833 {
834         cas_saturn_patch_t *patch = cas_saturn_patch;
835
836         cas_phy_powerdown(cp);
837
838         /* expanded memory access mode */
839         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
840
841         /* pointer configuration for new firmware */
842         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
843         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
844         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
845         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
846         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
847         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
848         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
849         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
850
851         /* download new firmware */
852         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
853         cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
854         while (patch->addr) {
855                 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
856                 patch++;
857         }
858
859         /* enable firmware */
860         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
861         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
862 }
863
864
865 /* phy initialization */
866 static void cas_phy_init(struct cas *cp)
867 {
868         u16 val;
869
870         /* if we're in MII/GMII mode, set up phy */
871         if (CAS_PHY_MII(cp->phy_type)) {
872                 writel(PCS_DATAPATH_MODE_MII,
873                        cp->regs + REG_PCS_DATAPATH_MODE);
874
875                 cas_mif_poll(cp, 0);
876                 cas_reset_mii_phy(cp); /* take out of isolate mode */
877
878                 if (PHY_LUCENT_B0 == cp->phy_id) {
879                         /* workaround link up/down issue with lucent */
880                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
881                         cas_phy_write(cp, MII_BMCR, 0x00f1);
882                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
883
884                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
885                         /* workarounds for broadcom phy */
886                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
887                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
888                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
889                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
890                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
891                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
892                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
893                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
894                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
895                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
896                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
897
898                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
899                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
900                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
901                         if (val & 0x0080) {
902                                 /* link workaround */
903                                 cas_phy_write(cp, BROADCOM_MII_REG4, 
904                                               val & ~0x0080);
905                         }
906                         
907                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
908                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? 
909                                SATURN_PCFG_FSI : 0x0, 
910                                cp->regs + REG_SATURN_PCFG);
911
912                         /* load firmware to address 10Mbps auto-negotiation
913                          * issue. NOTE: this will need to be changed if the 
914                          * default firmware gets fixed.
915                          */
916                         if (PHY_NS_DP83065 == cp->phy_id) {
917                                 cas_saturn_firmware_load(cp);
918                         }
919                         cas_phy_powerup(cp);
920                 }
921
922                 /* advertise capabilities */
923                 val = cas_phy_read(cp, MII_BMCR);
924                 val &= ~BMCR_ANENABLE;
925                 cas_phy_write(cp, MII_BMCR, val);
926                 udelay(10);
927
928                 cas_phy_write(cp, MII_ADVERTISE,
929                               cas_phy_read(cp, MII_ADVERTISE) |
930                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
931                                ADVERTISE_100HALF | ADVERTISE_100FULL |
932                                CAS_ADVERTISE_PAUSE | 
933                                CAS_ADVERTISE_ASYM_PAUSE));
934                 
935                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
936                         /* make sure that we don't advertise half
937                          * duplex to avoid a chip issue
938                          */
939                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
940                         val &= ~CAS_ADVERTISE_1000HALF;
941                         val |= CAS_ADVERTISE_1000FULL;
942                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
943                 }
944
945         } else {
946                 /* reset pcs for serdes */
947                 u32 val;
948                 int limit;
949
950                 writel(PCS_DATAPATH_MODE_SERDES,
951                        cp->regs + REG_PCS_DATAPATH_MODE);
952
953                 /* enable serdes pins on saturn */
954                 if (cp->cas_flags & CAS_FLAG_SATURN)
955                         writel(0, cp->regs + REG_SATURN_PCFG);
956
957                 /* Reset PCS unit. */
958                 val = readl(cp->regs + REG_PCS_MII_CTRL);
959                 val |= PCS_MII_RESET;
960                 writel(val, cp->regs + REG_PCS_MII_CTRL);
961
962                 limit = STOP_TRIES;
963                 while (limit-- > 0) {
964                         udelay(10);
965                         if ((readl(cp->regs + REG_PCS_MII_CTRL) & 
966                              PCS_MII_RESET) == 0)
967                                 break;
968                 }
969                 if (limit <= 0)
970                         printk(KERN_WARNING "%s: PCS reset bit would not "
971                                "clear [%08x].\n", cp->dev->name,
972                                readl(cp->regs + REG_PCS_STATE_MACHINE));
973
974                 /* Make sure PCS is disabled while changing advertisement
975                  * configuration.
976                  */
977                 writel(0x0, cp->regs + REG_PCS_CFG);
978
979                 /* Advertise all capabilities except half-duplex. */
980                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
981                 val &= ~PCS_MII_ADVERT_HD;
982                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | 
983                         PCS_MII_ADVERT_ASYM_PAUSE);
984                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
985
986                 /* enable PCS */
987                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
988
989                 /* pcs workaround: enable sync detect */
990                 writel(PCS_SERDES_CTRL_SYNCD_EN,
991                        cp->regs + REG_PCS_SERDES_CTRL);
992         }
993 }
994
995
996 static int cas_pcs_link_check(struct cas *cp)
997 {
998         u32 stat, state_machine;
999         int retval = 0;
1000
1001         /* The link status bit latches on zero, so you must
1002          * read it twice in such a case to see a transition
1003          * to the link being up.
1004          */
1005         stat = readl(cp->regs + REG_PCS_MII_STATUS);
1006         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1007                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1008
1009         /* The remote-fault indication is only valid
1010          * when autoneg has completed.
1011          */
1012         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1013                      PCS_MII_STATUS_REMOTE_FAULT)) ==
1014             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
1015                 if (netif_msg_link(cp))
1016                         printk(KERN_INFO "%s: PCS RemoteFault\n", 
1017                                cp->dev->name);
1018         }
1019
1020         /* work around link detection issue by querying the PCS state
1021          * machine directly.
1022          */
1023         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1024         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1025                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1026         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1027                 stat |= PCS_MII_STATUS_LINK_STATUS;
1028         }
1029
1030         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1031                 if (cp->lstate != link_up) {
1032                         if (cp->opened) {
1033                                 cp->lstate = link_up;
1034                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1035                                 
1036                                 cas_set_link_modes(cp);
1037                                 netif_carrier_on(cp->dev);
1038                         }
1039                 }
1040         } else if (cp->lstate == link_up) {
1041                 cp->lstate = link_down;
1042                 if (link_transition_timeout != 0 &&
1043                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1044                     !cp->link_transition_jiffies_valid) {
1045                         /*
1046                          * force a reset, as a workaround for the 
1047                          * link-failure problem. May want to move this to a 
1048                          * point a bit earlier in the sequence. If we had
1049                          * generated a reset a short time ago, we'll wait for
1050                          * the link timer to check the status until a
1051                          * timer expires (link_transistion_jiffies_valid is
1052                          * true when the timer is running.)  Instead of using
1053                          * a system timer, we just do a check whenever the
1054                          * link timer is running - this clears the flag after
1055                          * a suitable delay.
1056                          */
1057                         retval = 1;
1058                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1059                         cp->link_transition_jiffies = jiffies;
1060                         cp->link_transition_jiffies_valid = 1;
1061                 } else {
1062                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1063                 }
1064                 netif_carrier_off(cp->dev);
1065                 if (cp->opened && netif_msg_link(cp)) {
1066                         printk(KERN_INFO "%s: PCS link down.\n",
1067                                cp->dev->name);
1068                 }
1069
1070                 /* Cassini only: if you force a mode, there can be
1071                  * sync problems on link down. to fix that, the following
1072                  * things need to be checked:
1073                  * 1) read serialink state register
1074                  * 2) read pcs status register to verify link down.
1075                  * 3) if link down and serial link == 0x03, then you need
1076                  *    to global reset the chip.
1077                  */
1078                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1079                         /* should check to see if we're in a forced mode */
1080                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1081                         if (stat == 0x03)
1082                                 return 1;
1083                 }
1084         } else if (cp->lstate == link_down) {
1085                 if (link_transition_timeout != 0 &&
1086                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1087                     !cp->link_transition_jiffies_valid) {
1088                         /* force a reset, as a workaround for the
1089                          * link-failure problem.  May want to move
1090                          * this to a point a bit earlier in the
1091                          * sequence.
1092                          */
1093                         retval = 1;
1094                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1095                         cp->link_transition_jiffies = jiffies;
1096                         cp->link_transition_jiffies_valid = 1;
1097                 } else {
1098                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1099                 }
1100         }
1101
1102         return retval;
1103 }
1104
1105 static int cas_pcs_interrupt(struct net_device *dev, 
1106                              struct cas *cp, u32 status)
1107 {
1108         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1109
1110         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0) 
1111                 return 0;
1112         return cas_pcs_link_check(cp);
1113 }
1114
1115 static int cas_txmac_interrupt(struct net_device *dev, 
1116                                struct cas *cp, u32 status)
1117 {
1118         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1119
1120         if (!txmac_stat)
1121                 return 0;
1122
1123         if (netif_msg_intr(cp))
1124                 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1125                         cp->dev->name, txmac_stat);
1126
1127         /* Defer timer expiration is quite normal,
1128          * don't even log the event.
1129          */
1130         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1131             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1132                 return 0;
1133
1134         spin_lock(&cp->stat_lock[0]);
1135         if (txmac_stat & MAC_TX_UNDERRUN) {
1136                 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1137                        dev->name);
1138                 cp->net_stats[0].tx_fifo_errors++;
1139         }
1140
1141         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1142                 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1143                        dev->name);
1144                 cp->net_stats[0].tx_errors++;
1145         }
1146
1147         /* The rest are all cases of one of the 16-bit TX
1148          * counters expiring.
1149          */
1150         if (txmac_stat & MAC_TX_COLL_NORMAL)
1151                 cp->net_stats[0].collisions += 0x10000;
1152
1153         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1154                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1155                 cp->net_stats[0].collisions += 0x10000;
1156         }
1157
1158         if (txmac_stat & MAC_TX_COLL_LATE) {
1159                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1160                 cp->net_stats[0].collisions += 0x10000;
1161         }
1162         spin_unlock(&cp->stat_lock[0]);
1163
1164         /* We do not keep track of MAC_TX_COLL_FIRST and
1165          * MAC_TX_PEAK_ATTEMPTS events.
1166          */
1167         return 0;
1168 }
1169
1170 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware) 
1171 {
1172         cas_hp_inst_t *inst;
1173         u32 val;
1174         int i;
1175
1176         i = 0;
1177         while ((inst = firmware) && inst->note) {
1178                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1179
1180                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1181                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1182                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1183
1184                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1185                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1186                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1187                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1188                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1189                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1190                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1191                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1192
1193                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1194                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1195                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1196                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1197                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1198                 ++firmware;
1199                 ++i;
1200         }
1201 }
1202
1203 static void cas_init_rx_dma(struct cas *cp)
1204 {
1205         u64 desc_dma = cp->block_dvma; 
1206         u32 val;
1207         int i, size;
1208
1209         /* rx free descriptors */
1210         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); 
1211         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1212         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1213         if ((N_RX_DESC_RINGS > 1) &&
1214             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1215                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1216         writel(val, cp->regs + REG_RX_CFG);
1217
1218         val = (unsigned long) cp->init_rxds[0] - 
1219                 (unsigned long) cp->init_block;
1220         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1221         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1222         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1223
1224         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1225                 /* rx desc 2 is for IPSEC packets. however, 
1226                  * we don't it that for that purpose.
1227                  */
1228                 val = (unsigned long) cp->init_rxds[1] - 
1229                         (unsigned long) cp->init_block;
1230                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1231                 writel((desc_dma + val) & 0xffffffff, cp->regs + 
1232                        REG_PLUS_RX_DB1_LOW);
1233                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + 
1234                        REG_PLUS_RX_KICK1);
1235         }
1236         
1237         /* rx completion registers */
1238         val = (unsigned long) cp->init_rxcs[0] - 
1239                 (unsigned long) cp->init_block;
1240         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1241         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1242
1243         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1244                 /* rx comp 2-4 */
1245                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1246                         val = (unsigned long) cp->init_rxcs[i] - 
1247                                 (unsigned long) cp->init_block;
1248                         writel((desc_dma + val) >> 32, cp->regs + 
1249                                REG_PLUS_RX_CBN_HI(i));
1250                         writel((desc_dma + val) & 0xffffffff, cp->regs + 
1251                                REG_PLUS_RX_CBN_LOW(i));
1252                 }
1253         }
1254
1255         /* read selective clear regs to prevent spurious interrupts
1256          * on reset because complete == kick.
1257          * selective clear set up to prevent interrupts on resets
1258          */
1259         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1260         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1261         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1262                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1263                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1264
1265                 /* 2 is different from 3 and 4 */
1266                 if (N_RX_COMP_RINGS > 1)
1267                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1, 
1268                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1269
1270                 for (i = 2; i < N_RX_COMP_RINGS; i++) 
1271                         writel(INTR_RX_DONE_ALT, 
1272                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1273         }
1274
1275         /* set up pause thresholds */
1276         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1277                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1278         val |= CAS_BASE(RX_PAUSE_THRESH_ON, 
1279                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1280         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1281         
1282         /* zero out dma reassembly buffers */
1283         for (i = 0; i < 64; i++) {
1284                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1285                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1286                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1287                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1288         }
1289
1290         /* make sure address register is 0 for normal operation */
1291         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1292         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1293
1294         /* interrupt mitigation */
1295 #ifdef USE_RX_BLANK
1296         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1297         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1298         writel(val, cp->regs + REG_RX_BLANK);
1299 #else
1300         writel(0x0, cp->regs + REG_RX_BLANK);
1301 #endif
1302
1303         /* interrupt generation as a function of low water marks for
1304          * free desc and completion entries. these are used to trigger
1305          * housekeeping for rx descs. we don't use the free interrupt
1306          * as it's not very useful
1307          */
1308         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1309         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1310         writel(val, cp->regs + REG_RX_AE_THRESH);
1311         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1312                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1313                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1314         }
1315
1316         /* Random early detect registers. useful for congestion avoidance.
1317          * this should be tunable.
1318          */
1319         writel(0x0, cp->regs + REG_RX_RED);
1320         
1321         /* receive page sizes. default == 2K (0x800) */
1322         val = 0;
1323         if (cp->page_size == 0x1000)
1324                 val = 0x1;
1325         else if (cp->page_size == 0x2000)
1326                 val = 0x2;
1327         else if (cp->page_size == 0x4000)
1328                 val = 0x3;
1329         
1330         /* round mtu + offset. constrain to page size. */
1331         size = cp->dev->mtu + 64;
1332         if (size > cp->page_size)
1333                 size = cp->page_size;
1334
1335         if (size <= 0x400)
1336                 i = 0x0;
1337         else if (size <= 0x800)
1338                 i = 0x1;
1339         else if (size <= 0x1000)
1340                 i = 0x2;
1341         else
1342                 i = 0x3;
1343
1344         cp->mtu_stride = 1 << (i + 10);
1345         val  = CAS_BASE(RX_PAGE_SIZE, val);
1346         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); 
1347         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1348         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1349         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1350         
1351         /* enable the header parser if desired */
1352         if (CAS_HP_FIRMWARE == cas_prog_null)
1353                 return;
1354
1355         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1356         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1357         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1358         writel(val, cp->regs + REG_HP_CFG);
1359 }
1360
1361 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1362 {
1363         memset(rxc, 0, sizeof(*rxc));
1364         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); 
1365 }
1366
1367 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1368  * flipping is protected by the fact that the chip will not
1369  * hand back the same page index while it's being processed.
1370  */
1371 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1372 {
1373         cas_page_t *page = cp->rx_pages[1][index];
1374         cas_page_t *new;
1375
1376         if (cas_buffer_count(page) == 1)
1377                 return page;
1378
1379         new = cas_page_dequeue(cp);
1380         if (new) {
1381                 spin_lock(&cp->rx_inuse_lock);
1382                 list_add(&page->list, &cp->rx_inuse_list);
1383                 spin_unlock(&cp->rx_inuse_lock);
1384         }
1385         return new;
1386 }
1387                                    
1388 /* this needs to be changed if we actually use the ENC RX DESC ring */
1389 static cas_page_t *cas_page_swap(struct cas *cp, const int ring, 
1390                                  const int index)
1391 {
1392         cas_page_t **page0 = cp->rx_pages[0];
1393         cas_page_t **page1 = cp->rx_pages[1];
1394
1395         /* swap if buffer is in use */
1396         if (cas_buffer_count(page0[index]) > 1) {
1397                 cas_page_t *new = cas_page_spare(cp, index);
1398                 if (new) {
1399                         page1[index] = page0[index];
1400                         page0[index] = new;
1401                 }
1402         } 
1403         RX_USED_SET(page0[index], 0);
1404         return page0[index];
1405 }
1406
1407 static void cas_clean_rxds(struct cas *cp)
1408 {
1409         /* only clean ring 0 as ring 1 is used for spare buffers */
1410         struct cas_rx_desc *rxd = cp->init_rxds[0];
1411         int i, size;
1412
1413         /* release all rx flows */
1414         for (i = 0; i < N_RX_FLOWS; i++) {
1415                 struct sk_buff *skb;
1416                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1417                         cas_skb_release(skb);
1418                 }
1419         }
1420
1421         /* initialize descriptors */
1422         size = RX_DESC_RINGN_SIZE(0);
1423         for (i = 0; i < size; i++) {
1424                 cas_page_t *page = cas_page_swap(cp, 0, i);
1425                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1426                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) | 
1427                                             CAS_BASE(RX_INDEX_RING, 0));
1428         }
1429
1430         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4; 
1431         cp->rx_last[0] = 0;
1432         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1433 }
1434
1435 static void cas_clean_rxcs(struct cas *cp)
1436 {
1437         int i, j;
1438
1439         /* take ownership of rx comp descriptors */
1440         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1441         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1442         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1443                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1444                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1445                         cas_rxc_init(rxc + j);
1446                 }
1447         }
1448 }
1449
1450 #if 0
1451 /* When we get a RX fifo overflow, the RX unit is probably hung
1452  * so we do the following.
1453  *
1454  * If any part of the reset goes wrong, we return 1 and that causes the
1455  * whole chip to be reset.
1456  */
1457 static int cas_rxmac_reset(struct cas *cp)
1458 {
1459         struct net_device *dev = cp->dev;
1460         int limit;
1461         u32 val;
1462
1463         /* First, reset MAC RX. */
1464         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1465         for (limit = 0; limit < STOP_TRIES; limit++) {
1466                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1467                         break;
1468                 udelay(10);
1469         }
1470         if (limit == STOP_TRIES) {
1471                 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1472                        "chip.\n", dev->name);
1473                 return 1;
1474         }
1475
1476         /* Second, disable RX DMA. */
1477         writel(0, cp->regs + REG_RX_CFG);
1478         for (limit = 0; limit < STOP_TRIES; limit++) {
1479                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1480                         break;
1481                 udelay(10);
1482         }
1483         if (limit == STOP_TRIES) {
1484                 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1485                        "chip.\n", dev->name);
1486                 return 1;
1487         }
1488
1489         mdelay(5);
1490
1491         /* Execute RX reset command. */
1492         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1493         for (limit = 0; limit < STOP_TRIES; limit++) {
1494                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1495                         break;
1496                 udelay(10);
1497         }
1498         if (limit == STOP_TRIES) {
1499                 printk(KERN_ERR "%s: RX reset command will not execute, "
1500                        "resetting whole chip.\n", dev->name);
1501                 return 1;
1502         }
1503
1504         /* reset driver rx state */
1505         cas_clean_rxds(cp);
1506         cas_clean_rxcs(cp);
1507
1508         /* Now, reprogram the rest of RX unit. */
1509         cas_init_rx_dma(cp);
1510
1511         /* re-enable */
1512         val = readl(cp->regs + REG_RX_CFG);
1513         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1514         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1515         val = readl(cp->regs + REG_MAC_RX_CFG);
1516         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1517         return 0;
1518 }
1519 #endif
1520
1521 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1522                                u32 status)
1523 {
1524         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1525
1526         if (!stat)
1527                 return 0;
1528
1529         if (netif_msg_intr(cp))
1530                 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1531                         cp->dev->name, stat);
1532
1533         /* these are all rollovers */
1534         spin_lock(&cp->stat_lock[0]);
1535         if (stat & MAC_RX_ALIGN_ERR) 
1536                 cp->net_stats[0].rx_frame_errors += 0x10000;
1537
1538         if (stat & MAC_RX_CRC_ERR)
1539                 cp->net_stats[0].rx_crc_errors += 0x10000;
1540
1541         if (stat & MAC_RX_LEN_ERR)
1542                 cp->net_stats[0].rx_length_errors += 0x10000;
1543
1544         if (stat & MAC_RX_OVERFLOW) {
1545                 cp->net_stats[0].rx_over_errors++;
1546                 cp->net_stats[0].rx_fifo_errors++;
1547         }
1548
1549         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1550          * events.
1551          */
1552         spin_unlock(&cp->stat_lock[0]);
1553         return 0;
1554 }
1555
1556 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1557                              u32 status)
1558 {
1559         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1560
1561         if (!stat)
1562                 return 0;
1563
1564         if (netif_msg_intr(cp))
1565                 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1566                         cp->dev->name, stat);
1567
1568         /* This interrupt is just for pause frame and pause
1569          * tracking.  It is useful for diagnostics and debug
1570          * but probably by default we will mask these events.
1571          */
1572         if (stat & MAC_CTRL_PAUSE_STATE)
1573                 cp->pause_entered++;
1574
1575         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1576                 cp->pause_last_time_recvd = (stat >> 16);
1577
1578         return 0;
1579 }
1580
1581         
1582 /* Must be invoked under cp->lock. */
1583 static inline int cas_mdio_link_not_up(struct cas *cp)
1584 {
1585         u16 val;
1586         
1587         switch (cp->lstate) {
1588         case link_force_ret:
1589                 if (netif_msg_link(cp))
1590                         printk(KERN_INFO "%s: Autoneg failed again, keeping"
1591                                 " forced mode\n", cp->dev->name);
1592                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1593                 cp->timer_ticks = 5;
1594                 cp->lstate = link_force_ok;
1595                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1596                 break;
1597                 
1598         case link_aneg:
1599                 val = cas_phy_read(cp, MII_BMCR);
1600
1601                 /* Try forced modes. we try things in the following order:
1602                  * 1000 full -> 100 full/half -> 10 half
1603                  */
1604                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1605                 val |= BMCR_FULLDPLX;
1606                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 
1607                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1608                 cas_phy_write(cp, MII_BMCR, val);
1609                 cp->timer_ticks = 5;
1610                 cp->lstate = link_force_try;
1611                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1612                 break;
1613
1614         case link_force_try:
1615                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1616                 val = cas_phy_read(cp, MII_BMCR);
1617                 cp->timer_ticks = 5;
1618                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1619                         val &= ~CAS_BMCR_SPEED1000;
1620                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1621                         cas_phy_write(cp, MII_BMCR, val);
1622                         break;
1623                 }
1624
1625                 if (val & BMCR_SPEED100) {
1626                         if (val & BMCR_FULLDPLX) /* fd failed */
1627                                 val &= ~BMCR_FULLDPLX;
1628                         else { /* 100Mbps failed */
1629                                 val &= ~BMCR_SPEED100;
1630                         }
1631                         cas_phy_write(cp, MII_BMCR, val);
1632                         break;
1633                 }
1634         default:
1635                 break;
1636         }
1637         return 0;
1638 }
1639
1640
1641 /* must be invoked with cp->lock held */
1642 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1643 {
1644         int restart;
1645
1646         if (bmsr & BMSR_LSTATUS) {
1647                 /* Ok, here we got a link. If we had it due to a forced
1648                  * fallback, and we were configured for autoneg, we 
1649                  * retry a short autoneg pass. If you know your hub is
1650                  * broken, use ethtool ;)
1651                  */
1652                 if ((cp->lstate == link_force_try) && 
1653                     (cp->link_cntl & BMCR_ANENABLE)) {
1654                         cp->lstate = link_force_ret;
1655                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1656                         cas_mif_poll(cp, 0);
1657                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1658                         cp->timer_ticks = 5;
1659                         if (cp->opened && netif_msg_link(cp))
1660                                 printk(KERN_INFO "%s: Got link after fallback, retrying"
1661                                        " autoneg once...\n", cp->dev->name);
1662                         cas_phy_write(cp, MII_BMCR,
1663                                       cp->link_fcntl | BMCR_ANENABLE |
1664                                       BMCR_ANRESTART);
1665                         cas_mif_poll(cp, 1);
1666
1667                 } else if (cp->lstate != link_up) {
1668                         cp->lstate = link_up;
1669                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1670
1671                         if (cp->opened) {
1672                                 cas_set_link_modes(cp);
1673                                 netif_carrier_on(cp->dev);
1674                         }
1675                 }
1676                 return 0;
1677         }
1678
1679         /* link not up. if the link was previously up, we restart the
1680          * whole process
1681          */
1682         restart = 0;
1683         if (cp->lstate == link_up) {
1684                 cp->lstate = link_down;
1685                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1686
1687                 netif_carrier_off(cp->dev);
1688                 if (cp->opened && netif_msg_link(cp))
1689                         printk(KERN_INFO "%s: Link down\n",
1690                                cp->dev->name);
1691                 restart = 1;
1692                 
1693         } else if (++cp->timer_ticks > 10)
1694                 cas_mdio_link_not_up(cp);
1695                 
1696         return restart;
1697 }
1698
1699 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1700                              u32 status)
1701 {
1702         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1703         u16 bmsr;
1704
1705         /* check for a link change */
1706         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1707                 return 0;
1708
1709         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1710         return cas_mii_link_check(cp, bmsr);
1711 }
1712
1713 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1714                              u32 status)
1715 {
1716         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1717
1718         if (!stat)
1719                 return 0;
1720
1721         printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1722                readl(cp->regs + REG_BIM_DIAG));
1723
1724         /* cassini+ has this reserved */
1725         if ((stat & PCI_ERR_BADACK) &&
1726             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1727                 printk("<No ACK64# during ABS64 cycle> ");
1728
1729         if (stat & PCI_ERR_DTRTO)
1730                 printk("<Delayed transaction timeout> ");
1731         if (stat & PCI_ERR_OTHER)
1732                 printk("<other> ");
1733         if (stat & PCI_ERR_BIM_DMA_WRITE)
1734                 printk("<BIM DMA 0 write req> ");
1735         if (stat & PCI_ERR_BIM_DMA_READ)
1736                 printk("<BIM DMA 0 read req> ");
1737         printk("\n");
1738
1739         if (stat & PCI_ERR_OTHER) {
1740                 u16 cfg;
1741
1742                 /* Interrogate PCI config space for the
1743                  * true cause.
1744                  */
1745                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1746                 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1747                        dev->name, cfg);
1748                 if (cfg & PCI_STATUS_PARITY)
1749                         printk(KERN_ERR "%s: PCI parity error detected.\n",
1750                                dev->name);
1751                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1752                         printk(KERN_ERR "%s: PCI target abort.\n",
1753                                dev->name);
1754                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1755                         printk(KERN_ERR "%s: PCI master acks target abort.\n",
1756                                dev->name);
1757                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1758                         printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1759                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1760                         printk(KERN_ERR "%s: PCI system error SERR#.\n",
1761                                dev->name);
1762                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1763                         printk(KERN_ERR "%s: PCI parity error.\n",
1764                                dev->name);
1765
1766                 /* Write the error bits back to clear them. */
1767                 cfg &= (PCI_STATUS_PARITY |
1768                         PCI_STATUS_SIG_TARGET_ABORT |
1769                         PCI_STATUS_REC_TARGET_ABORT |
1770                         PCI_STATUS_REC_MASTER_ABORT |
1771                         PCI_STATUS_SIG_SYSTEM_ERROR |
1772                         PCI_STATUS_DETECTED_PARITY);
1773                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1774         }
1775
1776         /* For all PCI errors, we should reset the chip. */
1777         return 1;
1778 }
1779
1780 /* All non-normal interrupt conditions get serviced here.
1781  * Returns non-zero if we should just exit the interrupt
1782  * handler right now (ie. if we reset the card which invalidates
1783  * all of the other original irq status bits).
1784  */
1785 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1786                             u32 status)
1787 {
1788         if (status & INTR_RX_TAG_ERROR) {
1789                 /* corrupt RX tag framing */
1790                 if (netif_msg_rx_err(cp))
1791                         printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1792                                 cp->dev->name);
1793                 spin_lock(&cp->stat_lock[0]);
1794                 cp->net_stats[0].rx_errors++;
1795                 spin_unlock(&cp->stat_lock[0]);
1796                 goto do_reset;
1797         }
1798
1799         if (status & INTR_RX_LEN_MISMATCH) {
1800                 /* length mismatch. */
1801                 if (netif_msg_rx_err(cp))
1802                         printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1803                                 cp->dev->name);
1804                 spin_lock(&cp->stat_lock[0]);
1805                 cp->net_stats[0].rx_errors++;
1806                 spin_unlock(&cp->stat_lock[0]);
1807                 goto do_reset;
1808         }
1809
1810         if (status & INTR_PCS_STATUS) {
1811                 if (cas_pcs_interrupt(dev, cp, status))
1812                         goto do_reset;
1813         }
1814
1815         if (status & INTR_TX_MAC_STATUS) {
1816                 if (cas_txmac_interrupt(dev, cp, status))
1817                         goto do_reset;
1818         }
1819
1820         if (status & INTR_RX_MAC_STATUS) {
1821                 if (cas_rxmac_interrupt(dev, cp, status))
1822                         goto do_reset;
1823         }
1824
1825         if (status & INTR_MAC_CTRL_STATUS) {
1826                 if (cas_mac_interrupt(dev, cp, status))
1827                         goto do_reset;
1828         }
1829
1830         if (status & INTR_MIF_STATUS) {
1831                 if (cas_mif_interrupt(dev, cp, status))
1832                         goto do_reset;
1833         }
1834
1835         if (status & INTR_PCI_ERROR_STATUS) {
1836                 if (cas_pci_interrupt(dev, cp, status))
1837                         goto do_reset;
1838         }
1839         return 0;
1840
1841 do_reset:
1842 #if 1
1843         atomic_inc(&cp->reset_task_pending);
1844         atomic_inc(&cp->reset_task_pending_all);
1845         printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1846                dev->name, status);
1847         schedule_work(&cp->reset_task);
1848 #else
1849         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1850         printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1851         schedule_work(&cp->reset_task);
1852 #endif
1853         return 1;
1854 }
1855
1856 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1857  *       determining whether to do a netif_stop/wakeup
1858  */
1859 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1860 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1861 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1862                                   const int len)
1863 {
1864         unsigned long off = addr + len;
1865
1866         if (CAS_TABORT(cp) == 1)
1867                 return 0;
1868         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1869                 return 0;
1870         return TX_TARGET_ABORT_LEN;
1871 }
1872
1873 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1874 {
1875         struct cas_tx_desc *txds;
1876         struct sk_buff **skbs;
1877         struct net_device *dev = cp->dev;
1878         int entry, count;
1879
1880         spin_lock(&cp->tx_lock[ring]);
1881         txds = cp->init_txds[ring];
1882         skbs = cp->tx_skbs[ring];
1883         entry = cp->tx_old[ring];
1884
1885         count = TX_BUFF_COUNT(ring, entry, limit);
1886         while (entry != limit) {
1887                 struct sk_buff *skb = skbs[entry];
1888                 dma_addr_t daddr;
1889                 u32 dlen;
1890                 int frag;
1891
1892                 if (!skb) {
1893                         /* this should never occur */
1894                         entry = TX_DESC_NEXT(ring, entry);
1895                         continue;
1896                 }
1897
1898                 /* however, we might get only a partial skb release. */
1899                 count -= skb_shinfo(skb)->nr_frags +
1900                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1901                 if (count < 0)
1902                         break;
1903
1904                 if (netif_msg_tx_done(cp))
1905                         printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1906                                cp->dev->name, ring, entry);
1907
1908                 skbs[entry] = NULL;
1909                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1910                 
1911                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1912                         struct cas_tx_desc *txd = txds + entry;
1913
1914                         daddr = le64_to_cpu(txd->buffer);
1915                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1916                                        le64_to_cpu(txd->control));
1917                         pci_unmap_page(cp->pdev, daddr, dlen,
1918                                        PCI_DMA_TODEVICE);
1919                         entry = TX_DESC_NEXT(ring, entry);
1920
1921                         /* tiny buffer may follow */
1922                         if (cp->tx_tiny_use[ring][entry].used) {
1923                                 cp->tx_tiny_use[ring][entry].used = 0;
1924                                 entry = TX_DESC_NEXT(ring, entry);
1925                         } 
1926                 }
1927
1928                 spin_lock(&cp->stat_lock[ring]);
1929                 cp->net_stats[ring].tx_packets++;
1930                 cp->net_stats[ring].tx_bytes += skb->len;
1931                 spin_unlock(&cp->stat_lock[ring]);
1932                 dev_kfree_skb_irq(skb);
1933         }
1934         cp->tx_old[ring] = entry;
1935
1936         /* this is wrong for multiple tx rings. the net device needs
1937          * multiple queues for this to do the right thing.  we wait
1938          * for 2*packets to be available when using tiny buffers
1939          */
1940         if (netif_queue_stopped(dev) &&
1941             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1942                 netif_wake_queue(dev);
1943         spin_unlock(&cp->tx_lock[ring]);
1944 }
1945
1946 static void cas_tx(struct net_device *dev, struct cas *cp,
1947                    u32 status)
1948 {
1949         int limit, ring;
1950 #ifdef USE_TX_COMPWB
1951         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1952 #endif
1953         if (netif_msg_intr(cp))
1954                 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1955                         cp->dev->name, status, (unsigned long long)compwb);
1956         /* process all the rings */
1957         for (ring = 0; ring < N_TX_RINGS; ring++) {
1958 #ifdef USE_TX_COMPWB
1959                 /* use the completion writeback registers */
1960                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1961                         CAS_VAL(TX_COMPWB_LSB, compwb);
1962                 compwb = TX_COMPWB_NEXT(compwb);
1963 #else
1964                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1965 #endif
1966                 if (cp->tx_old[ring] != limit) 
1967                         cas_tx_ringN(cp, ring, limit);
1968         }
1969 }
1970
1971
1972 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc, 
1973                               int entry, const u64 *words, 
1974                               struct sk_buff **skbref)
1975 {
1976         int dlen, hlen, len, i, alloclen;
1977         int off, swivel = RX_SWIVEL_OFF_VAL;
1978         struct cas_page *page;
1979         struct sk_buff *skb;
1980         void *addr, *crcaddr;
1981         char *p; 
1982
1983         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1984         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1985         len  = hlen + dlen;
1986
1987         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT)) 
1988                 alloclen = len;
1989         else 
1990                 alloclen = max(hlen, RX_COPY_MIN);
1991
1992         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1993         if (skb == NULL) 
1994                 return -1;
1995
1996         *skbref = skb;
1997         skb->dev = cp->dev;
1998         skb_reserve(skb, swivel);
1999
2000         p = skb->data;
2001         addr = crcaddr = NULL;
2002         if (hlen) { /* always copy header pages */
2003                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2004                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2005                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 + 
2006                         swivel;
2007
2008                 i = hlen;
2009                 if (!dlen) /* attach FCS */
2010                         i += cp->crc_size;
2011                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2012                                     PCI_DMA_FROMDEVICE);
2013                 addr = cas_page_map(page->buffer);
2014                 memcpy(p, addr + off, i);
2015                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2016                                     PCI_DMA_FROMDEVICE);
2017                 cas_page_unmap(addr);
2018                 RX_USED_ADD(page, 0x100);
2019                 p += hlen;
2020                 swivel = 0;
2021         } 
2022
2023
2024         if (alloclen < (hlen + dlen)) {
2025                 skb_frag_t *frag = skb_shinfo(skb)->frags;
2026
2027                 /* normal or jumbo packets. we use frags */
2028                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2029                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2030                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2031
2032                 hlen = min(cp->page_size - off, dlen);
2033                 if (hlen < 0) {
2034                         if (netif_msg_rx_err(cp)) {
2035                                 printk(KERN_DEBUG "%s: rx page overflow: "
2036                                        "%d\n", cp->dev->name, hlen);
2037                         }
2038                         dev_kfree_skb_irq(skb);
2039                         return -1;
2040                 }
2041                 i = hlen;
2042                 if (i == dlen)  /* attach FCS */
2043                         i += cp->crc_size;
2044                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2045                                     PCI_DMA_FROMDEVICE);
2046
2047                 /* make sure we always copy a header */
2048                 swivel = 0;
2049                 if (p == (char *) skb->data) { /* not split */
2050                         addr = cas_page_map(page->buffer);
2051                         memcpy(p, addr + off, RX_COPY_MIN);
2052                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2053                                         PCI_DMA_FROMDEVICE);
2054                         cas_page_unmap(addr);
2055                         off += RX_COPY_MIN;
2056                         swivel = RX_COPY_MIN;
2057                         RX_USED_ADD(page, cp->mtu_stride);
2058                 } else {
2059                         RX_USED_ADD(page, hlen);
2060                 }
2061                 skb_put(skb, alloclen);
2062
2063                 skb_shinfo(skb)->nr_frags++;
2064                 skb->data_len += hlen - swivel;
2065                 skb->len      += hlen - swivel;
2066
2067                 get_page(page->buffer);
2068                 cas_buffer_inc(page);
2069                 frag->page = page->buffer;
2070                 frag->page_offset = off;
2071                 frag->size = hlen - swivel;
2072                 
2073                 /* any more data? */
2074                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2075                         hlen = dlen;
2076                         off = 0;
2077
2078                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2079                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2080                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, 
2081                                             hlen + cp->crc_size, 
2082                                             PCI_DMA_FROMDEVICE);
2083                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2084                                             hlen + cp->crc_size,
2085                                             PCI_DMA_FROMDEVICE);
2086
2087                         skb_shinfo(skb)->nr_frags++;
2088                         skb->data_len += hlen;
2089                         skb->len      += hlen; 
2090                         frag++;
2091
2092                         get_page(page->buffer);
2093                         cas_buffer_inc(page);
2094                         frag->page = page->buffer;
2095                         frag->page_offset = 0;
2096                         frag->size = hlen;
2097                         RX_USED_ADD(page, hlen + cp->crc_size);
2098                 }
2099
2100                 if (cp->crc_size) {
2101                         addr = cas_page_map(page->buffer);
2102                         crcaddr  = addr + off + hlen;
2103                 }
2104
2105         } else {
2106                 /* copying packet */
2107                 if (!dlen)
2108                         goto end_copy_pkt;
2109
2110                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2111                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2112                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2113                 hlen = min(cp->page_size - off, dlen);
2114                 if (hlen < 0) {
2115                         if (netif_msg_rx_err(cp)) {
2116                                 printk(KERN_DEBUG "%s: rx page overflow: "
2117                                        "%d\n", cp->dev->name, hlen);
2118                         }
2119                         dev_kfree_skb_irq(skb);
2120                         return -1;
2121                 }
2122                 i = hlen;
2123                 if (i == dlen) /* attach FCS */
2124                         i += cp->crc_size;
2125                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2126                                     PCI_DMA_FROMDEVICE);
2127                 addr = cas_page_map(page->buffer);
2128                 memcpy(p, addr + off, i);
2129                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2130                                     PCI_DMA_FROMDEVICE);
2131                 cas_page_unmap(addr);
2132                 if (p == (char *) skb->data) /* not split */
2133                         RX_USED_ADD(page, cp->mtu_stride);
2134                 else
2135                         RX_USED_ADD(page, i);
2136         
2137                 /* any more data? */
2138                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2139                         p += hlen;
2140                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2141                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2142                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, 
2143                                             dlen + cp->crc_size, 
2144                                             PCI_DMA_FROMDEVICE);
2145                         addr = cas_page_map(page->buffer);
2146                         memcpy(p, addr, dlen + cp->crc_size);
2147                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2148                                             dlen + cp->crc_size,
2149                                             PCI_DMA_FROMDEVICE);
2150                         cas_page_unmap(addr);
2151                         RX_USED_ADD(page, dlen + cp->crc_size); 
2152                 }
2153 end_copy_pkt:
2154                 if (cp->crc_size) {
2155                         addr    = NULL;
2156                         crcaddr = skb->data + alloclen;
2157                 }
2158                 skb_put(skb, alloclen);
2159         }
2160
2161         i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
2162         if (cp->crc_size) {
2163                 /* checksum includes FCS. strip it out. */
2164                 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
2165                 if (addr)
2166                         cas_page_unmap(addr);
2167         }
2168         skb->csum = ntohs(i ^ 0xffff);
2169         skb->ip_summed = CHECKSUM_HW;
2170         skb->protocol = eth_type_trans(skb, cp->dev);
2171         return len;
2172 }
2173
2174
2175 /* we can handle up to 64 rx flows at a time. we do the same thing
2176  * as nonreassm except that we batch up the buffers. 
2177  * NOTE: we currently just treat each flow as a bunch of packets that
2178  *       we pass up. a better way would be to coalesce the packets
2179  *       into a jumbo packet. to do that, we need to do the following:
2180  *       1) the first packet will have a clean split between header and
2181  *          data. save both.
2182  *       2) each time the next flow packet comes in, extend the
2183  *          data length and merge the checksums.
2184  *       3) on flow release, fix up the header.
2185  *       4) make sure the higher layer doesn't care.
2186  * because packets get coalesced, we shouldn't run into fragment count 
2187  * issues.
2188  */
2189 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2190                                    struct sk_buff *skb)
2191 {
2192         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2193         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2194         
2195         /* this is protected at a higher layer, so no need to 
2196          * do any additional locking here. stick the buffer
2197          * at the end.
2198          */
2199         __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2200         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2201                 while ((skb = __skb_dequeue(flow))) {
2202                         cas_skb_release(skb);
2203                 }
2204         }
2205 }
2206
2207 /* put rx descriptor back on ring. if a buffer is in use by a higher
2208  * layer, this will need to put in a replacement.
2209  */
2210 static void cas_post_page(struct cas *cp, const int ring, const int index)
2211 {
2212         cas_page_t *new;
2213         int entry;
2214
2215         entry = cp->rx_old[ring];
2216
2217         new = cas_page_swap(cp, ring, index);
2218         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2219         cp->init_rxds[ring][entry].index  =
2220                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) | 
2221                             CAS_BASE(RX_INDEX_RING, ring));
2222
2223         entry = RX_DESC_ENTRY(ring, entry + 1);
2224         cp->rx_old[ring] = entry;
2225         
2226         if (entry % 4)
2227                 return;
2228
2229         if (ring == 0)
2230                 writel(entry, cp->regs + REG_RX_KICK);
2231         else if ((N_RX_DESC_RINGS > 1) &&
2232                  (cp->cas_flags & CAS_FLAG_REG_PLUS)) 
2233                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2234 }
2235
2236
2237 /* only when things are bad */
2238 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2239 {
2240         unsigned int entry, last, count, released;
2241         int cluster;
2242         cas_page_t **page = cp->rx_pages[ring];
2243
2244         entry = cp->rx_old[ring];
2245
2246         if (netif_msg_intr(cp))
2247                 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2248                        cp->dev->name, ring, entry);
2249
2250         cluster = -1;
2251         count = entry & 0x3; 
2252         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2253         released = 0;
2254         while (entry != last) {
2255                 /* make a new buffer if it's still in use */
2256                 if (cas_buffer_count(page[entry]) > 1) {
2257                         cas_page_t *new = cas_page_dequeue(cp);
2258                         if (!new) {
2259                                 /* let the timer know that we need to 
2260                                  * do this again
2261                                  */
2262                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2263                                 if (!timer_pending(&cp->link_timer))
2264                                         mod_timer(&cp->link_timer, jiffies + 
2265                                                   CAS_LINK_FAST_TIMEOUT);
2266                                 cp->rx_old[ring]  = entry;
2267                                 cp->rx_last[ring] = num ? num - released : 0;
2268                                 return -ENOMEM;
2269                         }
2270                         spin_lock(&cp->rx_inuse_lock);
2271                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2272                         spin_unlock(&cp->rx_inuse_lock);
2273                         cp->init_rxds[ring][entry].buffer = 
2274                                 cpu_to_le64(new->dma_addr);
2275                         page[entry] = new;
2276                         
2277                 }
2278
2279                 if (++count == 4) {
2280                         cluster = entry;
2281                         count = 0;
2282                 }
2283                 released++;
2284                 entry = RX_DESC_ENTRY(ring, entry + 1);
2285         }
2286         cp->rx_old[ring] = entry;
2287
2288         if (cluster < 0) 
2289                 return 0;
2290
2291         if (ring == 0)
2292                 writel(cluster, cp->regs + REG_RX_KICK);
2293         else if ((N_RX_DESC_RINGS > 1) &&
2294                  (cp->cas_flags & CAS_FLAG_REG_PLUS)) 
2295                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2296         return 0;
2297 }
2298
2299
2300 /* process a completion ring. packets are set up in three basic ways:
2301  * small packets: should be copied header + data in single buffer.
2302  * large packets: header and data in a single buffer.
2303  * split packets: header in a separate buffer from data. 
2304  *                data may be in multiple pages. data may be > 256
2305  *                bytes but in a single page. 
2306  *
2307  * NOTE: RX page posting is done in this routine as well. while there's
2308  *       the capability of using multiple RX completion rings, it isn't
2309  *       really worthwhile due to the fact that the page posting will
2310  *       force serialization on the single descriptor ring. 
2311  */
2312 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2313 {
2314         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2315         int entry, drops;
2316         int npackets = 0;
2317
2318         if (netif_msg_intr(cp))
2319                 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2320                        cp->dev->name, ring,
2321                        readl(cp->regs + REG_RX_COMP_HEAD), 
2322                        cp->rx_new[ring]);
2323
2324         entry = cp->rx_new[ring];
2325         drops = 0;
2326         while (1) {
2327                 struct cas_rx_comp *rxc = rxcs + entry;
2328                 struct sk_buff *skb;
2329                 int type, len;
2330                 u64 words[4];
2331                 int i, dring;
2332
2333                 words[0] = le64_to_cpu(rxc->word1);
2334                 words[1] = le64_to_cpu(rxc->word2);
2335                 words[2] = le64_to_cpu(rxc->word3);
2336                 words[3] = le64_to_cpu(rxc->word4);
2337
2338                 /* don't touch if still owned by hw */
2339                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2340                 if (type == 0)
2341                         break;
2342
2343                 /* hw hasn't cleared the zero bit yet */
2344                 if (words[3] & RX_COMP4_ZERO) {
2345                         break;
2346                 }
2347
2348                 /* get info on the packet */
2349                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2350                         spin_lock(&cp->stat_lock[ring]);
2351                         cp->net_stats[ring].rx_errors++;
2352                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2353                                 cp->net_stats[ring].rx_length_errors++;
2354                         if (words[3] & RX_COMP4_BAD)
2355                                 cp->net_stats[ring].rx_crc_errors++;
2356                         spin_unlock(&cp->stat_lock[ring]);
2357
2358                         /* We'll just return it to Cassini. */
2359                 drop_it:
2360                         spin_lock(&cp->stat_lock[ring]);
2361                         ++cp->net_stats[ring].rx_dropped;
2362                         spin_unlock(&cp->stat_lock[ring]);
2363                         goto next;
2364                 }
2365
2366                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2367                 if (len < 0) {
2368                         ++drops;
2369                         goto drop_it;
2370                 }
2371
2372                 /* see if it's a flow re-assembly or not. the driver
2373                  * itself handles release back up.
2374                  */
2375                 if (RX_DONT_BATCH || (type == 0x2)) {
2376                         /* non-reassm: these always get released */
2377                         cas_skb_release(skb); 
2378                 } else {
2379                         cas_rx_flow_pkt(cp, words, skb);
2380                 }
2381
2382                 spin_lock(&cp->stat_lock[ring]);
2383                 cp->net_stats[ring].rx_packets++;
2384                 cp->net_stats[ring].rx_bytes += len;
2385                 spin_unlock(&cp->stat_lock[ring]);
2386                 cp->dev->last_rx = jiffies;
2387
2388         next:
2389                 npackets++;
2390
2391                 /* should it be released? */
2392                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2393                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2394                         dring = CAS_VAL(RX_INDEX_RING, i);
2395                         i = CAS_VAL(RX_INDEX_NUM, i);
2396                         cas_post_page(cp, dring, i);
2397                 }
2398                 
2399                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2400                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2401                         dring = CAS_VAL(RX_INDEX_RING, i);
2402                         i = CAS_VAL(RX_INDEX_NUM, i);
2403                         cas_post_page(cp, dring, i);
2404                 }
2405
2406                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2407                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2408                         dring = CAS_VAL(RX_INDEX_RING, i);
2409                         i = CAS_VAL(RX_INDEX_NUM, i);
2410                         cas_post_page(cp, dring, i);
2411                 }
2412
2413                 /* skip to the next entry */
2414                 entry = RX_COMP_ENTRY(ring, entry + 1 + 
2415                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2416 #ifdef USE_NAPI
2417                 if (budget && (npackets >= budget))
2418                         break;
2419 #endif
2420         }
2421         cp->rx_new[ring] = entry;
2422
2423         if (drops)
2424                 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2425                        cp->dev->name);
2426         return npackets;
2427 }
2428
2429
2430 /* put completion entries back on the ring */
2431 static void cas_post_rxcs_ringN(struct net_device *dev,
2432                                 struct cas *cp, int ring)
2433 {
2434         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2435         int last, entry;
2436
2437         last = cp->rx_cur[ring];
2438         entry = cp->rx_new[ring]; 
2439         if (netif_msg_intr(cp))
2440                 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2441                        dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2442                        entry);
2443         
2444         /* zero and re-mark descriptors */
2445         while (last != entry) {
2446                 cas_rxc_init(rxc + last);
2447                 last = RX_COMP_ENTRY(ring, last + 1);
2448         }
2449         cp->rx_cur[ring] = last;
2450
2451         if (ring == 0)
2452                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2453         else if (cp->cas_flags & CAS_FLAG_REG_PLUS) 
2454                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2455 }
2456
2457
2458
2459 /* cassini can use all four PCI interrupts for the completion ring. 
2460  * rings 3 and 4 are identical
2461  */
2462 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2463 static inline void cas_handle_irqN(struct net_device *dev, 
2464                                    struct cas *cp, const u32 status,
2465                                    const int ring)
2466 {
2467         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT)) 
2468                 cas_post_rxcs_ringN(dev, cp, ring);
2469 }
2470
2471 static irqreturn_t cas_interruptN(int irq, void *dev_id, struct pt_regs *regs)
2472 {
2473         struct net_device *dev = dev_id;
2474         struct cas *cp = netdev_priv(dev);
2475         unsigned long flags;
2476         int ring;
2477         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2478
2479         /* check for shared irq */
2480         if (status == 0)
2481                 return IRQ_NONE;
2482
2483         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2484         spin_lock_irqsave(&cp->lock, flags);
2485         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2486 #ifdef USE_NAPI
2487                 cas_mask_intr(cp);
2488                 netif_rx_schedule(dev);
2489 #else
2490                 cas_rx_ringN(cp, ring, 0);
2491 #endif
2492                 status &= ~INTR_RX_DONE_ALT;
2493         }
2494
2495         if (status)
2496                 cas_handle_irqN(dev, cp, status, ring);
2497         spin_unlock_irqrestore(&cp->lock, flags);
2498         return IRQ_HANDLED;
2499 }
2500 #endif
2501
2502 #ifdef USE_PCI_INTB
2503 /* everything but rx packets */
2504 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2505 {
2506         if (status & INTR_RX_BUF_UNAVAIL_1) {
2507                 /* Frame arrived, no free RX buffers available. 
2508                  * NOTE: we can get this on a link transition. */
2509                 cas_post_rxds_ringN(cp, 1, 0);
2510                 spin_lock(&cp->stat_lock[1]);
2511                 cp->net_stats[1].rx_dropped++;
2512                 spin_unlock(&cp->stat_lock[1]);
2513         }
2514
2515         if (status & INTR_RX_BUF_AE_1) 
2516                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - 
2517                                     RX_AE_FREEN_VAL(1));
2518
2519         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2520                 cas_post_rxcs_ringN(cp, 1);
2521 }
2522
2523 /* ring 2 handles a few more events than 3 and 4 */
2524 static irqreturn_t cas_interrupt1(int irq, void *dev_id, struct pt_regs *regs)
2525 {
2526         struct net_device *dev = dev_id;
2527         struct cas *cp = netdev_priv(dev);
2528         unsigned long flags;
2529         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2530
2531         /* check for shared interrupt */
2532         if (status == 0)
2533                 return IRQ_NONE;
2534
2535         spin_lock_irqsave(&cp->lock, flags);
2536         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2537 #ifdef USE_NAPI
2538                 cas_mask_intr(cp);
2539                 netif_rx_schedule(dev);
2540 #else
2541                 cas_rx_ringN(cp, 1, 0);
2542 #endif
2543                 status &= ~INTR_RX_DONE_ALT;
2544         }
2545         if (status)
2546                 cas_handle_irq1(cp, status);
2547         spin_unlock_irqrestore(&cp->lock, flags);
2548         return IRQ_HANDLED;
2549 }
2550 #endif
2551
2552 static inline void cas_handle_irq(struct net_device *dev,
2553                                   struct cas *cp, const u32 status)
2554 {
2555         /* housekeeping interrupts */
2556         if (status & INTR_ERROR_MASK)
2557                 cas_abnormal_irq(dev, cp, status);
2558
2559         if (status & INTR_RX_BUF_UNAVAIL) {
2560                 /* Frame arrived, no free RX buffers available. 
2561                  * NOTE: we can get this on a link transition.
2562                  */
2563                 cas_post_rxds_ringN(cp, 0, 0);
2564                 spin_lock(&cp->stat_lock[0]);
2565                 cp->net_stats[0].rx_dropped++;
2566                 spin_unlock(&cp->stat_lock[0]);
2567         } else if (status & INTR_RX_BUF_AE) {
2568                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2569                                     RX_AE_FREEN_VAL(0));
2570         }
2571
2572         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2573                 cas_post_rxcs_ringN(dev, cp, 0);
2574 }
2575
2576 static irqreturn_t cas_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2577 {
2578         struct net_device *dev = dev_id;
2579         struct cas *cp = netdev_priv(dev);
2580         unsigned long flags;
2581         u32 status = readl(cp->regs + REG_INTR_STATUS);
2582
2583         if (status == 0)
2584                 return IRQ_NONE;
2585
2586         spin_lock_irqsave(&cp->lock, flags);
2587         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2588                 cas_tx(dev, cp, status);
2589                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2590         }
2591
2592         if (status & INTR_RX_DONE) {
2593 #ifdef USE_NAPI
2594                 cas_mask_intr(cp);
2595                 netif_rx_schedule(dev);
2596 #else
2597                 cas_rx_ringN(cp, 0, 0);
2598 #endif
2599                 status &= ~INTR_RX_DONE;
2600         }
2601
2602         if (status)
2603                 cas_handle_irq(dev, cp, status);
2604         spin_unlock_irqrestore(&cp->lock, flags);
2605         return IRQ_HANDLED;
2606 }
2607
2608
2609 #ifdef USE_NAPI
2610 static int cas_poll(struct net_device *dev, int *budget)
2611 {
2612         struct cas *cp = netdev_priv(dev);
2613         int i, enable_intr, todo, credits;
2614         u32 status = readl(cp->regs + REG_INTR_STATUS);
2615         unsigned long flags;
2616
2617         spin_lock_irqsave(&cp->lock, flags);
2618         cas_tx(dev, cp, status);
2619         spin_unlock_irqrestore(&cp->lock, flags);
2620
2621         /* NAPI rx packets. we spread the credits across all of the
2622          * rxc rings
2623          */
2624         todo = min(*budget, dev->quota);
2625
2626         /* to make sure we're fair with the work we loop through each
2627          * ring N_RX_COMP_RING times with a request of 
2628          * todo / N_RX_COMP_RINGS
2629          */
2630         enable_intr = 1;
2631         credits = 0;
2632         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2633                 int j;
2634                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2635                         credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS);
2636                         if (credits >= todo) {
2637                                 enable_intr = 0;
2638                                 goto rx_comp;
2639                         }
2640                 }
2641         }
2642
2643 rx_comp:
2644         *budget    -= credits;
2645         dev->quota -= credits;
2646
2647         /* final rx completion */
2648         spin_lock_irqsave(&cp->lock, flags);
2649         if (status)
2650                 cas_handle_irq(dev, cp, status);
2651
2652 #ifdef USE_PCI_INTB
2653         if (N_RX_COMP_RINGS > 1) {
2654                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2655                 if (status)
2656                         cas_handle_irq1(dev, cp, status);
2657         }
2658 #endif
2659
2660 #ifdef USE_PCI_INTC
2661         if (N_RX_COMP_RINGS > 2) {
2662                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2663                 if (status)
2664                         cas_handle_irqN(dev, cp, status, 2);
2665         }
2666 #endif
2667
2668 #ifdef USE_PCI_INTD
2669         if (N_RX_COMP_RINGS > 3) {
2670                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2671                 if (status)
2672                         cas_handle_irqN(dev, cp, status, 3);
2673         }
2674 #endif
2675         spin_unlock_irqrestore(&cp->lock, flags);
2676         if (enable_intr) {
2677                 netif_rx_complete(dev);
2678                 cas_unmask_intr(cp);
2679                 return 0;
2680         }
2681         return 1;
2682 }
2683 #endif
2684
2685 #ifdef CONFIG_NET_POLL_CONTROLLER
2686 static void cas_netpoll(struct net_device *dev)
2687 {
2688         struct cas *cp = netdev_priv(dev);
2689
2690         cas_disable_irq(cp, 0);
2691         cas_interrupt(cp->pdev->irq, dev, NULL);
2692         cas_enable_irq(cp, 0);
2693
2694 #ifdef USE_PCI_INTB
2695         if (N_RX_COMP_RINGS > 1) {
2696                 /* cas_interrupt1(); */
2697         }
2698 #endif
2699 #ifdef USE_PCI_INTC
2700         if (N_RX_COMP_RINGS > 2) {
2701                 /* cas_interruptN(); */
2702         }
2703 #endif
2704 #ifdef USE_PCI_INTD
2705         if (N_RX_COMP_RINGS > 3) {
2706                 /* cas_interruptN(); */
2707         }
2708 #endif
2709 }
2710 #endif
2711
2712 static void cas_tx_timeout(struct net_device *dev)
2713 {
2714         struct cas *cp = netdev_priv(dev);
2715
2716         printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2717         if (!cp->hw_running) {
2718                 printk("%s: hrm.. hw not running!\n", dev->name);
2719                 return;
2720         }
2721
2722         printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2723                dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2724
2725         printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2726                dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2727
2728         printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2729                "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2730                dev->name,
2731                readl(cp->regs + REG_TX_CFG),
2732                readl(cp->regs + REG_MAC_TX_STATUS),
2733                readl(cp->regs + REG_MAC_TX_CFG),
2734                readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2735                readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2736                readl(cp->regs + REG_TX_FIFO_READ_PTR),
2737                readl(cp->regs + REG_TX_SM_1),
2738                readl(cp->regs + REG_TX_SM_2));
2739
2740         printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2741                dev->name,
2742                readl(cp->regs + REG_RX_CFG),
2743                readl(cp->regs + REG_MAC_RX_STATUS),
2744                readl(cp->regs + REG_MAC_RX_CFG));
2745
2746         printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2747                dev->name,
2748                readl(cp->regs + REG_HP_STATE_MACHINE),
2749                readl(cp->regs + REG_HP_STATUS0),
2750                readl(cp->regs + REG_HP_STATUS1),
2751                readl(cp->regs + REG_HP_STATUS2));
2752
2753 #if 1
2754         atomic_inc(&cp->reset_task_pending);
2755         atomic_inc(&cp->reset_task_pending_all);
2756         schedule_work(&cp->reset_task);
2757 #else
2758         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2759         schedule_work(&cp->reset_task);
2760 #endif
2761 }
2762
2763 static inline int cas_intme(int ring, int entry)
2764 {
2765         /* Algorithm: IRQ every 1/2 of descriptors. */
2766         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2767                 return 1;
2768         return 0;
2769 }
2770
2771
2772 static void cas_write_txd(struct cas *cp, int ring, int entry,
2773                           dma_addr_t mapping, int len, u64 ctrl, int last)
2774 {
2775         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2776
2777         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2778         if (cas_intme(ring, entry))
2779                 ctrl |= TX_DESC_INTME;
2780         if (last)
2781                 ctrl |= TX_DESC_EOF;
2782         txd->control = cpu_to_le64(ctrl);
2783         txd->buffer = cpu_to_le64(mapping);
2784 }
2785
2786 static inline void *tx_tiny_buf(struct cas *cp, const int ring, 
2787                                 const int entry)
2788 {
2789         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2790 }
2791
2792 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring, 
2793                                      const int entry, const int tentry)
2794 {
2795         cp->tx_tiny_use[ring][tentry].nbufs++;
2796         cp->tx_tiny_use[ring][entry].used = 1;
2797         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2798 }
2799
2800 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring, 
2801                                     struct sk_buff *skb)
2802 {
2803         struct net_device *dev = cp->dev;
2804         int entry, nr_frags, frag, tabort, tentry;
2805         dma_addr_t mapping;
2806         unsigned long flags;
2807         u64 ctrl;
2808         u32 len;
2809
2810         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2811
2812         /* This is a hard error, log it. */
2813         if (TX_BUFFS_AVAIL(cp, ring) <= 
2814             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2815                 netif_stop_queue(dev);
2816                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2817                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2818                        "queue awake!\n", dev->name);
2819                 return 1;
2820         }
2821
2822         ctrl = 0;
2823         if (skb->ip_summed == CHECKSUM_HW) {
2824                 u64 csum_start_off, csum_stuff_off;
2825
2826                 csum_start_off = (u64) (skb->h.raw - skb->data);
2827                 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
2828
2829                 ctrl =  TX_DESC_CSUM_EN | 
2830                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2831                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2832         }
2833
2834         entry = cp->tx_new[ring];
2835         cp->tx_skbs[ring][entry] = skb;
2836
2837         nr_frags = skb_shinfo(skb)->nr_frags;
2838         len = skb_headlen(skb);
2839         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2840                                offset_in_page(skb->data), len,
2841                                PCI_DMA_TODEVICE);
2842
2843         tentry = entry;
2844         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2845         if (unlikely(tabort)) {
2846                 /* NOTE: len is always >  tabort */
2847                 cas_write_txd(cp, ring, entry, mapping, len - tabort, 
2848                               ctrl | TX_DESC_SOF, 0);
2849                 entry = TX_DESC_NEXT(ring, entry);
2850
2851                 memcpy(tx_tiny_buf(cp, ring, entry), skb->data + 
2852                        len - tabort, tabort);
2853                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2854                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2855                               (nr_frags == 0));
2856         } else {
2857                 cas_write_txd(cp, ring, entry, mapping, len, ctrl | 
2858                               TX_DESC_SOF, (nr_frags == 0));
2859         }
2860         entry = TX_DESC_NEXT(ring, entry);
2861
2862         for (frag = 0; frag < nr_frags; frag++) {
2863                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2864
2865                 len = fragp->size;
2866                 mapping = pci_map_page(cp->pdev, fragp->page,
2867                                        fragp->page_offset, len,
2868                                        PCI_DMA_TODEVICE);
2869
2870                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2871                 if (unlikely(tabort)) {
2872                         void *addr;
2873
2874                         /* NOTE: len is always > tabort */
2875                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2876                                       ctrl, 0);
2877                         entry = TX_DESC_NEXT(ring, entry);
2878                         
2879                         addr = cas_page_map(fragp->page);
2880                         memcpy(tx_tiny_buf(cp, ring, entry),
2881                                addr + fragp->page_offset + len - tabort, 
2882                                tabort);
2883                         cas_page_unmap(addr);
2884                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2885                         len     = tabort;
2886                 }
2887
2888                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2889                               (frag + 1 == nr_frags));
2890                 entry = TX_DESC_NEXT(ring, entry);
2891         }
2892
2893         cp->tx_new[ring] = entry;
2894         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2895                 netif_stop_queue(dev);
2896
2897         if (netif_msg_tx_queued(cp))
2898                 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2899                        "avail %d\n",
2900                        dev->name, ring, entry, skb->len, 
2901                        TX_BUFFS_AVAIL(cp, ring));
2902         writel(entry, cp->regs + REG_TX_KICKN(ring));
2903         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2904         return 0;
2905
2906
2907 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2908 {
2909         struct cas *cp = netdev_priv(dev);
2910
2911         /* this is only used as a load-balancing hint, so it doesn't
2912          * need to be SMP safe
2913          */
2914         static int ring; 
2915
2916         skb = skb_padto(skb, cp->min_frame_size);
2917         if (!skb)
2918                 return 0;
2919
2920         /* XXX: we need some higher-level QoS hooks to steer packets to
2921          *      individual queues.
2922          */
2923         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2924                 return 1;
2925         dev->trans_start = jiffies;
2926         return 0;
2927 }
2928
2929 static void cas_init_tx_dma(struct cas *cp)
2930 {
2931         u64 desc_dma = cp->block_dvma;
2932         unsigned long off;
2933         u32 val;
2934         int i;
2935
2936         /* set up tx completion writeback registers. must be 8-byte aligned */
2937 #ifdef USE_TX_COMPWB
2938         off = offsetof(struct cas_init_block, tx_compwb);
2939         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2940         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2941 #endif
2942
2943         /* enable completion writebacks, enable paced mode,
2944          * disable read pipe, and disable pre-interrupt compwbs
2945          */
2946         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | 
2947                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2948                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE | 
2949                 TX_CFG_INTR_COMPWB_DIS;
2950
2951         /* write out tx ring info and tx desc bases */
2952         for (i = 0; i < MAX_TX_RINGS; i++) {
2953                 off = (unsigned long) cp->init_txds[i] - 
2954                         (unsigned long) cp->init_block;
2955
2956                 val |= CAS_TX_RINGN_BASE(i);
2957                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2958                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2959                        REG_TX_DBN_LOW(i));
2960                 /* don't zero out the kick register here as the system
2961                  * will wedge
2962                  */
2963         }
2964         writel(val, cp->regs + REG_TX_CFG);
2965
2966         /* program max burst sizes. these numbers should be different
2967          * if doing QoS.
2968          */
2969 #ifdef USE_QOS
2970         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2971         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2972         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2973         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2974 #else
2975         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2976         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2977         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2978         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2979 #endif
2980 }
2981
2982 /* Must be invoked under cp->lock. */
2983 static inline void cas_init_dma(struct cas *cp)
2984 {
2985         cas_init_tx_dma(cp);
2986         cas_init_rx_dma(cp);
2987 }
2988
2989 /* Must be invoked under cp->lock. */
2990 static u32 cas_setup_multicast(struct cas *cp)
2991 {
2992         u32 rxcfg = 0;
2993         int i;
2994         
2995         if (cp->dev->flags & IFF_PROMISC) {
2996                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2997
2998         } else if (cp->dev->flags & IFF_ALLMULTI) {
2999                 for (i=0; i < 16; i++)
3000                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
3001                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3002
3003         } else {
3004                 u16 hash_table[16];
3005                 u32 crc;
3006                 struct dev_mc_list *dmi = cp->dev->mc_list;
3007                 int i;
3008
3009                 /* use the alternate mac address registers for the
3010                  * first 15 multicast addresses
3011                  */
3012                 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
3013                         if (!dmi) {
3014                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
3015                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
3016                                 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
3017                                 continue;
3018                         }
3019                         writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5], 
3020                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
3021                         writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3], 
3022                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
3023                         writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1], 
3024                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
3025                         dmi = dmi->next;
3026                 }
3027
3028                 /* use hw hash table for the next series of 
3029                  * multicast addresses
3030                  */
3031                 memset(hash_table, 0, sizeof(hash_table));
3032                 while (dmi) {
3033                         crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3034                         crc >>= 24;
3035                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3036                         dmi = dmi->next;
3037                 }
3038                 for (i=0; i < 16; i++)
3039                         writel(hash_table[i], cp->regs + 
3040                                REG_MAC_HASH_TABLEN(i));
3041                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3042         }
3043
3044         return rxcfg;
3045 }
3046
3047 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3048 static void cas_clear_mac_err(struct cas *cp)
3049 {
3050         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3051         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3052         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3053         writel(0, cp->regs + REG_MAC_COLL_LATE);
3054         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3055         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3056         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3057         writel(0, cp->regs + REG_MAC_LEN_ERR);
3058         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3059         writel(0, cp->regs + REG_MAC_FCS_ERR);
3060         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3061 }
3062
3063
3064 static void cas_mac_reset(struct cas *cp)
3065 {
3066         int i;
3067
3068         /* do both TX and RX reset */
3069         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3070         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3071
3072         /* wait for TX */
3073         i = STOP_TRIES;
3074         while (i-- > 0) {
3075                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3076                         break;
3077                 udelay(10);
3078         }
3079
3080         /* wait for RX */
3081         i = STOP_TRIES;
3082         while (i-- > 0) {
3083                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3084                         break;
3085                 udelay(10);
3086         }
3087
3088         if (readl(cp->regs + REG_MAC_TX_RESET) |
3089             readl(cp->regs + REG_MAC_RX_RESET))
3090                 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3091                        cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3092                        readl(cp->regs + REG_MAC_RX_RESET),
3093                        readl(cp->regs + REG_MAC_STATE_MACHINE));
3094 }
3095
3096
3097 /* Must be invoked under cp->lock. */
3098 static void cas_init_mac(struct cas *cp)
3099 {
3100         unsigned char *e = &cp->dev->dev_addr[0];
3101         int i;
3102 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3103         u32 rxcfg;
3104 #endif
3105         cas_mac_reset(cp);
3106
3107         /* setup core arbitration weight register */
3108         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3109
3110         /* XXX Use pci_dma_burst_advice() */
3111 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3112         /* set the infinite burst register for chips that don't have
3113          * pci issues.
3114          */
3115         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3116                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3117 #endif
3118
3119         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3120
3121         writel(0x00, cp->regs + REG_MAC_IPG0);
3122         writel(0x08, cp->regs + REG_MAC_IPG1);
3123         writel(0x04, cp->regs + REG_MAC_IPG2);
3124         
3125         /* change later for 802.3z */
3126         writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 
3127
3128         /* min frame + FCS */
3129         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3130
3131         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3132          * specify the maximum frame size to prevent RX tag errors on 
3133          * oversized frames.
3134          */
3135         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3136                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME, 
3137                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)), 
3138                cp->regs + REG_MAC_FRAMESIZE_MAX);
3139
3140         /* NOTE: crc_size is used as a surrogate for half-duplex. 
3141          * workaround saturn half-duplex issue by increasing preamble
3142          * size to 65 bytes.
3143          */
3144         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3145                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3146         else
3147                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3148         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3149         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3150         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3151
3152         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3153
3154         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3155         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3156         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3157         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3158         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3159
3160         /* setup mac address in perfect filter array */
3161         for (i = 0; i < 45; i++)
3162                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3163
3164         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3165         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3166         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3167
3168         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3169         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3170         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3171
3172 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3173         cp->mac_rx_cfg = cas_setup_multicast(cp);
3174 #else
3175         /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3176          * a writel does not seem to be necessary because Cassini
3177          * seems to preserve the configuration when we do the reset.
3178          * If the chip is in trouble, though, it is not clear if we
3179          * can really count on this behavior. cas_set_multicast uses
3180          * spin_lock_irqsave, but we are called only in cas_init_hw and
3181          * cas_init_hw is protected by cas_lock_all, which calls
3182          * spin_lock_irq (so it doesn't need to save the flags, and
3183          * we should be OK for the writel, as that is the only 
3184          * difference).
3185          */
3186         cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3187         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3188 #endif
3189         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3190         cas_clear_mac_err(cp);
3191         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3192
3193         /* Setup MAC interrupts.  We want to get all of the interesting
3194          * counter expiration events, but we do not want to hear about
3195          * normal rx/tx as the DMA engine tells us that.
3196          */
3197         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3198         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3199
3200         /* Don't enable even the PAUSE interrupts for now, we
3201          * make no use of those events other than to record them.
3202          */
3203         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3204 }
3205
3206 /* Must be invoked under cp->lock. */
3207 static void cas_init_pause_thresholds(struct cas *cp)
3208 {
3209         /* Calculate pause thresholds.  Setting the OFF threshold to the
3210          * full RX fifo size effectively disables PAUSE generation
3211          */
3212         if (cp->rx_fifo_size <= (2 * 1024)) {
3213                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3214         } else {
3215                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3216                 if (max_frame * 3 > cp->rx_fifo_size) {
3217                         cp->rx_pause_off = 7104;
3218                         cp->rx_pause_on  = 960;
3219                 } else {
3220                         int off = (cp->rx_fifo_size - (max_frame * 2));
3221                         int on = off - max_frame;
3222                         cp->rx_pause_off = off;
3223                         cp->rx_pause_on = on;
3224                 }
3225         }
3226 }
3227
3228 static int cas_vpd_match(const void __iomem *p, const char *str)
3229 {
3230         int len = strlen(str) + 1;
3231         int i;
3232         
3233         for (i = 0; i < len; i++) {
3234                 if (readb(p + i) != str[i])
3235                         return 0;
3236         }
3237         return 1;
3238 }
3239
3240
3241 /* get the mac address by reading the vpd information in the rom.
3242  * also get the phy type and determine if there's an entropy generator.
3243  * NOTE: this is a bit convoluted for the following reasons:
3244  *  1) vpd info has order-dependent mac addresses for multinic cards
3245  *  2) the only way to determine the nic order is to use the slot
3246  *     number.
3247  *  3) fiber cards don't have bridges, so their slot numbers don't
3248  *     mean anything.
3249  *  4) we don't actually know we have a fiber card until after 
3250  *     the mac addresses are parsed.
3251  */
3252 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3253                             const int offset)
3254 {
3255         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3256         void __iomem *base, *kstart;
3257         int i, len;
3258         int found = 0;
3259 #define VPD_FOUND_MAC        0x01
3260 #define VPD_FOUND_PHY        0x02
3261
3262         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3263         int mac_off  = 0;
3264
3265         /* give us access to the PROM */
3266         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3267                cp->regs + REG_BIM_LOCAL_DEV_EN);
3268
3269         /* check for an expansion rom */
3270         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3271                 goto use_random_mac_addr;
3272
3273         /* search for beginning of vpd */
3274         base = NULL;
3275         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3276                 /* check for PCIR */
3277                 if ((readb(p + i + 0) == 0x50) &&
3278                     (readb(p + i + 1) == 0x43) &&
3279                     (readb(p + i + 2) == 0x49) &&
3280                     (readb(p + i + 3) == 0x52)) {
3281                         base = p + (readb(p + i + 8) | 
3282                                     (readb(p + i + 9) << 8));
3283                         break;
3284                 }               
3285         }
3286
3287         if (!base || (readb(base) != 0x82))
3288                 goto use_random_mac_addr;
3289         
3290         i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3291         while (i < EXPANSION_ROM_SIZE) {
3292                 if (readb(base + i) != 0x90) /* no vpd found */
3293                         goto use_random_mac_addr;
3294
3295                 /* found a vpd field */
3296                 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3297
3298                 /* extract keywords */
3299                 kstart = base + i + 3;
3300                 p = kstart;
3301                 while ((p - kstart) < len) {
3302                         int klen = readb(p + 2);
3303                         int j;
3304                         char type;
3305
3306                         p += 3;
3307                         
3308                         /* look for the following things:
3309                          * -- correct length == 29
3310                          * 3 (type) + 2 (size) + 
3311                          * 18 (strlen("local-mac-address") + 1) + 
3312                          * 6 (mac addr) 
3313                          * -- VPD Instance 'I'
3314                          * -- VPD Type Bytes 'B'
3315                          * -- VPD data length == 6
3316                          * -- property string == local-mac-address
3317                          * 
3318                          * -- correct length == 24
3319                          * 3 (type) + 2 (size) + 
3320                          * 12 (strlen("entropy-dev") + 1) + 
3321                          * 7 (strlen("vms110") + 1)
3322                          * -- VPD Instance 'I'
3323                          * -- VPD Type String 'B'
3324                          * -- VPD data length == 7
3325                          * -- property string == entropy-dev
3326                          *
3327                          * -- correct length == 18
3328                          * 3 (type) + 2 (size) + 
3329                          * 9 (strlen("phy-type") + 1) + 
3330                          * 4 (strlen("pcs") + 1)
3331                          * -- VPD Instance 'I'
3332                          * -- VPD Type String 'S'
3333                          * -- VPD data length == 4
3334                          * -- property string == phy-type
3335                          * 
3336                          * -- correct length == 23
3337                          * 3 (type) + 2 (size) + 
3338                          * 14 (strlen("phy-interface") + 1) + 
3339                          * 4 (strlen("pcs") + 1)
3340                          * -- VPD Instance 'I'
3341                          * -- VPD Type String 'S'
3342                          * -- VPD data length == 4
3343                          * -- property string == phy-interface
3344                          */
3345                         if (readb(p) != 'I')
3346                                 goto next;
3347
3348                         /* finally, check string and length */
3349                         type = readb(p + 3);
3350                         if (type == 'B') {
3351                                 if ((klen == 29) && readb(p + 4) == 6 &&
3352                                     cas_vpd_match(p + 5, 
3353                                                   "local-mac-address")) {
3354                                         if (mac_off++ > offset) 
3355                                                 goto next;
3356
3357                                         /* set mac address */
3358                                         for (j = 0; j < 6; j++) 
3359                                                 dev_addr[j] = 
3360                                                         readb(p + 23 + j);
3361                                         goto found_mac;
3362                                 }
3363                         }
3364
3365                         if (type != 'S')
3366                                 goto next;
3367
3368 #ifdef USE_ENTROPY_DEV
3369                         if ((klen == 24) && 
3370                             cas_vpd_match(p + 5, "entropy-dev") &&
3371                             cas_vpd_match(p + 17, "vms110")) {
3372                                 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3373                                 goto next;
3374                         }
3375 #endif
3376
3377                         if (found & VPD_FOUND_PHY)
3378                                 goto next;
3379
3380                         if ((klen == 18) && readb(p + 4) == 4 &&
3381                             cas_vpd_match(p + 5, "phy-type")) {
3382                                 if (cas_vpd_match(p + 14, "pcs")) {
3383                                         phy_type = CAS_PHY_SERDES;
3384                                         goto found_phy;
3385                                 }
3386                         }
3387                         
3388                         if ((klen == 23) && readb(p + 4) == 4 &&
3389                             cas_vpd_match(p + 5, "phy-interface")) {
3390                                 if (cas_vpd_match(p + 19, "pcs")) {
3391                                         phy_type = CAS_PHY_SERDES;
3392                                         goto found_phy;
3393                                 }
3394                         }
3395 found_mac:
3396                         found |= VPD_FOUND_MAC;
3397                         goto next;
3398
3399 found_phy:
3400                         found |= VPD_FOUND_PHY;
3401
3402 next:
3403                         p += klen;
3404                 }
3405                 i += len + 3;
3406         }
3407
3408 use_random_mac_addr:
3409         if (found & VPD_FOUND_MAC)
3410                 goto done;
3411
3412         /* Sun MAC prefix then 3 random bytes. */
3413         printk(PFX "MAC address not found in ROM VPD\n");
3414         dev_addr[0] = 0x08;
3415         dev_addr[1] = 0x00;
3416         dev_addr[2] = 0x20;
3417         get_random_bytes(dev_addr + 3, 3);
3418
3419 done:
3420         writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3421         return phy_type;
3422 }
3423
3424 /* check pci invariants */
3425 static void cas_check_pci_invariants(struct cas *cp)
3426 {
3427         struct pci_dev *pdev = cp->pdev;
3428         u8 rev;
3429
3430         cp->cas_flags = 0;
3431         pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
3432         if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3433             (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3434                 if (rev >= CAS_ID_REVPLUS)
3435                         cp->cas_flags |= CAS_FLAG_REG_PLUS;
3436                 if (rev < CAS_ID_REVPLUS02u)
3437                         cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3438
3439                 /* Original Cassini supports HW CSUM, but it's not
3440                  * enabled by default as it can trigger TX hangs.
3441                  */
3442                 if (rev < CAS_ID_REV2)
3443                         cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3444         } else {
3445                 /* Only sun has original cassini chips.  */
3446                 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3447
3448                 /* We use a flag because the same phy might be externally
3449                  * connected.
3450                  */
3451                 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3452                     (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3453                         cp->cas_flags |= CAS_FLAG_SATURN;
3454         }
3455 }
3456
3457
3458 static int cas_check_invariants(struct cas *cp)
3459 {
3460         struct pci_dev *pdev = cp->pdev;
3461         u32 cfg;
3462         int i;
3463
3464         /* get page size for rx buffers. */
3465         cp->page_order = 0; 
3466 #ifdef USE_PAGE_ORDER
3467         if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3468                 /* see if we can allocate larger pages */
3469                 struct page *page = alloc_pages(GFP_ATOMIC, 
3470                                                 CAS_JUMBO_PAGE_SHIFT - 
3471                                                 PAGE_SHIFT);
3472                 if (page) {
3473                         __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3474                         cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3475                 } else {
3476                         printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3477                 }
3478         }
3479 #endif
3480         cp->page_size = (PAGE_SIZE << cp->page_order);
3481
3482         /* Fetch the FIFO configurations. */
3483         cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3484         cp->rx_fifo_size = RX_FIFO_SIZE;
3485
3486         /* finish phy determination. MDIO1 takes precedence over MDIO0 if 
3487          * they're both connected.
3488          */
3489         cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr, 
3490                                         PCI_SLOT(pdev->devfn));
3491         if (cp->phy_type & CAS_PHY_SERDES) {
3492                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3493                 return 0; /* no more checking needed */
3494         } 
3495
3496         /* MII */
3497         cfg = readl(cp->regs + REG_MIF_CFG);
3498         if (cfg & MIF_CFG_MDIO_1) {
3499                 cp->phy_type = CAS_PHY_MII_MDIO1;
3500         } else if (cfg & MIF_CFG_MDIO_0) {
3501                 cp->phy_type = CAS_PHY_MII_MDIO0;
3502         }
3503
3504         cas_mif_poll(cp, 0);
3505         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3506
3507         for (i = 0; i < 32; i++) {
3508                 u32 phy_id;
3509                 int j;
3510
3511                 for (j = 0; j < 3; j++) {
3512                         cp->phy_addr = i;
3513                         phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3514                         phy_id |= cas_phy_read(cp, MII_PHYSID2);
3515                         if (phy_id && (phy_id != 0xFFFFFFFF)) {
3516                                 cp->phy_id = phy_id;
3517                                 goto done;
3518                         }
3519                 }
3520         }
3521         printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3522                readl(cp->regs + REG_MIF_STATE_MACHINE));
3523         return -1;
3524
3525 done:
3526         /* see if we can do gigabit */
3527         cfg = cas_phy_read(cp, MII_BMSR);
3528         if ((cfg & CAS_BMSR_1000_EXTEND) && 
3529             cas_phy_read(cp, CAS_MII_1000_EXTEND))
3530                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3531         return 0;
3532 }
3533
3534 /* Must be invoked under cp->lock. */
3535 static inline void cas_start_dma(struct cas *cp)
3536 {
3537         int i;
3538         u32 val;
3539         int txfailed = 0;
3540         
3541         /* enable dma */
3542         val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3543         writel(val, cp->regs + REG_TX_CFG);
3544         val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3545         writel(val, cp->regs + REG_RX_CFG);
3546
3547         /* enable the mac */
3548         val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3549         writel(val, cp->regs + REG_MAC_TX_CFG);
3550         val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3551         writel(val, cp->regs + REG_MAC_RX_CFG);
3552
3553         i = STOP_TRIES;
3554         while (i-- > 0) {
3555                 val = readl(cp->regs + REG_MAC_TX_CFG);
3556                 if ((val & MAC_TX_CFG_EN))
3557                         break;
3558                 udelay(10);
3559         }
3560         if (i < 0) txfailed = 1;
3561         i = STOP_TRIES;
3562         while (i-- > 0) {
3563                 val = readl(cp->regs + REG_MAC_RX_CFG);
3564                 if ((val & MAC_RX_CFG_EN)) {
3565                         if (txfailed) {
3566                           printk(KERN_ERR 
3567                                  "%s: enabling mac failed [tx:%08x:%08x].\n", 
3568                                  cp->dev->name,
3569                                  readl(cp->regs + REG_MIF_STATE_MACHINE),
3570                                  readl(cp->regs + REG_MAC_STATE_MACHINE));
3571                         }
3572                         goto enable_rx_done;
3573                 }
3574                 udelay(10);
3575         }
3576         printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n", 
3577                cp->dev->name,
3578                (txfailed? "tx,rx":"rx"),
3579                readl(cp->regs + REG_MIF_STATE_MACHINE),
3580                readl(cp->regs + REG_MAC_STATE_MACHINE));
3581
3582 enable_rx_done:
3583         cas_unmask_intr(cp); /* enable interrupts */
3584         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3585         writel(0, cp->regs + REG_RX_COMP_TAIL);
3586
3587         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3588                 if (N_RX_DESC_RINGS > 1) 
3589                         writel(RX_DESC_RINGN_SIZE(1) - 4, 
3590                                cp->regs + REG_PLUS_RX_KICK1);
3591
3592                 for (i = 1; i < N_RX_COMP_RINGS; i++) 
3593                         writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3594         }
3595 }
3596
3597 /* Must be invoked under cp->lock. */
3598 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3599                                    int *pause)
3600 {
3601         u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3602         *fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3603         *pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3604         if (val & PCS_MII_LPA_ASYM_PAUSE)
3605                 *pause |= 0x10;
3606         *spd = 1000;
3607 }
3608
3609 /* Must be invoked under cp->lock. */
3610 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3611                                    int *pause)
3612 {
3613         u32 val;
3614
3615         *fd = 0;
3616         *spd = 10;
3617         *pause = 0;
3618         
3619         /* use GMII registers */
3620         val = cas_phy_read(cp, MII_LPA);
3621         if (val & CAS_LPA_PAUSE)
3622                 *pause = 0x01;
3623
3624         if (val & CAS_LPA_ASYM_PAUSE)
3625                 *pause |= 0x10;
3626
3627         if (val & LPA_DUPLEX)
3628                 *fd = 1;
3629         if (val & LPA_100)
3630                 *spd = 100;
3631
3632         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3633                 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3634                 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3635                         *spd = 1000;
3636                 if (val & CAS_LPA_1000FULL)
3637                         *fd = 1;
3638         }
3639 }
3640
3641 /* A link-up condition has occurred, initialize and enable the
3642  * rest of the chip.
3643  *
3644  * Must be invoked under cp->lock.
3645  */
3646 static void cas_set_link_modes(struct cas *cp)
3647 {
3648         u32 val;
3649         int full_duplex, speed, pause;
3650
3651         full_duplex = 0;
3652         speed = 10;
3653         pause = 0;
3654
3655         if (CAS_PHY_MII(cp->phy_type)) {
3656                 cas_mif_poll(cp, 0);
3657                 val = cas_phy_read(cp, MII_BMCR);
3658                 if (val & BMCR_ANENABLE) {
3659                         cas_read_mii_link_mode(cp, &full_duplex, &speed, 
3660                                                &pause);
3661                 } else {
3662                         if (val & BMCR_FULLDPLX)
3663                                 full_duplex = 1;
3664
3665                         if (val & BMCR_SPEED100)
3666                                 speed = 100;
3667                         else if (val & CAS_BMCR_SPEED1000)
3668                                 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3669                                         1000 : 100;
3670                 }
3671                 cas_mif_poll(cp, 1);
3672
3673         } else {
3674                 val = readl(cp->regs + REG_PCS_MII_CTRL);
3675                 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3676                 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3677                         if (val & PCS_MII_CTRL_DUPLEX)
3678                                 full_duplex = 1;
3679                 }
3680         }
3681
3682         if (netif_msg_link(cp))
3683                 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3684                        cp->dev->name, speed, (full_duplex ? "full" : "half"));
3685
3686         val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3687         if (CAS_PHY_MII(cp->phy_type)) {
3688                 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3689                 if (!full_duplex)
3690                         val |= MAC_XIF_DISABLE_ECHO;
3691         }
3692         if (full_duplex) 
3693                 val |= MAC_XIF_FDPLX_LED;
3694         if (speed == 1000)
3695                 val |= MAC_XIF_GMII_MODE;
3696         writel(val, cp->regs + REG_MAC_XIF_CFG);
3697
3698         /* deal with carrier and collision detect. */
3699         val = MAC_TX_CFG_IPG_EN;
3700         if (full_duplex) {
3701                 val |= MAC_TX_CFG_IGNORE_CARRIER;
3702                 val |= MAC_TX_CFG_IGNORE_COLL;
3703         } else {
3704 #ifndef USE_CSMA_CD_PROTO
3705                 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3706                 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3707 #endif
3708         }
3709         /* val now set up for REG_MAC_TX_CFG */
3710
3711         /* If gigabit and half-duplex, enable carrier extension
3712          * mode.  increase slot time to 512 bytes as well. 
3713          * else, disable it and make sure slot time is 64 bytes.
3714          * also activate checksum bug workaround
3715          */
3716         if ((speed == 1000) && !full_duplex) {
3717                 writel(val | MAC_TX_CFG_CARRIER_EXTEND, 
3718                        cp->regs + REG_MAC_TX_CFG);
3719
3720                 val = readl(cp->regs + REG_MAC_RX_CFG);
3721                 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3722                 writel(val | MAC_RX_CFG_CARRIER_EXTEND, 
3723                        cp->regs + REG_MAC_RX_CFG);
3724
3725                 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3726
3727                 cp->crc_size = 4;
3728                 /* minimum size gigabit frame at half duplex */
3729                 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3730
3731         } else {
3732                 writel(val, cp->regs + REG_MAC_TX_CFG);
3733
3734                 /* checksum bug workaround. don't strip FCS when in 
3735                  * half-duplex mode
3736                  */
3737                 val = readl(cp->regs + REG_MAC_RX_CFG);
3738                 if (full_duplex) {
3739                         val |= MAC_RX_CFG_STRIP_FCS;
3740                         cp->crc_size = 0;
3741                         cp->min_frame_size = CAS_MIN_MTU;
3742                 } else {
3743                         val &= ~MAC_RX_CFG_STRIP_FCS;
3744                         cp->crc_size = 4;
3745                         cp->min_frame_size = CAS_MIN_FRAME;
3746                 }
3747                 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, 
3748                        cp->regs + REG_MAC_RX_CFG);
3749                 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3750         }
3751
3752         if (netif_msg_link(cp)) {
3753                 if (pause & 0x01) {
3754                         printk(KERN_INFO "%s: Pause is enabled "
3755                                "(rxfifo: %d off: %d on: %d)\n",
3756                                cp->dev->name,
3757                                cp->rx_fifo_size,
3758                                cp->rx_pause_off,
3759                                cp->rx_pause_on);
3760                 } else if (pause & 0x10) {
3761                         printk(KERN_INFO "%s: TX pause enabled\n",
3762                                cp->dev->name);
3763                 } else {
3764                         printk(KERN_INFO "%s: Pause is disabled\n",
3765                                cp->dev->name);
3766                 }
3767         }
3768
3769         val = readl(cp->regs + REG_MAC_CTRL_CFG);
3770         val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3771         if (pause) { /* symmetric or asymmetric pause */
3772                 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3773                 if (pause & 0x01) { /* symmetric pause */
3774                         val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3775                 } 
3776         }
3777         writel(val, cp->regs + REG_MAC_CTRL_CFG);
3778         cas_start_dma(cp);
3779 }
3780
3781 /* Must be invoked under cp->lock. */
3782 static void cas_init_hw(struct cas *cp, int restart_link)
3783 {
3784         if (restart_link)
3785                 cas_phy_init(cp);
3786
3787         cas_init_pause_thresholds(cp);
3788         cas_init_mac(cp);
3789         cas_init_dma(cp);
3790
3791         if (restart_link) {
3792                 /* Default aneg parameters */
3793                 cp->timer_ticks = 0;
3794                 cas_begin_auto_negotiation(cp, NULL);
3795         } else if (cp->lstate == link_up) {
3796                 cas_set_link_modes(cp);
3797                 netif_carrier_on(cp->dev);
3798         }
3799 }
3800
3801 /* Must be invoked under cp->lock. on earlier cassini boards,
3802  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3803  * let it settle out, and then restore pci state.
3804  */
3805 static void cas_hard_reset(struct cas *cp)
3806 {
3807         writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); 
3808         udelay(20);
3809         pci_restore_state(cp->pdev);
3810 }
3811
3812
3813 static void cas_global_reset(struct cas *cp, int blkflag)
3814 {
3815         int limit;
3816
3817         /* issue a global reset. don't use RSTOUT. */
3818         if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3819                 /* For PCS, when the blkflag is set, we should set the
3820                  * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3821                  * the last autonegotiation from being cleared.  We'll
3822                  * need some special handling if the chip is set into a
3823                  * loopback mode.
3824                  */
3825                 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK), 
3826                        cp->regs + REG_SW_RESET);
3827         } else {
3828                 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3829         }
3830
3831         /* need to wait at least 3ms before polling register */
3832         mdelay(3);
3833
3834         limit = STOP_TRIES;
3835         while (limit-- > 0) {
3836                 u32 val = readl(cp->regs + REG_SW_RESET);
3837                 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3838                         goto done;
3839                 udelay(10);
3840         }
3841         printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3842
3843 done:
3844         /* enable various BIM interrupts */
3845         writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE | 
3846                BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3847
3848         /* clear out pci error status mask for handled errors.
3849          * we don't deal with DMA counter overflows as they happen
3850          * all the time.
3851          */
3852         writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO | 
3853                                PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE | 
3854                                PCI_ERR_BIM_DMA_READ), cp->regs + 
3855                REG_PCI_ERR_STATUS_MASK);
3856
3857         /* set up for MII by default to address mac rx reset timeout
3858          * issue
3859          */
3860         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3861 }
3862
3863 static void cas_reset(struct cas *cp, int blkflag)
3864 {
3865         u32 val;
3866
3867         cas_mask_intr(cp);
3868         cas_global_reset(cp, blkflag);
3869         cas_mac_reset(cp);
3870         cas_entropy_reset(cp);
3871
3872         /* disable dma engines. */
3873         val = readl(cp->regs + REG_TX_CFG);
3874         val &= ~TX_CFG_DMA_EN;
3875         writel(val, cp->regs + REG_TX_CFG);
3876
3877         val = readl(cp->regs + REG_RX_CFG);
3878         val &= ~RX_CFG_DMA_EN;
3879         writel(val, cp->regs + REG_RX_CFG);
3880
3881         /* program header parser */
3882         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3883             (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3884                 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3885         } else {
3886                 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3887         }
3888
3889         /* clear out error registers */
3890         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3891         cas_clear_mac_err(cp);
3892         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3893 }
3894
3895 /* Shut down the chip, must be called with pm_sem held.  */
3896 static void cas_shutdown(struct cas *cp)
3897 {
3898         unsigned long flags;
3899
3900         /* Make us not-running to avoid timers respawning */
3901         cp->hw_running = 0;
3902
3903         del_timer_sync(&cp->link_timer);
3904
3905         /* Stop the reset task */
3906 #if 0
3907         while (atomic_read(&cp->reset_task_pending_mtu) ||
3908                atomic_read(&cp->reset_task_pending_spare) ||
3909                atomic_read(&cp->reset_task_pending_all))
3910                 schedule();
3911
3912 #else
3913         while (atomic_read(&cp->reset_task_pending))
3914                 schedule();
3915 #endif  
3916         /* Actually stop the chip */
3917         cas_lock_all_save(cp, flags);
3918         cas_reset(cp, 0);
3919         if (cp->cas_flags & CAS_FLAG_SATURN)
3920                 cas_phy_powerdown(cp);
3921         cas_unlock_all_restore(cp, flags);
3922 }
3923
3924 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3925 {
3926         struct cas *cp = netdev_priv(dev);
3927
3928         if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3929                 return -EINVAL;
3930
3931         dev->mtu = new_mtu;
3932         if (!netif_running(dev) || !netif_device_present(dev))
3933                 return 0;
3934
3935         /* let the reset task handle it */
3936 #if 1
3937         atomic_inc(&cp->reset_task_pending);
3938         if ((cp->phy_type & CAS_PHY_SERDES)) {
3939                 atomic_inc(&cp->reset_task_pending_all);
3940         } else {
3941                 atomic_inc(&cp->reset_task_pending_mtu);
3942         }
3943         schedule_work(&cp->reset_task);
3944 #else
3945         atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ? 
3946                    CAS_RESET_ALL : CAS_RESET_MTU);
3947         printk(KERN_ERR "reset called in cas_change_mtu\n");
3948         schedule_work(&cp->reset_task);
3949 #endif
3950
3951         flush_scheduled_work();
3952         return 0;
3953 }
3954
3955 static void cas_clean_txd(struct cas *cp, int ring)
3956 {
3957         struct cas_tx_desc *txd = cp->init_txds[ring];
3958         struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3959         u64 daddr, dlen;
3960         int i, size;
3961
3962         size = TX_DESC_RINGN_SIZE(ring);
3963         for (i = 0; i < size; i++) {
3964                 int frag;
3965
3966                 if (skbs[i] == NULL)
3967                         continue;
3968
3969                 skb = skbs[i];
3970                 skbs[i] = NULL;
3971
3972                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3973                         int ent = i & (size - 1);
3974
3975                         /* first buffer is never a tiny buffer and so
3976                          * needs to be unmapped.
3977                          */
3978                         daddr = le64_to_cpu(txd[ent].buffer);
3979                         dlen  =  CAS_VAL(TX_DESC_BUFLEN, 
3980                                          le64_to_cpu(txd[ent].control));
3981                         pci_unmap_page(cp->pdev, daddr, dlen,
3982                                        PCI_DMA_TODEVICE);
3983
3984                         if (frag != skb_shinfo(skb)->nr_frags) {
3985                                 i++;
3986
3987                                 /* next buffer might by a tiny buffer.
3988                                  * skip past it.
3989                                  */
3990                                 ent = i & (size - 1);
3991                                 if (cp->tx_tiny_use[ring][ent].used)
3992                                         i++;
3993                         }
3994                 }
3995                 dev_kfree_skb_any(skb);
3996         }
3997
3998         /* zero out tiny buf usage */
3999         memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
4000 }
4001
4002 /* freed on close */
4003 static inline void cas_free_rx_desc(struct cas *cp, int ring)
4004 {
4005         cas_page_t **page = cp->rx_pages[ring];
4006         int i, size;
4007
4008         size = RX_DESC_RINGN_SIZE(ring);
4009         for (i = 0; i < size; i++) {
4010                 if (page[i]) {
4011                         cas_page_free(cp, page[i]);
4012                         page[i] = NULL;
4013                 }
4014         }
4015 }
4016
4017 static void cas_free_rxds(struct cas *cp)
4018 {
4019         int i;
4020
4021         for (i = 0; i < N_RX_DESC_RINGS; i++)
4022                 cas_free_rx_desc(cp, i);
4023 }
4024
4025 /* Must be invoked under cp->lock. */
4026 static void cas_clean_rings(struct cas *cp)
4027 {
4028         int i;
4029
4030         /* need to clean all tx rings */
4031         memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
4032         memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
4033         for (i = 0; i < N_TX_RINGS; i++)
4034                 cas_clean_txd(cp, i);
4035
4036         /* zero out init block */
4037         memset(cp->init_block, 0, sizeof(struct cas_init_block));
4038         cas_clean_rxds(cp);
4039         cas_clean_rxcs(cp);
4040 }
4041
4042 /* allocated on open */
4043 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4044 {
4045         cas_page_t **page = cp->rx_pages[ring];
4046         int size, i = 0;
4047
4048         size = RX_DESC_RINGN_SIZE(ring);
4049         for (i = 0; i < size; i++) {
4050                 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL) 
4051                         return -1;
4052         }
4053         return 0;
4054 }
4055
4056 static int cas_alloc_rxds(struct cas *cp)
4057 {
4058         int i;
4059
4060         for (i = 0; i < N_RX_DESC_RINGS; i++) {
4061                 if (cas_alloc_rx_desc(cp, i) < 0) {
4062                         cas_free_rxds(cp);
4063                         return -1;
4064                 }
4065         }
4066         return 0;
4067 }
4068
4069 static void cas_reset_task(void *data)
4070 {
4071         struct cas *cp = (struct cas *) data;
4072 #if 0
4073         int pending = atomic_read(&cp->reset_task_pending);
4074 #else
4075         int pending_all = atomic_read(&cp->reset_task_pending_all);
4076         int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4077         int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4078
4079         if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4080                 /* We can have more tasks scheduled than actually
4081                  * needed.
4082                  */
4083                 atomic_dec(&cp->reset_task_pending);
4084                 return;
4085         }
4086 #endif
4087         /* The link went down, we reset the ring, but keep
4088          * DMA stopped. Use this function for reset
4089          * on error as well.
4090          */
4091         if (cp->hw_running) {
4092                 unsigned long flags;
4093
4094                 /* Make sure we don't get interrupts or tx packets */
4095                 netif_device_detach(cp->dev);
4096                 cas_lock_all_save(cp, flags);
4097
4098                 if (cp->opened) {
4099                         /* We call cas_spare_recover when we call cas_open.
4100                          * but we do not initialize the lists cas_spare_recover
4101                          * uses until cas_open is called.
4102                          */
4103                         cas_spare_recover(cp, GFP_ATOMIC);
4104                 }
4105 #if 1
4106                 /* test => only pending_spare set */
4107                 if (!pending_all && !pending_mtu)
4108                         goto done;
4109 #else
4110                 if (pending == CAS_RESET_SPARE)
4111                         goto done;
4112 #endif
4113                 /* when pending == CAS_RESET_ALL, the following
4114                  * call to cas_init_hw will restart auto negotiation.
4115                  * Setting the second argument of cas_reset to
4116                  * !(pending == CAS_RESET_ALL) will set this argument
4117                  * to 1 (avoiding reinitializing the PHY for the normal 
4118                  * PCS case) when auto negotiation is not restarted.
4119                  */
4120 #if 1
4121                 cas_reset(cp, !(pending_all > 0));
4122                 if (cp->opened)
4123                         cas_clean_rings(cp);
4124                 cas_init_hw(cp, (pending_all > 0));
4125 #else
4126                 cas_reset(cp, !(pending == CAS_RESET_ALL));
4127                 if (cp->opened)
4128                         cas_clean_rings(cp);
4129                 cas_init_hw(cp, pending == CAS_RESET_ALL);
4130 #endif
4131
4132 done:
4133                 cas_unlock_all_restore(cp, flags);
4134                 netif_device_attach(cp->dev);
4135         }
4136 #if 1
4137         atomic_sub(pending_all, &cp->reset_task_pending_all);
4138         atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4139         atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4140         atomic_dec(&cp->reset_task_pending);
4141 #else
4142         atomic_set(&cp->reset_task_pending, 0);
4143 #endif
4144 }
4145
4146 static void cas_link_timer(unsigned long data)
4147 {
4148         struct cas *cp = (struct cas *) data;
4149         int mask, pending = 0, reset = 0;
4150         unsigned long flags;
4151
4152         if (link_transition_timeout != 0 &&
4153             cp->link_transition_jiffies_valid &&
4154             ((jiffies - cp->link_transition_jiffies) > 
4155               (link_transition_timeout))) {
4156                 /* One-second counter so link-down workaround doesn't 
4157                  * cause resets to occur so fast as to fool the switch
4158                  * into thinking the link is down.
4159                  */
4160                 cp->link_transition_jiffies_valid = 0;
4161         }
4162
4163         if (!cp->hw_running)
4164                 return;
4165
4166         spin_lock_irqsave(&cp->lock, flags);
4167         cas_lock_tx(cp);
4168         cas_entropy_gather(cp);
4169
4170         /* If the link task is still pending, we just
4171          * reschedule the link timer
4172          */
4173 #if 1
4174         if (atomic_read(&cp->reset_task_pending_all) ||
4175             atomic_read(&cp->reset_task_pending_spare) ||
4176             atomic_read(&cp->reset_task_pending_mtu)) 
4177                 goto done;
4178 #else
4179         if (atomic_read(&cp->reset_task_pending)) 
4180                 goto done;
4181 #endif
4182
4183         /* check for rx cleaning */
4184         if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4185                 int i, rmask;
4186
4187                 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4188                         rmask = CAS_FLAG_RXD_POST(i);
4189                         if ((mask & rmask) == 0)
4190                                 continue;
4191
4192                         /* post_rxds will do a mod_timer */
4193                         if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4194                                 pending = 1;
4195                                 continue;
4196                         }
4197                         cp->cas_flags &= ~rmask;
4198                 }
4199         }
4200
4201         if (CAS_PHY_MII(cp->phy_type)) {
4202                 u16 bmsr;
4203                 cas_mif_poll(cp, 0);
4204                 bmsr = cas_phy_read(cp, MII_BMSR);
4205                 /* WTZ: Solaris driver reads this twice, but that
4206                  * may be due to the PCS case and the use of a
4207                  * common implementation. Read it twice here to be
4208                  * safe.
4209                  */
4210                 bmsr = cas_phy_read(cp, MII_BMSR);
4211                 cas_mif_poll(cp, 1);
4212                 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4213                 reset = cas_mii_link_check(cp, bmsr);
4214         } else {
4215                 reset = cas_pcs_link_check(cp);
4216         }
4217
4218         if (reset)
4219                 goto done;
4220
4221         /* check for tx state machine confusion */
4222         if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4223                 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4224                 u32 wptr, rptr;
4225                 int tlm  = CAS_VAL(MAC_SM_TLM, val);
4226
4227                 if (((tlm == 0x5) || (tlm == 0x3)) &&
4228                     (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4229                         if (netif_msg_tx_err(cp))
4230                                 printk(KERN_DEBUG "%s: tx err: "
4231                                        "MAC_STATE[%08x]\n",
4232                                        cp->dev->name, val);
4233                         reset = 1;
4234                         goto done;
4235                 }
4236
4237                 val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4238                 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4239                 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4240                 if ((val == 0) && (wptr != rptr)) {
4241                         if (netif_msg_tx_err(cp))
4242                                 printk(KERN_DEBUG "%s: tx err: "
4243                                        "TX_FIFO[%08x:%08x:%08x]\n",
4244                                        cp->dev->name, val, wptr, rptr);
4245                         reset = 1;
4246                 }
4247
4248                 if (reset)
4249                         cas_hard_reset(cp);
4250         }
4251
4252 done:
4253         if (reset) {
4254 #if 1
4255                 atomic_inc(&cp->reset_task_pending);
4256                 atomic_inc(&cp->reset_task_pending_all);
4257                 schedule_work(&cp->reset_task);
4258 #else
4259                 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4260                 printk(KERN_ERR "reset called in cas_link_timer\n");
4261                 schedule_work(&cp->reset_task);
4262 #endif
4263         }
4264
4265         if (!pending)
4266                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4267         cas_unlock_tx(cp);
4268         spin_unlock_irqrestore(&cp->lock, flags);
4269 }
4270
4271 /* tiny buffers are used to avoid target abort issues with 
4272  * older cassini's
4273  */
4274 static void cas_tx_tiny_free(struct cas *cp)
4275 {
4276         struct pci_dev *pdev = cp->pdev;
4277         int i;
4278
4279         for (i = 0; i < N_TX_RINGS; i++) {
4280                 if (!cp->tx_tiny_bufs[i])
4281                         continue;
4282
4283                 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK, 
4284                                     cp->tx_tiny_bufs[i],
4285                                     cp->tx_tiny_dvma[i]);
4286                 cp->tx_tiny_bufs[i] = NULL;
4287         }
4288 }
4289
4290 static int cas_tx_tiny_alloc(struct cas *cp)
4291 {
4292         struct pci_dev *pdev = cp->pdev;
4293         int i;
4294
4295         for (i = 0; i < N_TX_RINGS; i++) {
4296                 cp->tx_tiny_bufs[i] = 
4297                         pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4298                                              &cp->tx_tiny_dvma[i]);
4299                 if (!cp->tx_tiny_bufs[i]) {
4300                         cas_tx_tiny_free(cp);
4301                         return -1;
4302                 }
4303         }
4304         return 0;
4305 }
4306
4307
4308 static int cas_open(struct net_device *dev)
4309 {
4310         struct cas *cp = netdev_priv(dev);
4311         int hw_was_up, err;
4312         unsigned long flags;
4313
4314         down(&cp->pm_sem);
4315
4316         hw_was_up = cp->hw_running;
4317
4318         /* The power-management semaphore protects the hw_running
4319          * etc. state so it is safe to do this bit without cp->lock
4320          */
4321         if (!cp->hw_running) {
4322                 /* Reset the chip */
4323                 cas_lock_all_save(cp, flags);
4324                 /* We set the second arg to cas_reset to zero
4325                  * because cas_init_hw below will have its second 
4326                  * argument set to non-zero, which will force
4327                  * autonegotiation to start.
4328                  */
4329                 cas_reset(cp, 0);
4330                 cp->hw_running = 1;
4331                 cas_unlock_all_restore(cp, flags);
4332         }
4333
4334         if (cas_tx_tiny_alloc(cp) < 0)
4335                 return -ENOMEM;
4336
4337         /* alloc rx descriptors */
4338         err = -ENOMEM;
4339         if (cas_alloc_rxds(cp) < 0)
4340                 goto err_tx_tiny;
4341         
4342         /* allocate spares */
4343         cas_spare_init(cp);
4344         cas_spare_recover(cp, GFP_KERNEL);
4345
4346         /* We can now request the interrupt as we know it's masked
4347          * on the controller. cassini+ has up to 4 interrupts
4348          * that can be used, but you need to do explicit pci interrupt 
4349          * mapping to expose them
4350          */
4351         if (request_irq(cp->pdev->irq, cas_interrupt,
4352                         SA_SHIRQ, dev->name, (void *) dev)) {
4353                 printk(KERN_ERR "%s: failed to request irq !\n", 
4354                        cp->dev->name);
4355                 err = -EAGAIN;
4356                 goto err_spare;
4357         }
4358
4359         /* init hw */
4360         cas_lock_all_save(cp, flags);
4361         cas_clean_rings(cp);
4362         cas_init_hw(cp, !hw_was_up);
4363         cp->opened = 1;
4364         cas_unlock_all_restore(cp, flags);
4365
4366         netif_start_queue(dev);
4367         up(&cp->pm_sem);
4368         return 0;
4369
4370 err_spare:
4371         cas_spare_free(cp);
4372         cas_free_rxds(cp);
4373 err_tx_tiny:
4374         cas_tx_tiny_free(cp);
4375         up(&cp->pm_sem);
4376         return err;
4377 }
4378
4379 static int cas_close(struct net_device *dev)
4380 {
4381         unsigned long flags;
4382         struct cas *cp = netdev_priv(dev);
4383
4384         /* Make sure we don't get distracted by suspend/resume */
4385         down(&cp->pm_sem);
4386
4387         netif_stop_queue(dev);
4388
4389         /* Stop traffic, mark us closed */
4390         cas_lock_all_save(cp, flags);
4391         cp->opened = 0; 
4392         cas_reset(cp, 0);
4393         cas_phy_init(cp); 
4394         cas_begin_auto_negotiation(cp, NULL);
4395         cas_clean_rings(cp);
4396         cas_unlock_all_restore(cp, flags);
4397
4398         free_irq(cp->pdev->irq, (void *) dev);
4399         cas_spare_free(cp);
4400         cas_free_rxds(cp);
4401         cas_tx_tiny_free(cp);
4402         up(&cp->pm_sem);
4403         return 0;
4404 }
4405
4406 static struct {
4407         const char name[ETH_GSTRING_LEN];
4408 } ethtool_cassini_statnames[] = {
4409         {"collisions"},
4410         {"rx_bytes"},
4411         {"rx_crc_errors"},
4412         {"rx_dropped"},
4413         {"rx_errors"},
4414         {"rx_fifo_errors"},
4415         {"rx_frame_errors"},
4416         {"rx_length_errors"},
4417         {"rx_over_errors"},
4418         {"rx_packets"},
4419         {"tx_aborted_errors"},
4420         {"tx_bytes"},
4421         {"tx_dropped"},
4422         {"tx_errors"},
4423         {"tx_fifo_errors"},
4424         {"tx_packets"}
4425 };
4426 #define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN)
4427
4428 static struct {
4429         const int offsets;      /* neg. values for 2nd arg to cas_read_phy */
4430 } ethtool_register_table[] = {
4431         {-MII_BMSR},
4432         {-MII_BMCR},
4433         {REG_CAWR},
4434         {REG_INF_BURST},
4435         {REG_BIM_CFG},
4436         {REG_RX_CFG},
4437         {REG_HP_CFG},
4438         {REG_MAC_TX_CFG},
4439         {REG_MAC_RX_CFG},
4440         {REG_MAC_CTRL_CFG},
4441         {REG_MAC_XIF_CFG},
4442         {REG_MIF_CFG},
4443         {REG_PCS_CFG},
4444         {REG_SATURN_PCFG},
4445         {REG_PCS_MII_STATUS},
4446         {REG_PCS_STATE_MACHINE},
4447         {REG_MAC_COLL_EXCESS},
4448         {REG_MAC_COLL_LATE}
4449 };
4450 #define CAS_REG_LEN     (sizeof(ethtool_register_table)/sizeof(int))
4451 #define CAS_MAX_REGS    (sizeof (u32)*CAS_REG_LEN)
4452
4453 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4454 {
4455         u8 *p;
4456         int i;
4457         unsigned long flags;
4458
4459         spin_lock_irqsave(&cp->lock, flags);
4460         for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4461                 u16 hval;
4462                 u32 val;
4463                 if (ethtool_register_table[i].offsets < 0) {
4464                         hval = cas_phy_read(cp,
4465                                     -ethtool_register_table[i].offsets);
4466                         val = hval;
4467                 } else {
4468                         val= readl(cp->regs+ethtool_register_table[i].offsets);
4469                 }
4470                 memcpy(p, (u8 *)&val, sizeof(u32));
4471         }
4472         spin_unlock_irqrestore(&cp->lock, flags);
4473 }
4474
4475 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4476 {
4477         struct cas *cp = netdev_priv(dev);
4478         struct net_device_stats *stats = cp->net_stats;
4479         unsigned long flags;
4480         int i;
4481         unsigned long tmp;
4482
4483         /* we collate all of the stats into net_stats[N_TX_RING] */
4484         if (!cp->hw_running)
4485                 return stats + N_TX_RINGS;
4486         
4487         /* collect outstanding stats */
4488         /* WTZ: the Cassini spec gives these as 16 bit counters but
4489          * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4490          * in case the chip somehow puts any garbage in the other bits.
4491          * Also, counter usage didn't seem to mach what Adrian did
4492          * in the parts of the code that set these quantities. Made
4493          * that consistent.
4494          */
4495         spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4496         stats[N_TX_RINGS].rx_crc_errors += 
4497           readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4498         stats[N_TX_RINGS].rx_frame_errors += 
4499                 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4500         stats[N_TX_RINGS].rx_length_errors += 
4501                 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4502 #if 1
4503         tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4504                 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4505         stats[N_TX_RINGS].tx_aborted_errors += tmp;
4506         stats[N_TX_RINGS].collisions +=
4507           tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4508 #else
4509         stats[N_TX_RINGS].tx_aborted_errors += 
4510                 readl(cp->regs + REG_MAC_COLL_EXCESS);
4511         stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4512                 readl(cp->regs + REG_MAC_COLL_LATE);
4513 #endif
4514         cas_clear_mac_err(cp);
4515
4516         /* saved bits that are unique to ring 0 */
4517         spin_lock(&cp->stat_lock[0]);
4518         stats[N_TX_RINGS].collisions        += stats[0].collisions;
4519         stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4520         stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4521         stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4522         stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4523         stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4524         spin_unlock(&cp->stat_lock[0]);
4525
4526         for (i = 0; i < N_TX_RINGS; i++) {
4527                 spin_lock(&cp->stat_lock[i]);
4528                 stats[N_TX_RINGS].rx_length_errors += 
4529                         stats[i].rx_length_errors;
4530                 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4531                 stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4532                 stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4533                 stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4534                 stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4535                 stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4536                 stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4537                 stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4538                 stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4539                 memset(stats + i, 0, sizeof(struct net_device_stats));
4540                 spin_unlock(&cp->stat_lock[i]);
4541         }
4542         spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4543         return stats + N_TX_RINGS;
4544 }
4545
4546
4547 static void cas_set_multicast(struct net_device *dev)
4548 {
4549         struct cas *cp = netdev_priv(dev);
4550         u32 rxcfg, rxcfg_new;
4551         unsigned long flags;
4552         int limit = STOP_TRIES;
4553         
4554         if (!cp->hw_running)
4555                 return;
4556                 
4557         spin_lock_irqsave(&cp->lock, flags);
4558         rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4559
4560         /* disable RX MAC and wait for completion */
4561         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4562         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4563                 if (!limit--)
4564                         break;
4565                 udelay(10);
4566         }
4567
4568         /* disable hash filter and wait for completion */
4569         limit = STOP_TRIES;
4570         rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4571         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4572         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4573                 if (!limit--)
4574                         break;
4575                 udelay(10);
4576         }
4577
4578         /* program hash filters */
4579         cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4580         rxcfg |= rxcfg_new;
4581         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4582         spin_unlock_irqrestore(&cp->lock, flags);
4583 }
4584
4585 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4586 {
4587         struct cas *cp = netdev_priv(dev);
4588         strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4589         strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4590         info->fw_version[0] = '\0';
4591         strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4592         info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4593                 cp->casreg_len : CAS_MAX_REGS;
4594         info->n_stats = CAS_NUM_STAT_KEYS;
4595 }
4596
4597 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4598 {
4599         struct cas *cp = netdev_priv(dev);
4600         u16 bmcr;
4601         int full_duplex, speed, pause;
4602         unsigned long flags;
4603         enum link_state linkstate = link_up;
4604
4605         cmd->advertising = 0;
4606         cmd->supported = SUPPORTED_Autoneg;
4607         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4608                 cmd->supported |= SUPPORTED_1000baseT_Full;
4609                 cmd->advertising |= ADVERTISED_1000baseT_Full;
4610         }
4611
4612         /* Record PHY settings if HW is on. */
4613         spin_lock_irqsave(&cp->lock, flags);
4614         bmcr = 0;
4615         linkstate = cp->lstate;
4616         if (CAS_PHY_MII(cp->phy_type)) {
4617                 cmd->port = PORT_MII;
4618                 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4619                         XCVR_INTERNAL : XCVR_EXTERNAL;
4620                 cmd->phy_address = cp->phy_addr;
4621                 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4622                         ADVERTISED_10baseT_Half | 
4623                         ADVERTISED_10baseT_Full | 
4624                         ADVERTISED_100baseT_Half | 
4625                         ADVERTISED_100baseT_Full;
4626
4627                 cmd->supported |=
4628                         (SUPPORTED_10baseT_Half | 
4629                          SUPPORTED_10baseT_Full |
4630                          SUPPORTED_100baseT_Half | 
4631                          SUPPORTED_100baseT_Full |
4632                          SUPPORTED_TP | SUPPORTED_MII);
4633
4634                 if (cp->hw_running) {
4635                         cas_mif_poll(cp, 0);
4636                         bmcr = cas_phy_read(cp, MII_BMCR);
4637                         cas_read_mii_link_mode(cp, &full_duplex, 
4638                                                &speed, &pause);
4639                         cas_mif_poll(cp, 1);
4640                 }
4641
4642         } else {
4643                 cmd->port = PORT_FIBRE;
4644                 cmd->transceiver = XCVR_INTERNAL;
4645                 cmd->phy_address = 0;
4646                 cmd->supported   |= SUPPORTED_FIBRE;
4647                 cmd->advertising |= ADVERTISED_FIBRE;
4648
4649                 if (cp->hw_running) {
4650                         /* pcs uses the same bits as mii */ 
4651                         bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4652                         cas_read_pcs_link_mode(cp, &full_duplex, 
4653                                                &speed, &pause);
4654                 }
4655         }
4656         spin_unlock_irqrestore(&cp->lock, flags);
4657
4658         if (bmcr & BMCR_ANENABLE) {
4659                 cmd->advertising |= ADVERTISED_Autoneg;
4660                 cmd->autoneg = AUTONEG_ENABLE;
4661                 cmd->speed = ((speed == 10) ?
4662                               SPEED_10 :
4663                               ((speed == 1000) ?
4664                                SPEED_1000 : SPEED_100));
4665                 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4666         } else {
4667                 cmd->autoneg = AUTONEG_DISABLE;
4668                 cmd->speed =
4669                         (bmcr & CAS_BMCR_SPEED1000) ?
4670                         SPEED_1000 : 
4671                         ((bmcr & BMCR_SPEED100) ? SPEED_100: 
4672                          SPEED_10);
4673                 cmd->duplex =
4674                         (bmcr & BMCR_FULLDPLX) ?
4675                         DUPLEX_FULL : DUPLEX_HALF;
4676         }
4677         if (linkstate != link_up) {
4678                 /* Force these to "unknown" if the link is not up and
4679                  * autonogotiation in enabled. We can set the link 
4680                  * speed to 0, but not cmd->duplex,
4681                  * because its legal values are 0 and 1.  Ethtool will
4682                  * print the value reported in parentheses after the
4683                  * word "Unknown" for unrecognized values.
4684                  *
4685                  * If in forced mode, we report the speed and duplex
4686                  * settings that we configured.
4687                  */
4688                 if (cp->link_cntl & BMCR_ANENABLE) {
4689                         cmd->speed = 0;
4690                         cmd->duplex = 0xff;
4691                 } else {
4692                         cmd->speed = SPEED_10;
4693                         if (cp->link_cntl & BMCR_SPEED100) {
4694                                 cmd->speed = SPEED_100;
4695                         } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4696                                 cmd->speed = SPEED_1000;
4697                         }
4698                         cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4699                                 DUPLEX_FULL : DUPLEX_HALF;
4700                 }
4701         }
4702         return 0;
4703 }
4704
4705 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4706 {
4707         struct cas *cp = netdev_priv(dev);
4708         unsigned long flags;
4709
4710         /* Verify the settings we care about. */
4711         if (cmd->autoneg != AUTONEG_ENABLE &&
4712             cmd->autoneg != AUTONEG_DISABLE)
4713                 return -EINVAL;
4714
4715         if (cmd->autoneg == AUTONEG_DISABLE &&
4716             ((cmd->speed != SPEED_1000 &&
4717               cmd->speed != SPEED_100 &&
4718               cmd->speed != SPEED_10) ||
4719              (cmd->duplex != DUPLEX_HALF &&
4720               cmd->duplex != DUPLEX_FULL)))
4721                 return -EINVAL;
4722
4723         /* Apply settings and restart link process. */
4724         spin_lock_irqsave(&cp->lock, flags);
4725         cas_begin_auto_negotiation(cp, cmd);
4726         spin_unlock_irqrestore(&cp->lock, flags);
4727         return 0;
4728 }
4729
4730 static int cas_nway_reset(struct net_device *dev)
4731 {
4732         struct cas *cp = netdev_priv(dev);
4733         unsigned long flags;
4734
4735         if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4736                 return -EINVAL;
4737
4738         /* Restart link process. */
4739         spin_lock_irqsave(&cp->lock, flags);
4740         cas_begin_auto_negotiation(cp, NULL);
4741         spin_unlock_irqrestore(&cp->lock, flags);
4742
4743         return 0;
4744 }
4745
4746 static u32 cas_get_link(struct net_device *dev)
4747 {
4748         struct cas *cp = netdev_priv(dev);
4749         return cp->lstate == link_up;
4750 }
4751
4752 static u32 cas_get_msglevel(struct net_device *dev)
4753 {
4754         struct cas *cp = netdev_priv(dev);
4755         return cp->msg_enable;
4756 }
4757
4758 static void cas_set_msglevel(struct net_device *dev, u32 value)
4759 {
4760         struct cas *cp = netdev_priv(dev);
4761         cp->msg_enable = value;
4762 }
4763
4764 static int cas_get_regs_len(struct net_device *dev)
4765 {
4766         struct cas *cp = netdev_priv(dev);
4767         return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4768 }
4769
4770 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4771                              void *p)
4772 {
4773         struct cas *cp = netdev_priv(dev);
4774         regs->version = 0;
4775         /* cas_read_regs handles locks (cp->lock).  */
4776         cas_read_regs(cp, p, regs->len / sizeof(u32));
4777 }
4778
4779 static int cas_get_stats_count(struct net_device *dev)
4780 {
4781         return CAS_NUM_STAT_KEYS;
4782 }
4783
4784 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4785 {
4786          memcpy(data, &ethtool_cassini_statnames, 
4787                                          CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4788 }
4789
4790 static void cas_get_ethtool_stats(struct net_device *dev,
4791                                       struct ethtool_stats *estats, u64 *data)
4792 {
4793         struct cas *cp = netdev_priv(dev);
4794         struct net_device_stats *stats = cas_get_stats(cp->dev);
4795         int i = 0;
4796         data[i++] = stats->collisions;
4797         data[i++] = stats->rx_bytes;
4798         data[i++] = stats->rx_crc_errors;
4799         data[i++] = stats->rx_dropped;
4800         data[i++] = stats->rx_errors;
4801         data[i++] = stats->rx_fifo_errors;
4802         data[i++] = stats->rx_frame_errors;
4803         data[i++] = stats->rx_length_errors;
4804         data[i++] = stats->rx_over_errors;
4805         data[i++] = stats->rx_packets;
4806         data[i++] = stats->tx_aborted_errors;
4807         data[i++] = stats->tx_bytes;
4808         data[i++] = stats->tx_dropped;
4809         data[i++] = stats->tx_errors;
4810         data[i++] = stats->tx_fifo_errors;
4811         data[i++] = stats->tx_packets;
4812         BUG_ON(i != CAS_NUM_STAT_KEYS);
4813 }
4814
4815 static struct ethtool_ops cas_ethtool_ops = {
4816         .get_drvinfo            = cas_get_drvinfo,
4817         .get_settings           = cas_get_settings,
4818         .set_settings           = cas_set_settings,
4819         .nway_reset             = cas_nway_reset,
4820         .get_link               = cas_get_link,
4821         .get_msglevel           = cas_get_msglevel,
4822         .set_msglevel           = cas_set_msglevel,
4823         .get_regs_len           = cas_get_regs_len,
4824         .get_regs               = cas_get_regs,
4825         .get_stats_count        = cas_get_stats_count,
4826         .get_strings            = cas_get_strings,
4827         .get_ethtool_stats      = cas_get_ethtool_stats,
4828 };
4829
4830 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4831 {
4832         struct cas *cp = netdev_priv(dev);
4833         struct mii_ioctl_data *data = if_mii(ifr);
4834         unsigned long flags;
4835         int rc = -EOPNOTSUPP;
4836         
4837         /* Hold the PM semaphore while doing ioctl's or we may collide
4838          * with open/close and power management and oops.
4839          */
4840         down(&cp->pm_sem);
4841         switch (cmd) {
4842         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
4843                 data->phy_id = cp->phy_addr;
4844                 /* Fallthrough... */
4845
4846         case SIOCGMIIREG:               /* Read MII PHY register. */
4847                 spin_lock_irqsave(&cp->lock, flags);
4848                 cas_mif_poll(cp, 0);
4849                 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4850                 cas_mif_poll(cp, 1);
4851                 spin_unlock_irqrestore(&cp->lock, flags);
4852                 rc = 0;
4853                 break;
4854
4855         case SIOCSMIIREG:               /* Write MII PHY register. */
4856                 if (!capable(CAP_NET_ADMIN)) {
4857                         rc = -EPERM;
4858                         break;
4859                 }
4860                 spin_lock_irqsave(&cp->lock, flags);
4861                 cas_mif_poll(cp, 0);
4862                 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4863                 cas_mif_poll(cp, 1);
4864                 spin_unlock_irqrestore(&cp->lock, flags);
4865                 break;
4866         default:
4867                 break;
4868         };
4869
4870         up(&cp->pm_sem);
4871         return rc;
4872 }
4873
4874 static int __devinit cas_init_one(struct pci_dev *pdev,
4875                                   const struct pci_device_id *ent)
4876 {
4877         static int cas_version_printed = 0;
4878         unsigned long casreg_base, casreg_len;
4879         struct net_device *dev;
4880         struct cas *cp;
4881         int i, err, pci_using_dac;
4882         u16 pci_cmd;
4883         u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4884
4885         if (cas_version_printed++ == 0)
4886                 printk(KERN_INFO "%s", version);
4887
4888         err = pci_enable_device(pdev);
4889         if (err) {
4890                 printk(KERN_ERR PFX "Cannot enable PCI device, "
4891                        "aborting.\n");
4892                 return err;
4893         }
4894
4895         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4896                 printk(KERN_ERR PFX "Cannot find proper PCI device "
4897                        "base address, aborting.\n");
4898                 err = -ENODEV;
4899                 goto err_out_disable_pdev;
4900         }
4901
4902         dev = alloc_etherdev(sizeof(*cp));
4903         if (!dev) {
4904                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
4905                 err = -ENOMEM;
4906                 goto err_out_disable_pdev;
4907         }
4908         SET_MODULE_OWNER(dev);
4909         SET_NETDEV_DEV(dev, &pdev->dev);
4910
4911         err = pci_request_regions(pdev, dev->name);
4912         if (err) {
4913                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
4914                        "aborting.\n");
4915                 goto err_out_free_netdev;
4916         }
4917         pci_set_master(pdev);
4918
4919         /* we must always turn on parity response or else parity
4920          * doesn't get generated properly. disable SERR/PERR as well.
4921          * in addition, we want to turn MWI on.
4922          */
4923         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4924         pci_cmd &= ~PCI_COMMAND_SERR;
4925         pci_cmd |= PCI_COMMAND_PARITY;
4926         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4927         pci_set_mwi(pdev);
4928         /*
4929          * On some architectures, the default cache line size set
4930          * by pci_set_mwi reduces perforamnce.  We have to increase
4931          * it for this case.  To start, we'll print some configuration
4932          * data.
4933          */
4934 #if 1
4935         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4936                              &orig_cacheline_size);
4937         if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4938                 cas_cacheline_size = 
4939                         (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ? 
4940                         CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4941                 if (pci_write_config_byte(pdev, 
4942                                           PCI_CACHE_LINE_SIZE, 
4943                                           cas_cacheline_size)) {
4944                         printk(KERN_ERR PFX "Could not set PCI cache "
4945                                "line size\n");
4946                         goto err_write_cacheline;
4947                 }
4948         }
4949 #endif
4950
4951
4952         /* Configure DMA attributes. */
4953         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4954                 pci_using_dac = 1;
4955                 err = pci_set_consistent_dma_mask(pdev,
4956                                                   DMA_64BIT_MASK);
4957                 if (err < 0) {
4958                         printk(KERN_ERR PFX "Unable to obtain 64-bit DMA "
4959                                "for consistent allocations\n");
4960                         goto err_out_free_res;
4961                 }
4962
4963         } else {
4964                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4965                 if (err) {
4966                         printk(KERN_ERR PFX "No usable DMA configuration, "
4967                                "aborting.\n");
4968                         goto err_out_free_res;
4969                 }
4970                 pci_using_dac = 0;
4971         }
4972
4973         casreg_base = pci_resource_start(pdev, 0);
4974         casreg_len = pci_resource_len(pdev, 0);
4975
4976         cp = netdev_priv(dev);
4977         cp->pdev = pdev;
4978 #if 1
4979         /* A value of 0 indicates we never explicitly set it */
4980         cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
4981 #endif
4982         cp->dev = dev;
4983         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE : 
4984           cassini_debug;
4985
4986         cp->link_transition = LINK_TRANSITION_UNKNOWN;
4987         cp->link_transition_jiffies_valid = 0;
4988
4989         spin_lock_init(&cp->lock);
4990         spin_lock_init(&cp->rx_inuse_lock);
4991         spin_lock_init(&cp->rx_spare_lock);
4992         for (i = 0; i < N_TX_RINGS; i++) {
4993                 spin_lock_init(&cp->stat_lock[i]);
4994                 spin_lock_init(&cp->tx_lock[i]);
4995         }
4996         spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
4997         init_MUTEX(&cp->pm_sem);
4998
4999         init_timer(&cp->link_timer);
5000         cp->link_timer.function = cas_link_timer;
5001         cp->link_timer.data = (unsigned long) cp;
5002
5003 #if 1
5004         /* Just in case the implementation of atomic operations
5005          * change so that an explicit initialization is necessary.
5006          */
5007         atomic_set(&cp->reset_task_pending, 0);
5008         atomic_set(&cp->reset_task_pending_all, 0);
5009         atomic_set(&cp->reset_task_pending_spare, 0);
5010         atomic_set(&cp->reset_task_pending_mtu, 0);
5011 #endif
5012         INIT_WORK(&cp->reset_task, cas_reset_task, cp);
5013
5014         /* Default link parameters */
5015         if (link_mode >= 0 && link_mode <= 6)
5016                 cp->link_cntl = link_modes[link_mode];
5017         else
5018                 cp->link_cntl = BMCR_ANENABLE;
5019         cp->lstate = link_down;
5020         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5021         netif_carrier_off(cp->dev);
5022         cp->timer_ticks = 0;
5023
5024         /* give us access to cassini registers */
5025         cp->regs = ioremap(casreg_base, casreg_len);
5026         if (cp->regs == 0UL) {
5027                 printk(KERN_ERR PFX "Cannot map device registers, "
5028                        "aborting.\n");
5029                 goto err_out_free_res;
5030         }
5031         cp->casreg_len = casreg_len;
5032
5033         pci_save_state(pdev);
5034         cas_check_pci_invariants(cp);
5035         cas_hard_reset(cp);
5036         cas_reset(cp, 0);
5037         if (cas_check_invariants(cp))
5038                 goto err_out_iounmap;
5039
5040         cp->init_block = (struct cas_init_block *)
5041                 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5042                                      &cp->block_dvma);
5043         if (!cp->init_block) {
5044                 printk(KERN_ERR PFX "Cannot allocate init block, "
5045                        "aborting.\n");
5046                 goto err_out_iounmap;
5047         }
5048
5049         for (i = 0; i < N_TX_RINGS; i++) 
5050                 cp->init_txds[i] = cp->init_block->txds[i];
5051
5052         for (i = 0; i < N_RX_DESC_RINGS; i++) 
5053                 cp->init_rxds[i] = cp->init_block->rxds[i];
5054
5055         for (i = 0; i < N_RX_COMP_RINGS; i++) 
5056                 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5057
5058         for (i = 0; i < N_RX_FLOWS; i++)
5059                 skb_queue_head_init(&cp->rx_flows[i]);
5060
5061         dev->open = cas_open;
5062         dev->stop = cas_close;
5063         dev->hard_start_xmit = cas_start_xmit;
5064         dev->get_stats = cas_get_stats;
5065         dev->set_multicast_list = cas_set_multicast;
5066         dev->do_ioctl = cas_ioctl;
5067         dev->ethtool_ops = &cas_ethtool_ops;
5068         dev->tx_timeout = cas_tx_timeout;
5069         dev->watchdog_timeo = CAS_TX_TIMEOUT;
5070         dev->change_mtu = cas_change_mtu;
5071 #ifdef USE_NAPI
5072         dev->poll = cas_poll;
5073         dev->weight = 64;
5074 #endif
5075 #ifdef CONFIG_NET_POLL_CONTROLLER
5076         dev->poll_controller = cas_netpoll;
5077 #endif
5078         dev->irq = pdev->irq;
5079         dev->dma = 0;
5080
5081         /* Cassini features. */
5082         if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5083                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5084
5085         if (pci_using_dac)
5086                 dev->features |= NETIF_F_HIGHDMA;
5087
5088         if (register_netdev(dev)) {
5089                 printk(KERN_ERR PFX "Cannot register net device, "
5090                        "aborting.\n");
5091                 goto err_out_free_consistent;
5092         }
5093
5094         i = readl(cp->regs + REG_BIM_CFG);
5095         printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5096                "Ethernet[%d] ",  dev->name, 
5097                (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "", 
5098                (i & BIM_CFG_32BIT) ? "32" : "64",
5099                (i & BIM_CFG_66MHZ) ? "66" : "33",
5100                (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq); 
5101
5102         for (i = 0; i < 6; i++)
5103                 printk("%2.2x%c", dev->dev_addr[i],
5104                        i == 5 ? ' ' : ':');
5105         printk("\n");
5106
5107         pci_set_drvdata(pdev, dev);
5108         cp->hw_running = 1;
5109         cas_entropy_reset(cp);
5110         cas_phy_init(cp);
5111         cas_begin_auto_negotiation(cp, NULL);
5112         return 0;
5113
5114 err_out_free_consistent:
5115         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5116                             cp->init_block, cp->block_dvma);
5117
5118 err_out_iounmap:
5119         down(&cp->pm_sem);
5120         if (cp->hw_running)
5121                 cas_shutdown(cp);
5122         up(&cp->pm_sem);
5123
5124         iounmap(cp->regs);
5125
5126
5127 err_out_free_res:
5128         pci_release_regions(pdev);
5129
5130 err_write_cacheline:
5131         /* Try to restore it in case the error occured after we
5132          * set it. 
5133          */
5134         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5135
5136 err_out_free_netdev:
5137         free_netdev(dev);
5138
5139 err_out_disable_pdev:
5140         pci_disable_device(pdev);
5141         pci_set_drvdata(pdev, NULL);
5142         return -ENODEV;
5143 }
5144
5145 static void __devexit cas_remove_one(struct pci_dev *pdev)
5146 {
5147         struct net_device *dev = pci_get_drvdata(pdev);
5148         struct cas *cp;
5149         if (!dev)
5150                 return;
5151
5152         cp = netdev_priv(dev);
5153         unregister_netdev(dev);
5154
5155         down(&cp->pm_sem);
5156         flush_scheduled_work();
5157         if (cp->hw_running)
5158                 cas_shutdown(cp);
5159         up(&cp->pm_sem);
5160
5161 #if 1
5162         if (cp->orig_cacheline_size) {
5163                 /* Restore the cache line size if we had modified
5164                  * it.
5165                  */
5166                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 
5167                                       cp->orig_cacheline_size);
5168         }
5169 #endif
5170         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5171                             cp->init_block, cp->block_dvma);
5172         iounmap(cp->regs);
5173         free_netdev(dev);
5174         pci_release_regions(pdev);
5175         pci_disable_device(pdev);
5176         pci_set_drvdata(pdev, NULL);
5177 }
5178
5179 #ifdef CONFIG_PM
5180 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5181 {
5182         struct net_device *dev = pci_get_drvdata(pdev);
5183         struct cas *cp = netdev_priv(dev);
5184         unsigned long flags;
5185
5186         /* We hold the PM semaphore during entire driver
5187          * sleep time
5188          */
5189         down(&cp->pm_sem);
5190         
5191         /* If the driver is opened, we stop the DMA */
5192         if (cp->opened) {
5193                 netif_device_detach(dev);
5194
5195                 cas_lock_all_save(cp, flags);
5196
5197                 /* We can set the second arg of cas_reset to 0
5198                  * because on resume, we'll call cas_init_hw with
5199                  * its second arg set so that autonegotiation is
5200                  * restarted.
5201                  */
5202                 cas_reset(cp, 0);
5203                 cas_clean_rings(cp);
5204                 cas_unlock_all_restore(cp, flags);
5205         }
5206
5207         if (cp->hw_running)
5208                 cas_shutdown(cp);
5209
5210         return 0;
5211 }
5212
5213 static int cas_resume(struct pci_dev *pdev)
5214 {
5215         struct net_device *dev = pci_get_drvdata(pdev);
5216         struct cas *cp = netdev_priv(dev);
5217
5218         printk(KERN_INFO "%s: resuming\n", dev->name);
5219
5220         cas_hard_reset(cp);
5221         if (cp->opened) {
5222                 unsigned long flags;
5223                 cas_lock_all_save(cp, flags);
5224                 cas_reset(cp, 0);
5225                 cp->hw_running = 1;
5226                 cas_clean_rings(cp);
5227                 cas_init_hw(cp, 1);
5228                 cas_unlock_all_restore(cp, flags);
5229
5230                 netif_device_attach(dev);
5231         }
5232         up(&cp->pm_sem);
5233         return 0;
5234 }
5235 #endif /* CONFIG_PM */
5236
5237 static struct pci_driver cas_driver = {
5238         .name           = DRV_MODULE_NAME,
5239         .id_table       = cas_pci_tbl,
5240         .probe          = cas_init_one,
5241         .remove         = __devexit_p(cas_remove_one),
5242 #ifdef CONFIG_PM
5243         .suspend        = cas_suspend,
5244         .resume         = cas_resume
5245 #endif
5246 };
5247
5248 static int __init cas_init(void)
5249 {
5250         if (linkdown_timeout > 0)
5251                 link_transition_timeout = linkdown_timeout * HZ;
5252         else
5253                 link_transition_timeout = 0;
5254
5255         return pci_module_init(&cas_driver);
5256 }
5257
5258 static void __exit cas_cleanup(void)
5259 {
5260         pci_unregister_driver(&cas_driver);
5261 }
5262
5263 module_init(cas_init);
5264 module_exit(cas_cleanup);