Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / cassini.c
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2  *
3  * Copyright (C) 2004 Sun Microsystems Inc.
4  * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19  * 02111-1307, USA.
20  *
21  * This driver uses the sungem driver (c) David Miller
22  * (davem@redhat.com) as its basis.
23  *
24  * The cassini chip has a number of features that distinguish it from
25  * the gem chip:
26  *  4 transmit descriptor rings that are used for either QoS (VLAN) or
27  *      load balancing (non-VLAN mode)
28  *  batching of multiple packets
29  *  multiple CPU dispatching
30  *  page-based RX descriptor engine with separate completion rings
31  *  Gigabit support (GMII and PCS interface)
32  *  MIF link up/down detection works
33  *
34  * RX is handled by page sized buffers that are attached as fragments to
35  * the skb. here's what's done:
36  *  -- driver allocates pages at a time and keeps reference counts
37  *     on them.
38  *  -- the upper protocol layers assume that the header is in the skb
39  *     itself. as a result, cassini will copy a small amount (64 bytes)
40  *     to make them happy.
41  *  -- driver appends the rest of the data pages as frags to skbuffs
42  *     and increments the reference count
43  *  -- on page reclamation, the driver swaps the page with a spare page.
44  *     if that page is still in use, it frees its reference to that page,
45  *     and allocates a new page for use. otherwise, it just recycles the
46  *     the page.
47  *
48  * NOTE: cassini can parse the header. however, it's not worth it
49  *       as long as the network stack requires a header copy.
50  *
51  * TX has 4 queues. currently these queues are used in a round-robin
52  * fashion for load balancing. They can also be used for QoS. for that
53  * to work, however, QoS information needs to be exposed down to the driver
54  * level so that subqueues get targeted to particular transmit rings.
55  * alternatively, the queues can be configured via use of the all-purpose
56  * ioctl.
57  *
58  * RX DATA: the rx completion ring has all the info, but the rx desc
59  * ring has all of the data. RX can conceivably come in under multiple
60  * interrupts, but the INT# assignment needs to be set up properly by
61  * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62  * that. also, the two descriptor rings are designed to distinguish between
63  * encrypted and non-encrypted packets, but we use them for buffering
64  * instead.
65  *
66  * by default, the selective clear mask is set up to process rx packets.
67  */
68
69 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/vmalloc.h>
79 #include <linux/ioport.h>
80 #include <linux/pci.h>
81 #include <linux/mm.h>
82 #include <linux/highmem.h>
83 #include <linux/list.h>
84 #include <linux/dma-mapping.h>
85
86 #include <linux/netdevice.h>
87 #include <linux/etherdevice.h>
88 #include <linux/skbuff.h>
89 #include <linux/ethtool.h>
90 #include <linux/crc32.h>
91 #include <linux/random.h>
92 #include <linux/mii.h>
93 #include <linux/ip.h>
94 #include <linux/tcp.h>
95 #include <linux/mutex.h>
96 #include <linux/firmware.h>
97
98 #include <net/checksum.h>
99
100 #include <asm/atomic.h>
101 #include <asm/system.h>
102 #include <asm/io.h>
103 #include <asm/byteorder.h>
104 #include <asm/uaccess.h>
105
106 #define cas_page_map(x)      kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
107 #define cas_page_unmap(x)    kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
108 #define CAS_NCPUS            num_online_cpus()
109
110 #define cas_skb_release(x)  netif_rx(x)
111
112 /* select which firmware to use */
113 #define USE_HP_WORKAROUND
114 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
115 #define CAS_HP_ALT_FIRMWARE   cas_prog_null /* alternate firmware */
116
117 #include "cassini.h"
118
119 #define USE_TX_COMPWB      /* use completion writeback registers */
120 #define USE_CSMA_CD_PROTO  /* standard CSMA/CD */
121 #define USE_RX_BLANK       /* hw interrupt mitigation */
122 #undef USE_ENTROPY_DEV     /* don't test for entropy device */
123
124 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
125  * also, we need to make cp->lock finer-grained.
126  */
127 #undef  USE_PCI_INTB
128 #undef  USE_PCI_INTC
129 #undef  USE_PCI_INTD
130 #undef  USE_QOS
131
132 #undef  USE_VPD_DEBUG       /* debug vpd information if defined */
133
134 /* rx processing options */
135 #define USE_PAGE_ORDER      /* specify to allocate large rx pages */
136 #define RX_DONT_BATCH  0    /* if 1, don't batch flows */
137 #define RX_COPY_ALWAYS 0    /* if 0, use frags */
138 #define RX_COPY_MIN    64   /* copy a little to make upper layers happy */
139 #undef  RX_COUNT_BUFFERS    /* define to calculate RX buffer stats */
140
141 #define DRV_MODULE_NAME         "cassini"
142 #define DRV_MODULE_VERSION      "1.6"
143 #define DRV_MODULE_RELDATE      "21 May 2008"
144
145 #define CAS_DEF_MSG_ENABLE        \
146         (NETIF_MSG_DRV          | \
147          NETIF_MSG_PROBE        | \
148          NETIF_MSG_LINK         | \
149          NETIF_MSG_TIMER        | \
150          NETIF_MSG_IFDOWN       | \
151          NETIF_MSG_IFUP         | \
152          NETIF_MSG_RX_ERR       | \
153          NETIF_MSG_TX_ERR)
154
155 /* length of time before we decide the hardware is borked,
156  * and dev->tx_timeout() should be called to fix the problem
157  */
158 #define CAS_TX_TIMEOUT                  (HZ)
159 #define CAS_LINK_TIMEOUT                (22*HZ/10)
160 #define CAS_LINK_FAST_TIMEOUT           (1)
161
162 /* timeout values for state changing. these specify the number
163  * of 10us delays to be used before giving up.
164  */
165 #define STOP_TRIES_PHY 1000
166 #define STOP_TRIES     5000
167
168 /* specify a minimum frame size to deal with some fifo issues
169  * max mtu == 2 * page size - ethernet header - 64 - swivel =
170  *            2 * page_size - 0x50
171  */
172 #define CAS_MIN_FRAME                   97
173 #define CAS_1000MB_MIN_FRAME            255
174 #define CAS_MIN_MTU                     60
175 #define CAS_MAX_MTU                     min(((cp->page_size << 1) - 0x50), 9000)
176
177 #if 1
178 /*
179  * Eliminate these and use separate atomic counters for each, to
180  * avoid a race condition.
181  */
182 #else
183 #define CAS_RESET_MTU                   1
184 #define CAS_RESET_ALL                   2
185 #define CAS_RESET_SPARE                 3
186 #endif
187
188 static char version[] __devinitdata =
189         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
190
191 static int cassini_debug = -1;  /* -1 == use CAS_DEF_MSG_ENABLE as value */
192 static int link_mode;
193
194 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
195 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
196 MODULE_LICENSE("GPL");
197 MODULE_FIRMWARE("sun/cassini.bin");
198 module_param(cassini_debug, int, 0);
199 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
200 module_param(link_mode, int, 0);
201 MODULE_PARM_DESC(link_mode, "default link mode");
202
203 /*
204  * Work around for a PCS bug in which the link goes down due to the chip
205  * being confused and never showing a link status of "up."
206  */
207 #define DEFAULT_LINKDOWN_TIMEOUT 5
208 /*
209  * Value in seconds, for user input.
210  */
211 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
212 module_param(linkdown_timeout, int, 0);
213 MODULE_PARM_DESC(linkdown_timeout,
214 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
215
216 /*
217  * value in 'ticks' (units used by jiffies). Set when we init the
218  * module because 'HZ' in actually a function call on some flavors of
219  * Linux.  This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
220  */
221 static int link_transition_timeout;
222
223
224
225 static u16 link_modes[] __devinitdata = {
226         BMCR_ANENABLE,                   /* 0 : autoneg */
227         0,                               /* 1 : 10bt half duplex */
228         BMCR_SPEED100,                   /* 2 : 100bt half duplex */
229         BMCR_FULLDPLX,                   /* 3 : 10bt full duplex */
230         BMCR_SPEED100|BMCR_FULLDPLX,     /* 4 : 100bt full duplex */
231         CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
232 };
233
234 static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = {
235         { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
236           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
237         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239         { 0, }
240 };
241
242 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
243
244 static void cas_set_link_modes(struct cas *cp);
245
246 static inline void cas_lock_tx(struct cas *cp)
247 {
248         int i;
249
250         for (i = 0; i < N_TX_RINGS; i++)
251                 spin_lock(&cp->tx_lock[i]);
252 }
253
254 static inline void cas_lock_all(struct cas *cp)
255 {
256         spin_lock_irq(&cp->lock);
257         cas_lock_tx(cp);
258 }
259
260 /* WTZ: QA was finding deadlock problems with the previous
261  * versions after long test runs with multiple cards per machine.
262  * See if replacing cas_lock_all with safer versions helps. The
263  * symptoms QA is reporting match those we'd expect if interrupts
264  * aren't being properly restored, and we fixed a previous deadlock
265  * with similar symptoms by using save/restore versions in other
266  * places.
267  */
268 #define cas_lock_all_save(cp, flags) \
269 do { \
270         struct cas *xxxcp = (cp); \
271         spin_lock_irqsave(&xxxcp->lock, flags); \
272         cas_lock_tx(xxxcp); \
273 } while (0)
274
275 static inline void cas_unlock_tx(struct cas *cp)
276 {
277         int i;
278
279         for (i = N_TX_RINGS; i > 0; i--)
280                 spin_unlock(&cp->tx_lock[i - 1]);
281 }
282
283 static inline void cas_unlock_all(struct cas *cp)
284 {
285         cas_unlock_tx(cp);
286         spin_unlock_irq(&cp->lock);
287 }
288
289 #define cas_unlock_all_restore(cp, flags) \
290 do { \
291         struct cas *xxxcp = (cp); \
292         cas_unlock_tx(xxxcp); \
293         spin_unlock_irqrestore(&xxxcp->lock, flags); \
294 } while (0)
295
296 static void cas_disable_irq(struct cas *cp, const int ring)
297 {
298         /* Make sure we won't get any more interrupts */
299         if (ring == 0) {
300                 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
301                 return;
302         }
303
304         /* disable completion interrupts and selectively mask */
305         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
306                 switch (ring) {
307 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
308 #ifdef USE_PCI_INTB
309                 case 1:
310 #endif
311 #ifdef USE_PCI_INTC
312                 case 2:
313 #endif
314 #ifdef USE_PCI_INTD
315                 case 3:
316 #endif
317                         writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
318                                cp->regs + REG_PLUS_INTRN_MASK(ring));
319                         break;
320 #endif
321                 default:
322                         writel(INTRN_MASK_CLEAR_ALL, cp->regs +
323                                REG_PLUS_INTRN_MASK(ring));
324                         break;
325                 }
326         }
327 }
328
329 static inline void cas_mask_intr(struct cas *cp)
330 {
331         int i;
332
333         for (i = 0; i < N_RX_COMP_RINGS; i++)
334                 cas_disable_irq(cp, i);
335 }
336
337 static void cas_enable_irq(struct cas *cp, const int ring)
338 {
339         if (ring == 0) { /* all but TX_DONE */
340                 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
341                 return;
342         }
343
344         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
345                 switch (ring) {
346 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
347 #ifdef USE_PCI_INTB
348                 case 1:
349 #endif
350 #ifdef USE_PCI_INTC
351                 case 2:
352 #endif
353 #ifdef USE_PCI_INTD
354                 case 3:
355 #endif
356                         writel(INTRN_MASK_RX_EN, cp->regs +
357                                REG_PLUS_INTRN_MASK(ring));
358                         break;
359 #endif
360                 default:
361                         break;
362                 }
363         }
364 }
365
366 static inline void cas_unmask_intr(struct cas *cp)
367 {
368         int i;
369
370         for (i = 0; i < N_RX_COMP_RINGS; i++)
371                 cas_enable_irq(cp, i);
372 }
373
374 static inline void cas_entropy_gather(struct cas *cp)
375 {
376 #ifdef USE_ENTROPY_DEV
377         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
378                 return;
379
380         batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
381                             readl(cp->regs + REG_ENTROPY_IV),
382                             sizeof(uint64_t)*8);
383 #endif
384 }
385
386 static inline void cas_entropy_reset(struct cas *cp)
387 {
388 #ifdef USE_ENTROPY_DEV
389         if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
390                 return;
391
392         writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
393                cp->regs + REG_BIM_LOCAL_DEV_EN);
394         writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
395         writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
396
397         /* if we read back 0x0, we don't have an entropy device */
398         if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
399                 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
400 #endif
401 }
402
403 /* access to the phy. the following assumes that we've initialized the MIF to
404  * be in frame rather than bit-bang mode
405  */
406 static u16 cas_phy_read(struct cas *cp, int reg)
407 {
408         u32 cmd;
409         int limit = STOP_TRIES_PHY;
410
411         cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
412         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
413         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
414         cmd |= MIF_FRAME_TURN_AROUND_MSB;
415         writel(cmd, cp->regs + REG_MIF_FRAME);
416
417         /* poll for completion */
418         while (limit-- > 0) {
419                 udelay(10);
420                 cmd = readl(cp->regs + REG_MIF_FRAME);
421                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
422                         return cmd & MIF_FRAME_DATA_MASK;
423         }
424         return 0xFFFF; /* -1 */
425 }
426
427 static int cas_phy_write(struct cas *cp, int reg, u16 val)
428 {
429         int limit = STOP_TRIES_PHY;
430         u32 cmd;
431
432         cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
433         cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
434         cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
435         cmd |= MIF_FRAME_TURN_AROUND_MSB;
436         cmd |= val & MIF_FRAME_DATA_MASK;
437         writel(cmd, cp->regs + REG_MIF_FRAME);
438
439         /* poll for completion */
440         while (limit-- > 0) {
441                 udelay(10);
442                 cmd = readl(cp->regs + REG_MIF_FRAME);
443                 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
444                         return 0;
445         }
446         return -1;
447 }
448
449 static void cas_phy_powerup(struct cas *cp)
450 {
451         u16 ctl = cas_phy_read(cp, MII_BMCR);
452
453         if ((ctl & BMCR_PDOWN) == 0)
454                 return;
455         ctl &= ~BMCR_PDOWN;
456         cas_phy_write(cp, MII_BMCR, ctl);
457 }
458
459 static void cas_phy_powerdown(struct cas *cp)
460 {
461         u16 ctl = cas_phy_read(cp, MII_BMCR);
462
463         if (ctl & BMCR_PDOWN)
464                 return;
465         ctl |= BMCR_PDOWN;
466         cas_phy_write(cp, MII_BMCR, ctl);
467 }
468
469 /* cp->lock held. note: the last put_page will free the buffer */
470 static int cas_page_free(struct cas *cp, cas_page_t *page)
471 {
472         pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
473                        PCI_DMA_FROMDEVICE);
474         __free_pages(page->buffer, cp->page_order);
475         kfree(page);
476         return 0;
477 }
478
479 #ifdef RX_COUNT_BUFFERS
480 #define RX_USED_ADD(x, y)       ((x)->used += (y))
481 #define RX_USED_SET(x, y)       ((x)->used  = (y))
482 #else
483 #define RX_USED_ADD(x, y)
484 #define RX_USED_SET(x, y)
485 #endif
486
487 /* local page allocation routines for the receive buffers. jumbo pages
488  * require at least 8K contiguous and 8K aligned buffers.
489  */
490 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
491 {
492         cas_page_t *page;
493
494         page = kmalloc(sizeof(cas_page_t), flags);
495         if (!page)
496                 return NULL;
497
498         INIT_LIST_HEAD(&page->list);
499         RX_USED_SET(page, 0);
500         page->buffer = alloc_pages(flags, cp->page_order);
501         if (!page->buffer)
502                 goto page_err;
503         page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
504                                       cp->page_size, PCI_DMA_FROMDEVICE);
505         return page;
506
507 page_err:
508         kfree(page);
509         return NULL;
510 }
511
512 /* initialize spare pool of rx buffers, but allocate during the open */
513 static void cas_spare_init(struct cas *cp)
514 {
515         spin_lock(&cp->rx_inuse_lock);
516         INIT_LIST_HEAD(&cp->rx_inuse_list);
517         spin_unlock(&cp->rx_inuse_lock);
518
519         spin_lock(&cp->rx_spare_lock);
520         INIT_LIST_HEAD(&cp->rx_spare_list);
521         cp->rx_spares_needed = RX_SPARE_COUNT;
522         spin_unlock(&cp->rx_spare_lock);
523 }
524
525 /* used on close. free all the spare buffers. */
526 static void cas_spare_free(struct cas *cp)
527 {
528         struct list_head list, *elem, *tmp;
529
530         /* free spare buffers */
531         INIT_LIST_HEAD(&list);
532         spin_lock(&cp->rx_spare_lock);
533         list_splice_init(&cp->rx_spare_list, &list);
534         spin_unlock(&cp->rx_spare_lock);
535         list_for_each_safe(elem, tmp, &list) {
536                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
537         }
538
539         INIT_LIST_HEAD(&list);
540 #if 1
541         /*
542          * Looks like Adrian had protected this with a different
543          * lock than used everywhere else to manipulate this list.
544          */
545         spin_lock(&cp->rx_inuse_lock);
546         list_splice_init(&cp->rx_inuse_list, &list);
547         spin_unlock(&cp->rx_inuse_lock);
548 #else
549         spin_lock(&cp->rx_spare_lock);
550         list_splice_init(&cp->rx_inuse_list, &list);
551         spin_unlock(&cp->rx_spare_lock);
552 #endif
553         list_for_each_safe(elem, tmp, &list) {
554                 cas_page_free(cp, list_entry(elem, cas_page_t, list));
555         }
556 }
557
558 /* replenish spares if needed */
559 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
560 {
561         struct list_head list, *elem, *tmp;
562         int needed, i;
563
564         /* check inuse list. if we don't need any more free buffers,
565          * just free it
566          */
567
568         /* make a local copy of the list */
569         INIT_LIST_HEAD(&list);
570         spin_lock(&cp->rx_inuse_lock);
571         list_splice_init(&cp->rx_inuse_list, &list);
572         spin_unlock(&cp->rx_inuse_lock);
573
574         list_for_each_safe(elem, tmp, &list) {
575                 cas_page_t *page = list_entry(elem, cas_page_t, list);
576
577                 /*
578                  * With the lockless pagecache, cassini buffering scheme gets
579                  * slightly less accurate: we might find that a page has an
580                  * elevated reference count here, due to a speculative ref,
581                  * and skip it as in-use. Ideally we would be able to reclaim
582                  * it. However this would be such a rare case, it doesn't
583                  * matter too much as we should pick it up the next time round.
584                  *
585                  * Importantly, if we find that the page has a refcount of 1
586                  * here (our refcount), then we know it is definitely not inuse
587                  * so we can reuse it.
588                  */
589                 if (page_count(page->buffer) > 1)
590                         continue;
591
592                 list_del(elem);
593                 spin_lock(&cp->rx_spare_lock);
594                 if (cp->rx_spares_needed > 0) {
595                         list_add(elem, &cp->rx_spare_list);
596                         cp->rx_spares_needed--;
597                         spin_unlock(&cp->rx_spare_lock);
598                 } else {
599                         spin_unlock(&cp->rx_spare_lock);
600                         cas_page_free(cp, page);
601                 }
602         }
603
604         /* put any inuse buffers back on the list */
605         if (!list_empty(&list)) {
606                 spin_lock(&cp->rx_inuse_lock);
607                 list_splice(&list, &cp->rx_inuse_list);
608                 spin_unlock(&cp->rx_inuse_lock);
609         }
610
611         spin_lock(&cp->rx_spare_lock);
612         needed = cp->rx_spares_needed;
613         spin_unlock(&cp->rx_spare_lock);
614         if (!needed)
615                 return;
616
617         /* we still need spares, so try to allocate some */
618         INIT_LIST_HEAD(&list);
619         i = 0;
620         while (i < needed) {
621                 cas_page_t *spare = cas_page_alloc(cp, flags);
622                 if (!spare)
623                         break;
624                 list_add(&spare->list, &list);
625                 i++;
626         }
627
628         spin_lock(&cp->rx_spare_lock);
629         list_splice(&list, &cp->rx_spare_list);
630         cp->rx_spares_needed -= i;
631         spin_unlock(&cp->rx_spare_lock);
632 }
633
634 /* pull a page from the list. */
635 static cas_page_t *cas_page_dequeue(struct cas *cp)
636 {
637         struct list_head *entry;
638         int recover;
639
640         spin_lock(&cp->rx_spare_lock);
641         if (list_empty(&cp->rx_spare_list)) {
642                 /* try to do a quick recovery */
643                 spin_unlock(&cp->rx_spare_lock);
644                 cas_spare_recover(cp, GFP_ATOMIC);
645                 spin_lock(&cp->rx_spare_lock);
646                 if (list_empty(&cp->rx_spare_list)) {
647                         netif_err(cp, rx_err, cp->dev,
648                                   "no spare buffers available\n");
649                         spin_unlock(&cp->rx_spare_lock);
650                         return NULL;
651                 }
652         }
653
654         entry = cp->rx_spare_list.next;
655         list_del(entry);
656         recover = ++cp->rx_spares_needed;
657         spin_unlock(&cp->rx_spare_lock);
658
659         /* trigger the timer to do the recovery */
660         if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
661 #if 1
662                 atomic_inc(&cp->reset_task_pending);
663                 atomic_inc(&cp->reset_task_pending_spare);
664                 schedule_work(&cp->reset_task);
665 #else
666                 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
667                 schedule_work(&cp->reset_task);
668 #endif
669         }
670         return list_entry(entry, cas_page_t, list);
671 }
672
673
674 static void cas_mif_poll(struct cas *cp, const int enable)
675 {
676         u32 cfg;
677
678         cfg  = readl(cp->regs + REG_MIF_CFG);
679         cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
680
681         if (cp->phy_type & CAS_PHY_MII_MDIO1)
682                 cfg |= MIF_CFG_PHY_SELECT;
683
684         /* poll and interrupt on link status change. */
685         if (enable) {
686                 cfg |= MIF_CFG_POLL_EN;
687                 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
688                 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
689         }
690         writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
691                cp->regs + REG_MIF_MASK);
692         writel(cfg, cp->regs + REG_MIF_CFG);
693 }
694
695 /* Must be invoked under cp->lock */
696 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
697 {
698         u16 ctl;
699 #if 1
700         int lcntl;
701         int changed = 0;
702         int oldstate = cp->lstate;
703         int link_was_not_down = !(oldstate == link_down);
704 #endif
705         /* Setup link parameters */
706         if (!ep)
707                 goto start_aneg;
708         lcntl = cp->link_cntl;
709         if (ep->autoneg == AUTONEG_ENABLE)
710                 cp->link_cntl = BMCR_ANENABLE;
711         else {
712                 u32 speed = ethtool_cmd_speed(ep);
713                 cp->link_cntl = 0;
714                 if (speed == SPEED_100)
715                         cp->link_cntl |= BMCR_SPEED100;
716                 else if (speed == SPEED_1000)
717                         cp->link_cntl |= CAS_BMCR_SPEED1000;
718                 if (ep->duplex == DUPLEX_FULL)
719                         cp->link_cntl |= BMCR_FULLDPLX;
720         }
721 #if 1
722         changed = (lcntl != cp->link_cntl);
723 #endif
724 start_aneg:
725         if (cp->lstate == link_up) {
726                 netdev_info(cp->dev, "PCS link down\n");
727         } else {
728                 if (changed) {
729                         netdev_info(cp->dev, "link configuration changed\n");
730                 }
731         }
732         cp->lstate = link_down;
733         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
734         if (!cp->hw_running)
735                 return;
736 #if 1
737         /*
738          * WTZ: If the old state was link_up, we turn off the carrier
739          * to replicate everything we do elsewhere on a link-down
740          * event when we were already in a link-up state..
741          */
742         if (oldstate == link_up)
743                 netif_carrier_off(cp->dev);
744         if (changed  && link_was_not_down) {
745                 /*
746                  * WTZ: This branch will simply schedule a full reset after
747                  * we explicitly changed link modes in an ioctl. See if this
748                  * fixes the link-problems we were having for forced mode.
749                  */
750                 atomic_inc(&cp->reset_task_pending);
751                 atomic_inc(&cp->reset_task_pending_all);
752                 schedule_work(&cp->reset_task);
753                 cp->timer_ticks = 0;
754                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
755                 return;
756         }
757 #endif
758         if (cp->phy_type & CAS_PHY_SERDES) {
759                 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
760
761                 if (cp->link_cntl & BMCR_ANENABLE) {
762                         val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
763                         cp->lstate = link_aneg;
764                 } else {
765                         if (cp->link_cntl & BMCR_FULLDPLX)
766                                 val |= PCS_MII_CTRL_DUPLEX;
767                         val &= ~PCS_MII_AUTONEG_EN;
768                         cp->lstate = link_force_ok;
769                 }
770                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
771                 writel(val, cp->regs + REG_PCS_MII_CTRL);
772
773         } else {
774                 cas_mif_poll(cp, 0);
775                 ctl = cas_phy_read(cp, MII_BMCR);
776                 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
777                          CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
778                 ctl |= cp->link_cntl;
779                 if (ctl & BMCR_ANENABLE) {
780                         ctl |= BMCR_ANRESTART;
781                         cp->lstate = link_aneg;
782                 } else {
783                         cp->lstate = link_force_ok;
784                 }
785                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
786                 cas_phy_write(cp, MII_BMCR, ctl);
787                 cas_mif_poll(cp, 1);
788         }
789
790         cp->timer_ticks = 0;
791         mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
792 }
793
794 /* Must be invoked under cp->lock. */
795 static int cas_reset_mii_phy(struct cas *cp)
796 {
797         int limit = STOP_TRIES_PHY;
798         u16 val;
799
800         cas_phy_write(cp, MII_BMCR, BMCR_RESET);
801         udelay(100);
802         while (--limit) {
803                 val = cas_phy_read(cp, MII_BMCR);
804                 if ((val & BMCR_RESET) == 0)
805                         break;
806                 udelay(10);
807         }
808         return limit <= 0;
809 }
810
811 static int cas_saturn_firmware_init(struct cas *cp)
812 {
813         const struct firmware *fw;
814         const char fw_name[] = "sun/cassini.bin";
815         int err;
816
817         if (PHY_NS_DP83065 != cp->phy_id)
818                 return 0;
819
820         err = request_firmware(&fw, fw_name, &cp->pdev->dev);
821         if (err) {
822                 pr_err("Failed to load firmware \"%s\"\n",
823                        fw_name);
824                 return err;
825         }
826         if (fw->size < 2) {
827                 pr_err("bogus length %zu in \"%s\"\n",
828                        fw->size, fw_name);
829                 err = -EINVAL;
830                 goto out;
831         }
832         cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
833         cp->fw_size = fw->size - 2;
834         cp->fw_data = vmalloc(cp->fw_size);
835         if (!cp->fw_data) {
836                 err = -ENOMEM;
837                 pr_err("\"%s\" Failed %d\n", fw_name, err);
838                 goto out;
839         }
840         memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
841 out:
842         release_firmware(fw);
843         return err;
844 }
845
846 static void cas_saturn_firmware_load(struct cas *cp)
847 {
848         int i;
849
850         cas_phy_powerdown(cp);
851
852         /* expanded memory access mode */
853         cas_phy_write(cp, DP83065_MII_MEM, 0x0);
854
855         /* pointer configuration for new firmware */
856         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
857         cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
858         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
859         cas_phy_write(cp, DP83065_MII_REGD, 0x82);
860         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
861         cas_phy_write(cp, DP83065_MII_REGD, 0x0);
862         cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
863         cas_phy_write(cp, DP83065_MII_REGD, 0x39);
864
865         /* download new firmware */
866         cas_phy_write(cp, DP83065_MII_MEM, 0x1);
867         cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
868         for (i = 0; i < cp->fw_size; i++)
869                 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
870
871         /* enable firmware */
872         cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
873         cas_phy_write(cp, DP83065_MII_REGD, 0x1);
874 }
875
876
877 /* phy initialization */
878 static void cas_phy_init(struct cas *cp)
879 {
880         u16 val;
881
882         /* if we're in MII/GMII mode, set up phy */
883         if (CAS_PHY_MII(cp->phy_type)) {
884                 writel(PCS_DATAPATH_MODE_MII,
885                        cp->regs + REG_PCS_DATAPATH_MODE);
886
887                 cas_mif_poll(cp, 0);
888                 cas_reset_mii_phy(cp); /* take out of isolate mode */
889
890                 if (PHY_LUCENT_B0 == cp->phy_id) {
891                         /* workaround link up/down issue with lucent */
892                         cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
893                         cas_phy_write(cp, MII_BMCR, 0x00f1);
894                         cas_phy_write(cp, LUCENT_MII_REG, 0x0);
895
896                 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
897                         /* workarounds for broadcom phy */
898                         cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
899                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
900                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
901                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
902                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
903                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
904                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
905                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
906                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
907                         cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
908                         cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
909
910                 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
911                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
912                         val = cas_phy_read(cp, BROADCOM_MII_REG4);
913                         if (val & 0x0080) {
914                                 /* link workaround */
915                                 cas_phy_write(cp, BROADCOM_MII_REG4,
916                                               val & ~0x0080);
917                         }
918
919                 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
920                         writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
921                                SATURN_PCFG_FSI : 0x0,
922                                cp->regs + REG_SATURN_PCFG);
923
924                         /* load firmware to address 10Mbps auto-negotiation
925                          * issue. NOTE: this will need to be changed if the
926                          * default firmware gets fixed.
927                          */
928                         if (PHY_NS_DP83065 == cp->phy_id) {
929                                 cas_saturn_firmware_load(cp);
930                         }
931                         cas_phy_powerup(cp);
932                 }
933
934                 /* advertise capabilities */
935                 val = cas_phy_read(cp, MII_BMCR);
936                 val &= ~BMCR_ANENABLE;
937                 cas_phy_write(cp, MII_BMCR, val);
938                 udelay(10);
939
940                 cas_phy_write(cp, MII_ADVERTISE,
941                               cas_phy_read(cp, MII_ADVERTISE) |
942                               (ADVERTISE_10HALF | ADVERTISE_10FULL |
943                                ADVERTISE_100HALF | ADVERTISE_100FULL |
944                                CAS_ADVERTISE_PAUSE |
945                                CAS_ADVERTISE_ASYM_PAUSE));
946
947                 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
948                         /* make sure that we don't advertise half
949                          * duplex to avoid a chip issue
950                          */
951                         val  = cas_phy_read(cp, CAS_MII_1000_CTRL);
952                         val &= ~CAS_ADVERTISE_1000HALF;
953                         val |= CAS_ADVERTISE_1000FULL;
954                         cas_phy_write(cp, CAS_MII_1000_CTRL, val);
955                 }
956
957         } else {
958                 /* reset pcs for serdes */
959                 u32 val;
960                 int limit;
961
962                 writel(PCS_DATAPATH_MODE_SERDES,
963                        cp->regs + REG_PCS_DATAPATH_MODE);
964
965                 /* enable serdes pins on saturn */
966                 if (cp->cas_flags & CAS_FLAG_SATURN)
967                         writel(0, cp->regs + REG_SATURN_PCFG);
968
969                 /* Reset PCS unit. */
970                 val = readl(cp->regs + REG_PCS_MII_CTRL);
971                 val |= PCS_MII_RESET;
972                 writel(val, cp->regs + REG_PCS_MII_CTRL);
973
974                 limit = STOP_TRIES;
975                 while (--limit > 0) {
976                         udelay(10);
977                         if ((readl(cp->regs + REG_PCS_MII_CTRL) &
978                              PCS_MII_RESET) == 0)
979                                 break;
980                 }
981                 if (limit <= 0)
982                         netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
983                                     readl(cp->regs + REG_PCS_STATE_MACHINE));
984
985                 /* Make sure PCS is disabled while changing advertisement
986                  * configuration.
987                  */
988                 writel(0x0, cp->regs + REG_PCS_CFG);
989
990                 /* Advertise all capabilities except half-duplex. */
991                 val  = readl(cp->regs + REG_PCS_MII_ADVERT);
992                 val &= ~PCS_MII_ADVERT_HD;
993                 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
994                         PCS_MII_ADVERT_ASYM_PAUSE);
995                 writel(val, cp->regs + REG_PCS_MII_ADVERT);
996
997                 /* enable PCS */
998                 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
999
1000                 /* pcs workaround: enable sync detect */
1001                 writel(PCS_SERDES_CTRL_SYNCD_EN,
1002                        cp->regs + REG_PCS_SERDES_CTRL);
1003         }
1004 }
1005
1006
1007 static int cas_pcs_link_check(struct cas *cp)
1008 {
1009         u32 stat, state_machine;
1010         int retval = 0;
1011
1012         /* The link status bit latches on zero, so you must
1013          * read it twice in such a case to see a transition
1014          * to the link being up.
1015          */
1016         stat = readl(cp->regs + REG_PCS_MII_STATUS);
1017         if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1018                 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1019
1020         /* The remote-fault indication is only valid
1021          * when autoneg has completed.
1022          */
1023         if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1024                      PCS_MII_STATUS_REMOTE_FAULT)) ==
1025             (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
1026                 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1027
1028         /* work around link detection issue by querying the PCS state
1029          * machine directly.
1030          */
1031         state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1032         if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1033                 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1034         } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1035                 stat |= PCS_MII_STATUS_LINK_STATUS;
1036         }
1037
1038         if (stat & PCS_MII_STATUS_LINK_STATUS) {
1039                 if (cp->lstate != link_up) {
1040                         if (cp->opened) {
1041                                 cp->lstate = link_up;
1042                                 cp->link_transition = LINK_TRANSITION_LINK_UP;
1043
1044                                 cas_set_link_modes(cp);
1045                                 netif_carrier_on(cp->dev);
1046                         }
1047                 }
1048         } else if (cp->lstate == link_up) {
1049                 cp->lstate = link_down;
1050                 if (link_transition_timeout != 0 &&
1051                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1052                     !cp->link_transition_jiffies_valid) {
1053                         /*
1054                          * force a reset, as a workaround for the
1055                          * link-failure problem. May want to move this to a
1056                          * point a bit earlier in the sequence. If we had
1057                          * generated a reset a short time ago, we'll wait for
1058                          * the link timer to check the status until a
1059                          * timer expires (link_transistion_jiffies_valid is
1060                          * true when the timer is running.)  Instead of using
1061                          * a system timer, we just do a check whenever the
1062                          * link timer is running - this clears the flag after
1063                          * a suitable delay.
1064                          */
1065                         retval = 1;
1066                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1067                         cp->link_transition_jiffies = jiffies;
1068                         cp->link_transition_jiffies_valid = 1;
1069                 } else {
1070                         cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1071                 }
1072                 netif_carrier_off(cp->dev);
1073                 if (cp->opened)
1074                         netif_info(cp, link, cp->dev, "PCS link down\n");
1075
1076                 /* Cassini only: if you force a mode, there can be
1077                  * sync problems on link down. to fix that, the following
1078                  * things need to be checked:
1079                  * 1) read serialink state register
1080                  * 2) read pcs status register to verify link down.
1081                  * 3) if link down and serial link == 0x03, then you need
1082                  *    to global reset the chip.
1083                  */
1084                 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1085                         /* should check to see if we're in a forced mode */
1086                         stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1087                         if (stat == 0x03)
1088                                 return 1;
1089                 }
1090         } else if (cp->lstate == link_down) {
1091                 if (link_transition_timeout != 0 &&
1092                     cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1093                     !cp->link_transition_jiffies_valid) {
1094                         /* force a reset, as a workaround for the
1095                          * link-failure problem.  May want to move
1096                          * this to a point a bit earlier in the
1097                          * sequence.
1098                          */
1099                         retval = 1;
1100                         cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1101                         cp->link_transition_jiffies = jiffies;
1102                         cp->link_transition_jiffies_valid = 1;
1103                 } else {
1104                         cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1105                 }
1106         }
1107
1108         return retval;
1109 }
1110
1111 static int cas_pcs_interrupt(struct net_device *dev,
1112                              struct cas *cp, u32 status)
1113 {
1114         u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1115
1116         if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1117                 return 0;
1118         return cas_pcs_link_check(cp);
1119 }
1120
1121 static int cas_txmac_interrupt(struct net_device *dev,
1122                                struct cas *cp, u32 status)
1123 {
1124         u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1125
1126         if (!txmac_stat)
1127                 return 0;
1128
1129         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1130                      "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1131
1132         /* Defer timer expiration is quite normal,
1133          * don't even log the event.
1134          */
1135         if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1136             !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1137                 return 0;
1138
1139         spin_lock(&cp->stat_lock[0]);
1140         if (txmac_stat & MAC_TX_UNDERRUN) {
1141                 netdev_err(dev, "TX MAC xmit underrun\n");
1142                 cp->net_stats[0].tx_fifo_errors++;
1143         }
1144
1145         if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1146                 netdev_err(dev, "TX MAC max packet size error\n");
1147                 cp->net_stats[0].tx_errors++;
1148         }
1149
1150         /* The rest are all cases of one of the 16-bit TX
1151          * counters expiring.
1152          */
1153         if (txmac_stat & MAC_TX_COLL_NORMAL)
1154                 cp->net_stats[0].collisions += 0x10000;
1155
1156         if (txmac_stat & MAC_TX_COLL_EXCESS) {
1157                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1158                 cp->net_stats[0].collisions += 0x10000;
1159         }
1160
1161         if (txmac_stat & MAC_TX_COLL_LATE) {
1162                 cp->net_stats[0].tx_aborted_errors += 0x10000;
1163                 cp->net_stats[0].collisions += 0x10000;
1164         }
1165         spin_unlock(&cp->stat_lock[0]);
1166
1167         /* We do not keep track of MAC_TX_COLL_FIRST and
1168          * MAC_TX_PEAK_ATTEMPTS events.
1169          */
1170         return 0;
1171 }
1172
1173 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1174 {
1175         cas_hp_inst_t *inst;
1176         u32 val;
1177         int i;
1178
1179         i = 0;
1180         while ((inst = firmware) && inst->note) {
1181                 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1182
1183                 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1184                 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1185                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1186
1187                 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1188                 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1189                 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1190                 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1191                 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1192                 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1193                 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1194                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1195
1196                 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1197                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1198                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1199                 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1200                 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1201                 ++firmware;
1202                 ++i;
1203         }
1204 }
1205
1206 static void cas_init_rx_dma(struct cas *cp)
1207 {
1208         u64 desc_dma = cp->block_dvma;
1209         u32 val;
1210         int i, size;
1211
1212         /* rx free descriptors */
1213         val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1214         val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1215         val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1216         if ((N_RX_DESC_RINGS > 1) &&
1217             (cp->cas_flags & CAS_FLAG_REG_PLUS))  /* do desc 2 */
1218                 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1219         writel(val, cp->regs + REG_RX_CFG);
1220
1221         val = (unsigned long) cp->init_rxds[0] -
1222                 (unsigned long) cp->init_block;
1223         writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1224         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1225         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1226
1227         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1228                 /* rx desc 2 is for IPSEC packets. however,
1229                  * we don't it that for that purpose.
1230                  */
1231                 val = (unsigned long) cp->init_rxds[1] -
1232                         (unsigned long) cp->init_block;
1233                 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1234                 writel((desc_dma + val) & 0xffffffff, cp->regs +
1235                        REG_PLUS_RX_DB1_LOW);
1236                 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1237                        REG_PLUS_RX_KICK1);
1238         }
1239
1240         /* rx completion registers */
1241         val = (unsigned long) cp->init_rxcs[0] -
1242                 (unsigned long) cp->init_block;
1243         writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1244         writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1245
1246         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1247                 /* rx comp 2-4 */
1248                 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1249                         val = (unsigned long) cp->init_rxcs[i] -
1250                                 (unsigned long) cp->init_block;
1251                         writel((desc_dma + val) >> 32, cp->regs +
1252                                REG_PLUS_RX_CBN_HI(i));
1253                         writel((desc_dma + val) & 0xffffffff, cp->regs +
1254                                REG_PLUS_RX_CBN_LOW(i));
1255                 }
1256         }
1257
1258         /* read selective clear regs to prevent spurious interrupts
1259          * on reset because complete == kick.
1260          * selective clear set up to prevent interrupts on resets
1261          */
1262         readl(cp->regs + REG_INTR_STATUS_ALIAS);
1263         writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1264         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1265                 for (i = 1; i < N_RX_COMP_RINGS; i++)
1266                         readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1267
1268                 /* 2 is different from 3 and 4 */
1269                 if (N_RX_COMP_RINGS > 1)
1270                         writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1271                                cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1272
1273                 for (i = 2; i < N_RX_COMP_RINGS; i++)
1274                         writel(INTR_RX_DONE_ALT,
1275                                cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1276         }
1277
1278         /* set up pause thresholds */
1279         val  = CAS_BASE(RX_PAUSE_THRESH_OFF,
1280                         cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1281         val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1282                         cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1283         writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1284
1285         /* zero out dma reassembly buffers */
1286         for (i = 0; i < 64; i++) {
1287                 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1288                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1289                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1290                 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1291         }
1292
1293         /* make sure address register is 0 for normal operation */
1294         writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1295         writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1296
1297         /* interrupt mitigation */
1298 #ifdef USE_RX_BLANK
1299         val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1300         val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1301         writel(val, cp->regs + REG_RX_BLANK);
1302 #else
1303         writel(0x0, cp->regs + REG_RX_BLANK);
1304 #endif
1305
1306         /* interrupt generation as a function of low water marks for
1307          * free desc and completion entries. these are used to trigger
1308          * housekeeping for rx descs. we don't use the free interrupt
1309          * as it's not very useful
1310          */
1311         /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1312         val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1313         writel(val, cp->regs + REG_RX_AE_THRESH);
1314         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1315                 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1316                 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1317         }
1318
1319         /* Random early detect registers. useful for congestion avoidance.
1320          * this should be tunable.
1321          */
1322         writel(0x0, cp->regs + REG_RX_RED);
1323
1324         /* receive page sizes. default == 2K (0x800) */
1325         val = 0;
1326         if (cp->page_size == 0x1000)
1327                 val = 0x1;
1328         else if (cp->page_size == 0x2000)
1329                 val = 0x2;
1330         else if (cp->page_size == 0x4000)
1331                 val = 0x3;
1332
1333         /* round mtu + offset. constrain to page size. */
1334         size = cp->dev->mtu + 64;
1335         if (size > cp->page_size)
1336                 size = cp->page_size;
1337
1338         if (size <= 0x400)
1339                 i = 0x0;
1340         else if (size <= 0x800)
1341                 i = 0x1;
1342         else if (size <= 0x1000)
1343                 i = 0x2;
1344         else
1345                 i = 0x3;
1346
1347         cp->mtu_stride = 1 << (i + 10);
1348         val  = CAS_BASE(RX_PAGE_SIZE, val);
1349         val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1350         val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1351         val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1352         writel(val, cp->regs + REG_RX_PAGE_SIZE);
1353
1354         /* enable the header parser if desired */
1355         if (CAS_HP_FIRMWARE == cas_prog_null)
1356                 return;
1357
1358         val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1359         val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1360         val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1361         writel(val, cp->regs + REG_HP_CFG);
1362 }
1363
1364 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1365 {
1366         memset(rxc, 0, sizeof(*rxc));
1367         rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1368 }
1369
1370 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1371  * flipping is protected by the fact that the chip will not
1372  * hand back the same page index while it's being processed.
1373  */
1374 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1375 {
1376         cas_page_t *page = cp->rx_pages[1][index];
1377         cas_page_t *new;
1378
1379         if (page_count(page->buffer) == 1)
1380                 return page;
1381
1382         new = cas_page_dequeue(cp);
1383         if (new) {
1384                 spin_lock(&cp->rx_inuse_lock);
1385                 list_add(&page->list, &cp->rx_inuse_list);
1386                 spin_unlock(&cp->rx_inuse_lock);
1387         }
1388         return new;
1389 }
1390
1391 /* this needs to be changed if we actually use the ENC RX DESC ring */
1392 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1393                                  const int index)
1394 {
1395         cas_page_t **page0 = cp->rx_pages[0];
1396         cas_page_t **page1 = cp->rx_pages[1];
1397
1398         /* swap if buffer is in use */
1399         if (page_count(page0[index]->buffer) > 1) {
1400                 cas_page_t *new = cas_page_spare(cp, index);
1401                 if (new) {
1402                         page1[index] = page0[index];
1403                         page0[index] = new;
1404                 }
1405         }
1406         RX_USED_SET(page0[index], 0);
1407         return page0[index];
1408 }
1409
1410 static void cas_clean_rxds(struct cas *cp)
1411 {
1412         /* only clean ring 0 as ring 1 is used for spare buffers */
1413         struct cas_rx_desc *rxd = cp->init_rxds[0];
1414         int i, size;
1415
1416         /* release all rx flows */
1417         for (i = 0; i < N_RX_FLOWS; i++) {
1418                 struct sk_buff *skb;
1419                 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1420                         cas_skb_release(skb);
1421                 }
1422         }
1423
1424         /* initialize descriptors */
1425         size = RX_DESC_RINGN_SIZE(0);
1426         for (i = 0; i < size; i++) {
1427                 cas_page_t *page = cas_page_swap(cp, 0, i);
1428                 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1429                 rxd[i].index  = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1430                                             CAS_BASE(RX_INDEX_RING, 0));
1431         }
1432
1433         cp->rx_old[0]  = RX_DESC_RINGN_SIZE(0) - 4;
1434         cp->rx_last[0] = 0;
1435         cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1436 }
1437
1438 static void cas_clean_rxcs(struct cas *cp)
1439 {
1440         int i, j;
1441
1442         /* take ownership of rx comp descriptors */
1443         memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1444         memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1445         for (i = 0; i < N_RX_COMP_RINGS; i++) {
1446                 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1447                 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1448                         cas_rxc_init(rxc + j);
1449                 }
1450         }
1451 }
1452
1453 #if 0
1454 /* When we get a RX fifo overflow, the RX unit is probably hung
1455  * so we do the following.
1456  *
1457  * If any part of the reset goes wrong, we return 1 and that causes the
1458  * whole chip to be reset.
1459  */
1460 static int cas_rxmac_reset(struct cas *cp)
1461 {
1462         struct net_device *dev = cp->dev;
1463         int limit;
1464         u32 val;
1465
1466         /* First, reset MAC RX. */
1467         writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1468         for (limit = 0; limit < STOP_TRIES; limit++) {
1469                 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1470                         break;
1471                 udelay(10);
1472         }
1473         if (limit == STOP_TRIES) {
1474                 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1475                 return 1;
1476         }
1477
1478         /* Second, disable RX DMA. */
1479         writel(0, cp->regs + REG_RX_CFG);
1480         for (limit = 0; limit < STOP_TRIES; limit++) {
1481                 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1482                         break;
1483                 udelay(10);
1484         }
1485         if (limit == STOP_TRIES) {
1486                 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1487                 return 1;
1488         }
1489
1490         mdelay(5);
1491
1492         /* Execute RX reset command. */
1493         writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1494         for (limit = 0; limit < STOP_TRIES; limit++) {
1495                 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1496                         break;
1497                 udelay(10);
1498         }
1499         if (limit == STOP_TRIES) {
1500                 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1501                 return 1;
1502         }
1503
1504         /* reset driver rx state */
1505         cas_clean_rxds(cp);
1506         cas_clean_rxcs(cp);
1507
1508         /* Now, reprogram the rest of RX unit. */
1509         cas_init_rx_dma(cp);
1510
1511         /* re-enable */
1512         val = readl(cp->regs + REG_RX_CFG);
1513         writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1514         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1515         val = readl(cp->regs + REG_MAC_RX_CFG);
1516         writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1517         return 0;
1518 }
1519 #endif
1520
1521 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1522                                u32 status)
1523 {
1524         u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1525
1526         if (!stat)
1527                 return 0;
1528
1529         netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1530
1531         /* these are all rollovers */
1532         spin_lock(&cp->stat_lock[0]);
1533         if (stat & MAC_RX_ALIGN_ERR)
1534                 cp->net_stats[0].rx_frame_errors += 0x10000;
1535
1536         if (stat & MAC_RX_CRC_ERR)
1537                 cp->net_stats[0].rx_crc_errors += 0x10000;
1538
1539         if (stat & MAC_RX_LEN_ERR)
1540                 cp->net_stats[0].rx_length_errors += 0x10000;
1541
1542         if (stat & MAC_RX_OVERFLOW) {
1543                 cp->net_stats[0].rx_over_errors++;
1544                 cp->net_stats[0].rx_fifo_errors++;
1545         }
1546
1547         /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1548          * events.
1549          */
1550         spin_unlock(&cp->stat_lock[0]);
1551         return 0;
1552 }
1553
1554 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1555                              u32 status)
1556 {
1557         u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1558
1559         if (!stat)
1560                 return 0;
1561
1562         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1563                      "mac interrupt, stat: 0x%x\n", stat);
1564
1565         /* This interrupt is just for pause frame and pause
1566          * tracking.  It is useful for diagnostics and debug
1567          * but probably by default we will mask these events.
1568          */
1569         if (stat & MAC_CTRL_PAUSE_STATE)
1570                 cp->pause_entered++;
1571
1572         if (stat & MAC_CTRL_PAUSE_RECEIVED)
1573                 cp->pause_last_time_recvd = (stat >> 16);
1574
1575         return 0;
1576 }
1577
1578
1579 /* Must be invoked under cp->lock. */
1580 static inline int cas_mdio_link_not_up(struct cas *cp)
1581 {
1582         u16 val;
1583
1584         switch (cp->lstate) {
1585         case link_force_ret:
1586                 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1587                 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1588                 cp->timer_ticks = 5;
1589                 cp->lstate = link_force_ok;
1590                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1591                 break;
1592
1593         case link_aneg:
1594                 val = cas_phy_read(cp, MII_BMCR);
1595
1596                 /* Try forced modes. we try things in the following order:
1597                  * 1000 full -> 100 full/half -> 10 half
1598                  */
1599                 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1600                 val |= BMCR_FULLDPLX;
1601                 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1602                         CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1603                 cas_phy_write(cp, MII_BMCR, val);
1604                 cp->timer_ticks = 5;
1605                 cp->lstate = link_force_try;
1606                 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1607                 break;
1608
1609         case link_force_try:
1610                 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1611                 val = cas_phy_read(cp, MII_BMCR);
1612                 cp->timer_ticks = 5;
1613                 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1614                         val &= ~CAS_BMCR_SPEED1000;
1615                         val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1616                         cas_phy_write(cp, MII_BMCR, val);
1617                         break;
1618                 }
1619
1620                 if (val & BMCR_SPEED100) {
1621                         if (val & BMCR_FULLDPLX) /* fd failed */
1622                                 val &= ~BMCR_FULLDPLX;
1623                         else { /* 100Mbps failed */
1624                                 val &= ~BMCR_SPEED100;
1625                         }
1626                         cas_phy_write(cp, MII_BMCR, val);
1627                         break;
1628                 }
1629         default:
1630                 break;
1631         }
1632         return 0;
1633 }
1634
1635
1636 /* must be invoked with cp->lock held */
1637 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1638 {
1639         int restart;
1640
1641         if (bmsr & BMSR_LSTATUS) {
1642                 /* Ok, here we got a link. If we had it due to a forced
1643                  * fallback, and we were configured for autoneg, we
1644                  * retry a short autoneg pass. If you know your hub is
1645                  * broken, use ethtool ;)
1646                  */
1647                 if ((cp->lstate == link_force_try) &&
1648                     (cp->link_cntl & BMCR_ANENABLE)) {
1649                         cp->lstate = link_force_ret;
1650                         cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1651                         cas_mif_poll(cp, 0);
1652                         cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1653                         cp->timer_ticks = 5;
1654                         if (cp->opened)
1655                                 netif_info(cp, link, cp->dev,
1656                                            "Got link after fallback, retrying autoneg once...\n");
1657                         cas_phy_write(cp, MII_BMCR,
1658                                       cp->link_fcntl | BMCR_ANENABLE |
1659                                       BMCR_ANRESTART);
1660                         cas_mif_poll(cp, 1);
1661
1662                 } else if (cp->lstate != link_up) {
1663                         cp->lstate = link_up;
1664                         cp->link_transition = LINK_TRANSITION_LINK_UP;
1665
1666                         if (cp->opened) {
1667                                 cas_set_link_modes(cp);
1668                                 netif_carrier_on(cp->dev);
1669                         }
1670                 }
1671                 return 0;
1672         }
1673
1674         /* link not up. if the link was previously up, we restart the
1675          * whole process
1676          */
1677         restart = 0;
1678         if (cp->lstate == link_up) {
1679                 cp->lstate = link_down;
1680                 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1681
1682                 netif_carrier_off(cp->dev);
1683                 if (cp->opened)
1684                         netif_info(cp, link, cp->dev, "Link down\n");
1685                 restart = 1;
1686
1687         } else if (++cp->timer_ticks > 10)
1688                 cas_mdio_link_not_up(cp);
1689
1690         return restart;
1691 }
1692
1693 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1694                              u32 status)
1695 {
1696         u32 stat = readl(cp->regs + REG_MIF_STATUS);
1697         u16 bmsr;
1698
1699         /* check for a link change */
1700         if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1701                 return 0;
1702
1703         bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1704         return cas_mii_link_check(cp, bmsr);
1705 }
1706
1707 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1708                              u32 status)
1709 {
1710         u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1711
1712         if (!stat)
1713                 return 0;
1714
1715         netdev_err(dev, "PCI error [%04x:%04x]",
1716                    stat, readl(cp->regs + REG_BIM_DIAG));
1717
1718         /* cassini+ has this reserved */
1719         if ((stat & PCI_ERR_BADACK) &&
1720             ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1721                 pr_cont(" <No ACK64# during ABS64 cycle>");
1722
1723         if (stat & PCI_ERR_DTRTO)
1724                 pr_cont(" <Delayed transaction timeout>");
1725         if (stat & PCI_ERR_OTHER)
1726                 pr_cont(" <other>");
1727         if (stat & PCI_ERR_BIM_DMA_WRITE)
1728                 pr_cont(" <BIM DMA 0 write req>");
1729         if (stat & PCI_ERR_BIM_DMA_READ)
1730                 pr_cont(" <BIM DMA 0 read req>");
1731         pr_cont("\n");
1732
1733         if (stat & PCI_ERR_OTHER) {
1734                 u16 cfg;
1735
1736                 /* Interrogate PCI config space for the
1737                  * true cause.
1738                  */
1739                 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1740                 netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
1741                 if (cfg & PCI_STATUS_PARITY)
1742                         netdev_err(dev, "PCI parity error detected\n");
1743                 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1744                         netdev_err(dev, "PCI target abort\n");
1745                 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1746                         netdev_err(dev, "PCI master acks target abort\n");
1747                 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1748                         netdev_err(dev, "PCI master abort\n");
1749                 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1750                         netdev_err(dev, "PCI system error SERR#\n");
1751                 if (cfg & PCI_STATUS_DETECTED_PARITY)
1752                         netdev_err(dev, "PCI parity error\n");
1753
1754                 /* Write the error bits back to clear them. */
1755                 cfg &= (PCI_STATUS_PARITY |
1756                         PCI_STATUS_SIG_TARGET_ABORT |
1757                         PCI_STATUS_REC_TARGET_ABORT |
1758                         PCI_STATUS_REC_MASTER_ABORT |
1759                         PCI_STATUS_SIG_SYSTEM_ERROR |
1760                         PCI_STATUS_DETECTED_PARITY);
1761                 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1762         }
1763
1764         /* For all PCI errors, we should reset the chip. */
1765         return 1;
1766 }
1767
1768 /* All non-normal interrupt conditions get serviced here.
1769  * Returns non-zero if we should just exit the interrupt
1770  * handler right now (ie. if we reset the card which invalidates
1771  * all of the other original irq status bits).
1772  */
1773 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1774                             u32 status)
1775 {
1776         if (status & INTR_RX_TAG_ERROR) {
1777                 /* corrupt RX tag framing */
1778                 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1779                              "corrupt rx tag framing\n");
1780                 spin_lock(&cp->stat_lock[0]);
1781                 cp->net_stats[0].rx_errors++;
1782                 spin_unlock(&cp->stat_lock[0]);
1783                 goto do_reset;
1784         }
1785
1786         if (status & INTR_RX_LEN_MISMATCH) {
1787                 /* length mismatch. */
1788                 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1789                              "length mismatch for rx frame\n");
1790                 spin_lock(&cp->stat_lock[0]);
1791                 cp->net_stats[0].rx_errors++;
1792                 spin_unlock(&cp->stat_lock[0]);
1793                 goto do_reset;
1794         }
1795
1796         if (status & INTR_PCS_STATUS) {
1797                 if (cas_pcs_interrupt(dev, cp, status))
1798                         goto do_reset;
1799         }
1800
1801         if (status & INTR_TX_MAC_STATUS) {
1802                 if (cas_txmac_interrupt(dev, cp, status))
1803                         goto do_reset;
1804         }
1805
1806         if (status & INTR_RX_MAC_STATUS) {
1807                 if (cas_rxmac_interrupt(dev, cp, status))
1808                         goto do_reset;
1809         }
1810
1811         if (status & INTR_MAC_CTRL_STATUS) {
1812                 if (cas_mac_interrupt(dev, cp, status))
1813                         goto do_reset;
1814         }
1815
1816         if (status & INTR_MIF_STATUS) {
1817                 if (cas_mif_interrupt(dev, cp, status))
1818                         goto do_reset;
1819         }
1820
1821         if (status & INTR_PCI_ERROR_STATUS) {
1822                 if (cas_pci_interrupt(dev, cp, status))
1823                         goto do_reset;
1824         }
1825         return 0;
1826
1827 do_reset:
1828 #if 1
1829         atomic_inc(&cp->reset_task_pending);
1830         atomic_inc(&cp->reset_task_pending_all);
1831         netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1832         schedule_work(&cp->reset_task);
1833 #else
1834         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1835         netdev_err(dev, "reset called in cas_abnormal_irq\n");
1836         schedule_work(&cp->reset_task);
1837 #endif
1838         return 1;
1839 }
1840
1841 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1842  *       determining whether to do a netif_stop/wakeup
1843  */
1844 #define CAS_TABORT(x)      (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1845 #define CAS_ROUND_PAGE(x)  (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1846 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1847                                   const int len)
1848 {
1849         unsigned long off = addr + len;
1850
1851         if (CAS_TABORT(cp) == 1)
1852                 return 0;
1853         if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1854                 return 0;
1855         return TX_TARGET_ABORT_LEN;
1856 }
1857
1858 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1859 {
1860         struct cas_tx_desc *txds;
1861         struct sk_buff **skbs;
1862         struct net_device *dev = cp->dev;
1863         int entry, count;
1864
1865         spin_lock(&cp->tx_lock[ring]);
1866         txds = cp->init_txds[ring];
1867         skbs = cp->tx_skbs[ring];
1868         entry = cp->tx_old[ring];
1869
1870         count = TX_BUFF_COUNT(ring, entry, limit);
1871         while (entry != limit) {
1872                 struct sk_buff *skb = skbs[entry];
1873                 dma_addr_t daddr;
1874                 u32 dlen;
1875                 int frag;
1876
1877                 if (!skb) {
1878                         /* this should never occur */
1879                         entry = TX_DESC_NEXT(ring, entry);
1880                         continue;
1881                 }
1882
1883                 /* however, we might get only a partial skb release. */
1884                 count -= skb_shinfo(skb)->nr_frags +
1885                         + cp->tx_tiny_use[ring][entry].nbufs + 1;
1886                 if (count < 0)
1887                         break;
1888
1889                 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1890                              "tx[%d] done, slot %d\n", ring, entry);
1891
1892                 skbs[entry] = NULL;
1893                 cp->tx_tiny_use[ring][entry].nbufs = 0;
1894
1895                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1896                         struct cas_tx_desc *txd = txds + entry;
1897
1898                         daddr = le64_to_cpu(txd->buffer);
1899                         dlen = CAS_VAL(TX_DESC_BUFLEN,
1900                                        le64_to_cpu(txd->control));
1901                         pci_unmap_page(cp->pdev, daddr, dlen,
1902                                        PCI_DMA_TODEVICE);
1903                         entry = TX_DESC_NEXT(ring, entry);
1904
1905                         /* tiny buffer may follow */
1906                         if (cp->tx_tiny_use[ring][entry].used) {
1907                                 cp->tx_tiny_use[ring][entry].used = 0;
1908                                 entry = TX_DESC_NEXT(ring, entry);
1909                         }
1910                 }
1911
1912                 spin_lock(&cp->stat_lock[ring]);
1913                 cp->net_stats[ring].tx_packets++;
1914                 cp->net_stats[ring].tx_bytes += skb->len;
1915                 spin_unlock(&cp->stat_lock[ring]);
1916                 dev_kfree_skb_irq(skb);
1917         }
1918         cp->tx_old[ring] = entry;
1919
1920         /* this is wrong for multiple tx rings. the net device needs
1921          * multiple queues for this to do the right thing.  we wait
1922          * for 2*packets to be available when using tiny buffers
1923          */
1924         if (netif_queue_stopped(dev) &&
1925             (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1926                 netif_wake_queue(dev);
1927         spin_unlock(&cp->tx_lock[ring]);
1928 }
1929
1930 static void cas_tx(struct net_device *dev, struct cas *cp,
1931                    u32 status)
1932 {
1933         int limit, ring;
1934 #ifdef USE_TX_COMPWB
1935         u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1936 #endif
1937         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1938                      "tx interrupt, status: 0x%x, %llx\n",
1939                      status, (unsigned long long)compwb);
1940         /* process all the rings */
1941         for (ring = 0; ring < N_TX_RINGS; ring++) {
1942 #ifdef USE_TX_COMPWB
1943                 /* use the completion writeback registers */
1944                 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1945                         CAS_VAL(TX_COMPWB_LSB, compwb);
1946                 compwb = TX_COMPWB_NEXT(compwb);
1947 #else
1948                 limit = readl(cp->regs + REG_TX_COMPN(ring));
1949 #endif
1950                 if (cp->tx_old[ring] != limit)
1951                         cas_tx_ringN(cp, ring, limit);
1952         }
1953 }
1954
1955
1956 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1957                               int entry, const u64 *words,
1958                               struct sk_buff **skbref)
1959 {
1960         int dlen, hlen, len, i, alloclen;
1961         int off, swivel = RX_SWIVEL_OFF_VAL;
1962         struct cas_page *page;
1963         struct sk_buff *skb;
1964         void *addr, *crcaddr;
1965         __sum16 csum;
1966         char *p;
1967
1968         hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1969         dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1970         len  = hlen + dlen;
1971
1972         if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1973                 alloclen = len;
1974         else
1975                 alloclen = max(hlen, RX_COPY_MIN);
1976
1977         skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1978         if (skb == NULL)
1979                 return -1;
1980
1981         *skbref = skb;
1982         skb_reserve(skb, swivel);
1983
1984         p = skb->data;
1985         addr = crcaddr = NULL;
1986         if (hlen) { /* always copy header pages */
1987                 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1988                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1989                 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1990                         swivel;
1991
1992                 i = hlen;
1993                 if (!dlen) /* attach FCS */
1994                         i += cp->crc_size;
1995                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1996                                     PCI_DMA_FROMDEVICE);
1997                 addr = cas_page_map(page->buffer);
1998                 memcpy(p, addr + off, i);
1999                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2000                                     PCI_DMA_FROMDEVICE);
2001                 cas_page_unmap(addr);
2002                 RX_USED_ADD(page, 0x100);
2003                 p += hlen;
2004                 swivel = 0;
2005         }
2006
2007
2008         if (alloclen < (hlen + dlen)) {
2009                 skb_frag_t *frag = skb_shinfo(skb)->frags;
2010
2011                 /* normal or jumbo packets. we use frags */
2012                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2013                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2014                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2015
2016                 hlen = min(cp->page_size - off, dlen);
2017                 if (hlen < 0) {
2018                         netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2019                                      "rx page overflow: %d\n", hlen);
2020                         dev_kfree_skb_irq(skb);
2021                         return -1;
2022                 }
2023                 i = hlen;
2024                 if (i == dlen)  /* attach FCS */
2025                         i += cp->crc_size;
2026                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2027                                     PCI_DMA_FROMDEVICE);
2028
2029                 /* make sure we always copy a header */
2030                 swivel = 0;
2031                 if (p == (char *) skb->data) { /* not split */
2032                         addr = cas_page_map(page->buffer);
2033                         memcpy(p, addr + off, RX_COPY_MIN);
2034                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2035                                         PCI_DMA_FROMDEVICE);
2036                         cas_page_unmap(addr);
2037                         off += RX_COPY_MIN;
2038                         swivel = RX_COPY_MIN;
2039                         RX_USED_ADD(page, cp->mtu_stride);
2040                 } else {
2041                         RX_USED_ADD(page, hlen);
2042                 }
2043                 skb_put(skb, alloclen);
2044
2045                 skb_shinfo(skb)->nr_frags++;
2046                 skb->data_len += hlen - swivel;
2047                 skb->truesize += hlen - swivel;
2048                 skb->len      += hlen - swivel;
2049
2050                 get_page(page->buffer);
2051                 frag->page = page->buffer;
2052                 frag->page_offset = off;
2053                 frag->size = hlen - swivel;
2054
2055                 /* any more data? */
2056                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2057                         hlen = dlen;
2058                         off = 0;
2059
2060                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2061                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2062                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2063                                             hlen + cp->crc_size,
2064                                             PCI_DMA_FROMDEVICE);
2065                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2066                                             hlen + cp->crc_size,
2067                                             PCI_DMA_FROMDEVICE);
2068
2069                         skb_shinfo(skb)->nr_frags++;
2070                         skb->data_len += hlen;
2071                         skb->len      += hlen;
2072                         frag++;
2073
2074                         get_page(page->buffer);
2075                         frag->page = page->buffer;
2076                         frag->page_offset = 0;
2077                         frag->size = hlen;
2078                         RX_USED_ADD(page, hlen + cp->crc_size);
2079                 }
2080
2081                 if (cp->crc_size) {
2082                         addr = cas_page_map(page->buffer);
2083                         crcaddr  = addr + off + hlen;
2084                 }
2085
2086         } else {
2087                 /* copying packet */
2088                 if (!dlen)
2089                         goto end_copy_pkt;
2090
2091                 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2092                 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2093                 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2094                 hlen = min(cp->page_size - off, dlen);
2095                 if (hlen < 0) {
2096                         netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2097                                      "rx page overflow: %d\n", hlen);
2098                         dev_kfree_skb_irq(skb);
2099                         return -1;
2100                 }
2101                 i = hlen;
2102                 if (i == dlen) /* attach FCS */
2103                         i += cp->crc_size;
2104                 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2105                                     PCI_DMA_FROMDEVICE);
2106                 addr = cas_page_map(page->buffer);
2107                 memcpy(p, addr + off, i);
2108                 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2109                                     PCI_DMA_FROMDEVICE);
2110                 cas_page_unmap(addr);
2111                 if (p == (char *) skb->data) /* not split */
2112                         RX_USED_ADD(page, cp->mtu_stride);
2113                 else
2114                         RX_USED_ADD(page, i);
2115
2116                 /* any more data? */
2117                 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2118                         p += hlen;
2119                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2120                         page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2121                         pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2122                                             dlen + cp->crc_size,
2123                                             PCI_DMA_FROMDEVICE);
2124                         addr = cas_page_map(page->buffer);
2125                         memcpy(p, addr, dlen + cp->crc_size);
2126                         pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2127                                             dlen + cp->crc_size,
2128                                             PCI_DMA_FROMDEVICE);
2129                         cas_page_unmap(addr);
2130                         RX_USED_ADD(page, dlen + cp->crc_size);
2131                 }
2132 end_copy_pkt:
2133                 if (cp->crc_size) {
2134                         addr    = NULL;
2135                         crcaddr = skb->data + alloclen;
2136                 }
2137                 skb_put(skb, alloclen);
2138         }
2139
2140         csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2141         if (cp->crc_size) {
2142                 /* checksum includes FCS. strip it out. */
2143                 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2144                                               csum_unfold(csum)));
2145                 if (addr)
2146                         cas_page_unmap(addr);
2147         }
2148         skb->protocol = eth_type_trans(skb, cp->dev);
2149         if (skb->protocol == htons(ETH_P_IP)) {
2150                 skb->csum = csum_unfold(~csum);
2151                 skb->ip_summed = CHECKSUM_COMPLETE;
2152         } else
2153                 skb_checksum_none_assert(skb);
2154         return len;
2155 }
2156
2157
2158 /* we can handle up to 64 rx flows at a time. we do the same thing
2159  * as nonreassm except that we batch up the buffers.
2160  * NOTE: we currently just treat each flow as a bunch of packets that
2161  *       we pass up. a better way would be to coalesce the packets
2162  *       into a jumbo packet. to do that, we need to do the following:
2163  *       1) the first packet will have a clean split between header and
2164  *          data. save both.
2165  *       2) each time the next flow packet comes in, extend the
2166  *          data length and merge the checksums.
2167  *       3) on flow release, fix up the header.
2168  *       4) make sure the higher layer doesn't care.
2169  * because packets get coalesced, we shouldn't run into fragment count
2170  * issues.
2171  */
2172 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2173                                    struct sk_buff *skb)
2174 {
2175         int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2176         struct sk_buff_head *flow = &cp->rx_flows[flowid];
2177
2178         /* this is protected at a higher layer, so no need to
2179          * do any additional locking here. stick the buffer
2180          * at the end.
2181          */
2182         __skb_queue_tail(flow, skb);
2183         if (words[0] & RX_COMP1_RELEASE_FLOW) {
2184                 while ((skb = __skb_dequeue(flow))) {
2185                         cas_skb_release(skb);
2186                 }
2187         }
2188 }
2189
2190 /* put rx descriptor back on ring. if a buffer is in use by a higher
2191  * layer, this will need to put in a replacement.
2192  */
2193 static void cas_post_page(struct cas *cp, const int ring, const int index)
2194 {
2195         cas_page_t *new;
2196         int entry;
2197
2198         entry = cp->rx_old[ring];
2199
2200         new = cas_page_swap(cp, ring, index);
2201         cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2202         cp->init_rxds[ring][entry].index  =
2203                 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2204                             CAS_BASE(RX_INDEX_RING, ring));
2205
2206         entry = RX_DESC_ENTRY(ring, entry + 1);
2207         cp->rx_old[ring] = entry;
2208
2209         if (entry % 4)
2210                 return;
2211
2212         if (ring == 0)
2213                 writel(entry, cp->regs + REG_RX_KICK);
2214         else if ((N_RX_DESC_RINGS > 1) &&
2215                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2216                 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2217 }
2218
2219
2220 /* only when things are bad */
2221 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2222 {
2223         unsigned int entry, last, count, released;
2224         int cluster;
2225         cas_page_t **page = cp->rx_pages[ring];
2226
2227         entry = cp->rx_old[ring];
2228
2229         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2230                      "rxd[%d] interrupt, done: %d\n", ring, entry);
2231
2232         cluster = -1;
2233         count = entry & 0x3;
2234         last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2235         released = 0;
2236         while (entry != last) {
2237                 /* make a new buffer if it's still in use */
2238                 if (page_count(page[entry]->buffer) > 1) {
2239                         cas_page_t *new = cas_page_dequeue(cp);
2240                         if (!new) {
2241                                 /* let the timer know that we need to
2242                                  * do this again
2243                                  */
2244                                 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2245                                 if (!timer_pending(&cp->link_timer))
2246                                         mod_timer(&cp->link_timer, jiffies +
2247                                                   CAS_LINK_FAST_TIMEOUT);
2248                                 cp->rx_old[ring]  = entry;
2249                                 cp->rx_last[ring] = num ? num - released : 0;
2250                                 return -ENOMEM;
2251                         }
2252                         spin_lock(&cp->rx_inuse_lock);
2253                         list_add(&page[entry]->list, &cp->rx_inuse_list);
2254                         spin_unlock(&cp->rx_inuse_lock);
2255                         cp->init_rxds[ring][entry].buffer =
2256                                 cpu_to_le64(new->dma_addr);
2257                         page[entry] = new;
2258
2259                 }
2260
2261                 if (++count == 4) {
2262                         cluster = entry;
2263                         count = 0;
2264                 }
2265                 released++;
2266                 entry = RX_DESC_ENTRY(ring, entry + 1);
2267         }
2268         cp->rx_old[ring] = entry;
2269
2270         if (cluster < 0)
2271                 return 0;
2272
2273         if (ring == 0)
2274                 writel(cluster, cp->regs + REG_RX_KICK);
2275         else if ((N_RX_DESC_RINGS > 1) &&
2276                  (cp->cas_flags & CAS_FLAG_REG_PLUS))
2277                 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2278         return 0;
2279 }
2280
2281
2282 /* process a completion ring. packets are set up in three basic ways:
2283  * small packets: should be copied header + data in single buffer.
2284  * large packets: header and data in a single buffer.
2285  * split packets: header in a separate buffer from data.
2286  *                data may be in multiple pages. data may be > 256
2287  *                bytes but in a single page.
2288  *
2289  * NOTE: RX page posting is done in this routine as well. while there's
2290  *       the capability of using multiple RX completion rings, it isn't
2291  *       really worthwhile due to the fact that the page posting will
2292  *       force serialization on the single descriptor ring.
2293  */
2294 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2295 {
2296         struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2297         int entry, drops;
2298         int npackets = 0;
2299
2300         netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2301                      "rx[%d] interrupt, done: %d/%d\n",
2302                      ring,
2303                      readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2304
2305         entry = cp->rx_new[ring];
2306         drops = 0;
2307         while (1) {
2308                 struct cas_rx_comp *rxc = rxcs + entry;
2309                 struct sk_buff *uninitialized_var(skb);
2310                 int type, len;
2311                 u64 words[4];
2312                 int i, dring;
2313
2314                 words[0] = le64_to_cpu(rxc->word1);
2315                 words[1] = le64_to_cpu(rxc->word2);
2316                 words[2] = le64_to_cpu(rxc->word3);
2317                 words[3] = le64_to_cpu(rxc->word4);
2318
2319                 /* don't touch if still owned by hw */
2320                 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2321                 if (type == 0)
2322                         break;
2323
2324                 /* hw hasn't cleared the zero bit yet */
2325                 if (words[3] & RX_COMP4_ZERO) {
2326                         break;
2327                 }
2328
2329                 /* get info on the packet */
2330                 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2331                         spin_lock(&cp->stat_lock[ring]);
2332                         cp->net_stats[ring].rx_errors++;
2333                         if (words[3] & RX_COMP4_LEN_MISMATCH)
2334                                 cp->net_stats[ring].rx_length_errors++;
2335                         if (words[3] & RX_COMP4_BAD)
2336                                 cp->net_stats[ring].rx_crc_errors++;
2337                         spin_unlock(&cp->stat_lock[ring]);
2338
2339                         /* We'll just return it to Cassini. */
2340                 drop_it:
2341                         spin_lock(&cp->stat_lock[ring]);
2342                         ++cp->net_stats[ring].rx_dropped;
2343                         spin_unlock(&cp->stat_lock[ring]);
2344                         goto next;
2345                 }
2346
2347                 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2348                 if (len < 0) {
2349                         ++drops;
2350                         goto drop_it;
2351                 }
2352
2353                 /* see if it's a flow re-assembly or not. the driver
2354                  * itself handles release back up.
2355                  */
2356                 if (RX_DONT_BATCH || (type == 0x2)) {
2357                         /* non-reassm: these always get released */
2358                         cas_skb_release(skb);
2359                 } else {
2360                         cas_rx_flow_pkt(cp, words, skb);
2361                 }
2362
2363                 spin_lock(&cp->stat_lock[ring]);
2364                 cp->net_stats[ring].rx_packets++;
2365                 cp->net_stats[ring].rx_bytes += len;
2366                 spin_unlock(&cp->stat_lock[ring]);
2367
2368         next:
2369                 npackets++;
2370
2371                 /* should it be released? */
2372                 if (words[0] & RX_COMP1_RELEASE_HDR) {
2373                         i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2374                         dring = CAS_VAL(RX_INDEX_RING, i);
2375                         i = CAS_VAL(RX_INDEX_NUM, i);
2376                         cas_post_page(cp, dring, i);
2377                 }
2378
2379                 if (words[0] & RX_COMP1_RELEASE_DATA) {
2380                         i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2381                         dring = CAS_VAL(RX_INDEX_RING, i);
2382                         i = CAS_VAL(RX_INDEX_NUM, i);
2383                         cas_post_page(cp, dring, i);
2384                 }
2385
2386                 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2387                         i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2388                         dring = CAS_VAL(RX_INDEX_RING, i);
2389                         i = CAS_VAL(RX_INDEX_NUM, i);
2390                         cas_post_page(cp, dring, i);
2391                 }
2392
2393                 /* skip to the next entry */
2394                 entry = RX_COMP_ENTRY(ring, entry + 1 +
2395                                       CAS_VAL(RX_COMP1_SKIP, words[0]));
2396 #ifdef USE_NAPI
2397                 if (budget && (npackets >= budget))
2398                         break;
2399 #endif
2400         }
2401         cp->rx_new[ring] = entry;
2402
2403         if (drops)
2404                 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2405         return npackets;
2406 }
2407
2408
2409 /* put completion entries back on the ring */
2410 static void cas_post_rxcs_ringN(struct net_device *dev,
2411                                 struct cas *cp, int ring)
2412 {
2413         struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2414         int last, entry;
2415
2416         last = cp->rx_cur[ring];
2417         entry = cp->rx_new[ring];
2418         netif_printk(cp, intr, KERN_DEBUG, dev,
2419                      "rxc[%d] interrupt, done: %d/%d\n",
2420                      ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2421
2422         /* zero and re-mark descriptors */
2423         while (last != entry) {
2424                 cas_rxc_init(rxc + last);
2425                 last = RX_COMP_ENTRY(ring, last + 1);
2426         }
2427         cp->rx_cur[ring] = last;
2428
2429         if (ring == 0)
2430                 writel(last, cp->regs + REG_RX_COMP_TAIL);
2431         else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2432                 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2433 }
2434
2435
2436
2437 /* cassini can use all four PCI interrupts for the completion ring.
2438  * rings 3 and 4 are identical
2439  */
2440 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2441 static inline void cas_handle_irqN(struct net_device *dev,
2442                                    struct cas *cp, const u32 status,
2443                                    const int ring)
2444 {
2445         if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2446                 cas_post_rxcs_ringN(dev, cp, ring);
2447 }
2448
2449 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2450 {
2451         struct net_device *dev = dev_id;
2452         struct cas *cp = netdev_priv(dev);
2453         unsigned long flags;
2454         int ring;
2455         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2456
2457         /* check for shared irq */
2458         if (status == 0)
2459                 return IRQ_NONE;
2460
2461         ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2462         spin_lock_irqsave(&cp->lock, flags);
2463         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2464 #ifdef USE_NAPI
2465                 cas_mask_intr(cp);
2466                 napi_schedule(&cp->napi);
2467 #else
2468                 cas_rx_ringN(cp, ring, 0);
2469 #endif
2470                 status &= ~INTR_RX_DONE_ALT;
2471         }
2472
2473         if (status)
2474                 cas_handle_irqN(dev, cp, status, ring);
2475         spin_unlock_irqrestore(&cp->lock, flags);
2476         return IRQ_HANDLED;
2477 }
2478 #endif
2479
2480 #ifdef USE_PCI_INTB
2481 /* everything but rx packets */
2482 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2483 {
2484         if (status & INTR_RX_BUF_UNAVAIL_1) {
2485                 /* Frame arrived, no free RX buffers available.
2486                  * NOTE: we can get this on a link transition. */
2487                 cas_post_rxds_ringN(cp, 1, 0);
2488                 spin_lock(&cp->stat_lock[1]);
2489                 cp->net_stats[1].rx_dropped++;
2490                 spin_unlock(&cp->stat_lock[1]);
2491         }
2492
2493         if (status & INTR_RX_BUF_AE_1)
2494                 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2495                                     RX_AE_FREEN_VAL(1));
2496
2497         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2498                 cas_post_rxcs_ringN(cp, 1);
2499 }
2500
2501 /* ring 2 handles a few more events than 3 and 4 */
2502 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2503 {
2504         struct net_device *dev = dev_id;
2505         struct cas *cp = netdev_priv(dev);
2506         unsigned long flags;
2507         u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2508
2509         /* check for shared interrupt */
2510         if (status == 0)
2511                 return IRQ_NONE;
2512
2513         spin_lock_irqsave(&cp->lock, flags);
2514         if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2515 #ifdef USE_NAPI
2516                 cas_mask_intr(cp);
2517                 napi_schedule(&cp->napi);
2518 #else
2519                 cas_rx_ringN(cp, 1, 0);
2520 #endif
2521                 status &= ~INTR_RX_DONE_ALT;
2522         }
2523         if (status)
2524                 cas_handle_irq1(cp, status);
2525         spin_unlock_irqrestore(&cp->lock, flags);
2526         return IRQ_HANDLED;
2527 }
2528 #endif
2529
2530 static inline void cas_handle_irq(struct net_device *dev,
2531                                   struct cas *cp, const u32 status)
2532 {
2533         /* housekeeping interrupts */
2534         if (status & INTR_ERROR_MASK)
2535                 cas_abnormal_irq(dev, cp, status);
2536
2537         if (status & INTR_RX_BUF_UNAVAIL) {
2538                 /* Frame arrived, no free RX buffers available.
2539                  * NOTE: we can get this on a link transition.
2540                  */
2541                 cas_post_rxds_ringN(cp, 0, 0);
2542                 spin_lock(&cp->stat_lock[0]);
2543                 cp->net_stats[0].rx_dropped++;
2544                 spin_unlock(&cp->stat_lock[0]);
2545         } else if (status & INTR_RX_BUF_AE) {
2546                 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2547                                     RX_AE_FREEN_VAL(0));
2548         }
2549
2550         if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2551                 cas_post_rxcs_ringN(dev, cp, 0);
2552 }
2553
2554 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2555 {
2556         struct net_device *dev = dev_id;
2557         struct cas *cp = netdev_priv(dev);
2558         unsigned long flags;
2559         u32 status = readl(cp->regs + REG_INTR_STATUS);
2560
2561         if (status == 0)
2562                 return IRQ_NONE;
2563
2564         spin_lock_irqsave(&cp->lock, flags);
2565         if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2566                 cas_tx(dev, cp, status);
2567                 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2568         }
2569
2570         if (status & INTR_RX_DONE) {
2571 #ifdef USE_NAPI
2572                 cas_mask_intr(cp);
2573                 napi_schedule(&cp->napi);
2574 #else
2575                 cas_rx_ringN(cp, 0, 0);
2576 #endif
2577                 status &= ~INTR_RX_DONE;
2578         }
2579
2580         if (status)
2581                 cas_handle_irq(dev, cp, status);
2582         spin_unlock_irqrestore(&cp->lock, flags);
2583         return IRQ_HANDLED;
2584 }
2585
2586
2587 #ifdef USE_NAPI
2588 static int cas_poll(struct napi_struct *napi, int budget)
2589 {
2590         struct cas *cp = container_of(napi, struct cas, napi);
2591         struct net_device *dev = cp->dev;
2592         int i, enable_intr, credits;
2593         u32 status = readl(cp->regs + REG_INTR_STATUS);
2594         unsigned long flags;
2595
2596         spin_lock_irqsave(&cp->lock, flags);
2597         cas_tx(dev, cp, status);
2598         spin_unlock_irqrestore(&cp->lock, flags);
2599
2600         /* NAPI rx packets. we spread the credits across all of the
2601          * rxc rings
2602          *
2603          * to make sure we're fair with the work we loop through each
2604          * ring N_RX_COMP_RING times with a request of
2605          * budget / N_RX_COMP_RINGS
2606          */
2607         enable_intr = 1;
2608         credits = 0;
2609         for (i = 0; i < N_RX_COMP_RINGS; i++) {
2610                 int j;
2611                 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2612                         credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2613                         if (credits >= budget) {
2614                                 enable_intr = 0;
2615                                 goto rx_comp;
2616                         }
2617                 }
2618         }
2619
2620 rx_comp:
2621         /* final rx completion */
2622         spin_lock_irqsave(&cp->lock, flags);
2623         if (status)
2624                 cas_handle_irq(dev, cp, status);
2625
2626 #ifdef USE_PCI_INTB
2627         if (N_RX_COMP_RINGS > 1) {
2628                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2629                 if (status)
2630                         cas_handle_irq1(dev, cp, status);
2631         }
2632 #endif
2633
2634 #ifdef USE_PCI_INTC
2635         if (N_RX_COMP_RINGS > 2) {
2636                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2637                 if (status)
2638                         cas_handle_irqN(dev, cp, status, 2);
2639         }
2640 #endif
2641
2642 #ifdef USE_PCI_INTD
2643         if (N_RX_COMP_RINGS > 3) {
2644                 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2645                 if (status)
2646                         cas_handle_irqN(dev, cp, status, 3);
2647         }
2648 #endif
2649         spin_unlock_irqrestore(&cp->lock, flags);
2650         if (enable_intr) {
2651                 napi_complete(napi);
2652                 cas_unmask_intr(cp);
2653         }
2654         return credits;
2655 }
2656 #endif
2657
2658 #ifdef CONFIG_NET_POLL_CONTROLLER
2659 static void cas_netpoll(struct net_device *dev)
2660 {
2661         struct cas *cp = netdev_priv(dev);
2662
2663         cas_disable_irq(cp, 0);
2664         cas_interrupt(cp->pdev->irq, dev);
2665         cas_enable_irq(cp, 0);
2666
2667 #ifdef USE_PCI_INTB
2668         if (N_RX_COMP_RINGS > 1) {
2669                 /* cas_interrupt1(); */
2670         }
2671 #endif
2672 #ifdef USE_PCI_INTC
2673         if (N_RX_COMP_RINGS > 2) {
2674                 /* cas_interruptN(); */
2675         }
2676 #endif
2677 #ifdef USE_PCI_INTD
2678         if (N_RX_COMP_RINGS > 3) {
2679                 /* cas_interruptN(); */
2680         }
2681 #endif
2682 }
2683 #endif
2684
2685 static void cas_tx_timeout(struct net_device *dev)
2686 {
2687         struct cas *cp = netdev_priv(dev);
2688
2689         netdev_err(dev, "transmit timed out, resetting\n");
2690         if (!cp->hw_running) {
2691                 netdev_err(dev, "hrm.. hw not running!\n");
2692                 return;
2693         }
2694
2695         netdev_err(dev, "MIF_STATE[%08x]\n",
2696                    readl(cp->regs + REG_MIF_STATE_MACHINE));
2697
2698         netdev_err(dev, "MAC_STATE[%08x]\n",
2699                    readl(cp->regs + REG_MAC_STATE_MACHINE));
2700
2701         netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2702                    readl(cp->regs + REG_TX_CFG),
2703                    readl(cp->regs + REG_MAC_TX_STATUS),
2704                    readl(cp->regs + REG_MAC_TX_CFG),
2705                    readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2706                    readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2707                    readl(cp->regs + REG_TX_FIFO_READ_PTR),
2708                    readl(cp->regs + REG_TX_SM_1),
2709                    readl(cp->regs + REG_TX_SM_2));
2710
2711         netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2712                    readl(cp->regs + REG_RX_CFG),
2713                    readl(cp->regs + REG_MAC_RX_STATUS),
2714                    readl(cp->regs + REG_MAC_RX_CFG));
2715
2716         netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2717                    readl(cp->regs + REG_HP_STATE_MACHINE),
2718                    readl(cp->regs + REG_HP_STATUS0),
2719                    readl(cp->regs + REG_HP_STATUS1),
2720                    readl(cp->regs + REG_HP_STATUS2));
2721
2722 #if 1
2723         atomic_inc(&cp->reset_task_pending);
2724         atomic_inc(&cp->reset_task_pending_all);
2725         schedule_work(&cp->reset_task);
2726 #else
2727         atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2728         schedule_work(&cp->reset_task);
2729 #endif
2730 }
2731
2732 static inline int cas_intme(int ring, int entry)
2733 {
2734         /* Algorithm: IRQ every 1/2 of descriptors. */
2735         if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2736                 return 1;
2737         return 0;
2738 }
2739
2740
2741 static void cas_write_txd(struct cas *cp, int ring, int entry,
2742                           dma_addr_t mapping, int len, u64 ctrl, int last)
2743 {
2744         struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2745
2746         ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2747         if (cas_intme(ring, entry))
2748                 ctrl |= TX_DESC_INTME;
2749         if (last)
2750                 ctrl |= TX_DESC_EOF;
2751         txd->control = cpu_to_le64(ctrl);
2752         txd->buffer = cpu_to_le64(mapping);
2753 }
2754
2755 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2756                                 const int entry)
2757 {
2758         return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2759 }
2760
2761 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2762                                      const int entry, const int tentry)
2763 {
2764         cp->tx_tiny_use[ring][tentry].nbufs++;
2765         cp->tx_tiny_use[ring][entry].used = 1;
2766         return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2767 }
2768
2769 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2770                                     struct sk_buff *skb)
2771 {
2772         struct net_device *dev = cp->dev;
2773         int entry, nr_frags, frag, tabort, tentry;
2774         dma_addr_t mapping;
2775         unsigned long flags;
2776         u64 ctrl;
2777         u32 len;
2778
2779         spin_lock_irqsave(&cp->tx_lock[ring], flags);
2780
2781         /* This is a hard error, log it. */
2782         if (TX_BUFFS_AVAIL(cp, ring) <=
2783             CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2784                 netif_stop_queue(dev);
2785                 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2786                 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2787                 return 1;
2788         }
2789
2790         ctrl = 0;
2791         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2792                 const u64 csum_start_off = skb_checksum_start_offset(skb);
2793                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2794
2795                 ctrl =  TX_DESC_CSUM_EN |
2796                         CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2797                         CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2798         }
2799
2800         entry = cp->tx_new[ring];
2801         cp->tx_skbs[ring][entry] = skb;
2802
2803         nr_frags = skb_shinfo(skb)->nr_frags;
2804         len = skb_headlen(skb);
2805         mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2806                                offset_in_page(skb->data), len,
2807                                PCI_DMA_TODEVICE);
2808
2809         tentry = entry;
2810         tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2811         if (unlikely(tabort)) {
2812                 /* NOTE: len is always >  tabort */
2813                 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2814                               ctrl | TX_DESC_SOF, 0);
2815                 entry = TX_DESC_NEXT(ring, entry);
2816
2817                 skb_copy_from_linear_data_offset(skb, len - tabort,
2818                               tx_tiny_buf(cp, ring, entry), tabort);
2819                 mapping = tx_tiny_map(cp, ring, entry, tentry);
2820                 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2821                               (nr_frags == 0));
2822         } else {
2823                 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2824                               TX_DESC_SOF, (nr_frags == 0));
2825         }
2826         entry = TX_DESC_NEXT(ring, entry);
2827
2828         for (frag = 0; frag < nr_frags; frag++) {
2829                 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2830
2831                 len = fragp->size;
2832                 mapping = pci_map_page(cp->pdev, fragp->page,
2833                                        fragp->page_offset, len,
2834                                        PCI_DMA_TODEVICE);
2835
2836                 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2837                 if (unlikely(tabort)) {
2838                         void *addr;
2839
2840                         /* NOTE: len is always > tabort */
2841                         cas_write_txd(cp, ring, entry, mapping, len - tabort,
2842                                       ctrl, 0);
2843                         entry = TX_DESC_NEXT(ring, entry);
2844
2845                         addr = cas_page_map(fragp->page);
2846                         memcpy(tx_tiny_buf(cp, ring, entry),
2847                                addr + fragp->page_offset + len - tabort,
2848                                tabort);
2849                         cas_page_unmap(addr);
2850                         mapping = tx_tiny_map(cp, ring, entry, tentry);
2851                         len     = tabort;
2852                 }
2853
2854                 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2855                               (frag + 1 == nr_frags));
2856                 entry = TX_DESC_NEXT(ring, entry);
2857         }
2858
2859         cp->tx_new[ring] = entry;
2860         if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2861                 netif_stop_queue(dev);
2862
2863         netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2864                      "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2865                      ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2866         writel(entry, cp->regs + REG_TX_KICKN(ring));
2867         spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2868         return 0;
2869 }
2870
2871 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2872 {
2873         struct cas *cp = netdev_priv(dev);
2874
2875         /* this is only used as a load-balancing hint, so it doesn't
2876          * need to be SMP safe
2877          */
2878         static int ring;
2879
2880         if (skb_padto(skb, cp->min_frame_size))
2881                 return NETDEV_TX_OK;
2882
2883         /* XXX: we need some higher-level QoS hooks to steer packets to
2884          *      individual queues.
2885          */
2886         if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2887                 return NETDEV_TX_BUSY;
2888         return NETDEV_TX_OK;
2889 }
2890
2891 static void cas_init_tx_dma(struct cas *cp)
2892 {
2893         u64 desc_dma = cp->block_dvma;
2894         unsigned long off;
2895         u32 val;
2896         int i;
2897
2898         /* set up tx completion writeback registers. must be 8-byte aligned */
2899 #ifdef USE_TX_COMPWB
2900         off = offsetof(struct cas_init_block, tx_compwb);
2901         writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2902         writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2903 #endif
2904
2905         /* enable completion writebacks, enable paced mode,
2906          * disable read pipe, and disable pre-interrupt compwbs
2907          */
2908         val =   TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2909                 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2910                 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2911                 TX_CFG_INTR_COMPWB_DIS;
2912
2913         /* write out tx ring info and tx desc bases */
2914         for (i = 0; i < MAX_TX_RINGS; i++) {
2915                 off = (unsigned long) cp->init_txds[i] -
2916                         (unsigned long) cp->init_block;
2917
2918                 val |= CAS_TX_RINGN_BASE(i);
2919                 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2920                 writel((desc_dma + off) & 0xffffffff, cp->regs +
2921                        REG_TX_DBN_LOW(i));
2922                 /* don't zero out the kick register here as the system
2923                  * will wedge
2924                  */
2925         }
2926         writel(val, cp->regs + REG_TX_CFG);
2927
2928         /* program max burst sizes. these numbers should be different
2929          * if doing QoS.
2930          */
2931 #ifdef USE_QOS
2932         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2933         writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2934         writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2935         writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2936 #else
2937         writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2938         writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2939         writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2940         writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2941 #endif
2942 }
2943
2944 /* Must be invoked under cp->lock. */
2945 static inline void cas_init_dma(struct cas *cp)
2946 {
2947         cas_init_tx_dma(cp);
2948         cas_init_rx_dma(cp);
2949 }
2950
2951 static void cas_process_mc_list(struct cas *cp)
2952 {
2953         u16 hash_table[16];
2954         u32 crc;
2955         struct netdev_hw_addr *ha;
2956         int i = 1;
2957
2958         memset(hash_table, 0, sizeof(hash_table));
2959         netdev_for_each_mc_addr(ha, cp->dev) {
2960                 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2961                         /* use the alternate mac address registers for the
2962                          * first 15 multicast addresses
2963                          */
2964                         writel((ha->addr[4] << 8) | ha->addr[5],
2965                                cp->regs + REG_MAC_ADDRN(i*3 + 0));
2966                         writel((ha->addr[2] << 8) | ha->addr[3],
2967                                cp->regs + REG_MAC_ADDRN(i*3 + 1));
2968                         writel((ha->addr[0] << 8) | ha->addr[1],
2969                                cp->regs + REG_MAC_ADDRN(i*3 + 2));
2970                         i++;
2971                 }
2972                 else {
2973                         /* use hw hash table for the next series of
2974                          * multicast addresses
2975                          */
2976                         crc = ether_crc_le(ETH_ALEN, ha->addr);
2977                         crc >>= 24;
2978                         hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2979                 }
2980         }
2981         for (i = 0; i < 16; i++)
2982                 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2983 }
2984
2985 /* Must be invoked under cp->lock. */
2986 static u32 cas_setup_multicast(struct cas *cp)
2987 {
2988         u32 rxcfg = 0;
2989         int i;
2990
2991         if (cp->dev->flags & IFF_PROMISC) {
2992                 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2993
2994         } else if (cp->dev->flags & IFF_ALLMULTI) {
2995                 for (i=0; i < 16; i++)
2996                         writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2997                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2998
2999         } else {
3000                 cas_process_mc_list(cp);
3001                 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3002         }
3003
3004         return rxcfg;
3005 }
3006
3007 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3008 static void cas_clear_mac_err(struct cas *cp)
3009 {
3010         writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3011         writel(0, cp->regs + REG_MAC_COLL_FIRST);
3012         writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3013         writel(0, cp->regs + REG_MAC_COLL_LATE);
3014         writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3015         writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3016         writel(0, cp->regs + REG_MAC_RECV_FRAME);
3017         writel(0, cp->regs + REG_MAC_LEN_ERR);
3018         writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3019         writel(0, cp->regs + REG_MAC_FCS_ERR);
3020         writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3021 }
3022
3023
3024 static void cas_mac_reset(struct cas *cp)
3025 {
3026         int i;
3027
3028         /* do both TX and RX reset */
3029         writel(0x1, cp->regs + REG_MAC_TX_RESET);
3030         writel(0x1, cp->regs + REG_MAC_RX_RESET);
3031
3032         /* wait for TX */
3033         i = STOP_TRIES;
3034         while (i-- > 0) {
3035                 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3036                         break;
3037                 udelay(10);
3038         }
3039
3040         /* wait for RX */
3041         i = STOP_TRIES;
3042         while (i-- > 0) {
3043                 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3044                         break;
3045                 udelay(10);
3046         }
3047
3048         if (readl(cp->regs + REG_MAC_TX_RESET) |
3049             readl(cp->regs + REG_MAC_RX_RESET))
3050                 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3051                            readl(cp->regs + REG_MAC_TX_RESET),
3052                            readl(cp->regs + REG_MAC_RX_RESET),
3053                            readl(cp->regs + REG_MAC_STATE_MACHINE));
3054 }
3055
3056
3057 /* Must be invoked under cp->lock. */
3058 static void cas_init_mac(struct cas *cp)
3059 {
3060         unsigned char *e = &cp->dev->dev_addr[0];
3061         int i;
3062         cas_mac_reset(cp);
3063
3064         /* setup core arbitration weight register */
3065         writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3066
3067         /* XXX Use pci_dma_burst_advice() */
3068 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3069         /* set the infinite burst register for chips that don't have
3070          * pci issues.
3071          */
3072         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3073                 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3074 #endif
3075
3076         writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3077
3078         writel(0x00, cp->regs + REG_MAC_IPG0);
3079         writel(0x08, cp->regs + REG_MAC_IPG1);
3080         writel(0x04, cp->regs + REG_MAC_IPG2);
3081
3082         /* change later for 802.3z */
3083         writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3084
3085         /* min frame + FCS */
3086         writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3087
3088         /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3089          * specify the maximum frame size to prevent RX tag errors on
3090          * oversized frames.
3091          */
3092         writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3093                CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3094                         (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3095                cp->regs + REG_MAC_FRAMESIZE_MAX);
3096
3097         /* NOTE: crc_size is used as a surrogate for half-duplex.
3098          * workaround saturn half-duplex issue by increasing preamble
3099          * size to 65 bytes.
3100          */
3101         if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3102                 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3103         else
3104                 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3105         writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3106         writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3107         writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3108
3109         writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3110
3111         writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3112         writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3113         writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3114         writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3115         writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3116
3117         /* setup mac address in perfect filter array */
3118         for (i = 0; i < 45; i++)
3119                 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3120
3121         writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3122         writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3123         writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3124
3125         writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3126         writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3127         writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3128
3129         cp->mac_rx_cfg = cas_setup_multicast(cp);
3130
3131         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3132         cas_clear_mac_err(cp);
3133         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3134
3135         /* Setup MAC interrupts.  We want to get all of the interesting
3136          * counter expiration events, but we do not want to hear about
3137          * normal rx/tx as the DMA engine tells us that.
3138          */
3139         writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3140         writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3141
3142         /* Don't enable even the PAUSE interrupts for now, we
3143          * make no use of those events other than to record them.
3144          */
3145         writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3146 }
3147
3148 /* Must be invoked under cp->lock. */
3149 static void cas_init_pause_thresholds(struct cas *cp)
3150 {
3151         /* Calculate pause thresholds.  Setting the OFF threshold to the
3152          * full RX fifo size effectively disables PAUSE generation
3153          */
3154         if (cp->rx_fifo_size <= (2 * 1024)) {
3155                 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3156         } else {
3157                 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3158                 if (max_frame * 3 > cp->rx_fifo_size) {
3159                         cp->rx_pause_off = 7104;
3160                         cp->rx_pause_on  = 960;
3161                 } else {
3162                         int off = (cp->rx_fifo_size - (max_frame * 2));
3163                         int on = off - max_frame;
3164                         cp->rx_pause_off = off;
3165                         cp->rx_pause_on = on;
3166                 }
3167         }
3168 }
3169
3170 static int cas_vpd_match(const void __iomem *p, const char *str)
3171 {
3172         int len = strlen(str) + 1;
3173         int i;
3174
3175         for (i = 0; i < len; i++) {
3176                 if (readb(p + i) != str[i])
3177                         return 0;
3178         }
3179         return 1;
3180 }
3181
3182
3183 /* get the mac address by reading the vpd information in the rom.
3184  * also get the phy type and determine if there's an entropy generator.
3185  * NOTE: this is a bit convoluted for the following reasons:
3186  *  1) vpd info has order-dependent mac addresses for multinic cards
3187  *  2) the only way to determine the nic order is to use the slot
3188  *     number.
3189  *  3) fiber cards don't have bridges, so their slot numbers don't
3190  *     mean anything.
3191  *  4) we don't actually know we have a fiber card until after
3192  *     the mac addresses are parsed.
3193  */
3194 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3195                             const int offset)
3196 {
3197         void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3198         void __iomem *base, *kstart;
3199         int i, len;
3200         int found = 0;
3201 #define VPD_FOUND_MAC        0x01
3202 #define VPD_FOUND_PHY        0x02
3203
3204         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3205         int mac_off  = 0;
3206
3207 #if defined(CONFIG_SPARC)
3208         const unsigned char *addr;
3209 #endif
3210
3211         /* give us access to the PROM */
3212         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3213                cp->regs + REG_BIM_LOCAL_DEV_EN);
3214
3215         /* check for an expansion rom */
3216         if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3217                 goto use_random_mac_addr;
3218
3219         /* search for beginning of vpd */
3220         base = NULL;
3221         for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3222                 /* check for PCIR */
3223                 if ((readb(p + i + 0) == 0x50) &&
3224                     (readb(p + i + 1) == 0x43) &&
3225                     (readb(p + i + 2) == 0x49) &&
3226                     (readb(p + i + 3) == 0x52)) {
3227                         base = p + (readb(p + i + 8) |
3228                                     (readb(p + i + 9) << 8));
3229                         break;
3230                 }
3231         }
3232
3233         if (!base || (readb(base) != 0x82))
3234                 goto use_random_mac_addr;
3235
3236         i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3237         while (i < EXPANSION_ROM_SIZE) {
3238                 if (readb(base + i) != 0x90) /* no vpd found */
3239                         goto use_random_mac_addr;
3240
3241                 /* found a vpd field */
3242                 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3243
3244                 /* extract keywords */
3245                 kstart = base + i + 3;
3246                 p = kstart;
3247                 while ((p - kstart) < len) {
3248                         int klen = readb(p + 2);
3249                         int j;
3250                         char type;
3251
3252                         p += 3;
3253
3254                         /* look for the following things:
3255                          * -- correct length == 29
3256                          * 3 (type) + 2 (size) +
3257                          * 18 (strlen("local-mac-address") + 1) +
3258                          * 6 (mac addr)
3259                          * -- VPD Instance 'I'
3260                          * -- VPD Type Bytes 'B'
3261                          * -- VPD data length == 6
3262                          * -- property string == local-mac-address
3263                          *
3264                          * -- correct length == 24
3265                          * 3 (type) + 2 (size) +
3266                          * 12 (strlen("entropy-dev") + 1) +
3267                          * 7 (strlen("vms110") + 1)
3268                          * -- VPD Instance 'I'
3269                          * -- VPD Type String 'B'
3270                          * -- VPD data length == 7
3271                          * -- property string == entropy-dev
3272                          *
3273                          * -- correct length == 18
3274                          * 3 (type) + 2 (size) +
3275                          * 9 (strlen("phy-type") + 1) +
3276                          * 4 (strlen("pcs") + 1)
3277                          * -- VPD Instance 'I'
3278                          * -- VPD Type String 'S'
3279                          * -- VPD data length == 4
3280                          * -- property string == phy-type
3281                          *
3282                          * -- correct length == 23
3283                          * 3 (type) + 2 (size) +
3284                          * 14 (strlen("phy-interface") + 1) +
3285                          * 4 (strlen("pcs") + 1)
3286                          * -- VPD Instance 'I'
3287                          * -- VPD Type String 'S'
3288                          * -- VPD data length == 4
3289                          * -- property string == phy-interface
3290                          */
3291                         if (readb(p) != 'I')
3292                                 goto next;
3293
3294                         /* finally, check string and length */
3295                         type = readb(p + 3);
3296                         if (type == 'B') {
3297                                 if ((klen == 29) && readb(p + 4) == 6 &&
3298                                     cas_vpd_match(p + 5,
3299                                                   "local-mac-address")) {
3300                                         if (mac_off++ > offset)
3301                                                 goto next;
3302
3303                                         /* set mac address */
3304                                         for (j = 0; j < 6; j++)
3305                                                 dev_addr[j] =
3306                                                         readb(p + 23 + j);
3307                                         goto found_mac;
3308                                 }
3309                         }
3310
3311                         if (type != 'S')
3312                                 goto next;
3313
3314 #ifdef USE_ENTROPY_DEV
3315                         if ((klen == 24) &&
3316                             cas_vpd_match(p + 5, "entropy-dev") &&
3317                             cas_vpd_match(p + 17, "vms110")) {
3318                                 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3319                                 goto next;
3320                         }
3321 #endif
3322
3323                         if (found & VPD_FOUND_PHY)
3324                                 goto next;
3325
3326                         if ((klen == 18) && readb(p + 4) == 4 &&
3327                             cas_vpd_match(p + 5, "phy-type")) {
3328                                 if (cas_vpd_match(p + 14, "pcs")) {
3329                                         phy_type = CAS_PHY_SERDES;
3330                                         goto found_phy;
3331                                 }
3332                         }
3333
3334                         if ((klen == 23) && readb(p + 4) == 4 &&
3335                             cas_vpd_match(p + 5, "phy-interface")) {
3336                                 if (cas_vpd_match(p + 19, "pcs")) {
3337                                         phy_type = CAS_PHY_SERDES;
3338                                         goto found_phy;
3339                                 }
3340                         }
3341 found_mac:
3342                         found |= VPD_FOUND_MAC;
3343                         goto next;
3344
3345 found_phy:
3346                         found |= VPD_FOUND_PHY;
3347
3348 next:
3349                         p += klen;
3350                 }
3351                 i += len + 3;
3352         }
3353
3354 use_random_mac_addr:
3355         if (found & VPD_FOUND_MAC)
3356                 goto done;
3357
3358 #if defined(CONFIG_SPARC)
3359         addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3360         if (addr != NULL) {
3361                 memcpy(dev_addr, addr, 6);
3362                 goto done;
3363         }
3364 #endif
3365
3366         /* Sun MAC prefix then 3 random bytes. */
3367         pr_info("MAC address not found in ROM VPD\n");
3368         dev_addr[0] = 0x08;
3369         dev_addr[1] = 0x00;
3370         dev_addr[2] = 0x20;
3371         get_random_bytes(dev_addr + 3, 3);
3372
3373 done:
3374         writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3375         return phy_type;
3376 }
3377
3378 /* check pci invariants */
3379 static void cas_check_pci_invariants(struct cas *cp)
3380 {
3381         struct pci_dev *pdev = cp->pdev;
3382
3383         cp->cas_flags = 0;
3384         if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3385             (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3386                 if (pdev->revision >= CAS_ID_REVPLUS)
3387                         cp->cas_flags |= CAS_FLAG_REG_PLUS;
3388                 if (pdev->revision < CAS_ID_REVPLUS02u)
3389                         cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3390
3391                 /* Original Cassini supports HW CSUM, but it's not
3392                  * enabled by default as it can trigger TX hangs.
3393                  */
3394                 if (pdev->revision < CAS_ID_REV2)
3395                         cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3396         } else {
3397                 /* Only sun has original cassini chips.  */
3398                 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3399
3400                 /* We use a flag because the same phy might be externally
3401                  * connected.
3402                  */
3403                 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3404                     (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3405                         cp->cas_flags |= CAS_FLAG_SATURN;
3406         }
3407 }
3408
3409
3410 static int cas_check_invariants(struct cas *cp)
3411 {
3412         struct pci_dev *pdev = cp->pdev;
3413         u32 cfg;
3414         int i;
3415
3416         /* get page size for rx buffers. */
3417         cp->page_order = 0;
3418 #ifdef USE_PAGE_ORDER
3419         if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3420                 /* see if we can allocate larger pages */
3421                 struct page *page = alloc_pages(GFP_ATOMIC,
3422                                                 CAS_JUMBO_PAGE_SHIFT -
3423                                                 PAGE_SHIFT);
3424                 if (page) {
3425                         __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3426                         cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3427                 } else {
3428                         printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3429                 }
3430         }
3431 #endif
3432         cp->page_size = (PAGE_SIZE << cp->page_order);
3433
3434         /* Fetch the FIFO configurations. */
3435         cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3436         cp->rx_fifo_size = RX_FIFO_SIZE;
3437
3438         /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3439          * they're both connected.
3440          */
3441         cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3442                                         PCI_SLOT(pdev->devfn));
3443         if (cp->phy_type & CAS_PHY_SERDES) {
3444                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3445                 return 0; /* no more checking needed */
3446         }
3447
3448         /* MII */
3449         cfg = readl(cp->regs + REG_MIF_CFG);
3450         if (cfg & MIF_CFG_MDIO_1) {
3451                 cp->phy_type = CAS_PHY_MII_MDIO1;
3452         } else if (cfg & MIF_CFG_MDIO_0) {
3453                 cp->phy_type = CAS_PHY_MII_MDIO0;
3454         }
3455
3456         cas_mif_poll(cp, 0);
3457         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3458
3459         for (i = 0; i < 32; i++) {
3460                 u32 phy_id;
3461                 int j;
3462
3463                 for (j = 0; j < 3; j++) {
3464                         cp->phy_addr = i;
3465                         phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3466                         phy_id |= cas_phy_read(cp, MII_PHYSID2);
3467                         if (phy_id && (phy_id != 0xFFFFFFFF)) {
3468                                 cp->phy_id = phy_id;
3469                                 goto done;
3470                         }
3471                 }
3472         }
3473         pr_err("MII phy did not respond [%08x]\n",
3474                readl(cp->regs + REG_MIF_STATE_MACHINE));
3475         return -1;
3476
3477 done:
3478         /* see if we can do gigabit */
3479         cfg = cas_phy_read(cp, MII_BMSR);
3480         if ((cfg & CAS_BMSR_1000_EXTEND) &&
3481             cas_phy_read(cp, CAS_MII_1000_EXTEND))
3482                 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3483         return 0;
3484 }
3485
3486 /* Must be invoked under cp->lock. */
3487 static inline void cas_start_dma(struct cas *cp)
3488 {
3489         int i;
3490         u32 val;
3491         int txfailed = 0;
3492
3493         /* enable dma */
3494         val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3495         writel(val, cp->regs + REG_TX_CFG);
3496         val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3497         writel(val, cp->regs + REG_RX_CFG);
3498
3499         /* enable the mac */
3500         val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3501         writel(val, cp->regs + REG_MAC_TX_CFG);
3502         val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3503         writel(val, cp->regs + REG_MAC_RX_CFG);
3504
3505         i = STOP_TRIES;
3506         while (i-- > 0) {
3507                 val = readl(cp->regs + REG_MAC_TX_CFG);
3508                 if ((val & MAC_TX_CFG_EN))
3509                         break;
3510                 udelay(10);
3511         }
3512         if (i < 0) txfailed = 1;
3513         i = STOP_TRIES;
3514         while (i-- > 0) {
3515                 val = readl(cp->regs + REG_MAC_RX_CFG);
3516                 if ((val & MAC_RX_CFG_EN)) {
3517                         if (txfailed) {
3518                                 netdev_err(cp->dev,
3519                                            "enabling mac failed [tx:%08x:%08x]\n",
3520                                            readl(cp->regs + REG_MIF_STATE_MACHINE),
3521                                            readl(cp->regs + REG_MAC_STATE_MACHINE));
3522                         }
3523                         goto enable_rx_done;
3524                 }
3525                 udelay(10);
3526         }
3527         netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3528                    (txfailed ? "tx,rx" : "rx"),
3529                    readl(cp->regs + REG_MIF_STATE_MACHINE),
3530                    readl(cp->regs + REG_MAC_STATE_MACHINE));
3531
3532 enable_rx_done:
3533         cas_unmask_intr(cp); /* enable interrupts */
3534         writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3535         writel(0, cp->regs + REG_RX_COMP_TAIL);
3536
3537         if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3538                 if (N_RX_DESC_RINGS > 1)
3539                         writel(RX_DESC_RINGN_SIZE(1) - 4,
3540                                cp->regs + REG_PLUS_RX_KICK1);
3541
3542                 for (i = 1; i < N_RX_COMP_RINGS; i++)
3543                         writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3544         }
3545 }
3546
3547 /* Must be invoked under cp->lock. */
3548 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3549                                    int *pause)
3550 {
3551         u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3552         *fd     = (val & PCS_MII_LPA_FD) ? 1 : 0;
3553         *pause  = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3554         if (val & PCS_MII_LPA_ASYM_PAUSE)
3555                 *pause |= 0x10;
3556         *spd = 1000;
3557 }
3558
3559 /* Must be invoked under cp->lock. */
3560 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3561                                    int *pause)
3562 {
3563         u32 val;
3564
3565         *fd = 0;
3566         *spd = 10;
3567         *pause = 0;
3568
3569         /* use GMII registers */
3570         val = cas_phy_read(cp, MII_LPA);
3571         if (val & CAS_LPA_PAUSE)
3572                 *pause = 0x01;
3573
3574         if (val & CAS_LPA_ASYM_PAUSE)
3575                 *pause |= 0x10;
3576
3577         if (val & LPA_DUPLEX)
3578                 *fd = 1;
3579         if (val & LPA_100)
3580                 *spd = 100;
3581
3582         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3583                 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3584                 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3585                         *spd = 1000;
3586                 if (val & CAS_LPA_1000FULL)
3587                         *fd = 1;
3588         }
3589 }
3590
3591 /* A link-up condition has occurred, initialize and enable the
3592  * rest of the chip.
3593  *
3594  * Must be invoked under cp->lock.
3595  */
3596 static void cas_set_link_modes(struct cas *cp)
3597 {
3598         u32 val;
3599         int full_duplex, speed, pause;
3600
3601         full_duplex = 0;
3602         speed = 10;
3603         pause = 0;
3604
3605         if (CAS_PHY_MII(cp->phy_type)) {
3606                 cas_mif_poll(cp, 0);
3607                 val = cas_phy_read(cp, MII_BMCR);
3608                 if (val & BMCR_ANENABLE) {
3609                         cas_read_mii_link_mode(cp, &full_duplex, &speed,
3610                                                &pause);
3611                 } else {
3612                         if (val & BMCR_FULLDPLX)
3613                                 full_duplex = 1;
3614
3615                         if (val & BMCR_SPEED100)
3616                                 speed = 100;
3617                         else if (val & CAS_BMCR_SPEED1000)
3618                                 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3619                                         1000 : 100;
3620                 }
3621                 cas_mif_poll(cp, 1);
3622
3623         } else {
3624                 val = readl(cp->regs + REG_PCS_MII_CTRL);
3625                 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3626                 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3627                         if (val & PCS_MII_CTRL_DUPLEX)
3628                                 full_duplex = 1;
3629                 }
3630         }
3631
3632         netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3633                    speed, full_duplex ? "full" : "half");
3634
3635         val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3636         if (CAS_PHY_MII(cp->phy_type)) {
3637                 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3638                 if (!full_duplex)
3639                         val |= MAC_XIF_DISABLE_ECHO;
3640         }
3641         if (full_duplex)
3642                 val |= MAC_XIF_FDPLX_LED;
3643         if (speed == 1000)
3644                 val |= MAC_XIF_GMII_MODE;
3645         writel(val, cp->regs + REG_MAC_XIF_CFG);
3646
3647         /* deal with carrier and collision detect. */
3648         val = MAC_TX_CFG_IPG_EN;
3649         if (full_duplex) {
3650                 val |= MAC_TX_CFG_IGNORE_CARRIER;
3651                 val |= MAC_TX_CFG_IGNORE_COLL;
3652         } else {
3653 #ifndef USE_CSMA_CD_PROTO
3654                 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3655                 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3656 #endif
3657         }
3658         /* val now set up for REG_MAC_TX_CFG */
3659
3660         /* If gigabit and half-duplex, enable carrier extension
3661          * mode.  increase slot time to 512 bytes as well.
3662          * else, disable it and make sure slot time is 64 bytes.
3663          * also activate checksum bug workaround
3664          */
3665         if ((speed == 1000) && !full_duplex) {
3666                 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3667                        cp->regs + REG_MAC_TX_CFG);
3668
3669                 val = readl(cp->regs + REG_MAC_RX_CFG);
3670                 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3671                 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3672                        cp->regs + REG_MAC_RX_CFG);
3673
3674                 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3675
3676                 cp->crc_size = 4;
3677                 /* minimum size gigabit frame at half duplex */
3678                 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3679
3680         } else {
3681                 writel(val, cp->regs + REG_MAC_TX_CFG);
3682
3683                 /* checksum bug workaround. don't strip FCS when in
3684                  * half-duplex mode
3685                  */
3686                 val = readl(cp->regs + REG_MAC_RX_CFG);
3687                 if (full_duplex) {
3688                         val |= MAC_RX_CFG_STRIP_FCS;
3689                         cp->crc_size = 0;
3690                         cp->min_frame_size = CAS_MIN_MTU;
3691                 } else {
3692                         val &= ~MAC_RX_CFG_STRIP_FCS;
3693                         cp->crc_size = 4;
3694                         cp->min_frame_size = CAS_MIN_FRAME;
3695                 }
3696                 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3697                        cp->regs + REG_MAC_RX_CFG);
3698                 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3699         }
3700
3701         if (netif_msg_link(cp)) {
3702                 if (pause & 0x01) {
3703                         netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3704                                     cp->rx_fifo_size,
3705                                     cp->rx_pause_off,
3706                                     cp->rx_pause_on);
3707                 } else if (pause & 0x10) {
3708                         netdev_info(cp->dev, "TX pause enabled\n");
3709                 } else {
3710                         netdev_info(cp->dev, "Pause is disabled\n");
3711                 }
3712         }
3713
3714         val = readl(cp->regs + REG_MAC_CTRL_CFG);
3715         val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3716         if (pause) { /* symmetric or asymmetric pause */
3717                 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3718                 if (pause & 0x01) { /* symmetric pause */
3719                         val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3720                 }
3721         }
3722         writel(val, cp->regs + REG_MAC_CTRL_CFG);
3723         cas_start_dma(cp);
3724 }
3725
3726 /* Must be invoked under cp->lock. */
3727 static void cas_init_hw(struct cas *cp, int restart_link)
3728 {
3729         if (restart_link)
3730                 cas_phy_init(cp);
3731
3732         cas_init_pause_thresholds(cp);
3733         cas_init_mac(cp);
3734         cas_init_dma(cp);
3735
3736         if (restart_link) {
3737                 /* Default aneg parameters */
3738                 cp->timer_ticks = 0;
3739                 cas_begin_auto_negotiation(cp, NULL);
3740         } else if (cp->lstate == link_up) {
3741                 cas_set_link_modes(cp);
3742                 netif_carrier_on(cp->dev);
3743         }
3744 }
3745
3746 /* Must be invoked under cp->lock. on earlier cassini boards,
3747  * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3748  * let it settle out, and then restore pci state.
3749  */
3750 static void cas_hard_reset(struct cas *cp)
3751 {
3752         writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3753         udelay(20);
3754         pci_restore_state(cp->pdev);
3755 }
3756
3757
3758 static void cas_global_reset(struct cas *cp, int blkflag)
3759 {
3760         int limit;
3761
3762         /* issue a global reset. don't use RSTOUT. */
3763         if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3764                 /* For PCS, when the blkflag is set, we should set the
3765                  * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3766                  * the last autonegotiation from being cleared.  We'll
3767                  * need some special handling if the chip is set into a
3768                  * loopback mode.
3769                  */
3770                 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3771                        cp->regs + REG_SW_RESET);
3772         } else {
3773                 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3774         }
3775
3776         /* need to wait at least 3ms before polling register */
3777         mdelay(3);
3778
3779         limit = STOP_TRIES;
3780         while (limit-- > 0) {
3781                 u32 val = readl(cp->regs + REG_SW_RESET);
3782                 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3783                         goto done;
3784                 udelay(10);
3785         }
3786         netdev_err(cp->dev, "sw reset failed\n");
3787
3788 done:
3789         /* enable various BIM interrupts */
3790         writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3791                BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3792
3793         /* clear out pci error status mask for handled errors.
3794          * we don't deal with DMA counter overflows as they happen
3795          * all the time.
3796          */
3797         writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3798                                PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3799                                PCI_ERR_BIM_DMA_READ), cp->regs +
3800                REG_PCI_ERR_STATUS_MASK);
3801
3802         /* set up for MII by default to address mac rx reset timeout
3803          * issue
3804          */
3805         writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3806 }
3807
3808 static void cas_reset(struct cas *cp, int blkflag)
3809 {
3810         u32 val;
3811
3812         cas_mask_intr(cp);
3813         cas_global_reset(cp, blkflag);
3814         cas_mac_reset(cp);
3815         cas_entropy_reset(cp);
3816
3817         /* disable dma engines. */
3818         val = readl(cp->regs + REG_TX_CFG);
3819         val &= ~TX_CFG_DMA_EN;
3820         writel(val, cp->regs + REG_TX_CFG);
3821
3822         val = readl(cp->regs + REG_RX_CFG);
3823         val &= ~RX_CFG_DMA_EN;
3824         writel(val, cp->regs + REG_RX_CFG);
3825
3826         /* program header parser */
3827         if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3828             (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3829                 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3830         } else {
3831                 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3832         }
3833
3834         /* clear out error registers */
3835         spin_lock(&cp->stat_lock[N_TX_RINGS]);
3836         cas_clear_mac_err(cp);
3837         spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3838 }
3839
3840 /* Shut down the chip, must be called with pm_mutex held.  */
3841 static void cas_shutdown(struct cas *cp)
3842 {
3843         unsigned long flags;
3844
3845         /* Make us not-running to avoid timers respawning */
3846         cp->hw_running = 0;
3847
3848         del_timer_sync(&cp->link_timer);
3849
3850         /* Stop the reset task */
3851 #if 0
3852         while (atomic_read(&cp->reset_task_pending_mtu) ||
3853                atomic_read(&cp->reset_task_pending_spare) ||
3854                atomic_read(&cp->reset_task_pending_all))
3855                 schedule();
3856
3857 #else
3858         while (atomic_read(&cp->reset_task_pending))
3859                 schedule();
3860 #endif
3861         /* Actually stop the chip */
3862         cas_lock_all_save(cp, flags);
3863         cas_reset(cp, 0);
3864         if (cp->cas_flags & CAS_FLAG_SATURN)
3865                 cas_phy_powerdown(cp);
3866         cas_unlock_all_restore(cp, flags);
3867 }
3868
3869 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3870 {
3871         struct cas *cp = netdev_priv(dev);
3872
3873         if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3874                 return -EINVAL;
3875
3876         dev->mtu = new_mtu;
3877         if (!netif_running(dev) || !netif_device_present(dev))
3878                 return 0;
3879
3880         /* let the reset task handle it */
3881 #if 1
3882         atomic_inc(&cp->reset_task_pending);
3883         if ((cp->phy_type & CAS_PHY_SERDES)) {
3884                 atomic_inc(&cp->reset_task_pending_all);
3885         } else {
3886                 atomic_inc(&cp->reset_task_pending_mtu);
3887         }
3888         schedule_work(&cp->reset_task);
3889 #else
3890         atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3891                    CAS_RESET_ALL : CAS_RESET_MTU);
3892         pr_err("reset called in cas_change_mtu\n");
3893         schedule_work(&cp->reset_task);
3894 #endif
3895
3896         flush_work_sync(&cp->reset_task);
3897         return 0;
3898 }
3899
3900 static void cas_clean_txd(struct cas *cp, int ring)
3901 {
3902         struct cas_tx_desc *txd = cp->init_txds[ring];
3903         struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3904         u64 daddr, dlen;
3905         int i, size;
3906
3907         size = TX_DESC_RINGN_SIZE(ring);
3908         for (i = 0; i < size; i++) {
3909                 int frag;
3910
3911                 if (skbs[i] == NULL)
3912                         continue;
3913
3914                 skb = skbs[i];
3915                 skbs[i] = NULL;
3916
3917                 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags;  frag++) {
3918                         int ent = i & (size - 1);
3919
3920                         /* first buffer is never a tiny buffer and so
3921                          * needs to be unmapped.
3922                          */
3923                         daddr = le64_to_cpu(txd[ent].buffer);
3924                         dlen  =  CAS_VAL(TX_DESC_BUFLEN,
3925                                          le64_to_cpu(txd[ent].control));
3926                         pci_unmap_page(cp->pdev, daddr, dlen,
3927                                        PCI_DMA_TODEVICE);
3928
3929                         if (frag != skb_shinfo(skb)->nr_frags) {
3930                                 i++;
3931
3932                                 /* next buffer might by a tiny buffer.
3933                                  * skip past it.
3934                                  */
3935                                 ent = i & (size - 1);
3936                                 if (cp->tx_tiny_use[ring][ent].used)
3937                                         i++;
3938                         }
3939                 }
3940                 dev_kfree_skb_any(skb);
3941         }
3942
3943         /* zero out tiny buf usage */
3944         memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3945 }
3946
3947 /* freed on close */
3948 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3949 {
3950         cas_page_t **page = cp->rx_pages[ring];
3951         int i, size;
3952
3953         size = RX_DESC_RINGN_SIZE(ring);
3954         for (i = 0; i < size; i++) {
3955                 if (page[i]) {
3956                         cas_page_free(cp, page[i]);
3957                         page[i] = NULL;
3958                 }
3959         }
3960 }
3961
3962 static void cas_free_rxds(struct cas *cp)
3963 {
3964         int i;
3965
3966         for (i = 0; i < N_RX_DESC_RINGS; i++)
3967                 cas_free_rx_desc(cp, i);
3968 }
3969
3970 /* Must be invoked under cp->lock. */
3971 static void cas_clean_rings(struct cas *cp)
3972 {
3973         int i;
3974
3975         /* need to clean all tx rings */
3976         memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3977         memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3978         for (i = 0; i < N_TX_RINGS; i++)
3979                 cas_clean_txd(cp, i);
3980
3981         /* zero out init block */
3982         memset(cp->init_block, 0, sizeof(struct cas_init_block));
3983         cas_clean_rxds(cp);
3984         cas_clean_rxcs(cp);
3985 }
3986
3987 /* allocated on open */
3988 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3989 {
3990         cas_page_t **page = cp->rx_pages[ring];
3991         int size, i = 0;
3992
3993         size = RX_DESC_RINGN_SIZE(ring);
3994         for (i = 0; i < size; i++) {
3995                 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
3996                         return -1;
3997         }
3998         return 0;
3999 }
4000
4001 static int cas_alloc_rxds(struct cas *cp)
4002 {
4003         int i;
4004
4005         for (i = 0; i < N_RX_DESC_RINGS; i++) {
4006                 if (cas_alloc_rx_desc(cp, i) < 0) {
4007                         cas_free_rxds(cp);
4008                         return -1;
4009                 }
4010         }
4011         return 0;
4012 }
4013
4014 static void cas_reset_task(struct work_struct *work)
4015 {
4016         struct cas *cp = container_of(work, struct cas, reset_task);
4017 #if 0
4018         int pending = atomic_read(&cp->reset_task_pending);
4019 #else
4020         int pending_all = atomic_read(&cp->reset_task_pending_all);
4021         int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4022         int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4023
4024         if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4025                 /* We can have more tasks scheduled than actually
4026                  * needed.
4027                  */
4028                 atomic_dec(&cp->reset_task_pending);
4029                 return;
4030         }
4031 #endif
4032         /* The link went down, we reset the ring, but keep
4033          * DMA stopped. Use this function for reset
4034          * on error as well.
4035          */
4036         if (cp->hw_running) {
4037                 unsigned long flags;
4038
4039                 /* Make sure we don't get interrupts or tx packets */
4040                 netif_device_detach(cp->dev);
4041                 cas_lock_all_save(cp, flags);
4042
4043                 if (cp->opened) {
4044                         /* We call cas_spare_recover when we call cas_open.
4045                          * but we do not initialize the lists cas_spare_recover
4046                          * uses until cas_open is called.
4047                          */
4048                         cas_spare_recover(cp, GFP_ATOMIC);
4049                 }
4050 #if 1
4051                 /* test => only pending_spare set */
4052                 if (!pending_all && !pending_mtu)
4053                         goto done;
4054 #else
4055                 if (pending == CAS_RESET_SPARE)
4056                         goto done;
4057 #endif
4058                 /* when pending == CAS_RESET_ALL, the following
4059                  * call to cas_init_hw will restart auto negotiation.
4060                  * Setting the second argument of cas_reset to
4061                  * !(pending == CAS_RESET_ALL) will set this argument
4062                  * to 1 (avoiding reinitializing the PHY for the normal
4063                  * PCS case) when auto negotiation is not restarted.
4064                  */
4065 #if 1
4066                 cas_reset(cp, !(pending_all > 0));
4067                 if (cp->opened)
4068                         cas_clean_rings(cp);
4069                 cas_init_hw(cp, (pending_all > 0));
4070 #else
4071                 cas_reset(cp, !(pending == CAS_RESET_ALL));
4072                 if (cp->opened)
4073                         cas_clean_rings(cp);
4074                 cas_init_hw(cp, pending == CAS_RESET_ALL);
4075 #endif
4076
4077 done:
4078                 cas_unlock_all_restore(cp, flags);
4079                 netif_device_attach(cp->dev);
4080         }
4081 #if 1
4082         atomic_sub(pending_all, &cp->reset_task_pending_all);
4083         atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4084         atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4085         atomic_dec(&cp->reset_task_pending);
4086 #else
4087         atomic_set(&cp->reset_task_pending, 0);
4088 #endif
4089 }
4090
4091 static void cas_link_timer(unsigned long data)
4092 {
4093         struct cas *cp = (struct cas *) data;
4094         int mask, pending = 0, reset = 0;
4095         unsigned long flags;
4096
4097         if (link_transition_timeout != 0 &&
4098             cp->link_transition_jiffies_valid &&
4099             ((jiffies - cp->link_transition_jiffies) >
4100               (link_transition_timeout))) {
4101                 /* One-second counter so link-down workaround doesn't
4102                  * cause resets to occur so fast as to fool the switch
4103                  * into thinking the link is down.
4104                  */
4105                 cp->link_transition_jiffies_valid = 0;
4106         }
4107
4108         if (!cp->hw_running)
4109                 return;
4110
4111         spin_lock_irqsave(&cp->lock, flags);
4112         cas_lock_tx(cp);
4113         cas_entropy_gather(cp);
4114
4115         /* If the link task is still pending, we just
4116          * reschedule the link timer
4117          */
4118 #if 1
4119         if (atomic_read(&cp->reset_task_pending_all) ||
4120             atomic_read(&cp->reset_task_pending_spare) ||
4121             atomic_read(&cp->reset_task_pending_mtu))
4122                 goto done;
4123 #else
4124         if (atomic_read(&cp->reset_task_pending))
4125                 goto done;
4126 #endif
4127
4128         /* check for rx cleaning */
4129         if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4130                 int i, rmask;
4131
4132                 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4133                         rmask = CAS_FLAG_RXD_POST(i);
4134                         if ((mask & rmask) == 0)
4135                                 continue;
4136
4137                         /* post_rxds will do a mod_timer */
4138                         if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4139                                 pending = 1;
4140                                 continue;
4141                         }
4142                         cp->cas_flags &= ~rmask;
4143                 }
4144         }
4145
4146         if (CAS_PHY_MII(cp->phy_type)) {
4147                 u16 bmsr;
4148                 cas_mif_poll(cp, 0);
4149                 bmsr = cas_phy_read(cp, MII_BMSR);
4150                 /* WTZ: Solaris driver reads this twice, but that
4151                  * may be due to the PCS case and the use of a
4152                  * common implementation. Read it twice here to be
4153                  * safe.
4154                  */
4155                 bmsr = cas_phy_read(cp, MII_BMSR);
4156                 cas_mif_poll(cp, 1);
4157                 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4158                 reset = cas_mii_link_check(cp, bmsr);
4159         } else {
4160                 reset = cas_pcs_link_check(cp);
4161         }
4162
4163         if (reset)
4164                 goto done;
4165
4166         /* check for tx state machine confusion */
4167         if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4168                 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4169                 u32 wptr, rptr;
4170                 int tlm  = CAS_VAL(MAC_SM_TLM, val);
4171
4172                 if (((tlm == 0x5) || (tlm == 0x3)) &&
4173                     (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4174                         netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4175                                      "tx err: MAC_STATE[%08x]\n", val);
4176                         reset = 1;
4177                         goto done;
4178                 }
4179
4180                 val  = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4181                 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4182                 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4183                 if ((val == 0) && (wptr != rptr)) {
4184                         netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4185                                      "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4186                                      val, wptr, rptr);
4187                         reset = 1;
4188                 }
4189
4190                 if (reset)
4191                         cas_hard_reset(cp);
4192         }
4193
4194 done:
4195         if (reset) {
4196 #if 1
4197                 atomic_inc(&cp->reset_task_pending);
4198                 atomic_inc(&cp->reset_task_pending_all);
4199                 schedule_work(&cp->reset_task);
4200 #else
4201                 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4202                 pr_err("reset called in cas_link_timer\n");
4203                 schedule_work(&cp->reset_task);
4204 #endif
4205         }
4206
4207         if (!pending)
4208                 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4209         cas_unlock_tx(cp);
4210         spin_unlock_irqrestore(&cp->lock, flags);
4211 }
4212
4213 /* tiny buffers are used to avoid target abort issues with
4214  * older cassini's
4215  */
4216 static void cas_tx_tiny_free(struct cas *cp)
4217 {
4218         struct pci_dev *pdev = cp->pdev;
4219         int i;
4220
4221         for (i = 0; i < N_TX_RINGS; i++) {
4222                 if (!cp->tx_tiny_bufs[i])
4223                         continue;
4224
4225                 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4226                                     cp->tx_tiny_bufs[i],
4227                                     cp->tx_tiny_dvma[i]);
4228                 cp->tx_tiny_bufs[i] = NULL;
4229         }
4230 }
4231
4232 static int cas_tx_tiny_alloc(struct cas *cp)
4233 {
4234         struct pci_dev *pdev = cp->pdev;
4235         int i;
4236
4237         for (i = 0; i < N_TX_RINGS; i++) {
4238                 cp->tx_tiny_bufs[i] =
4239                         pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4240                                              &cp->tx_tiny_dvma[i]);
4241                 if (!cp->tx_tiny_bufs[i]) {
4242                         cas_tx_tiny_free(cp);
4243                         return -1;
4244                 }
4245         }
4246         return 0;
4247 }
4248
4249
4250 static int cas_open(struct net_device *dev)
4251 {
4252         struct cas *cp = netdev_priv(dev);
4253         int hw_was_up, err;
4254         unsigned long flags;
4255
4256         mutex_lock(&cp->pm_mutex);
4257
4258         hw_was_up = cp->hw_running;
4259
4260         /* The power-management mutex protects the hw_running
4261          * etc. state so it is safe to do this bit without cp->lock
4262          */
4263         if (!cp->hw_running) {
4264                 /* Reset the chip */
4265                 cas_lock_all_save(cp, flags);
4266                 /* We set the second arg to cas_reset to zero
4267                  * because cas_init_hw below will have its second
4268                  * argument set to non-zero, which will force
4269                  * autonegotiation to start.
4270                  */
4271                 cas_reset(cp, 0);
4272                 cp->hw_running = 1;
4273                 cas_unlock_all_restore(cp, flags);
4274         }
4275
4276         err = -ENOMEM;
4277         if (cas_tx_tiny_alloc(cp) < 0)
4278                 goto err_unlock;
4279
4280         /* alloc rx descriptors */
4281         if (cas_alloc_rxds(cp) < 0)
4282                 goto err_tx_tiny;
4283
4284         /* allocate spares */
4285         cas_spare_init(cp);
4286         cas_spare_recover(cp, GFP_KERNEL);
4287
4288         /* We can now request the interrupt as we know it's masked
4289          * on the controller. cassini+ has up to 4 interrupts
4290          * that can be used, but you need to do explicit pci interrupt
4291          * mapping to expose them
4292          */
4293         if (request_irq(cp->pdev->irq, cas_interrupt,
4294                         IRQF_SHARED, dev->name, (void *) dev)) {
4295                 netdev_err(cp->dev, "failed to request irq !\n");
4296                 err = -EAGAIN;
4297                 goto err_spare;
4298         }
4299
4300 #ifdef USE_NAPI
4301         napi_enable(&cp->napi);
4302 #endif
4303         /* init hw */
4304         cas_lock_all_save(cp, flags);
4305         cas_clean_rings(cp);
4306         cas_init_hw(cp, !hw_was_up);
4307         cp->opened = 1;
4308         cas_unlock_all_restore(cp, flags);
4309
4310         netif_start_queue(dev);
4311         mutex_unlock(&cp->pm_mutex);
4312         return 0;
4313
4314 err_spare:
4315         cas_spare_free(cp);
4316         cas_free_rxds(cp);
4317 err_tx_tiny:
4318         cas_tx_tiny_free(cp);
4319 err_unlock:
4320         mutex_unlock(&cp->pm_mutex);
4321         return err;
4322 }
4323
4324 static int cas_close(struct net_device *dev)
4325 {
4326         unsigned long flags;
4327         struct cas *cp = netdev_priv(dev);
4328
4329 #ifdef USE_NAPI
4330         napi_disable(&cp->napi);
4331 #endif
4332         /* Make sure we don't get distracted by suspend/resume */
4333         mutex_lock(&cp->pm_mutex);
4334
4335         netif_stop_queue(dev);
4336
4337         /* Stop traffic, mark us closed */
4338         cas_lock_all_save(cp, flags);
4339         cp->opened = 0;
4340         cas_reset(cp, 0);
4341         cas_phy_init(cp);
4342         cas_begin_auto_negotiation(cp, NULL);
4343         cas_clean_rings(cp);
4344         cas_unlock_all_restore(cp, flags);
4345
4346         free_irq(cp->pdev->irq, (void *) dev);
4347         cas_spare_free(cp);
4348         cas_free_rxds(cp);
4349         cas_tx_tiny_free(cp);
4350         mutex_unlock(&cp->pm_mutex);
4351         return 0;
4352 }
4353
4354 static struct {
4355         const char name[ETH_GSTRING_LEN];
4356 } ethtool_cassini_statnames[] = {
4357         {"collisions"},
4358         {"rx_bytes"},
4359         {"rx_crc_errors"},
4360         {"rx_dropped"},
4361         {"rx_errors"},
4362         {"rx_fifo_errors"},
4363         {"rx_frame_errors"},
4364         {"rx_length_errors"},
4365         {"rx_over_errors"},
4366         {"rx_packets"},
4367         {"tx_aborted_errors"},
4368         {"tx_bytes"},
4369         {"tx_dropped"},
4370         {"tx_errors"},
4371         {"tx_fifo_errors"},
4372         {"tx_packets"}
4373 };
4374 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4375
4376 static struct {
4377         const int offsets;      /* neg. values for 2nd arg to cas_read_phy */
4378 } ethtool_register_table[] = {
4379         {-MII_BMSR},
4380         {-MII_BMCR},
4381         {REG_CAWR},
4382         {REG_INF_BURST},
4383         {REG_BIM_CFG},
4384         {REG_RX_CFG},
4385         {REG_HP_CFG},
4386         {REG_MAC_TX_CFG},
4387         {REG_MAC_RX_CFG},
4388         {REG_MAC_CTRL_CFG},
4389         {REG_MAC_XIF_CFG},
4390         {REG_MIF_CFG},
4391         {REG_PCS_CFG},
4392         {REG_SATURN_PCFG},
4393         {REG_PCS_MII_STATUS},
4394         {REG_PCS_STATE_MACHINE},
4395         {REG_MAC_COLL_EXCESS},
4396         {REG_MAC_COLL_LATE}
4397 };
4398 #define CAS_REG_LEN     ARRAY_SIZE(ethtool_register_table)
4399 #define CAS_MAX_REGS    (sizeof (u32)*CAS_REG_LEN)
4400
4401 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4402 {
4403         u8 *p;
4404         int i;
4405         unsigned long flags;
4406
4407         spin_lock_irqsave(&cp->lock, flags);
4408         for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4409                 u16 hval;
4410                 u32 val;
4411                 if (ethtool_register_table[i].offsets < 0) {
4412                         hval = cas_phy_read(cp,
4413                                     -ethtool_register_table[i].offsets);
4414                         val = hval;
4415                 } else {
4416                         val= readl(cp->regs+ethtool_register_table[i].offsets);
4417                 }
4418                 memcpy(p, (u8 *)&val, sizeof(u32));
4419         }
4420         spin_unlock_irqrestore(&cp->lock, flags);
4421 }
4422
4423 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4424 {
4425         struct cas *cp = netdev_priv(dev);
4426         struct net_device_stats *stats = cp->net_stats;
4427         unsigned long flags;
4428         int i;
4429         unsigned long tmp;
4430
4431         /* we collate all of the stats into net_stats[N_TX_RING] */
4432         if (!cp->hw_running)
4433                 return stats + N_TX_RINGS;
4434
4435         /* collect outstanding stats */
4436         /* WTZ: the Cassini spec gives these as 16 bit counters but
4437          * stored in 32-bit words.  Added a mask of 0xffff to be safe,
4438          * in case the chip somehow puts any garbage in the other bits.
4439          * Also, counter usage didn't seem to mach what Adrian did
4440          * in the parts of the code that set these quantities. Made
4441          * that consistent.
4442          */
4443         spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4444         stats[N_TX_RINGS].rx_crc_errors +=
4445           readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4446         stats[N_TX_RINGS].rx_frame_errors +=
4447                 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4448         stats[N_TX_RINGS].rx_length_errors +=
4449                 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4450 #if 1
4451         tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4452                 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4453         stats[N_TX_RINGS].tx_aborted_errors += tmp;
4454         stats[N_TX_RINGS].collisions +=
4455           tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4456 #else
4457         stats[N_TX_RINGS].tx_aborted_errors +=
4458                 readl(cp->regs + REG_MAC_COLL_EXCESS);
4459         stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4460                 readl(cp->regs + REG_MAC_COLL_LATE);
4461 #endif
4462         cas_clear_mac_err(cp);
4463
4464         /* saved bits that are unique to ring 0 */
4465         spin_lock(&cp->stat_lock[0]);
4466         stats[N_TX_RINGS].collisions        += stats[0].collisions;
4467         stats[N_TX_RINGS].rx_over_errors    += stats[0].rx_over_errors;
4468         stats[N_TX_RINGS].rx_frame_errors   += stats[0].rx_frame_errors;
4469         stats[N_TX_RINGS].rx_fifo_errors    += stats[0].rx_fifo_errors;
4470         stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4471         stats[N_TX_RINGS].tx_fifo_errors    += stats[0].tx_fifo_errors;
4472         spin_unlock(&cp->stat_lock[0]);
4473
4474         for (i = 0; i < N_TX_RINGS; i++) {
4475                 spin_lock(&cp->stat_lock[i]);
4476                 stats[N_TX_RINGS].rx_length_errors +=
4477                         stats[i].rx_length_errors;
4478                 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4479                 stats[N_TX_RINGS].rx_packets    += stats[i].rx_packets;
4480                 stats[N_TX_RINGS].tx_packets    += stats[i].tx_packets;
4481                 stats[N_TX_RINGS].rx_bytes      += stats[i].rx_bytes;
4482                 stats[N_TX_RINGS].tx_bytes      += stats[i].tx_bytes;
4483                 stats[N_TX_RINGS].rx_errors     += stats[i].rx_errors;
4484                 stats[N_TX_RINGS].tx_errors     += stats[i].tx_errors;
4485                 stats[N_TX_RINGS].rx_dropped    += stats[i].rx_dropped;
4486                 stats[N_TX_RINGS].tx_dropped    += stats[i].tx_dropped;
4487                 memset(stats + i, 0, sizeof(struct net_device_stats));
4488                 spin_unlock(&cp->stat_lock[i]);
4489         }
4490         spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4491         return stats + N_TX_RINGS;
4492 }
4493
4494
4495 static void cas_set_multicast(struct net_device *dev)
4496 {
4497         struct cas *cp = netdev_priv(dev);
4498         u32 rxcfg, rxcfg_new;
4499         unsigned long flags;
4500         int limit = STOP_TRIES;
4501
4502         if (!cp->hw_running)
4503                 return;
4504
4505         spin_lock_irqsave(&cp->lock, flags);
4506         rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4507
4508         /* disable RX MAC and wait for completion */
4509         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4510         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4511                 if (!limit--)
4512                         break;
4513                 udelay(10);
4514         }
4515
4516         /* disable hash filter and wait for completion */
4517         limit = STOP_TRIES;
4518         rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4519         writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4520         while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4521                 if (!limit--)
4522                         break;
4523                 udelay(10);
4524         }
4525
4526         /* program hash filters */
4527         cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4528         rxcfg |= rxcfg_new;
4529         writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4530         spin_unlock_irqrestore(&cp->lock, flags);
4531 }
4532
4533 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4534 {
4535         struct cas *cp = netdev_priv(dev);
4536         strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4537         strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4538         info->fw_version[0] = '\0';
4539         strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4540         info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4541                 cp->casreg_len : CAS_MAX_REGS;
4542         info->n_stats = CAS_NUM_STAT_KEYS;
4543 }
4544
4545 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4546 {
4547         struct cas *cp = netdev_priv(dev);
4548         u16 bmcr;
4549         int full_duplex, speed, pause;
4550         unsigned long flags;
4551         enum link_state linkstate = link_up;
4552
4553         cmd->advertising = 0;
4554         cmd->supported = SUPPORTED_Autoneg;
4555         if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4556                 cmd->supported |= SUPPORTED_1000baseT_Full;
4557                 cmd->advertising |= ADVERTISED_1000baseT_Full;
4558         }
4559
4560         /* Record PHY settings if HW is on. */
4561         spin_lock_irqsave(&cp->lock, flags);
4562         bmcr = 0;
4563         linkstate = cp->lstate;
4564         if (CAS_PHY_MII(cp->phy_type)) {
4565                 cmd->port = PORT_MII;
4566                 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4567                         XCVR_INTERNAL : XCVR_EXTERNAL;
4568                 cmd->phy_address = cp->phy_addr;
4569                 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4570                         ADVERTISED_10baseT_Half |
4571                         ADVERTISED_10baseT_Full |
4572                         ADVERTISED_100baseT_Half |
4573                         ADVERTISED_100baseT_Full;
4574
4575                 cmd->supported |=
4576                         (SUPPORTED_10baseT_Half |
4577                          SUPPORTED_10baseT_Full |
4578                          SUPPORTED_100baseT_Half |
4579                          SUPPORTED_100baseT_Full |
4580                          SUPPORTED_TP | SUPPORTED_MII);
4581
4582                 if (cp->hw_running) {
4583                         cas_mif_poll(cp, 0);
4584                         bmcr = cas_phy_read(cp, MII_BMCR);
4585                         cas_read_mii_link_mode(cp, &full_duplex,
4586                                                &speed, &pause);
4587                         cas_mif_poll(cp, 1);
4588                 }
4589
4590         } else {
4591                 cmd->port = PORT_FIBRE;
4592                 cmd->transceiver = XCVR_INTERNAL;
4593                 cmd->phy_address = 0;
4594                 cmd->supported   |= SUPPORTED_FIBRE;
4595                 cmd->advertising |= ADVERTISED_FIBRE;
4596
4597                 if (cp->hw_running) {
4598                         /* pcs uses the same bits as mii */
4599                         bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4600                         cas_read_pcs_link_mode(cp, &full_duplex,
4601                                                &speed, &pause);
4602                 }
4603         }
4604         spin_unlock_irqrestore(&cp->lock, flags);
4605
4606         if (bmcr & BMCR_ANENABLE) {
4607                 cmd->advertising |= ADVERTISED_Autoneg;
4608                 cmd->autoneg = AUTONEG_ENABLE;
4609                 ethtool_cmd_speed_set(cmd, ((speed == 10) ?
4610                                             SPEED_10 :
4611                                             ((speed == 1000) ?
4612                                              SPEED_1000 : SPEED_100)));
4613                 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4614         } else {
4615                 cmd->autoneg = AUTONEG_DISABLE;
4616                 ethtool_cmd_speed_set(cmd, ((bmcr & CAS_BMCR_SPEED1000) ?
4617                                             SPEED_1000 :
4618                                             ((bmcr & BMCR_SPEED100) ?
4619                                              SPEED_100 : SPEED_10)));
4620                 cmd->duplex =
4621                         (bmcr & BMCR_FULLDPLX) ?
4622                         DUPLEX_FULL : DUPLEX_HALF;
4623         }
4624         if (linkstate != link_up) {
4625                 /* Force these to "unknown" if the link is not up and
4626                  * autonogotiation in enabled. We can set the link
4627                  * speed to 0, but not cmd->duplex,
4628                  * because its legal values are 0 and 1.  Ethtool will
4629                  * print the value reported in parentheses after the
4630                  * word "Unknown" for unrecognized values.
4631                  *
4632                  * If in forced mode, we report the speed and duplex
4633                  * settings that we configured.
4634                  */
4635                 if (cp->link_cntl & BMCR_ANENABLE) {
4636                         ethtool_cmd_speed_set(cmd, 0);
4637                         cmd->duplex = 0xff;
4638                 } else {
4639                         ethtool_cmd_speed_set(cmd, SPEED_10);
4640                         if (cp->link_cntl & BMCR_SPEED100) {
4641                                 ethtool_cmd_speed_set(cmd, SPEED_100);
4642                         } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4643                                 ethtool_cmd_speed_set(cmd, SPEED_1000);
4644                         }
4645                         cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4646                                 DUPLEX_FULL : DUPLEX_HALF;
4647                 }
4648         }
4649         return 0;
4650 }
4651
4652 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4653 {
4654         struct cas *cp = netdev_priv(dev);
4655         unsigned long flags;
4656         u32 speed = ethtool_cmd_speed(cmd);
4657
4658         /* Verify the settings we care about. */
4659         if (cmd->autoneg != AUTONEG_ENABLE &&
4660             cmd->autoneg != AUTONEG_DISABLE)
4661                 return -EINVAL;
4662
4663         if (cmd->autoneg == AUTONEG_DISABLE &&
4664             ((speed != SPEED_1000 &&
4665               speed != SPEED_100 &&
4666               speed != SPEED_10) ||
4667              (cmd->duplex != DUPLEX_HALF &&
4668               cmd->duplex != DUPLEX_FULL)))
4669                 return -EINVAL;
4670
4671         /* Apply settings and restart link process. */
4672         spin_lock_irqsave(&cp->lock, flags);
4673         cas_begin_auto_negotiation(cp, cmd);
4674         spin_unlock_irqrestore(&cp->lock, flags);
4675         return 0;
4676 }
4677
4678 static int cas_nway_reset(struct net_device *dev)
4679 {
4680         struct cas *cp = netdev_priv(dev);
4681         unsigned long flags;
4682
4683         if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4684                 return -EINVAL;
4685
4686         /* Restart link process. */
4687         spin_lock_irqsave(&cp->lock, flags);
4688         cas_begin_auto_negotiation(cp, NULL);
4689         spin_unlock_irqrestore(&cp->lock, flags);
4690
4691         return 0;
4692 }
4693
4694 static u32 cas_get_link(struct net_device *dev)
4695 {
4696         struct cas *cp = netdev_priv(dev);
4697         return cp->lstate == link_up;
4698 }
4699
4700 static u32 cas_get_msglevel(struct net_device *dev)
4701 {
4702         struct cas *cp = netdev_priv(dev);
4703         return cp->msg_enable;
4704 }
4705
4706 static void cas_set_msglevel(struct net_device *dev, u32 value)
4707 {
4708         struct cas *cp = netdev_priv(dev);
4709         cp->msg_enable = value;
4710 }
4711
4712 static int cas_get_regs_len(struct net_device *dev)
4713 {
4714         struct cas *cp = netdev_priv(dev);
4715         return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4716 }
4717
4718 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4719                              void *p)
4720 {
4721         struct cas *cp = netdev_priv(dev);
4722         regs->version = 0;
4723         /* cas_read_regs handles locks (cp->lock).  */
4724         cas_read_regs(cp, p, regs->len / sizeof(u32));
4725 }
4726
4727 static int cas_get_sset_count(struct net_device *dev, int sset)
4728 {
4729         switch (sset) {
4730         case ETH_SS_STATS:
4731                 return CAS_NUM_STAT_KEYS;
4732         default:
4733                 return -EOPNOTSUPP;
4734         }
4735 }
4736
4737 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4738 {
4739          memcpy(data, &ethtool_cassini_statnames,
4740                                          CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4741 }
4742
4743 static void cas_get_ethtool_stats(struct net_device *dev,
4744                                       struct ethtool_stats *estats, u64 *data)
4745 {
4746         struct cas *cp = netdev_priv(dev);
4747         struct net_device_stats *stats = cas_get_stats(cp->dev);
4748         int i = 0;
4749         data[i++] = stats->collisions;
4750         data[i++] = stats->rx_bytes;
4751         data[i++] = stats->rx_crc_errors;
4752         data[i++] = stats->rx_dropped;
4753         data[i++] = stats->rx_errors;
4754         data[i++] = stats->rx_fifo_errors;
4755         data[i++] = stats->rx_frame_errors;
4756         data[i++] = stats->rx_length_errors;
4757         data[i++] = stats->rx_over_errors;
4758         data[i++] = stats->rx_packets;
4759         data[i++] = stats->tx_aborted_errors;
4760         data[i++] = stats->tx_bytes;
4761         data[i++] = stats->tx_dropped;
4762         data[i++] = stats->tx_errors;
4763         data[i++] = stats->tx_fifo_errors;
4764         data[i++] = stats->tx_packets;
4765         BUG_ON(i != CAS_NUM_STAT_KEYS);
4766 }
4767
4768 static const struct ethtool_ops cas_ethtool_ops = {
4769         .get_drvinfo            = cas_get_drvinfo,
4770         .get_settings           = cas_get_settings,
4771         .set_settings           = cas_set_settings,
4772         .nway_reset             = cas_nway_reset,
4773         .get_link               = cas_get_link,
4774         .get_msglevel           = cas_get_msglevel,
4775         .set_msglevel           = cas_set_msglevel,
4776         .get_regs_len           = cas_get_regs_len,
4777         .get_regs               = cas_get_regs,
4778         .get_sset_count         = cas_get_sset_count,
4779         .get_strings            = cas_get_strings,
4780         .get_ethtool_stats      = cas_get_ethtool_stats,
4781 };
4782
4783 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4784 {
4785         struct cas *cp = netdev_priv(dev);
4786         struct mii_ioctl_data *data = if_mii(ifr);
4787         unsigned long flags;
4788         int rc = -EOPNOTSUPP;
4789
4790         /* Hold the PM mutex while doing ioctl's or we may collide
4791          * with open/close and power management and oops.
4792          */
4793         mutex_lock(&cp->pm_mutex);
4794         switch (cmd) {
4795         case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
4796                 data->phy_id = cp->phy_addr;
4797                 /* Fallthrough... */
4798
4799         case SIOCGMIIREG:               /* Read MII PHY register. */
4800                 spin_lock_irqsave(&cp->lock, flags);
4801                 cas_mif_poll(cp, 0);
4802                 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4803                 cas_mif_poll(cp, 1);
4804                 spin_unlock_irqrestore(&cp->lock, flags);
4805                 rc = 0;
4806                 break;
4807
4808         case SIOCSMIIREG:               /* Write MII PHY register. */
4809                 spin_lock_irqsave(&cp->lock, flags);
4810                 cas_mif_poll(cp, 0);
4811                 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4812                 cas_mif_poll(cp, 1);
4813                 spin_unlock_irqrestore(&cp->lock, flags);
4814                 break;
4815         default:
4816                 break;
4817         }
4818
4819         mutex_unlock(&cp->pm_mutex);
4820         return rc;
4821 }
4822
4823 /* When this chip sits underneath an Intel 31154 bridge, it is the
4824  * only subordinate device and we can tweak the bridge settings to
4825  * reflect that fact.
4826  */
4827 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4828 {
4829         struct pci_dev *pdev = cas_pdev->bus->self;
4830         u32 val;
4831
4832         if (!pdev)
4833                 return;
4834
4835         if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4836                 return;
4837
4838         /* Clear bit 10 (Bus Parking Control) in the Secondary
4839          * Arbiter Control/Status Register which lives at offset
4840          * 0x41.  Using a 32-bit word read/modify/write at 0x40
4841          * is much simpler so that's how we do this.
4842          */
4843         pci_read_config_dword(pdev, 0x40, &val);
4844         val &= ~0x00040000;
4845         pci_write_config_dword(pdev, 0x40, val);
4846
4847         /* Max out the Multi-Transaction Timer settings since
4848          * Cassini is the only device present.
4849          *
4850          * The register is 16-bit and lives at 0x50.  When the
4851          * settings are enabled, it extends the GRANT# signal
4852          * for a requestor after a transaction is complete.  This
4853          * allows the next request to run without first needing
4854          * to negotiate the GRANT# signal back.
4855          *
4856          * Bits 12:10 define the grant duration:
4857          *
4858          *      1       --      16 clocks
4859          *      2       --      32 clocks
4860          *      3       --      64 clocks
4861          *      4       --      128 clocks
4862          *      5       --      256 clocks
4863          *
4864          * All other values are illegal.
4865          *
4866          * Bits 09:00 define which REQ/GNT signal pairs get the
4867          * GRANT# signal treatment.  We set them all.
4868          */
4869         pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4870
4871         /* The Read Prefecth Policy register is 16-bit and sits at
4872          * offset 0x52.  It enables a "smart" pre-fetch policy.  We
4873          * enable it and max out all of the settings since only one
4874          * device is sitting underneath and thus bandwidth sharing is
4875          * not an issue.
4876          *
4877          * The register has several 3 bit fields, which indicates a
4878          * multiplier applied to the base amount of prefetching the
4879          * chip would do.  These fields are at:
4880          *
4881          *      15:13   ---     ReRead Primary Bus
4882          *      12:10   ---     FirstRead Primary Bus
4883          *      09:07   ---     ReRead Secondary Bus
4884          *      06:04   ---     FirstRead Secondary Bus
4885          *
4886          * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4887          * get enabled on.  Bit 3 is a grouped enabler which controls
4888          * all of the REQ/GNT pairs from [8:3].  Bits 2 to 0 control
4889          * the individual REQ/GNT pairs [2:0].
4890          */
4891         pci_write_config_word(pdev, 0x52,
4892                               (0x7 << 13) |
4893                               (0x7 << 10) |
4894                               (0x7 <<  7) |
4895                               (0x7 <<  4) |
4896                               (0xf <<  0));
4897
4898         /* Force cacheline size to 0x8 */
4899         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4900
4901         /* Force latency timer to maximum setting so Cassini can
4902          * sit on the bus as long as it likes.
4903          */
4904         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4905 }
4906
4907 static const struct net_device_ops cas_netdev_ops = {
4908         .ndo_open               = cas_open,
4909         .ndo_stop               = cas_close,
4910         .ndo_start_xmit         = cas_start_xmit,
4911         .ndo_get_stats          = cas_get_stats,
4912         .ndo_set_multicast_list = cas_set_multicast,
4913         .ndo_do_ioctl           = cas_ioctl,
4914         .ndo_tx_timeout         = cas_tx_timeout,
4915         .ndo_change_mtu         = cas_change_mtu,
4916         .ndo_set_mac_address    = eth_mac_addr,
4917         .ndo_validate_addr      = eth_validate_addr,
4918 #ifdef CONFIG_NET_POLL_CONTROLLER
4919         .ndo_poll_controller    = cas_netpoll,
4920 #endif
4921 };
4922
4923 static int __devinit cas_init_one(struct pci_dev *pdev,
4924                                   const struct pci_device_id *ent)
4925 {
4926         static int cas_version_printed = 0;
4927         unsigned long casreg_len;
4928         struct net_device *dev;
4929         struct cas *cp;
4930         int i, err, pci_using_dac;
4931         u16 pci_cmd;
4932         u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4933
4934         if (cas_version_printed++ == 0)
4935                 pr_info("%s", version);
4936
4937         err = pci_enable_device(pdev);
4938         if (err) {
4939                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4940                 return err;
4941         }
4942
4943         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4944                 dev_err(&pdev->dev, "Cannot find proper PCI device "
4945                        "base address, aborting\n");
4946                 err = -ENODEV;
4947                 goto err_out_disable_pdev;
4948         }
4949
4950         dev = alloc_etherdev(sizeof(*cp));
4951         if (!dev) {
4952                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
4953                 err = -ENOMEM;
4954                 goto err_out_disable_pdev;
4955         }
4956         SET_NETDEV_DEV(dev, &pdev->dev);
4957
4958         err = pci_request_regions(pdev, dev->name);
4959         if (err) {
4960                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4961                 goto err_out_free_netdev;
4962         }
4963         pci_set_master(pdev);
4964
4965         /* we must always turn on parity response or else parity
4966          * doesn't get generated properly. disable SERR/PERR as well.
4967          * in addition, we want to turn MWI on.
4968          */
4969         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4970         pci_cmd &= ~PCI_COMMAND_SERR;
4971         pci_cmd |= PCI_COMMAND_PARITY;
4972         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4973         if (pci_try_set_mwi(pdev))
4974                 pr_warning("Could not enable MWI for %s\n", pci_name(pdev));
4975
4976         cas_program_bridge(pdev);
4977
4978         /*
4979          * On some architectures, the default cache line size set
4980          * by pci_try_set_mwi reduces perforamnce.  We have to increase
4981          * it for this case.  To start, we'll print some configuration
4982          * data.
4983          */
4984 #if 1
4985         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4986                              &orig_cacheline_size);
4987         if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4988                 cas_cacheline_size =
4989                         (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4990                         CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4991                 if (pci_write_config_byte(pdev,
4992                                           PCI_CACHE_LINE_SIZE,
4993                                           cas_cacheline_size)) {
4994                         dev_err(&pdev->dev, "Could not set PCI cache "
4995                                "line size\n");
4996                         goto err_write_cacheline;
4997                 }
4998         }
4999 #endif
5000
5001
5002         /* Configure DMA attributes. */
5003         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5004                 pci_using_dac = 1;
5005                 err = pci_set_consistent_dma_mask(pdev,
5006                                                   DMA_BIT_MASK(64));
5007                 if (err < 0) {
5008                         dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5009                                "for consistent allocations\n");
5010                         goto err_out_free_res;
5011                 }
5012
5013         } else {
5014                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5015                 if (err) {
5016                         dev_err(&pdev->dev, "No usable DMA configuration, "
5017                                "aborting\n");
5018                         goto err_out_free_res;
5019                 }
5020                 pci_using_dac = 0;
5021         }
5022
5023         casreg_len = pci_resource_len(pdev, 0);
5024
5025         cp = netdev_priv(dev);
5026         cp->pdev = pdev;
5027 #if 1
5028         /* A value of 0 indicates we never explicitly set it */
5029         cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5030 #endif
5031         cp->dev = dev;
5032         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5033           cassini_debug;
5034
5035 #if defined(CONFIG_SPARC)
5036         cp->of_node = pci_device_to_OF_node(pdev);
5037 #endif
5038
5039         cp->link_transition = LINK_TRANSITION_UNKNOWN;
5040         cp->link_transition_jiffies_valid = 0;
5041
5042         spin_lock_init(&cp->lock);
5043         spin_lock_init(&cp->rx_inuse_lock);
5044         spin_lock_init(&cp->rx_spare_lock);
5045         for (i = 0; i < N_TX_RINGS; i++) {
5046                 spin_lock_init(&cp->stat_lock[i]);
5047                 spin_lock_init(&cp->tx_lock[i]);
5048         }
5049         spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5050         mutex_init(&cp->pm_mutex);
5051
5052         init_timer(&cp->link_timer);
5053         cp->link_timer.function = cas_link_timer;
5054         cp->link_timer.data = (unsigned long) cp;
5055
5056 #if 1
5057         /* Just in case the implementation of atomic operations
5058          * change so that an explicit initialization is necessary.
5059          */
5060         atomic_set(&cp->reset_task_pending, 0);
5061         atomic_set(&cp->reset_task_pending_all, 0);
5062         atomic_set(&cp->reset_task_pending_spare, 0);
5063         atomic_set(&cp->reset_task_pending_mtu, 0);
5064 #endif
5065         INIT_WORK(&cp->reset_task, cas_reset_task);
5066
5067         /* Default link parameters */
5068         if (link_mode >= 0 && link_mode < 6)
5069                 cp->link_cntl = link_modes[link_mode];
5070         else
5071                 cp->link_cntl = BMCR_ANENABLE;
5072         cp->lstate = link_down;
5073         cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5074         netif_carrier_off(cp->dev);
5075         cp->timer_ticks = 0;
5076
5077         /* give us access to cassini registers */
5078         cp->regs = pci_iomap(pdev, 0, casreg_len);
5079         if (!cp->regs) {
5080                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5081                 goto err_out_free_res;
5082         }
5083         cp->casreg_len = casreg_len;
5084
5085         pci_save_state(pdev);
5086         cas_check_pci_invariants(cp);
5087         cas_hard_reset(cp);
5088         cas_reset(cp, 0);
5089         if (cas_check_invariants(cp))
5090                 goto err_out_iounmap;
5091         if (cp->cas_flags & CAS_FLAG_SATURN)
5092                 if (cas_saturn_firmware_init(cp))
5093                         goto err_out_iounmap;
5094
5095         cp->init_block = (struct cas_init_block *)
5096                 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5097                                      &cp->block_dvma);
5098         if (!cp->init_block) {
5099                 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5100                 goto err_out_iounmap;
5101         }
5102
5103         for (i = 0; i < N_TX_RINGS; i++)
5104                 cp->init_txds[i] = cp->init_block->txds[i];
5105
5106         for (i = 0; i < N_RX_DESC_RINGS; i++)
5107                 cp->init_rxds[i] = cp->init_block->rxds[i];
5108
5109         for (i = 0; i < N_RX_COMP_RINGS; i++)
5110                 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5111
5112         for (i = 0; i < N_RX_FLOWS; i++)
5113                 skb_queue_head_init(&cp->rx_flows[i]);
5114
5115         dev->netdev_ops = &cas_netdev_ops;
5116         dev->ethtool_ops = &cas_ethtool_ops;
5117         dev->watchdog_timeo = CAS_TX_TIMEOUT;
5118
5119 #ifdef USE_NAPI
5120         netif_napi_add(dev, &cp->napi, cas_poll, 64);
5121 #endif
5122         dev->irq = pdev->irq;
5123         dev->dma = 0;
5124
5125         /* Cassini features. */
5126         if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5127                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5128
5129         if (pci_using_dac)
5130                 dev->features |= NETIF_F_HIGHDMA;
5131
5132         if (register_netdev(dev)) {
5133                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5134                 goto err_out_free_consistent;
5135         }
5136
5137         i = readl(cp->regs + REG_BIM_CFG);
5138         netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5139                     (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5140                     (i & BIM_CFG_32BIT) ? "32" : "64",
5141                     (i & BIM_CFG_66MHZ) ? "66" : "33",
5142                     (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5143                     dev->dev_addr);
5144
5145         pci_set_drvdata(pdev, dev);
5146         cp->hw_running = 1;
5147         cas_entropy_reset(cp);
5148         cas_phy_init(cp);
5149         cas_begin_auto_negotiation(cp, NULL);
5150         return 0;
5151
5152 err_out_free_consistent:
5153         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5154                             cp->init_block, cp->block_dvma);
5155
5156 err_out_iounmap:
5157         mutex_lock(&cp->pm_mutex);
5158         if (cp->hw_running)
5159                 cas_shutdown(cp);
5160         mutex_unlock(&cp->pm_mutex);
5161
5162         pci_iounmap(pdev, cp->regs);
5163
5164
5165 err_out_free_res:
5166         pci_release_regions(pdev);
5167
5168 err_write_cacheline:
5169         /* Try to restore it in case the error occurred after we
5170          * set it.
5171          */
5172         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5173
5174 err_out_free_netdev:
5175         free_netdev(dev);
5176
5177 err_out_disable_pdev:
5178         pci_disable_device(pdev);
5179         pci_set_drvdata(pdev, NULL);
5180         return -ENODEV;
5181 }
5182
5183 static void __devexit cas_remove_one(struct pci_dev *pdev)
5184 {
5185         struct net_device *dev = pci_get_drvdata(pdev);
5186         struct cas *cp;
5187         if (!dev)
5188                 return;
5189
5190         cp = netdev_priv(dev);
5191         unregister_netdev(dev);
5192
5193         if (cp->fw_data)
5194                 vfree(cp->fw_data);
5195
5196         mutex_lock(&cp->pm_mutex);
5197         cancel_work_sync(&cp->reset_task);
5198         if (cp->hw_running)
5199                 cas_shutdown(cp);
5200         mutex_unlock(&cp->pm_mutex);
5201
5202 #if 1
5203         if (cp->orig_cacheline_size) {
5204                 /* Restore the cache line size if we had modified
5205                  * it.
5206                  */
5207                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5208                                       cp->orig_cacheline_size);
5209         }
5210 #endif
5211         pci_free_consistent(pdev, sizeof(struct cas_init_block),
5212                             cp->init_block, cp->block_dvma);
5213         pci_iounmap(pdev, cp->regs);
5214         free_netdev(dev);
5215         pci_release_regions(pdev);
5216         pci_disable_device(pdev);
5217         pci_set_drvdata(pdev, NULL);
5218 }
5219
5220 #ifdef CONFIG_PM
5221 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5222 {
5223         struct net_device *dev = pci_get_drvdata(pdev);
5224         struct cas *cp = netdev_priv(dev);
5225         unsigned long flags;
5226
5227         mutex_lock(&cp->pm_mutex);
5228
5229         /* If the driver is opened, we stop the DMA */
5230         if (cp->opened) {
5231                 netif_device_detach(dev);
5232
5233                 cas_lock_all_save(cp, flags);
5234
5235                 /* We can set the second arg of cas_reset to 0
5236                  * because on resume, we'll call cas_init_hw with
5237                  * its second arg set so that autonegotiation is
5238                  * restarted.
5239                  */
5240                 cas_reset(cp, 0);
5241                 cas_clean_rings(cp);
5242                 cas_unlock_all_restore(cp, flags);
5243         }
5244
5245         if (cp->hw_running)
5246                 cas_shutdown(cp);
5247         mutex_unlock(&cp->pm_mutex);
5248
5249         return 0;
5250 }
5251
5252 static int cas_resume(struct pci_dev *pdev)
5253 {
5254         struct net_device *dev = pci_get_drvdata(pdev);
5255         struct cas *cp = netdev_priv(dev);
5256
5257         netdev_info(dev, "resuming\n");
5258
5259         mutex_lock(&cp->pm_mutex);
5260         cas_hard_reset(cp);
5261         if (cp->opened) {
5262                 unsigned long flags;
5263                 cas_lock_all_save(cp, flags);
5264                 cas_reset(cp, 0);
5265                 cp->hw_running = 1;
5266                 cas_clean_rings(cp);
5267                 cas_init_hw(cp, 1);
5268                 cas_unlock_all_restore(cp, flags);
5269
5270                 netif_device_attach(dev);
5271         }
5272         mutex_unlock(&cp->pm_mutex);
5273         return 0;
5274 }
5275 #endif /* CONFIG_PM */
5276
5277 static struct pci_driver cas_driver = {
5278         .name           = DRV_MODULE_NAME,
5279         .id_table       = cas_pci_tbl,
5280         .probe          = cas_init_one,
5281         .remove         = __devexit_p(cas_remove_one),
5282 #ifdef CONFIG_PM
5283         .suspend        = cas_suspend,
5284         .resume         = cas_resume
5285 #endif
5286 };
5287
5288 static int __init cas_init(void)
5289 {
5290         if (linkdown_timeout > 0)
5291                 link_transition_timeout = linkdown_timeout * HZ;
5292         else
5293                 link_transition_timeout = 0;
5294
5295         return pci_register_driver(&cas_driver);
5296 }
5297
5298 static void __exit cas_cleanup(void)
5299 {
5300         pci_unregister_driver(&cas_driver);
5301 }
5302
5303 module_init(cas_init);
5304 module_exit(cas_cleanup);