bnx2x: Disable napi
[linux-2.6.git] / drivers / net / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2009 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>  /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52
53 #include "bnx2x_reg.h"
54 #include "bnx2x_fw_defs.h"
55 #include "bnx2x_hsi.h"
56 #include "bnx2x_link.h"
57 #include "bnx2x.h"
58 #include "bnx2x_init.h"
59
60 #define DRV_MODULE_VERSION      "1.45.24"
61 #define DRV_MODULE_RELDATE      "2009/01/14"
62 #define BNX2X_BC_VER            0x040200
63
64 /* Time in jiffies before concluding the transmitter is hung */
65 #define TX_TIMEOUT              (5*HZ)
66
67 static char version[] __devinitdata =
68         "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
69         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71 MODULE_AUTHOR("Eliezer Tamir");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
75
76 static int disable_tpa;
77 static int use_inta;
78 static int poll;
79 static int debug;
80 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
81 static int use_multi;
82
83 module_param(disable_tpa, int, 0);
84 module_param(use_inta, int, 0);
85 module_param(poll, int, 0);
86 module_param(debug, int, 0);
87 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
88 MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
89 MODULE_PARM_DESC(poll, "use polling (for debug)");
90 MODULE_PARM_DESC(debug, "default debug msglevel");
91
92 #ifdef BNX2X_MULTI
93 module_param(use_multi, int, 0);
94 MODULE_PARM_DESC(use_multi, "use per-CPU queues");
95 #endif
96 static struct workqueue_struct *bnx2x_wq;
97
98 enum bnx2x_board_type {
99         BCM57710 = 0,
100         BCM57711 = 1,
101         BCM57711E = 2,
102 };
103
104 /* indexed by board_type, above */
105 static struct {
106         char *name;
107 } board_info[] __devinitdata = {
108         { "Broadcom NetXtreme II BCM57710 XGb" },
109         { "Broadcom NetXtreme II BCM57711 XGb" },
110         { "Broadcom NetXtreme II BCM57711E XGb" }
111 };
112
113
114 static const struct pci_device_id bnx2x_pci_tbl[] = {
115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
121         { 0 }
122 };
123
124 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
125
126 /****************************************************************************
127 * General service functions
128 ****************************************************************************/
129
130 /* used only at init
131  * locking is done by mcp
132  */
133 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
134 {
135         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
136         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
137         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
138                                PCICFG_VENDOR_ID_OFFSET);
139 }
140
141 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
142 {
143         u32 val;
144
145         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
146         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
147         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
148                                PCICFG_VENDOR_ID_OFFSET);
149
150         return val;
151 }
152
153 static const u32 dmae_reg_go_c[] = {
154         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158 };
159
160 /* copy command into DMAE command memory and set DMAE command go */
161 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162                             int idx)
163 {
164         u32 cmd_offset;
165         int i;
166
167         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171                 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
173         }
174         REG_WR(bp, dmae_reg_go_c[idx], 1);
175 }
176
177 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
178                       u32 len32)
179 {
180         struct dmae_command *dmae = &bp->init_dmae;
181         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
182         int cnt = 200;
183
184         if (!bp->dmae_ready) {
185                 u32 *data = bnx2x_sp(bp, wb_data[0]);
186
187                 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
188                    "  using indirect\n", dst_addr, len32);
189                 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
190                 return;
191         }
192
193         mutex_lock(&bp->dmae_mutex);
194
195         memset(dmae, 0, sizeof(struct dmae_command));
196
197         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
198                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
199                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
200 #ifdef __BIG_ENDIAN
201                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
202 #else
203                         DMAE_CMD_ENDIANITY_DW_SWAP |
204 #endif
205                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
206                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
207         dmae->src_addr_lo = U64_LO(dma_addr);
208         dmae->src_addr_hi = U64_HI(dma_addr);
209         dmae->dst_addr_lo = dst_addr >> 2;
210         dmae->dst_addr_hi = 0;
211         dmae->len = len32;
212         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
213         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
214         dmae->comp_val = DMAE_COMP_VAL;
215
216         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
217            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
218                     "dst_addr [%x:%08x (%08x)]\n"
219            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
220            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
221            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
222            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
223         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
224            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
225            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
226
227         *wb_comp = 0;
228
229         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
230
231         udelay(5);
232
233         while (*wb_comp != DMAE_COMP_VAL) {
234                 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
235
236                 if (!cnt) {
237                         BNX2X_ERR("dmae timeout!\n");
238                         break;
239                 }
240                 cnt--;
241                 /* adjust delay for emulation/FPGA */
242                 if (CHIP_REV_IS_SLOW(bp))
243                         msleep(100);
244                 else
245                         udelay(5);
246         }
247
248         mutex_unlock(&bp->dmae_mutex);
249 }
250
251 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
252 {
253         struct dmae_command *dmae = &bp->init_dmae;
254         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
255         int cnt = 200;
256
257         if (!bp->dmae_ready) {
258                 u32 *data = bnx2x_sp(bp, wb_data[0]);
259                 int i;
260
261                 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x  len32 %d)"
262                    "  using indirect\n", src_addr, len32);
263                 for (i = 0; i < len32; i++)
264                         data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
265                 return;
266         }
267
268         mutex_lock(&bp->dmae_mutex);
269
270         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
271         memset(dmae, 0, sizeof(struct dmae_command));
272
273         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
274                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
275                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
276 #ifdef __BIG_ENDIAN
277                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
278 #else
279                         DMAE_CMD_ENDIANITY_DW_SWAP |
280 #endif
281                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
282                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
283         dmae->src_addr_lo = src_addr >> 2;
284         dmae->src_addr_hi = 0;
285         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
286         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
287         dmae->len = len32;
288         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
289         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
290         dmae->comp_val = DMAE_COMP_VAL;
291
292         DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
293            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
294                     "dst_addr [%x:%08x (%08x)]\n"
295            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
296            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
297            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
298            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
299
300         *wb_comp = 0;
301
302         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
303
304         udelay(5);
305
306         while (*wb_comp != DMAE_COMP_VAL) {
307
308                 if (!cnt) {
309                         BNX2X_ERR("dmae timeout!\n");
310                         break;
311                 }
312                 cnt--;
313                 /* adjust delay for emulation/FPGA */
314                 if (CHIP_REV_IS_SLOW(bp))
315                         msleep(100);
316                 else
317                         udelay(5);
318         }
319         DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
320            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
321            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
322
323         mutex_unlock(&bp->dmae_mutex);
324 }
325
326 /* used only for slowpath so not inlined */
327 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
328 {
329         u32 wb_write[2];
330
331         wb_write[0] = val_hi;
332         wb_write[1] = val_lo;
333         REG_WR_DMAE(bp, reg, wb_write, 2);
334 }
335
336 #ifdef USE_WB_RD
337 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
338 {
339         u32 wb_data[2];
340
341         REG_RD_DMAE(bp, reg, wb_data, 2);
342
343         return HILO_U64(wb_data[0], wb_data[1]);
344 }
345 #endif
346
347 static int bnx2x_mc_assert(struct bnx2x *bp)
348 {
349         char last_idx;
350         int i, rc = 0;
351         u32 row0, row1, row2, row3;
352
353         /* XSTORM */
354         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
355                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
356         if (last_idx)
357                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
358
359         /* print the asserts */
360         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
361
362                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
363                               XSTORM_ASSERT_LIST_OFFSET(i));
364                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
365                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
366                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
368                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
370
371                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
372                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
373                                   " 0x%08x 0x%08x 0x%08x\n",
374                                   i, row3, row2, row1, row0);
375                         rc++;
376                 } else {
377                         break;
378                 }
379         }
380
381         /* TSTORM */
382         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
383                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
384         if (last_idx)
385                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
386
387         /* print the asserts */
388         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
389
390                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
391                               TSTORM_ASSERT_LIST_OFFSET(i));
392                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
393                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
394                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
396                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
398
399                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
400                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
401                                   " 0x%08x 0x%08x 0x%08x\n",
402                                   i, row3, row2, row1, row0);
403                         rc++;
404                 } else {
405                         break;
406                 }
407         }
408
409         /* CSTORM */
410         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
411                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
412         if (last_idx)
413                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
414
415         /* print the asserts */
416         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
417
418                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
419                               CSTORM_ASSERT_LIST_OFFSET(i));
420                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
421                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
422                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
424                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
426
427                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
428                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
429                                   " 0x%08x 0x%08x 0x%08x\n",
430                                   i, row3, row2, row1, row0);
431                         rc++;
432                 } else {
433                         break;
434                 }
435         }
436
437         /* USTORM */
438         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
439                            USTORM_ASSERT_LIST_INDEX_OFFSET);
440         if (last_idx)
441                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
442
443         /* print the asserts */
444         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
445
446                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
447                               USTORM_ASSERT_LIST_OFFSET(i));
448                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
449                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
450                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
451                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
452                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
453                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
454
455                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
456                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
457                                   " 0x%08x 0x%08x 0x%08x\n",
458                                   i, row3, row2, row1, row0);
459                         rc++;
460                 } else {
461                         break;
462                 }
463         }
464
465         return rc;
466 }
467
468 static void bnx2x_fw_dump(struct bnx2x *bp)
469 {
470         u32 mark, offset;
471         u32 data[9];
472         int word;
473
474         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
475         mark = ((mark + 0x3) & ~0x3);
476         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
477
478         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
479                 for (word = 0; word < 8; word++)
480                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
481                                                   offset + 4*word));
482                 data[8] = 0x0;
483                 printk(KERN_CONT "%s", (char *)data);
484         }
485         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
486                 for (word = 0; word < 8; word++)
487                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
488                                                   offset + 4*word));
489                 data[8] = 0x0;
490                 printk(KERN_CONT "%s", (char *)data);
491         }
492         printk("\n" KERN_ERR PFX "end of fw dump\n");
493 }
494
495 static void bnx2x_panic_dump(struct bnx2x *bp)
496 {
497         int i;
498         u16 j, start, end;
499
500         bp->stats_state = STATS_STATE_DISABLED;
501         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
502
503         BNX2X_ERR("begin crash dump -----------------\n");
504
505         for_each_queue(bp, i) {
506                 struct bnx2x_fastpath *fp = &bp->fp[i];
507                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
508
509                 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
510                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)\n",
511                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
512                           fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
513                 BNX2X_ERR("          rx_bd_prod(%x)  rx_bd_cons(%x)"
514                           "  *rx_bd_cons_sb(%x)  rx_comp_prod(%x)"
515                           "  rx_comp_cons(%x)  *rx_cons_sb(%x)\n",
516                           fp->rx_bd_prod, fp->rx_bd_cons,
517                           le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
518                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
519                 BNX2X_ERR("          rx_sge_prod(%x)  last_max_sge(%x)"
520                           "  fp_c_idx(%x)  *sb_c_idx(%x)  fp_u_idx(%x)"
521                           "  *sb_u_idx(%x)  bd data(%x,%x)\n",
522                           fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
523                           fp->status_blk->c_status_block.status_block_index,
524                           fp->fp_u_idx,
525                           fp->status_blk->u_status_block.status_block_index,
526                           hw_prods->packets_prod, hw_prods->bds_prod);
527
528                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
529                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
530                 for (j = start; j < end; j++) {
531                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
532
533                         BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
534                                   sw_bd->skb, sw_bd->first_bd);
535                 }
536
537                 start = TX_BD(fp->tx_bd_cons - 10);
538                 end = TX_BD(fp->tx_bd_cons + 254);
539                 for (j = start; j < end; j++) {
540                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
541
542                         BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
543                                   j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
544                 }
545
546                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
547                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
548                 for (j = start; j < end; j++) {
549                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
550                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
551
552                         BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
553                                   j, rx_bd[1], rx_bd[0], sw_bd->skb);
554                 }
555
556                 start = RX_SGE(fp->rx_sge_prod);
557                 end = RX_SGE(fp->last_max_sge);
558                 for (j = start; j < end; j++) {
559                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
560                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
561
562                         BNX2X_ERR("rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
563                                   j, rx_sge[1], rx_sge[0], sw_page->page);
564                 }
565
566                 start = RCQ_BD(fp->rx_comp_cons - 10);
567                 end = RCQ_BD(fp->rx_comp_cons + 503);
568                 for (j = start; j < end; j++) {
569                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
570
571                         BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
572                                   j, cqe[0], cqe[1], cqe[2], cqe[3]);
573                 }
574         }
575
576         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
577                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
578                   "  spq_prod_idx(%u)\n",
579                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
580                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
581
582         bnx2x_fw_dump(bp);
583         bnx2x_mc_assert(bp);
584         BNX2X_ERR("end crash dump -----------------\n");
585 }
586
587 static void bnx2x_int_enable(struct bnx2x *bp)
588 {
589         int port = BP_PORT(bp);
590         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
591         u32 val = REG_RD(bp, addr);
592         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
593
594         if (msix) {
595                 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
596                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
597                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
598         } else {
599                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
600                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
601                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
602                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
603
604                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
605                    val, port, addr, msix);
606
607                 REG_WR(bp, addr, val);
608
609                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
610         }
611
612         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
613            val, port, addr, msix);
614
615         REG_WR(bp, addr, val);
616
617         if (CHIP_IS_E1H(bp)) {
618                 /* init leading/trailing edge */
619                 if (IS_E1HMF(bp)) {
620                         val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
621                         if (bp->port.pmf)
622                                 /* enable nig attention */
623                                 val |= 0x0100;
624                 } else
625                         val = 0xffff;
626
627                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
628                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
629         }
630 }
631
632 static void bnx2x_int_disable(struct bnx2x *bp)
633 {
634         int port = BP_PORT(bp);
635         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
636         u32 val = REG_RD(bp, addr);
637
638         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
639                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
640                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
641                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
642
643         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
644            val, port, addr);
645
646         REG_WR(bp, addr, val);
647         if (REG_RD(bp, addr) != val)
648                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
649 }
650
651 static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
652 {
653         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
654         int i;
655
656         /* disable interrupt handling */
657         atomic_inc(&bp->intr_sem);
658         if (disable_hw)
659                 /* prevent the HW from sending interrupts */
660                 bnx2x_int_disable(bp);
661
662         /* make sure all ISRs are done */
663         if (msix) {
664                 for_each_queue(bp, i)
665                         synchronize_irq(bp->msix_table[i].vector);
666
667                 /* one more for the Slow Path IRQ */
668                 synchronize_irq(bp->msix_table[i].vector);
669         } else
670                 synchronize_irq(bp->pdev->irq);
671
672         /* make sure sp_task is not running */
673         cancel_delayed_work(&bp->sp_task);
674         flush_workqueue(bnx2x_wq);
675 }
676
677 /* fast path */
678
679 /*
680  * General service functions
681  */
682
683 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
684                                 u8 storm, u16 index, u8 op, u8 update)
685 {
686         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
687                        COMMAND_REG_INT_ACK);
688         struct igu_ack_register igu_ack;
689
690         igu_ack.status_block_index = index;
691         igu_ack.sb_id_and_flags =
692                         ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
693                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
694                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
695                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
696
697         DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
698            (*(u32 *)&igu_ack), hc_addr);
699         REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
700 }
701
702 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
703 {
704         struct host_status_block *fpsb = fp->status_blk;
705         u16 rc = 0;
706
707         barrier(); /* status block is written to by the chip */
708         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
709                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
710                 rc |= 1;
711         }
712         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
713                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
714                 rc |= 2;
715         }
716         return rc;
717 }
718
719 static u16 bnx2x_ack_int(struct bnx2x *bp)
720 {
721         u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
722                        COMMAND_REG_SIMD_MASK);
723         u32 result = REG_RD(bp, hc_addr);
724
725         DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
726            result, hc_addr);
727
728         return result;
729 }
730
731
732 /*
733  * fast path service functions
734  */
735
736 static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
737 {
738         u16 tx_cons_sb;
739
740         /* Tell compiler that status block fields can change */
741         barrier();
742         tx_cons_sb = le16_to_cpu(*fp->tx_cons_sb);
743         return ((fp->tx_pkt_prod != tx_cons_sb) ||
744                 (fp->tx_pkt_prod != fp->tx_pkt_cons));
745 }
746
747 /* free skb in the packet ring at pos idx
748  * return idx of last bd freed
749  */
750 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
751                              u16 idx)
752 {
753         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
754         struct eth_tx_bd *tx_bd;
755         struct sk_buff *skb = tx_buf->skb;
756         u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
757         int nbd;
758
759         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
760            idx, tx_buf, skb);
761
762         /* unmap first bd */
763         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
764         tx_bd = &fp->tx_desc_ring[bd_idx];
765         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
766                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
767
768         nbd = le16_to_cpu(tx_bd->nbd) - 1;
769         new_cons = nbd + tx_buf->first_bd;
770 #ifdef BNX2X_STOP_ON_ERROR
771         if (nbd > (MAX_SKB_FRAGS + 2)) {
772                 BNX2X_ERR("BAD nbd!\n");
773                 bnx2x_panic();
774         }
775 #endif
776
777         /* Skip a parse bd and the TSO split header bd
778            since they have no mapping */
779         if (nbd)
780                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
781
782         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
783                                            ETH_TX_BD_FLAGS_TCP_CSUM |
784                                            ETH_TX_BD_FLAGS_SW_LSO)) {
785                 if (--nbd)
786                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
787                 tx_bd = &fp->tx_desc_ring[bd_idx];
788                 /* is this a TSO split header bd? */
789                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
790                         if (--nbd)
791                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
792                 }
793         }
794
795         /* now free frags */
796         while (nbd > 0) {
797
798                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
799                 tx_bd = &fp->tx_desc_ring[bd_idx];
800                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
801                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
802                 if (--nbd)
803                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
804         }
805
806         /* release skb */
807         WARN_ON(!skb);
808         dev_kfree_skb(skb);
809         tx_buf->first_bd = 0;
810         tx_buf->skb = NULL;
811
812         return new_cons;
813 }
814
815 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
816 {
817         s16 used;
818         u16 prod;
819         u16 cons;
820
821         barrier(); /* Tell compiler that prod and cons can change */
822         prod = fp->tx_bd_prod;
823         cons = fp->tx_bd_cons;
824
825         /* NUM_TX_RINGS = number of "next-page" entries
826            It will be used as a threshold */
827         used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
828
829 #ifdef BNX2X_STOP_ON_ERROR
830         WARN_ON(used < 0);
831         WARN_ON(used > fp->bp->tx_ring_size);
832         WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
833 #endif
834
835         return (s16)(fp->bp->tx_ring_size) - used;
836 }
837
838 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
839 {
840         struct bnx2x *bp = fp->bp;
841         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
842         int done = 0;
843
844 #ifdef BNX2X_STOP_ON_ERROR
845         if (unlikely(bp->panic))
846                 return;
847 #endif
848
849         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
850         sw_cons = fp->tx_pkt_cons;
851
852         while (sw_cons != hw_cons) {
853                 u16 pkt_cons;
854
855                 pkt_cons = TX_BD(sw_cons);
856
857                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
858
859                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %u\n",
860                    hw_cons, sw_cons, pkt_cons);
861
862 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
863                         rmb();
864                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
865                 }
866 */
867                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
868                 sw_cons++;
869                 done++;
870
871                 if (done == work)
872                         break;
873         }
874
875         fp->tx_pkt_cons = sw_cons;
876         fp->tx_bd_cons = bd_cons;
877
878         /* Need to make the tx_cons update visible to start_xmit()
879          * before checking for netif_queue_stopped().  Without the
880          * memory barrier, there is a small possibility that start_xmit()
881          * will miss it and cause the queue to be stopped forever.
882          */
883         smp_mb();
884
885         /* TBD need a thresh? */
886         if (unlikely(netif_queue_stopped(bp->dev))) {
887
888                 netif_tx_lock(bp->dev);
889
890                 if (netif_queue_stopped(bp->dev) &&
891                     (bp->state == BNX2X_STATE_OPEN) &&
892                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
893                         netif_wake_queue(bp->dev);
894
895                 netif_tx_unlock(bp->dev);
896         }
897 }
898
899
900 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
901                            union eth_rx_cqe *rr_cqe)
902 {
903         struct bnx2x *bp = fp->bp;
904         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
905         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
906
907         DP(BNX2X_MSG_SP,
908            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
909            FP_IDX(fp), cid, command, bp->state,
910            rr_cqe->ramrod_cqe.ramrod_type);
911
912         bp->spq_left++;
913
914         if (FP_IDX(fp)) {
915                 switch (command | fp->state) {
916                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
917                                                 BNX2X_FP_STATE_OPENING):
918                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
919                            cid);
920                         fp->state = BNX2X_FP_STATE_OPEN;
921                         break;
922
923                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
924                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
925                            cid);
926                         fp->state = BNX2X_FP_STATE_HALTED;
927                         break;
928
929                 default:
930                         BNX2X_ERR("unexpected MC reply (%d)  "
931                                   "fp->state is %x\n", command, fp->state);
932                         break;
933                 }
934                 mb(); /* force bnx2x_wait_ramrod() to see the change */
935                 return;
936         }
937
938         switch (command | bp->state) {
939         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
940                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
941                 bp->state = BNX2X_STATE_OPEN;
942                 break;
943
944         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
945                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
946                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
947                 fp->state = BNX2X_FP_STATE_HALTED;
948                 break;
949
950         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
951                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
952                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
953                 break;
954
955
956         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
957         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
958                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
959                 bp->set_mac_pending = 0;
960                 break;
961
962         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
963                 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
964                 break;
965
966         default:
967                 BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
968                           command, bp->state);
969                 break;
970         }
971         mb(); /* force bnx2x_wait_ramrod() to see the change */
972 }
973
974 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
975                                      struct bnx2x_fastpath *fp, u16 index)
976 {
977         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
978         struct page *page = sw_buf->page;
979         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
980
981         /* Skip "next page" elements */
982         if (!page)
983                 return;
984
985         pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
986                        SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
987         __free_pages(page, PAGES_PER_SGE_SHIFT);
988
989         sw_buf->page = NULL;
990         sge->addr_hi = 0;
991         sge->addr_lo = 0;
992 }
993
994 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
995                                            struct bnx2x_fastpath *fp, int last)
996 {
997         int i;
998
999         for (i = 0; i < last; i++)
1000                 bnx2x_free_rx_sge(bp, fp, i);
1001 }
1002
1003 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1004                                      struct bnx2x_fastpath *fp, u16 index)
1005 {
1006         struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1007         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1008         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1009         dma_addr_t mapping;
1010
1011         if (unlikely(page == NULL))
1012                 return -ENOMEM;
1013
1014         mapping = pci_map_page(bp->pdev, page, 0, SGE_PAGE_SIZE*PAGES_PER_SGE,
1015                                PCI_DMA_FROMDEVICE);
1016         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1017                 __free_pages(page, PAGES_PER_SGE_SHIFT);
1018                 return -ENOMEM;
1019         }
1020
1021         sw_buf->page = page;
1022         pci_unmap_addr_set(sw_buf, mapping, mapping);
1023
1024         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1025         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1026
1027         return 0;
1028 }
1029
1030 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1031                                      struct bnx2x_fastpath *fp, u16 index)
1032 {
1033         struct sk_buff *skb;
1034         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1035         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1036         dma_addr_t mapping;
1037
1038         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1039         if (unlikely(skb == NULL))
1040                 return -ENOMEM;
1041
1042         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_size,
1043                                  PCI_DMA_FROMDEVICE);
1044         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1045                 dev_kfree_skb(skb);
1046                 return -ENOMEM;
1047         }
1048
1049         rx_buf->skb = skb;
1050         pci_unmap_addr_set(rx_buf, mapping, mapping);
1051
1052         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1053         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1054
1055         return 0;
1056 }
1057
1058 /* note that we are not allocating a new skb,
1059  * we are just moving one from cons to prod
1060  * we are not creating a new mapping,
1061  * so there is no need to check for dma_mapping_error().
1062  */
1063 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1064                                struct sk_buff *skb, u16 cons, u16 prod)
1065 {
1066         struct bnx2x *bp = fp->bp;
1067         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1068         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1069         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1070         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1071
1072         pci_dma_sync_single_for_device(bp->pdev,
1073                                        pci_unmap_addr(cons_rx_buf, mapping),
1074                                        bp->rx_offset + RX_COPY_THRESH,
1075                                        PCI_DMA_FROMDEVICE);
1076
1077         prod_rx_buf->skb = cons_rx_buf->skb;
1078         pci_unmap_addr_set(prod_rx_buf, mapping,
1079                            pci_unmap_addr(cons_rx_buf, mapping));
1080         *prod_bd = *cons_bd;
1081 }
1082
1083 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1084                                              u16 idx)
1085 {
1086         u16 last_max = fp->last_max_sge;
1087
1088         if (SUB_S16(idx, last_max) > 0)
1089                 fp->last_max_sge = idx;
1090 }
1091
1092 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1093 {
1094         int i, j;
1095
1096         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1097                 int idx = RX_SGE_CNT * i - 1;
1098
1099                 for (j = 0; j < 2; j++) {
1100                         SGE_MASK_CLEAR_BIT(fp, idx);
1101                         idx--;
1102                 }
1103         }
1104 }
1105
1106 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1107                                   struct eth_fast_path_rx_cqe *fp_cqe)
1108 {
1109         struct bnx2x *bp = fp->bp;
1110         u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1111                                      le16_to_cpu(fp_cqe->len_on_bd)) >>
1112                       SGE_PAGE_SHIFT;
1113         u16 last_max, last_elem, first_elem;
1114         u16 delta = 0;
1115         u16 i;
1116
1117         if (!sge_len)
1118                 return;
1119
1120         /* First mark all used pages */
1121         for (i = 0; i < sge_len; i++)
1122                 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1123
1124         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1125            sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1126
1127         /* Here we assume that the last SGE index is the biggest */
1128         prefetch((void *)(fp->sge_mask));
1129         bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1130
1131         last_max = RX_SGE(fp->last_max_sge);
1132         last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1133         first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1134
1135         /* If ring is not full */
1136         if (last_elem + 1 != first_elem)
1137                 last_elem++;
1138
1139         /* Now update the prod */
1140         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1141                 if (likely(fp->sge_mask[i]))
1142                         break;
1143
1144                 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1145                 delta += RX_SGE_MASK_ELEM_SZ;
1146         }
1147
1148         if (delta > 0) {
1149                 fp->rx_sge_prod += delta;
1150                 /* clear page-end entries */
1151                 bnx2x_clear_sge_mask_next_elems(fp);
1152         }
1153
1154         DP(NETIF_MSG_RX_STATUS,
1155            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
1156            fp->last_max_sge, fp->rx_sge_prod);
1157 }
1158
1159 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1160 {
1161         /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1162         memset(fp->sge_mask, 0xff,
1163                (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1164
1165         /* Clear the two last indices in the page to 1:
1166            these are the indices that correspond to the "next" element,
1167            hence will never be indicated and should be removed from
1168            the calculations. */
1169         bnx2x_clear_sge_mask_next_elems(fp);
1170 }
1171
1172 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1173                             struct sk_buff *skb, u16 cons, u16 prod)
1174 {
1175         struct bnx2x *bp = fp->bp;
1176         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1177         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1178         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1179         dma_addr_t mapping;
1180
1181         /* move empty skb from pool to prod and map it */
1182         prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1183         mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1184                                  bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1185         pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1186
1187         /* move partial skb from cons to pool (don't unmap yet) */
1188         fp->tpa_pool[queue] = *cons_rx_buf;
1189
1190         /* mark bin state as start - print error if current state != stop */
1191         if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1192                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1193
1194         fp->tpa_state[queue] = BNX2X_TPA_START;
1195
1196         /* point prod_bd to new skb */
1197         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1198         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1199
1200 #ifdef BNX2X_STOP_ON_ERROR
1201         fp->tpa_queue_used |= (1 << queue);
1202 #ifdef __powerpc64__
1203         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1204 #else
1205         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1206 #endif
1207            fp->tpa_queue_used);
1208 #endif
1209 }
1210
1211 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1212                                struct sk_buff *skb,
1213                                struct eth_fast_path_rx_cqe *fp_cqe,
1214                                u16 cqe_idx)
1215 {
1216         struct sw_rx_page *rx_pg, old_rx_pg;
1217         u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1218         u32 i, frag_len, frag_size, pages;
1219         int err;
1220         int j;
1221
1222         frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1223         pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
1224
1225         /* This is needed in order to enable forwarding support */
1226         if (frag_size)
1227                 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
1228                                                max(frag_size, (u32)len_on_bd));
1229
1230 #ifdef BNX2X_STOP_ON_ERROR
1231         if (pages >
1232             min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
1233                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1234                           pages, cqe_idx);
1235                 BNX2X_ERR("fp_cqe->pkt_len = %d  fp_cqe->len_on_bd = %d\n",
1236                           fp_cqe->pkt_len, len_on_bd);
1237                 bnx2x_panic();
1238                 return -EINVAL;
1239         }
1240 #endif
1241
1242         /* Run through the SGL and compose the fragmented skb */
1243         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1244                 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1245
1246                 /* FW gives the indices of the SGE as if the ring is an array
1247                    (meaning that "next" element will consume 2 indices) */
1248                 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
1249                 rx_pg = &fp->rx_page_ring[sge_idx];
1250                 old_rx_pg = *rx_pg;
1251
1252                 /* If we fail to allocate a substitute page, we simply stop
1253                    where we are and drop the whole packet */
1254                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1255                 if (unlikely(err)) {
1256                         bp->eth_stats.rx_skb_alloc_failed++;
1257                         return err;
1258                 }
1259
1260                 /* Unmap the page as we r going to pass it to the stack */
1261                 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1262                               SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1263
1264                 /* Add one frag and update the appropriate fields in the skb */
1265                 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1266
1267                 skb->data_len += frag_len;
1268                 skb->truesize += frag_len;
1269                 skb->len += frag_len;
1270
1271                 frag_size -= frag_len;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1278                            u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1279                            u16 cqe_idx)
1280 {
1281         struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1282         struct sk_buff *skb = rx_buf->skb;
1283         /* alloc new skb */
1284         struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1285
1286         /* Unmap skb in the pool anyway, as we are going to change
1287            pool entry status to BNX2X_TPA_STOP even if new skb allocation
1288            fails. */
1289         pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1290                          bp->rx_buf_size, PCI_DMA_FROMDEVICE);
1291
1292         if (likely(new_skb)) {
1293                 /* fix ip xsum and give it to the stack */
1294                 /* (no need to map the new skb) */
1295 #ifdef BCM_VLAN
1296                 int is_vlan_cqe =
1297                         (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1298                          PARSING_FLAGS_VLAN);
1299                 int is_not_hwaccel_vlan_cqe =
1300                         (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1301 #endif
1302
1303                 prefetch(skb);
1304                 prefetch(((char *)(skb)) + 128);
1305
1306 #ifdef BNX2X_STOP_ON_ERROR
1307                 if (pad + len > bp->rx_buf_size) {
1308                         BNX2X_ERR("skb_put is about to fail...  "
1309                                   "pad %d  len %d  rx_buf_size %d\n",
1310                                   pad, len, bp->rx_buf_size);
1311                         bnx2x_panic();
1312                         return;
1313                 }
1314 #endif
1315
1316                 skb_reserve(skb, pad);
1317                 skb_put(skb, len);
1318
1319                 skb->protocol = eth_type_trans(skb, bp->dev);
1320                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1321
1322                 {
1323                         struct iphdr *iph;
1324
1325                         iph = (struct iphdr *)skb->data;
1326 #ifdef BCM_VLAN
1327                         /* If there is no Rx VLAN offloading -
1328                            take VLAN tag into an account */
1329                         if (unlikely(is_not_hwaccel_vlan_cqe))
1330                                 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1331 #endif
1332                         iph->check = 0;
1333                         iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1334                 }
1335
1336                 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1337                                          &cqe->fast_path_cqe, cqe_idx)) {
1338 #ifdef BCM_VLAN
1339                         if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1340                             (!is_not_hwaccel_vlan_cqe))
1341                                 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1342                                                 le16_to_cpu(cqe->fast_path_cqe.
1343                                                             vlan_tag));
1344                         else
1345 #endif
1346                                 netif_receive_skb(skb);
1347                 } else {
1348                         DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1349                            " - dropping packet!\n");
1350                         dev_kfree_skb(skb);
1351                 }
1352
1353
1354                 /* put new skb in bin */
1355                 fp->tpa_pool[queue].skb = new_skb;
1356
1357         } else {
1358                 /* else drop the packet and keep the buffer in the bin */
1359                 DP(NETIF_MSG_RX_STATUS,
1360                    "Failed to allocate new skb - dropping packet!\n");
1361                 bp->eth_stats.rx_skb_alloc_failed++;
1362         }
1363
1364         fp->tpa_state[queue] = BNX2X_TPA_STOP;
1365 }
1366
1367 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1368                                         struct bnx2x_fastpath *fp,
1369                                         u16 bd_prod, u16 rx_comp_prod,
1370                                         u16 rx_sge_prod)
1371 {
1372         struct tstorm_eth_rx_producers rx_prods = {0};
1373         int i;
1374
1375         /* Update producers */
1376         rx_prods.bd_prod = bd_prod;
1377         rx_prods.cqe_prod = rx_comp_prod;
1378         rx_prods.sge_prod = rx_sge_prod;
1379
1380         /*
1381          * Make sure that the BD and SGE data is updated before updating the
1382          * producers since FW might read the BD/SGE right after the producer
1383          * is updated.
1384          * This is only applicable for weak-ordered memory model archs such
1385          * as IA-64. The following barrier is also mandatory since FW will
1386          * assumes BDs must have buffers.
1387          */
1388         wmb();
1389
1390         for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)
1391                 REG_WR(bp, BAR_TSTRORM_INTMEM +
1392                        TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1393                        ((u32 *)&rx_prods)[i]);
1394
1395         mmiowb(); /* keep prod updates ordered */
1396
1397         DP(NETIF_MSG_RX_STATUS,
1398            "Wrote: bd_prod %u  cqe_prod %u  sge_prod %u\n",
1399            bd_prod, rx_comp_prod, rx_sge_prod);
1400 }
1401
1402 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1403 {
1404         struct bnx2x *bp = fp->bp;
1405         u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1406         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1407         int rx_pkt = 0;
1408
1409 #ifdef BNX2X_STOP_ON_ERROR
1410         if (unlikely(bp->panic))
1411                 return 0;
1412 #endif
1413
1414         /* CQ "next element" is of the size of the regular element,
1415            that's why it's ok here */
1416         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1417         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1418                 hw_comp_cons++;
1419
1420         bd_cons = fp->rx_bd_cons;
1421         bd_prod = fp->rx_bd_prod;
1422         bd_prod_fw = bd_prod;
1423         sw_comp_cons = fp->rx_comp_cons;
1424         sw_comp_prod = fp->rx_comp_prod;
1425
1426         /* Memory barrier necessary as speculative reads of the rx
1427          * buffer can be ahead of the index in the status block
1428          */
1429         rmb();
1430
1431         DP(NETIF_MSG_RX_STATUS,
1432            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
1433            FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1434
1435         while (sw_comp_cons != hw_comp_cons) {
1436                 struct sw_rx_bd *rx_buf = NULL;
1437                 struct sk_buff *skb;
1438                 union eth_rx_cqe *cqe;
1439                 u8 cqe_fp_flags;
1440                 u16 len, pad;
1441
1442                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1443                 bd_prod = RX_BD(bd_prod);
1444                 bd_cons = RX_BD(bd_cons);
1445
1446                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1447                 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1448
1449                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
1450                    "  queue %x  vlan %x  len %u\n", CQE_TYPE(cqe_fp_flags),
1451                    cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1452                    le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
1453                    le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1454                    le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1455
1456                 /* is this a slowpath msg? */
1457                 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1458                         bnx2x_sp_event(fp, cqe);
1459                         goto next_cqe;
1460
1461                 /* this is an rx packet */
1462                 } else {
1463                         rx_buf = &fp->rx_buf_ring[bd_cons];
1464                         skb = rx_buf->skb;
1465                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1466                         pad = cqe->fast_path_cqe.placement_offset;
1467
1468                         /* If CQE is marked both TPA_START and TPA_END
1469                            it is a non-TPA CQE */
1470                         if ((!fp->disable_tpa) &&
1471                             (TPA_TYPE(cqe_fp_flags) !=
1472                                         (TPA_TYPE_START | TPA_TYPE_END))) {
1473                                 u16 queue = cqe->fast_path_cqe.queue_index;
1474
1475                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1476                                         DP(NETIF_MSG_RX_STATUS,
1477                                            "calling tpa_start on queue %d\n",
1478                                            queue);
1479
1480                                         bnx2x_tpa_start(fp, queue, skb,
1481                                                         bd_cons, bd_prod);
1482                                         goto next_rx;
1483                                 }
1484
1485                                 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1486                                         DP(NETIF_MSG_RX_STATUS,
1487                                            "calling tpa_stop on queue %d\n",
1488                                            queue);
1489
1490                                         if (!BNX2X_RX_SUM_FIX(cqe))
1491                                                 BNX2X_ERR("STOP on none TCP "
1492                                                           "data\n");
1493
1494                                         /* This is a size of the linear data
1495                                            on this skb */
1496                                         len = le16_to_cpu(cqe->fast_path_cqe.
1497                                                                 len_on_bd);
1498                                         bnx2x_tpa_stop(bp, fp, queue, pad,
1499                                                     len, cqe, comp_ring_cons);
1500 #ifdef BNX2X_STOP_ON_ERROR
1501                                         if (bp->panic)
1502                                                 return -EINVAL;
1503 #endif
1504
1505                                         bnx2x_update_sge_prod(fp,
1506                                                         &cqe->fast_path_cqe);
1507                                         goto next_cqe;
1508                                 }
1509                         }
1510
1511                         pci_dma_sync_single_for_device(bp->pdev,
1512                                         pci_unmap_addr(rx_buf, mapping),
1513                                                        pad + RX_COPY_THRESH,
1514                                                        PCI_DMA_FROMDEVICE);
1515                         prefetch(skb);
1516                         prefetch(((char *)(skb)) + 128);
1517
1518                         /* is this an error packet? */
1519                         if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1520                                 DP(NETIF_MSG_RX_ERR,
1521                                    "ERROR  flags %x  rx packet %u\n",
1522                                    cqe_fp_flags, sw_comp_cons);
1523                                 bp->eth_stats.rx_err_discard_pkt++;
1524                                 goto reuse_rx;
1525                         }
1526
1527                         /* Since we don't have a jumbo ring
1528                          * copy small packets if mtu > 1500
1529                          */
1530                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1531                             (len <= RX_COPY_THRESH)) {
1532                                 struct sk_buff *new_skb;
1533
1534                                 new_skb = netdev_alloc_skb(bp->dev,
1535                                                            len + pad);
1536                                 if (new_skb == NULL) {
1537                                         DP(NETIF_MSG_RX_ERR,
1538                                            "ERROR  packet dropped "
1539                                            "because of alloc failure\n");
1540                                         bp->eth_stats.rx_skb_alloc_failed++;
1541                                         goto reuse_rx;
1542                                 }
1543
1544                                 /* aligned copy */
1545                                 skb_copy_from_linear_data_offset(skb, pad,
1546                                                     new_skb->data + pad, len);
1547                                 skb_reserve(new_skb, pad);
1548                                 skb_put(new_skb, len);
1549
1550                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1551
1552                                 skb = new_skb;
1553
1554                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1555                                 pci_unmap_single(bp->pdev,
1556                                         pci_unmap_addr(rx_buf, mapping),
1557                                                  bp->rx_buf_size,
1558                                                  PCI_DMA_FROMDEVICE);
1559                                 skb_reserve(skb, pad);
1560                                 skb_put(skb, len);
1561
1562                         } else {
1563                                 DP(NETIF_MSG_RX_ERR,
1564                                    "ERROR  packet dropped because "
1565                                    "of alloc failure\n");
1566                                 bp->eth_stats.rx_skb_alloc_failed++;
1567 reuse_rx:
1568                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1569                                 goto next_rx;
1570                         }
1571
1572                         skb->protocol = eth_type_trans(skb, bp->dev);
1573
1574                         skb->ip_summed = CHECKSUM_NONE;
1575                         if (bp->rx_csum) {
1576                                 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1577                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1578                                 else
1579                                         bp->eth_stats.hw_csum_err++;
1580                         }
1581                 }
1582
1583 #ifdef BCM_VLAN
1584                 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
1585                     (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1586                      PARSING_FLAGS_VLAN))
1587                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1588                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1589                 else
1590 #endif
1591                         netif_receive_skb(skb);
1592
1593
1594 next_rx:
1595                 rx_buf->skb = NULL;
1596
1597                 bd_cons = NEXT_RX_IDX(bd_cons);
1598                 bd_prod = NEXT_RX_IDX(bd_prod);
1599                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1600                 rx_pkt++;
1601 next_cqe:
1602                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1603                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1604
1605                 if (rx_pkt == budget)
1606                         break;
1607         } /* while */
1608
1609         fp->rx_bd_cons = bd_cons;
1610         fp->rx_bd_prod = bd_prod_fw;
1611         fp->rx_comp_cons = sw_comp_cons;
1612         fp->rx_comp_prod = sw_comp_prod;
1613
1614         /* Update producers */
1615         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1616                              fp->rx_sge_prod);
1617
1618         fp->rx_pkt += rx_pkt;
1619         fp->rx_calls++;
1620
1621         return rx_pkt;
1622 }
1623
1624 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1625 {
1626         struct bnx2x_fastpath *fp = fp_cookie;
1627         struct bnx2x *bp = fp->bp;
1628         int index = FP_IDX(fp);
1629
1630         /* Return here if interrupt is disabled */
1631         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1632                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1633                 return IRQ_HANDLED;
1634         }
1635
1636         DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1637            index, FP_SB_ID(fp));
1638         bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1639
1640 #ifdef BNX2X_STOP_ON_ERROR
1641         if (unlikely(bp->panic))
1642                 return IRQ_HANDLED;
1643 #endif
1644
1645         prefetch(fp->rx_cons_sb);
1646         prefetch(fp->tx_cons_sb);
1647         prefetch(&fp->status_blk->c_status_block.status_block_index);
1648         prefetch(&fp->status_blk->u_status_block.status_block_index);
1649
1650         netif_rx_schedule(&bnx2x_fp(bp, index, napi));
1651
1652         return IRQ_HANDLED;
1653 }
1654
1655 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1656 {
1657         struct net_device *dev = dev_instance;
1658         struct bnx2x *bp = netdev_priv(dev);
1659         u16 status = bnx2x_ack_int(bp);
1660         u16 mask;
1661
1662         /* Return here if interrupt is shared and it's not for us */
1663         if (unlikely(status == 0)) {
1664                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1665                 return IRQ_NONE;
1666         }
1667         DP(NETIF_MSG_INTR, "got an interrupt  status %u\n", status);
1668
1669         /* Return here if interrupt is disabled */
1670         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1671                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1672                 return IRQ_HANDLED;
1673         }
1674
1675 #ifdef BNX2X_STOP_ON_ERROR
1676         if (unlikely(bp->panic))
1677                 return IRQ_HANDLED;
1678 #endif
1679
1680         mask = 0x2 << bp->fp[0].sb_id;
1681         if (status & mask) {
1682                 struct bnx2x_fastpath *fp = &bp->fp[0];
1683
1684                 prefetch(fp->rx_cons_sb);
1685                 prefetch(fp->tx_cons_sb);
1686                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1687                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1688
1689                 netif_rx_schedule(&bnx2x_fp(bp, 0, napi));
1690
1691                 status &= ~mask;
1692         }
1693
1694
1695         if (unlikely(status & 0x1)) {
1696                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1697
1698                 status &= ~0x1;
1699                 if (!status)
1700                         return IRQ_HANDLED;
1701         }
1702
1703         if (status)
1704                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1705                    status);
1706
1707         return IRQ_HANDLED;
1708 }
1709
1710 /* end of fast path */
1711
1712 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1713
1714 /* Link */
1715
1716 /*
1717  * General service functions
1718  */
1719
1720 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1721 {
1722         u32 lock_status;
1723         u32 resource_bit = (1 << resource);
1724         int func = BP_FUNC(bp);
1725         u32 hw_lock_control_reg;
1726         int cnt;
1727
1728         /* Validating that the resource is within range */
1729         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1730                 DP(NETIF_MSG_HW,
1731                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1732                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1733                 return -EINVAL;
1734         }
1735
1736         if (func <= 5) {
1737                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1738         } else {
1739                 hw_lock_control_reg =
1740                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1741         }
1742
1743         /* Validating that the resource is not already taken */
1744         lock_status = REG_RD(bp, hw_lock_control_reg);
1745         if (lock_status & resource_bit) {
1746                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1747                    lock_status, resource_bit);
1748                 return -EEXIST;
1749         }
1750
1751         /* Try for 5 second every 5ms */
1752         for (cnt = 0; cnt < 1000; cnt++) {
1753                 /* Try to acquire the lock */
1754                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1755                 lock_status = REG_RD(bp, hw_lock_control_reg);
1756                 if (lock_status & resource_bit)
1757                         return 0;
1758
1759                 msleep(5);
1760         }
1761         DP(NETIF_MSG_HW, "Timeout\n");
1762         return -EAGAIN;
1763 }
1764
1765 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1766 {
1767         u32 lock_status;
1768         u32 resource_bit = (1 << resource);
1769         int func = BP_FUNC(bp);
1770         u32 hw_lock_control_reg;
1771
1772         /* Validating that the resource is within range */
1773         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1774                 DP(NETIF_MSG_HW,
1775                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1776                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1777                 return -EINVAL;
1778         }
1779
1780         if (func <= 5) {
1781                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1782         } else {
1783                 hw_lock_control_reg =
1784                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1785         }
1786
1787         /* Validating that the resource is currently taken */
1788         lock_status = REG_RD(bp, hw_lock_control_reg);
1789         if (!(lock_status & resource_bit)) {
1790                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1791                    lock_status, resource_bit);
1792                 return -EFAULT;
1793         }
1794
1795         REG_WR(bp, hw_lock_control_reg, resource_bit);
1796         return 0;
1797 }
1798
1799 /* HW Lock for shared dual port PHYs */
1800 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1801 {
1802         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1803
1804         mutex_lock(&bp->port.phy_mutex);
1805
1806         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1807             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1808                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1809 }
1810
1811 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1812 {
1813         u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1814
1815         if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1816             (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1817                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1818
1819         mutex_unlock(&bp->port.phy_mutex);
1820 }
1821
1822 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1823 {
1824         /* The GPIO should be swapped if swap register is set and active */
1825         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1826                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1827         int gpio_shift = gpio_num +
1828                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1829         u32 gpio_mask = (1 << gpio_shift);
1830         u32 gpio_reg;
1831
1832         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1833                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1834                 return -EINVAL;
1835         }
1836
1837         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1838         /* read GPIO and mask except the float bits */
1839         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1840
1841         switch (mode) {
1842         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1843                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1844                    gpio_num, gpio_shift);
1845                 /* clear FLOAT and set CLR */
1846                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1847                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1848                 break;
1849
1850         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1851                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1852                    gpio_num, gpio_shift);
1853                 /* clear FLOAT and set SET */
1854                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1855                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1856                 break;
1857
1858         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1859                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1860                    gpio_num, gpio_shift);
1861                 /* set FLOAT */
1862                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1863                 break;
1864
1865         default:
1866                 break;
1867         }
1868
1869         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1870         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1871
1872         return 0;
1873 }
1874
1875 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1876 {
1877         u32 spio_mask = (1 << spio_num);
1878         u32 spio_reg;
1879
1880         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1881             (spio_num > MISC_REGISTERS_SPIO_7)) {
1882                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1883                 return -EINVAL;
1884         }
1885
1886         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1887         /* read SPIO and mask except the float bits */
1888         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1889
1890         switch (mode) {
1891         case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1892                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1893                 /* clear FLOAT and set CLR */
1894                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1895                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1896                 break;
1897
1898         case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1899                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1900                 /* clear FLOAT and set SET */
1901                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1902                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1903                 break;
1904
1905         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1906                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1907                 /* set FLOAT */
1908                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1909                 break;
1910
1911         default:
1912                 break;
1913         }
1914
1915         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1916         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1917
1918         return 0;
1919 }
1920
1921 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1922 {
1923         switch (bp->link_vars.ieee_fc &
1924                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1925         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1926                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1927                                           ADVERTISED_Pause);
1928                 break;
1929         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1930                 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1931                                          ADVERTISED_Pause);
1932                 break;
1933         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1934                 bp->port.advertising |= ADVERTISED_Asym_Pause;
1935                 break;
1936         default:
1937                 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1938                                           ADVERTISED_Pause);
1939                 break;
1940         }
1941 }
1942
1943 static void bnx2x_link_report(struct bnx2x *bp)
1944 {
1945         if (bp->link_vars.link_up) {
1946                 if (bp->state == BNX2X_STATE_OPEN)
1947                         netif_carrier_on(bp->dev);
1948                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1949
1950                 printk("%d Mbps ", bp->link_vars.line_speed);
1951
1952                 if (bp->link_vars.duplex == DUPLEX_FULL)
1953                         printk("full duplex");
1954                 else
1955                         printk("half duplex");
1956
1957                 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
1958                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
1959                                 printk(", receive ");
1960                                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1961                                         printk("& transmit ");
1962                         } else {
1963                                 printk(", transmit ");
1964                         }
1965                         printk("flow control ON");
1966                 }
1967                 printk("\n");
1968
1969         } else { /* link_down */
1970                 netif_carrier_off(bp->dev);
1971                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1972         }
1973 }
1974
1975 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1976 {
1977         if (!BP_NOMCP(bp)) {
1978                 u8 rc;
1979
1980                 /* Initialize link parameters structure variables */
1981                 /* It is recommended to turn off RX FC for jumbo frames
1982                    for better performance */
1983                 if (IS_E1HMF(bp))
1984                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1985                 else if (bp->dev->mtu > 5000)
1986                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1987                 else
1988                         bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1989
1990                 bnx2x_acquire_phy_lock(bp);
1991                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1992                 bnx2x_release_phy_lock(bp);
1993
1994                 bnx2x_calc_fc_adv(bp);
1995
1996                 if (bp->link_vars.link_up)
1997                         bnx2x_link_report(bp);
1998
1999
2000                 return rc;
2001         }
2002         BNX2X_ERR("Bootcode is missing -not initializing link\n");
2003         return -EINVAL;
2004 }
2005
2006 static void bnx2x_link_set(struct bnx2x *bp)
2007 {
2008         if (!BP_NOMCP(bp)) {
2009                 bnx2x_acquire_phy_lock(bp);
2010                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2011                 bnx2x_release_phy_lock(bp);
2012
2013                 bnx2x_calc_fc_adv(bp);
2014         } else
2015                 BNX2X_ERR("Bootcode is missing -not setting link\n");
2016 }
2017
2018 static void bnx2x__link_reset(struct bnx2x *bp)
2019 {
2020         if (!BP_NOMCP(bp)) {
2021                 bnx2x_acquire_phy_lock(bp);
2022                 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
2023                 bnx2x_release_phy_lock(bp);
2024         } else
2025                 BNX2X_ERR("Bootcode is missing -not resetting link\n");
2026 }
2027
2028 static u8 bnx2x_link_test(struct bnx2x *bp)
2029 {
2030         u8 rc;
2031
2032         bnx2x_acquire_phy_lock(bp);
2033         rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2034         bnx2x_release_phy_lock(bp);
2035
2036         return rc;
2037 }
2038
2039 /* Calculates the sum of vn_min_rates.
2040    It's needed for further normalizing of the min_rates.
2041
2042    Returns:
2043      sum of vn_min_rates
2044        or
2045      0 - if all the min_rates are 0.
2046      In the later case fairness algorithm should be deactivated.
2047      If not all min_rates are zero then those that are zeroes will
2048      be set to 1.
2049  */
2050 static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
2051 {
2052         int i, port = BP_PORT(bp);
2053         u32 wsum = 0;
2054         int all_zero = 1;
2055
2056         for (i = 0; i < E1HVN_MAX; i++) {
2057                 u32 vn_cfg =
2058                         SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2059                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2060                                      FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2061                 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2062                         /* If min rate is zero - set it to 1 */
2063                         if (!vn_min_rate)
2064                                 vn_min_rate = DEF_MIN_RATE;
2065                         else
2066                                 all_zero = 0;
2067
2068                         wsum += vn_min_rate;
2069                 }
2070         }
2071
2072         /* ... only if all min rates are zeros - disable FAIRNESS */
2073         if (all_zero)
2074                 return 0;
2075
2076         return wsum;
2077 }
2078
2079 static void bnx2x_init_port_minmax(struct bnx2x *bp,
2080                                    int en_fness,
2081                                    u16 port_rate,
2082                                    struct cmng_struct_per_port *m_cmng_port)
2083 {
2084         u32 r_param = port_rate / 8;
2085         int port = BP_PORT(bp);
2086         int i;
2087
2088         memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2089
2090         /* Enable minmax only if we are in e1hmf mode */
2091         if (IS_E1HMF(bp)) {
2092                 u32 fair_periodic_timeout_usec;
2093                 u32 t_fair;
2094
2095                 /* Enable rate shaping and fairness */
2096                 m_cmng_port->flags.cmng_vn_enable = 1;
2097                 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2098                 m_cmng_port->flags.rate_shaping_enable = 1;
2099
2100                 if (!en_fness)
2101                         DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2102                            "  fairness will be disabled\n");
2103
2104                 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2105                 m_cmng_port->rs_vars.rs_periodic_timeout =
2106                                                 RS_PERIODIC_TIMEOUT_USEC / 4;
2107
2108                 /* this is the threshold below which no timer arming will occur
2109                    1.25 coefficient is for the threshold to be a little bigger
2110                    than the real time, to compensate for timer in-accuracy */
2111                 m_cmng_port->rs_vars.rs_threshold =
2112                                 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2113
2114                 /* resolution of fairness timer */
2115                 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2116                 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2117                 t_fair = T_FAIR_COEF / port_rate;
2118
2119                 /* this is the threshold below which we won't arm
2120                    the timer anymore */
2121                 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2122
2123                 /* we multiply by 1e3/8 to get bytes/msec.
2124                    We don't want the credits to pass a credit
2125                    of the T_FAIR*FAIR_MEM (algorithm resolution) */
2126                 m_cmng_port->fair_vars.upper_bound =
2127                                                 r_param * t_fair * FAIR_MEM;
2128                 /* since each tick is 4 usec */
2129                 m_cmng_port->fair_vars.fairness_timeout =
2130                                                 fair_periodic_timeout_usec / 4;
2131
2132         } else {
2133                 /* Disable rate shaping and fairness */
2134                 m_cmng_port->flags.cmng_vn_enable = 0;
2135                 m_cmng_port->flags.fairness_enable = 0;
2136                 m_cmng_port->flags.rate_shaping_enable = 0;
2137
2138                 DP(NETIF_MSG_IFUP,
2139                    "Single function mode  minmax will be disabled\n");
2140         }
2141
2142         /* Store it to internal memory */
2143         for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2144                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2145                        XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2146                        ((u32 *)(m_cmng_port))[i]);
2147 }
2148
2149 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2150                                    u32 wsum, u16 port_rate,
2151                                  struct cmng_struct_per_port *m_cmng_port)
2152 {
2153         struct rate_shaping_vars_per_vn m_rs_vn;
2154         struct fairness_vars_per_vn m_fair_vn;
2155         u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2156         u16 vn_min_rate, vn_max_rate;
2157         int i;
2158
2159         /* If function is hidden - set min and max to zeroes */
2160         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2161                 vn_min_rate = 0;
2162                 vn_max_rate = 0;
2163
2164         } else {
2165                 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2166                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2167                 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2168                    if current min rate is zero - set it to 1.
2169                    This is a requirement of the algorithm. */
2170                 if ((vn_min_rate == 0) && wsum)
2171                         vn_min_rate = DEF_MIN_RATE;
2172                 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2173                                 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2174         }
2175
2176         DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d  vn_max_rate=%d  "
2177            "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2178
2179         memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2180         memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2181
2182         /* global vn counter - maximal Mbps for this vn */
2183         m_rs_vn.vn_counter.rate = vn_max_rate;
2184
2185         /* quota - number of bytes transmitted in this period */
2186         m_rs_vn.vn_counter.quota =
2187                                 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2188
2189 #ifdef BNX2X_PER_PROT_QOS
2190         /* per protocol counter */
2191         for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2192                 /* maximal Mbps for this protocol */
2193                 m_rs_vn.protocol_counters[protocol].rate =
2194                                                 protocol_max_rate[protocol];
2195                 /* the quota in each timer period -
2196                    number of bytes transmitted in this period */
2197                 m_rs_vn.protocol_counters[protocol].quota =
2198                         (u32)(rs_periodic_timeout_usec *
2199                           ((double)m_rs_vn.
2200                                    protocol_counters[protocol].rate/8));
2201         }
2202 #endif
2203
2204         if (wsum) {
2205                 /* credit for each period of the fairness algorithm:
2206                    number of bytes in T_FAIR (the vn share the port rate).
2207                    wsum should not be larger than 10000, thus
2208                    T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2209                 m_fair_vn.vn_credit_delta =
2210                         max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2211                             (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2212                 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2213                    m_fair_vn.vn_credit_delta);
2214         }
2215
2216 #ifdef BNX2X_PER_PROT_QOS
2217         do {
2218                 u32 protocolWeightSum = 0;
2219
2220                 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2221                         protocolWeightSum +=
2222                                         drvInit.protocol_min_rate[protocol];
2223                 /* per protocol counter -
2224                    NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2225                 if (protocolWeightSum > 0) {
2226                         for (protocol = 0;
2227                              protocol < NUM_OF_PROTOCOLS; protocol++)
2228                                 /* credit for each period of the
2229                                    fairness algorithm - number of bytes in
2230                                    T_FAIR (the protocol share the vn rate) */
2231                                 m_fair_vn.protocol_credit_delta[protocol] =
2232                                         (u32)((vn_min_rate / 8) * t_fair *
2233                                         protocol_min_rate / protocolWeightSum);
2234                 }
2235         } while (0);
2236 #endif
2237
2238         /* Store it to internal memory */
2239         for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2240                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2241                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2242                        ((u32 *)(&m_rs_vn))[i]);
2243
2244         for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2245                 REG_WR(bp, BAR_XSTRORM_INTMEM +
2246                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2247                        ((u32 *)(&m_fair_vn))[i]);
2248 }
2249
2250 /* This function is called upon link interrupt */
2251 static void bnx2x_link_attn(struct bnx2x *bp)
2252 {
2253         int vn;
2254
2255         /* Make sure that we are synced with the current statistics */
2256         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2257
2258         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2259
2260         if (bp->link_vars.link_up) {
2261
2262                 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2263                         struct host_port_stats *pstats;
2264
2265                         pstats = bnx2x_sp(bp, port_stats);
2266                         /* reset old bmac stats */
2267                         memset(&(pstats->mac_stx[0]), 0,
2268                                sizeof(struct mac_stx));
2269                 }
2270                 if ((bp->state == BNX2X_STATE_OPEN) ||
2271                     (bp->state == BNX2X_STATE_DISABLED))
2272                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2273         }
2274
2275         /* indicate link status */
2276         bnx2x_link_report(bp);
2277
2278         if (IS_E1HMF(bp)) {
2279                 int func;
2280
2281                 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2282                         if (vn == BP_E1HVN(bp))
2283                                 continue;
2284
2285                         func = ((vn << 1) | BP_PORT(bp));
2286
2287                         /* Set the attention towards other drivers
2288                            on the same port */
2289                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2290                                (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2291                 }
2292         }
2293
2294         if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2295                 struct cmng_struct_per_port m_cmng_port;
2296                 u32 wsum;
2297                 int port = BP_PORT(bp);
2298
2299                 /* Init RATE SHAPING and FAIRNESS contexts */
2300                 wsum = bnx2x_calc_vn_wsum(bp);
2301                 bnx2x_init_port_minmax(bp, (int)wsum,
2302                                         bp->link_vars.line_speed,
2303                                         &m_cmng_port);
2304                 if (IS_E1HMF(bp))
2305                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
2306                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
2307                                         wsum, bp->link_vars.line_speed,
2308                                                      &m_cmng_port);
2309         }
2310 }
2311
2312 static void bnx2x__link_status_update(struct bnx2x *bp)
2313 {
2314         if (bp->state != BNX2X_STATE_OPEN)
2315                 return;
2316
2317         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2318
2319         if (bp->link_vars.link_up)
2320                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2321         else
2322                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2323
2324         /* indicate link status */
2325         bnx2x_link_report(bp);
2326 }
2327
2328 static void bnx2x_pmf_update(struct bnx2x *bp)
2329 {
2330         int port = BP_PORT(bp);
2331         u32 val;
2332
2333         bp->port.pmf = 1;
2334         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2335
2336         /* enable nig attention */
2337         val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2338         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2339         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2340
2341         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2342 }
2343
2344 /* end of Link */
2345
2346 /* slow path */
2347
2348 /*
2349  * General service functions
2350  */
2351
2352 /* the slow path queue is odd since completions arrive on the fastpath ring */
2353 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2354                          u32 data_hi, u32 data_lo, int common)
2355 {
2356         int func = BP_FUNC(bp);
2357
2358         DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2359            "SPQE (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
2360            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2361            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2362            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2363
2364 #ifdef BNX2X_STOP_ON_ERROR
2365         if (unlikely(bp->panic))
2366                 return -EIO;
2367 #endif
2368
2369         spin_lock_bh(&bp->spq_lock);
2370
2371         if (!bp->spq_left) {
2372                 BNX2X_ERR("BUG! SPQ ring full!\n");
2373                 spin_unlock_bh(&bp->spq_lock);
2374                 bnx2x_panic();
2375                 return -EBUSY;
2376         }
2377
2378         /* CID needs port number to be encoded int it */
2379         bp->spq_prod_bd->hdr.conn_and_cmd_data =
2380                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2381                                      HW_CID(bp, cid)));
2382         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2383         if (common)
2384                 bp->spq_prod_bd->hdr.type |=
2385                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2386
2387         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2388         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2389
2390         bp->spq_left--;
2391
2392         if (bp->spq_prod_bd == bp->spq_last_bd) {
2393                 bp->spq_prod_bd = bp->spq;
2394                 bp->spq_prod_idx = 0;
2395                 DP(NETIF_MSG_TIMER, "end of spq\n");
2396
2397         } else {
2398                 bp->spq_prod_bd++;
2399                 bp->spq_prod_idx++;
2400         }
2401
2402         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2403                bp->spq_prod_idx);
2404
2405         spin_unlock_bh(&bp->spq_lock);
2406         return 0;
2407 }
2408
2409 /* acquire split MCP access lock register */
2410 static int bnx2x_acquire_alr(struct bnx2x *bp)
2411 {
2412         u32 i, j, val;
2413         int rc = 0;
2414
2415         might_sleep();
2416         i = 100;
2417         for (j = 0; j < i*10; j++) {
2418                 val = (1UL << 31);
2419                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2420                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2421                 if (val & (1L << 31))
2422                         break;
2423
2424                 msleep(5);
2425         }
2426         if (!(val & (1L << 31))) {
2427                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2428                 rc = -EBUSY;
2429         }
2430
2431         return rc;
2432 }
2433
2434 /* release split MCP access lock register */
2435 static void bnx2x_release_alr(struct bnx2x *bp)
2436 {
2437         u32 val = 0;
2438
2439         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2440 }
2441
2442 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2443 {
2444         struct host_def_status_block *def_sb = bp->def_status_blk;
2445         u16 rc = 0;
2446
2447         barrier(); /* status block is written to by the chip */
2448         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2449                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2450                 rc |= 1;
2451         }
2452         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2453                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2454                 rc |= 2;
2455         }
2456         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2457                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2458                 rc |= 4;
2459         }
2460         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2461                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2462                 rc |= 8;
2463         }
2464         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2465                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2466                 rc |= 16;
2467         }
2468         return rc;
2469 }
2470
2471 /*
2472  * slow path service functions
2473  */
2474
2475 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2476 {
2477         int port = BP_PORT(bp);
2478         u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2479                        COMMAND_REG_ATTN_BITS_SET);
2480         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2481                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
2482         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2483                                        NIG_REG_MASK_INTERRUPT_PORT0;
2484         u32 aeu_mask;
2485
2486         if (bp->attn_state & asserted)
2487                 BNX2X_ERR("IGU ERROR\n");
2488
2489         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2490         aeu_mask = REG_RD(bp, aeu_addr);
2491
2492         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
2493            aeu_mask, asserted);
2494         aeu_mask &= ~(asserted & 0xff);
2495         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2496
2497         REG_WR(bp, aeu_addr, aeu_mask);
2498         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2499
2500         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2501         bp->attn_state |= asserted;
2502         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2503
2504         if (asserted & ATTN_HARD_WIRED_MASK) {
2505                 if (asserted & ATTN_NIG_FOR_FUNC) {
2506
2507                         bnx2x_acquire_phy_lock(bp);
2508
2509                         /* save nig interrupt mask */
2510                         bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2511                         REG_WR(bp, nig_int_mask_addr, 0);
2512
2513                         bnx2x_link_attn(bp);
2514
2515                         /* handle unicore attn? */
2516                 }
2517                 if (asserted & ATTN_SW_TIMER_4_FUNC)
2518                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2519
2520                 if (asserted & GPIO_2_FUNC)
2521                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2522
2523                 if (asserted & GPIO_3_FUNC)
2524                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2525
2526                 if (asserted & GPIO_4_FUNC)
2527                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2528
2529                 if (port == 0) {
2530                         if (asserted & ATTN_GENERAL_ATTN_1) {
2531                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2532                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2533                         }
2534                         if (asserted & ATTN_GENERAL_ATTN_2) {
2535                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2536                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2537                         }
2538                         if (asserted & ATTN_GENERAL_ATTN_3) {
2539                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2540                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2541                         }
2542                 } else {
2543                         if (asserted & ATTN_GENERAL_ATTN_4) {
2544                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2545                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2546                         }
2547                         if (asserted & ATTN_GENERAL_ATTN_5) {
2548                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2549                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2550                         }
2551                         if (asserted & ATTN_GENERAL_ATTN_6) {
2552                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2553                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2554                         }
2555                 }
2556
2557         } /* if hardwired */
2558
2559         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2560            asserted, hc_addr);
2561         REG_WR(bp, hc_addr, asserted);
2562
2563         /* now set back the mask */
2564         if (asserted & ATTN_NIG_FOR_FUNC) {
2565                 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2566                 bnx2x_release_phy_lock(bp);
2567         }
2568 }
2569
2570 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2571 {
2572         int port = BP_PORT(bp);
2573         int reg_offset;
2574         u32 val;
2575
2576         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2577                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2578
2579         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2580
2581                 val = REG_RD(bp, reg_offset);
2582                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2583                 REG_WR(bp, reg_offset, val);
2584
2585                 BNX2X_ERR("SPIO5 hw attention\n");
2586
2587                 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2588                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
2589                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2590                         /* Fan failure attention */
2591
2592                         /* The PHY reset is controlled by GPIO 1 */
2593                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2594                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2595                         /* Low power mode is controlled by GPIO 2 */
2596                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2597                                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2598                         /* mark the failure */
2599                         bp->link_params.ext_phy_config &=
2600                                         ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2601                         bp->link_params.ext_phy_config |=
2602                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2603                         SHMEM_WR(bp,
2604                                  dev_info.port_hw_config[port].
2605                                                         external_phy_config,
2606                                  bp->link_params.ext_phy_config);
2607                         /* log the failure */
2608                         printk(KERN_ERR PFX "Fan Failure on Network"
2609                                " Controller %s has caused the driver to"
2610                                " shutdown the card to prevent permanent"
2611                                " damage.  Please contact Dell Support for"
2612                                " assistance\n", bp->dev->name);
2613                         break;
2614
2615                 default:
2616                         break;
2617                 }
2618         }
2619
2620         if (attn & HW_INTERRUT_ASSERT_SET_0) {
2621
2622                 val = REG_RD(bp, reg_offset);
2623                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2624                 REG_WR(bp, reg_offset, val);
2625
2626                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2627                           (attn & HW_INTERRUT_ASSERT_SET_0));
2628                 bnx2x_panic();
2629         }
2630 }
2631
2632 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2633 {
2634         u32 val;
2635
2636         if (attn & BNX2X_DOORQ_ASSERT) {
2637
2638                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2639                 BNX2X_ERR("DB hw attention 0x%x\n", val);
2640                 /* DORQ discard attention */
2641                 if (val & 0x2)
2642                         BNX2X_ERR("FATAL error from DORQ\n");
2643         }
2644
2645         if (attn & HW_INTERRUT_ASSERT_SET_1) {
2646
2647                 int port = BP_PORT(bp);
2648                 int reg_offset;
2649
2650                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2651                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2652
2653                 val = REG_RD(bp, reg_offset);
2654                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2655                 REG_WR(bp, reg_offset, val);
2656
2657                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2658                           (attn & HW_INTERRUT_ASSERT_SET_1));
2659                 bnx2x_panic();
2660         }
2661 }
2662
2663 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2664 {
2665         u32 val;
2666
2667         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2668
2669                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2670                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2671                 /* CFC error attention */
2672                 if (val & 0x2)
2673                         BNX2X_ERR("FATAL error from CFC\n");
2674         }
2675
2676         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2677
2678                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2679                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2680                 /* RQ_USDMDP_FIFO_OVERFLOW */
2681                 if (val & 0x18000)
2682                         BNX2X_ERR("FATAL error from PXP\n");
2683         }
2684
2685         if (attn & HW_INTERRUT_ASSERT_SET_2) {
2686
2687                 int port = BP_PORT(bp);
2688                 int reg_offset;
2689
2690                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2691                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2692
2693                 val = REG_RD(bp, reg_offset);
2694                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2695                 REG_WR(bp, reg_offset, val);
2696
2697                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2698                           (attn & HW_INTERRUT_ASSERT_SET_2));
2699                 bnx2x_panic();
2700         }
2701 }
2702
2703 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2704 {
2705         u32 val;
2706
2707         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2708
2709                 if (attn & BNX2X_PMF_LINK_ASSERT) {
2710                         int func = BP_FUNC(bp);
2711
2712                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2713                         bnx2x__link_status_update(bp);
2714                         if (SHMEM_RD(bp, func_mb[func].drv_status) &
2715                                                         DRV_STATUS_PMF)
2716                                 bnx2x_pmf_update(bp);
2717
2718                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2719
2720                         BNX2X_ERR("MC assert!\n");
2721                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2722                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2723                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2724                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2725                         bnx2x_panic();
2726
2727                 } else if (attn & BNX2X_MCP_ASSERT) {
2728
2729                         BNX2X_ERR("MCP assert!\n");
2730                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2731                         bnx2x_fw_dump(bp);
2732
2733                 } else
2734                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2735         }
2736
2737         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2738                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2739                 if (attn & BNX2X_GRC_TIMEOUT) {
2740                         val = CHIP_IS_E1H(bp) ?
2741                                 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2742                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
2743                 }
2744                 if (attn & BNX2X_GRC_RSV) {
2745                         val = CHIP_IS_E1H(bp) ?
2746                                 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2747                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
2748                 }
2749                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2750         }
2751 }
2752
2753 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2754 {
2755         struct attn_route attn;
2756         struct attn_route group_mask;
2757         int port = BP_PORT(bp);
2758         int index;
2759         u32 reg_addr;
2760         u32 val;
2761         u32 aeu_mask;
2762
2763         /* need to take HW lock because MCP or other port might also
2764            try to handle this event */
2765         bnx2x_acquire_alr(bp);
2766
2767         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2768         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2769         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2770         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2771         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2772            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2773
2774         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2775                 if (deasserted & (1 << index)) {
2776                         group_mask = bp->attn_group[index];
2777
2778                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2779                            index, group_mask.sig[0], group_mask.sig[1],
2780                            group_mask.sig[2], group_mask.sig[3]);
2781
2782                         bnx2x_attn_int_deasserted3(bp,
2783                                         attn.sig[3] & group_mask.sig[3]);
2784                         bnx2x_attn_int_deasserted1(bp,
2785                                         attn.sig[1] & group_mask.sig[1]);
2786                         bnx2x_attn_int_deasserted2(bp,
2787                                         attn.sig[2] & group_mask.sig[2]);
2788                         bnx2x_attn_int_deasserted0(bp,
2789                                         attn.sig[0] & group_mask.sig[0]);
2790
2791                         if ((attn.sig[0] & group_mask.sig[0] &
2792                                                 HW_PRTY_ASSERT_SET_0) ||
2793                             (attn.sig[1] & group_mask.sig[1] &
2794                                                 HW_PRTY_ASSERT_SET_1) ||
2795                             (attn.sig[2] & group_mask.sig[2] &
2796                                                 HW_PRTY_ASSERT_SET_2))
2797                                 BNX2X_ERR("FATAL HW block parity attention\n");
2798                 }
2799         }
2800
2801         bnx2x_release_alr(bp);
2802
2803         reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2804
2805         val = ~deasserted;
2806         DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2807            val, reg_addr);
2808         REG_WR(bp, reg_addr, val);
2809
2810         if (~bp->attn_state & deasserted)
2811                 BNX2X_ERR("IGU ERROR\n");
2812
2813         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2814                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
2815
2816         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2817         aeu_mask = REG_RD(bp, reg_addr);
2818
2819         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
2820            aeu_mask, deasserted);
2821         aeu_mask |= (deasserted & 0xff);
2822         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2823
2824         REG_WR(bp, reg_addr, aeu_mask);
2825         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2826
2827         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2828         bp->attn_state &= ~deasserted;
2829         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2830 }
2831
2832 static void bnx2x_attn_int(struct bnx2x *bp)
2833 {
2834         /* read local copy of bits */
2835         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
2836                                                                 attn_bits);
2837         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
2838                                                                 attn_bits_ack);
2839         u32 attn_state = bp->attn_state;
2840
2841         /* look for changed bits */
2842         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
2843         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
2844
2845         DP(NETIF_MSG_HW,
2846            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
2847            attn_bits, attn_ack, asserted, deasserted);
2848
2849         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2850                 BNX2X_ERR("BAD attention state\n");
2851
2852         /* handle bits that were raised */
2853         if (asserted)
2854                 bnx2x_attn_int_asserted(bp, asserted);
2855
2856         if (deasserted)
2857                 bnx2x_attn_int_deasserted(bp, deasserted);
2858 }
2859
2860 static void bnx2x_sp_task(struct work_struct *work)
2861 {
2862         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
2863         u16 status;
2864
2865
2866         /* Return here if interrupt is disabled */
2867         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2868                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2869                 return;
2870         }
2871
2872         status = bnx2x_update_dsb_idx(bp);
2873 /*      if (status == 0)                                     */
2874 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
2875
2876         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
2877
2878         /* HW attentions */
2879         if (status & 0x1)
2880                 bnx2x_attn_int(bp);
2881
2882         /* CStorm events: query_stats, port delete ramrod */
2883         if (status & 0x2)
2884                 bp->stats_pending = 0;
2885
2886         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
2887                      IGU_INT_NOP, 1);
2888         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2889                      IGU_INT_NOP, 1);
2890         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2891                      IGU_INT_NOP, 1);
2892         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2893                      IGU_INT_NOP, 1);
2894         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2895                      IGU_INT_ENABLE, 1);
2896
2897 }
2898
2899 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2900 {
2901         struct net_device *dev = dev_instance;
2902         struct bnx2x *bp = netdev_priv(dev);
2903
2904         /* Return here if interrupt is disabled */
2905         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2906                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
2907                 return IRQ_HANDLED;
2908         }
2909
2910         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
2911
2912 #ifdef BNX2X_STOP_ON_ERROR
2913         if (unlikely(bp->panic))
2914                 return IRQ_HANDLED;
2915 #endif
2916
2917         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
2918
2919         return IRQ_HANDLED;
2920 }
2921
2922 /* end of slow path */
2923
2924 /* Statistics */
2925
2926 /****************************************************************************
2927 * Macros
2928 ****************************************************************************/
2929
2930 /* sum[hi:lo] += add[hi:lo] */
2931 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2932         do { \
2933                 s_lo += a_lo; \
2934                 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
2935         } while (0)
2936
2937 /* difference = minuend - subtrahend */
2938 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2939         do { \
2940                 if (m_lo < s_lo) { \
2941                         /* underflow */ \
2942                         d_hi = m_hi - s_hi; \
2943                         if (d_hi > 0) { \
2944                                 /* we can 'loan' 1 */ \
2945                                 d_hi--; \
2946                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2947                         } else { \
2948                                 /* m_hi <= s_hi */ \
2949                                 d_hi = 0; \
2950                                 d_lo = 0; \
2951                         } \
2952                 } else { \
2953                         /* m_lo >= s_lo */ \
2954                         if (m_hi < s_hi) { \
2955                                 d_hi = 0; \
2956                                 d_lo = 0; \
2957                         } else { \
2958                                 /* m_hi >= s_hi */ \
2959                                 d_hi = m_hi - s_hi; \
2960                                 d_lo = m_lo - s_lo; \
2961                         } \
2962                 } \
2963         } while (0)
2964
2965 #define UPDATE_STAT64(s, t) \
2966         do { \
2967                 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2968                         diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2969                 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2970                 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2971                 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2972                        pstats->mac_stx[1].t##_lo, diff.lo); \
2973         } while (0)
2974
2975 #define UPDATE_STAT64_NIG(s, t) \
2976         do { \
2977                 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2978                         diff.lo, new->s##_lo, old->s##_lo); \
2979                 ADD_64(estats->t##_hi, diff.hi, \
2980                        estats->t##_lo, diff.lo); \
2981         } while (0)
2982
2983 /* sum[hi:lo] += add */
2984 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2985         do { \
2986                 s_lo += a; \
2987                 s_hi += (s_lo < a) ? 1 : 0; \
2988         } while (0)
2989
2990 #define UPDATE_EXTEND_STAT(s) \
2991         do { \
2992                 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
2993                               pstats->mac_stx[1].s##_lo, \
2994                               new->s); \
2995         } while (0)
2996
2997 #define UPDATE_EXTEND_TSTAT(s, t) \
2998         do { \
2999                 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
3000                 old_tclient->s = le32_to_cpu(tclient->s); \
3001                 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
3002         } while (0)
3003
3004 #define UPDATE_EXTEND_XSTAT(s, t) \
3005         do { \
3006                 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
3007                 old_xclient->s = le32_to_cpu(xclient->s); \
3008                 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
3009         } while (0)
3010
3011 /*
3012  * General service functions
3013  */
3014
3015 static inline long bnx2x_hilo(u32 *hiref)
3016 {
3017         u32 lo = *(hiref + 1);
3018 #if (BITS_PER_LONG == 64)
3019         u32 hi = *hiref;
3020
3021         return HILO_U64(hi, lo);
3022 #else
3023         return lo;
3024 #endif
3025 }
3026
3027 /*
3028  * Init service functions
3029  */
3030
3031 static void bnx2x_storm_stats_post(struct bnx2x *bp)
3032 {
3033         if (!bp->stats_pending) {
3034                 struct eth_query_ramrod_data ramrod_data = {0};
3035                 int rc;
3036
3037                 ramrod_data.drv_counter = bp->stats_counter++;
3038                 ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;
3039                 ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
3040
3041                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3042                                    ((u32 *)&ramrod_data)[1],
3043                                    ((u32 *)&ramrod_data)[0], 0);
3044                 if (rc == 0) {
3045                         /* stats ramrod has it's own slot on the spq */
3046                         bp->spq_left++;
3047                         bp->stats_pending = 1;
3048                 }
3049         }
3050 }
3051
3052 static void bnx2x_stats_init(struct bnx2x *bp)
3053 {
3054         int port = BP_PORT(bp);
3055
3056         bp->executer_idx = 0;
3057         bp->stats_counter = 0;
3058
3059         /* port stats */
3060         if (!BP_NOMCP(bp))
3061                 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3062         else
3063                 bp->port.port_stx = 0;
3064         DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3065
3066         memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3067         bp->port.old_nig_stats.brb_discard =
3068                         REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3069         bp->port.old_nig_stats.brb_truncate =
3070                         REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3071         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3072                     &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3073         REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3074                     &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3075
3076         /* function stats */
3077         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3078         memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3079         memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats));
3080         memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3081
3082         bp->stats_state = STATS_STATE_DISABLED;
3083         if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3084                 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3085 }
3086
3087 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3088 {
3089         struct dmae_command *dmae = &bp->stats_dmae;
3090         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3091
3092         *stats_comp = DMAE_COMP_VAL;
3093
3094         /* loader */
3095         if (bp->executer_idx) {
3096                 int loader_idx = PMF_DMAE_C(bp);
3097
3098                 memset(dmae, 0, sizeof(struct dmae_command));
3099
3100                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3101                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3102                                 DMAE_CMD_DST_RESET |
3103 #ifdef __BIG_ENDIAN
3104                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3105 #else
3106                                 DMAE_CMD_ENDIANITY_DW_SWAP |
3107 #endif
3108                                 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3109                                                DMAE_CMD_PORT_0) |
3110                                 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3111                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3112                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3113                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3114                                      sizeof(struct dmae_command) *
3115                                      (loader_idx + 1)) >> 2;
3116                 dmae->dst_addr_hi = 0;
3117                 dmae->len = sizeof(struct dmae_command) >> 2;
3118                 if (CHIP_IS_E1(bp))
3119                         dmae->len--;
3120                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3121                 dmae->comp_addr_hi = 0;
3122                 dmae->comp_val = 1;
3123
3124                 *stats_comp = 0;
3125                 bnx2x_post_dmae(bp, dmae, loader_idx);
3126
3127         } else if (bp->func_stx) {
3128                 *stats_comp = 0;
3129                 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3130         }
3131 }
3132
3133 static int bnx2x_stats_comp(struct bnx2x *bp)
3134 {
3135         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3136         int cnt = 10;
3137
3138         might_sleep();
3139         while (*stats_comp != DMAE_COMP_VAL) {
3140                 if (!cnt) {
3141                         BNX2X_ERR("timeout waiting for stats finished\n");
3142                         break;
3143                 }
3144                 cnt--;
3145                 msleep(1);
3146         }
3147         return 1;
3148 }
3149
3150 /*
3151  * Statistics service functions
3152  */
3153
3154 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3155 {
3156         struct dmae_command *dmae;
3157         u32 opcode;
3158         int loader_idx = PMF_DMAE_C(bp);
3159         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3160
3161         /* sanity */
3162         if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3163                 BNX2X_ERR("BUG!\n");
3164                 return;
3165         }
3166
3167         bp->executer_idx = 0;
3168
3169         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3170                   DMAE_CMD_C_ENABLE |
3171                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3172 #ifdef __BIG_ENDIAN
3173                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3174 #else
3175                   DMAE_CMD_ENDIANITY_DW_SWAP |
3176 #endif
3177                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3178                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3179
3180         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3181         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3182         dmae->src_addr_lo = bp->port.port_stx >> 2;
3183         dmae->src_addr_hi = 0;
3184         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3185         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3186         dmae->len = DMAE_LEN32_RD_MAX;
3187         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3188         dmae->comp_addr_hi = 0;
3189         dmae->comp_val = 1;
3190
3191         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3192         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3193         dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3194         dmae->src_addr_hi = 0;
3195         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3196                                    DMAE_LEN32_RD_MAX * 4);
3197         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3198                                    DMAE_LEN32_RD_MAX * 4);
3199         dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3200         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3201         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3202         dmae->comp_val = DMAE_COMP_VAL;
3203
3204         *stats_comp = 0;
3205         bnx2x_hw_stats_post(bp);
3206         bnx2x_stats_comp(bp);
3207 }
3208
3209 static void bnx2x_port_stats_init(struct bnx2x *bp)
3210 {
3211         struct dmae_command *dmae;
3212         int port = BP_PORT(bp);
3213         int vn = BP_E1HVN(bp);
3214         u32 opcode;
3215         int loader_idx = PMF_DMAE_C(bp);
3216         u32 mac_addr;
3217         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3218
3219         /* sanity */
3220         if (!bp->link_vars.link_up || !bp->port.pmf) {
3221                 BNX2X_ERR("BUG!\n");
3222                 return;
3223         }
3224
3225         bp->executer_idx = 0;
3226
3227         /* MCP */
3228         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3229                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3230                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3231 #ifdef __BIG_ENDIAN
3232                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3233 #else
3234                   DMAE_CMD_ENDIANITY_DW_SWAP |
3235 #endif
3236                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3237                   (vn << DMAE_CMD_E1HVN_SHIFT));
3238
3239         if (bp->port.port_stx) {
3240
3241                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3242                 dmae->opcode = opcode;
3243                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3244                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3245                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3246                 dmae->dst_addr_hi = 0;
3247                 dmae->len = sizeof(struct host_port_stats) >> 2;
3248                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3249                 dmae->comp_addr_hi = 0;
3250                 dmae->comp_val = 1;
3251         }
3252
3253         if (bp->func_stx) {
3254
3255                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3256                 dmae->opcode = opcode;
3257                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3258                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3259                 dmae->dst_addr_lo = bp->func_stx >> 2;
3260                 dmae->dst_addr_hi = 0;
3261                 dmae->len = sizeof(struct host_func_stats) >> 2;
3262                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3263                 dmae->comp_addr_hi = 0;
3264                 dmae->comp_val = 1;
3265         }
3266
3267         /* MAC */
3268         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3269                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3270                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3271 #ifdef __BIG_ENDIAN
3272                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3273 #else
3274                   DMAE_CMD_ENDIANITY_DW_SWAP |
3275 #endif
3276                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3277                   (vn << DMAE_CMD_E1HVN_SHIFT));
3278
3279         if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3280
3281                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3282                                    NIG_REG_INGRESS_BMAC0_MEM);
3283
3284                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3285                    BIGMAC_REGISTER_TX_STAT_GTBYT */
3286                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3287                 dmae->opcode = opcode;
3288                 dmae->src_addr_lo = (mac_addr +
3289                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3290                 dmae->src_addr_hi = 0;
3291                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3292                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3293                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3294                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3295                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3296                 dmae->comp_addr_hi = 0;
3297                 dmae->comp_val = 1;
3298
3299                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3300                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
3301                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3302                 dmae->opcode = opcode;
3303                 dmae->src_addr_lo = (mac_addr +
3304                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3305                 dmae->src_addr_hi = 0;
3306                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3307                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3308                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3309                                 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3310                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3311                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3312                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3313                 dmae->comp_addr_hi = 0;
3314                 dmae->comp_val = 1;
3315
3316         } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3317
3318                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3319
3320                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3321                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3322                 dmae->opcode = opcode;
3323                 dmae->src_addr_lo = (mac_addr +
3324                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3325                 dmae->src_addr_hi = 0;
3326                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3327                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3328                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3329                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3330                 dmae->comp_addr_hi = 0;
3331                 dmae->comp_val = 1;
3332
3333                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3334                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3335                 dmae->opcode = opcode;
3336                 dmae->src_addr_lo = (mac_addr +
3337                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3338                 dmae->src_addr_hi = 0;
3339                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3340                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3341                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3342                      offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3343                 dmae->len = 1;
3344                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3345                 dmae->comp_addr_hi = 0;
3346                 dmae->comp_val = 1;
3347
3348                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3349                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3350                 dmae->opcode = opcode;
3351                 dmae->src_addr_lo = (mac_addr +
3352                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3353                 dmae->src_addr_hi = 0;
3354                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3355                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3356                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3357                         offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3358                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3359                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3360                 dmae->comp_addr_hi = 0;
3361                 dmae->comp_val = 1;
3362         }
3363
3364         /* NIG */
3365         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3366         dmae->opcode = opcode;
3367         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3368                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
3369         dmae->src_addr_hi = 0;
3370         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3371         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3372         dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3373         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3374         dmae->comp_addr_hi = 0;
3375         dmae->comp_val = 1;
3376
3377         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3378         dmae->opcode = opcode;
3379         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3380                                     NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3381         dmae->src_addr_hi = 0;
3382         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3383                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3384         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3385                         offsetof(struct nig_stats, egress_mac_pkt0_lo));
3386         dmae->len = (2*sizeof(u32)) >> 2;
3387         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3388         dmae->comp_addr_hi = 0;
3389         dmae->comp_val = 1;
3390
3391         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3392         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3393                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3394                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3395 #ifdef __BIG_ENDIAN
3396                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3397 #else
3398                         DMAE_CMD_ENDIANITY_DW_SWAP |
3399 #endif
3400                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3401                         (vn << DMAE_CMD_E1HVN_SHIFT));
3402         dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3403                                     NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3404         dmae->src_addr_hi = 0;
3405         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3406                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3407         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3408                         offsetof(struct nig_stats, egress_mac_pkt1_lo));
3409         dmae->len = (2*sizeof(u32)) >> 2;
3410         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3411         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3412         dmae->comp_val = DMAE_COMP_VAL;
3413
3414         *stats_comp = 0;
3415 }
3416
3417 static void bnx2x_func_stats_init(struct bnx2x *bp)
3418 {
3419         struct dmae_command *dmae = &bp->stats_dmae;
3420         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3421
3422         /* sanity */
3423         if (!bp->func_stx) {
3424                 BNX2X_ERR("BUG!\n");
3425                 return;
3426         }
3427
3428         bp->executer_idx = 0;
3429         memset(dmae, 0, sizeof(struct dmae_command));
3430
3431         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3432                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3433                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3434 #ifdef __BIG_ENDIAN
3435                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
3436 #else
3437                         DMAE_CMD_ENDIANITY_DW_SWAP |
3438 #endif
3439                         (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3440                         (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3441         dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3442         dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3443         dmae->dst_addr_lo = bp->func_stx >> 2;
3444         dmae->dst_addr_hi = 0;
3445         dmae->len = sizeof(struct host_func_stats) >> 2;
3446         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3447         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3448         dmae->comp_val = DMAE_COMP_VAL;
3449
3450         *stats_comp = 0;
3451 }
3452
3453 static void bnx2x_stats_start(struct bnx2x *bp)
3454 {
3455         if (bp->port.pmf)
3456                 bnx2x_port_stats_init(bp);
3457
3458         else if (bp->func_stx)
3459                 bnx2x_func_stats_init(bp);
3460
3461         bnx2x_hw_stats_post(bp);
3462         bnx2x_storm_stats_post(bp);
3463 }
3464
3465 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3466 {
3467         bnx2x_stats_comp(bp);
3468         bnx2x_stats_pmf_update(bp);
3469         bnx2x_stats_start(bp);
3470 }
3471
3472 static void bnx2x_stats_restart(struct bnx2x *bp)
3473 {
3474         bnx2x_stats_comp(bp);
3475         bnx2x_stats_start(bp);
3476 }
3477
3478 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3479 {
3480         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3481         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3482         struct regpair diff;
3483
3484         UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3485         UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3486         UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3487         UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3488         UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3489         UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3490         UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3491         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3492         UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3493         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3494         UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3495         UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3496         UPDATE_STAT64(tx_stat_gt127,
3497                                 tx_stat_etherstatspkts65octetsto127octets);
3498         UPDATE_STAT64(tx_stat_gt255,
3499                                 tx_stat_etherstatspkts128octetsto255octets);
3500         UPDATE_STAT64(tx_stat_gt511,
3501                                 tx_stat_etherstatspkts256octetsto511octets);
3502         UPDATE_STAT64(tx_stat_gt1023,
3503                                 tx_stat_etherstatspkts512octetsto1023octets);
3504         UPDATE_STAT64(tx_stat_gt1518,
3505                                 tx_stat_etherstatspkts1024octetsto1522octets);
3506         UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3507         UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3508         UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3509         UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3510         UPDATE_STAT64(tx_stat_gterr,
3511                                 tx_stat_dot3statsinternalmactransmiterrors);
3512         UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3513 }
3514
3515 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3516 {
3517         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3518         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3519
3520         UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3521         UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3522         UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3523         UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3524         UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3525         UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3526         UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3527         UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3528         UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3529         UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3530         UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3531         UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3532         UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3533         UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3534         UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3535         UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3536         UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3537         UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3538         UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3539         UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3540         UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3541         UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3542         UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3543         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3544         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3545         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3546         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3547         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3548         UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3549         UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3550         UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3551 }
3552
3553 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3554 {
3555         struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3556         struct nig_stats *old = &(bp->port.old_nig_stats);
3557         struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3558         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3559         struct regpair diff;
3560
3561         if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3562                 bnx2x_bmac_stats_update(bp);
3563
3564         else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3565                 bnx2x_emac_stats_update(bp);
3566
3567         else { /* unreached */
3568                 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3569                 return -1;
3570         }
3571
3572         ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3573                       new->brb_discard - old->brb_discard);
3574         ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3575                       new->brb_truncate - old->brb_truncate);
3576
3577         UPDATE_STAT64_NIG(egress_mac_pkt0,
3578                                         etherstatspkts1024octetsto1522octets);
3579         UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3580
3581         memcpy(old, new, sizeof(struct nig_stats));
3582
3583         memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3584                sizeof(struct mac_stx));
3585         estats->brb_drop_hi = pstats->brb_drop_hi;
3586         estats->brb_drop_lo = pstats->brb_drop_lo;
3587
3588         pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3589
3590         return 0;
3591 }
3592
3593 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3594 {
3595         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3596         int cl_id = BP_CL_ID(bp);
3597         struct tstorm_per_port_stats *tport =
3598                                 &stats->tstorm_common.port_statistics;
3599         struct tstorm_per_client_stats *tclient =
3600                         &stats->tstorm_common.client_statistics[cl_id];
3601         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3602         struct xstorm_per_client_stats *xclient =
3603                         &stats->xstorm_common.client_statistics[cl_id];
3604         struct xstorm_per_client_stats *old_xclient = &bp->old_xclient;
3605         struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3606         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3607         u32 diff;
3608
3609         /* are storm stats valid? */
3610         if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3611                                                         bp->stats_counter) {
3612                 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
3613                    "  tstorm counter (%d) != stats_counter (%d)\n",
3614                    tclient->stats_counter, bp->stats_counter);
3615                 return -1;
3616         }
3617         if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3618                                                         bp->stats_counter) {
3619                 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
3620                    "  xstorm counter (%d) != stats_counter (%d)\n",
3621                    xclient->stats_counter, bp->stats_counter);
3622                 return -2;
3623         }
3624
3625         fstats->total_bytes_received_hi =
3626         fstats->valid_bytes_received_hi =
3627                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
3628         fstats->total_bytes_received_lo =
3629         fstats->valid_bytes_received_lo =
3630                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
3631
3632         estats->error_bytes_received_hi =
3633                                 le32_to_cpu(tclient->rcv_error_bytes.hi);
3634         estats->error_bytes_received_lo =
3635                                 le32_to_cpu(tclient->rcv_error_bytes.lo);
3636         ADD_64(estats->error_bytes_received_hi,
3637                estats->rx_stat_ifhcinbadoctets_hi,
3638                estats->error_bytes_received_lo,
3639                estats->rx_stat_ifhcinbadoctets_lo);
3640
3641         ADD_64(fstats->total_bytes_received_hi,
3642                estats->error_bytes_received_hi,
3643                fstats->total_bytes_received_lo,
3644                estats->error_bytes_received_lo);
3645
3646         UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received);
3647         UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3648                                 total_multicast_packets_received);
3649         UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3650                                 total_broadcast_packets_received);
3651
3652         fstats->total_bytes_transmitted_hi =
3653                                 le32_to_cpu(xclient->total_sent_bytes.hi);
3654         fstats->total_bytes_transmitted_lo =
3655                                 le32_to_cpu(xclient->total_sent_bytes.lo);
3656
3657         UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3658                                 total_unicast_packets_transmitted);
3659         UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3660                                 total_multicast_packets_transmitted);
3661         UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3662                                 total_broadcast_packets_transmitted);
3663
3664         memcpy(estats, &(fstats->total_bytes_received_hi),
3665                sizeof(struct host_func_stats) - 2*sizeof(u32));
3666
3667         estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard);
3668         estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard);
3669         estats->brb_truncate_discard =
3670                                 le32_to_cpu(tport->brb_truncate_discard);
3671         estats->mac_discard = le32_to_cpu(tport->mac_discard);
3672
3673         old_tclient->rcv_unicast_bytes.hi =
3674                                 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
3675         old_tclient->rcv_unicast_bytes.lo =
3676                                 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
3677         old_tclient->rcv_broadcast_bytes.hi =
3678                                 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
3679         old_tclient->rcv_broadcast_bytes.lo =
3680                                 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
3681         old_tclient->rcv_multicast_bytes.hi =
3682                                 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
3683         old_tclient->rcv_multicast_bytes.lo =
3684                                 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
3685         old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts);
3686
3687         old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard);
3688         old_tclient->packets_too_big_discard =
3689                                 le32_to_cpu(tclient->packets_too_big_discard);
3690         estats->no_buff_discard =
3691         old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
3692         old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
3693
3694         old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts);
3695         old_xclient->unicast_bytes_sent.hi =
3696                                 le32_to_cpu(xclient->unicast_bytes_sent.hi);
3697         old_xclient->unicast_bytes_sent.lo =
3698                                 le32_to_cpu(xclient->unicast_bytes_sent.lo);
3699         old_xclient->multicast_bytes_sent.hi =
3700                                 le32_to_cpu(xclient->multicast_bytes_sent.hi);
3701         old_xclient->multicast_bytes_sent.lo =
3702                                 le32_to_cpu(xclient->multicast_bytes_sent.lo);
3703         old_xclient->broadcast_bytes_sent.hi =
3704                                 le32_to_cpu(xclient->broadcast_bytes_sent.hi);
3705         old_xclient->broadcast_bytes_sent.lo =
3706                                 le32_to_cpu(xclient->broadcast_bytes_sent.lo);
3707
3708         fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3709
3710         return 0;
3711 }
3712
3713 static void bnx2x_net_stats_update(struct bnx2x *bp)
3714 {
3715         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3716         struct bnx2x_eth_stats *estats = &bp->eth_stats;
3717         struct net_device_stats *nstats = &bp->dev->stats;
3718
3719         nstats->rx_packets =
3720                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3721                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3722                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3723
3724         nstats->tx_packets =
3725                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3726                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3727                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3728
3729         nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi);
3730
3731         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3732
3733         nstats->rx_dropped = old_tclient->checksum_discard +
3734                              estats->mac_discard;
3735         nstats->tx_dropped = 0;
3736
3737         nstats->multicast =
3738                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
3739
3740         nstats->collisions =
3741                         estats->tx_stat_dot3statssinglecollisionframes_lo +
3742                         estats->tx_stat_dot3statsmultiplecollisionframes_lo +
3743                         estats->tx_stat_dot3statslatecollisions_lo +
3744                         estats->tx_stat_dot3statsexcessivecollisions_lo;
3745
3746         estats->jabber_packets_received =
3747                                 old_tclient->packets_too_big_discard +
3748                                 estats->rx_stat_dot3statsframestoolong_lo;
3749
3750         nstats->rx_length_errors =
3751                                 estats->rx_stat_etherstatsundersizepkts_lo +
3752                                 estats->jabber_packets_received;
3753         nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3754         nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3755         nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3756         nstats->rx_fifo_errors = old_tclient->no_buff_discard;
3757         nstats->rx_missed_errors = estats->xxoverflow_discard;
3758
3759         nstats->rx_errors = nstats->rx_length_errors +
3760                             nstats->rx_over_errors +
3761                             nstats->rx_crc_errors +
3762                             nstats->rx_frame_errors +
3763                             nstats->rx_fifo_errors +
3764                             nstats->rx_missed_errors;
3765
3766         nstats->tx_aborted_errors =
3767                         estats->tx_stat_dot3statslatecollisions_lo +
3768                         estats->tx_stat_dot3statsexcessivecollisions_lo;
3769         nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo;
3770         nstats->tx_fifo_errors = 0;
3771         nstats->tx_heartbeat_errors = 0;
3772         nstats->tx_window_errors = 0;
3773
3774         nstats->tx_errors = nstats->tx_aborted_errors +
3775                             nstats->tx_carrier_errors;
3776 }
3777
3778 static void bnx2x_stats_update(struct bnx2x *bp)
3779 {
3780         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3781         int update = 0;
3782
3783         if (*stats_comp != DMAE_COMP_VAL)
3784                 return;
3785
3786         if (bp->port.pmf)
3787                 update = (bnx2x_hw_stats_update(bp) == 0);
3788
3789         update |= (bnx2x_storm_stats_update(bp) == 0);
3790
3791         if (update)
3792                 bnx2x_net_stats_update(bp);
3793
3794         else {
3795                 if (bp->stats_pending) {
3796                         bp->stats_pending++;
3797                         if (bp->stats_pending == 3) {
3798                                 BNX2X_ERR("stats not updated for 3 times\n");
3799                                 bnx2x_panic();
3800                                 return;
3801                         }
3802                 }
3803         }
3804
3805         if (bp->msglevel & NETIF_MSG_TIMER) {
3806                 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3807                 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3808                 struct net_device_stats *nstats = &bp->dev->stats;
3809                 int i;
3810
3811                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3812                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
3813                                   "  tx pkt (%lx)\n",
3814                        bnx2x_tx_avail(bp->fp),
3815                        le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3816                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
3817                                   "  rx pkt (%lx)\n",
3818                        (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3819                              bp->fp->rx_comp_cons),
3820                        le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3821                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u\n",
3822                        netif_queue_stopped(bp->dev) ? "Xoff" : "Xon",
3823                        estats->driver_xoff, estats->brb_drop_lo);
3824                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
3825                         "packets_too_big_discard %u  no_buff_discard %u  "
3826                         "mac_discard %u  mac_filter_discard %u  "
3827                         "xxovrflow_discard %u  brb_truncate_discard %u  "
3828                         "ttl0_discard %u\n",
3829                        old_tclient->checksum_discard,
3830                        old_tclient->packets_too_big_discard,
3831                        old_tclient->no_buff_discard, estats->mac_discard,
3832                        estats->mac_filter_discard, estats->xxoverflow_discard,
3833                        estats->brb_truncate_discard,
3834                        old_tclient->ttl0_discard);
3835
3836                 for_each_queue(bp, i) {
3837                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3838                                bnx2x_fp(bp, i, tx_pkt),
3839                                bnx2x_fp(bp, i, rx_pkt),
3840                                bnx2x_fp(bp, i, rx_calls));
3841                 }
3842         }
3843
3844         bnx2x_hw_stats_post(bp);
3845         bnx2x_storm_stats_post(bp);
3846 }
3847
3848 static void bnx2x_port_stats_stop(struct bnx2x *bp)
3849 {
3850         struct dmae_command *dmae;
3851         u32 opcode;
3852         int loader_idx = PMF_DMAE_C(bp);
3853         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3854
3855         bp->executer_idx = 0;
3856
3857         opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3858                   DMAE_CMD_C_ENABLE |
3859                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3860 #ifdef __BIG_ENDIAN
3861                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
3862 #else
3863                   DMAE_CMD_ENDIANITY_DW_SWAP |
3864 #endif
3865                   (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3866                   (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3867
3868         if (bp->port.port_stx) {
3869
3870                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3871                 if (bp->func_stx)
3872                         dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3873                 else
3874                         dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3875                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3876                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3877                 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3878                 dmae->dst_addr_hi = 0;
3879                 dmae->len = sizeof(struct host_port_stats) >> 2;
3880                 if (bp->func_stx) {
3881                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3882                         dmae->comp_addr_hi = 0;
3883                         dmae->comp_val = 1;
3884                 } else {
3885                         dmae->comp_addr_lo =
3886                                 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3887                         dmae->comp_addr_hi =
3888                                 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3889                         dmae->comp_val = DMAE_COMP_VAL;
3890
3891                         *stats_comp = 0;
3892                 }
3893         }
3894
3895         if (bp->func_stx) {
3896
3897                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3898                 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3899                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3900                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3901                 dmae->dst_addr_lo = bp->func_stx >> 2;
3902                 dmae->dst_addr_hi = 0;
3903                 dmae->len = sizeof(struct host_func_stats) >> 2;
3904                 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3905                 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3906                 dmae->comp_val = DMAE_COMP_VAL;
3907
3908                 *stats_comp = 0;
3909         }
3910 }
3911
3912 static void bnx2x_stats_stop(struct bnx2x *bp)
3913 {
3914         int update = 0;
3915
3916         bnx2x_stats_comp(bp);
3917
3918         if (bp->port.pmf)
3919                 update = (bnx2x_hw_stats_update(bp) == 0);
3920
3921         update |= (bnx2x_storm_stats_update(bp) == 0);
3922
3923         if (update) {
3924                 bnx2x_net_stats_update(bp);
3925
3926                 if (bp->port.pmf)
3927                         bnx2x_port_stats_stop(bp);
3928
3929                 bnx2x_hw_stats_post(bp);
3930                 bnx2x_stats_comp(bp);
3931         }
3932 }
3933
3934 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
3935 {
3936 }
3937
3938 static const struct {
3939         void (*action)(struct bnx2x *bp);
3940         enum bnx2x_stats_state next_state;
3941 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
3942 /* state        event   */
3943 {
3944 /* DISABLED     PMF     */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
3945 /*              LINK_UP */ {bnx2x_stats_start,      STATS_STATE_ENABLED},
3946 /*              UPDATE  */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
3947 /*              STOP    */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
3948 },
3949 {
3950 /* ENABLED      PMF     */ {bnx2x_stats_pmf_start,  STATS_STATE_ENABLED},
3951 /*              LINK_UP */ {bnx2x_stats_restart,    STATS_STATE_ENABLED},
3952 /*              UPDATE  */ {bnx2x_stats_update,     STATS_STATE_ENABLED},
3953 /*              STOP    */ {bnx2x_stats_stop,       STATS_STATE_DISABLED}
3954 }
3955 };
3956
3957 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
3958 {
3959         enum bnx2x_stats_state state = bp->stats_state;
3960
3961         bnx2x_stats_stm[state][event].action(bp);
3962         bp->stats_state = bnx2x_stats_stm[state][event].next_state;
3963
3964         if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
3965                 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
3966                    state, event, bp->stats_state);
3967 }
3968
3969 static void bnx2x_timer(unsigned long data)
3970 {
3971         struct bnx2x *bp = (struct bnx2x *) data;
3972
3973         if (!netif_running(bp->dev))
3974                 return;
3975
3976         if (atomic_read(&bp->intr_sem) != 0)
3977                 goto timer_restart;
3978
3979         if (poll) {
3980                 struct bnx2x_fastpath *fp = &bp->fp[0];
3981                 int rc;
3982
3983                 bnx2x_tx_int(fp, 1000);
3984                 rc = bnx2x_rx_int(fp, 1000);
3985         }
3986
3987         if (!BP_NOMCP(bp)) {
3988                 int func = BP_FUNC(bp);
3989                 u32 drv_pulse;
3990                 u32 mcp_pulse;
3991
3992                 ++bp->fw_drv_pulse_wr_seq;
3993                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3994                 /* TBD - add SYSTEM_TIME */
3995                 drv_pulse = bp->fw_drv_pulse_wr_seq;
3996                 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
3997
3998                 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
3999                              MCP_PULSE_SEQ_MASK);
4000                 /* The delta between driver pulse and mcp response
4001                  * should be 1 (before mcp response) or 0 (after mcp response)
4002                  */
4003                 if ((drv_pulse != mcp_pulse) &&
4004                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4005                         /* someone lost a heartbeat... */
4006                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4007                                   drv_pulse, mcp_pulse);
4008                 }
4009         }
4010
4011         if ((bp->state == BNX2X_STATE_OPEN) ||
4012             (bp->state == BNX2X_STATE_DISABLED))
4013                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4014
4015 timer_restart:
4016         mod_timer(&bp->timer, jiffies + bp->current_interval);
4017 }
4018
4019 /* end of Statistics */
4020
4021 /* nic init */
4022
4023 /*
4024  * nic init service functions
4025  */
4026
4027 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4028 {
4029         int port = BP_PORT(bp);
4030
4031         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4032                         USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4033                         sizeof(struct ustorm_status_block)/4);
4034         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4035                         CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4036                         sizeof(struct cstorm_status_block)/4);
4037 }
4038
4039 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4040                           dma_addr_t mapping, int sb_id)
4041 {
4042         int port = BP_PORT(bp);
4043         int func = BP_FUNC(bp);
4044         int index;
4045         u64 section;
4046
4047         /* USTORM */
4048         section = ((u64)mapping) + offsetof(struct host_status_block,
4049                                             u_status_block);
4050         sb->u_status_block.status_block_id = sb_id;
4051
4052         REG_WR(bp, BAR_USTRORM_INTMEM +
4053                USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4054         REG_WR(bp, BAR_USTRORM_INTMEM +
4055                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4056                U64_HI(section));
4057         REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4058                 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4059
4060         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4061                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4062                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4063
4064         /* CSTORM */
4065         section = ((u64)mapping) + offsetof(struct host_status_block,
4066                                             c_status_block);
4067         sb->c_status_block.status_block_id = sb_id;
4068
4069         REG_WR(bp, BAR_CSTRORM_INTMEM +
4070                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4071         REG_WR(bp, BAR_CSTRORM_INTMEM +
4072                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4073                U64_HI(section));
4074         REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4075                 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4076
4077         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4078                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4079                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4080
4081         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4082 }
4083
4084 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4085 {
4086         int func = BP_FUNC(bp);
4087
4088         bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4089                         USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4090                         sizeof(struct ustorm_def_status_block)/4);
4091         bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4092                         CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4093                         sizeof(struct cstorm_def_status_block)/4);
4094         bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4095                         XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4096                         sizeof(struct xstorm_def_status_block)/4);
4097         bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4098                         TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4099                         sizeof(struct tstorm_def_status_block)/4);
4100 }
4101
4102 static void bnx2x_init_def_sb(struct bnx2x *bp,
4103                               struct host_def_status_block *def_sb,
4104                               dma_addr_t mapping, int sb_id)
4105 {
4106         int port = BP_PORT(bp);
4107         int func = BP_FUNC(bp);
4108         int index, val, reg_offset;
4109         u64 section;
4110
4111         /* ATTN */
4112         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4113                                             atten_status_block);
4114         def_sb->atten_status_block.status_block_id = sb_id;
4115
4116         bp->attn_state = 0;
4117
4118         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4119                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4120
4121         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4122                 bp->attn_group[index].sig[0] = REG_RD(bp,
4123                                                      reg_offset + 0x10*index);
4124                 bp->attn_group[index].sig[1] = REG_RD(bp,
4125                                                reg_offset + 0x4 + 0x10*index);
4126                 bp->attn_group[index].sig[2] = REG_RD(bp,
4127                                                reg_offset + 0x8 + 0x10*index);
4128                 bp->attn_group[index].sig[3] = REG_RD(bp,
4129                                                reg_offset + 0xc + 0x10*index);
4130         }
4131
4132         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4133                              HC_REG_ATTN_MSG0_ADDR_L);
4134
4135         REG_WR(bp, reg_offset, U64_LO(section));
4136         REG_WR(bp, reg_offset + 4, U64_HI(section));
4137
4138         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4139
4140         val = REG_RD(bp, reg_offset);
4141         val |= sb_id;
4142         REG_WR(bp, reg_offset, val);
4143
4144         /* USTORM */
4145         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4146                                             u_def_status_block);
4147         def_sb->u_def_status_block.status_block_id = sb_id;
4148
4149         REG_WR(bp, BAR_USTRORM_INTMEM +
4150                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4151         REG_WR(bp, BAR_USTRORM_INTMEM +
4152                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4153                U64_HI(section));
4154         REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4155                 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4156
4157         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4158                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4159                          USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4160
4161         /* CSTORM */
4162         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4163                                             c_def_status_block);
4164         def_sb->c_def_status_block.status_block_id = sb_id;
4165
4166         REG_WR(bp, BAR_CSTRORM_INTMEM +
4167                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4168         REG_WR(bp, BAR_CSTRORM_INTMEM +
4169                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4170                U64_HI(section));
4171         REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4172                 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4173
4174         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4175                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4176                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4177
4178         /* TSTORM */
4179         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4180                                             t_def_status_block);
4181         def_sb->t_def_status_block.status_block_id = sb_id;
4182
4183         REG_WR(bp, BAR_TSTRORM_INTMEM +
4184                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4185         REG_WR(bp, BAR_TSTRORM_INTMEM +
4186                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4187                U64_HI(section));
4188         REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4189                 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4190
4191         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4192                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4193                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4194
4195         /* XSTORM */
4196         section = ((u64)mapping) + offsetof(struct host_def_status_block,
4197                                             x_def_status_block);
4198         def_sb->x_def_status_block.status_block_id = sb_id;
4199
4200         REG_WR(bp, BAR_XSTRORM_INTMEM +
4201                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4202         REG_WR(bp, BAR_XSTRORM_INTMEM +
4203                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4204                U64_HI(section));
4205         REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4206                 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4207
4208         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4209                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4210                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4211
4212         bp->stats_pending = 0;
4213         bp->set_mac_pending = 0;
4214
4215         bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4216 }
4217
4218 static void bnx2x_update_coalesce(struct bnx2x *bp)
4219 {
4220         int port = BP_PORT(bp);
4221         int i;
4222
4223         for_each_queue(bp, i) {
4224                 int sb_id = bp->fp[i].sb_id;
4225
4226                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4227                 REG_WR8(bp, BAR_USTRORM_INTMEM +
4228                         USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4229                                                     U_SB_ETH_RX_CQ_INDEX),
4230                         bp->rx_ticks/12);
4231                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4232                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4233                                                      U_SB_ETH_RX_CQ_INDEX),
4234                          bp->rx_ticks ? 0 : 1);
4235                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4236                          USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4237                                                      U_SB_ETH_RX_BD_INDEX),
4238                          bp->rx_ticks ? 0 : 1);
4239
4240                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4241                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4242                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4243                                                     C_SB_ETH_TX_CQ_INDEX),
4244                         bp->tx_ticks/12);
4245                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4246                          CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4247                                                      C_SB_ETH_TX_CQ_INDEX),
4248                          bp->tx_ticks ? 0 : 1);
4249         }
4250 }
4251
4252 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4253                                        struct bnx2x_fastpath *fp, int last)
4254 {
4255         int i;
4256
4257         for (i = 0; i < last; i++) {
4258                 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4259                 struct sk_buff *skb = rx_buf->skb;
4260
4261                 if (skb == NULL) {
4262                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4263                         continue;
4264                 }
4265
4266                 if (fp->tpa_state[i] == BNX2X_TPA_START)
4267                         pci_unmap_single(bp->pdev,
4268                                          pci_unmap_addr(rx_buf, mapping),
4269                                          bp->rx_buf_size,
4270                                          PCI_DMA_FROMDEVICE);
4271
4272                 dev_kfree_skb(skb);
4273                 rx_buf->skb = NULL;
4274         }
4275 }
4276
4277 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4278 {
4279         int func = BP_FUNC(bp);
4280         int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4281                                               ETH_MAX_AGGREGATION_QUEUES_E1H;
4282         u16 ring_prod, cqe_ring_prod;
4283         int i, j;
4284
4285         bp->rx_buf_size = bp->dev->mtu;
4286         bp->rx_buf_size += bp->rx_offset + ETH_OVREHEAD +
4287                 BCM_RX_ETH_PAYLOAD_ALIGN;
4288
4289         if (bp->flags & TPA_ENABLE_FLAG) {
4290                 DP(NETIF_MSG_IFUP,
4291                    "rx_buf_size %d  effective_mtu %d\n",
4292                    bp->rx_buf_size, bp->dev->mtu + ETH_OVREHEAD);
4293
4294                 for_each_queue(bp, j) {
4295                         struct bnx2x_fastpath *fp = &bp->fp[j];
4296
4297                         for (i = 0; i < max_agg_queues; i++) {
4298                                 fp->tpa_pool[i].skb =
4299                                    netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4300                                 if (!fp->tpa_pool[i].skb) {
4301                                         BNX2X_ERR("Failed to allocate TPA "
4302                                                   "skb pool for queue[%d] - "
4303                                                   "disabling TPA on this "
4304                                                   "queue!\n", j);
4305                                         bnx2x_free_tpa_pool(bp, fp, i);
4306                                         fp->disable_tpa = 1;
4307                                         break;
4308                                 }
4309                                 pci_unmap_addr_set((struct sw_rx_bd *)
4310                                                         &bp->fp->tpa_pool[i],
4311                                                    mapping, 0);
4312                                 fp->tpa_state[i] = BNX2X_TPA_STOP;
4313                         }
4314                 }
4315         }
4316
4317         for_each_queue(bp, j) {
4318                 struct bnx2x_fastpath *fp = &bp->fp[j];
4319
4320                 fp->rx_bd_cons = 0;
4321                 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4322                 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4323
4324                 /* "next page" elements initialization */
4325                 /* SGE ring */
4326                 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4327                         struct eth_rx_sge *sge;
4328
4329                         sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4330                         sge->addr_hi =
4331                                 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4332                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4333                         sge->addr_lo =
4334                                 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4335                                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4336                 }
4337
4338                 bnx2x_init_sge_ring_bit_mask(fp);
4339
4340                 /* RX BD ring */
4341                 for (i = 1; i <= NUM_RX_RINGS; i++) {
4342                         struct eth_rx_bd *rx_bd;
4343
4344                         rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4345                         rx_bd->addr_hi =
4346                                 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4347                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4348                         rx_bd->addr_lo =
4349                                 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4350                                             BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4351                 }
4352
4353                 /* CQ ring */
4354                 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4355                         struct eth_rx_cqe_next_page *nextpg;
4356
4357                         nextpg = (struct eth_rx_cqe_next_page *)
4358                                 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4359                         nextpg->addr_hi =
4360                                 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4361                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4362                         nextpg->addr_lo =
4363                                 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4364                                            BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4365                 }
4366
4367                 /* Allocate SGEs and initialize the ring elements */
4368                 for (i = 0, ring_prod = 0;
4369                      i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4370
4371                         if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4372                                 BNX2X_ERR("was only able to allocate "
4373                                           "%d rx sges\n", i);
4374                                 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4375                                 /* Cleanup already allocated elements */
4376                                 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4377                                 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4378                                 fp->disable_tpa = 1;
4379                                 ring_prod = 0;
4380                                 break;
4381                         }
4382                         ring_prod = NEXT_SGE_IDX(ring_prod);
4383                 }
4384                 fp->rx_sge_prod = ring_prod;
4385
4386                 /* Allocate BDs and initialize BD ring */
4387                 fp->rx_comp_cons = 0;
4388                 cqe_ring_prod = ring_prod = 0;
4389                 for (i = 0; i < bp->rx_ring_size; i++) {
4390                         if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4391                                 BNX2X_ERR("was only able to allocate "
4392                                           "%d rx skbs\n", i);
4393                                 bp->eth_stats.rx_skb_alloc_failed++;
4394                                 break;
4395                         }
4396                         ring_prod = NEXT_RX_IDX(ring_prod);
4397                         cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4398                         WARN_ON(ring_prod <= i);
4399                 }
4400
4401                 fp->rx_bd_prod = ring_prod;
4402                 /* must not have more available CQEs than BDs */
4403                 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4404                                        cqe_ring_prod);
4405                 fp->rx_pkt = fp->rx_calls = 0;
4406
4407                 /* Warning!
4408                  * this will generate an interrupt (to the TSTORM)
4409                  * must only be done after chip is initialized
4410                  */
4411                 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4412                                      fp->rx_sge_prod);
4413                 if (j != 0)
4414                         continue;
4415
4416                 REG_WR(bp, BAR_USTRORM_INTMEM +
4417                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4418                        U64_LO(fp->rx_comp_mapping));
4419                 REG_WR(bp, BAR_USTRORM_INTMEM +
4420                        USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4421                        U64_HI(fp->rx_comp_mapping));
4422         }
4423 }
4424
4425 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4426 {
4427         int i, j;
4428
4429         for_each_queue(bp, j) {
4430                 struct bnx2x_fastpath *fp = &bp->fp[j];
4431
4432                 for (i = 1; i <= NUM_TX_RINGS; i++) {
4433                         struct eth_tx_bd *tx_bd =
4434                                 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4435
4436                         tx_bd->addr_hi =
4437                                 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4438                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4439                         tx_bd->addr_lo =
4440                                 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4441                                             BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4442                 }
4443
4444                 fp->tx_pkt_prod = 0;
4445                 fp->tx_pkt_cons = 0;
4446                 fp->tx_bd_prod = 0;
4447                 fp->tx_bd_cons = 0;
4448                 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4449                 fp->tx_pkt = 0;
4450         }
4451 }
4452
4453 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4454 {
4455         int func = BP_FUNC(bp);
4456
4457         spin_lock_init(&bp->spq_lock);
4458
4459         bp->spq_left = MAX_SPQ_PENDING;
4460         bp->spq_prod_idx = 0;
4461         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4462         bp->spq_prod_bd = bp->spq;
4463         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4464
4465         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4466                U64_LO(bp->spq_mapping));
4467         REG_WR(bp,
4468                XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4469                U64_HI(bp->spq_mapping));
4470
4471         REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4472                bp->spq_prod_idx);
4473 }
4474
4475 static void bnx2x_init_context(struct bnx2x *bp)
4476 {
4477         int i;
4478
4479         for_each_queue(bp, i) {
4480                 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4481                 struct bnx2x_fastpath *fp = &bp->fp[i];
4482                 u8 sb_id = FP_SB_ID(fp);
4483
4484                 context->xstorm_st_context.tx_bd_page_base_hi =
4485                                                 U64_HI(fp->tx_desc_mapping);
4486                 context->xstorm_st_context.tx_bd_page_base_lo =
4487                                                 U64_LO(fp->tx_desc_mapping);
4488                 context->xstorm_st_context.db_data_addr_hi =
4489                                                 U64_HI(fp->tx_prods_mapping);
4490                 context->xstorm_st_context.db_data_addr_lo =
4491                                                 U64_LO(fp->tx_prods_mapping);
4492                 context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |
4493                                 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4494
4495                 context->ustorm_st_context.common.sb_index_numbers =
4496                                                 BNX2X_RX_SB_INDEX_NUM;
4497                 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4498                 context->ustorm_st_context.common.status_block_id = sb_id;
4499                 context->ustorm_st_context.common.flags =
4500                         USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
4501                 context->ustorm_st_context.common.mc_alignment_size =
4502                         BCM_RX_ETH_PAYLOAD_ALIGN;
4503                 context->ustorm_st_context.common.bd_buff_size =
4504                                                 bp->rx_buf_size;
4505                 context->ustorm_st_context.common.bd_page_base_hi =
4506                                                 U64_HI(fp->rx_desc_mapping);
4507                 context->ustorm_st_context.common.bd_page_base_lo =
4508                                                 U64_LO(fp->rx_desc_mapping);
4509                 if (!fp->disable_tpa) {
4510                         context->ustorm_st_context.common.flags |=
4511                                 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4512                                  USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4513                         context->ustorm_st_context.common.sge_buff_size =
4514                                         (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
4515                         context->ustorm_st_context.common.sge_page_base_hi =
4516                                                 U64_HI(fp->rx_sge_mapping);
4517                         context->ustorm_st_context.common.sge_page_base_lo =
4518                                                 U64_LO(fp->rx_sge_mapping);
4519                 }
4520
4521                 context->cstorm_st_context.sb_index_number =
4522                                                 C_SB_ETH_TX_CQ_INDEX;
4523                 context->cstorm_st_context.status_block_id = sb_id;
4524
4525                 context->xstorm_ag_context.cdu_reserved =
4526                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4527                                                CDU_REGION_NUMBER_XCM_AG,
4528                                                ETH_CONNECTION_TYPE);
4529                 context->ustorm_ag_context.cdu_usage =
4530                         CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4531                                                CDU_REGION_NUMBER_UCM_AG,
4532                                                ETH_CONNECTION_TYPE);
4533         }
4534 }
4535
4536 static void bnx2x_init_ind_table(struct bnx2x *bp)
4537 {
4538         int func = BP_FUNC(bp);
4539         int i;
4540
4541         if (!is_multi(bp))
4542                 return;
4543
4544         DP(NETIF_MSG_IFUP, "Initializing indirection table\n");
4545         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4546                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4547                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4548                         BP_CL_ID(bp) + (i % bp->num_queues));
4549 }
4550
4551 static void bnx2x_set_client_config(struct bnx2x *bp)
4552 {
4553         struct tstorm_eth_client_config tstorm_client = {0};
4554         int port = BP_PORT(bp);
4555         int i;
4556
4557         tstorm_client.mtu = bp->dev->mtu;
4558         tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4559         tstorm_client.config_flags =
4560                                 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4561 #ifdef BCM_VLAN
4562         if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
4563                 tstorm_client.config_flags |=
4564                                 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
4565                 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4566         }
4567 #endif
4568
4569         if (bp->flags & TPA_ENABLE_FLAG) {
4570                 tstorm_client.max_sges_for_packet =
4571                         SGE_PAGE_ALIGN(tstorm_client.mtu) >> SGE_PAGE_SHIFT;
4572                 tstorm_client.max_sges_for_packet =
4573                         ((tstorm_client.max_sges_for_packet +
4574                           PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4575                         PAGES_PER_SGE_SHIFT;
4576
4577                 tstorm_client.config_flags |=
4578                                 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4579         }
4580
4581         for_each_queue(bp, i) {
4582                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4583                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4584                        ((u32 *)&tstorm_client)[0]);
4585                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4586                        TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4587                        ((u32 *)&tstorm_client)[1]);
4588         }
4589
4590         DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4591            ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4592 }
4593
4594 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4595 {
4596         struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4597         int mode = bp->rx_mode;
4598         int mask = (1 << BP_L_ID(bp));
4599         int func = BP_FUNC(bp);
4600         int i;
4601
4602         DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
4603
4604         switch (mode) {
4605         case BNX2X_RX_MODE_NONE: /* no Rx */
4606                 tstorm_mac_filter.ucast_drop_all = mask;
4607                 tstorm_mac_filter.mcast_drop_all = mask;
4608                 tstorm_mac_filter.bcast_drop_all = mask;
4609                 break;
4610         case BNX2X_RX_MODE_NORMAL:
4611                 tstorm_mac_filter.bcast_accept_all = mask;
4612                 break;
4613         case BNX2X_RX_MODE_ALLMULTI:
4614                 tstorm_mac_filter.mcast_accept_all = mask;
4615                 tstorm_mac_filter.bcast_accept_all = mask;
4616                 break;
4617         case BNX2X_RX_MODE_PROMISC:
4618                 tstorm_mac_filter.ucast_accept_all = mask;
4619                 tstorm_mac_filter.mcast_accept_all = mask;
4620                 tstorm_mac_filter.bcast_accept_all = mask;
4621                 break;
4622         default:
4623                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4624                 break;
4625         }
4626
4627         for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4628                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4629                        TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4630                        ((u32 *)&tstorm_mac_filter)[i]);
4631
4632 /*              DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4633                    ((u32 *)&tstorm_mac_filter)[i]); */
4634         }
4635
4636         if (mode != BNX2X_RX_MODE_NONE)
4637                 bnx2x_set_client_config(bp);
4638 }
4639
4640 static void bnx2x_init_internal_common(struct bnx2x *bp)
4641 {
4642         int i;
4643
4644         if (bp->flags & TPA_ENABLE_FLAG) {
4645                 struct tstorm_eth_tpa_exist tpa = {0};
4646
4647                 tpa.tpa_exist = 1;
4648
4649                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
4650                        ((u32 *)&tpa)[0]);
4651                 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
4652                        ((u32 *)&tpa)[1]);
4653         }
4654
4655         /* Zero this manually as its initialization is
4656            currently missing in the initTool */
4657         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4658                 REG_WR(bp, BAR_USTRORM_INTMEM +
4659                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
4660 }
4661
4662 static void bnx2x_init_internal_port(struct bnx2x *bp)
4663 {
4664         int port = BP_PORT(bp);
4665
4666         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4667         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4668         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4669         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4670 }
4671
4672 static void bnx2x_init_internal_func(struct bnx2x *bp)
4673 {
4674         struct tstorm_eth_function_common_config tstorm_config = {0};
4675         struct stats_indication_flags stats_flags = {0};
4676         int port = BP_PORT(bp);
4677         int func = BP_FUNC(bp);
4678         int i;
4679         u16 max_agg_size;
4680
4681         if (is_multi(bp)) {
4682                 tstorm_config.config_flags = MULTI_FLAGS;
4683                 tstorm_config.rss_result_mask = MULTI_MASK;
4684         }
4685
4686         tstorm_config.leading_client_id = BP_L_ID(bp);
4687
4688         REG_WR(bp, BAR_TSTRORM_INTMEM +
4689                TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4690                (*(u32 *)&tstorm_config));
4691
4692         bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4693         bnx2x_set_storm_rx_mode(bp);
4694
4695         /* reset xstorm per client statistics */
4696         for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4697                 REG_WR(bp, BAR_XSTRORM_INTMEM +
4698                        XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4699                        i*4, 0);
4700         }
4701         /* reset tstorm per client statistics */
4702         for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4703                 REG_WR(bp, BAR_TSTRORM_INTMEM +
4704                        TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4705                        i*4, 0);
4706         }
4707
4708         /* Init statistics related context */
4709         stats_flags.collect_eth = 1;
4710
4711         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4712                ((u32 *)&stats_flags)[0]);
4713         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4714                ((u32 *)&stats_flags)[1]);
4715
4716         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4717                ((u32 *)&stats_flags)[0]);
4718         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4719                ((u32 *)&stats_flags)[1]);
4720
4721         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4722                ((u32 *)&stats_flags)[0]);
4723         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4724                ((u32 *)&stats_flags)[1]);
4725
4726         REG_WR(bp, BAR_XSTRORM_INTMEM +
4727                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4728                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4729         REG_WR(bp, BAR_XSTRORM_INTMEM +
4730                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4731                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4732
4733         REG_WR(bp, BAR_TSTRORM_INTMEM +
4734                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4735                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4736         REG_WR(bp, BAR_TSTRORM_INTMEM +
4737                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4738                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4739
4740         if (CHIP_IS_E1H(bp)) {
4741                 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4742                         IS_E1HMF(bp));
4743                 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4744                         IS_E1HMF(bp));
4745                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4746                         IS_E1HMF(bp));
4747                 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4748                         IS_E1HMF(bp));
4749
4750                 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4751                          bp->e1hov);
4752         }
4753
4754         /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
4755         max_agg_size =
4756                 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
4757                           SGE_PAGE_SIZE * PAGES_PER_SGE),
4758                     (u32)0xffff);
4759         for_each_queue(bp, i) {
4760                 struct bnx2x_fastpath *fp = &bp->fp[i];
4761
4762                 REG_WR(bp, BAR_USTRORM_INTMEM +
4763                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4764                        U64_LO(fp->rx_comp_mapping));
4765                 REG_WR(bp, BAR_USTRORM_INTMEM +
4766                        USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4767                        U64_HI(fp->rx_comp_mapping));
4768
4769                 REG_WR16(bp, BAR_USTRORM_INTMEM +
4770                          USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4771                          max_agg_size);
4772         }
4773 }
4774
4775 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4776 {
4777         switch (load_code) {
4778         case FW_MSG_CODE_DRV_LOAD_COMMON:
4779                 bnx2x_init_internal_common(bp);
4780                 /* no break */
4781
4782         case FW_MSG_CODE_DRV_LOAD_PORT:
4783                 bnx2x_init_internal_port(bp);
4784                 /* no break */
4785
4786         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4787                 bnx2x_init_internal_func(bp);
4788                 break;
4789
4790         default:
4791                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4792                 break;
4793         }
4794 }
4795
4796 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4797 {
4798         int i;
4799
4800         for_each_queue(bp, i) {
4801                 struct bnx2x_fastpath *fp = &bp->fp[i];
4802
4803                 fp->bp = bp;
4804                 fp->state = BNX2X_FP_STATE_CLOSED;
4805                 fp->index = i;
4806                 fp->cl_id = BP_L_ID(bp) + i;
4807                 fp->sb_id = fp->cl_id;
4808                 DP(NETIF_MSG_IFUP,
4809                    "bnx2x_init_sb(%p,%p) index %d  cl_id %d  sb %d\n",
4810                    bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4811                 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4812                               FP_SB_ID(fp));
4813                 bnx2x_update_fpsb_idx(fp);
4814         }
4815
4816         bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4817                           DEF_SB_ID);
4818         bnx2x_update_dsb_idx(bp);
4819         bnx2x_update_coalesce(bp);
4820         bnx2x_init_rx_rings(bp);
4821         bnx2x_init_tx_ring(bp);
4822         bnx2x_init_sp_ring(bp);
4823         bnx2x_init_context(bp);
4824         bnx2x_init_internal(bp, load_code);
4825         bnx2x_init_ind_table(bp);
4826         bnx2x_stats_init(bp);
4827
4828         /* At this point, we are ready for interrupts */
4829         atomic_set(&bp->intr_sem, 0);
4830
4831         /* flush all before enabling interrupts */
4832         mb();
4833         mmiowb();
4834
4835         bnx2x_int_enable(bp);
4836 }
4837
4838 /* end of nic init */
4839
4840 /*
4841  * gzip service functions
4842  */
4843
4844 static int bnx2x_gunzip_init(struct bnx2x *bp)
4845 {
4846         bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4847                                               &bp->gunzip_mapping);
4848         if (bp->gunzip_buf  == NULL)
4849                 goto gunzip_nomem1;
4850
4851         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4852         if (bp->strm  == NULL)
4853                 goto gunzip_nomem2;
4854
4855         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4856                                       GFP_KERNEL);
4857         if (bp->strm->workspace == NULL)
4858                 goto gunzip_nomem3;
4859
4860         return 0;
4861
4862 gunzip_nomem3:
4863         kfree(bp->strm);
4864         bp->strm = NULL;
4865
4866 gunzip_nomem2:
4867         pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4868                             bp->gunzip_mapping);
4869         bp->gunzip_buf = NULL;
4870
4871 gunzip_nomem1:
4872         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4873                " un-compression\n", bp->dev->name);
4874         return -ENOMEM;
4875 }
4876
4877 static void bnx2x_gunzip_end(struct bnx2x *bp)
4878 {
4879         kfree(bp->strm->workspace);
4880
4881         kfree(bp->strm);
4882         bp->strm = NULL;
4883
4884         if (bp->gunzip_buf) {
4885                 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4886                                     bp->gunzip_mapping);
4887                 bp->gunzip_buf = NULL;
4888         }
4889 }
4890
4891 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4892 {
4893         int n, rc;
4894
4895         /* check gzip header */
4896         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4897                 return -EINVAL;
4898
4899         n = 10;
4900
4901 #define FNAME                           0x8
4902
4903         if (zbuf[3] & FNAME)
4904                 while ((zbuf[n++] != 0) && (n < len));
4905
4906         bp->strm->next_in = zbuf + n;
4907         bp->strm->avail_in = len - n;
4908         bp->strm->next_out = bp->gunzip_buf;
4909         bp->strm->avail_out = FW_BUF_SIZE;
4910
4911         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4912         if (rc != Z_OK)
4913                 return rc;
4914
4915         rc = zlib_inflate(bp->strm, Z_FINISH);
4916         if ((rc != Z_OK) && (rc != Z_STREAM_END))
4917                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4918                        bp->dev->name, bp->strm->msg);
4919
4920         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4921         if (bp->gunzip_outlen & 0x3)
4922                 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4923                                     " gunzip_outlen (%d) not aligned\n",
4924                        bp->dev->name, bp->gunzip_outlen);
4925         bp->gunzip_outlen >>= 2;
4926
4927         zlib_inflateEnd(bp->strm);
4928
4929         if (rc == Z_STREAM_END)
4930                 return 0;
4931
4932         return rc;
4933 }
4934
4935 /* nic load/unload */
4936
4937 /*
4938  * General service functions
4939  */
4940
4941 /* send a NIG loopback debug packet */
4942 static void bnx2x_lb_pckt(struct bnx2x *bp)
4943 {
4944         u32 wb_write[3];
4945
4946         /* Ethernet source and destination addresses */
4947         wb_write[0] = 0x55555555;
4948         wb_write[1] = 0x55555555;
4949         wb_write[2] = 0x20;             /* SOP */
4950         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4951
4952         /* NON-IP protocol */
4953         wb_write[0] = 0x09000000;
4954         wb_write[1] = 0x55555555;
4955         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
4956         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4957 }
4958
4959 /* some of the internal memories
4960  * are not directly readable from the driver
4961  * to test them we send debug packets
4962  */
4963 static int bnx2x_int_mem_test(struct bnx2x *bp)
4964 {
4965         int factor;
4966         int count, i;
4967         u32 val = 0;
4968
4969         if (CHIP_REV_IS_FPGA(bp))
4970                 factor = 120;
4971         else if (CHIP_REV_IS_EMUL(bp))
4972                 factor = 200;
4973         else
4974                 factor = 1;
4975
4976         DP(NETIF_MSG_HW, "start part1\n");
4977
4978         /* Disable inputs of parser neighbor blocks */
4979         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4980         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4981         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4982         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4983
4984         /*  Write 0 to parser credits for CFC search request */
4985         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4986
4987         /* send Ethernet packet */
4988         bnx2x_lb_pckt(bp);
4989
4990         /* TODO do i reset NIG statistic? */
4991         /* Wait until NIG register shows 1 packet of size 0x10 */
4992         count = 1000 * factor;
4993         while (count) {
4994
4995                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4996                 val = *bnx2x_sp(bp, wb_data[0]);
4997                 if (val == 0x10)
4998                         break;
4999
5000                 msleep(10);
5001                 count--;
5002         }
5003         if (val != 0x10) {
5004                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5005                 return -1;
5006         }
5007
5008         /* Wait until PRS register shows 1 packet */
5009         count = 1000 * factor;
5010         while (count) {
5011                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5012                 if (val == 1)
5013                         break;
5014
5015                 msleep(10);
5016                 count--;
5017         }
5018         if (val != 0x1) {
5019                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5020                 return -2;
5021         }
5022
5023         /* Reset and init BRB, PRS */
5024         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5025         msleep(50);
5026         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5027         msleep(50);
5028         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5029         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5030
5031         DP(NETIF_MSG_HW, "part2\n");
5032
5033         /* Disable inputs of parser neighbor blocks */
5034         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5035         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5036         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5037         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5038
5039         /* Write 0 to parser credits for CFC search request */
5040         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5041
5042         /* send 10 Ethernet packets */
5043         for (i = 0; i < 10; i++)
5044                 bnx2x_lb_pckt(bp);
5045
5046         /* Wait until NIG register shows 10 + 1
5047            packets of size 11*0x10 = 0xb0 */
5048         count = 1000 * factor;
5049         while (count) {
5050
5051                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5052                 val = *bnx2x_sp(bp, wb_data[0]);
5053                 if (val == 0xb0)
5054                         break;
5055
5056                 msleep(10);
5057                 count--;
5058         }
5059         if (val != 0xb0) {
5060                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5061                 return -3;
5062         }
5063
5064         /* Wait until PRS register shows 2 packets */
5065         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5066         if (val != 2)
5067                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5068
5069         /* Write 1 to parser credits for CFC search request */
5070         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5071
5072         /* Wait until PRS register shows 3 packets */
5073         msleep(10 * factor);
5074         /* Wait until NIG register shows 1 packet of size 0x10 */
5075         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5076         if (val != 3)
5077                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
5078
5079         /* clear NIG EOP FIFO */
5080         for (i = 0; i < 11; i++)
5081                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5082         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5083         if (val != 1) {
5084                 BNX2X_ERR("clear of NIG failed\n");
5085                 return -4;
5086         }
5087
5088         /* Reset and init BRB, PRS, NIG */
5089         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5090         msleep(50);
5091         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5092         msleep(50);
5093         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5094         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5095 #ifndef BCM_ISCSI
5096         /* set NIC mode */
5097         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5098 #endif
5099
5100         /* Enable inputs of parser neighbor blocks */
5101         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5102         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5103         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5104         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5105
5106         DP(NETIF_MSG_HW, "done\n");
5107
5108         return 0; /* OK */
5109 }
5110
5111 static void enable_blocks_attention(struct bnx2x *bp)
5112 {
5113         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5114         REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5115         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5116         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5117         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5118         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5119         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5120         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5121         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5122 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5123 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5124         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5125         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5126         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5127 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5128 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5129         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5130         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5131         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5132         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5133 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5134 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5135         if (CHIP_REV_IS_FPGA(bp))
5136                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5137         else
5138                 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5139         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5140         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5141         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5142 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5143 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5144         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5145         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5146 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5147         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
5148 }
5149
5150
5151 static void bnx2x_reset_common(struct bnx2x *bp)
5152 {
5153         /* reset_common */
5154         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5155                0xd3ffff7f);
5156         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
5157 }
5158
5159 static int bnx2x_init_common(struct bnx2x *bp)
5160 {
5161         u32 val, i;
5162
5163         DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
5164
5165         bnx2x_reset_common(bp);
5166         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5167         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5168
5169         bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5170         if (CHIP_IS_E1H(bp))
5171                 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5172
5173         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5174         msleep(30);
5175         REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5176
5177         bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5178         if (CHIP_IS_E1(bp)) {
5179                 /* enable HW interrupt from PXP on USDM overflow
5180                    bit 16 on INT_MASK_0 */
5181                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5182         }
5183
5184         bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5185         bnx2x_init_pxp(bp);
5186
5187 #ifdef __BIG_ENDIAN
5188         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5189         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5190         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5191         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5192         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5193
5194 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5195         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5196         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5197         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5198         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5199 #endif
5200
5201         REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5202 #ifdef BCM_ISCSI
5203         REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5204         REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5205         REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5206 #endif
5207
5208         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5209                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5210
5211         /* let the HW do it's magic ... */
5212         msleep(100);
5213         /* finish PXP init */
5214         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5215         if (val != 1) {
5216                 BNX2X_ERR("PXP2 CFG failed\n");
5217                 return -EBUSY;
5218         }
5219         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5220         if (val != 1) {
5221                 BNX2X_ERR("PXP2 RD_INIT failed\n");
5222                 return -EBUSY;
5223         }
5224
5225         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5226         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5227
5228         bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5229
5230         /* clean the DMAE memory */
5231         bp->dmae_ready = 1;
5232         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5233
5234         bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5235         bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5236         bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5237         bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5238
5239         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5240         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5241         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5242         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5243
5244         bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5245         /* soft reset pulse */
5246         REG_WR(bp, QM_REG_SOFT_RESET, 1);
5247         REG_WR(bp, QM_REG_SOFT_RESET, 0);
5248
5249 #ifdef BCM_ISCSI
5250         bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5251 #endif
5252
5253         bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5254         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5255         if (!CHIP_REV_IS_SLOW(bp)) {
5256                 /* enable hw interrupt from doorbell Q */
5257                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5258         }
5259
5260         bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5261         if (CHIP_REV_IS_SLOW(bp)) {
5262                 /* fix for emulation and FPGA for no pause */
5263                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5264                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5265                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5266                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5267         }
5268
5269         bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5270         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5271         /* set NIC mode */
5272         REG_WR(bp, PRS_REG_NIC_MODE, 1);
5273         if (CHIP_IS_E1H(bp))
5274                 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5275
5276         bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5277         bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5278         bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5279         bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5280
5281         if (CHIP_IS_E1H(bp)) {
5282                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5283                                 STORM_INTMEM_SIZE_E1H/2);
5284                 bnx2x_init_fill(bp,
5285                                 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5286                                 0, STORM_INTMEM_SIZE_E1H/2);
5287                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5288                                 STORM_INTMEM_SIZE_E1H/2);
5289                 bnx2x_init_fill(bp,
5290                                 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5291                                 0, STORM_INTMEM_SIZE_E1H/2);
5292                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5293                                 STORM_INTMEM_SIZE_E1H/2);
5294                 bnx2x_init_fill(bp,
5295                                 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5296                                 0, STORM_INTMEM_SIZE_E1H/2);
5297                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5298                                 STORM_INTMEM_SIZE_E1H/2);
5299                 bnx2x_init_fill(bp,
5300                                 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5301                                 0, STORM_INTMEM_SIZE_E1H/2);
5302         } else { /* E1 */
5303                 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5304                                 STORM_INTMEM_SIZE_E1);
5305                 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5306                                 STORM_INTMEM_SIZE_E1);
5307                 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5308                                 STORM_INTMEM_SIZE_E1);
5309                 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5310                                 STORM_INTMEM_SIZE_E1);
5311         }
5312
5313         bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5314         bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5315         bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5316         bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5317
5318         /* sync semi rtc */
5319         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5320                0x80000000);
5321         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5322                0x80000000);
5323
5324         bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5325         bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5326         bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5327
5328         REG_WR(bp, SRC_REG_SOFT_RST, 1);
5329         for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5330                 REG_WR(bp, i, 0xc0cac01a);
5331                 /* TODO: replace with something meaningful */
5332         }
5333         if (CHIP_IS_E1H(bp))
5334                 bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5335         REG_WR(bp, SRC_REG_SOFT_RST, 0);
5336
5337         if (sizeof(union cdu_context) != 1024)
5338                 /* we currently assume that a context is 1024 bytes */
5339                 printk(KERN_ALERT PFX "please adjust the size of"
5340                        " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5341
5342         bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5343         val = (4 << 24) + (0 << 12) + 1024;
5344         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5345         if (CHIP_IS_E1(bp)) {
5346                 /* !!! fix pxp client crdit until excel update */
5347                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5348                 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5349         }
5350
5351         bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5352         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5353
5354         bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5355         bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5356
5357         /* PXPCS COMMON comes here */
5358         /* Reset PCIE errors for debug */
5359         REG_WR(bp, 0x2814, 0xffffffff);
5360         REG_WR(bp, 0x3820, 0xffffffff);
5361
5362         /* EMAC0 COMMON comes here */
5363         /* EMAC1 COMMON comes here */
5364         /* DBU COMMON comes here */
5365         /* DBG COMMON comes here */
5366
5367         bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5368         if (CHIP_IS_E1H(bp)) {
5369                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5370                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5371         }
5372
5373         if (CHIP_REV_IS_SLOW(bp))
5374                 msleep(200);
5375
5376         /* finish CFC init */
5377         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5378         if (val != 1) {
5379                 BNX2X_ERR("CFC LL_INIT failed\n");
5380                 return -EBUSY;
5381         }
5382         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5383         if (val != 1) {
5384                 BNX2X_ERR("CFC AC_INIT failed\n");
5385                 return -EBUSY;
5386         }
5387         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5388         if (val != 1) {
5389                 BNX2X_ERR("CFC CAM_INIT failed\n");
5390                 return -EBUSY;
5391         }
5392         REG_WR(bp, CFC_REG_DEBUG0, 0);
5393
5394         /* read NIG statistic
5395            to see if this is our first up since powerup */
5396         bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5397         val = *bnx2x_sp(bp, wb_data[0]);
5398
5399         /* do internal memory self test */
5400         if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5401                 BNX2X_ERR("internal mem self test failed\n");
5402                 return -EBUSY;
5403         }
5404
5405         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5406         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5407         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5408                 /* Fan failure is indicated by SPIO 5 */
5409                 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5410                                MISC_REGISTERS_SPIO_INPUT_HI_Z);
5411
5412                 /* set to active low mode */
5413                 val = REG_RD(bp, MISC_REG_SPIO_INT);
5414                 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5415                                         MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5416                 REG_WR(bp, MISC_REG_SPIO_INT, val);
5417
5418                 /* enable interrupt to signal the IGU */
5419                 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5420                 val |= (1 << MISC_REGISTERS_SPIO_5);
5421                 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5422                 break;
5423
5424         default:
5425                 break;
5426         }
5427
5428         /* clear PXP2 attentions */
5429         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5430
5431         enable_blocks_attention(bp);
5432
5433         if (!BP_NOMCP(bp)) {
5434                 bnx2x_acquire_phy_lock(bp);
5435                 bnx2x_common_init_phy(bp, bp->common.shmem_base);
5436                 bnx2x_release_phy_lock(bp);
5437         } else
5438                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5439
5440         return 0;
5441 }
5442
5443 static int bnx2x_init_port(struct bnx2x *bp)
5444 {
5445         int port = BP_PORT(bp);
5446         u32 val;
5447
5448         DP(BNX2X_MSG_MCP, "starting port init  port %x\n", port);
5449
5450         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5451
5452         /* Port PXP comes here */
5453         /* Port PXP2 comes here */
5454 #ifdef BCM_ISCSI
5455         /* Port0  1
5456          * Port1  385 */
5457         i++;
5458         wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5459         wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5460         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5461         REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5462
5463         /* Port0  2
5464          * Port1  386 */
5465         i++;
5466         wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5467         wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5468         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5469         REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5470
5471         /* Port0  3
5472          * Port1  387 */
5473         i++;
5474         wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5475         wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5476         REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5477         REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5478 #endif
5479         /* Port CMs come here */
5480
5481         /* Port QM comes here */
5482 #ifdef BCM_ISCSI
5483         REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5484         REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5485
5486         bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5487                              func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5488 #endif
5489         /* Port DQ comes here */
5490         /* Port BRB1 comes here */
5491         /* Port PRS comes here */
5492         /* Port TSDM comes here */
5493         /* Port CSDM comes here */
5494         /* Port USDM comes here */
5495         /* Port XSDM comes here */
5496         bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5497                              port ? TSEM_PORT1_END : TSEM_PORT0_END);
5498         bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5499                              port ? USEM_PORT1_END : USEM_PORT0_END);
5500         bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5501                              port ? CSEM_PORT1_END : CSEM_PORT0_END);
5502         bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5503                              port ? XSEM_PORT1_END : XSEM_PORT0_END);
5504         /* Port UPB comes here */
5505         /* Port XPB comes here */
5506
5507         bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5508                              port ? PBF_PORT1_END : PBF_PORT0_END);
5509
5510         /* configure PBF to work without PAUSE mtu 9000 */
5511         REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5512
5513         /* update threshold */
5514         REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5515         /* update init credit */
5516         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5517
5518         /* probe changes */
5519         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5520         msleep(5);
5521         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5522
5523 #ifdef BCM_ISCSI
5524         /* tell the searcher where the T2 table is */
5525         REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5526
5527         wb_write[0] = U64_LO(bp->t2_mapping);
5528         wb_write[1] = U64_HI(bp->t2_mapping);
5529         REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5530         wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5531         wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5532         REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5533
5534         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5535         /* Port SRCH comes here */
5536 #endif
5537         /* Port CDU comes here */
5538         /* Port CFC comes here */
5539
5540         if (CHIP_IS_E1(bp)) {
5541                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5542                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5543         }
5544         bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
5545                              port ? HC_PORT1_END : HC_PORT0_END);
5546
5547         bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
5548                                     MISC_AEU_PORT0_START,
5549                              port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5550         /* init aeu_mask_attn_func_0/1:
5551          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5552          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5553          *             bits 4-7 are used for "per vn group attention" */
5554         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5555                (IS_E1HMF(bp) ? 0xF7 : 0x7));
5556
5557         /* Port PXPCS comes here */
5558         /* Port EMAC0 comes here */
5559         /* Port EMAC1 comes here */
5560         /* Port DBU comes here */
5561         /* Port DBG comes here */
5562         bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
5563                              port ? NIG_PORT1_END : NIG_PORT0_END);
5564
5565         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5566
5567         if (CHIP_IS_E1H(bp)) {
5568                 u32 wsum;
5569                 struct cmng_struct_per_port m_cmng_port;
5570                 int vn;
5571
5572                 /* 0x2 disable e1hov, 0x1 enable */
5573                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5574                        (IS_E1HMF(bp) ? 0x1 : 0x2));
5575
5576                 /* Init RATE SHAPING and FAIRNESS contexts.
5577                    Initialize as if there is 10G link. */
5578                 wsum = bnx2x_calc_vn_wsum(bp);
5579                 bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
5580                 if (IS_E1HMF(bp))
5581                         for (vn = VN_0; vn < E1HVN_MAX; vn++)
5582                                 bnx2x_init_vn_minmax(bp, 2*vn + port,
5583                                         wsum, 10000, &m_cmng_port);
5584         }
5585
5586         /* Port MCP comes here */
5587         /* Port DMAE comes here */
5588
5589         switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5590         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
5591         case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5592                 /* add SPIO 5 to group 0 */
5593                 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5594                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5595                 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
5596                 break;
5597
5598         default:
5599                 break;
5600         }
5601
5602         bnx2x__link_reset(bp);
5603
5604         return 0;
5605 }
5606
5607 #define ILT_PER_FUNC            (768/2)
5608 #define FUNC_ILT_BASE(func)     (func * ILT_PER_FUNC)
5609 /* the phys address is shifted right 12 bits and has an added
5610    1=valid bit added to the 53rd bit
5611    then since this is a wide register(TM)
5612    we split it into two 32 bit writes
5613  */
5614 #define ONCHIP_ADDR1(x)         ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5615 #define ONCHIP_ADDR2(x)         ((u32)((1 << 20) | ((u64)x >> 44)))
5616 #define PXP_ONE_ILT(x)          (((x) << 10) | x)
5617 #define PXP_ILT_RANGE(f, l)     (((l) << 10) | f)
5618
5619 #define CNIC_ILT_LINES          0
5620
5621 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5622 {
5623         int reg;
5624
5625         if (CHIP_IS_E1H(bp))
5626                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5627         else /* E1 */
5628                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5629
5630         bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5631 }
5632
5633 static int bnx2x_init_func(struct bnx2x *bp)
5634 {
5635         int port = BP_PORT(bp);
5636         int func = BP_FUNC(bp);
5637         int i;
5638
5639         DP(BNX2X_MSG_MCP, "starting func init  func %x\n", func);
5640
5641         i = FUNC_ILT_BASE(func);
5642
5643         bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
5644         if (CHIP_IS_E1H(bp)) {
5645                 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
5646                 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
5647         } else /* E1 */
5648                 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
5649                        PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
5650
5651
5652         if (CHIP_IS_E1H(bp)) {
5653                 for (i = 0; i < 9; i++)
5654                         bnx2x_init_block(bp,
5655                                          cm_start[func][i], cm_end[func][i]);
5656
5657                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5658                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
5659         }
5660
5661         /* HC init per function */
5662         if (CHIP_IS_E1H(bp)) {
5663                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5664
5665                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5666                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5667         }
5668         bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
5669
5670         if (CHIP_IS_E1H(bp))
5671                 REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);
5672
5673         /* Reset PCIE errors for debug */
5674         REG_WR(bp, 0x2114, 0xffffffff);
5675         REG_WR(bp, 0x2120, 0xffffffff);
5676
5677         return 0;
5678 }
5679
5680 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5681 {
5682         int i, rc = 0;
5683
5684         DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
5685            BP_FUNC(bp), load_code);
5686
5687         bp->dmae_ready = 0;
5688         mutex_init(&bp->dmae_mutex);
5689         bnx2x_gunzip_init(bp);
5690
5691         switch (load_code) {
5692         case FW_MSG_CODE_DRV_LOAD_COMMON:
5693                 rc = bnx2x_init_common(bp);
5694                 if (rc)
5695                         goto init_hw_err;
5696                 /* no break */
5697
5698         case FW_MSG_CODE_DRV_LOAD_PORT:
5699                 bp->dmae_ready = 1;
5700                 rc = bnx2x_init_port(bp);
5701                 if (rc)
5702                         goto init_hw_err;
5703                 /* no break */
5704
5705         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5706                 bp->dmae_ready = 1;
5707                 rc = bnx2x_init_func(bp);
5708                 if (rc)
5709                         goto init_hw_err;
5710                 break;
5711
5712         default:
5713                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5714                 break;
5715         }
5716
5717         if (!BP_NOMCP(bp)) {
5718                 int func = BP_FUNC(bp);
5719
5720                 bp->fw_drv_pulse_wr_seq =
5721                                 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
5722                                  DRV_PULSE_SEQ_MASK);
5723                 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
5724                 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x  func_stx 0x%x\n",
5725                    bp->fw_drv_pulse_wr_seq, bp->func_stx);
5726         } else
5727                 bp->func_stx = 0;
5728
5729         /* this needs to be done before gunzip end */
5730         bnx2x_zero_def_sb(bp);
5731         for_each_queue(bp, i)
5732                 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
5733
5734 init_hw_err:
5735         bnx2x_gunzip_end(bp);
5736
5737         return rc;
5738 }
5739
5740 /* send the MCP a request, block until there is a reply */
5741 static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5742 {
5743         int func = BP_FUNC(bp);
5744         u32 seq = ++bp->fw_seq;
5745         u32 rc = 0;
5746         u32 cnt = 1;
5747         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5748
5749         SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5750         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5751
5752         do {
5753                 /* let the FW do it's magic ... */
5754                 msleep(delay);
5755
5756                 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5757
5758                 /* Give the FW up to 2 second (200*10ms) */
5759         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
5760
5761         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5762            cnt*delay, rc, seq);
5763
5764         /* is this a reply to our command? */
5765         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
5766                 rc &= FW_MSG_CODE_MASK;
5767
5768         } else {
5769                 /* FW BUG! */
5770                 BNX2X_ERR("FW failed to respond!\n");
5771                 bnx2x_fw_dump(bp);
5772                 rc = 0;
5773         }
5774
5775         return rc;
5776 }
5777
5778 static void bnx2x_free_mem(struct bnx2x *bp)
5779 {
5780
5781 #define BNX2X_PCI_FREE(x, y, size) \
5782         do { \
5783                 if (x) { \
5784                         pci_free_consistent(bp->pdev, size, x, y); \
5785                         x = NULL; \
5786                         y = 0; \
5787                 } \
5788      &